From 0c94434db7f35045f0f2ec2bda9a88d092a56ec0 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Sat, 26 Jan 2019 07:59:40 -0800
Subject: [PATCH] Add DSP back to tilegrid.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fuzzers/005-tilegrid/Makefile         |  5 +++
 fuzzers/005-tilegrid/add_tdb.py       |  1 +
 fuzzers/005-tilegrid/dsp/Makefile     |  4 ++
 fuzzers/005-tilegrid/dsp/generate.tcl | 19 ++++++++++
 fuzzers/005-tilegrid/dsp/top.py       | 53 +++++++++++++++++++++++++++
 5 files changed, 82 insertions(+)
 create mode 100644 fuzzers/005-tilegrid/dsp/Makefile
 create mode 100644 fuzzers/005-tilegrid/dsp/generate.tcl
 create mode 100644 fuzzers/005-tilegrid/dsp/top.py

diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile
index f99d969a..59575a36 100644
--- a/fuzzers/005-tilegrid/Makefile
+++ b/fuzzers/005-tilegrid/Makefile
@@ -11,6 +11,7 @@ TILEGRID_TDB_DEPENDENCIES += bram_block/build/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += bram_int/build/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += clb/build/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += clb_int/build/segbits_tilegrid.tdb
+TILEGRID_TDB_DEPENDENCIES += dsp/build/segbits_tilegrid.tdb
 GENERATE_FULL_ARGS=
 
 ifeq (${XRAY_DATABASE}, zynq7)
@@ -65,6 +66,9 @@ bram_block/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 bram_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 	cd bram_int && $(MAKE)
 
+dsp/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
+	cd dsp && $(MAKE)
+
 build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
 	python3 add_tdb.py \
 		--fn-in build/basicdb/tilegrid.json \
@@ -92,6 +96,7 @@ clean:
 	cd bram && $(MAKE) clean
 	cd bram_block && $(MAKE) clean
 	cd bram_int && $(MAKE) clean
+	cd dsp && $(MAKE) clean
 	cd monitor && $(MAKE) clean
 
 .PHONY: database pushdb clean run
diff --git a/fuzzers/005-tilegrid/add_tdb.py b/fuzzers/005-tilegrid/add_tdb.py
index 5004de93..a16f7a63 100644
--- a/fuzzers/005-tilegrid/add_tdb.py
+++ b/fuzzers/005-tilegrid/add_tdb.py
@@ -63,6 +63,7 @@ def run(fn_in, fn_out, verbose=False):
         ("bram/build/segbits_tilegrid.tdb", 28, 10),
         ("bram_block/build/segbits_tilegrid.tdb", 128, 10),
         ("clb/build/segbits_tilegrid.tdb", 36, 2),
+        ("dsp/build/segbits_tilegrid.tdb", 28, 2),
         ("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),
diff --git a/fuzzers/005-tilegrid/dsp/Makefile b/fuzzers/005-tilegrid/dsp/Makefile
new file mode 100644
index 00000000..c21ff864
--- /dev/null
+++ b/fuzzers/005-tilegrid/dsp/Makefile
@@ -0,0 +1,4 @@
+N ?= 30
+GENERATE_ARGS?="--oneval 1 --design params.csv --dword 0 --dframe 1B"
+include ../fuzzaddr/common.mk
+
diff --git a/fuzzers/005-tilegrid/dsp/generate.tcl b/fuzzers/005-tilegrid/dsp/generate.tcl
new file mode 100644
index 00000000..9e8cab8a
--- /dev/null
+++ b/fuzzers/005-tilegrid/dsp/generate.tcl
@@ -0,0 +1,19 @@
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run
diff --git a/fuzzers/005-tilegrid/dsp/top.py b/fuzzers/005-tilegrid/dsp/top.py
new file mode 100644
index 00000000..cbd75a79
--- /dev/null
+++ b/fuzzers/005-tilegrid/dsp/top.py
@@ -0,0 +1,53 @@
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+
+
+def gen_sites():
+    db = Database(util.get_db_root())
+    grid = db.grid()
+    for tile_name in grid.tiles():
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+        if gridinfo.tile_type in ['DSP_L', 'DSP_R']:
+            site_name = sorted(gridinfo.sites.keys())[0]
+            yield tile_name, site_name
+
+
+def write_params(params):
+    pinstr = 'tile,val,site\n'
+    for tile, (site, val) in sorted(params.items()):
+        pinstr += '%s,%s,%s\n' % (tile, val, site)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print(
+        '''
+module top();
+    ''')
+
+    params = {}
+
+    sites = list(gen_sites())
+    for (tile_name, site_name), isone in zip(sites,
+                                             util.gen_fuzz_states(len(sites))):
+        params[tile_name] = (site_name, isone)
+
+        print(
+            '''
+            (* KEEP, DONT_TOUCH, LOC = "{0}" *)
+            DSP48E1 #(
+                .MASK({1})
+            ) dsp_{0} (
+            );
+'''.format(site_name, isone))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()