From 0c0068697ae35326fb898be330cc385d1d927e73 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Thu, 4 Apr 2019 10:17:28 -0700
Subject: [PATCH] docs: Fix header levels for format section.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
---
 docs/format/db.rst   | 17 ++++++++++-------
 docs/format/tile.rst | 24 ++++++++++++------------
 2 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/docs/format/db.rst b/docs/format/db.rst
index 6c5885f4..fd6a7e71 100644
--- a/docs/format/db.rst
+++ b/docs/format/db.rst
@@ -1,17 +1,20 @@
+.db Files
+=========
+
 Introduction
-================
+------------
 
 This section documents how prjxray represents the bitstream database
 
 These ".db" files come in two common flavors:
- * segbits_*.db: encodes bitstream bits
- * mask_*.db: which bits are used by a segment? Probably needs to be converted to tile
+ * `segbits_*.db`_: encodes bitstream bits
+ * `mask_*.db`_: which bits are used by a segment? Probably needs to be converted to tile
 
 Also note: .rdb (raw db) is a convention for a non-expanded .db file (see below)
 
 
-segbits
-================
+segbits_*.db
+------------
 
 These are created by segmatch to describe bitstream IP encoding.
 
@@ -55,8 +58,8 @@ Related tools:
    * Ex: CLB is solved by first solving LUT bits, and then solving FF bits
 
 
-mask
-================
+mask_*.db
+---------
 
 These are just simple bit lists
 
diff --git a/docs/format/tile.rst b/docs/format/tile.rst
index 767b2cfe..ff80a0cd 100644
--- a/docs/format/tile.rst
+++ b/docs/format/tile.rst
@@ -1,5 +1,8 @@
+.json Files
+===========
+
 Introduction
-================
+------------
 
 This section documents how prjxray represents FPGA fabric. Its primarily composed of two files:
  * tilegrid.json: list of tiles and how they appear in the bitstream
@@ -11,23 +14,23 @@ General notes:
 
 
 tilegrid.json
-================
+-------------
 
 This section assumes you are already familiar with the 7 series bitstream format.
 
 This file contains two elements:
  * segments: each entry lists sections of the bitstream that encode part of one or more tiles
- * tiles: corres
+ * tiles: cores
 
-segments  
-################
+segments
+########
 
 Segments are a prjxray concept.
 
 Each entry has the following fields:
  * baseaddr: a tuple of (base address, inter-frame offset)
  * frames: how many frames are required to make a complete segment
- * words: number of inter-frame words requird for a complete segment
+ * words: number of inter-frame words required for a complete segment
  * tiles: which tiles reference this segment
  * type: prjxray given segment type
 
@@ -56,7 +59,7 @@ Interpreted as:
   * Since its 2 FDRI words out of possible 101, its the last 2 words
   * It spans across 36 different frame loads
   * The data in this segment is used by two different tiles: CLBLL_L_X16Y149, INT_L_X16Y149
-  
+
 Historical note:
 In the original encoding, a segment was a collection of tiles that were encoded together.
 For example, a CLB is encoded along with a nearby switch.
@@ -65,7 +68,7 @@ the configuration and data are stored in seperate parts of the bitstream.
 The BRAM itself also spans multiple tiles and has multiple switchboxes.
 
 tiles
-################
+#####
 
 Each entry has the following fields:
  * grid_x: tile column, increasing right
@@ -74,8 +77,6 @@ Each entry has the following fields:
  * sites: dictionary of sites name: site type contained within tile
  * type: Vivado given tile type
 
-
-
 Sample entry:
 
 .. code-block:: json
@@ -97,9 +98,8 @@ Interpreted as:
  * Contains two sites, both of which are SLICEL
  * A CLBLL_L type tile
 
-
 tileconn.json
-================
+-------------
 
 This file documents how adjacent tile pairs are connected.
 No directionality is given.