From 0a79eb67531b964a3e6a231b4ceb511b891979a8 Mon Sep 17 00:00:00 2001 From: Jake Mercer Date: Sat, 2 Nov 2019 11:45:43 +0000 Subject: [PATCH] FORMAT - Whitespace Fixes CI is failing due to this. Signed-off-by: Jake Mercer --- minitests/litex_litedram/src.vivado/verilog/VexRiscv.v | 8 ++++---- minitests/litex_litedram/src.yosys/verilog/VexRiscv.v | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/minitests/litex_litedram/src.vivado/verilog/VexRiscv.v b/minitests/litex_litedram/src.vivado/verilog/VexRiscv.v index c1891ed2..10fc8f52 100644 --- a/minitests/litex_litedram/src.vivado/verilog/VexRiscv.v +++ b/minitests/litex_litedram/src.vivado/verilog/VexRiscv.v @@ -2523,7 +2523,7 @@ module VexRiscv ( end end - InstructionCache IBusCachedPlugin_cache ( + InstructionCache IBusCachedPlugin_cache ( .io_flush(_zz_221_), .io_cpu_prefetch_isValid(_zz_222_), .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), @@ -2569,9 +2569,9 @@ module VexRiscv ( .io_mem_rsp_payload_data(iBus_rsp_payload_data), .io_mem_rsp_payload_error(iBus_rsp_payload_error), .clk(clk), - .reset(reset) + .reset(reset) ); - DataCache dataCache_1_ ( + DataCache dataCache_1_ ( .io_cpu_execute_isValid(_zz_230_), .io_cpu_execute_address(_zz_231_), .io_cpu_execute_args_wr(execute_MEMORY_WR), @@ -2619,7 +2619,7 @@ module VexRiscv ( .io_mem_rsp_payload_data(dBus_rsp_payload_data), .io_mem_rsp_payload_error(dBus_rsp_payload_error), .clk(clk), - .reset(reset) + .reset(reset) ); always @(*) begin case(_zz_371_) diff --git a/minitests/litex_litedram/src.yosys/verilog/VexRiscv.v b/minitests/litex_litedram/src.yosys/verilog/VexRiscv.v index c1891ed2..10fc8f52 100644 --- a/minitests/litex_litedram/src.yosys/verilog/VexRiscv.v +++ b/minitests/litex_litedram/src.yosys/verilog/VexRiscv.v @@ -2523,7 +2523,7 @@ module VexRiscv ( end end - InstructionCache IBusCachedPlugin_cache ( + InstructionCache IBusCachedPlugin_cache ( .io_flush(_zz_221_), .io_cpu_prefetch_isValid(_zz_222_), .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), @@ -2569,9 +2569,9 @@ module VexRiscv ( .io_mem_rsp_payload_data(iBus_rsp_payload_data), .io_mem_rsp_payload_error(iBus_rsp_payload_error), .clk(clk), - .reset(reset) + .reset(reset) ); - DataCache dataCache_1_ ( + DataCache dataCache_1_ ( .io_cpu_execute_isValid(_zz_230_), .io_cpu_execute_address(_zz_231_), .io_cpu_execute_args_wr(execute_MEMORY_WR), @@ -2619,7 +2619,7 @@ module VexRiscv ( .io_mem_rsp_payload_data(dBus_rsp_payload_data), .io_mem_rsp_payload_error(dBus_rsp_payload_error), .clk(clk), - .reset(reset) + .reset(reset) ); always @(*) begin case(_zz_371_)