From 1d140ac3b16bbc1c17934f2dc5014dc380d7ce95 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 21 Mar 2019 14:24:04 -0700 Subject: [PATCH 1/3] Add another IOI variant. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fuzzers/071-ppips/generate.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fuzzers/071-ppips/generate.tcl b/fuzzers/071-ppips/generate.tcl index 581db62d..a0c19193 100644 --- a/fuzzers/071-ppips/generate.tcl +++ b/fuzzers/071-ppips/generate.tcl @@ -91,7 +91,7 @@ foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} { } } -foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R IO_INT_INTERFACE_R IO_INT_INTERFACE_L RIOI3 LIOI3 LIOI3_TBYTESRC RIOI3_TBYTESRC LIOI3_SING RIOI3_SING} { +foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R IO_INT_INTERFACE_R IO_INT_INTERFACE_L RIOI3 LIOI3 LIOI3_TBYTETERM RIOI3_TBYTETERM LIOI3_TBYTESRC RIOI3_TBYTESRC LIOI3_SING RIOI3_SING} { set tiles [get_tiles -filter "TILE_TYPE == $tile_type"] if {[llength $tiles] != 0} { set tile [lindex $tiles 0] From 34559709bb7f718ac93fbee3c156b6707d3b1b8d Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 22 Mar 2019 08:15:45 -0700 Subject: [PATCH 2/3] Add BRKH_INT, fix grammer, and add some line breaks. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fuzzers/071-ppips/generate.tcl | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/fuzzers/071-ppips/generate.tcl b/fuzzers/071-ppips/generate.tcl index a0c19193..8c129315 100644 --- a/fuzzers/071-ppips/generate.tcl +++ b/fuzzers/071-ppips/generate.tcl @@ -73,7 +73,7 @@ proc write_bram_ppips_db {filename tile} { } elseif [string match "*LOGIC_OUTS*" $dst_wire] { # LOGIC_OUTS pips appear to be always, even thought multiple inputs to # the pip junction. Best guess is that the underlying hardware is - # actually just one wire, and there is no actually junction. + # actually just one wire, and there is no actual junction. foreach src_wire [get_wires -uphill -of_objects $pip] { puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always" } @@ -91,7 +91,11 @@ foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} { } } -foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R IO_INT_INTERFACE_R IO_INT_INTERFACE_L RIOI3 LIOI3 LIOI3_TBYTETERM RIOI3_TBYTETERM LIOI3_TBYTESRC RIOI3_TBYTESRC LIOI3_SING RIOI3_SING} { +foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R \ + CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R \ + IO_INT_INTERFACE_R IO_INT_INTERFACE_L RIOI3 LIOI3 LIOI3_TBYTETERM \ + RIOI3_TBYTETERM LIOI3_TBYTESRC RIOI3_TBYTESRC LIOI3_SING RIOI3_SING \ + BRKH_INT} { set tiles [get_tiles -filter "TILE_TYPE == $tile_type"] if {[llength $tiles] != 0} { set tile [lindex $tiles 0] From e1fde3203d353c1561b3af340799bf27c574c454 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 22 Mar 2019 08:35:53 -0700 Subject: [PATCH 3/3] Run make format. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fuzzers/071-ppips/generate.tcl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/fuzzers/071-ppips/generate.tcl b/fuzzers/071-ppips/generate.tcl index 8c129315..b7228769 100644 --- a/fuzzers/071-ppips/generate.tcl +++ b/fuzzers/071-ppips/generate.tcl @@ -92,10 +92,10 @@ foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} { } foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R \ - CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R \ - IO_INT_INTERFACE_R IO_INT_INTERFACE_L RIOI3 LIOI3 LIOI3_TBYTETERM \ - RIOI3_TBYTETERM LIOI3_TBYTESRC RIOI3_TBYTESRC LIOI3_SING RIOI3_SING \ - BRKH_INT} { + CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R \ + IO_INT_INTERFACE_R IO_INT_INTERFACE_L RIOI3 LIOI3 LIOI3_TBYTETERM \ + RIOI3_TBYTETERM LIOI3_TBYTESRC RIOI3_TBYTESRC LIOI3_SING RIOI3_SING \ + BRKH_INT} { set tiles [get_tiles -filter "TILE_TYPE == $tile_type"] if {[llength $tiles] != 0} { set tile [lindex $tiles 0]