diff --git a/minitests/carry_cin_cyinit/README b/minitests/carry_cin_cyinit/README
new file mode 100644
index 00000000..a5c7094b
--- /dev/null
+++ b/minitests/carry_cin_cyinit/README
@@ -0,0 +1,5 @@
+
+This will create an "impossible" CYINIT/CI config for CARRY4. We have no idea
+atm what that does in hardware. Vivado outputs a warning but still generates a
+bit-stream. (see comment in top.v)
+
diff --git a/minitests/clbconfigs/README b/minitests/clbconfigs/README
new file mode 100644
index 00000000..dc2fac24
--- /dev/null
+++ b/minitests/clbconfigs/README
@@ -0,0 +1,6 @@
+
+Some small examples on manually placing elements within a CLB.
+
+Probably only works for with the Artix 7 settings because contains
+hardcoded slice addresses.
+
diff --git a/minitests/clbconfigs/runme.tcl b/minitests/clbconfigs/runme.tcl
index f422d6ea..bd9b9f98 100644
--- a/minitests/clbconfigs/runme.tcl
+++ b/minitests/clbconfigs/runme.tcl
@@ -1,6 +1,6 @@
-# close_project
-# create_project -force -part $::env(XRAY_PART) design design
-# read_verilog top.v
+create_project -force -part $::env(XRAY_PART) design design
+read_verilog top.v
+
 synth_design -top top
 
 set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
diff --git a/minitests/lvb_long_mux/README b/minitests/lvb_long_mux/README
new file mode 100644
index 00000000..d41d0ac1
--- /dev/null
+++ b/minitests/lvb_long_mux/README
@@ -0,0 +1,30 @@
+
+A small example for the bidirectional buffers that connect long lines. The configuration
+bit (00_45 for LVB_L12<-->LVB_L12) confiures the direction of the buffer.
+
+Probably only works for with the Artix 7 settings because contains
+hardcoded slice addresses.
+
+Expected output is something like this:
+
+
+	$ python3 ../../utils/segprint.py design_a.bits INT_L_X12Y132 INT_L_X14Y132 INT_L_X16Y132
+
+	seg SEG_CLBLL_L_X12Y132
+	bit 00_45
+
+	seg SEG_CLBLL_L_X14Y132
+
+	seg SEG_CLBLL_L_X16Y132
+	bit 00_45
+
+
+	$ python3 ../../utils/segprint.py design_b.bits INT_L_X12Y132 INT_L_X14Y132 INT_L_X16Y132
+
+	seg SEG_CLBLL_L_X12Y132
+
+	seg SEG_CLBLL_L_X14Y132
+	bit 00_45
+
+	seg SEG_CLBLL_L_X16Y132
+
diff --git a/minitests/nodes_wires_list/README b/minitests/nodes_wires_list/README
new file mode 100644
index 00000000..d6bd9230
--- /dev/null
+++ b/minitests/nodes_wires_list/README
@@ -0,0 +1,4 @@
+
+This generates a list of all routing nodes and the wires that make up that
+node. Routing nodes that only contain one wire are not included in the list.
+
diff --git a/minitests/switchboxes/README b/minitests/switchboxes/README
new file mode 100644
index 00000000..d6479ed8
--- /dev/null
+++ b/minitests/switchboxes/README
@@ -0,0 +1,10 @@
+
+Some small tests with PIPs. Lists all the PIPs in a regular CLB and INT tile.
+
+None of the PIPs in the CLB are "real". Some are 1:1 connections that are
+"always on" and the others are simply implemented by permuting the LUT init
+values.
+
+Probably only works for with the Artix 7 settings because contains
+hardcoded slice addresses.
+