# Minitest for OSERDES

## Description

This test allows to verify that OSERDES is working on hardware. Tested modes are:

- SDR 2:1
- SDR 3:1
- SDR 4:1
- SDR 5:1
- SDR 6:1
- SDR 7:1
- SDR 8:1
- DDR 4:1
- DDR 6:1
- DDR 8:1

No chaining of two OSERDES bels.

A pseudo random sequence of words is generated by a LFSR. The sequence is then serialized by the OSERDES and the output bitstream goes to the output pin. The pin is using 3-state buffer which is constantly on. This allows to read serialized data from the same pin without the need of hardware pin loopback connection.

Simultaneously to the OSERDES operation, the word sequence is serialized internally by the FPGA logic. Both bitstreams are then compared and an error indication signal is generated. In order to mitigate for the OSERDES latency, the reference bitstream is delayed by a number of clock cycles which is adaptively changed.

LEDs indicate whether data is being received corectly. When a LED is lit then
there is correct reception:

- LED0  - SDR 2:1
- LED1  - SDR 3:1
- LED2  - SDR 4:1
- LED3  - SDR 5:1
- LED4  - SDR 6:1
- LED5  - SDR 7:1
- LED6  - SDR 8:1
- LED7  - DDR 4:1
- LED8  - DDR 6:1
- LED9  - DDR 8:1
- LED10 - Blinking continuously

The switch SW0 is used as reset.

## Building

To build the project run the following command and the bit file will be generated.
```
make basys3_oserdes_rates.bit
```
