From c042adc57143f0ae41c202f4d9d985761efa6ea4 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Sat, 8 Mar 2025 07:23:21 +0700 Subject: [PATCH] xc7K160t: add GTX base addresses to tilegrid (still missing for other kintex parts) --- kintex7/xc7k160t/tilegrid.json | 999 +++++++++++++++++++--- kintex7/xc7k160tffg676-2/package_pins.csv | 858 +++++++++---------- 2 files changed, 1310 insertions(+), 547 deletions(-) diff --git a/kintex7/xc7k160t/tilegrid.json b/kintex7/xc7k160t/tilegrid.json index 366188c..3f8e71f 100644 --- a/kintex7/xc7k160t/tilegrid.json +++ b/kintex7/xc7k160t/tilegrid.json @@ -291902,7 +291902,14 @@ "type": "DSP_R" }, "GTX_CHANNEL_0_X172Y162": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y3", "grid_x": 172, "grid_y": 98, @@ -291923,7 +291930,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_0_X172Y214": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 32, + "offset": 0, + "words": 22 + } + }, "clock_region": "X1Y4", "grid_x": 172, "grid_y": 46, @@ -291944,7 +291958,14 @@ "type": "GTX_CHANNEL_0" }, "GTX_CHANNEL_1_X172Y173": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y3", "grid_x": 172, "grid_y": 87, @@ -291965,7 +291986,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_1_X172Y225": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 32, + "offset": 22, + "words": 22 + } + }, "clock_region": "X1Y4", "grid_x": 172, "grid_y": 35, @@ -291986,7 +292014,14 @@ "type": "GTX_CHANNEL_1" }, "GTX_CHANNEL_2_X172Y191": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y3", "grid_x": 172, "grid_y": 69, @@ -292007,7 +292042,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_2_X172Y243": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 32, + "offset": 57, + "words": 22 + } + }, "clock_region": "X1Y4", "grid_x": 172, "grid_y": 17, @@ -292028,7 +292070,14 @@ "type": "GTX_CHANNEL_2" }, "GTX_CHANNEL_3_X172Y202": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y3", "grid_x": 172, "grid_y": 58, @@ -292049,7 +292098,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_CHANNEL_3_X172Y254": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 32, + "offset": 79, + "words": 22 + } + }, "clock_region": "X1Y4", "grid_x": 172, "grid_y": 6, @@ -292070,7 +292126,14 @@ "type": "GTX_CHANNEL_3" }, "GTX_COMMON_X172Y179": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y3", "grid_x": 172, "grid_y": 81, @@ -292093,7 +292156,14 @@ "type": "GTX_COMMON" }, "GTX_COMMON_X172Y231": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 32, + "offset": 0, + "words": 101 + } + }, "clock_region": "X1Y4", "grid_x": 172, "grid_y": 29, @@ -292116,7 +292186,14 @@ "type": "GTX_COMMON" }, "GTX_INT_INTERFACE_X67Y150": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 169, "grid_y": 103, "pin_functions": {}, @@ -292125,7 +292202,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y151": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 169, "grid_y": 102, "pin_functions": {}, @@ -292134,7 +292218,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y152": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 169, "grid_y": 101, "pin_functions": {}, @@ -292143,7 +292234,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y153": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 169, "grid_y": 100, "pin_functions": {}, @@ -292152,7 +292250,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y154": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 169, "grid_y": 99, "pin_functions": {}, @@ -292161,7 +292266,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y155": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 169, "grid_y": 98, "pin_functions": {}, @@ -292170,7 +292282,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y156": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 169, "grid_y": 97, "pin_functions": {}, @@ -292179,7 +292298,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y157": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 169, "grid_y": 96, "pin_functions": {}, @@ -292188,7 +292314,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y158": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 169, "grid_y": 95, "pin_functions": {}, @@ -292197,7 +292330,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y159": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 169, "grid_y": 94, "pin_functions": {}, @@ -292206,7 +292346,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y160": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 169, "grid_y": 93, "pin_functions": {}, @@ -292215,7 +292362,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y161": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 169, "grid_y": 92, "pin_functions": {}, @@ -292224,7 +292378,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y162": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 169, "grid_y": 91, "pin_functions": {}, @@ -292233,7 +292394,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y163": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 169, "grid_y": 90, "pin_functions": {}, @@ -292242,7 +292410,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y164": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 169, "grid_y": 89, "pin_functions": {}, @@ -292251,7 +292426,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y165": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 169, "grid_y": 88, "pin_functions": {}, @@ -292260,7 +292442,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y166": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 169, "grid_y": 87, "pin_functions": {}, @@ -292269,7 +292458,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y167": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 169, "grid_y": 86, "pin_functions": {}, @@ -292278,7 +292474,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y168": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 169, "grid_y": 85, "pin_functions": {}, @@ -292287,7 +292490,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y169": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 169, "grid_y": 84, "pin_functions": {}, @@ -292296,7 +292506,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y170": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 169, "grid_y": 83, "pin_functions": {}, @@ -292305,7 +292522,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y171": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 169, "grid_y": 82, "pin_functions": {}, @@ -292314,7 +292538,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y172": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 169, "grid_y": 81, "pin_functions": {}, @@ -292323,7 +292554,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y173": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 169, "grid_y": 80, "pin_functions": {}, @@ -292332,7 +292570,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y174": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 169, "grid_y": 79, "pin_functions": {}, @@ -292341,7 +292586,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y175": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 169, "grid_y": 77, "pin_functions": {}, @@ -292350,7 +292602,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y176": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 169, "grid_y": 76, "pin_functions": {}, @@ -292359,7 +292618,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y177": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 169, "grid_y": 75, "pin_functions": {}, @@ -292368,7 +292634,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y178": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 169, "grid_y": 74, "pin_functions": {}, @@ -292377,7 +292650,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y179": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 169, "grid_y": 73, "pin_functions": {}, @@ -292386,7 +292666,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y180": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 169, "grid_y": 72, "pin_functions": {}, @@ -292395,7 +292682,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y181": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 169, "grid_y": 71, "pin_functions": {}, @@ -292404,7 +292698,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y182": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 169, "grid_y": 70, "pin_functions": {}, @@ -292413,7 +292714,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y183": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 169, "grid_y": 69, "pin_functions": {}, @@ -292422,7 +292730,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y184": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 169, "grid_y": 68, "pin_functions": {}, @@ -292431,7 +292746,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y185": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 169, "grid_y": 67, "pin_functions": {}, @@ -292440,7 +292762,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y186": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 169, "grid_y": 66, "pin_functions": {}, @@ -292449,7 +292778,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y187": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 169, "grid_y": 65, "pin_functions": {}, @@ -292458,7 +292794,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y188": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 169, "grid_y": 64, "pin_functions": {}, @@ -292467,7 +292810,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y189": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 169, "grid_y": 63, "pin_functions": {}, @@ -292476,7 +292826,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y190": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 169, "grid_y": 62, "pin_functions": {}, @@ -292485,7 +292842,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y191": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 169, "grid_y": 61, "pin_functions": {}, @@ -292494,7 +292858,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y192": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 169, "grid_y": 60, "pin_functions": {}, @@ -292503,7 +292874,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y193": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 169, "grid_y": 59, "pin_functions": {}, @@ -292512,7 +292890,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y194": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 169, "grid_y": 58, "pin_functions": {}, @@ -292521,7 +292906,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y195": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 169, "grid_y": 57, "pin_functions": {}, @@ -292530,7 +292922,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y196": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 169, "grid_y": 56, "pin_functions": {}, @@ -292539,7 +292938,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y197": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 169, "grid_y": 55, "pin_functions": {}, @@ -292548,7 +292954,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y198": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 169, "grid_y": 54, "pin_functions": {}, @@ -292557,7 +292970,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y199": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00002180", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 169, "grid_y": 53, "pin_functions": {}, @@ -292566,7 +292986,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y200": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": -2, + "words": 2 + } + }, "grid_x": 169, "grid_y": 51, "pin_functions": {}, @@ -292575,7 +293002,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y201": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 0, + "words": 2 + } + }, "grid_x": 169, "grid_y": 50, "pin_functions": {}, @@ -292584,7 +293018,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y202": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 2, + "words": 2 + } + }, "grid_x": 169, "grid_y": 49, "pin_functions": {}, @@ -292593,7 +293034,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y203": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 4, + "words": 2 + } + }, "grid_x": 169, "grid_y": 48, "pin_functions": {}, @@ -292602,7 +293050,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y204": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 6, + "words": 2 + } + }, "grid_x": 169, "grid_y": 47, "pin_functions": {}, @@ -292611,7 +293066,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y205": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 8, + "words": 2 + } + }, "grid_x": 169, "grid_y": 46, "pin_functions": {}, @@ -292620,7 +293082,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y206": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 10, + "words": 2 + } + }, "grid_x": 169, "grid_y": 45, "pin_functions": {}, @@ -292629,7 +293098,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y207": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 12, + "words": 2 + } + }, "grid_x": 169, "grid_y": 44, "pin_functions": {}, @@ -292638,7 +293114,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y208": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 14, + "words": 2 + } + }, "grid_x": 169, "grid_y": 43, "pin_functions": {}, @@ -292647,7 +293130,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y209": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 16, + "words": 2 + } + }, "grid_x": 169, "grid_y": 42, "pin_functions": {}, @@ -292656,7 +293146,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y210": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 18, + "words": 2 + } + }, "grid_x": 169, "grid_y": 41, "pin_functions": {}, @@ -292665,7 +293162,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y211": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 20, + "words": 2 + } + }, "grid_x": 169, "grid_y": 40, "pin_functions": {}, @@ -292674,7 +293178,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y212": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 22, + "words": 2 + } + }, "grid_x": 169, "grid_y": 39, "pin_functions": {}, @@ -292683,7 +293194,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y213": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 24, + "words": 2 + } + }, "grid_x": 169, "grid_y": 38, "pin_functions": {}, @@ -292692,7 +293210,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y214": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 26, + "words": 2 + } + }, "grid_x": 169, "grid_y": 37, "pin_functions": {}, @@ -292701,7 +293226,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y215": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 28, + "words": 2 + } + }, "grid_x": 169, "grid_y": 36, "pin_functions": {}, @@ -292710,7 +293242,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y216": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 30, + "words": 2 + } + }, "grid_x": 169, "grid_y": 35, "pin_functions": {}, @@ -292719,7 +293258,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y217": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 32, + "words": 2 + } + }, "grid_x": 169, "grid_y": 34, "pin_functions": {}, @@ -292728,7 +293274,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y218": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 34, + "words": 2 + } + }, "grid_x": 169, "grid_y": 33, "pin_functions": {}, @@ -292737,7 +293290,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y219": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 36, + "words": 2 + } + }, "grid_x": 169, "grid_y": 32, "pin_functions": {}, @@ -292746,7 +293306,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y220": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 38, + "words": 2 + } + }, "grid_x": 169, "grid_y": 31, "pin_functions": {}, @@ -292755,7 +293322,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y221": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 40, + "words": 2 + } + }, "grid_x": 169, "grid_y": 30, "pin_functions": {}, @@ -292764,7 +293338,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y222": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 42, + "words": 2 + } + }, "grid_x": 169, "grid_y": 29, "pin_functions": {}, @@ -292773,7 +293354,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y223": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 44, + "words": 2 + } + }, "grid_x": 169, "grid_y": 28, "pin_functions": {}, @@ -292782,7 +293370,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y224": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 46, + "words": 2 + } + }, "grid_x": 169, "grid_y": 27, "pin_functions": {}, @@ -292791,7 +293386,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y225": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 49, + "words": 2 + } + }, "grid_x": 169, "grid_y": 25, "pin_functions": {}, @@ -292800,7 +293402,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y226": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 51, + "words": 2 + } + }, "grid_x": 169, "grid_y": 24, "pin_functions": {}, @@ -292809,7 +293418,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y227": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 53, + "words": 2 + } + }, "grid_x": 169, "grid_y": 23, "pin_functions": {}, @@ -292818,7 +293434,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y228": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 55, + "words": 2 + } + }, "grid_x": 169, "grid_y": 22, "pin_functions": {}, @@ -292827,7 +293450,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y229": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 57, + "words": 2 + } + }, "grid_x": 169, "grid_y": 21, "pin_functions": {}, @@ -292836,7 +293466,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y230": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 59, + "words": 2 + } + }, "grid_x": 169, "grid_y": 20, "pin_functions": {}, @@ -292845,7 +293482,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y231": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 61, + "words": 2 + } + }, "grid_x": 169, "grid_y": 19, "pin_functions": {}, @@ -292854,7 +293498,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y232": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 63, + "words": 2 + } + }, "grid_x": 169, "grid_y": 18, "pin_functions": {}, @@ -292863,7 +293514,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y233": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 65, + "words": 2 + } + }, "grid_x": 169, "grid_y": 17, "pin_functions": {}, @@ -292872,7 +293530,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y234": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 67, + "words": 2 + } + }, "grid_x": 169, "grid_y": 16, "pin_functions": {}, @@ -292881,7 +293546,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y235": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 69, + "words": 2 + } + }, "grid_x": 169, "grid_y": 15, "pin_functions": {}, @@ -292890,7 +293562,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y236": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 71, + "words": 2 + } + }, "grid_x": 169, "grid_y": 14, "pin_functions": {}, @@ -292899,7 +293578,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y237": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 73, + "words": 2 + } + }, "grid_x": 169, "grid_y": 13, "pin_functions": {}, @@ -292908,7 +293594,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y238": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 75, + "words": 2 + } + }, "grid_x": 169, "grid_y": 12, "pin_functions": {}, @@ -292917,7 +293610,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y239": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 77, + "words": 2 + } + }, "grid_x": 169, "grid_y": 11, "pin_functions": {}, @@ -292926,7 +293626,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y240": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 79, + "words": 2 + } + }, "grid_x": 169, "grid_y": 10, "pin_functions": {}, @@ -292935,7 +293642,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y241": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 81, + "words": 2 + } + }, "grid_x": 169, "grid_y": 9, "pin_functions": {}, @@ -292944,7 +293658,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y242": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 83, + "words": 2 + } + }, "grid_x": 169, "grid_y": 8, "pin_functions": {}, @@ -292953,7 +293674,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y243": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 85, + "words": 2 + } + }, "grid_x": 169, "grid_y": 7, "pin_functions": {}, @@ -292962,7 +293690,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y244": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 87, + "words": 2 + } + }, "grid_x": 169, "grid_y": 6, "pin_functions": {}, @@ -292971,7 +293706,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y245": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 89, + "words": 2 + } + }, "grid_x": 169, "grid_y": 5, "pin_functions": {}, @@ -292980,7 +293722,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y246": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 91, + "words": 2 + } + }, "grid_x": 169, "grid_y": 4, "pin_functions": {}, @@ -292989,7 +293738,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y247": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 93, + "words": 2 + } + }, "grid_x": 169, "grid_y": 3, "pin_functions": {}, @@ -292998,7 +293754,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y248": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 95, + "words": 2 + } + }, "grid_x": 169, "grid_y": 2, "pin_functions": {}, @@ -293007,7 +293770,14 @@ "type": "GTX_INT_INTERFACE" }, "GTX_INT_INTERFACE_X67Y249": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00022180", + "frames": 28, + "offset": 97, + "words": 2 + } + }, "grid_x": 169, "grid_y": 1, "pin_functions": {}, @@ -733680,14 +734450,7 @@ "type": "RIOI" }, "RIOI_X73Y9": { - "bits": { - "CLB_IO_CLK": { - "baseaddr": "0x00442480", - "frames": 42, - "offset": 18, - "words": 4 - } - }, + "bits": {}, "clock_region": "X1Y0", "grid_x": 188, "grid_y": 250, diff --git a/kintex7/xc7k160tffg676-2/package_pins.csv b/kintex7/xc7k160tffg676-2/package_pins.csv index c0b23b3..c8dfcc5 100644 --- a/kintex7/xc7k160tffg676-2/package_pins.csv +++ b/kintex7/xc7k160tffg676-2/package_pins.csv @@ -1,443 +1,443 @@ pin,bank,site,tile,pin_function -A3,116,OPAD_X0Y14,GTX_CHANNEL_3_X172Y254,MGTXTXN3_116 -A4,116,OPAD_X0Y15,GTX_CHANNEL_3_X172Y254,MGTXTXP3_116 -A8,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16 -A9,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16 -A10,16,IOB_X0Y205,LIOB33_X0Y205,IO_L22N_T3_16 -A12,16,IOB_X0Y201,LIOB33_X0Y201,IO_L24N_T3_16 -A13,16,IOB_X0Y202,LIOB33_X0Y201,IO_L24P_T3_16 -A14,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16 -A15,16,IOB_X0Y203,LIOB33_X0Y203,IO_L23N_T3_16 -A17,15,IOB_X0Y193,LIOB33_X0Y193,IO_L3N_T0_DQS_AD1N_15 -A18,15,IOB_X0Y196,LIOB33_X0Y195,IO_L2P_T0_AD8P_15 -A19,15,IOB_X0Y195,LIOB33_X0Y195,IO_L2N_T0_AD8N_15 -A20,14,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_D12_14 -A22,14,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_D03_14 -A23,14,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_D04_14 -A24,14,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_D05_14 -A25,14,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_D01_DIN_14 -AA2,34,IOB_X1Y125,RIOB18_X73Y125,IO_L12N_T1_MRCC_34 -AA3,34,IOB_X1Y126,RIOB18_X73Y125,IO_L12P_T1_MRCC_34 -AA4,34,IOB_X1Y124,RIOB18_X73Y123,IO_L13P_T2_MRCC_34 -AA5,34,IOB_X1Y120,RIOB18_X73Y119,IO_L15P_T2_DQS_34 -AA7,33,IOB_X1Y83,RIOB18_X73Y83,IO_L8N_T1_33 -AA8,33,IOB_X1Y84,RIOB18_X73Y83,IO_L8P_T1_33 -AA9,33,IOB_X1Y78,RIOB18_X73Y77,IO_L11P_T1_SRCC_33 -AA10,33,IOB_X1Y72,RIOB18_X73Y71,IO_L14P_T2_SRCC_33 -AA12,33,IOB_X1Y67,RIOB18_X73Y67,IO_L16N_T2_33 -AA13,33,IOB_X1Y68,RIOB18_X73Y67,IO_L16P_T2_33 -AA14,32,IOB_X1Y36,RIOB18_X73Y35,IO_L7P_T1_32 -AA15,32,IOB_X1Y35,RIOB18_X73Y35,IO_L7N_T1_32 -AA17,32,IOB_X1Y28,RIOB18_X73Y27,IO_L11P_T1_SRCC_32 -AA18,32,IOB_X1Y27,RIOB18_X73Y27,IO_L11N_T1_SRCC_32 -AA19,32,IOB_X1Y18,RIOB18_X73Y17,IO_L16P_T2_32 -AA20,32,IOB_X1Y17,RIOB18_X73Y17,IO_L16N_T2_32 -AA22,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12 -AA23,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12 -AA24,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12 -AA25,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12 -AB1,34,IOB_X1Y132,RIOB18_X73Y131,IO_L9P_T1_DQS_34 -AB2,34,IOB_X1Y128,RIOB18_X73Y127,IO_L11P_T1_SRCC_34 -AB4,34,IOB_X1Y123,RIOB18_X73Y123,IO_L13N_T2_MRCC_34 -AB5,34,IOB_X1Y119,RIOB18_X73Y119,IO_L15N_T2_DQS_34 -AB6,34,IOB_X1Y118,RIOB18_X73Y117,IO_L16P_T2_34 -AB7,33,IOB_X1Y80,RIOB18_X73Y79,IO_L10P_T1_33 -AB9,33,IOB_X1Y77,RIOB18_X73Y77,IO_L11N_T1_SRCC_33 -AB10,33,IOB_X1Y71,RIOB18_X73Y71,IO_L14N_T2_SRCC_33 -AB11,33,IOB_X1Y74,RIOB18_X73Y73,IO_L13P_T2_MRCC_33 -AB12,33,IOB_X1Y70,RIOB18_X73Y69,IO_L15P_T2_DQS_33 -AB14,32,IOB_X1Y30,RIOB18_X73Y29,IO_L10P_T1_32 -AB15,32,IOB_X1Y29,RIOB18_X73Y29,IO_L10N_T1_32 -AB16,32,IOB_X1Y26,RIOB18_X73Y25,IO_L12P_T1_MRCC_32 -AB17,32,IOB_X1Y22,RIOB18_X73Y21,IO_L14P_T2_SRCC_32 -AB19,32,IOB_X1Y14,RIOB18_X73Y13,IO_L18P_T2_32 -AB20,32,IOB_X1Y13,RIOB18_X73Y13,IO_L18N_T2_32 -AB21,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12 -AB22,12,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_12 -AB24,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12 -AB25,12,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_12 -AB26,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12 -AC1,34,IOB_X1Y131,RIOB18_X73Y131,IO_L9N_T1_DQS_34 -AC2,34,IOB_X1Y127,RIOB18_X73Y127,IO_L11N_T1_SRCC_34 -AC3,34,IOB_X1Y121,RIOB18_X73Y121,IO_L14N_T2_SRCC_34 -AC4,34,IOB_X1Y122,RIOB18_X73Y121,IO_L14P_T2_SRCC_34 -AC6,34,IOB_X1Y117,RIOB18_X73Y117,IO_L16N_T2_34 -AC7,33,IOB_X1Y79,RIOB18_X73Y79,IO_L10N_T1_33 -AC8,33,IOB_X1Y82,RIOB18_X73Y81,IO_L9P_T1_DQS_33 -AC9,33,IOB_X1Y76,RIOB18_X73Y75,IO_L12P_T1_MRCC_33 -AC11,33,IOB_X1Y73,RIOB18_X73Y73,IO_L13N_T2_MRCC_33 -AC12,33,IOB_X1Y69,RIOB18_X73Y69,IO_L15N_T2_DQS_33 -AC13,33,IOB_X1Y66,RIOB18_X73Y65,IO_L17P_T2_33 -AC14,32,IOB_X1Y34,RIOB18_X73Y33,IO_L8P_T1_32 -AC16,32,IOB_X1Y25,RIOB18_X73Y25,IO_L12N_T1_MRCC_32 -AC17,32,IOB_X1Y21,RIOB18_X73Y21,IO_L14N_T2_SRCC_32 -AC18,32,IOB_X1Y24,RIOB18_X73Y23,IO_L13P_T2_MRCC_32 -AC19,32,IOB_X1Y16,RIOB18_X73Y15,IO_L17P_T2_32 -AC21,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12 -AC22,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12 -AC23,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12 -AC24,12,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_12 -AC26,12,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_12 -AD1,34,IOB_X1Y110,RIOB18_X73Y109,IO_L20P_T3_34 -AD3,34,IOB_X1Y111,RIOB18_X73Y111,IO_L19N_T3_VREF_34 -AD4,34,IOB_X1Y112,RIOB18_X73Y111,IO_L19P_T3_34 -AD5,34,IOB_X1Y113,RIOB18_X73Y113,IO_L18N_T2_34 -AD6,34,IOB_X1Y114,RIOB18_X73Y113,IO_L18P_T2_34 -AD8,33,IOB_X1Y81,RIOB18_X73Y81,IO_L9N_T1_DQS_33 -AD9,33,IOB_X1Y75,RIOB18_X73Y75,IO_L12N_T1_MRCC_33 -AD10,33,IOB_X1Y60,RIOB18_X73Y59,IO_L20P_T3_33 -AD11,33,IOB_X1Y62,RIOB18_X73Y61,IO_L19P_T3_33 -AD13,33,IOB_X1Y65,RIOB18_X73Y65,IO_L17N_T2_33 -AD14,32,IOB_X1Y33,RIOB18_X73Y33,IO_L8N_T1_32 -AD15,32,IOB_X1Y42,RIOB18_X73Y41,IO_L4P_T0_32 -AD16,32,IOB_X1Y38,RIOB18_X73Y37,IO_L6P_T0_32 -AD18,32,IOB_X1Y23,RIOB18_X73Y23,IO_L13N_T2_MRCC_32 -AD19,32,IOB_X1Y15,RIOB18_X73Y15,IO_L17N_T2_32 -AD20,32,IOB_X1Y20,RIOB18_X73Y19,IO_L15P_T2_DQS_32 -AD21,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12 -AD23,12,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_12 -AD24,12,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_12 -AD25,12,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_12 -AD26,12,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_12 -AE1,34,IOB_X1Y109,RIOB18_X73Y109,IO_L20N_T3_34 -AE2,34,IOB_X1Y105,RIOB18_X73Y105,IO_L22N_T3_34 -AE3,34,IOB_X1Y106,RIOB18_X73Y105,IO_L22P_T3_34 -AE5,34,IOB_X1Y103,RIOB18_X73Y103,IO_L23N_T3_34 -AE6,34,IOB_X1Y104,RIOB18_X73Y103,IO_L23P_T3_34 -AE7,33,IOB_X1Y86,RIOB18_X73Y85,IO_L7P_T1_33 -AE8,33,IOB_X1Y56,RIOB18_X73Y55,IO_L22P_T3_33 -AE10,33,IOB_X1Y59,RIOB18_X73Y59,IO_L20N_T3_33 -AE11,33,IOB_X1Y61,RIOB18_X73Y61,IO_L19N_T3_VREF_33 -AE12,33,IOB_X1Y58,RIOB18_X73Y57,IO_L21P_T3_DQS_33 -AE13,33,IOB_X1Y54,RIOB18_X73Y53,IO_L23P_T3_33 -AE15,32,IOB_X1Y41,RIOB18_X73Y41,IO_L4N_T0_32 -AE16,32,IOB_X1Y37,RIOB18_X73Y37,IO_L6N_T0_VREF_32 -AE17,32,IOB_X1Y48,RIOB18_X73Y47,IO_L1P_T0_32 -AE18,32,IOB_X1Y44,RIOB18_X73Y43,IO_L3P_T0_DQS_32 -AE20,32,IOB_X1Y19,RIOB18_X73Y19,IO_L15N_T2_DQS_32 -AE21,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12 -AE22,12,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_12 -AE23,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12 -AE25,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12 -AE26,12,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_12 -AF2,34,IOB_X1Y101,RIOB18_X73Y101,IO_L24N_T3_34 -AF3,34,IOB_X1Y102,RIOB18_X73Y101,IO_L24P_T3_34 -AF4,34,IOB_X1Y107,RIOB18_X73Y107,IO_L21N_T3_DQS_34 -AF5,34,IOB_X1Y108,RIOB18_X73Y107,IO_L21P_T3_DQS_34 -AF7,33,IOB_X1Y85,RIOB18_X73Y85,IO_L7N_T1_33 -AF8,33,IOB_X1Y55,RIOB18_X73Y55,IO_L22N_T3_33 -AF9,33,IOB_X1Y51,RIOB18_X73Y51,IO_L24N_T3_33 -AF10,33,IOB_X1Y52,RIOB18_X73Y51,IO_L24P_T3_33 -AF12,33,IOB_X1Y57,RIOB18_X73Y57,IO_L21N_T3_DQS_33 -AF13,33,IOB_X1Y53,RIOB18_X73Y53,IO_L23N_T3_33 -AF14,32,IOB_X1Y46,RIOB18_X73Y45,IO_L2P_T0_32 -AF15,32,IOB_X1Y45,RIOB18_X73Y45,IO_L2N_T0_32 -AF17,32,IOB_X1Y47,RIOB18_X73Y47,IO_L1N_T0_32 -AF18,32,IOB_X1Y43,RIOB18_X73Y43,IO_L3N_T0_DQS_32 -AF19,32,IOB_X1Y40,RIOB18_X73Y39,IO_L5P_T0_32 -AF20,32,IOB_X1Y39,RIOB18_X73Y39,IO_L5N_T0_32 -AF22,12,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_12 -AF23,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12 -AF24,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12 -AF25,12,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_12 -B1,116,OPAD_X0Y12,GTX_CHANNEL_2_X172Y243,MGTXTXN2_116 -B2,116,OPAD_X0Y13,GTX_CHANNEL_2_X172Y243,MGTXTXP2_116 -B5,116,IPAD_X1Y60,GTX_CHANNEL_3_X172Y254,MGTXRXN3_116 -B6,116,IPAD_X1Y61,GTX_CHANNEL_3_X172Y254,MGTXRXP3_116 -B9,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16 -B10,16,IOB_X0Y206,LIOB33_X0Y205,IO_L22P_T3_16 -B11,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16 -B12,16,IOB_X0Y210,LIOB33_X0Y209,IO_L20P_T3_16 -B14,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16 -B15,16,IOB_X0Y204,LIOB33_X0Y203,IO_L23P_T3_16 -B16,15,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_AD0N_15 -B17,15,IOB_X0Y194,LIOB33_X0Y193,IO_L3P_T0_DQS_AD1P_15 -B19,15,IOB_X0Y191,LIOB33_X0Y191,IO_L4N_T0_AD9N_15 -B20,14,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_D11_14 -B21,14,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_D15_14 -B22,14,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_D02_14 -B24,14,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_D00_MOSI_14 -B25,14,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_PUDC_B_14 -B26,14,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_EMCCLK_14 -C3,116,IPAD_X1Y54,GTX_CHANNEL_2_X172Y243,MGTXRXN2_116 -C4,116,IPAD_X1Y55,GTX_CHANNEL_2_X172Y243,MGTXRXP2_116 -C9,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16 -C11,16,IOB_X0Y223,LIOB33_X0Y223,IO_L13N_T2_MRCC_16 -C12,16,IOB_X0Y224,LIOB33_X0Y223,IO_L13P_T2_MRCC_16 -C13,16,IOB_X0Y211,LIOB33_X0Y211,IO_L19N_T3_VREF_16 -C14,16,IOB_X0Y212,LIOB33_X0Y211,IO_L19P_T3_16 -C16,15,IOB_X0Y198,LIOB33_X0Y197,IO_L1P_T0_AD0P_15 -C17,15,IOB_X0Y190,LIOB33_X0Y189,IO_L5P_T0_AD2P_15 -C18,15,IOB_X0Y189,LIOB33_X0Y189,IO_L5N_T0_AD2N_15 -C19,15,IOB_X0Y192,LIOB33_X0Y191,IO_L4P_T0_AD9P_15 -C21,14,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_D14_14 -C22,14,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_D10_14 -C23,14,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_FCS_B_14 -C24,14,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_D08_VREF_14 -C26,14,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_D07_14 -D1,116,OPAD_X0Y10,GTX_CHANNEL_1_X172Y225,MGTXTXN1_116 -D2,116,OPAD_X0Y11,GTX_CHANNEL_1_X172Y225,MGTXTXP1_116 -D5,116,IPAD_X1Y45,GTX_COMMON_X172Y231,MGTREFCLK0N_116 -D6,116,IPAD_X1Y44,GTX_COMMON_X172Y231,MGTREFCLK0P_116 -D8,16,IOB_X0Y233,LIOB33_X0Y233,IO_L8N_T1_16 -D9,16,IOB_X0Y234,LIOB33_X0Y233,IO_L8P_T1_16 -D10,16,IOB_X0Y225,LIOB33_X0Y225,IO_L12N_T1_MRCC_16 -D11,16,IOB_X0Y221,LIOB33_X0Y221,IO_L14N_T2_SRCC_16 -D13,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16 -D14,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16 -D15,15,IOB_X0Y188,LIOB33_X0Y187,IO_L6P_T0_15 -D16,15,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_15 -D18,15,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_15 -D19,15,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_15 -D20,15,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_ADV_B_15 -D21,14,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_D09_14 -D23,14,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_14 -D24,14,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_14 -D25,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14 -D26,14,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_D06_14 -E3,116,IPAD_X1Y42,GTX_CHANNEL_1_X172Y225,MGTXRXN1_116 -E4,116,IPAD_X1Y43,GTX_CHANNEL_1_X172Y225,MGTXRXP1_116 -E10,16,IOB_X0Y226,LIOB33_X0Y225,IO_L12P_T1_MRCC_16 -E11,16,IOB_X0Y222,LIOB33_X0Y221,IO_L14P_T2_SRCC_16 -E12,16,IOB_X0Y213,LIOB33_X0Y213,IO_L18N_T2_16 -E13,16,IOB_X0Y214,LIOB33_X0Y213,IO_L18P_T2_16 -E15,15,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_AD4P_15 -E16,15,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_AD4N_15 -E17,15,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_AD5N_15 -E18,15,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_15 -E20,15,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_A25_15 -E21,14,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_14 -E22,14,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_D13_14 -E23,14,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_14 -E25,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14 -E26,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14 -F1,116,OPAD_X0Y8,GTX_CHANNEL_0_X172Y214,MGTXTXN0_116 -F2,116,OPAD_X0Y9,GTX_CHANNEL_0_X172Y214,MGTXTXP0_116 -F5,116,IPAD_X1Y47,GTX_COMMON_X172Y231,MGTREFCLK1N_116 -F6,116,IPAD_X1Y46,GTX_COMMON_X172Y231,MGTREFCLK1P_116 -F8,16,IOB_X0Y235,LIOB33_X0Y235,IO_L7N_T1_16 -F9,16,IOB_X0Y236,LIOB33_X0Y235,IO_L7P_T1_16 -F10,16,IOB_X0Y227,LIOB33_X0Y227,IO_L11N_T1_SRCC_16 -F12,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16 -F13,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16 -F14,16,IOB_X0Y220,LIOB33_X0Y219,IO_L15P_T2_DQS_16 -F15,15,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_AD3N_15 -F17,15,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_AD5P_15 -F18,15,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_AD12N_15 -F19,15,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_A26_15 -F20,15,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_A27_15 -F22,14,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_14 -F23,14,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_14 -F24,14,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_14 -F25,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14 -G3,116,IPAD_X1Y36,GTX_CHANNEL_0_X172Y214,MGTXRXN0_116 -G4,116,IPAD_X1Y37,GTX_CHANNEL_0_X172Y214,MGTXRXP0_116 -G9,16,IOB_X0Y245,LIOB33_X0Y245,IO_L2N_T0_16 -G10,16,IOB_X0Y246,LIOB33_X0Y245,IO_L2P_T0_16 -G11,16,IOB_X0Y228,LIOB33_X0Y227,IO_L11P_T1_SRCC_16 -G12,16,IOB_X0Y218,LIOB33_X0Y217,IO_L16P_T2_16 -G14,16,IOB_X0Y239,LIOB33_X0Y239,IO_L5N_T0_16 -G15,15,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_AD3P_15 -G16,15,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_AD10N_15 -G17,15,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_AD12P_15 -G19,15,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_A28_15 -G20,15,IOB_X0Y163,LIOB33_X0Y163,IO_L18N_T2_A23_15 -G21,14,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A09_D25_VREF_14 -G22,14,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_14 -G24,14,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_14 -G25,14,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_CSI_B_14 -G26,14,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A15_D31_14 -H1,115,OPAD_X0Y6,GTX_CHANNEL_3_X172Y202,MGTXTXN3_115 -H2,115,OPAD_X0Y7,GTX_CHANNEL_3_X172Y202,MGTXTXP3_115 -H5,115,IPAD_X1Y9,GTX_COMMON_X172Y179,MGTREFCLK0N_115 -H6,115,IPAD_X1Y8,GTX_COMMON_X172Y179,MGTREFCLK0P_115 -H8,16,IOB_X0Y247,LIOB33_X0Y247,IO_L1N_T0_16 -H9,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16 -H11,16,IOB_X0Y237,LIOB33_X0Y237,IO_L6N_T0_VREF_16 -H12,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16 -H13,16,IOB_X0Y243,LIOB33_X0Y243,IO_L3N_T0_DQS_16 -H14,16,IOB_X0Y240,LIOB33_X0Y239,IO_L5P_T0_16 -H16,15,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_AD10P_15 -H17,15,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_15 -H18,15,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_15 -H19,15,IOB_X0Y164,LIOB33_X0Y163,IO_L18P_T2_A24_15 -H21,14,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A10_D26_14 -H22,14,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A06_D22_14 -H23,14,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A08_D24_14 -H24,14,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A07_D23_14 -H26,14,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A11_D27_14 -J3,115,IPAD_X1Y30,GTX_CHANNEL_3_X172Y202,MGTXRXN3_115 -J4,115,IPAD_X1Y31,GTX_CHANNEL_3_X172Y202,MGTXRXP3_115 -J8,16,IOB_X0Y249,LIOB33_SING_X0Y249,IO_0_16 -J10,16,IOB_X0Y241,LIOB33_X0Y241,IO_L4N_T0_16 -J11,16,IOB_X0Y242,LIOB33_X0Y241,IO_L4P_T0_16 -J13,16,IOB_X0Y244,LIOB33_X0Y243,IO_L3P_T0_DQS_16 -J14,16,IOB_X0Y200,LIOB33_SING_X0Y200,IO_25_16 -J15,15,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_AD11P_15 -J16,15,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_AD11N_15 -J18,15,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_A20_15 -J19,15,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_A19_15 -J20,15,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_A21_VREF_15 -J21,14,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_14 -J23,14,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_A00_D16_14 -J24,14,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A05_D21_14 -J25,14,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A04_D20_14 -J26,14,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A12_D28_14 -K1,115,OPAD_X0Y4,GTX_CHANNEL_2_X172Y191,MGTXTXN2_115 -K2,115,OPAD_X0Y5,GTX_CHANNEL_2_X172Y191,MGTXTXP2_115 -K5,115,IPAD_X1Y11,GTX_COMMON_X172Y179,MGTREFCLK1N_115 -K6,115,IPAD_X1Y10,GTX_COMMON_X172Y179,MGTREFCLK1P_115 -K15,15,IOB_X0Y199,LIOB33_SING_X0Y199,IO_0_15 -K16,15,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_A17_15 -K17,15,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_A16_15 -K18,15,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_RS0_15 -K20,15,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_A22_15 -K21,14,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_14 -K22,14,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_A02_D18_14 -K23,14,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_A01_D17_14 -K25,13,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_13 -K26,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13 -L3,115,IPAD_X1Y24,GTX_CHANNEL_2_X172Y191,MGTXRXN2_115 -L4,115,IPAD_X1Y25,GTX_CHANNEL_2_X172Y191,MGTXRXP2_115 -L17,15,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_RS1_15 -L18,15,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_FWE_B_15 -L19,15,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_15 -L20,15,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_A18_15 -L22,14,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_A03_D19_14 -L23,14,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_14 -L24,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13 -L25,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13 -M1,115,OPAD_X0Y2,GTX_CHANNEL_1_X172Y173,MGTXTXN1_115 -M2,115,OPAD_X0Y3,GTX_CHANNEL_1_X172Y173,MGTXTXP1_115 -M16,15,IOB_X0Y150,LIOB33_SING_X0Y150,IO_25_15 -M17,15,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_FOE_B_15 -M19,13,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_13 -M20,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13 -M21,13,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_13 -M22,13,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_13 -M24,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13 -M25,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13 -M26,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13 -N3,115,IPAD_X1Y6,GTX_CHANNEL_1_X172Y173,MGTXRXN1_115 -N4,115,IPAD_X1Y7,GTX_CHANNEL_1_X172Y173,MGTXRXP1_115 N12,0,IPAD_X0Y18,MONITOR_BOT_FUJI2_X61Y183,VP_0 -N16,13,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_13 -N17,13,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_13 -N18,13,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_13 -N19,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13 -N21,13,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_13 -N22,13,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_13 -N23,13,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_13 -N24,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13 -N26,13,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_13 -P1,115,OPAD_X0Y0,GTX_CHANNEL_0_X172Y162,MGTXTXN0_115 -P2,115,OPAD_X0Y1,GTX_CHANNEL_0_X172Y162,MGTXTXP0_115 P11,0,IPAD_X0Y19,MONITOR_BOT_FUJI2_X61Y183,VN_0 -P16,13,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_13 -P18,13,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_13 -P19,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13 -P20,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13 -P21,13,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_13 -P23,13,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_13 -P24,13,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_13 -P25,13,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_13 -P26,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13 -R3,115,IPAD_X1Y0,GTX_CHANNEL_0_X172Y162,MGTXRXN0_115 -R4,115,IPAD_X1Y1,GTX_CHANNEL_0_X172Y162,MGTXRXP0_115 -R16,13,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_13 -R17,13,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_13 -R18,13,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_13 -R20,13,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_13 -R21,13,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_13 -R22,13,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_13 -R23,13,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_13 -R25,13,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_13 -R26,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13 -T7,34,IOB_X1Y100,RIOB18_SING_X73Y100,IO_25_VRP_34 -T17,13,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_13 -T18,13,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_13 -T19,13,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_VREF_13 -T20,13,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_13 -T22,13,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_13 -T23,13,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_13 -T24,13,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_13 -T25,13,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_13 -U1,34,IOB_X1Y145,RIOB18_X73Y145,IO_L2N_T0_34 -U2,34,IOB_X1Y146,RIOB18_X73Y145,IO_L2P_T0_34 -U4,34,IOB_X1Y149,RIOB18_SING_X73Y149,IO_0_VRN_34 -U5,34,IOB_X1Y147,RIOB18_X73Y147,IO_L1N_T0_34 -U6,34,IOB_X1Y148,RIOB18_X73Y147,IO_L1P_T0_34 -U7,34,IOB_X1Y140,RIOB18_X73Y139,IO_L5P_T0_34 -U9,33,IOB_X1Y99,RIOB18_SING_X73Y99,IO_0_VRN_33 -U16,13,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_13 -U17,13,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_13 -U19,13,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_13 -U20,13,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_13 U21,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12 U22,12,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_12 +V22,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12 U24,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12 U25,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12 -U26,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12 -V1,34,IOB_X1Y133,RIOB18_X73Y133,IO_L8N_T1_34 -V2,34,IOB_X1Y134,RIOB18_X73Y133,IO_L8P_T1_34 -V3,34,IOB_X1Y142,RIOB18_X73Y141,IO_L4P_T0_34 -V4,34,IOB_X1Y138,RIOB18_X73Y137,IO_L6P_T0_34 -V6,34,IOB_X1Y139,RIOB18_X73Y139,IO_L5N_T0_34 -V7,33,IOB_X1Y95,RIOB18_X73Y95,IO_L2N_T0_33 -V8,33,IOB_X1Y96,RIOB18_X73Y95,IO_L2P_T0_33 -V9,33,IOB_X1Y88,RIOB18_X73Y87,IO_L6P_T0_33 -V11,33,IOB_X1Y98,RIOB18_X73Y97,IO_L1P_T0_33 -V12,33,IOB_X1Y50,RIOB18_SING_X73Y50,IO_25_VRP_33 -V13,32,IOB_X1Y49,RIOB18_SING_X73Y49,IO_0_VRN_32 -V14,32,IOB_X1Y2,RIOB18_X73Y1,IO_L24P_T3_32 -V16,32,IOB_X1Y10,RIOB18_X73Y9,IO_L20P_T3_32 -V17,32,IOB_X1Y9,RIOB18_X73Y9,IO_L20N_T3_32 -V18,32,IOB_X1Y4,RIOB18_X73Y3,IO_L23P_T3_32 -V19,32,IOB_X1Y3,RIOB18_X73Y3,IO_L23N_T3_32 -V21,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12 -V22,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12 V23,12,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_12 V24,12,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_12 +U26,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12 V26,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12 -W1,34,IOB_X1Y130,RIOB18_X73Y129,IO_L10P_T1_34 -W3,34,IOB_X1Y141,RIOB18_X73Y141,IO_L4N_T0_34 -W4,34,IOB_X1Y137,RIOB18_X73Y137,IO_L6N_T0_VREF_34 -W5,34,IOB_X1Y143,RIOB18_X73Y143,IO_L3N_T0_DQS_34 -W6,34,IOB_X1Y144,RIOB18_X73Y143,IO_L3P_T0_DQS_34 -W8,33,IOB_X1Y87,RIOB18_X73Y87,IO_L6N_T0_VREF_33 -W9,33,IOB_X1Y93,RIOB18_X73Y93,IO_L3N_T0_DQS_33 -W10,33,IOB_X1Y94,RIOB18_X73Y93,IO_L3P_T0_DQS_33 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