diff --git a/Info.md b/Info.md index 8d9b94e..fff47f0 100644 --- a/Info.md +++ b/Info.md @@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING). # Details -Last updated on Thu 18 Feb 2021 04:28:24 PM UTC (2021-02-18T16:28:24+00:00). +Last updated on Thu 25 Feb 2021 06:48:02 PM UTC (2021-02-25T18:48:02+00:00). -Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [f3028e15](https://github.com/SymbiFlow/prjxray/commit/f3028e157e5f554e085af2a58247e2c8c7be0f3b). +Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [6867429c](https://github.com/SymbiFlow/prjxray/commit/6867429cc3a4ce422b06ceda100b868a0a7f8b23). Latest commit was; ``` -commit f3028e157e5f554e085af2a58247e2c8c7be0f3b -Merge: 2c9571d1 82662476 +commit 6867429cc3a4ce422b06ceda100b868a0a7f8b23 +Merge: 45abab75 9b4f4551 Author: litghost <537074+litghost@users.noreply.github.com> -Date: Wed Feb 17 09:26:49 2021 -0800 +Date: Wed Feb 24 08:23:12 2021 -0800 - Merge pull request #1591 from antmicro/add-dsp-pips + Merge pull request #1592 from antmicro/fix-iob-lvds-tmds - 101-dsp-pips: solve DSP-related PIPs + 030-iob: improve rdb processing for LVDS and TMDS ``` @@ -59,7 +59,7 @@ Date: Wed Feb 17 09:26:49 2021 -0800 ### Settings -Created using following [settings/artix7.sh (sha256: 00d45bf1672d3460e8d452cda8e747fa713eed629aa086b219162886452013e4)](https://github.com/SymbiFlow/prjxray/blob/f3028e157e5f554e085af2a58247e2c8c7be0f3b/settings/artix7.sh) +Created using following [settings/artix7.sh (sha256: 00d45bf1672d3460e8d452cda8e747fa713eed629aa086b219162886452013e4)](https://github.com/SymbiFlow/prjxray/blob/6867429cc3a4ce422b06ceda100b868a0a7f8b23/settings/artix7.sh) ```shell #!/bin/bash # Copyright (C) 2017-2020 The Project X-Ray Authors. @@ -109,24 +109,20 @@ Results have checksums; * [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9 ./artix7/harness/README.md`](./artix7/harness/README.md) * [`560f255b569fd4798989f45104d4a511b51380418d4ca6fc53201141b36b20aa ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit) * [`1d8a121c3aa3bca7893429cfb08a8748206134271432daa52cdc9d3f5593bda0 ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp) - * [`38d9952e3e0a9bee6829dd338fa1965e150fd0d75fea13891d7a6a64fb5e14a5 ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json) + * [`b57ed4b48e47f3bc75e9a95dd15bc40082d3bbb35883a646d98c1ed60402713c ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json) * [`fb90ad5fe10750f33d5802e1409ebc2406f7b0adab4bf6ef12b53c0e100b43ea ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt) * [`931c1598b75005a8a8e5b2225cc7454c2c7be451cb907bc4c047cb04db99772d ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit) * [`5d06132c788097344a9bca7040a08dd0e1632e177ed8def1d7445132020cc768 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp) - * [`b1ff8026fb1ae19410884c09075306fe0cbeef8b4116bf7070979d19d1842bfa ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json) + * [`ff29541f33458d2912cc630f03df7ee959246bb783c5840cddea32b42746b52f ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json) * [`884af447661ff1cb653cd8280602c2348435366b35bf2627e2221af34899d191 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt) * [`128e73ee026cf2238a35c7e993b845e3551919c90fc77b277635bc5098d59741 ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit) * [`955daed70c5728c13865eddc9bd7001d93183a50c560559a7b6628aa85b1fbbe ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp) - * [`c9cc30b017bf4345b3f0d6707f76cd50da2e7b6f045877bc99c1404147b1bb1e ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json) + * [`b902e72932a9039258a0e469a0499e5621adc1e797e6b201290d05a9313ac3cd ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json) * [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt) * [`d3109010f8fced3be08e720741a157d08b7042359e84d04bbe677f50cbf10a04 ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit) * [`abedfa7f2ee5a4dbc51b582ebae62dd20489f745a4a239e49b18ba3e02be019f ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp) - * [`77aaf986289d5d97ab80a61fe6ef9708e03a95f4de895ec8c9b364c602b98424 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json) + * [`a63c62d553aa5811bf3d98c82d998733bf27e28c57328c08e7329f5dd980b9c2 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json) * [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt) - * [`3ad62b024991225f1565e84159f2eb59d08e9fc6cf2577ea1698952b5dc0e4ec ./artix7/harness/basys3/swbut_50/design.bit`](./artix7/harness/basys3/swbut_50/design.bit) - * [`773fe43b4974ab353bde87e544abb6b541cdcb280de40df76afa96f7fa23db46 ./artix7/harness/basys3/swbut_50/design.dcp`](./artix7/harness/basys3/swbut_50/design.dcp) - * [`5d08d9434fd6a8340dfe354613455554c037f6c886a35f6cc98055ff955613c1 ./artix7/harness/basys3/swbut_50/design.json`](./artix7/harness/basys3/swbut_50/design.json) - * [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut_50/design.txt`](./artix7/harness/basys3/swbut_50/design.txt) * [`e5ebd51966bcfddb9b04078203231810df64f5afd3e3a608a5fb8fdc7d3c3304 ./artix7/mapping/devices.yaml`](./artix7/mapping/devices.yaml) * [`9a63d519dcfee4016602553490a53c00a2fbc8cd0355ed201cfa3545650f6ce4 ./artix7/mapping/parts.yaml`](./artix7/mapping/parts.yaml) * [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db) @@ -217,6 +213,22 @@ Results have checksums; * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_l.origin_info.db`](./artix7/ppips_dsp_l.origin_info.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_r.db`](./artix7/ppips_dsp_r.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_r.origin_info.db`](./artix7/ppips_dsp_r.origin_info.db) + * [`9a41911dfa0be59fced626ba228abf9ef7cf020affbd2743a26ed16b6856dfd5 ./artix7/ppips_gtp_channel_0.db`](./artix7/ppips_gtp_channel_0.db) + * [`4179cf95c0e079b2bf699e944e3059470147c60de6cfcdda9bd70c907f6851df ./artix7/ppips_gtp_channel_0_mid_left.db`](./artix7/ppips_gtp_channel_0_mid_left.db) + * [`3550a2e77580e0f8385418efd0beea4d6fe2f7e21544da921116459589e58a9a ./artix7/ppips_gtp_channel_0_mid_right.db`](./artix7/ppips_gtp_channel_0_mid_right.db) + * [`42449df4353f2fc1764ee337f0e18afb0d4b419e611eda5ea7282180587c118b ./artix7/ppips_gtp_channel_1.db`](./artix7/ppips_gtp_channel_1.db) + * [`663a27fa99c2e337e961d6636bf41d57e4bbade7ba31af82623280f40ecc54f7 ./artix7/ppips_gtp_channel_1_mid_left.db`](./artix7/ppips_gtp_channel_1_mid_left.db) + * [`5502dc8909a39565bb584df2e702c9d5aada1ab7b520fa01366eb1e07e9521ca ./artix7/ppips_gtp_channel_1_mid_right.db`](./artix7/ppips_gtp_channel_1_mid_right.db) + * [`b14787fc826a3c64160af864346775ca1e387a08f23679a72c9e4fa11a436b40 ./artix7/ppips_gtp_channel_2.db`](./artix7/ppips_gtp_channel_2.db) + * [`21df745b5828962164f7d7b54df58bb308a2083f8863d5be10e870367f34a1f4 ./artix7/ppips_gtp_channel_2_mid_left.db`](./artix7/ppips_gtp_channel_2_mid_left.db) + * [`993c198a976dd0ffe90592296923210480aec35a3f259295c3486a783390d892 ./artix7/ppips_gtp_channel_2_mid_right.db`](./artix7/ppips_gtp_channel_2_mid_right.db) + * [`229584a094cadcf181cc7c9b04a0c151ad9fc0b230cccc761b33beb7109156ed ./artix7/ppips_gtp_channel_3.db`](./artix7/ppips_gtp_channel_3.db) + * [`df7fe61346d9a21e1b69ba2a045b8da6f6efa4a0d1dfab29f86577475d7b7cc3 ./artix7/ppips_gtp_channel_3_mid_left.db`](./artix7/ppips_gtp_channel_3_mid_left.db) + * [`565286894f6c314d07809888b3c17279f8784bc38dfe59ee16d3b7874ba770f8 ./artix7/ppips_gtp_channel_3_mid_right.db`](./artix7/ppips_gtp_channel_3_mid_right.db) + * [`e5b17573f36b84838c40a76bdf9015fd89bd860bb2dde3a0da80061248bcd17a ./artix7/ppips_gtp_common.db`](./artix7/ppips_gtp_common.db) + * [`afe293d42525ca4fb85e4fc795d841f9d71ac0d3be85b3d5b1c6011834492348 ./artix7/ppips_gtp_common_mid_left.db`](./artix7/ppips_gtp_common_mid_left.db) + * [`6bb1ed0b882bd46476fdc425721b67096282828cc9a7adc22176a634e1253820 ./artix7/ppips_gtp_common_mid_right.db`](./artix7/ppips_gtp_common_mid_right.db) + * [`35dd7280544b90f1de8b8d02b952a2e3180e734653c5a9889dbac3854d887cd3 ./artix7/ppips_gtp_int_interface.db`](./artix7/ppips_gtp_int_interface.db) * [`edeccdbee739f85558baee09f68ebee6cca1f2121b1ef7e38839e8a9f0797641 ./artix7/ppips_hclk_cmt.db`](./artix7/ppips_hclk_cmt.db) * [`633e6ad608c7b7fc6b5d863812fea75fd0162bf6d58dd6794e6d3f32100ec2a3 ./artix7/ppips_hclk_ioi3.db`](./artix7/ppips_hclk_ioi3.db) * [`b61bbc9db6d0de1141a87d787f5d118be0a244802eed712612ff2aa0b6aeb73a ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db) @@ -326,11 +338,11 @@ Results have checksums; * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db) * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db) - * [`457f32c2e85b71fa23faad709b0675d7cd26a8559d240a896de67d7da3bddb2d ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db) + * [`53f0117e2838f3d7b71a9132f35aec36950a59186cfcd4cb9c39d86149ee28a0 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db) - * [`f5efce54cdf0d717cc559fe071620af71389f8ddceb113b6f2fc294bb10049c1 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db) - * [`ed2b09c63c7af8dcee883f6d145743aa83d90ace16b6a3613312b6f1ce455617 ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db) - * [`3fc479e800feb07c1acdd9345785a0bd227b4be4e3863ed38aa58186c15b1a26 ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db) + * [`ac84ef8991ce42d55bd72b28e4b26d7ec00f37c94a3d2fb0c77fa4e76ea28194 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db) + * [`72a187998817e8fb0bb4922f02821a0d31051fb7ff7c5139549e601fe68b082b ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db) + * [`39de3860980e187c9d7911a18adf6536c0218f21284ef287f63bd9932f78ed5b ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db) * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db) * [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./artix7/segbits_lioi3.origin_info.db`](./artix7/segbits_lioi3.origin_info.db) * [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./artix7/segbits_lioi3_tbytesrc.db`](./artix7/segbits_lioi3_tbytesrc.db) @@ -339,12 +351,12 @@ Results have checksums; * [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250 ./artix7/segbits_lioi3_tbyteterm.origin_info.db`](./artix7/segbits_lioi3_tbyteterm.origin_info.db) * [`5d3619d34977c6fc9a2e25e0b7db002af348bf35747b99fba89072778c943c5c ./artix7/segbits_pcie_bot.db`](./artix7/segbits_pcie_bot.db) * [`f2a3c7410f318cb6906c49916104864894d0d2daba55a2173dc2033c8037bae7 ./artix7/segbits_pcie_bot.origin_info.db`](./artix7/segbits_pcie_bot.origin_info.db) - * [`b3256c5444d1721cd0f3291d381b3276348cf3c9943bb6e8dd2b0ba5f3a63c4b ./artix7/segbits_pcie_int_interface_l.db`](./artix7/segbits_pcie_int_interface_l.db) - * [`e4199fa3f738dd20e85250c6032628b275a859378c4a2a8716c6111cbafabdb5 ./artix7/segbits_pcie_int_interface_l.origin_info.db`](./artix7/segbits_pcie_int_interface_l.origin_info.db) + * [`0eb48fb48373d46d4ec033976696223e34fc16a000cad8e067e2bebf76f0a8df ./artix7/segbits_pcie_int_interface_l.db`](./artix7/segbits_pcie_int_interface_l.db) + * [`ed58243250118f8cb3e7378e04b9861aa580db4991b7026b3edc439e0cfe0a77 ./artix7/segbits_pcie_int_interface_l.origin_info.db`](./artix7/segbits_pcie_int_interface_l.origin_info.db) * [`0bc32fce572935289e5ac7b10c95fb96b78418270016546d42ab11276285343e ./artix7/segbits_pcie_int_interface_r.db`](./artix7/segbits_pcie_int_interface_r.db) * [`ad36811e5e38c911473f2c3a6b805e7bb1f6186408bb6740c0dd906754762e3b ./artix7/segbits_pcie_int_interface_r.origin_info.db`](./artix7/segbits_pcie_int_interface_r.origin_info.db) - * [`10541d81df91208703a5757830c0b89f177b18b097523f76e9f5d8f5d57e519a ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db) - * [`d9185e3cc5aee6614fd8ee0deb7d9d83ef030f4df99186d9868eede4b91b15d2 ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db) + * [`f3d531a299bfa96ec116cb97070592a2ae75776bf9738f0b192b0015b2eb74e0 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db) + * [`7b42c4babeef6857ac0e9ef248b0ba2279a3f95fd46dcf86f8f3660e2495bb74 ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db) * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./artix7/segbits_rioi3.db`](./artix7/segbits_rioi3.db) * [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./artix7/segbits_rioi3.origin_info.db`](./artix7/segbits_rioi3.origin_info.db) * [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./artix7/segbits_rioi3_tbytesrc.db`](./artix7/segbits_rioi3_tbytesrc.db) @@ -616,7 +628,7 @@ Results have checksums; ### Settings -Created using following [settings/kintex7.sh (sha256: f04c23dee2bff14bf48a04f60034d3f3d674bb3e40182cc88201265679ac42fb)](https://github.com/SymbiFlow/prjxray/blob/f3028e157e5f554e085af2a58247e2c8c7be0f3b/settings/kintex7.sh) +Created using following [settings/kintex7.sh (sha256: f04c23dee2bff14bf48a04f60034d3f3d674bb3e40182cc88201265679ac42fb)](https://github.com/SymbiFlow/prjxray/blob/6867429cc3a4ce422b06ceda100b868a0a7f8b23/settings/kintex7.sh) ```shell # Copyright (C) 2017-2020 The Project X-Ray Authors. # @@ -799,19 +811,19 @@ Results have checksums; * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db) * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db) - * [`328b6a3f6f338a3f94526f7f936e442ba9579a0e739e5432b4a63eab47360996 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db) + * [`e1439b1e1f115bff678208fc65c78f4eb104aa59d2599adb5f5c9bda1c554e47 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db) - * [`af9a0ceb5d80201d21e5677b7aeb676f6ecb822abb6c7e90dd23b39da18e0194 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db) - * [`ed2b09c63c7af8dcee883f6d145743aa83d90ace16b6a3613312b6f1ce455617 ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db) - * [`3fc479e800feb07c1acdd9345785a0bd227b4be4e3863ed38aa58186c15b1a26 ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db) + * [`fdcb761e2a4274a34fb6cf5b9029c5c1d48fca331038366ac2fe0eedb0f635f5 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db) + * [`72a187998817e8fb0bb4922f02821a0d31051fb7ff7c5139549e601fe68b082b ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db) + * [`39de3860980e187c9d7911a18adf6536c0218f21284ef287f63bd9932f78ed5b ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db) * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db) * [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./kintex7/segbits_lioi3.origin_info.db`](./kintex7/segbits_lioi3.origin_info.db) * [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./kintex7/segbits_lioi3_tbytesrc.db`](./kintex7/segbits_lioi3_tbytesrc.db) * [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c ./kintex7/segbits_lioi3_tbytesrc.origin_info.db`](./kintex7/segbits_lioi3_tbytesrc.origin_info.db) * [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b ./kintex7/segbits_lioi3_tbyteterm.db`](./kintex7/segbits_lioi3_tbyteterm.db) * [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250 ./kintex7/segbits_lioi3_tbyteterm.origin_info.db`](./kintex7/segbits_lioi3_tbyteterm.origin_info.db) - * [`10541d81df91208703a5757830c0b89f177b18b097523f76e9f5d8f5d57e519a ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db) - * [`d9185e3cc5aee6614fd8ee0deb7d9d83ef030f4df99186d9868eede4b91b15d2 ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db) + * [`f3d531a299bfa96ec116cb97070592a2ae75776bf9738f0b192b0015b2eb74e0 ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db) + * [`7b42c4babeef6857ac0e9ef248b0ba2279a3f95fd46dcf86f8f3660e2495bb74 ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db) * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./kintex7/segbits_rioi3.db`](./kintex7/segbits_rioi3.db) * [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./kintex7/segbits_rioi3.origin_info.db`](./kintex7/segbits_rioi3.origin_info.db) * [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./kintex7/segbits_rioi3_tbytesrc.db`](./kintex7/segbits_rioi3_tbytesrc.db) @@ -995,7 +1007,7 @@ Results have checksums; ### Settings -Created using following [settings/zynq7.sh (sha256: 241ebc54a73b6a3cb3eacea09b798fe9887d955ccdfe7b48994a9a10928837c2)](https://github.com/SymbiFlow/prjxray/blob/f3028e157e5f554e085af2a58247e2c8c7be0f3b/settings/zynq7.sh) +Created using following [settings/zynq7.sh (sha256: 241ebc54a73b6a3cb3eacea09b798fe9887d955ccdfe7b48994a9a10928837c2)](https://github.com/SymbiFlow/prjxray/blob/6867429cc3a4ce422b06ceda100b868a0a7f8b23/settings/zynq7.sh) ```shell # Copyright (C) 2017-2020 The Project X-Ray Authors. # @@ -1037,11 +1049,6 @@ eval $(python3 ${XRAY_UTILS_DIR}/create_environment.py) Results have checksums; * [`c38e176a49188f55bcf4f092c5dc0ae22018d174573e3894ce8e8b882792c5ed ./zynq7/element_counts.csv`](./zynq7/element_counts.csv) - * [`bfd74012f2b02547e824bac877b790ce12b84694b375205e26cb96b5f517672d ./zynq7/harness/README.md`](./zynq7/harness/README.md) - * [`71c89f2ff630726ef4daba9c3f7c2e15bd8e6d07dc576bfabdafdde72488a0da ./zynq7/harness/zybo/swbut/design.bit`](./zynq7/harness/zybo/swbut/design.bit) - * [`0ffc8577fbaf5ff4db2c3379c2a41b7860056f8dffba2a718d62896f7e7ebb8f ./zynq7/harness/zybo/swbut/design.dcp`](./zynq7/harness/zybo/swbut/design.dcp) - * [`391028996b2c3debae68c665e2432b63d391dc8428cfac9e92789b4ee4717f41 ./zynq7/harness/zybo/swbut/design.json`](./zynq7/harness/zybo/swbut/design.json) - * [`9315fdbbd691414d1cd31b798b080f53bcfe7fefc735f86f9b4d5f013d14c168 ./zynq7/harness/zybo/swbut/design.txt`](./zynq7/harness/zybo/swbut/design.txt) * [`f7801492da30281313a79230964418196192a4ecbef8d79e183429a5ca8db0d5 ./zynq7/mapping/devices.yaml`](./zynq7/mapping/devices.yaml) * [`130554b91fe91a8166096fd5425c55c6b7fa1a9a1f44bf37cce431eb111d1639 ./zynq7/mapping/parts.yaml`](./zynq7/mapping/parts.yaml) * [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_l.block_ram.db`](./zynq7/mask_bram_l.block_ram.db) @@ -1196,19 +1203,19 @@ Results have checksums; * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db) * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db) - * [`ae75525546d228829d7ba8cebcff71b25d75a50ef7fbeabe60645ee99592d86e ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db) + * [`621e9074a0f82f119ee9746ff098e92505920351aa885f6106952abef368858b ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db) - * [`1ba0ff2afa1d09037fdb6e31f6289712f3fbd37441a5f787536dc03ab78fb7ed ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db) - * [`4523957b458005d3ca55aabfc7cbd967a3ef8717c2c9eee1c5be35b886a759db ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db) - * [`091f100d6ccce6e7941b68ee8321da7577533c655743ff21f078cefd877e6b9d ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db) + * [`a55eef9788528b90c6433681387fd48064d4af45fe820d76e3016978e962f9d2 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db) + * [`72a187998817e8fb0bb4922f02821a0d31051fb7ff7c5139549e601fe68b082b ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db) + * [`39de3860980e187c9d7911a18adf6536c0218f21284ef287f63bd9932f78ed5b ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db) * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db) * [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./zynq7/segbits_lioi3.origin_info.db`](./zynq7/segbits_lioi3.origin_info.db) * [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./zynq7/segbits_lioi3_tbytesrc.db`](./zynq7/segbits_lioi3_tbytesrc.db) * [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c ./zynq7/segbits_lioi3_tbytesrc.origin_info.db`](./zynq7/segbits_lioi3_tbytesrc.origin_info.db) * [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b ./zynq7/segbits_lioi3_tbyteterm.db`](./zynq7/segbits_lioi3_tbyteterm.db) * [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250 ./zynq7/segbits_lioi3_tbyteterm.origin_info.db`](./zynq7/segbits_lioi3_tbyteterm.origin_info.db) - * [`7ac48ecadab7345faefab216256796a8c8c507b0ae37e2acc04a671b6b75a23b ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db) - * [`22df2833dae390c044b62394764b79492d77db5fa15f6434d51c86e0ef10bcb3 ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db) + * [`f3d531a299bfa96ec116cb97070592a2ae75776bf9738f0b192b0015b2eb74e0 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db) + * [`7b42c4babeef6857ac0e9ef248b0ba2279a3f95fd46dcf86f8f3660e2495bb74 ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db) * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./zynq7/segbits_rioi3.db`](./zynq7/segbits_rioi3.db) * [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./zynq7/segbits_rioi3.origin_info.db`](./zynq7/segbits_rioi3.origin_info.db) * [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./zynq7/segbits_rioi3_tbytesrc.db`](./zynq7/segbits_rioi3_tbytesrc.db) diff --git a/artix7/harness/arty-a7/pmod/design.json b/artix7/harness/arty-a7/pmod/design.json index 584b664..d75cda6 100644 --- a/artix7/harness/arty-a7/pmod/design.json +++ b/artix7/harness/arty-a7/pmod/design.json @@ -1115,19 +1115,17 @@ "LIOB33_X0Y9.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", "LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y43.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y43.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP", "LIOB33_X0Y43.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN", "LIOB33_X0Y51.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y51.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y51.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y51.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y51.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y51.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y51.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y51.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -1135,10 +1133,9 @@ "LIOB33_X0Y51.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y51.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y53.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y53.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y53.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y53.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y53.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y53.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y53.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y53.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -1146,10 +1143,9 @@ "LIOB33_X0Y53.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y53.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y75.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y75.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y75.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y75.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -1157,10 +1153,9 @@ "LIOB33_X0Y75.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y75.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y77.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y77.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y77.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y77.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y77.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y77.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y77.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y77.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y77.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", diff --git a/artix7/harness/arty-a7/swbut/design.json b/artix7/harness/arty-a7/swbut/design.json index faa60b0..a9ea557 100644 --- a/artix7/harness/arty-a7/swbut/design.json +++ b/artix7/harness/arty-a7/swbut/design.json @@ -871,28 +871,25 @@ "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y43.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y43.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP", "LIOB33_X0Y43.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN", "LIOB33_X0Y121.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y121.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y121.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y121.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y121.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y121.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y121.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y121.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", "LIOB33_X0Y121.IOB_Y1.PULLTYPE.PULLDOWN", "LIOB33_X0Y123.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y123.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y123.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y123.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y123.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y123.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y123.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y123.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y123.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -900,10 +897,9 @@ "LIOB33_X0Y123.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y123.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y125.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y125.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y125.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y125.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y125.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y125.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y125.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y125.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y125.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -911,10 +907,9 @@ "LIOB33_X0Y125.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y125.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y127.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y127.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y127.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y127.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y127.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y127.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y127.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y127.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y127.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -1037,10 +1032,9 @@ "RIOB33_X43Y61.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", "RIOB33_X43Y61.IOB_Y1.PULLTYPE.NONE", "RIOB33_X43Y75.IOB_Y0.IN_TERM.NONE", + "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y75.IOB_Y0.LVDS_25.IN", "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y75.IOB_Y1.IN_TERM.NONE", "RIOB33_X43Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", diff --git a/artix7/harness/arty-a7/uart/design.json b/artix7/harness/arty-a7/uart/design.json index 6c884f5..62abf2c 100644 --- a/artix7/harness/arty-a7/uart/design.json +++ b/artix7/harness/arty-a7/uart/design.json @@ -353,10 +353,9 @@ "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y43.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y43.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP", "LIOB33_X0Y43.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -414,19 +413,17 @@ "LIOI3_X0Y121.ILOGIC_Y1.ISERDES.NUM_CE.N1", "LIOI3_X0Y121.ILOGIC_Y1.ZINV_D", "RIOB33_X43Y67.IOB_Y0.IN_TERM.NONE", + "RIOB33_X43Y67.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y67.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y67.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y67.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y67.IOB_Y0.LVDS_25.IN", "RIOB33_X43Y67.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y67.IOB_Y1.IN_TERM.NONE", "RIOB33_X43Y67.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", "RIOB33_X43Y67.IOB_Y1.PULLTYPE.PULLDOWN", "RIOB33_X43Y75.IOB_Y0.IN_TERM.NONE", + "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y75.IOB_Y0.LVDS_25.IN", "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y75.IOB_Y1.IN_TERM.NONE", "RIOB33_X43Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", diff --git a/artix7/harness/basys3/swbut/design.json b/artix7/harness/basys3/swbut/design.json index 5e8514b..057c992 100644 --- a/artix7/harness/basys3/swbut/design.json +++ b/artix7/harness/basys3/swbut/design.json @@ -3527,10 +3527,9 @@ "LIOB33_X0Y3.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", "LIOB33_X0Y3.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y5.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y5.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y5.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y5.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y5.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y5.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y5.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y5.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -3538,10 +3537,9 @@ "LIOB33_X0Y5.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y5.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y7.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y7.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y7.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y7.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y7.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y7.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y7.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y7.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -3549,10 +3547,9 @@ "LIOB33_X0Y7.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y7.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y9.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y9.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y9.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y9.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y9.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y9.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y9.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y9.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -3560,10 +3557,9 @@ "LIOB33_X0Y9.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y11.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y11.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y11.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y11.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y11.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y11.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y11.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y11.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y11.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -3586,20 +3582,18 @@ "LIOB33_X0Y19.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", "LIOB33_X0Y19.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y43.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y43.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP", "LIOB33_X0Y43.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW", "LIOB33_X0Y43.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", "LIOB33_X0Y43.IOB_Y1.PULLTYPE.NONE", "LIOB33_X0Y111.IOB_Y0.IN_TERM.NONE", + "LIOB33_X0Y111.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "LIOB33_X0Y111.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "LIOB33_X0Y111.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "LIOB33_X0Y111.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "LIOB33_X0Y111.IOB_Y0.LVDS_25.IN", "LIOB33_X0Y111.IOB_Y0.PULLTYPE.NONE", "LIOB33_X0Y111.IOB_Y1.IN_TERM.NONE", "LIOB33_X0Y111.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW", @@ -3750,10 +3744,9 @@ "LIOI3_X0Y111.OLOGIC_Y1.OQUSED", "LIOI3_X0Y111.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF", "RIOB33_X43Y25.IOB_Y0.IN_TERM.NONE", + "RIOB33_X43Y25.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y25.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y25.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y25.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y25.IOB_Y0.LVDS_25.IN", "RIOB33_X43Y25.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y25.IOB_Y1.IN_TERM.NONE", "RIOB33_X43Y25.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -3774,10 +3767,9 @@ "RIOB33_X43Y37.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", "RIOB33_X43Y37.IOB_Y1.PULLTYPE.NONE", "RIOB33_X43Y39.IOB_Y0.IN_TERM.NONE", + "RIOB33_X43Y39.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y39.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y39.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y39.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y39.IOB_Y0.LVDS_25.IN", "RIOB33_X43Y39.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y39.IOB_Y1.IN_TERM.NONE", "RIOB33_X43Y39.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -3785,10 +3777,9 @@ "RIOB33_X43Y39.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y39.IOB_Y1.PULLTYPE.NONE", "RIOB33_X43Y43.IOB_Y0.IN_TERM.NONE", + "RIOB33_X43Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y43.IOB_Y0.LVDS_25.IN", "RIOB33_X43Y43.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y43.IOB_Y1.IN_TERM.NONE", "RIOB33_X43Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -3796,10 +3787,9 @@ "RIOB33_X43Y43.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y43.IOB_Y1.PULLTYPE.NONE", "RIOB33_X43Y45.IOB_Y0.IN_TERM.NONE", + "RIOB33_X43Y45.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y45.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y45.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y45.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y45.IOB_Y0.LVDS_25.IN", "RIOB33_X43Y45.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y45.IOB_Y1.IN_TERM.NONE", "RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", @@ -3807,10 +3797,9 @@ "RIOB33_X43Y45.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", "RIOB33_X43Y45.IOB_Y1.PULLTYPE.NONE", "RIOB33_X43Y47.IOB_Y0.IN_TERM.NONE", + "RIOB33_X43Y47.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY", "RIOB33_X43Y47.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y47.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY", "RIOB33_X43Y47.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y47.IOB_Y0.LVDS_25.IN", "RIOB33_X43Y47.IOB_Y0.PULLTYPE.NONE", "RIOB33_X43Y47.IOB_Y1.IN_TERM.NONE", "RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", diff --git a/artix7/harness/basys3/swbut_50/design.bit b/artix7/harness/basys3/swbut_50/design.bit deleted file mode 100644 index 17f0697..0000000 Binary files a/artix7/harness/basys3/swbut_50/design.bit and /dev/null differ diff --git a/artix7/harness/basys3/swbut_50/design.dcp b/artix7/harness/basys3/swbut_50/design.dcp deleted file mode 100644 index 51d7e15..0000000 Binary files a/artix7/harness/basys3/swbut_50/design.dcp and /dev/null differ diff --git a/artix7/harness/basys3/swbut_50/design.json b/artix7/harness/basys3/swbut_50/design.json deleted file mode 100644 index 93807a3..0000000 --- a/artix7/harness/basys3/swbut_50/design.json +++ /dev/null @@ -1,3763 +0,0 @@ -{ - "info": { - "GRID_X_MAX": 58, - "GRID_X_MIN": 10, - "GRID_Y_MAX": 51, - "GRID_Y_MIN": 0 - }, - "ports": [ - { - "name": "clk", - "node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0", - "pin": "W5", - "wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0" - }, - { - "name": "din[0]", - "node": "INT_L_X0Y102/EE2BEG2", - "pin": "V17", - "wire": "VBRK_X9Y107/VBRK_EE2A2", - "wires_outside_roi": [ - "BRKH_INT_X0Y49/BRKH_INT_L_LV1", - "BRKH_INT_X0Y99/BRKH_INT_NN6C2", - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_2", - "HCLK_L_X4Y26/HCLK_LV12", - "HCLK_L_X4Y78/HCLK_LV8", - "INT_INTERFACE_R_X1Y102/INT_INTERFACE_EE2A2", - "INT_L_X0Y11/LOGIC_OUTS_L18", - "INT_L_X0Y11/NR1BEG0", - "INT_L_X0Y12/LV_L0", - "INT_L_X0Y12/NR1END0", - "INT_L_X0Y13/LV_L1", - "INT_L_X0Y14/LV_L2", - "INT_L_X0Y15/LV_L3", - "INT_L_X0Y16/LV_L4", - "INT_L_X0Y17/LV_L5", - "INT_L_X0Y18/LV_L6", - "INT_L_X0Y19/LV_L7", - "INT_L_X0Y20/LV_L8", - "INT_L_X0Y21/LV_L9", - "INT_L_X0Y22/LV_L10", - "INT_L_X0Y23/LV_L11", - "INT_L_X0Y24/LV_L12", - "INT_L_X0Y25/LV_L13", - "INT_L_X0Y26/LV_L14", - "INT_L_X0Y27/LV_L15", - "INT_L_X0Y28/LV_L16", - "INT_L_X0Y29/LV_L17", - "INT_L_X0Y30/LV_L0", - "INT_L_X0Y30/LV_L18", - "INT_L_X0Y31/LV_L1", - "INT_L_X0Y32/LV_L2", - "INT_L_X0Y33/LV_L3", - "INT_L_X0Y34/LV_L4", - "INT_L_X0Y35/LV_L5", - "INT_L_X0Y36/LV_L6", - "INT_L_X0Y37/LV_L7", - "INT_L_X0Y38/LV_L8", - "INT_L_X0Y39/LV_L9", - "INT_L_X0Y40/LV_L10", - "INT_L_X0Y41/LV_L11", - "INT_L_X0Y42/LV_L12", - "INT_L_X0Y43/LV_L13", - "INT_L_X0Y44/LV_L14", - "INT_L_X0Y45/LV_L15", - "INT_L_X0Y46/LV_L16", - "INT_L_X0Y47/LV_L17", - "INT_L_X0Y48/LV_L0", - "INT_L_X0Y48/LV_L18", - "INT_L_X0Y49/LV_L1", - "INT_L_X0Y50/LV_L2", - "INT_L_X0Y51/LV_L3", - "INT_L_X0Y52/LV_L4", - "INT_L_X0Y53/LV_L5", - "INT_L_X0Y54/LV_L6", - "INT_L_X0Y55/LV_L7", - "INT_L_X0Y56/LV_L8", - "INT_L_X0Y57/LV_L9", - "INT_L_X0Y58/LV_L10", - "INT_L_X0Y59/LV_L11", - "INT_L_X0Y60/LV_L12", - "INT_L_X0Y61/LV_L13", - "INT_L_X0Y62/LV_L14", - "INT_L_X0Y63/LV_L15", - "INT_L_X0Y64/LV_L16", - "INT_L_X0Y65/LV_L17", - "INT_L_X0Y66/LV_L0", - "INT_L_X0Y66/LV_L18", - "INT_L_X0Y67/LV_L1", - "INT_L_X0Y68/LV_L2", - "INT_L_X0Y69/LV_L3", - "INT_L_X0Y70/LV_L4", - "INT_L_X0Y71/LV_L5", - "INT_L_X0Y72/LV_L6", - "INT_L_X0Y73/LV_L7", - "INT_L_X0Y74/LV_L8", - "INT_L_X0Y75/LV_L9", - "INT_L_X0Y76/LV_L10", - "INT_L_X0Y77/LV_L11", - "INT_L_X0Y78/LV_L12", - "INT_L_X0Y79/LV_L13", - "INT_L_X0Y80/LV_L14", - "INT_L_X0Y81/LV_L15", - "INT_L_X0Y82/LV_L16", - "INT_L_X0Y83/LV_L17", - "INT_L_X0Y84/LVB_L0", - "INT_L_X0Y84/LV_L18", - "INT_L_X0Y85/LVB_L1", - "INT_L_X0Y86/LVB_L2", - "INT_L_X0Y87/LVB_L3", - "INT_L_X0Y88/LVB_L4", - "INT_L_X0Y89/LVB_L5", - "INT_L_X0Y90/LVB_L6", - "INT_L_X0Y91/LVB_L7", - "INT_L_X0Y92/LVB_L8", - "INT_L_X0Y93/LVB_L9", - "INT_L_X0Y94/LVB_L10", - "INT_L_X0Y95/LVB_L11", - "INT_L_X0Y96/LVB_L12", - "INT_L_X0Y96/NN6BEG2", - "INT_L_X0Y97/NN6A2", - "INT_L_X0Y98/NN6B2", - "INT_L_X0Y99/NN6C2", - "INT_L_X0Y100/NN6D2", - "INT_L_X0Y101/NN6E2", - "INT_L_X0Y102/EE2BEG2", - "INT_L_X0Y102/NN6END2", - "INT_R_X1Y102/EE2A2", - "IO_INT_INTERFACE_L_X0Y11/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y11/INT_INTERFACE_LOGIC_OUTS_L_B18", - "LIOB33_X0Y11/IOB_IBUF1", - "LIOI3_X0Y11/IOI_ILOGIC1_O", - "LIOI3_X0Y11/IOI_LOGIC_OUTS18_0", - "LIOI3_X0Y11/LIOI_I1", - "LIOI3_X0Y11/LIOI_IBUF1", - "LIOI3_X0Y11/LIOI_ILOGIC1_D", - "L_TERM_INT_X2Y12/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y107/VBRK_EE2A2" - ] - }, - { - "name": "din[1]", - "node": "INT_L_X0Y104/EE2BEG2", - "pin": "V16", - "wire": "VBRK_X9Y109/VBRK_EE2A2", - "wires_outside_roi": [ - "BRKH_INT_X0Y49/BRKH_INT_L_LV0", - "BRKH_INT_X0Y99/BRKH_INT_NN6B2", - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_3", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_4", - "HCLK_L_X4Y26/HCLK_LV11", - "HCLK_L_X4Y78/HCLK_LV7", - "INT_INTERFACE_R_X1Y104/INT_INTERFACE_EE2A2", - "INT_L_X0Y12/LOGIC_OUTS_L18", - "INT_L_X0Y12/NR1BEG0", - "INT_L_X0Y13/LV_L0", - "INT_L_X0Y13/NR1END0", - "INT_L_X0Y14/LV_L1", - "INT_L_X0Y15/LV_L2", - "INT_L_X0Y16/LV_L3", - "INT_L_X0Y17/LV_L4", - "INT_L_X0Y18/LV_L5", - "INT_L_X0Y19/LV_L6", - "INT_L_X0Y20/LV_L7", - "INT_L_X0Y21/LV_L8", - "INT_L_X0Y22/LV_L9", - "INT_L_X0Y23/LV_L10", - "INT_L_X0Y24/LV_L11", - "INT_L_X0Y25/LV_L12", - "INT_L_X0Y26/LV_L13", - "INT_L_X0Y27/LV_L14", - "INT_L_X0Y28/LV_L15", - "INT_L_X0Y29/LV_L16", - "INT_L_X0Y30/LV_L17", - "INT_L_X0Y31/LV_L0", - "INT_L_X0Y31/LV_L18", - "INT_L_X0Y32/LV_L1", - "INT_L_X0Y33/LV_L2", - "INT_L_X0Y34/LV_L3", - "INT_L_X0Y35/LV_L4", - "INT_L_X0Y36/LV_L5", - "INT_L_X0Y37/LV_L6", - "INT_L_X0Y38/LV_L7", - "INT_L_X0Y39/LV_L8", - "INT_L_X0Y40/LV_L9", - "INT_L_X0Y41/LV_L10", - "INT_L_X0Y42/LV_L11", - "INT_L_X0Y43/LV_L12", - "INT_L_X0Y44/LV_L13", - "INT_L_X0Y45/LV_L14", - "INT_L_X0Y46/LV_L15", - "INT_L_X0Y47/LV_L16", - "INT_L_X0Y48/LV_L17", - "INT_L_X0Y49/LV_L0", - "INT_L_X0Y49/LV_L18", - "INT_L_X0Y50/LV_L1", - "INT_L_X0Y51/LV_L2", - "INT_L_X0Y52/LV_L3", - "INT_L_X0Y53/LV_L4", - "INT_L_X0Y54/LV_L5", - "INT_L_X0Y55/LV_L6", - "INT_L_X0Y56/LV_L7", - "INT_L_X0Y57/LV_L8", - "INT_L_X0Y58/LV_L9", - "INT_L_X0Y59/LV_L10", - "INT_L_X0Y60/LV_L11", - "INT_L_X0Y61/LV_L12", - "INT_L_X0Y62/LV_L13", - "INT_L_X0Y63/LV_L14", - "INT_L_X0Y64/LV_L15", - "INT_L_X0Y65/LV_L16", - "INT_L_X0Y66/LV_L17", - "INT_L_X0Y67/LV_L0", - "INT_L_X0Y67/LV_L18", - "INT_L_X0Y68/LV_L1", - "INT_L_X0Y69/LV_L2", - "INT_L_X0Y70/LV_L3", - "INT_L_X0Y71/LV_L4", - "INT_L_X0Y72/LV_L5", - "INT_L_X0Y73/LV_L6", - "INT_L_X0Y74/LV_L7", - "INT_L_X0Y75/LV_L8", - "INT_L_X0Y76/LV_L9", - "INT_L_X0Y77/LV_L10", - "INT_L_X0Y78/LV_L11", - "INT_L_X0Y79/LV_L12", - "INT_L_X0Y80/LV_L13", - "INT_L_X0Y81/LV_L14", - "INT_L_X0Y82/LV_L15", - "INT_L_X0Y83/LV_L16", - "INT_L_X0Y84/LV_L17", - "INT_L_X0Y85/LVB_L0", - "INT_L_X0Y85/LV_L18", - "INT_L_X0Y86/LVB_L1", - "INT_L_X0Y87/LVB_L2", - "INT_L_X0Y88/LVB_L3", - "INT_L_X0Y89/LVB_L4", - "INT_L_X0Y90/LVB_L5", - "INT_L_X0Y91/LVB_L6", - "INT_L_X0Y92/LVB_L7", - "INT_L_X0Y93/LVB_L8", - "INT_L_X0Y94/LVB_L9", - "INT_L_X0Y95/LVB_L10", - "INT_L_X0Y96/LVB_L11", - "INT_L_X0Y97/LVB_L12", - "INT_L_X0Y97/NN6BEG2", - "INT_L_X0Y98/NN6A2", - "INT_L_X0Y99/NN6B2", - "INT_L_X0Y100/NN6C2", - "INT_L_X0Y101/NN6D2", - "INT_L_X0Y102/NN6E2", - "INT_L_X0Y103/NN6END2", - "INT_L_X0Y103/NR1BEG2", - "INT_L_X0Y104/EE2BEG2", - "INT_L_X0Y104/NR1END2", - "INT_R_X1Y104/EE2A2", - "IO_INT_INTERFACE_L_X0Y12/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y12/INT_INTERFACE_LOGIC_OUTS_L_B18", - "LIOB33_X0Y11/IOB_IBUF0", - "LIOI3_X0Y11/IOI_ILOGIC0_O", - "LIOI3_X0Y11/IOI_LOGIC_OUTS18_1", - "LIOI3_X0Y11/LIOI_I0", - "LIOI3_X0Y11/LIOI_IBUF0", - "LIOI3_X0Y11/LIOI_ILOGIC0_D", - "L_TERM_INT_X2Y13/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y109/VBRK_EE2A2" - ] - }, - { - "name": "din[2]", - "node": "INT_L_X0Y106/EE2BEG2", - "pin": "W16", - "wire": "VBRK_X9Y111/VBRK_EE2A2", - "wires_outside_roi": [ - "BRKH_INT_X0Y49/BRKH_INT_L_LV2", - "BRKH_INT_X0Y99/BRKH_INT_L_LV16", - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_5", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_6", - "HCLK_L_X4Y26/HCLK_LV13", - "HCLK_L_X4Y78/HCLK_LV9", - "INT_INTERFACE_R_X1Y106/INT_INTERFACE_EE2A2", - "INT_L_X0Y10/LOGIC_OUTS_L18", - "INT_L_X0Y10/NR1BEG0", - "INT_L_X0Y11/LV_L0", - "INT_L_X0Y11/NR1END0", - "INT_L_X0Y12/LV_L1", - "INT_L_X0Y13/LV_L2", - "INT_L_X0Y14/LV_L3", - "INT_L_X0Y15/LV_L4", - "INT_L_X0Y16/LV_L5", - "INT_L_X0Y17/LV_L6", - "INT_L_X0Y18/LV_L7", - "INT_L_X0Y19/LV_L8", - "INT_L_X0Y20/LV_L9", - "INT_L_X0Y21/LV_L10", - "INT_L_X0Y22/LV_L11", - "INT_L_X0Y23/LV_L12", - "INT_L_X0Y24/LV_L13", - "INT_L_X0Y25/LV_L14", - "INT_L_X0Y26/LV_L15", - "INT_L_X0Y27/LV_L16", - "INT_L_X0Y28/LV_L17", - "INT_L_X0Y29/LV_L0", - "INT_L_X0Y29/LV_L18", - "INT_L_X0Y30/LV_L1", - "INT_L_X0Y31/LV_L2", - "INT_L_X0Y32/LV_L3", - "INT_L_X0Y33/LV_L4", - "INT_L_X0Y34/LV_L5", - "INT_L_X0Y35/LV_L6", - "INT_L_X0Y36/LV_L7", - "INT_L_X0Y37/LV_L8", - "INT_L_X0Y38/LV_L9", - "INT_L_X0Y39/LV_L10", - "INT_L_X0Y40/LV_L11", - "INT_L_X0Y41/LV_L12", - "INT_L_X0Y42/LV_L13", - "INT_L_X0Y43/LV_L14", - "INT_L_X0Y44/LV_L15", - "INT_L_X0Y45/LV_L16", - "INT_L_X0Y46/LV_L17", - "INT_L_X0Y47/LV_L0", - "INT_L_X0Y47/LV_L18", - "INT_L_X0Y48/LV_L1", - "INT_L_X0Y49/LV_L2", - "INT_L_X0Y50/LV_L3", - "INT_L_X0Y51/LV_L4", - "INT_L_X0Y52/LV_L5", - "INT_L_X0Y53/LV_L6", - "INT_L_X0Y54/LV_L7", - "INT_L_X0Y55/LV_L8", - "INT_L_X0Y56/LV_L9", - "INT_L_X0Y57/LV_L10", - "INT_L_X0Y58/LV_L11", - "INT_L_X0Y59/LV_L12", - "INT_L_X0Y60/LV_L13", - "INT_L_X0Y61/LV_L14", - "INT_L_X0Y62/LV_L15", - "INT_L_X0Y63/LV_L16", - "INT_L_X0Y64/LV_L17", - "INT_L_X0Y65/LV_L0", - "INT_L_X0Y65/LV_L18", - "INT_L_X0Y66/LV_L1", - "INT_L_X0Y67/LV_L2", - "INT_L_X0Y68/LV_L3", - "INT_L_X0Y69/LV_L4", - "INT_L_X0Y70/LV_L5", - "INT_L_X0Y71/LV_L6", - "INT_L_X0Y72/LV_L7", - "INT_L_X0Y73/LV_L8", - "INT_L_X0Y74/LV_L9", - "INT_L_X0Y75/LV_L10", - "INT_L_X0Y76/LV_L11", - "INT_L_X0Y77/LV_L12", - "INT_L_X0Y78/LV_L13", - "INT_L_X0Y79/LV_L14", - "INT_L_X0Y80/LV_L15", - "INT_L_X0Y81/LV_L16", - "INT_L_X0Y82/LV_L17", - "INT_L_X0Y83/LV_L0", - "INT_L_X0Y83/LV_L18", - "INT_L_X0Y84/LV_L1", - "INT_L_X0Y85/LV_L2", - "INT_L_X0Y86/LV_L3", - "INT_L_X0Y87/LV_L4", - "INT_L_X0Y88/LV_L5", - "INT_L_X0Y89/LV_L6", - "INT_L_X0Y90/LV_L7", - "INT_L_X0Y91/LV_L8", - "INT_L_X0Y92/LV_L9", - "INT_L_X0Y93/LV_L10", - "INT_L_X0Y94/LV_L11", - "INT_L_X0Y95/LV_L12", - "INT_L_X0Y96/LV_L13", - "INT_L_X0Y97/LV_L14", - "INT_L_X0Y98/LV_L15", - "INT_L_X0Y99/LV_L16", - "INT_L_X0Y100/LV_L17", - "INT_L_X0Y101/LV_L18", - "INT_L_X0Y101/NN6BEG3", - "INT_L_X0Y102/NN6A3", - "INT_L_X0Y103/NN6B3", - "INT_L_X0Y104/NN6C3", - "INT_L_X0Y105/NN6D3", - "INT_L_X0Y106/EE2BEG2", - "INT_L_X0Y106/EL1END2", - "INT_L_X0Y106/NN6E3", - "INT_L_X0Y106/SR1END3", - "INT_L_X0Y106/WL1BEG2", - "INT_L_X0Y107/NN6END3", - "INT_L_X0Y107/SR1BEG3", - "INT_L_X0Y107/SR1END_N3_3", - "INT_R_X1Y106/EE2A2", - "IO_INT_INTERFACE_L_X0Y10/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y10/INT_INTERFACE_LOGIC_OUTS_L_B18", - "IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_EL1BEG2", - "IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_WL1END2", - "LIOB33_X0Y9/IOB_IBUF0", - "LIOI3_X0Y9/IOI_ILOGIC0_O", - "LIOI3_X0Y9/IOI_LOGIC_OUTS18_1", - "LIOI3_X0Y9/LIOI_I0", - "LIOI3_X0Y9/LIOI_IBUF0", - "LIOI3_X0Y9/LIOI_ILOGIC0_D", - "L_TERM_INT_X2Y11/TERM_INT_LOGIC_OUTS_L_B18", - "L_TERM_INT_X2Y111/L_TERM_INT_WL1BEG2", - "VBRK_X9Y111/VBRK_EE2A2" - ] - }, - { - "name": "din[3]", - "node": "INT_L_X0Y108/EE2BEG2", - "pin": "W17", - "wire": "VBRK_X9Y113/VBRK_EE2A2", - "wires_outside_roi": [ - "BRKH_INT_X0Y49/BRKH_INT_L_LV3", - "BRKH_INT_X0Y99/BRKH_INT_L_LV17", - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_8", - "HCLK_L_X4Y26/HCLK_LV14", - "HCLK_L_X4Y78/HCLK_LV10", - "INT_INTERFACE_R_X1Y108/INT_INTERFACE_EE2A2", - "INT_L_X0Y9/LOGIC_OUTS_L18", - "INT_L_X0Y9/NR1BEG0", - "INT_L_X0Y10/LV_L0", - "INT_L_X0Y10/NR1END0", - "INT_L_X0Y11/LV_L1", - "INT_L_X0Y12/LV_L2", - "INT_L_X0Y13/LV_L3", - "INT_L_X0Y14/LV_L4", - "INT_L_X0Y15/LV_L5", - "INT_L_X0Y16/LV_L6", - "INT_L_X0Y17/LV_L7", - "INT_L_X0Y18/LV_L8", - "INT_L_X0Y19/LV_L9", - "INT_L_X0Y20/LV_L10", - "INT_L_X0Y21/LV_L11", - "INT_L_X0Y22/LV_L12", - "INT_L_X0Y23/LV_L13", - "INT_L_X0Y24/LV_L14", - "INT_L_X0Y25/LV_L15", - "INT_L_X0Y26/LV_L16", - "INT_L_X0Y27/LV_L17", - "INT_L_X0Y28/LV_L0", - "INT_L_X0Y28/LV_L18", - "INT_L_X0Y29/LV_L1", - "INT_L_X0Y30/LV_L2", - "INT_L_X0Y31/LV_L3", - "INT_L_X0Y32/LV_L4", - "INT_L_X0Y33/LV_L5", - "INT_L_X0Y34/LV_L6", - "INT_L_X0Y35/LV_L7", - "INT_L_X0Y36/LV_L8", - "INT_L_X0Y37/LV_L9", - "INT_L_X0Y38/LV_L10", - "INT_L_X0Y39/LV_L11", - "INT_L_X0Y40/LV_L12", - "INT_L_X0Y41/LV_L13", - "INT_L_X0Y42/LV_L14", - "INT_L_X0Y43/LV_L15", - "INT_L_X0Y44/LV_L16", - "INT_L_X0Y45/LV_L17", - "INT_L_X0Y46/LV_L0", - "INT_L_X0Y46/LV_L18", - "INT_L_X0Y47/LV_L1", - "INT_L_X0Y48/LV_L2", - "INT_L_X0Y49/LV_L3", - "INT_L_X0Y50/LV_L4", - "INT_L_X0Y51/LV_L5", - "INT_L_X0Y52/LV_L6", - "INT_L_X0Y53/LV_L7", - "INT_L_X0Y54/LV_L8", - "INT_L_X0Y55/LV_L9", - "INT_L_X0Y56/LV_L10", - "INT_L_X0Y57/LV_L11", - "INT_L_X0Y58/LV_L12", - "INT_L_X0Y59/LV_L13", - "INT_L_X0Y60/LV_L14", - "INT_L_X0Y61/LV_L15", - "INT_L_X0Y62/LV_L16", - "INT_L_X0Y63/LV_L17", - "INT_L_X0Y64/LV_L0", - "INT_L_X0Y64/LV_L18", - "INT_L_X0Y65/LV_L1", - "INT_L_X0Y66/LV_L2", - "INT_L_X0Y67/LV_L3", - "INT_L_X0Y68/LV_L4", - "INT_L_X0Y69/LV_L5", - "INT_L_X0Y70/LV_L6", - "INT_L_X0Y71/LV_L7", - "INT_L_X0Y72/LV_L8", - "INT_L_X0Y73/LV_L9", - "INT_L_X0Y74/LV_L10", - "INT_L_X0Y75/LV_L11", - "INT_L_X0Y76/LV_L12", - "INT_L_X0Y77/LV_L13", - "INT_L_X0Y78/LV_L14", - "INT_L_X0Y79/LV_L15", - "INT_L_X0Y80/LV_L16", - "INT_L_X0Y81/LV_L17", - "INT_L_X0Y82/LV_L0", - "INT_L_X0Y82/LV_L18", - "INT_L_X0Y83/LV_L1", - "INT_L_X0Y84/LV_L2", - "INT_L_X0Y85/LV_L3", - "INT_L_X0Y86/LV_L4", - "INT_L_X0Y87/LV_L5", - "INT_L_X0Y88/LV_L6", - "INT_L_X0Y89/LV_L7", - "INT_L_X0Y90/LV_L8", - "INT_L_X0Y91/LV_L9", - "INT_L_X0Y92/LV_L10", - "INT_L_X0Y93/LV_L11", - "INT_L_X0Y94/LV_L12", - "INT_L_X0Y95/LV_L13", - "INT_L_X0Y96/LV_L14", - "INT_L_X0Y97/LV_L15", - "INT_L_X0Y98/LV_L16", - "INT_L_X0Y99/LV_L17", - "INT_L_X0Y100/LV_L18", - "INT_L_X0Y100/NN6BEG3", - "INT_L_X0Y101/NN6A3", - "INT_L_X0Y102/NN6B3", - "INT_L_X0Y103/NN6C3", - "INT_L_X0Y104/NN6D3", - "INT_L_X0Y105/NN6E3", - "INT_L_X0Y106/NN6END3", - "INT_L_X0Y106/NR1BEG3", - "INT_L_X0Y107/NL1BEG2", - "INT_L_X0Y107/NR1END3", - "INT_L_X0Y108/EE2BEG2", - "INT_L_X0Y108/NL1END2", - "INT_R_X1Y108/EE2A2", - "IO_INT_INTERFACE_L_X0Y9/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y9/INT_INTERFACE_LOGIC_OUTS_L_B18", - "LIOB33_X0Y9/IOB_IBUF1", - "LIOI3_X0Y9/IOI_ILOGIC1_O", - "LIOI3_X0Y9/IOI_LOGIC_OUTS18_0", - "LIOI3_X0Y9/LIOI_I1", - "LIOI3_X0Y9/LIOI_IBUF1", - "LIOI3_X0Y9/LIOI_ILOGIC1_D", - "L_TERM_INT_X2Y10/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y113/VBRK_EE2A2" - ] - }, - { - "name": "din[4]", - "node": "INT_L_X0Y110/EE2BEG2", - "pin": "W15", - "wire": "VBRK_X9Y115/VBRK_EE2A2", - "wires_outside_roi": [ - "BRKH_INT_X0Y49/BRKH_INT_L_LV5", - "BRKH_INT_X0Y99/BRKH_INT_LVB_L8", - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_9", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_10", - "HCLK_L_X4Y26/HCLK_LV16", - "HCLK_L_X4Y78/HCLK_LV12", - "INT_INTERFACE_R_X1Y110/INT_INTERFACE_EE2A2", - "INT_L_X0Y7/LOGIC_OUTS_L18", - "INT_L_X0Y7/NR1BEG0", - "INT_L_X0Y8/LV_L0", - "INT_L_X0Y8/NR1END0", - "INT_L_X0Y9/LV_L1", - "INT_L_X0Y10/LV_L2", - "INT_L_X0Y11/LV_L3", - "INT_L_X0Y12/LV_L4", - "INT_L_X0Y13/LV_L5", - "INT_L_X0Y14/LV_L6", - "INT_L_X0Y15/LV_L7", - "INT_L_X0Y16/LV_L8", - "INT_L_X0Y17/LV_L9", - "INT_L_X0Y18/LV_L10", - "INT_L_X0Y19/LV_L11", - "INT_L_X0Y20/LV_L12", - "INT_L_X0Y21/LV_L13", - "INT_L_X0Y22/LV_L14", - "INT_L_X0Y23/LV_L15", - "INT_L_X0Y24/LV_L16", - "INT_L_X0Y25/LV_L17", - "INT_L_X0Y26/LV_L0", - "INT_L_X0Y26/LV_L18", - "INT_L_X0Y27/LV_L1", - "INT_L_X0Y28/LV_L2", - "INT_L_X0Y29/LV_L3", - "INT_L_X0Y30/LV_L4", - "INT_L_X0Y31/LV_L5", - "INT_L_X0Y32/LV_L6", - "INT_L_X0Y33/LV_L7", - "INT_L_X0Y34/LV_L8", - "INT_L_X0Y35/LV_L9", - "INT_L_X0Y36/LV_L10", - "INT_L_X0Y37/LV_L11", - "INT_L_X0Y38/LV_L12", - "INT_L_X0Y39/LV_L13", - "INT_L_X0Y40/LV_L14", - "INT_L_X0Y41/LV_L15", - "INT_L_X0Y42/LV_L16", - "INT_L_X0Y43/LV_L17", - "INT_L_X0Y44/LV_L0", - "INT_L_X0Y44/LV_L18", - "INT_L_X0Y45/LV_L1", - "INT_L_X0Y46/LV_L2", - "INT_L_X0Y47/LV_L3", - "INT_L_X0Y48/LV_L4", - "INT_L_X0Y49/LV_L5", - "INT_L_X0Y50/LV_L6", - "INT_L_X0Y51/LV_L7", - "INT_L_X0Y52/LV_L8", - "INT_L_X0Y53/LV_L9", - "INT_L_X0Y54/LV_L10", - "INT_L_X0Y55/LV_L11", - "INT_L_X0Y56/LV_L12", - "INT_L_X0Y57/LV_L13", - "INT_L_X0Y58/LV_L14", - "INT_L_X0Y59/LV_L15", - "INT_L_X0Y60/LV_L16", - "INT_L_X0Y61/LV_L17", - "INT_L_X0Y62/LV_L0", - "INT_L_X0Y62/LV_L18", - "INT_L_X0Y63/LV_L1", - "INT_L_X0Y64/LV_L2", - "INT_L_X0Y65/LV_L3", - "INT_L_X0Y66/LV_L4", - "INT_L_X0Y67/LV_L5", - "INT_L_X0Y68/LV_L6", - "INT_L_X0Y69/LV_L7", - "INT_L_X0Y70/LV_L8", - "INT_L_X0Y71/LV_L9", - "INT_L_X0Y72/LV_L10", - "INT_L_X0Y73/LV_L11", - "INT_L_X0Y74/LV_L12", - "INT_L_X0Y75/LV_L13", - "INT_L_X0Y76/LV_L14", - "INT_L_X0Y77/LV_L15", - "INT_L_X0Y78/LV_L16", - "INT_L_X0Y79/LV_L17", - "INT_L_X0Y80/LVB_L0", - "INT_L_X0Y80/LV_L18", - "INT_L_X0Y81/LVB_L1", - "INT_L_X0Y82/LVB_L2", - "INT_L_X0Y83/LVB_L3", - "INT_L_X0Y84/LVB_L4", - "INT_L_X0Y85/LVB_L5", - "INT_L_X0Y86/LVB_L6", - "INT_L_X0Y87/LVB_L7", - "INT_L_X0Y88/LVB_L8", - "INT_L_X0Y89/LVB_L9", - "INT_L_X0Y90/LVB_L10", - "INT_L_X0Y91/LVB_L11", - "INT_L_X0Y92/LVB_L0", - "INT_L_X0Y92/LVB_L12", - "INT_L_X0Y93/LVB_L1", - "INT_L_X0Y94/LVB_L2", - "INT_L_X0Y95/LVB_L3", - "INT_L_X0Y96/LVB_L4", - "INT_L_X0Y97/LVB_L5", - "INT_L_X0Y98/LVB_L6", - "INT_L_X0Y99/LVB_L7", - "INT_L_X0Y100/LVB_L8", - "INT_L_X0Y101/LVB_L9", - "INT_L_X0Y102/LVB_L10", - "INT_L_X0Y103/LVB_L11", - "INT_L_X0Y104/LVB_L12", - "INT_L_X0Y104/NN6BEG2", - "INT_L_X0Y105/NN6A2", - "INT_L_X0Y106/NN6B2", - "INT_L_X0Y107/NN6C2", - "INT_L_X0Y108/NN6D2", - "INT_L_X0Y109/NN6E2", - "INT_L_X0Y110/EE2BEG2", - "INT_L_X0Y110/NN6END2", - "INT_R_X1Y110/EE2A2", - "IO_INT_INTERFACE_L_X0Y7/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y7/INT_INTERFACE_LOGIC_OUTS_L_B18", - "LIOB33_X0Y7/IOB_IBUF1", - "LIOI3_TBYTESRC_X0Y7/IOI_ILOGIC1_O", - "LIOI3_TBYTESRC_X0Y7/IOI_LOGIC_OUTS18_0", - "LIOI3_TBYTESRC_X0Y7/LIOI_I1", - "LIOI3_TBYTESRC_X0Y7/LIOI_IBUF1", - "LIOI3_TBYTESRC_X0Y7/LIOI_ILOGIC1_D", - "L_TERM_INT_X2Y8/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y115/VBRK_EE2A2" - ] - }, - { - "name": "din[5]", - "node": "INT_L_X0Y112/EE2BEG2", - "pin": "V15", - "wire": "VBRK_X9Y117/VBRK_EE2A2", - "wires_outside_roi": [ - "BRKH_INT_X0Y49/BRKH_INT_L_LV4", - "BRKH_INT_X0Y99/BRKH_INT_NN6BEG3", - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_12", - "HCLK_L_X4Y26/HCLK_LV15", - "HCLK_L_X4Y78/HCLK_LV11", - "INT_INTERFACE_R_X1Y112/INT_INTERFACE_EE2A2", - "INT_L_X0Y8/LOGIC_OUTS_L18", - "INT_L_X0Y8/NR1BEG0", - "INT_L_X0Y9/LV_L0", - "INT_L_X0Y9/NR1END0", - "INT_L_X0Y10/LV_L1", - "INT_L_X0Y11/LV_L2", - "INT_L_X0Y12/LV_L3", - "INT_L_X0Y13/LV_L4", - "INT_L_X0Y14/LV_L5", - "INT_L_X0Y15/LV_L6", - "INT_L_X0Y16/LV_L7", - "INT_L_X0Y17/LV_L8", - "INT_L_X0Y18/LV_L9", - "INT_L_X0Y19/LV_L10", - "INT_L_X0Y20/LV_L11", - "INT_L_X0Y21/LV_L12", - "INT_L_X0Y22/LV_L13", - "INT_L_X0Y23/LV_L14", - "INT_L_X0Y24/LV_L15", - "INT_L_X0Y25/LV_L16", - "INT_L_X0Y26/LV_L17", - "INT_L_X0Y27/LV_L0", - "INT_L_X0Y27/LV_L18", - "INT_L_X0Y28/LV_L1", - "INT_L_X0Y29/LV_L2", - "INT_L_X0Y30/LV_L3", - "INT_L_X0Y31/LV_L4", - "INT_L_X0Y32/LV_L5", - "INT_L_X0Y33/LV_L6", - "INT_L_X0Y34/LV_L7", - "INT_L_X0Y35/LV_L8", - "INT_L_X0Y36/LV_L9", - "INT_L_X0Y37/LV_L10", - "INT_L_X0Y38/LV_L11", - "INT_L_X0Y39/LV_L12", - "INT_L_X0Y40/LV_L13", - "INT_L_X0Y41/LV_L14", - "INT_L_X0Y42/LV_L15", - "INT_L_X0Y43/LV_L16", - "INT_L_X0Y44/LV_L17", - "INT_L_X0Y45/LV_L0", - "INT_L_X0Y45/LV_L18", - "INT_L_X0Y46/LV_L1", - "INT_L_X0Y47/LV_L2", - "INT_L_X0Y48/LV_L3", - "INT_L_X0Y49/LV_L4", - "INT_L_X0Y50/LV_L5", - "INT_L_X0Y51/LV_L6", - "INT_L_X0Y52/LV_L7", - "INT_L_X0Y53/LV_L8", - "INT_L_X0Y54/LV_L9", - "INT_L_X0Y55/LV_L10", - "INT_L_X0Y56/LV_L11", - "INT_L_X0Y57/LV_L12", - "INT_L_X0Y58/LV_L13", - "INT_L_X0Y59/LV_L14", - "INT_L_X0Y60/LV_L15", - "INT_L_X0Y61/LV_L16", - "INT_L_X0Y62/LV_L17", - "INT_L_X0Y63/LV_L0", - "INT_L_X0Y63/LV_L18", - "INT_L_X0Y64/LV_L1", - "INT_L_X0Y65/LV_L2", - "INT_L_X0Y66/LV_L3", - "INT_L_X0Y67/LV_L4", - "INT_L_X0Y68/LV_L5", - "INT_L_X0Y69/LV_L6", - "INT_L_X0Y70/LV_L7", - "INT_L_X0Y71/LV_L8", - "INT_L_X0Y72/LV_L9", - "INT_L_X0Y73/LV_L10", - "INT_L_X0Y74/LV_L11", - "INT_L_X0Y75/LV_L12", - "INT_L_X0Y76/LV_L13", - "INT_L_X0Y77/LV_L14", - "INT_L_X0Y78/LV_L15", - "INT_L_X0Y79/LV_L16", - "INT_L_X0Y80/LV_L17", - "INT_L_X0Y81/LV_L0", - "INT_L_X0Y81/LV_L18", - "INT_L_X0Y82/LV_L1", - "INT_L_X0Y83/LV_L2", - "INT_L_X0Y84/LV_L3", - "INT_L_X0Y85/LV_L4", - "INT_L_X0Y86/LV_L5", - "INT_L_X0Y87/LV_L6", - "INT_L_X0Y88/LV_L7", - "INT_L_X0Y89/LV_L8", - "INT_L_X0Y90/LV_L9", - "INT_L_X0Y91/LV_L10", - "INT_L_X0Y92/LV_L11", - "INT_L_X0Y93/LV_L12", - "INT_L_X0Y94/LV_L13", - "INT_L_X0Y95/LV_L14", - "INT_L_X0Y96/LV_L15", - "INT_L_X0Y97/LV_L16", - "INT_L_X0Y98/LV_L17", - "INT_L_X0Y99/LV_L18", - "INT_L_X0Y99/NN6BEG3", - "INT_L_X0Y100/NN6A3", - "INT_L_X0Y101/NN6B3", - "INT_L_X0Y102/NN6C3", - "INT_L_X0Y103/NN6D3", - "INT_L_X0Y104/NN6E3", - "INT_L_X0Y105/NN6BEG3", - "INT_L_X0Y105/NN6END3", - "INT_L_X0Y106/NN6A3", - "INT_L_X0Y107/NN6B3", - "INT_L_X0Y108/NN6C3", - "INT_L_X0Y109/NN6D3", - "INT_L_X0Y110/NN6E3", - "INT_L_X0Y111/NL1BEG2", - "INT_L_X0Y111/NN6END3", - "INT_L_X0Y112/EE2BEG2", - "INT_L_X0Y112/NL1END2", - "INT_R_X1Y112/EE2A2", - "IO_INT_INTERFACE_L_X0Y8/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y8/INT_INTERFACE_LOGIC_OUTS_L_B18", - "LIOB33_X0Y7/IOB_IBUF0", - "LIOI3_TBYTESRC_X0Y7/IOI_ILOGIC0_O", - "LIOI3_TBYTESRC_X0Y7/IOI_LOGIC_OUTS18_1", - "LIOI3_TBYTESRC_X0Y7/LIOI_I0", - "LIOI3_TBYTESRC_X0Y7/LIOI_IBUF0", - "LIOI3_TBYTESRC_X0Y7/LIOI_ILOGIC0_D", - "L_TERM_INT_X2Y9/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y117/VBRK_EE2A2" - ] - }, - { - "name": "din[6]", - "node": "INT_L_X0Y114/EE2BEG2", - "pin": "W14", - "wire": "VBRK_X9Y119/VBRK_EE2A2", - "wires_outside_roi": [ - "BRKH_INT_X0Y49/BRKH_INT_L_LV7", - "BRKH_INT_X0Y99/BRKH_INT_LVB_L4", - "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_1", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_14", - "HCLK_L_X4Y26/HCLK_LV0", - "HCLK_L_X4Y78/HCLK_LV14", - "INT_INTERFACE_R_X1Y114/INT_INTERFACE_EE2A2", - "INT_L_X0Y5/LOGIC_OUTS_L18", - "INT_L_X0Y5/NR1BEG0", - "INT_L_X0Y6/LV_L0", - "INT_L_X0Y6/NR1END0", - "INT_L_X0Y7/LV_L1", - "INT_L_X0Y8/LV_L2", - "INT_L_X0Y9/LV_L3", - "INT_L_X0Y10/LV_L4", - "INT_L_X0Y11/LV_L5", - "INT_L_X0Y12/LV_L6", - "INT_L_X0Y13/LV_L7", - "INT_L_X0Y14/LV_L8", - "INT_L_X0Y15/LV_L9", - "INT_L_X0Y16/LV_L10", - "INT_L_X0Y17/LV_L11", - "INT_L_X0Y18/LV_L12", - "INT_L_X0Y19/LV_L13", - "INT_L_X0Y20/LV_L14", - "INT_L_X0Y21/LV_L15", - "INT_L_X0Y22/LV_L16", - "INT_L_X0Y23/LV_L17", - "INT_L_X0Y24/LV_L0", - "INT_L_X0Y24/LV_L18", - "INT_L_X0Y25/LV_L1", - "INT_L_X0Y26/LV_L2", - "INT_L_X0Y27/LV_L3", - "INT_L_X0Y28/LV_L4", - "INT_L_X0Y29/LV_L5", - "INT_L_X0Y30/LV_L6", - "INT_L_X0Y31/LV_L7", - "INT_L_X0Y32/LV_L8", - "INT_L_X0Y33/LV_L9", - "INT_L_X0Y34/LV_L10", - "INT_L_X0Y35/LV_L11", - "INT_L_X0Y36/LV_L12", - "INT_L_X0Y37/LV_L13", - "INT_L_X0Y38/LV_L14", - "INT_L_X0Y39/LV_L15", - "INT_L_X0Y40/LV_L16", - "INT_L_X0Y41/LV_L17", - "INT_L_X0Y42/LV_L0", - "INT_L_X0Y42/LV_L18", - "INT_L_X0Y43/LV_L1", - "INT_L_X0Y44/LV_L2", - "INT_L_X0Y45/LV_L3", - "INT_L_X0Y46/LV_L4", - "INT_L_X0Y47/LV_L5", - "INT_L_X0Y48/LV_L6", - "INT_L_X0Y49/LV_L7", - "INT_L_X0Y50/LV_L8", - "INT_L_X0Y51/LV_L9", - "INT_L_X0Y52/LV_L10", - "INT_L_X0Y53/LV_L11", - "INT_L_X0Y54/LV_L12", - "INT_L_X0Y55/LV_L13", - "INT_L_X0Y56/LV_L14", - "INT_L_X0Y57/LV_L15", - "INT_L_X0Y58/LV_L16", - "INT_L_X0Y59/LV_L17", - "INT_L_X0Y60/LV_L0", - "INT_L_X0Y60/LV_L18", - "INT_L_X0Y61/LV_L1", - "INT_L_X0Y62/LV_L2", - "INT_L_X0Y63/LV_L3", - "INT_L_X0Y64/LV_L4", - "INT_L_X0Y65/LV_L5", - "INT_L_X0Y66/LV_L6", - "INT_L_X0Y67/LV_L7", - "INT_L_X0Y68/LV_L8", - "INT_L_X0Y69/LV_L9", - "INT_L_X0Y70/LV_L10", - "INT_L_X0Y71/LV_L11", - "INT_L_X0Y72/LV_L12", - "INT_L_X0Y73/LV_L13", - "INT_L_X0Y74/LV_L14", - "INT_L_X0Y75/LV_L15", - "INT_L_X0Y76/LV_L16", - "INT_L_X0Y77/LV_L17", - "INT_L_X0Y78/LV_L0", - "INT_L_X0Y78/LV_L18", - "INT_L_X0Y79/LV_L1", - "INT_L_X0Y80/LV_L2", - "INT_L_X0Y81/LV_L3", - "INT_L_X0Y82/LV_L4", - "INT_L_X0Y83/LV_L5", - "INT_L_X0Y84/LV_L6", - "INT_L_X0Y85/LV_L7", - "INT_L_X0Y86/LV_L8", - "INT_L_X0Y87/LV_L9", - "INT_L_X0Y88/LV_L10", - "INT_L_X0Y89/LV_L11", - "INT_L_X0Y90/LV_L12", - "INT_L_X0Y91/LV_L13", - "INT_L_X0Y92/LV_L14", - "INT_L_X0Y93/LV_L15", - "INT_L_X0Y94/LV_L16", - "INT_L_X0Y95/LV_L17", - "INT_L_X0Y96/LVB_L0", - "INT_L_X0Y96/LV_L18", - "INT_L_X0Y97/LVB_L1", - "INT_L_X0Y98/LVB_L2", - "INT_L_X0Y99/LVB_L3", - "INT_L_X0Y100/LVB_L4", - "INT_L_X0Y101/LVB_L5", - "INT_L_X0Y102/LVB_L6", - "INT_L_X0Y103/LVB_L7", - "INT_L_X0Y104/LVB_L8", - "INT_L_X0Y105/LVB_L9", - "INT_L_X0Y106/LVB_L10", - "INT_L_X0Y107/LVB_L11", - "INT_L_X0Y108/LVB_L12", - "INT_L_X0Y108/NN6BEG2", - "INT_L_X0Y109/NN6A2", - "INT_L_X0Y110/NN6B2", - "INT_L_X0Y111/NN6C2", - "INT_L_X0Y112/NN6D2", - "INT_L_X0Y113/NN6E2", - "INT_L_X0Y114/EE2BEG2", - "INT_L_X0Y114/NN6END2", - "INT_R_X1Y114/EE2A2", - "IO_INT_INTERFACE_L_X0Y5/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y5/INT_INTERFACE_LOGIC_OUTS_L_B18", - "LIOB33_X0Y5/IOB_IBUF1", - "LIOI3_X0Y5/IOI_ILOGIC1_O", - "LIOI3_X0Y5/IOI_LOGIC_OUTS18_0", - "LIOI3_X0Y5/LIOI_I1", - "LIOI3_X0Y5/LIOI_IBUF1", - "LIOI3_X0Y5/LIOI_ILOGIC1_D", - "L_TERM_INT_X2Y6/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y119/VBRK_EE2A2" - ] - }, - { - "name": "din[7]", - "node": "INT_L_X0Y116/EE2BEG2", - "pin": "W13", - "wire": "VBRK_X9Y121/VBRK_EE2A2", - "wires_outside_roi": [ - "BRKH_INT_X0Y49/BRKH_INT_L_LV6", - "BRKH_INT_X0Y99/BRKH_INT_LVB_L3", - "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_0", - "HCLK_L_X4Y26/HCLK_LV17", - "HCLK_L_X4Y78/HCLK_LV13", - "INT_INTERFACE_R_X1Y116/INT_INTERFACE_EE2A2", - "INT_L_X0Y6/LOGIC_OUTS_L18", - "INT_L_X0Y6/NR1BEG0", - "INT_L_X0Y7/LV_L0", - "INT_L_X0Y7/NR1END0", - "INT_L_X0Y8/LV_L1", - "INT_L_X0Y9/LV_L2", - "INT_L_X0Y10/LV_L3", - "INT_L_X0Y11/LV_L4", - "INT_L_X0Y12/LV_L5", - "INT_L_X0Y13/LV_L6", - "INT_L_X0Y14/LV_L7", - "INT_L_X0Y15/LV_L8", - "INT_L_X0Y16/LV_L9", - "INT_L_X0Y17/LV_L10", - "INT_L_X0Y18/LV_L11", - "INT_L_X0Y19/LV_L12", - "INT_L_X0Y20/LV_L13", - "INT_L_X0Y21/LV_L14", - "INT_L_X0Y22/LV_L15", - "INT_L_X0Y23/LV_L16", - "INT_L_X0Y24/LV_L17", - "INT_L_X0Y25/LV_L0", - "INT_L_X0Y25/LV_L18", - "INT_L_X0Y26/LV_L1", - "INT_L_X0Y27/LV_L2", - "INT_L_X0Y28/LV_L3", - "INT_L_X0Y29/LV_L4", - "INT_L_X0Y30/LV_L5", - "INT_L_X0Y31/LV_L6", - "INT_L_X0Y32/LV_L7", - "INT_L_X0Y33/LV_L8", - "INT_L_X0Y34/LV_L9", - "INT_L_X0Y35/LV_L10", - "INT_L_X0Y36/LV_L11", - "INT_L_X0Y37/LV_L12", - "INT_L_X0Y38/LV_L13", - "INT_L_X0Y39/LV_L14", - "INT_L_X0Y40/LV_L15", - "INT_L_X0Y41/LV_L16", - "INT_L_X0Y42/LV_L17", - "INT_L_X0Y43/LV_L0", - "INT_L_X0Y43/LV_L18", - "INT_L_X0Y44/LV_L1", - "INT_L_X0Y45/LV_L2", - "INT_L_X0Y46/LV_L3", - "INT_L_X0Y47/LV_L4", - "INT_L_X0Y48/LV_L5", - "INT_L_X0Y49/LV_L6", - "INT_L_X0Y50/LV_L7", - "INT_L_X0Y51/LV_L8", - "INT_L_X0Y52/LV_L9", - "INT_L_X0Y53/LV_L10", - "INT_L_X0Y54/LV_L11", - "INT_L_X0Y55/LV_L12", - "INT_L_X0Y56/LV_L13", - "INT_L_X0Y57/LV_L14", - "INT_L_X0Y58/LV_L15", - "INT_L_X0Y59/LV_L16", - "INT_L_X0Y60/LV_L17", - "INT_L_X0Y61/LV_L0", - "INT_L_X0Y61/LV_L18", - "INT_L_X0Y62/LV_L1", - "INT_L_X0Y63/LV_L2", - "INT_L_X0Y64/LV_L3", - "INT_L_X0Y65/LV_L4", - "INT_L_X0Y66/LV_L5", - "INT_L_X0Y67/LV_L6", - "INT_L_X0Y68/LV_L7", - "INT_L_X0Y69/LV_L8", - "INT_L_X0Y70/LV_L9", - "INT_L_X0Y71/LV_L10", - "INT_L_X0Y72/LV_L11", - "INT_L_X0Y73/LV_L12", - "INT_L_X0Y74/LV_L13", - "INT_L_X0Y75/LV_L14", - "INT_L_X0Y76/LV_L15", - "INT_L_X0Y77/LV_L16", - "INT_L_X0Y78/LV_L17", - "INT_L_X0Y79/LV_L0", - "INT_L_X0Y79/LV_L18", - "INT_L_X0Y80/LV_L1", - "INT_L_X0Y81/LV_L2", - "INT_L_X0Y82/LV_L3", - "INT_L_X0Y83/LV_L4", - "INT_L_X0Y84/LV_L5", - "INT_L_X0Y85/LV_L6", - "INT_L_X0Y86/LV_L7", - "INT_L_X0Y87/LV_L8", - "INT_L_X0Y88/LV_L9", - "INT_L_X0Y89/LV_L10", - "INT_L_X0Y90/LV_L11", - "INT_L_X0Y91/LV_L12", - "INT_L_X0Y92/LV_L13", - "INT_L_X0Y93/LV_L14", - "INT_L_X0Y94/LV_L15", - "INT_L_X0Y95/LV_L16", - "INT_L_X0Y96/LV_L17", - "INT_L_X0Y97/LVB_L0", - "INT_L_X0Y97/LV_L18", - "INT_L_X0Y98/LVB_L1", - "INT_L_X0Y99/LVB_L2", - "INT_L_X0Y100/LVB_L3", - "INT_L_X0Y101/LVB_L4", - "INT_L_X0Y102/LVB_L5", - "INT_L_X0Y103/LVB_L6", - "INT_L_X0Y104/LVB_L7", - "INT_L_X0Y105/LVB_L8", - "INT_L_X0Y106/LVB_L9", - "INT_L_X0Y107/LVB_L10", - "INT_L_X0Y108/LVB_L11", - "INT_L_X0Y109/LVB_L12", - "INT_L_X0Y109/NN6BEG2", - "INT_L_X0Y110/NN6A2", - "INT_L_X0Y111/NN6B2", - "INT_L_X0Y112/NN6C2", - "INT_L_X0Y113/NN6D2", - "INT_L_X0Y114/NN6E2", - "INT_L_X0Y115/NN6END2", - "INT_L_X0Y115/NR1BEG2", - "INT_L_X0Y116/EE2BEG2", - "INT_L_X0Y116/NR1END2", - "INT_R_X1Y116/EE2A2", - "IO_INT_INTERFACE_L_X0Y6/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y6/INT_INTERFACE_LOGIC_OUTS_L_B18", - "LIOB33_X0Y5/IOB_IBUF0", - "LIOI3_X0Y5/IOI_ILOGIC0_O", - "LIOI3_X0Y5/IOI_LOGIC_OUTS18_1", - "LIOI3_X0Y5/LIOI_I0", - "LIOI3_X0Y5/LIOI_IBUF0", - "LIOI3_X0Y5/LIOI_ILOGIC0_D", - "L_TERM_INT_X2Y7/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y121/VBRK_EE2A2" - ] - }, - { - "name": "din[8]", - "node": "INT_R_X25Y126/WW2BEG1", - "pin": "V2", - "wire": "VBRK_X61Y132/VBRK_WW2END1", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y129/INT_INTERFACE_NW4END2", - "BRAM_INT_INTERFACE_R_X37Y59/INT_INTERFACE_LH6", - "BRAM_L_X30Y125/BRAM_NW4END2_4", - "BRAM_R_X37Y55/BRAM_LH6_4", - "BRKH_INT_X31Y99/BRKH_INT_LV4", - "BRKH_INT_X43Y49/BRKH_INT_LV8", - "CLBLL_L_X24Y126/CLBLL_WW2END1", - "CLBLL_L_X26Y126/CLBLL_WW4END2", - "CLBLL_L_X28Y126/CLBLL_WW4B2", - "CLBLL_L_X38Y59/CLBLL_LH6", - "CLBLL_L_X40Y59/CLBLL_LH4", - "CLBLL_R_X31Y59/CLBLL_LH12", - "CLBLM_L_X32Y59/CLBLM_LH12", - "CLBLM_L_X36Y59/CLBLM_LH8", - "CLBLM_R_X25Y126/CLBLM_WW4END2", - "CLBLM_R_X27Y126/CLBLM_WW4B2", - "CLBLM_R_X29Y129/CLBLM_NW4END2", - "CLBLM_R_X33Y59/CLBLM_LH10", - "CLBLM_R_X35Y59/CLBLM_LH8", - "CLBLM_R_X39Y59/CLBLM_LH4", - "CLBLM_R_X41Y59/CLBLM_LH2", - "CLK_HROW_TOP_R_X60Y130/CLK_HROW_WW2END1_5", - "CMT_FIFO_L_X107Y60/CMT_FIFO_LH2_8", - "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_9", - "DSP_L_X34Y55/DSP_LH10_4", - "HCLK_R_BOT_UTURN_X73Y130/B_TERM_UTURN_INT_SS6D1", - "HCLK_R_X78Y78/HCLK_LV15", - "HCLK_R_X78Y130/HCLK_LVB12", - "INT_INTERFACE_L_X34Y59/INT_INTERFACE_LH10", - "INT_INTERFACE_L_X42Y59/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y126/INT_INTERFACE_WW2END1", - "INT_L_X24Y126/WW2A1", - "INT_L_X26Y126/WW4C2", - "INT_L_X28Y126/WW4A2", - "INT_L_X30Y125/NW6A2", - "INT_L_X30Y126/NW6B2", - "INT_L_X30Y127/NW6C2", - "INT_L_X30Y128/NW6D2", - "INT_L_X30Y129/NW6E2", - "INT_L_X32Y59/LH11", - "INT_L_X34Y59/LH9", - "INT_L_X36Y59/LH7", - "INT_L_X38Y59/LH5", - "INT_L_X40Y59/LH3", - "INT_L_X42Y59/LH1", - "INT_R_X25Y126/WW2BEG1", - "INT_R_X25Y126/WW4END2", - "INT_R_X27Y126/WW4B2", - "INT_R_X29Y125/NN6E2", - "INT_R_X29Y125/SS6D1", - "INT_R_X29Y126/NN6END2", - "INT_R_X29Y126/SS6C1", - "INT_R_X29Y126/WW4BEG2", - "INT_R_X29Y127/SS6B1", - "INT_R_X29Y128/SS6A1", - "INT_R_X29Y129/NW6END2", - "INT_R_X29Y129/SS6BEG1", - "INT_R_X31Y59/LH12", - "INT_R_X31Y59/LV0", - "INT_R_X31Y60/LV1", - "INT_R_X31Y61/LV2", - "INT_R_X31Y62/LV3", - "INT_R_X31Y63/LV4", - "INT_R_X31Y64/LV5", - "INT_R_X31Y65/LV6", - "INT_R_X31Y66/LV7", - "INT_R_X31Y67/LV8", - "INT_R_X31Y68/LV9", - "INT_R_X31Y69/LV10", - "INT_R_X31Y70/LV11", - "INT_R_X31Y71/LV12", - "INT_R_X31Y72/LV13", - "INT_R_X31Y73/LV14", - "INT_R_X31Y74/LV15", - "INT_R_X31Y75/LV16", - "INT_R_X31Y76/LV17", - "INT_R_X31Y77/LV0", - "INT_R_X31Y77/LV18", - "INT_R_X31Y78/LV1", - "INT_R_X31Y79/LV2", - "INT_R_X31Y80/LV3", - "INT_R_X31Y81/LV4", - "INT_R_X31Y82/LV5", - "INT_R_X31Y83/LV6", - "INT_R_X31Y84/LV7", - "INT_R_X31Y85/LV8", - "INT_R_X31Y86/LV9", - "INT_R_X31Y87/LV10", - "INT_R_X31Y88/LV11", - "INT_R_X31Y89/LV12", - "INT_R_X31Y90/LV13", - "INT_R_X31Y91/LV14", - "INT_R_X31Y92/LV15", - "INT_R_X31Y93/LV16", - "INT_R_X31Y94/LV17", - "INT_R_X31Y95/LV0", - "INT_R_X31Y95/LV18", - "INT_R_X31Y96/LV1", - "INT_R_X31Y97/LV2", - "INT_R_X31Y98/LV3", - "INT_R_X31Y99/LV4", - "INT_R_X31Y100/LV5", - "INT_R_X31Y101/LV6", - "INT_R_X31Y102/LV7", - "INT_R_X31Y103/LV8", - "INT_R_X31Y104/LV9", - "INT_R_X31Y105/LV10", - "INT_R_X31Y106/LV11", - "INT_R_X31Y107/LV12", - "INT_R_X31Y108/LV13", - "INT_R_X31Y109/LV14", - "INT_R_X31Y110/LV15", - "INT_R_X31Y111/LV16", - "INT_R_X31Y112/LV17", - "INT_R_X31Y113/LV18", - "INT_R_X31Y113/LVB0", - "INT_R_X31Y114/LVB1", - "INT_R_X31Y115/LVB2", - "INT_R_X31Y116/LVB3", - "INT_R_X31Y117/LVB4", - "INT_R_X31Y118/LVB5", - "INT_R_X31Y119/LVB6", - "INT_R_X31Y120/LVB7", - "INT_R_X31Y121/LVB8", - "INT_R_X31Y122/LVB9", - "INT_R_X31Y123/LVB10", - "INT_R_X31Y124/LVB11", - "INT_R_X31Y125/LVB12", - "INT_R_X31Y125/NW6BEG2", - "INT_R_X33Y59/LH10", - "INT_R_X35Y59/LH8", - "INT_R_X37Y59/LH6", - "INT_R_X39Y59/LH4", - "INT_R_X41Y59/LH2", - "INT_R_X43Y40/LOGIC_OUTS18", - "INT_R_X43Y40/NR1BEG0", - "INT_R_X43Y41/LV0", - "INT_R_X43Y41/NR1END0", - "INT_R_X43Y42/LV1", - "INT_R_X43Y43/LV2", - "INT_R_X43Y44/LV3", - "INT_R_X43Y45/LV4", - "INT_R_X43Y46/LV5", - "INT_R_X43Y47/LV6", - "INT_R_X43Y48/LV7", - "INT_R_X43Y49/LV8", - "INT_R_X43Y50/LV9", - "INT_R_X43Y51/LV10", - "INT_R_X43Y52/LV11", - "INT_R_X43Y53/LV12", - "INT_R_X43Y54/LV13", - "INT_R_X43Y55/LV14", - "INT_R_X43Y56/LV15", - "INT_R_X43Y57/LV16", - "INT_R_X43Y58/LV17", - "INT_R_X43Y59/LH0", - "INT_R_X43Y59/LV18", - "IO_INT_INTERFACE_R_X43Y40/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X43Y40/INT_INTERFACE_LOGIC_OUTS_B18", - "RIOB33_X43Y39/IOB_IBUF0", - "RIOI3_X43Y39/IOI_ILOGIC0_O", - "RIOI3_X43Y39/IOI_LOGIC_OUTS18_1", - "RIOI3_X43Y39/RIOI_I0", - "RIOI3_X43Y39/RIOI_IBUF0", - "RIOI3_X43Y39/RIOI_ILOGIC0_D", - "R_TERM_INT_X112Y42/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X61Y132/VBRK_WW2END1", - "VBRK_X66Y132/VBRK_WW4END2", - "VBRK_X80Y62/VBRK_LH12", - "VBRK_X85Y62/VBRK_LH10", - "VBRK_X96Y62/VBRK_LH6", - "VBRK_X105Y62/VBRK_LH2" - ] - }, - { - "name": "din[9]", - "node": "INT_R_X25Y128/WW2BEG1", - "pin": "T3", - "wire": "VBRK_X61Y134/VBRK_WW2END1", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y128/INT_INTERFACE_NW4END2", - "BRAM_INT_INTERFACE_R_X37Y64/INT_INTERFACE_LH6", - "BRAM_L_X30Y125/BRAM_NW4END2_3", - "BRAM_R_X37Y60/BRAM_LH6_4", - "BRKH_INT_X31Y99/BRKH_INT_LV17", - "BRKH_INT_X43Y49/BRKH_INT_LV3", - "CLBLL_L_X24Y128/CLBLL_WW2END1", - "CLBLL_L_X26Y128/CLBLL_WW4END2", - "CLBLL_L_X28Y128/CLBLL_WW4B2", - "CLBLL_L_X38Y64/CLBLL_LH6", - "CLBLL_L_X40Y64/CLBLL_LH4", - "CLBLL_R_X31Y64/CLBLL_LH12", - "CLBLM_L_X32Y64/CLBLM_LH12", - "CLBLM_L_X36Y64/CLBLM_LH8", - "CLBLM_R_X25Y128/CLBLM_WW4END2", - "CLBLM_R_X27Y128/CLBLM_WW4B2", - "CLBLM_R_X29Y128/CLBLM_NW4END2", - "CLBLM_R_X33Y64/CLBLM_LH10", - "CLBLM_R_X35Y64/CLBLM_LH8", - "CLBLM_R_X39Y64/CLBLM_LH4", - "CLBLM_R_X41Y64/CLBLM_LH2", - "CLK_HROW_TOP_R_X60Y130/CLK_HROW_WW2END1_7", - "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_1", - "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_14", - "DSP_L_X34Y60/DSP_LH10_4", - "HCLK_L_X77Y130/HCLK_NW6A2", - "HCLK_R_X78Y78/HCLK_LV10", - "INT_INTERFACE_L_X34Y64/INT_INTERFACE_LH10", - "INT_INTERFACE_L_X42Y64/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y128/INT_INTERFACE_WW2END1", - "INT_L_X24Y128/WW2A1", - "INT_L_X26Y128/WW4C2", - "INT_L_X28Y128/WW4A2", - "INT_L_X30Y124/NW6A2", - "INT_L_X30Y125/NW6B2", - "INT_L_X30Y126/NW6C2", - "INT_L_X30Y127/NW6D2", - "INT_L_X30Y128/NW6E2", - "INT_L_X32Y64/LH11", - "INT_L_X34Y64/LH9", - "INT_L_X36Y64/LH7", - "INT_L_X38Y64/LH5", - "INT_L_X40Y64/LH3", - "INT_L_X42Y64/LH1", - "INT_R_X25Y128/WW2BEG1", - "INT_R_X25Y128/WW4END2", - "INT_R_X27Y128/WW4B2", - "INT_R_X29Y128/NW6END2", - "INT_R_X29Y128/WW4BEG2", - "INT_R_X31Y64/LH12", - "INT_R_X31Y64/LV0", - "INT_R_X31Y65/LV1", - "INT_R_X31Y66/LV2", - "INT_R_X31Y67/LV3", - "INT_R_X31Y68/LV4", - "INT_R_X31Y69/LV5", - "INT_R_X31Y70/LV6", - "INT_R_X31Y71/LV7", - "INT_R_X31Y72/LV8", - "INT_R_X31Y73/LV9", - "INT_R_X31Y74/LV10", - "INT_R_X31Y75/LV11", - "INT_R_X31Y76/LV12", - "INT_R_X31Y77/LV13", - "INT_R_X31Y78/LV14", - "INT_R_X31Y79/LV15", - "INT_R_X31Y80/LV16", - "INT_R_X31Y81/LV17", - "INT_R_X31Y82/LV0", - "INT_R_X31Y82/LV18", - "INT_R_X31Y83/LV1", - "INT_R_X31Y84/LV2", - "INT_R_X31Y85/LV3", - "INT_R_X31Y86/LV4", - "INT_R_X31Y87/LV5", - "INT_R_X31Y88/LV6", - "INT_R_X31Y89/LV7", - "INT_R_X31Y90/LV8", - "INT_R_X31Y91/LV9", - "INT_R_X31Y92/LV10", - "INT_R_X31Y93/LV11", - "INT_R_X31Y94/LV12", - "INT_R_X31Y95/LV13", - "INT_R_X31Y96/LV14", - "INT_R_X31Y97/LV15", - "INT_R_X31Y98/LV16", - "INT_R_X31Y99/LV17", - "INT_R_X31Y100/LV18", - "INT_R_X31Y100/LVB0", - "INT_R_X31Y101/LVB1", - "INT_R_X31Y102/LVB2", - "INT_R_X31Y103/LVB3", - "INT_R_X31Y104/LVB4", - "INT_R_X31Y105/LVB5", - "INT_R_X31Y106/LVB6", - "INT_R_X31Y107/LVB7", - "INT_R_X31Y108/LVB8", - "INT_R_X31Y109/LVB9", - "INT_R_X31Y110/LVB10", - "INT_R_X31Y111/LVB11", - "INT_R_X31Y112/LVB0", - "INT_R_X31Y112/LVB12", - "INT_R_X31Y113/LVB1", - "INT_R_X31Y114/LVB2", - "INT_R_X31Y115/LVB3", - "INT_R_X31Y116/LVB4", - "INT_R_X31Y117/LVB5", - "INT_R_X31Y118/LVB6", - "INT_R_X31Y119/LVB7", - "INT_R_X31Y120/LVB8", - "INT_R_X31Y121/LVB9", - "INT_R_X31Y122/LVB10", - "INT_R_X31Y123/LVB11", - "INT_R_X31Y124/LVB12", - "INT_R_X31Y124/NW6BEG2", - "INT_R_X33Y64/LH10", - "INT_R_X35Y64/LH8", - "INT_R_X37Y64/LH6", - "INT_R_X39Y64/LH4", - "INT_R_X41Y64/LH2", - "INT_R_X43Y45/LOGIC_OUTS18", - "INT_R_X43Y45/NR1BEG0", - "INT_R_X43Y46/LV0", - "INT_R_X43Y46/NR1END0", - "INT_R_X43Y47/LV1", - "INT_R_X43Y48/LV2", - "INT_R_X43Y49/LV3", - "INT_R_X43Y50/LV4", - "INT_R_X43Y51/LV5", - "INT_R_X43Y52/LV6", - "INT_R_X43Y53/LV7", - "INT_R_X43Y54/LV8", - "INT_R_X43Y55/LV9", - "INT_R_X43Y56/LV10", - "INT_R_X43Y57/LV11", - "INT_R_X43Y58/LV12", - "INT_R_X43Y59/LV13", - "INT_R_X43Y60/LV14", - "INT_R_X43Y61/LV15", - "INT_R_X43Y62/LV16", - "INT_R_X43Y63/LV17", - "INT_R_X43Y64/LH0", - "INT_R_X43Y64/LV18", - "IO_INT_INTERFACE_R_X43Y45/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X43Y45/INT_INTERFACE_LOGIC_OUTS_B18", - "RIOB33_X43Y45/IOB_IBUF1", - "RIOI3_X43Y45/IOI_ILOGIC1_O", - "RIOI3_X43Y45/IOI_LOGIC_OUTS18_0", - "RIOI3_X43Y45/RIOI_I1", - "RIOI3_X43Y45/RIOI_IBUF1", - "RIOI3_X43Y45/RIOI_ILOGIC1_D", - "R_TERM_INT_X112Y47/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X61Y134/VBRK_WW2END1", - "VBRK_X66Y134/VBRK_WW4END2", - "VBRK_X80Y67/VBRK_LH12", - "VBRK_X85Y67/VBRK_LH10", - "VBRK_X96Y67/VBRK_LH6", - "VBRK_X105Y67/VBRK_LH2" - ] - }, - { - "name": "din[10]", - "node": "INT_R_X25Y130/WW2BEG1", - "pin": "T2", - "wire": "VBRK_X61Y136/VBRK_WW2END1", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y130/INT_INTERFACE_NW4END2", - "BRAM_INT_INTERFACE_R_X37Y66/INT_INTERFACE_LH6", - "BRAM_L_X30Y130/BRAM_NW4END2_0", - "BRAM_R_X37Y65/BRAM_LH6_1", - "BRKH_INT_X31Y99/BRKH_INT_LV15", - "BRKH_INT_X43Y49/BRKH_INT_LV1", - "CLBLL_L_X24Y130/CLBLL_WW2END1", - "CLBLL_L_X26Y130/CLBLL_WW4END2", - "CLBLL_L_X28Y130/CLBLL_WW4B2", - "CLBLL_L_X38Y66/CLBLL_LH6", - "CLBLL_L_X40Y66/CLBLL_LH4", - "CLBLL_R_X31Y66/CLBLL_LH12", - "CLBLM_L_X32Y66/CLBLM_LH12", - "CLBLM_L_X36Y66/CLBLM_LH8", - "CLBLM_R_X25Y130/CLBLM_WW4END2", - "CLBLM_R_X27Y130/CLBLM_WW4B2", - "CLBLM_R_X29Y130/CLBLM_NW4END2", - "CLBLM_R_X33Y66/CLBLM_LH10", - "CLBLM_R_X35Y66/CLBLM_LH8", - "CLBLM_R_X39Y66/CLBLM_LH4", - "CLBLM_R_X41Y66/CLBLM_LH2", - "CLK_FEED_X60Y136/CLK_FEED_WW2END1", - "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_3", - "CMT_TOP_L_LOWER_T_X106Y70/CMT_TOP_LH2_0", - "DSP_L_X34Y65/DSP_LH10_1", - "HCLK_R_X78Y78/HCLK_LV8", - "HCLK_R_X78Y130/HCLK_LVB11", - "INT_INTERFACE_L_X34Y66/INT_INTERFACE_LH10", - "INT_INTERFACE_L_X42Y66/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y130/INT_INTERFACE_WW2END1", - "INT_L_X24Y130/WW2A1", - "INT_L_X26Y130/WW4C2", - "INT_L_X28Y130/WW4A2", - "INT_L_X30Y126/NW6A2", - "INT_L_X30Y127/NW6B2", - "INT_L_X30Y128/NW6C2", - "INT_L_X30Y129/NW6D2", - "INT_L_X30Y130/NW6E2", - "INT_L_X32Y66/LH11", - "INT_L_X34Y66/LH9", - "INT_L_X36Y66/LH7", - "INT_L_X38Y66/LH5", - "INT_L_X40Y66/LH3", - "INT_L_X42Y66/LH1", - "INT_R_X25Y130/WW2BEG1", - "INT_R_X25Y130/WW4END2", - "INT_R_X27Y130/WW4B2", - "INT_R_X29Y130/NW6END2", - "INT_R_X29Y130/WW4BEG2", - "INT_R_X31Y66/LH12", - "INT_R_X31Y66/LV0", - "INT_R_X31Y67/LV1", - "INT_R_X31Y68/LV2", - "INT_R_X31Y69/LV3", - "INT_R_X31Y70/LV4", - "INT_R_X31Y71/LV5", - "INT_R_X31Y72/LV6", - "INT_R_X31Y73/LV7", - "INT_R_X31Y74/LV8", - "INT_R_X31Y75/LV9", - "INT_R_X31Y76/LV10", - "INT_R_X31Y77/LV11", - "INT_R_X31Y78/LV12", - "INT_R_X31Y79/LV13", - "INT_R_X31Y80/LV14", - "INT_R_X31Y81/LV15", - "INT_R_X31Y82/LV16", - "INT_R_X31Y83/LV17", - "INT_R_X31Y84/LV0", - "INT_R_X31Y84/LV18", - "INT_R_X31Y85/LV1", - "INT_R_X31Y86/LV2", - "INT_R_X31Y87/LV3", - "INT_R_X31Y88/LV4", - "INT_R_X31Y89/LV5", - "INT_R_X31Y90/LV6", - "INT_R_X31Y91/LV7", - "INT_R_X31Y92/LV8", - "INT_R_X31Y93/LV9", - "INT_R_X31Y94/LV10", - "INT_R_X31Y95/LV11", - "INT_R_X31Y96/LV12", - "INT_R_X31Y97/LV13", - "INT_R_X31Y98/LV14", - "INT_R_X31Y99/LV15", - "INT_R_X31Y100/LV16", - "INT_R_X31Y101/LV17", - "INT_R_X31Y102/LV18", - "INT_R_X31Y102/LVB0", - "INT_R_X31Y103/LVB1", - "INT_R_X31Y104/LVB2", - "INT_R_X31Y105/LVB3", - "INT_R_X31Y106/LVB4", - "INT_R_X31Y107/LVB5", - "INT_R_X31Y108/LVB6", - "INT_R_X31Y109/LVB7", - "INT_R_X31Y110/LVB8", - "INT_R_X31Y111/LVB9", - "INT_R_X31Y112/LVB10", - "INT_R_X31Y113/LVB11", - "INT_R_X31Y114/LVB0", - "INT_R_X31Y114/LVB12", - "INT_R_X31Y115/LVB1", - "INT_R_X31Y116/LVB2", - "INT_R_X31Y117/LVB3", - "INT_R_X31Y118/LVB4", - "INT_R_X31Y119/LVB5", - "INT_R_X31Y120/LVB6", - "INT_R_X31Y121/LVB7", - "INT_R_X31Y122/LVB8", - "INT_R_X31Y123/LVB9", - "INT_R_X31Y124/LVB10", - "INT_R_X31Y125/LVB11", - "INT_R_X31Y126/LVB12", - "INT_R_X31Y126/NW6BEG2", - "INT_R_X33Y66/LH10", - "INT_R_X35Y66/LH8", - "INT_R_X37Y66/LH6", - "INT_R_X39Y66/LH4", - "INT_R_X41Y66/LH2", - "INT_R_X43Y47/LOGIC_OUTS18", - "INT_R_X43Y47/NR1BEG0", - "INT_R_X43Y48/LV0", - "INT_R_X43Y48/NR1END0", - "INT_R_X43Y49/LV1", - "INT_R_X43Y50/LV2", - "INT_R_X43Y51/LV3", - "INT_R_X43Y52/LV4", - "INT_R_X43Y53/LV5", - "INT_R_X43Y54/LV6", - "INT_R_X43Y55/LV7", - "INT_R_X43Y56/LV8", - "INT_R_X43Y57/LV9", - "INT_R_X43Y58/LV10", - "INT_R_X43Y59/LV11", - "INT_R_X43Y60/LV12", - "INT_R_X43Y61/LV13", - "INT_R_X43Y62/LV14", - "INT_R_X43Y63/LV15", - "INT_R_X43Y64/LV16", - "INT_R_X43Y65/LV17", - "INT_R_X43Y66/LH0", - "INT_R_X43Y66/LV18", - "IO_INT_INTERFACE_R_X43Y47/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X43Y47/INT_INTERFACE_LOGIC_OUTS_B18", - "RIOB33_X43Y47/IOB_IBUF1", - "RIOI3_X43Y47/IOI_ILOGIC1_O", - "RIOI3_X43Y47/IOI_LOGIC_OUTS18_0", - "RIOI3_X43Y47/RIOI_I1", - "RIOI3_X43Y47/RIOI_IBUF1", - "RIOI3_X43Y47/RIOI_ILOGIC1_D", - "R_TERM_INT_X112Y49/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X61Y136/VBRK_WW2END1", - "VBRK_X66Y136/VBRK_WW4END2", - "VBRK_X80Y69/VBRK_LH12", - "VBRK_X85Y69/VBRK_LH10", - "VBRK_X96Y69/VBRK_LH6", - "VBRK_X105Y69/VBRK_LH2" - ] - }, - { - "name": "din[11]", - "node": "INT_R_X25Y132/WW2BEG1", - "pin": "R3", - "wire": "VBRK_X61Y138/VBRK_WW2END1", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y129/INT_INTERFACE_NW4END3", - "BRAM_INT_INTERFACE_R_X37Y65/INT_INTERFACE_LH6", - "BRAM_L_X30Y125/BRAM_NW4END3_4", - "BRAM_R_X37Y65/BRAM_LH6_0", - "BRKH_INT_X31Y99/BRKH_INT_LV16", - "BRKH_INT_X43Y49/BRKH_INT_LV2", - "CLBLL_L_X24Y132/CLBLL_WW2END1", - "CLBLL_L_X26Y132/CLBLL_WW4END2", - "CLBLL_L_X28Y132/CLBLL_WW4B2", - "CLBLL_L_X38Y65/CLBLL_LH6", - "CLBLL_L_X40Y65/CLBLL_LH4", - "CLBLL_R_X31Y65/CLBLL_LH12", - "CLBLM_L_X32Y65/CLBLM_LH12", - "CLBLM_L_X36Y65/CLBLM_LH8", - "CLBLM_R_X25Y132/CLBLM_WW4END2", - "CLBLM_R_X27Y132/CLBLM_WW4B2", - "CLBLM_R_X29Y129/CLBLM_NW4END3", - "CLBLM_R_X33Y65/CLBLM_LH10", - "CLBLM_R_X35Y65/CLBLM_LH8", - "CLBLM_R_X39Y65/CLBLM_LH4", - "CLBLM_R_X41Y65/CLBLM_LH2", - "CLK_FEED_X60Y138/CLK_FEED_WW2END1", - "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_2", - "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_15", - "DSP_L_X34Y65/DSP_LH10_0", - "HCLK_R_BOT_UTURN_X73Y130/B_TERM_UTURN_INT_LVB4", - "HCLK_R_X78Y78/HCLK_LV9", - "HCLK_R_X78Y130/HCLK_NN6E3", - "INT_INTERFACE_L_X34Y65/INT_INTERFACE_LH10", - "INT_INTERFACE_L_X42Y65/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y132/INT_INTERFACE_WW2END1", - "INT_L_X24Y132/WW2A1", - "INT_L_X26Y132/WW4C2", - "INT_L_X28Y132/WW4A2", - "INT_L_X30Y125/NW6A3", - "INT_L_X30Y126/NW6B3", - "INT_L_X30Y127/NW6C3", - "INT_L_X30Y128/NW6D3", - "INT_L_X30Y129/NW6E3", - "INT_L_X32Y65/LH11", - "INT_L_X34Y65/LH9", - "INT_L_X36Y65/LH7", - "INT_L_X38Y65/LH5", - "INT_L_X40Y65/LH3", - "INT_L_X42Y65/LH1", - "INT_R_X25Y132/WW2BEG1", - "INT_R_X25Y132/WW4END2", - "INT_R_X27Y132/WW4B2", - "INT_R_X29Y125/LVB5", - "INT_R_X29Y125/LVB8", - "INT_R_X29Y126/LVB6", - "INT_R_X29Y126/LVB9", - "INT_R_X29Y127/LVB7", - "INT_R_X29Y127/LVB10", - "INT_R_X29Y128/LVB8", - "INT_R_X29Y128/LVB11", - "INT_R_X29Y129/LVB9", - "INT_R_X29Y129/LVB12", - "INT_R_X29Y129/NW6END3", - "INT_R_X29Y130/LVB10", - "INT_R_X29Y131/LVB11", - "INT_R_X29Y132/LVB12", - "INT_R_X29Y132/WW4BEG2", - "INT_R_X31Y65/LH12", - "INT_R_X31Y65/LV0", - "INT_R_X31Y66/LV1", - "INT_R_X31Y67/LV2", - "INT_R_X31Y68/LV3", - "INT_R_X31Y69/LV4", - "INT_R_X31Y70/LV5", - "INT_R_X31Y71/LV6", - "INT_R_X31Y72/LV7", - "INT_R_X31Y73/LV8", - "INT_R_X31Y74/LV9", - "INT_R_X31Y75/LV10", - "INT_R_X31Y76/LV11", - "INT_R_X31Y77/LV12", - "INT_R_X31Y78/LV13", - "INT_R_X31Y79/LV14", - "INT_R_X31Y80/LV15", - "INT_R_X31Y81/LV16", - "INT_R_X31Y82/LV17", - "INT_R_X31Y83/LV0", - "INT_R_X31Y83/LV18", - "INT_R_X31Y84/LV1", - "INT_R_X31Y85/LV2", - "INT_R_X31Y86/LV3", - "INT_R_X31Y87/LV4", - "INT_R_X31Y88/LV5", - "INT_R_X31Y89/LV6", - "INT_R_X31Y90/LV7", - "INT_R_X31Y91/LV8", - "INT_R_X31Y92/LV9", - "INT_R_X31Y93/LV10", - "INT_R_X31Y94/LV11", - "INT_R_X31Y95/LV12", - "INT_R_X31Y96/LV13", - "INT_R_X31Y97/LV14", - "INT_R_X31Y98/LV15", - "INT_R_X31Y99/LV16", - "INT_R_X31Y100/LV17", - "INT_R_X31Y101/LV0", - "INT_R_X31Y101/LV18", - "INT_R_X31Y102/LV1", - "INT_R_X31Y103/LV2", - "INT_R_X31Y104/LV3", - "INT_R_X31Y105/LV4", - "INT_R_X31Y106/LV5", - "INT_R_X31Y107/LV6", - "INT_R_X31Y108/LV7", - "INT_R_X31Y109/LV8", - "INT_R_X31Y110/LV9", - "INT_R_X31Y111/LV10", - "INT_R_X31Y112/LV11", - "INT_R_X31Y113/LV12", - "INT_R_X31Y114/LV13", - "INT_R_X31Y115/LV14", - "INT_R_X31Y116/LV15", - "INT_R_X31Y117/LV16", - "INT_R_X31Y118/LV17", - "INT_R_X31Y119/LV18", - "INT_R_X31Y119/NN6BEG3", - "INT_R_X31Y120/NN6A3", - "INT_R_X31Y121/NN6B3", - "INT_R_X31Y122/NN6C3", - "INT_R_X31Y123/NN6D3", - "INT_R_X31Y124/NN6E3", - "INT_R_X31Y125/NN6END3", - "INT_R_X31Y125/NW6BEG3", - "INT_R_X33Y65/LH10", - "INT_R_X35Y65/LH8", - "INT_R_X37Y65/LH6", - "INT_R_X39Y65/LH4", - "INT_R_X41Y65/LH2", - "INT_R_X43Y46/LOGIC_OUTS18", - "INT_R_X43Y46/NR1BEG0", - "INT_R_X43Y47/LV0", - "INT_R_X43Y47/NR1END0", - "INT_R_X43Y48/LV1", - "INT_R_X43Y49/LV2", - "INT_R_X43Y50/LV3", - "INT_R_X43Y51/LV4", - "INT_R_X43Y52/LV5", - "INT_R_X43Y53/LV6", - "INT_R_X43Y54/LV7", - "INT_R_X43Y55/LV8", - "INT_R_X43Y56/LV9", - "INT_R_X43Y57/LV10", - "INT_R_X43Y58/LV11", - "INT_R_X43Y59/LV12", - "INT_R_X43Y60/LV13", - "INT_R_X43Y61/LV14", - "INT_R_X43Y62/LV15", - "INT_R_X43Y63/LV16", - "INT_R_X43Y64/LV17", - "INT_R_X43Y65/LH0", - "INT_R_X43Y65/LV18", - "IO_INT_INTERFACE_R_X43Y46/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X43Y46/INT_INTERFACE_LOGIC_OUTS_B18", - "RIOB33_X43Y45/IOB_IBUF0", - "RIOI3_X43Y45/IOI_ILOGIC0_O", - "RIOI3_X43Y45/IOI_LOGIC_OUTS18_1", - "RIOI3_X43Y45/RIOI_I0", - "RIOI3_X43Y45/RIOI_IBUF0", - "RIOI3_X43Y45/RIOI_ILOGIC0_D", - "R_TERM_INT_X112Y48/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X61Y138/VBRK_WW2END1", - "VBRK_X66Y138/VBRK_WW4END2", - "VBRK_X80Y68/VBRK_LH12", - "VBRK_X85Y68/VBRK_LH10", - "VBRK_X96Y68/VBRK_LH6", - "VBRK_X105Y68/VBRK_LH2" - ] - }, - { - "name": "din[12]", - "node": "INT_R_X25Y134/WW2BEG1", - "pin": "W2", - "wire": "VBRK_X61Y140/VBRK_WW2END1", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y134/INT_INTERFACE_NW4END3", - "BRAM_INT_INTERFACE_R_X37Y58/INT_INTERFACE_LH6", - "BRAM_L_X30Y130/BRAM_NW4END3_4", - "BRAM_R_X37Y55/BRAM_LH6_3", - "BRKH_INT_X31Y99/BRKH_INT_LV5", - "BRKH_INT_X43Y49/BRKH_INT_LV9", - "CLBLL_L_X24Y134/CLBLL_WW2END1", - "CLBLL_L_X26Y134/CLBLL_WW4END2", - "CLBLL_L_X28Y134/CLBLL_WW4B2", - "CLBLL_L_X38Y58/CLBLL_LH6", - "CLBLL_L_X40Y58/CLBLL_LH4", - "CLBLL_R_X31Y58/CLBLL_LH12", - "CLBLM_L_X32Y58/CLBLM_LH12", - "CLBLM_L_X36Y58/CLBLM_LH8", - "CLBLM_R_X25Y134/CLBLM_WW4END2", - "CLBLM_R_X27Y134/CLBLM_WW4B2", - "CLBLM_R_X29Y134/CLBLM_NW4END3", - "CLBLM_R_X33Y58/CLBLM_LH10", - "CLBLM_R_X35Y58/CLBLM_LH8", - "CLBLM_R_X39Y58/CLBLM_LH4", - "CLBLM_R_X41Y58/CLBLM_LH2", - "CLK_FEED_X60Y140/CLK_FEED_WW2END1", - "CMT_FIFO_L_X107Y60/CMT_FIFO_LH2_7", - "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_8", - "DSP_L_X34Y55/DSP_LH10_3", - "HCLK_R_BOT_UTURN_X73Y130/B_TERM_UTURN_INT_LVB2", - "HCLK_R_X78Y78/HCLK_LV16", - "HCLK_R_X78Y130/HCLK_LV12", - "INT_INTERFACE_L_X34Y58/INT_INTERFACE_LH10", - "INT_INTERFACE_L_X42Y58/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y134/INT_INTERFACE_WW2END1", - "INT_L_X24Y134/WW2A1", - "INT_L_X26Y134/WW4C2", - "INT_L_X28Y134/WW4A2", - "INT_L_X30Y130/NW6A3", - "INT_L_X30Y131/NW6B3", - "INT_L_X30Y132/NW6C3", - "INT_L_X30Y133/NW6D3", - "INT_L_X30Y134/NW6E3", - "INT_L_X32Y58/LH11", - "INT_L_X34Y58/LH9", - "INT_L_X36Y58/LH7", - "INT_L_X38Y58/LH5", - "INT_L_X40Y58/LH3", - "INT_L_X42Y58/LH1", - "INT_R_X25Y134/WW2BEG1", - "INT_R_X25Y134/WW4END2", - "INT_R_X27Y134/WW4B2", - "INT_R_X29Y125/LVB3", - "INT_R_X29Y125/LVB10", - "INT_R_X29Y126/LVB4", - "INT_R_X29Y126/LVB11", - "INT_R_X29Y127/LVB5", - "INT_R_X29Y127/LVB12", - "INT_R_X29Y128/LVB6", - "INT_R_X29Y129/LVB7", - "INT_R_X29Y130/LVB8", - "INT_R_X29Y131/LVB9", - "INT_R_X29Y132/LVB10", - "INT_R_X29Y133/LVB11", - "INT_R_X29Y134/LVB12", - "INT_R_X29Y134/NW6END3", - "INT_R_X29Y134/WW4BEG2", - "INT_R_X31Y58/LH12", - "INT_R_X31Y58/LV0", - "INT_R_X31Y59/LV1", - "INT_R_X31Y60/LV2", - "INT_R_X31Y61/LV3", - "INT_R_X31Y62/LV4", - "INT_R_X31Y63/LV5", - "INT_R_X31Y64/LV6", - "INT_R_X31Y65/LV7", - "INT_R_X31Y66/LV8", - "INT_R_X31Y67/LV9", - "INT_R_X31Y68/LV10", - "INT_R_X31Y69/LV11", - "INT_R_X31Y70/LV12", - "INT_R_X31Y71/LV13", - "INT_R_X31Y72/LV14", - "INT_R_X31Y73/LV15", - "INT_R_X31Y74/LV16", - "INT_R_X31Y75/LV17", - "INT_R_X31Y76/LV0", - "INT_R_X31Y76/LV18", - "INT_R_X31Y77/LV1", - "INT_R_X31Y78/LV2", - "INT_R_X31Y79/LV3", - "INT_R_X31Y80/LV4", - "INT_R_X31Y81/LV5", - "INT_R_X31Y82/LV6", - "INT_R_X31Y83/LV7", - "INT_R_X31Y84/LV8", - "INT_R_X31Y85/LV9", - "INT_R_X31Y86/LV10", - "INT_R_X31Y87/LV11", - "INT_R_X31Y88/LV12", - "INT_R_X31Y89/LV13", - "INT_R_X31Y90/LV14", - "INT_R_X31Y91/LV15", - "INT_R_X31Y92/LV16", - "INT_R_X31Y93/LV17", - "INT_R_X31Y94/LV0", - "INT_R_X31Y94/LV18", - "INT_R_X31Y95/LV1", - "INT_R_X31Y96/LV2", - "INT_R_X31Y97/LV3", - "INT_R_X31Y98/LV4", - "INT_R_X31Y99/LV5", - "INT_R_X31Y100/LV6", - "INT_R_X31Y101/LV7", - "INT_R_X31Y102/LV8", - "INT_R_X31Y103/LV9", - "INT_R_X31Y104/LV10", - "INT_R_X31Y105/LV11", - "INT_R_X31Y106/LV12", - "INT_R_X31Y107/LV13", - "INT_R_X31Y108/LV14", - "INT_R_X31Y109/LV15", - "INT_R_X31Y110/LV16", - "INT_R_X31Y111/LV17", - "INT_R_X31Y112/LV0", - "INT_R_X31Y112/LV18", - "INT_R_X31Y113/LV1", - "INT_R_X31Y114/LV2", - "INT_R_X31Y115/LV3", - "INT_R_X31Y116/LV4", - "INT_R_X31Y117/LV5", - "INT_R_X31Y118/LV6", - "INT_R_X31Y119/LV7", - "INT_R_X31Y120/LV8", - "INT_R_X31Y121/LV9", - "INT_R_X31Y122/LV10", - "INT_R_X31Y123/LV11", - "INT_R_X31Y124/LV12", - "INT_R_X31Y125/LV13", - "INT_R_X31Y126/LV14", - "INT_R_X31Y127/LV15", - "INT_R_X31Y128/LV16", - "INT_R_X31Y129/LV17", - "INT_R_X31Y130/LV18", - "INT_R_X31Y130/NW6BEG3", - "INT_R_X33Y58/LH10", - "INT_R_X35Y58/LH8", - "INT_R_X37Y58/LH6", - "INT_R_X39Y58/LH4", - "INT_R_X41Y58/LH2", - "INT_R_X43Y39/LOGIC_OUTS18", - "INT_R_X43Y39/NR1BEG0", - "INT_R_X43Y40/LV0", - "INT_R_X43Y40/NR1END0", - "INT_R_X43Y41/LV1", - "INT_R_X43Y42/LV2", - "INT_R_X43Y43/LV3", - "INT_R_X43Y44/LV4", - "INT_R_X43Y45/LV5", - "INT_R_X43Y46/LV6", - "INT_R_X43Y47/LV7", - "INT_R_X43Y48/LV8", - "INT_R_X43Y49/LV9", - "INT_R_X43Y50/LV10", - "INT_R_X43Y51/LV11", - "INT_R_X43Y52/LV12", - "INT_R_X43Y53/LV13", - "INT_R_X43Y54/LV14", - "INT_R_X43Y55/LV15", - "INT_R_X43Y56/LV16", - "INT_R_X43Y57/LV17", - "INT_R_X43Y58/LH0", - "INT_R_X43Y58/LV18", - "IO_INT_INTERFACE_R_X43Y39/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X43Y39/INT_INTERFACE_LOGIC_OUTS_B18", - "RIOB33_X43Y39/IOB_IBUF1", - "RIOI3_X43Y39/IOI_ILOGIC1_O", - "RIOI3_X43Y39/IOI_LOGIC_OUTS18_0", - "RIOI3_X43Y39/RIOI_I1", - "RIOI3_X43Y39/RIOI_IBUF1", - "RIOI3_X43Y39/RIOI_ILOGIC1_D", - "R_TERM_INT_X112Y41/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X61Y140/VBRK_WW2END1", - "VBRK_X66Y140/VBRK_WW4END2", - "VBRK_X80Y61/VBRK_LH12", - "VBRK_X85Y61/VBRK_LH10", - "VBRK_X96Y61/VBRK_LH6", - "VBRK_X105Y61/VBRK_LH2" - ] - }, - { - "name": "din[13]", - "node": "INT_R_X25Y136/WW2BEG1", - "pin": "U1", - "wire": "VBRK_X61Y142/VBRK_WW2END1", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y132/INT_INTERFACE_NW4END2", - "BRAM_INT_INTERFACE_R_X37Y62/INT_INTERFACE_LH6", - "BRAM_L_X30Y130/BRAM_NW4END2_2", - "BRAM_R_X37Y60/BRAM_LH6_2", - "BRKH_INT_X31Y99/BRKH_INT_LV1", - "BRKH_INT_X43Y49/BRKH_INT_LV5", - "CLBLL_L_X24Y136/CLBLL_WW2END1", - "CLBLL_L_X26Y136/CLBLL_WW2END1", - "CLBLL_L_X28Y136/CLBLL_NW4END2", - "CLBLL_L_X38Y62/CLBLL_LH6", - "CLBLL_L_X40Y62/CLBLL_LH4", - "CLBLL_R_X31Y62/CLBLL_LH12", - "CLBLM_L_X32Y62/CLBLM_LH12", - "CLBLM_L_X36Y62/CLBLM_LH8", - "CLBLM_R_X25Y136/CLBLM_WW2END1", - "CLBLM_R_X27Y136/CLBLM_NW4END2", - "CLBLM_R_X29Y132/CLBLM_NW4END2", - "CLBLM_R_X33Y62/CLBLM_LH10", - "CLBLM_R_X35Y62/CLBLM_LH8", - "CLBLM_R_X39Y62/CLBLM_LH4", - "CLBLM_R_X41Y62/CLBLM_LH2", - "CLK_BUFG_REBUF_X60Y142/CLK_BUFG_REBUF_WW2END1_0", - "CMT_FIFO_L_X107Y60/CMT_FIFO_LH2_11", - "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_12", - "DSP_L_X34Y60/DSP_LH10_2", - "HCLK_R_X78Y78/HCLK_LV12", - "HCLK_R_X78Y130/HCLK_LVB9", - "INT_INTERFACE_L_X34Y62/INT_INTERFACE_LH10", - "INT_INTERFACE_L_X42Y62/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y136/INT_INTERFACE_WW2END1", - "INT_L_X24Y136/WW2A1", - "INT_L_X26Y136/WW2A1", - "INT_L_X28Y132/NW6A2", - "INT_L_X28Y133/NW6B2", - "INT_L_X28Y134/NW6C2", - "INT_L_X28Y135/NW6D2", - "INT_L_X28Y136/NW6E2", - "INT_L_X30Y128/NW6A2", - "INT_L_X30Y129/NW6B2", - "INT_L_X30Y130/NW6C2", - "INT_L_X30Y131/NW6D2", - "INT_L_X30Y132/NW6E2", - "INT_L_X32Y62/LH11", - "INT_L_X34Y62/LH9", - "INT_L_X36Y62/LH7", - "INT_L_X38Y62/LH5", - "INT_L_X40Y62/LH3", - "INT_L_X42Y62/LH1", - "INT_R_X25Y136/WW2BEG1", - "INT_R_X25Y136/WW2END1", - "INT_R_X27Y136/NW6END2", - "INT_R_X27Y136/WW2BEG1", - "INT_R_X29Y132/NW6BEG2", - "INT_R_X29Y132/NW6END2", - "INT_R_X31Y62/LH12", - "INT_R_X31Y62/LV0", - "INT_R_X31Y63/LV1", - "INT_R_X31Y64/LV2", - "INT_R_X31Y65/LV3", - "INT_R_X31Y66/LV4", - "INT_R_X31Y67/LV5", - "INT_R_X31Y68/LV6", - "INT_R_X31Y69/LV7", - "INT_R_X31Y70/LV8", - "INT_R_X31Y71/LV9", - "INT_R_X31Y72/LV10", - "INT_R_X31Y73/LV11", - "INT_R_X31Y74/LV12", - "INT_R_X31Y75/LV13", - "INT_R_X31Y76/LV14", - "INT_R_X31Y77/LV15", - "INT_R_X31Y78/LV16", - "INT_R_X31Y79/LV17", - "INT_R_X31Y80/LV0", - "INT_R_X31Y80/LV18", - "INT_R_X31Y81/LV1", - "INT_R_X31Y82/LV2", - "INT_R_X31Y83/LV3", - "INT_R_X31Y84/LV4", - "INT_R_X31Y85/LV5", - "INT_R_X31Y86/LV6", - "INT_R_X31Y87/LV7", - "INT_R_X31Y88/LV8", - "INT_R_X31Y89/LV9", - "INT_R_X31Y90/LV10", - "INT_R_X31Y91/LV11", - "INT_R_X31Y92/LV12", - "INT_R_X31Y93/LV13", - "INT_R_X31Y94/LV14", - "INT_R_X31Y95/LV15", - "INT_R_X31Y96/LV16", - "INT_R_X31Y97/LV17", - "INT_R_X31Y98/LV0", - "INT_R_X31Y98/LV18", - "INT_R_X31Y99/LV1", - "INT_R_X31Y100/LV2", - "INT_R_X31Y101/LV3", - "INT_R_X31Y102/LV4", - "INT_R_X31Y103/LV5", - "INT_R_X31Y104/LV6", - "INT_R_X31Y105/LV7", - "INT_R_X31Y106/LV8", - "INT_R_X31Y107/LV9", - "INT_R_X31Y108/LV10", - "INT_R_X31Y109/LV11", - "INT_R_X31Y110/LV12", - "INT_R_X31Y111/LV13", - "INT_R_X31Y112/LV14", - "INT_R_X31Y113/LV15", - "INT_R_X31Y114/LV16", - "INT_R_X31Y115/LV17", - "INT_R_X31Y116/LV18", - "INT_R_X31Y116/LVB0", - "INT_R_X31Y117/LVB1", - "INT_R_X31Y118/LVB2", - "INT_R_X31Y119/LVB3", - "INT_R_X31Y120/LVB4", - "INT_R_X31Y121/LVB5", - "INT_R_X31Y122/LVB6", - "INT_R_X31Y123/LVB7", - "INT_R_X31Y124/LVB8", - "INT_R_X31Y125/LVB9", - "INT_R_X31Y126/LVB10", - "INT_R_X31Y127/LVB11", - "INT_R_X31Y128/LVB12", - "INT_R_X31Y128/NW6BEG2", - "INT_R_X33Y62/LH10", - "INT_R_X35Y62/LH8", - "INT_R_X37Y62/LH6", - "INT_R_X39Y62/LH4", - "INT_R_X41Y62/LH2", - "INT_R_X43Y43/LOGIC_OUTS18", - "INT_R_X43Y43/NR1BEG0", - "INT_R_X43Y44/LV0", - "INT_R_X43Y44/NR1END0", - "INT_R_X43Y45/LV1", - "INT_R_X43Y46/LV2", - "INT_R_X43Y47/LV3", - "INT_R_X43Y48/LV4", - "INT_R_X43Y49/LV5", - "INT_R_X43Y50/LV6", - "INT_R_X43Y51/LV7", - "INT_R_X43Y52/LV8", - "INT_R_X43Y53/LV9", - "INT_R_X43Y54/LV10", - "INT_R_X43Y55/LV11", - "INT_R_X43Y56/LV12", - "INT_R_X43Y57/LV13", - "INT_R_X43Y58/LV14", - "INT_R_X43Y59/LV15", - "INT_R_X43Y60/LV16", - "INT_R_X43Y61/LV17", - "INT_R_X43Y62/LH0", - "INT_R_X43Y62/LV18", - "IO_INT_INTERFACE_R_X43Y43/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X43Y43/INT_INTERFACE_LOGIC_OUTS_B18", - "RIOB33_X43Y43/IOB_IBUF1", - "RIOI3_TBYTESRC_X43Y43/IOI_ILOGIC1_O", - "RIOI3_TBYTESRC_X43Y43/IOI_LOGIC_OUTS18_0", - "RIOI3_TBYTESRC_X43Y43/RIOI_I1", - "RIOI3_TBYTESRC_X43Y43/RIOI_IBUF1", - "RIOI3_TBYTESRC_X43Y43/RIOI_ILOGIC1_D", - "R_TERM_INT_X112Y45/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X61Y142/VBRK_WW2END1", - "VBRK_X66Y142/VBRK_WW2END1", - "VBRK_X80Y65/VBRK_LH12", - "VBRK_X85Y65/VBRK_LH10", - "VBRK_X96Y65/VBRK_LH6", - "VBRK_X105Y65/VBRK_LH2" - ] - }, - { - "name": "din[14]", - "node": "INT_R_X25Y138/WW2BEG1", - "pin": "T1", - "wire": "VBRK_X61Y144/VBRK_WW2END1", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y135/INT_INTERFACE_LH2", - "BRAM_INT_INTERFACE_R_X37Y63/INT_INTERFACE_LH6", - "BRAM_L_X30Y135/BRAM_LH2_0", - "BRAM_R_X37Y60/BRAM_LH6_3", - "BRKH_INT_X31Y99/BRKH_INT_LV0", - "BRKH_INT_X43Y49/BRKH_INT_LV4", - "CLBLL_L_X24Y135/CLBLL_LH8", - "CLBLL_L_X24Y138/CLBLL_WW2END1", - "CLBLL_L_X26Y135/CLBLL_LH6", - "CLBLL_L_X28Y135/CLBLL_LH4", - "CLBLL_L_X38Y63/CLBLL_LH6", - "CLBLL_L_X40Y63/CLBLL_LH4", - "CLBLL_R_X31Y63/CLBLL_LH12", - "CLBLM_L_X32Y63/CLBLM_LH12", - "CLBLM_L_X36Y63/CLBLM_LH8", - "CLBLM_R_X25Y135/CLBLM_LH6", - "CLBLM_R_X27Y135/CLBLM_LH4", - "CLBLM_R_X29Y135/CLBLM_LH2", - "CLBLM_R_X33Y63/CLBLM_LH10", - "CLBLM_R_X35Y63/CLBLM_LH8", - "CLBLM_R_X39Y63/CLBLM_LH4", - "CLBLM_R_X41Y63/CLBLM_LH2", - "CLK_FEED_X60Y141/CLK_FEED_LH8", - "CLK_FEED_X60Y144/CLK_FEED_WW2END1", - "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_0", - "CMT_TOP_L_LOWER_B_X106Y61/CMT_TOP_LH2_13", - "DSP_L_X34Y60/DSP_LH10_3", - "HCLK_R_X78Y78/HCLK_LV11", - "HCLK_R_X78Y130/HCLK_LV7", - "INT_INTERFACE_L_X34Y63/INT_INTERFACE_LH10", - "INT_INTERFACE_L_X42Y63/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y135/INT_INTERFACE_LH8", - "INT_INTERFACE_R_X23Y138/INT_INTERFACE_WW2END1", - "INT_L_X24Y135/LH7", - "INT_L_X24Y138/WW2A1", - "INT_L_X26Y135/LH5", - "INT_L_X28Y135/LH3", - "INT_L_X30Y135/LH1", - "INT_L_X32Y63/LH11", - "INT_L_X34Y63/LH9", - "INT_L_X36Y63/LH7", - "INT_L_X38Y63/LH5", - "INT_L_X40Y63/LH3", - "INT_L_X42Y63/LH1", - "INT_R_X25Y135/LH6", - "INT_R_X25Y135/LV0", - "INT_R_X25Y136/LV1", - "INT_R_X25Y137/LV2", - "INT_R_X25Y138/LV3", - "INT_R_X25Y138/SS6END1", - "INT_R_X25Y138/WW2BEG1", - "INT_R_X25Y139/LV4", - "INT_R_X25Y139/SS6E1", - "INT_R_X25Y140/LV5", - "INT_R_X25Y140/SS6D1", - "INT_R_X25Y141/LV6", - "INT_R_X25Y141/SS6C1", - "INT_R_X25Y142/LV7", - "INT_R_X25Y142/SS6B1", - "INT_R_X25Y143/LV8", - "INT_R_X25Y143/SS6A1", - "INT_R_X25Y144/LV9", - "INT_R_X25Y144/SS6BEG1", - "INT_R_X25Y145/LV10", - "INT_R_X25Y146/LV0", - "INT_R_X25Y146/LV11", - "INT_R_X25Y147/LV1", - "INT_R_X25Y147/LV12", - "INT_R_X25Y148/LV2", - "INT_R_X25Y148/LV13", - "INT_R_X25Y149/LV3", - "INT_R_X25Y149/LV14", - "INT_R_X27Y135/LH4", - "INT_R_X29Y135/LH2", - "INT_R_X31Y63/LH12", - "INT_R_X31Y63/LV0", - "INT_R_X31Y64/LV1", - "INT_R_X31Y65/LV2", - "INT_R_X31Y66/LV3", - "INT_R_X31Y67/LV4", - "INT_R_X31Y68/LV5", - "INT_R_X31Y69/LV6", - "INT_R_X31Y70/LV7", - "INT_R_X31Y71/LV8", - "INT_R_X31Y72/LV9", - "INT_R_X31Y73/LV10", - "INT_R_X31Y74/LV11", - "INT_R_X31Y75/LV12", - "INT_R_X31Y76/LV13", - "INT_R_X31Y77/LV14", - "INT_R_X31Y78/LV15", - "INT_R_X31Y79/LV16", - "INT_R_X31Y80/LV17", - "INT_R_X31Y81/LV0", - "INT_R_X31Y81/LV18", - "INT_R_X31Y82/LV1", - "INT_R_X31Y83/LV2", - "INT_R_X31Y84/LV3", - "INT_R_X31Y85/LV4", - "INT_R_X31Y86/LV5", - "INT_R_X31Y87/LV6", - "INT_R_X31Y88/LV7", - "INT_R_X31Y89/LV8", - "INT_R_X31Y90/LV9", - "INT_R_X31Y91/LV10", - "INT_R_X31Y92/LV11", - "INT_R_X31Y93/LV12", - "INT_R_X31Y94/LV13", - "INT_R_X31Y95/LV14", - "INT_R_X31Y96/LV15", - "INT_R_X31Y97/LV16", - "INT_R_X31Y98/LV17", - "INT_R_X31Y99/LV0", - "INT_R_X31Y99/LV18", - "INT_R_X31Y100/LV1", - "INT_R_X31Y101/LV2", - "INT_R_X31Y102/LV3", - "INT_R_X31Y103/LV4", - "INT_R_X31Y104/LV5", - "INT_R_X31Y105/LV6", - "INT_R_X31Y106/LV7", - "INT_R_X31Y107/LV8", - "INT_R_X31Y108/LV9", - "INT_R_X31Y109/LV10", - "INT_R_X31Y110/LV11", - "INT_R_X31Y111/LV12", - "INT_R_X31Y112/LV13", - "INT_R_X31Y113/LV14", - "INT_R_X31Y114/LV15", - "INT_R_X31Y115/LV16", - "INT_R_X31Y116/LV17", - "INT_R_X31Y117/LV0", - "INT_R_X31Y117/LV18", - "INT_R_X31Y118/LV1", - "INT_R_X31Y119/LV2", - "INT_R_X31Y120/LV3", - "INT_R_X31Y121/LV4", - "INT_R_X31Y122/LV5", - "INT_R_X31Y123/LV6", - "INT_R_X31Y124/LV7", - "INT_R_X31Y125/LV8", - "INT_R_X31Y126/LV9", - "INT_R_X31Y127/LV10", - "INT_R_X31Y128/LV11", - "INT_R_X31Y129/LV12", - "INT_R_X31Y130/LV13", - "INT_R_X31Y131/LV14", - "INT_R_X31Y132/LV15", - "INT_R_X31Y133/LV16", - "INT_R_X31Y134/LV17", - "INT_R_X31Y135/LH0", - "INT_R_X31Y135/LV18", - "INT_R_X33Y63/LH10", - "INT_R_X35Y63/LH8", - "INT_R_X37Y63/LH6", - "INT_R_X39Y63/LH4", - "INT_R_X41Y63/LH2", - "INT_R_X43Y44/LOGIC_OUTS18", - "INT_R_X43Y44/NR1BEG0", - "INT_R_X43Y45/LV0", - "INT_R_X43Y45/NR1END0", - "INT_R_X43Y46/LV1", - "INT_R_X43Y47/LV2", - "INT_R_X43Y48/LV3", - "INT_R_X43Y49/LV4", - "INT_R_X43Y50/LV5", - "INT_R_X43Y51/LV6", - "INT_R_X43Y52/LV7", - "INT_R_X43Y53/LV8", - "INT_R_X43Y54/LV9", - "INT_R_X43Y55/LV10", - "INT_R_X43Y56/LV11", - "INT_R_X43Y57/LV12", - "INT_R_X43Y58/LV13", - "INT_R_X43Y59/LV14", - "INT_R_X43Y60/LV15", - "INT_R_X43Y61/LV16", - "INT_R_X43Y62/LV17", - "INT_R_X43Y63/LH0", - "INT_R_X43Y63/LV18", - "IO_INT_INTERFACE_R_X43Y44/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X43Y44/INT_INTERFACE_LOGIC_OUTS_B18", - "RIOB33_X43Y43/IOB_IBUF0", - "RIOI3_TBYTESRC_X43Y43/IOI_ILOGIC0_O", - "RIOI3_TBYTESRC_X43Y43/IOI_LOGIC_OUTS18_1", - "RIOI3_TBYTESRC_X43Y43/RIOI_I0", - "RIOI3_TBYTESRC_X43Y43/RIOI_IBUF0", - "RIOI3_TBYTESRC_X43Y43/RIOI_ILOGIC0_D", - "R_TERM_INT_X112Y46/TERM_INT_LOGIC_OUTS_L_B18", - "T_TERM_INT_X64Y156/T_TERM_INT_UTURN_LV_R3", - "VBRK_X61Y141/VBRK_LH8", - "VBRK_X61Y144/VBRK_WW2END1", - "VBRK_X66Y141/VBRK_LH6", - "VBRK_X80Y66/VBRK_LH12", - "VBRK_X85Y66/VBRK_LH10", - "VBRK_X96Y66/VBRK_LH6", - "VBRK_X105Y66/VBRK_LH2" - ] - }, - { - "name": "din[15]", - "node": "INT_R_X25Y140/WW2BEG1", - "pin": "R2", - "wire": "VBRK_X61Y146/VBRK_WW2END1", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y139/INT_INTERFACE_WW4B3", - "BRAM_INT_INTERFACE_R_X37Y67/INT_INTERFACE_LH6", - "BRAM_L_X30Y135/BRAM_WW4B3_4", - "BRAM_R_X37Y65/BRAM_LH6_2", - "BRKH_INT_X31Y99/BRKH_INT_LV14", - "BRKH_INT_X43Y49/BRKH_INT_LV0", - "CLBLL_L_X24Y140/CLBLL_WW2END1", - "CLBLL_L_X26Y140/CLBLL_WL1END1", - "CLBLL_L_X28Y139/CLBLL_WW4END3", - "CLBLL_L_X38Y67/CLBLL_LH6", - "CLBLL_L_X40Y67/CLBLL_LH4", - "CLBLL_R_X31Y67/CLBLL_LH12", - "CLBLM_L_X32Y67/CLBLM_LH12", - "CLBLM_L_X36Y67/CLBLM_LH8", - "CLBLM_R_X25Y140/CLBLM_WL1END1", - "CLBLM_R_X27Y139/CLBLM_WW4END3", - "CLBLM_R_X29Y139/CLBLM_WW4B3", - "CLBLM_R_X33Y67/CLBLM_LH10", - "CLBLM_R_X35Y67/CLBLM_LH8", - "CLBLM_R_X39Y67/CLBLM_LH4", - "CLBLM_R_X41Y67/CLBLM_LH2", - "CLK_FEED_X60Y146/CLK_FEED_WW2END1", - "CMT_FIFO_L_X107Y72/CMT_FIFO_LH2_4", - "CMT_TOP_L_LOWER_T_X106Y70/CMT_TOP_LH2_1", - "DSP_L_X34Y65/DSP_LH10_2", - "HCLK_R_X78Y78/HCLK_LV7", - "HCLK_R_X78Y130/HCLK_LV3", - "INT_INTERFACE_L_X34Y67/INT_INTERFACE_LH10", - "INT_INTERFACE_L_X42Y67/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y140/INT_INTERFACE_WW2END1", - "INT_L_X24Y140/WW2A1", - "INT_L_X26Y140/NW2END3", - "INT_L_X26Y140/WL1BEG1", - "INT_L_X28Y139/WW4C3", - "INT_L_X30Y139/WW4A3", - "INT_L_X32Y67/LH11", - "INT_L_X34Y67/LH9", - "INT_L_X36Y67/LH7", - "INT_L_X38Y67/LH5", - "INT_L_X40Y67/LH3", - "INT_L_X42Y67/LH1", - "INT_R_X25Y140/WL1END1", - "INT_R_X25Y140/WW2BEG1", - "INT_R_X27Y139/NW2BEG3", - "INT_R_X27Y139/WW4END3", - "INT_R_X27Y140/NW2A3", - "INT_R_X29Y139/WW4B3", - "INT_R_X31Y67/LH12", - "INT_R_X31Y67/LV0", - "INT_R_X31Y68/LV1", - "INT_R_X31Y69/LV2", - "INT_R_X31Y70/LV3", - "INT_R_X31Y71/LV4", - "INT_R_X31Y72/LV5", - "INT_R_X31Y73/LV6", - "INT_R_X31Y74/LV7", - "INT_R_X31Y75/LV8", - "INT_R_X31Y76/LV9", - "INT_R_X31Y77/LV10", - "INT_R_X31Y78/LV11", - "INT_R_X31Y79/LV12", - "INT_R_X31Y80/LV13", - "INT_R_X31Y81/LV14", - "INT_R_X31Y82/LV15", - "INT_R_X31Y83/LV16", - "INT_R_X31Y84/LV17", - "INT_R_X31Y85/LV0", - "INT_R_X31Y85/LV18", - "INT_R_X31Y86/LV1", - "INT_R_X31Y87/LV2", - "INT_R_X31Y88/LV3", - "INT_R_X31Y89/LV4", - "INT_R_X31Y90/LV5", - "INT_R_X31Y91/LV6", - "INT_R_X31Y92/LV7", - "INT_R_X31Y93/LV8", - "INT_R_X31Y94/LV9", - "INT_R_X31Y95/LV10", - "INT_R_X31Y96/LV11", - "INT_R_X31Y97/LV12", - "INT_R_X31Y98/LV13", - "INT_R_X31Y99/LV14", - "INT_R_X31Y100/LV15", - "INT_R_X31Y101/LV16", - "INT_R_X31Y102/LV17", - "INT_R_X31Y103/LV0", - "INT_R_X31Y103/LV18", - "INT_R_X31Y104/LV1", - "INT_R_X31Y105/LV2", - "INT_R_X31Y106/LV3", - "INT_R_X31Y107/LV4", - "INT_R_X31Y108/LV5", - "INT_R_X31Y109/LV6", - "INT_R_X31Y110/LV7", - "INT_R_X31Y111/LV8", - "INT_R_X31Y112/LV9", - "INT_R_X31Y113/LV10", - "INT_R_X31Y114/LV11", - "INT_R_X31Y115/LV12", - "INT_R_X31Y116/LV13", - "INT_R_X31Y117/LV14", - "INT_R_X31Y118/LV15", - "INT_R_X31Y119/LV16", - "INT_R_X31Y120/LV17", - "INT_R_X31Y121/LV0", - "INT_R_X31Y121/LV18", - "INT_R_X31Y122/LV1", - "INT_R_X31Y123/LV2", - "INT_R_X31Y124/LV3", - "INT_R_X31Y125/LV4", - "INT_R_X31Y126/LV5", - "INT_R_X31Y127/LV6", - "INT_R_X31Y128/LV7", - "INT_R_X31Y129/LV8", - "INT_R_X31Y130/LV9", - "INT_R_X31Y131/LV10", - "INT_R_X31Y132/LV11", - "INT_R_X31Y133/LV12", - "INT_R_X31Y134/LV13", - "INT_R_X31Y135/LV14", - "INT_R_X31Y136/LV15", - "INT_R_X31Y137/LV16", - "INT_R_X31Y138/LV17", - "INT_R_X31Y139/LV18", - "INT_R_X31Y139/WW4BEG3", - "INT_R_X33Y67/LH10", - "INT_R_X35Y67/LH8", - "INT_R_X37Y67/LH6", - "INT_R_X39Y67/LH4", - "INT_R_X41Y67/LH2", - "INT_R_X43Y48/LOGIC_OUTS18", - "INT_R_X43Y48/NR1BEG0", - "INT_R_X43Y49/LV0", - "INT_R_X43Y49/NR1END0", - "INT_R_X43Y50/LV1", - "INT_R_X43Y51/LV2", - "INT_R_X43Y52/LV3", - "INT_R_X43Y53/LV4", - "INT_R_X43Y54/LV5", - "INT_R_X43Y55/LV6", - "INT_R_X43Y56/LV7", - "INT_R_X43Y57/LV8", - "INT_R_X43Y58/LV9", - "INT_R_X43Y59/LV10", - "INT_R_X43Y60/LV11", - "INT_R_X43Y61/LV12", - "INT_R_X43Y62/LV13", - "INT_R_X43Y63/LV14", - "INT_R_X43Y64/LV15", - "INT_R_X43Y65/LV16", - "INT_R_X43Y66/LV17", - "INT_R_X43Y67/LH0", - "INT_R_X43Y67/LV18", - "IO_INT_INTERFACE_R_X43Y48/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X43Y48/INT_INTERFACE_LOGIC_OUTS_B18", - "RIOB33_X43Y47/IOB_IBUF0", - "RIOI3_X43Y47/IOI_ILOGIC0_O", - "RIOI3_X43Y47/IOI_LOGIC_OUTS18_1", - "RIOI3_X43Y47/RIOI_I0", - "RIOI3_X43Y47/RIOI_IBUF0", - "RIOI3_X43Y47/RIOI_ILOGIC0_D", - "R_TERM_INT_X112Y50/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X61Y146/VBRK_WW2END1", - "VBRK_X66Y146/VBRK_WL1END1", - "VBRK_X80Y70/VBRK_LH12", - "VBRK_X85Y70/VBRK_LH10", - "VBRK_X96Y70/VBRK_LH6", - "VBRK_X105Y70/VBRK_LH2" - ] - }, - { - "name": "din[16]", - "node": "INT_L_X0Y118/EE2BEG2", - "pin": "B18", - "wire": "VBRK_X9Y123/VBRK_EE2A2", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_5", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_2", - "INT_INTERFACE_R_X1Y118/INT_INTERFACE_EE2A2", - "INT_L_X0Y112/LOGIC_OUTS_L18", - "INT_L_X0Y112/NE6A0", - "INT_L_X0Y112/NW6BEG0", - "INT_L_X0Y113/NE6B0", - "INT_L_X0Y114/NE6C0", - "INT_L_X0Y115/NE6D0", - "INT_L_X0Y116/NE6E0", - "INT_L_X0Y118/EE2BEG2", - "INT_L_X0Y118/EL1END2", - "INT_L_X0Y118/NW2END_S0_0", - "INT_L_X0Y118/WL1BEG2", - "INT_L_X0Y119/NW2END0", - "INT_R_X1Y116/NE6END0", - "INT_R_X1Y116/NN2BEG0", - "INT_R_X1Y117/NN2A0", - "INT_R_X1Y117/NN2END_S2_0", - "INT_R_X1Y118/EE2A2", - "INT_R_X1Y118/NN2END0", - "INT_R_X1Y118/NW2BEG0", - "INT_R_X1Y119/NW2A0", - "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_LOGIC_OUTS_L_B18", - "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_NE4BEG0", - "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_NW4A0", - "IO_INT_INTERFACE_L_X0Y118/INT_INTERFACE_EL1BEG2", - "IO_INT_INTERFACE_L_X0Y118/INT_INTERFACE_WL1END2", - "LIOB33_X0Y111/IOB_IBUF0", - "LIOI3_X0Y111/IOI_ILOGIC0_O", - "LIOI3_X0Y111/IOI_LOGIC_OUTS18_1", - "LIOI3_X0Y111/LIOI_I0", - "LIOI3_X0Y111/LIOI_IBUF0", - "LIOI3_X0Y111/LIOI_ILOGIC0_D", - "L_TERM_INT_X2Y117/L_TERM_INT_NW4BEG0", - "L_TERM_INT_X2Y117/TERM_INT_LOGIC_OUTS_L_B18", - "L_TERM_INT_X2Y123/L_TERM_INT_WL1BEG2", - "VBRK_X9Y123/VBRK_EE2A2" - ] - }, - { - "name": "dout[0]", - "node": "INT_L_X2Y115/SW6BEG0", - "pin": "U16", - "wire": "VBRK_X9Y120/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_2", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_SW4A0_15", - "INT_INTERFACE_R_X1Y115/INT_INTERFACE_SW4A0", - "INT_L_X0Y111/SW6END0", - "INT_R_X1Y111/SW6E0", - "INT_R_X1Y112/SW6D0", - "INT_R_X1Y113/SW6C0", - "INT_R_X1Y114/SW6B0", - "INT_R_X1Y115/SW6A0", - "VBRK_X9Y120/VBRK_SW4A0" - ] - }, - { - "name": "dout[1]", - "node": "INT_L_X2Y117/SW6BEG0", - "pin": "E19", - "wire": "VBRK_X9Y122/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_4", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_1", - "INT_INTERFACE_R_X1Y117/INT_INTERFACE_SW4A0", - "INT_L_X0Y113/SW6END0", - "INT_R_X1Y113/SW6E0", - "INT_R_X1Y114/SW6D0", - "INT_R_X1Y115/SW6C0", - "INT_R_X1Y116/SW6B0", - "INT_R_X1Y117/SW6A0", - "VBRK_X9Y122/VBRK_SW4A0" - ] - }, - { - "name": "dout[2]", - "node": "INT_L_X2Y119/SW6BEG0", - "pin": "U19", - "wire": "VBRK_X9Y124/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_6", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_3", - "INT_INTERFACE_R_X1Y119/INT_INTERFACE_SW4A0", - "INT_L_X0Y115/SW6END0", - "INT_R_X1Y115/SW6E0", - "INT_R_X1Y116/SW6D0", - "INT_R_X1Y117/SW6C0", - "INT_R_X1Y118/SW6B0", - "INT_R_X1Y119/SW6A0", - "VBRK_X9Y124/VBRK_SW4A0" - ] - }, - { - "name": "dout[3]", - "node": "INT_L_X2Y121/SW6BEG0", - "pin": "V19", - "wire": "VBRK_X9Y126/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_8", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_5", - "INT_INTERFACE_R_X1Y121/INT_INTERFACE_SW4A0", - "INT_L_X0Y117/SW6END0", - "INT_R_X1Y117/SW6E0", - "INT_R_X1Y118/SW6D0", - "INT_R_X1Y119/SW6C0", - "INT_R_X1Y120/SW6B0", - "INT_R_X1Y121/SW6A0", - "VBRK_X9Y126/VBRK_SW4A0" - ] - }, - { - "name": "dout[4]", - "node": "INT_L_X2Y123/SW6BEG0", - "pin": "W18", - "wire": "VBRK_X9Y128/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_10", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_7", - "INT_INTERFACE_R_X1Y123/INT_INTERFACE_SW4A0", - "INT_L_X0Y119/SW6END0", - "INT_R_X1Y119/SW6E0", - "INT_R_X1Y120/SW6D0", - "INT_R_X1Y121/SW6C0", - "INT_R_X1Y122/SW6B0", - "INT_R_X1Y123/SW6A0", - "VBRK_X9Y128/VBRK_SW4A0" - ] - }, - { - "name": "dout[5]", - "node": "INT_L_X2Y125/SW6BEG0", - "pin": "U15", - "wire": "VBRK_X9Y131/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_0", - "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_0", - "HCLK_R_X5Y130/HCLK_SW6B0", - "INT_INTERFACE_R_X1Y125/INT_INTERFACE_SW4A0", - "INT_L_X0Y121/SW6END0", - "INT_R_X1Y121/SW6E0", - "INT_R_X1Y122/SW6D0", - "INT_R_X1Y123/SW6C0", - "INT_R_X1Y124/SW6B0", - "INT_R_X1Y125/SW6A0", - "VBRK_X9Y131/VBRK_SW4A0" - ] - }, - { - "name": "dout[6]", - "node": "INT_L_X2Y127/SW6BEG0", - "pin": "U14", - "wire": "VBRK_X9Y133/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_2", - "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_2", - "HCLK_R_X5Y130/HCLK_SW6D0", - "INT_INTERFACE_R_X1Y127/INT_INTERFACE_SW4A0", - "INT_L_X0Y123/SW6END0", - "INT_R_X1Y123/SW6E0", - "INT_R_X1Y124/SW6D0", - "INT_R_X1Y125/SW6C0", - "INT_R_X1Y126/SW6B0", - "INT_R_X1Y127/SW6A0", - "VBRK_X9Y133/VBRK_SW4A0" - ] - }, - { - "name": "dout[7]", - "node": "INT_L_X2Y129/SW6BEG0", - "pin": "V14", - "wire": "VBRK_X9Y135/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_4", - "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_4", - "INT_INTERFACE_R_X1Y129/INT_INTERFACE_SW4A0", - "INT_L_X0Y125/SW6END0", - "INT_R_X1Y125/SW6E0", - "INT_R_X1Y126/SW6D0", - "INT_R_X1Y127/SW6C0", - "INT_R_X1Y128/SW6B0", - "INT_R_X1Y129/SW6A0", - "VBRK_X9Y135/VBRK_SW4A0" - ] - }, - { - "name": "dout[8]", - "node": "INT_L_X2Y131/SW6BEG0", - "pin": "V13", - "wire": "VBRK_X9Y137/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_6", - "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_6", - "INT_INTERFACE_R_X1Y131/INT_INTERFACE_SW4A0", - "INT_L_X0Y127/SW6END0", - "INT_R_X1Y127/SW6E0", - "INT_R_X1Y128/SW6D0", - "INT_R_X1Y129/SW6C0", - "INT_R_X1Y130/SW6B0", - "INT_R_X1Y131/SW6A0", - "VBRK_X9Y137/VBRK_SW4A0" - ] - }, - { - "name": "dout[9]", - "node": "INT_R_X23Y115/LH12", - "pin": "V3", - "wire": "VBRK_X61Y120/VBRK_LH12", - "wires_outside_roi": [ - "CLBLL_L_X24Y115/CLBLL_LH12", - "CLBLL_L_X26Y115/CLBLL_LH10", - "CLBLL_R_X31Y115/CLBLL_LH6", - "CLBLM_L_X32Y115/CLBLM_LH6", - "CLBLM_L_X36Y115/CLBLM_LH2", - "CLBLM_R_X25Y115/CLBLM_LH10", - "CLBLM_R_X33Y115/CLBLM_LH4", - "CLBLM_R_X35Y115/CLBLM_LH2", - "CLK_FEED_X60Y120/CLK_FEED_LH12", - "DSP_L_X34Y115/DSP_LH4_0", - "INT_INTERFACE_L_X34Y115/INT_INTERFACE_LH4", - "INT_INTERFACE_R_X23Y115/INT_INTERFACE_LH12", - "INT_L_X24Y115/LH11", - "INT_L_X26Y115/LH9", - "INT_L_X30Y115/LH7", - "INT_L_X32Y115/LH5", - "INT_L_X34Y115/LH3", - "INT_L_X36Y115/LH1", - "INT_R_X25Y115/LH10", - "INT_R_X27Y115/LH8", - "INT_R_X31Y115/LH6", - "INT_R_X33Y115/LH4", - "INT_R_X35Y115/LH2", - "INT_R_X37Y115/LH0", - "PCIE_BOT_X71Y115/PCIE_LH8_15", - "PCIE_INT_INTERFACE_L_X30Y115/INT_INTERFACE_LH8", - "PCIE_INT_INTERFACE_R_X27Y115/INT_INTERFACE_LH8", - "VBRK_X61Y120/VBRK_LH12", - "VBRK_X66Y120/VBRK_LH10", - "VBRK_X80Y120/VBRK_LH6", - "VBRK_X85Y120/VBRK_LH4" - ] - }, - { - "name": "dout[10]", - "node": "INT_R_X23Y117/LH12", - "pin": "W3", - "wire": "VBRK_X61Y122/VBRK_LH12", - "wires_outside_roi": [ - "CLBLL_L_X24Y117/CLBLL_LH12", - "CLBLL_L_X26Y117/CLBLL_LH10", - "CLBLL_R_X31Y117/CLBLL_LH6", - "CLBLM_L_X32Y117/CLBLM_LH6", - "CLBLM_L_X36Y117/CLBLM_LH2", - "CLBLM_R_X25Y117/CLBLM_LH10", - "CLBLM_R_X33Y117/CLBLM_LH4", - "CLBLM_R_X35Y117/CLBLM_LH2", - "CLK_FEED_X60Y122/CLK_FEED_LH12", - "DSP_L_X34Y115/DSP_LH4_2", - "INT_INTERFACE_L_X34Y117/INT_INTERFACE_LH4", - "INT_INTERFACE_R_X23Y117/INT_INTERFACE_LH12", - "INT_L_X24Y117/LH11", - "INT_L_X26Y117/LH9", - "INT_L_X30Y117/LH7", - "INT_L_X32Y117/LH5", - "INT_L_X34Y117/LH3", - "INT_L_X36Y117/LH1", - "INT_R_X25Y117/LH10", - "INT_R_X27Y117/LH8", - "INT_R_X31Y117/LH6", - "INT_R_X33Y117/LH4", - "INT_R_X35Y117/LH2", - "INT_R_X37Y117/LH0", - "PCIE_BOT_X71Y115/PCIE_LH8_17", - "PCIE_INT_INTERFACE_L_X30Y117/INT_INTERFACE_LH8", - "PCIE_INT_INTERFACE_R_X27Y117/INT_INTERFACE_LH8", - "VBRK_X61Y122/VBRK_LH12", - "VBRK_X66Y122/VBRK_LH10", - "VBRK_X80Y122/VBRK_LH6", - "VBRK_X85Y122/VBRK_LH4" - ] - }, - { - "name": "dout[11]", - "node": "INT_R_X23Y119/LH12", - "pin": "U3", - "wire": "VBRK_X61Y124/VBRK_LH12", - "wires_outside_roi": [ - "CLBLL_L_X24Y119/CLBLL_LH12", - "CLBLL_L_X26Y119/CLBLL_LH10", - "CLBLL_R_X31Y119/CLBLL_LH6", - "CLBLM_L_X32Y119/CLBLM_LH6", - "CLBLM_L_X36Y119/CLBLM_LH2", - "CLBLM_R_X25Y119/CLBLM_LH10", - "CLBLM_R_X33Y119/CLBLM_LH4", - "CLBLM_R_X35Y119/CLBLM_LH2", - "CLK_FEED_X60Y124/CLK_FEED_LH12", - "DSP_L_X34Y115/DSP_LH4_4", - "INT_INTERFACE_L_X34Y119/INT_INTERFACE_LH4", - "INT_INTERFACE_R_X23Y119/INT_INTERFACE_LH12", - "INT_L_X24Y119/LH11", - "INT_L_X26Y119/LH9", - "INT_L_X30Y119/LH7", - "INT_L_X32Y119/LH5", - "INT_L_X34Y119/LH3", - "INT_L_X36Y119/LH1", - "INT_R_X25Y119/LH10", - "INT_R_X27Y119/LH8", - "INT_R_X31Y119/LH6", - "INT_R_X33Y119/LH4", - "INT_R_X35Y119/LH2", - "INT_R_X37Y119/LH0", - "PCIE_BOT_X71Y115/PCIE_LH8_19", - "PCIE_INT_INTERFACE_L_X30Y119/INT_INTERFACE_LH8", - "PCIE_INT_INTERFACE_R_X27Y119/INT_INTERFACE_LH8", - "VBRK_X61Y124/VBRK_LH12", - "VBRK_X66Y124/VBRK_LH10", - "VBRK_X80Y124/VBRK_LH6", - "VBRK_X85Y124/VBRK_LH4" - ] - }, - { - "name": "dout[12]", - "node": "INT_R_X23Y121/LH12", - "pin": "P3", - "wire": "VBRK_X61Y126/VBRK_LH12", - "wires_outside_roi": [ - "CLBLL_L_X24Y121/CLBLL_LH12", - "CLBLL_L_X26Y121/CLBLL_LH10", - "CLBLL_R_X31Y121/CLBLL_LH6", - "CLBLM_L_X32Y121/CLBLM_LH6", - "CLBLM_L_X36Y121/CLBLM_LH2", - "CLBLM_R_X25Y121/CLBLM_LH10", - "CLBLM_R_X33Y121/CLBLM_LH4", - "CLBLM_R_X35Y121/CLBLM_LH2", - "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_0", - "DSP_L_X34Y120/DSP_LH4_1", - "INT_INTERFACE_L_X34Y121/INT_INTERFACE_LH4", - "INT_INTERFACE_R_X23Y121/INT_INTERFACE_LH12", - "INT_L_X24Y121/LH11", - "INT_L_X26Y121/LH9", - "INT_L_X30Y121/LH7", - "INT_L_X32Y121/LH5", - "INT_L_X34Y121/LH3", - "INT_L_X36Y121/LH1", - "INT_R_X25Y121/LH10", - "INT_R_X27Y121/LH8", - "INT_R_X31Y121/LH6", - "INT_R_X33Y121/LH4", - "INT_R_X35Y121/LH2", - "INT_R_X37Y121/LH0", - "PCIE_INT_INTERFACE_L_X30Y121/INT_INTERFACE_LH8", - "PCIE_INT_INTERFACE_R_X27Y121/INT_INTERFACE_LH8", - "PCIE_TOP_X71Y125/PCIE_LH8_1", - "VBRK_X61Y126/VBRK_LH12", - "VBRK_X66Y126/VBRK_LH10", - "VBRK_X80Y126/VBRK_LH6", - "VBRK_X85Y126/VBRK_LH4" - ] - }, - { - "name": "dout[13]", - "node": "INT_R_X23Y123/LH12", - "pin": "N3", - "wire": "VBRK_X61Y128/VBRK_LH12", - "wires_outside_roi": [ - "CLBLL_L_X24Y123/CLBLL_LH12", - "CLBLL_L_X26Y123/CLBLL_LH10", - "CLBLL_R_X31Y123/CLBLL_LH6", - "CLBLM_L_X32Y123/CLBLM_LH6", - "CLBLM_L_X36Y123/CLBLM_LH2", - "CLBLM_R_X25Y123/CLBLM_LH10", - "CLBLM_R_X33Y123/CLBLM_LH4", - "CLBLM_R_X35Y123/CLBLM_LH2", - "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_2", - "DSP_L_X34Y120/DSP_LH4_3", - "INT_INTERFACE_L_X34Y123/INT_INTERFACE_LH4", - "INT_INTERFACE_R_X23Y123/INT_INTERFACE_LH12", - "INT_L_X24Y123/LH11", - "INT_L_X26Y123/LH9", - "INT_L_X30Y123/LH7", - "INT_L_X32Y123/LH5", - "INT_L_X34Y123/LH3", - "INT_L_X36Y123/LH1", - "INT_R_X25Y123/LH10", - "INT_R_X27Y123/LH8", - "INT_R_X31Y123/LH6", - "INT_R_X33Y123/LH4", - "INT_R_X35Y123/LH2", - "INT_R_X37Y123/LH0", - "PCIE_INT_INTERFACE_L_X30Y123/INT_INTERFACE_LH8", - "PCIE_INT_INTERFACE_R_X27Y123/INT_INTERFACE_LH8", - "PCIE_TOP_X71Y125/PCIE_LH8_3", - "VBRK_X61Y128/VBRK_LH12", - "VBRK_X66Y128/VBRK_LH10", - "VBRK_X80Y128/VBRK_LH6", - "VBRK_X85Y128/VBRK_LH4" - ] - }, - { - "name": "dout[14]", - "node": "INT_R_X23Y125/LH12", - "pin": "P1", - "wire": "VBRK_X61Y131/VBRK_LH12", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y125/INT_INTERFACE_LH6", - "BRAM_L_X30Y125/BRAM_LH6_0", - "CLBLL_L_X24Y125/CLBLL_LH12", - "CLBLL_L_X26Y125/CLBLL_LH10", - "CLBLL_L_X28Y125/CLBLL_LH8", - "CLBLL_R_X31Y125/CLBLL_LH4", - "CLBLM_L_X32Y125/CLBLM_LH4", - "CLBLM_R_X25Y125/CLBLM_LH10", - "CLBLM_R_X27Y125/CLBLM_LH8", - "CLBLM_R_X29Y125/CLBLM_LH6", - "CLBLM_R_X33Y125/CLBLM_LH2", - "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_4", - "DSP_L_X34Y125/DSP_LH2_0", - "INT_INTERFACE_L_X34Y125/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y125/INT_INTERFACE_LH12", - "INT_L_X24Y125/LH11", - "INT_L_X26Y125/LH9", - "INT_L_X28Y125/LH7", - "INT_L_X30Y125/LH5", - "INT_L_X32Y125/LH3", - "INT_L_X34Y125/LH1", - "INT_R_X25Y125/LH10", - "INT_R_X27Y125/LH8", - "INT_R_X29Y125/LH6", - "INT_R_X31Y125/LH4", - "INT_R_X33Y125/LH2", - "INT_R_X35Y125/LH0", - "VBRK_X61Y131/VBRK_LH12", - "VBRK_X66Y131/VBRK_LH10", - "VBRK_X80Y131/VBRK_LH4", - "VBRK_X85Y131/VBRK_LH2" - ] - }, - { - "name": "dout[15]", - "node": "INT_R_X23Y127/LH12", - "pin": "L1", - "wire": "VBRK_X61Y133/VBRK_LH12", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y127/INT_INTERFACE_LH6", - "BRAM_L_X30Y125/BRAM_LH6_2", - "CLBLL_L_X24Y127/CLBLL_LH12", - "CLBLL_L_X26Y127/CLBLL_LH10", - "CLBLL_L_X28Y127/CLBLL_LH8", - "CLBLL_R_X31Y127/CLBLL_LH4", - "CLBLM_L_X32Y127/CLBLM_LH4", - "CLBLM_R_X25Y127/CLBLM_LH10", - "CLBLM_R_X27Y127/CLBLM_LH8", - "CLBLM_R_X29Y127/CLBLM_LH6", - "CLBLM_R_X33Y127/CLBLM_LH2", - "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_6", - "DSP_L_X34Y125/DSP_LH2_2", - "INT_INTERFACE_L_X34Y127/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y127/INT_INTERFACE_LH12", - "INT_L_X24Y127/LH11", - "INT_L_X26Y127/LH9", - "INT_L_X28Y127/LH7", - "INT_L_X30Y127/LH5", - "INT_L_X32Y127/LH3", - "INT_L_X34Y127/LH1", - "INT_R_X25Y127/LH10", - "INT_R_X27Y127/LH8", - "INT_R_X29Y127/LH6", - "INT_R_X31Y127/LH4", - "INT_R_X33Y127/LH2", - "INT_R_X35Y127/LH0", - "VBRK_X61Y133/VBRK_LH12", - "VBRK_X66Y133/VBRK_LH10", - "VBRK_X80Y133/VBRK_LH4", - "VBRK_X85Y133/VBRK_LH2" - ] - }, - { - "name": "dout[16]", - "node": "INT_L_X2Y133/SW6BEG0", - "pin": "A18", - "wire": "VBRK_X9Y139/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_8", - "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_8", - "INT_INTERFACE_R_X1Y133/INT_INTERFACE_SW4A0", - "INT_L_X0Y129/SW6END0", - "INT_R_X1Y129/SW6E0", - "INT_R_X1Y130/SW6D0", - "INT_R_X1Y131/SW6C0", - "INT_R_X1Y132/SW6B0", - "INT_R_X1Y133/SW6A0", - "VBRK_X9Y139/VBRK_SW4A0" - ] - } - ], - "required_features": [ - "", - "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE", - "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED", - "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0", - "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_BOT_R_CK_MUXED0", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3", - "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_CK_GCLK0.CLK_BUFG_BUFGCTRL0_O", - "CLK_BUFG_REBUF_X60Y38.GCLK0_ENABLE_BELOW", - "CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT", - "CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_ABOVE", - "CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_BELOW", - "CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT", - "CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_ABOVE", - "CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_BELOW", - "CLK_BUFG_REBUF_X60Y117.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT", - "CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_ABOVE", - "CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_BELOW", - "CLK_BUFG_REBUF_X60Y142.GCLK0_ENABLE_ABOVE", - "CLK_HROW_BOT_R_X60Y26.CLK_HROW_BOT_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0", - "CLK_HROW_BOT_R_X60Y26.CLK_HROW_CK_IN_R0_ACTIVE", - "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK0_ACTIVE", - "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE", - "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE", - "CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK0", - "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE", - "HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_ACTIVE", - "HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_USED", - "HCLK_CMT_L_X106Y26.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0", - "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_USED", - "INT_L_X0Y0.IMUX_L34.SS2END1", - "INT_L_X0Y1.IMUX_L34.WW2END0", - "INT_L_X0Y2.IMUX_L34.SS2END1", - "INT_L_X0Y2.SS2BEG1.SR1END1", - "INT_L_X0Y3.IMUX_L34.WW2END0", - "INT_L_X0Y3.SR1BEG1.SS6END0", - "INT_L_X0Y4.IMUX_L34.SR1BEG_S0", - "INT_L_X0Y4.SR1BEG_S0.WL1END3", - "INT_L_X0Y4.SS2BEG1.SR1END1", - "INT_L_X0Y5.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y5.SR1BEG1.SS2END0", - "INT_L_X0Y6.LV_L0.NR1END0", - "INT_L_X0Y6.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y7.LV_L0.NR1END0", - "INT_L_X0Y7.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y7.SS2BEG0.SS6END0", - "INT_L_X0Y8.LV_L0.NR1END0", - "INT_L_X0Y8.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y9.LV_L0.NR1END0", - "INT_L_X0Y9.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y9.SS6BEG0.SS6END0", - "INT_L_X0Y10.LV_L0.NR1END0", - "INT_L_X0Y10.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y11.LV_L0.NR1END0", - "INT_L_X0Y11.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y12.LV_L0.NR1END0", - "INT_L_X0Y12.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y13.LV_L0.NR1END0", - "INT_L_X0Y13.SE6BEG0.SS2END0", - "INT_L_X0Y13.SS6BEG0.SS6END0", - "INT_L_X0Y15.SS2BEG0.SS6END0", - "INT_L_X0Y15.SS6BEG0.LV_L0", - "INT_L_X0Y17.NR1BEG1.EL1END1", - "INT_L_X0Y17.SE6BEG0.LV_L0", - "INT_L_X0Y17.WL1BEG1.SS6END2", - "INT_L_X0Y18.IMUX_L34.NR1END1", - "INT_L_X0Y19.FAN_ALT1.SS2END2", - "INT_L_X0Y19.IMUX_L34.FAN_BOUNCE1", - "INT_L_X0Y19.SS6BEG0.LV_L0", - "INT_L_X0Y20.FAN_ALT1.EL1END3", - "INT_L_X0Y20.IMUX_L34.FAN_BOUNCE1", - "INT_L_X0Y21.SS2BEG2.SS6END2", - "INT_L_X0Y21.SS6BEG0.LV_L0", - "INT_L_X0Y21.WL1BEG_N3.SS6END0", - "INT_L_X0Y23.SS6BEG2.SS6END2", - "INT_L_X0Y24.LV_L0.LV_L18", - "INT_L_X0Y25.LV_L0.LV_L18", - "INT_L_X0Y26.LV_L0.LV_L18", - "INT_L_X0Y27.LV_L0.LV_L18", - "INT_L_X0Y27.SS6BEG0.SS6END0", - "INT_L_X0Y27.SS6BEG2.SS6END2", - "INT_L_X0Y28.LV_L0.LV_L18", - "INT_L_X0Y29.LV_L0.LV_L18", - "INT_L_X0Y29.SS6BEG2.SS6END2", - "INT_L_X0Y30.LV_L0.LV_L18", - "INT_L_X0Y31.LV_L0.LV_L18", - "INT_L_X0Y33.LV_L18.LV_L0", - "INT_L_X0Y33.SS6BEG0.SS6END0", - "INT_L_X0Y33.SS6BEG2.SS6END2", - "INT_L_X0Y35.LV_L18.LV_L0", - "INT_L_X0Y35.SS6BEG2.SS6END2", - "INT_L_X0Y37.LV_L18.LV_L0", - "INT_L_X0Y39.LV_L18.LV_L0", - "INT_L_X0Y39.SS6BEG0.SS6END0", - "INT_L_X0Y39.SS6BEG2.SS6END2", - "INT_L_X0Y41.SS6BEG2.SS6END2", - "INT_L_X0Y42.LV_L0.LV_L18", - "INT_L_X0Y43.IMUX_L34.WW2END0", - "INT_L_X0Y43.LV_L0.LV_L18", - "INT_L_X0Y44.LV_L0.LV_L18", - "INT_L_X0Y45.LV_L0.LV_L18", - "INT_L_X0Y45.SS6BEG0.SS6END0", - "INT_L_X0Y45.SS6BEG2.SS6END2", - "INT_L_X0Y46.LV_L0.LV_L18", - "INT_L_X0Y47.LV_L0.LV_L18", - "INT_L_X0Y47.SS6BEG2.SS6END2", - "INT_L_X0Y48.LV_L0.LV_L18", - "INT_L_X0Y49.LV_L0.LV_L18", - "INT_L_X0Y51.LV_L18.LV_L0", - "INT_L_X0Y51.SS6BEG0.SS6END0", - "INT_L_X0Y51.SS6BEG2.SS6END2", - "INT_L_X0Y53.LV_L18.LV_L0", - "INT_L_X0Y53.SE6BEG0.SS6END0", - "INT_L_X0Y53.SS6BEG2.SS6END2", - "INT_L_X0Y55.LV_L18.LV_L0", - "INT_L_X0Y57.LV_L18.LV_L0", - "INT_L_X0Y57.SS6BEG0.SS6END0", - "INT_L_X0Y57.SS6BEG2.SS6END2", - "INT_L_X0Y59.SS6BEG0.LV_L0", - "INT_L_X0Y59.SS6BEG2.SS6END2", - "INT_L_X0Y60.LV_L0.LV_L18", - "INT_L_X0Y61.LV_L0.LV_L18", - "INT_L_X0Y62.LV_L0.LV_L18", - "INT_L_X0Y63.LV_L0.LV_L18", - "INT_L_X0Y63.SS6BEG0.SS6END0", - "INT_L_X0Y63.SS6BEG2.SS6END2", - "INT_L_X0Y64.LV_L0.LV_L18", - "INT_L_X0Y65.LV_L0.LV_L18", - "INT_L_X0Y65.SS6BEG2.SS6END2", - "INT_L_X0Y66.LV_L0.LV_L18", - "INT_L_X0Y67.LV_L0.LV_L18", - "INT_L_X0Y69.LV_L18.LV_L0", - "INT_L_X0Y69.SS6BEG0.SS6END0", - "INT_L_X0Y69.SS6BEG2.SS6END2", - "INT_L_X0Y71.LV_L18.LV_L0", - "INT_L_X0Y71.SS6BEG2.SS6END2", - "INT_L_X0Y73.LV_L18.LV_L0", - "INT_L_X0Y75.LV_L18.LV_L0", - "INT_L_X0Y75.SS6BEG0.SS6END0", - "INT_L_X0Y75.SS6BEG2.LVB_L0", - "INT_L_X0Y77.LV_L18.LV_L0", - "INT_L_X0Y77.SS6BEG2.LVB_L0", - "INT_L_X0Y77.SW6BEG0.SW6END0", - "INT_L_X0Y78.LV_L0.LV_L18", - "INT_L_X0Y79.LV_L0.LV_L18", - "INT_L_X0Y80.LVB_L0.LV_L18", - "INT_L_X0Y81.LV_L0.LV_L18", - "INT_L_X0Y81.SS6BEG0.SW6END0", - "INT_L_X0Y82.LV_L0.LV_L18", - "INT_L_X0Y83.LV_L0.LV_L18", - "INT_L_X0Y84.LVB_L0.LV_L18", - "INT_L_X0Y85.LVB_L0.LV_L18", - "INT_L_X0Y85.SE6BEG0.LV_L0", - "INT_L_X0Y87.LVB_L12.LVB_L0", - "INT_L_X0Y87.LV_L18.LV_L0", - "INT_L_X0Y89.LVB_L12.LVB_L0", - "INT_L_X0Y89.LV_L18.LV_L0", - "INT_L_X0Y89.SE6BEG0.SW6END0", - "INT_L_X0Y91.LV_L18.LV_L0", - "INT_L_X0Y92.LVB_L0.LVB_L12", - "INT_L_X0Y93.LV_L18.LV_L0", - "INT_L_X0Y95.LV_L18.LV_L0", - "INT_L_X0Y96.LVB_L0.LV_L18", - "INT_L_X0Y96.NN6BEG2.LVB_L12", - "INT_L_X0Y97.LVB_L0.LV_L18", - "INT_L_X0Y97.NN6BEG2.LVB_L12", - "INT_L_X0Y97.SE6BEG0.LV_L0", - "INT_L_X0Y99.LVB_L12.LV_L0", - "INT_L_X0Y99.NN6BEG3.LV_L18", - "INT_L_X0Y100.NN6BEG3.LV_L18", - "INT_L_X0Y101.LVB_L12.LV_L0", - "INT_L_X0Y101.NN6BEG3.LV_L18", - "INT_L_X0Y102.EE2BEG2.NN6END2", - "INT_L_X0Y103.LV_L18.LV_L0", - "INT_L_X0Y103.NR1BEG2.NN6END2", - "INT_L_X0Y104.EE2BEG2.NR1END2", - "INT_L_X0Y104.NN6BEG2.LVB_L12", - "INT_L_X0Y105.LV_L18.LV_L0", - "INT_L_X0Y105.NN6BEG3.NN6END3", - "INT_L_X0Y106.EE2BEG2.EL1END2", - "INT_L_X0Y106.NR1BEG3.NN6END3", - "INT_L_X0Y106.WL1BEG2.SR1END3", - "INT_L_X0Y107.LV_L18.LV_L0", - "INT_L_X0Y107.NL1BEG2.NR1END3", - "INT_L_X0Y107.SR1BEG3.NN6END3", - "INT_L_X0Y108.EE2BEG2.NL1END2", - "INT_L_X0Y108.NN6BEG2.LVB_L12", - "INT_L_X0Y109.LV_L18.LV_L0", - "INT_L_X0Y109.NN6BEG2.LVB_L12", - "INT_L_X0Y110.EE2BEG2.NN6END2", - "INT_L_X0Y111.IMUX_L34.WR1END1", - "INT_L_X0Y111.LV_L18.SW6END0", - "INT_L_X0Y111.NL1BEG2.NN6END3", - "INT_L_X0Y111.WW2BEG0.SS6END0", - "INT_L_X0Y112.EE2BEG2.NL1END2", - "INT_L_X0Y112.NW6BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y113.LV_L18.SW6END0", - "INT_L_X0Y114.EE2BEG2.NN6END2", - "INT_L_X0Y115.LV_L18.SW6END0", - "INT_L_X0Y115.NR1BEG2.NN6END2", - "INT_L_X0Y116.EE2BEG2.NR1END2", - "INT_L_X0Y117.LV_L18.SW6END0", - "INT_L_X0Y117.SS6BEG0.SS6END0", - "INT_L_X0Y118.EE2BEG2.EL1END2", - "INT_L_X0Y118.WL1BEG2.NW2END_S0_0", - "INT_L_X0Y119.LV_L18.SW6END0", - "INT_L_X0Y121.LV_L18.SW6END0", - "INT_L_X0Y123.LV_L18.SW6END0", - "INT_L_X0Y123.SS6BEG0.SS6END0", - "INT_L_X0Y125.LV_L18.SW6END0", - "INT_L_X0Y127.LV_L18.SW6END0", - "INT_L_X0Y129.SS6BEG0.SW6END0", - "INT_L_X2Y1.WW2BEG0.SS6END0", - "INT_L_X2Y3.WW2BEG0.SS6END0", - "INT_L_X2Y7.SS6BEG0.SS6END0", - "INT_L_X2Y9.SS6BEG0.SE6END0", - "INT_L_X2Y13.SS6BEG0.SE6END0", - "INT_L_X2Y43.WW2BEG0.SS6END0", - "INT_L_X2Y49.SS6BEG0.SE6END0", - "INT_L_X2Y81.SW6BEG0.SE6END0", - "INT_L_X2Y85.SW6BEG0.SE6END0", - "INT_L_X2Y93.SW6BEG0.SE6END0", - "INT_L_X26Y140.WL1BEG1.NW2END3", - "INT_L_X40Y42.SE6BEG0.SE2END0", - "INT_L_X40Y62.EE4BEG0.SE2END0", - "INT_L_X40Y80.SE6BEG0.SE2END0", - "INT_L_X42Y32.ER1BEG1.SS6END0", - "INT_L_X42Y38.SS6BEG0.SE6END0", - "INT_L_X42Y39.SE2BEG1.ER1END1", - "INT_L_X42Y76.ER1BEG1.SE6END0", - "INT_L_X42Y77.SE2BEG1.ER1END1", - "INT_R_X1Y5.WL1BEG_N3.SS6END0", - "INT_R_X1Y11.SS6BEG0.LV0", - "INT_R_X1Y29.LV18.LV0", - "INT_R_X1Y47.LV18.LV0", - "INT_R_X1Y65.LV18.SW6END0", - "INT_R_X1Y73.SE6BEG0.SE6END0", - "INT_R_X1Y111.WR1BEG1.EE2END0", - "INT_R_X1Y116.NN2BEG0.NE6END0", - "INT_R_X1Y118.NW2BEG0.NN2END0", - "INT_R_X3Y69.SW6BEG0.SE6END0", - "INT_R_X25Y126.WW2BEG1.WW4END2", - "INT_R_X25Y128.WW2BEG1.WW4END2", - "INT_R_X25Y130.WW2BEG1.WW4END2", - "INT_R_X25Y132.WW2BEG1.WW4END2", - "INT_R_X25Y134.WW2BEG1.WW4END2", - "INT_R_X25Y135.LV0.LH6", - "INT_R_X25Y136.WW2BEG1.WW2END1", - "INT_R_X25Y138.WW2BEG1.SS6END1", - "INT_R_X25Y140.WW2BEG1.WL1END1", - "INT_R_X25Y144.SS6BEG1.LV9", - "INT_R_X27Y136.WW2BEG1.NW6END2", - "INT_R_X27Y139.NW2BEG3.WW4END3", - "INT_R_X29Y126.WW4BEG2.NN6END2", - "INT_R_X29Y128.WW4BEG2.NW6END2", - "INT_R_X29Y129.LVB12.NW6END3", - "INT_R_X29Y129.SS6BEG1.NW6END2", - "INT_R_X29Y130.WW4BEG2.NW6END2", - "INT_R_X29Y132.NW6BEG2.NW6END2", - "INT_R_X29Y132.WW4BEG2.LVB12", - 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"RIOB33_X43Y45.IOB_Y1.IN_TERM.NONE", - "RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY", - "RIOB33_X43Y45.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y45.IOB_Y1.PULLTYPE.NONE", - "RIOB33_X43Y47.IOB_Y0.IN_TERM.NONE", - "RIOB33_X43Y47.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y47.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY", - "RIOB33_X43Y47.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y47.IOB_Y0.PULLTYPE.NONE", - "RIOB33_X43Y47.IOB_Y1.IN_TERM.NONE", - "RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY", - "RIOB33_X43Y47.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X43Y47.IOB_Y1.PULLTYPE.NONE", - "RIOB33_X43Y61.IOB_Y0.IN_TERM.NONE", - "RIOB33_X43Y61.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y61.IOB_Y0.PULLTYPE.PULLDOWN", - "RIOB33_X43Y61.IOB_Y1.IN_TERM.NONE", - "RIOB33_X43Y61.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_X43Y61.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_X43Y61.IOB_Y1.PULLTYPE.NONE", - "RIOB33_X43Y75.IOB_Y0.IN_TERM.NONE", - "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_X43Y75.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE", - "RIOB33_X43Y75.IOB_Y1.IN_TERM.NONE", - "RIOB33_X43Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_X43Y75.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_X43Y75.IOB_Y1.PULLTYPE.NONE", - "RIOB33_X43Y87.IOB_Y0.IN_TERM.NONE", - "RIOB33_X43Y87.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X43Y87.IOB_Y0.PULLTYPE.PULLDOWN", - "RIOB33_X43Y87.IOB_Y1.IN_TERM.NONE", - "RIOB33_X43Y87.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_X43Y87.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_X43Y87.IOB_Y1.PULLTYPE.NONE", - "RIOI3_TBYTESRC_X43Y31.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_TBYTESRC_X43Y31.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_TBYTESRC_X43Y31.OLOGIC_Y0.OMUX.D1", - "RIOI3_TBYTESRC_X43Y31.OLOGIC_Y0.OQUSED", - "RIOI3_TBYTESRC_X43Y31.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_TBYTESRC_X43Y43.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_TBYTESRC_X43Y43.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_TBYTESRC_X43Y43.ILOGIC_Y0.ZINV_D", - "RIOI3_TBYTESRC_X43Y43.ILOGIC_Y1.ZINV_D", - "RIOI3_TBYTETERM_X43Y37.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_TBYTETERM_X43Y37.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y0.OMUX.D1", - "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y0.OQUSED", - "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y1.OMUX.D1", - "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y1.OQUSED", - "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_TBYTETERM_X43Y87.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_TBYTETERM_X43Y87.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_TBYTETERM_X43Y87.OLOGIC_Y1.OMUX.D1", - "RIOI3_TBYTETERM_X43Y87.OLOGIC_Y1.OQUSED", - "RIOI3_TBYTETERM_X43Y87.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_X43Y25.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X43Y25.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X43Y25.ILOGIC_Y0.ZINV_D", - "RIOI3_X43Y39.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X43Y39.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X43Y39.ILOGIC_Y0.ZINV_D", - "RIOI3_X43Y39.ILOGIC_Y1.ZINV_D", - "RIOI3_X43Y45.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X43Y45.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X43Y45.ILOGIC_Y0.ZINV_D", - "RIOI3_X43Y45.ILOGIC_Y1.ZINV_D", - "RIOI3_X43Y47.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X43Y47.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X43Y47.ILOGIC_Y0.ZINV_D", - "RIOI3_X43Y47.ILOGIC_Y1.ZINV_D", - "RIOI3_X43Y61.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X43Y61.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X43Y61.OLOGIC_Y1.OMUX.D1", - "RIOI3_X43Y61.OLOGIC_Y1.OQUSED", - "RIOI3_X43Y61.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_X43Y75.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X43Y75.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X43Y75.OLOGIC_Y0.OMUX.D1", - "RIOI3_X43Y75.OLOGIC_Y0.OQUSED", - "RIOI3_X43Y75.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_X43Y75.OLOGIC_Y1.OMUX.D1", - "RIOI3_X43Y75.OLOGIC_Y1.OQUSED", - "RIOI3_X43Y75.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF" - ] -} diff --git a/artix7/harness/basys3/swbut_50/design.txt b/artix7/harness/basys3/swbut_50/design.txt deleted file mode 100644 index 8cf3900..0000000 --- a/artix7/harness/basys3/swbut_50/design.txt +++ /dev/null @@ -1,36 +0,0 @@ -name node pin wire -clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 W5 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0 -din[0] INT_L_X0Y102/EE2BEG2 V17 VBRK_X9Y107/VBRK_EE2A2 -din[1] INT_L_X0Y104/EE2BEG2 V16 VBRK_X9Y109/VBRK_EE2A2 -din[2] INT_L_X0Y106/EE2BEG2 W16 VBRK_X9Y111/VBRK_EE2A2 -din[3] INT_L_X0Y108/EE2BEG2 W17 VBRK_X9Y113/VBRK_EE2A2 -din[4] INT_L_X0Y110/EE2BEG2 W15 VBRK_X9Y115/VBRK_EE2A2 -din[5] INT_L_X0Y112/EE2BEG2 V15 VBRK_X9Y117/VBRK_EE2A2 -din[6] INT_L_X0Y114/EE2BEG2 W14 VBRK_X9Y119/VBRK_EE2A2 -din[7] INT_L_X0Y116/EE2BEG2 W13 VBRK_X9Y121/VBRK_EE2A2 -din[8] INT_R_X25Y126/WW2BEG1 V2 VBRK_X61Y132/VBRK_WW2END1 -din[9] INT_R_X25Y128/WW2BEG1 T3 VBRK_X61Y134/VBRK_WW2END1 -din[10] INT_R_X25Y130/WW2BEG1 T2 VBRK_X61Y136/VBRK_WW2END1 -din[11] INT_R_X25Y132/WW2BEG1 R3 VBRK_X61Y138/VBRK_WW2END1 -din[12] INT_R_X25Y134/WW2BEG1 W2 VBRK_X61Y140/VBRK_WW2END1 -din[13] INT_R_X25Y136/WW2BEG1 U1 VBRK_X61Y142/VBRK_WW2END1 -din[14] INT_R_X25Y138/WW2BEG1 T1 VBRK_X61Y144/VBRK_WW2END1 -din[15] INT_R_X25Y140/WW2BEG1 R2 VBRK_X61Y146/VBRK_WW2END1 -din[16] INT_L_X0Y118/EE2BEG2 B18 VBRK_X9Y123/VBRK_EE2A2 -dout[0] INT_L_X2Y115/SW6BEG0 U16 VBRK_X9Y120/VBRK_SW4A0 -dout[1] INT_L_X2Y117/SW6BEG0 E19 VBRK_X9Y122/VBRK_SW4A0 -dout[2] INT_L_X2Y119/SW6BEG0 U19 VBRK_X9Y124/VBRK_SW4A0 -dout[3] INT_L_X2Y121/SW6BEG0 V19 VBRK_X9Y126/VBRK_SW4A0 -dout[4] INT_L_X2Y123/SW6BEG0 W18 VBRK_X9Y128/VBRK_SW4A0 -dout[5] INT_L_X2Y125/SW6BEG0 U15 VBRK_X9Y131/VBRK_SW4A0 -dout[6] INT_L_X2Y127/SW6BEG0 U14 VBRK_X9Y133/VBRK_SW4A0 -dout[7] INT_L_X2Y129/SW6BEG0 V14 VBRK_X9Y135/VBRK_SW4A0 -dout[8] INT_L_X2Y131/SW6BEG0 V13 VBRK_X9Y137/VBRK_SW4A0 -dout[9] INT_R_X23Y115/LH12 V3 VBRK_X61Y120/VBRK_LH12 -dout[10] INT_R_X23Y117/LH12 W3 VBRK_X61Y122/VBRK_LH12 -dout[11] INT_R_X23Y119/LH12 U3 VBRK_X61Y124/VBRK_LH12 -dout[12] INT_R_X23Y121/LH12 P3 VBRK_X61Y126/VBRK_LH12 -dout[13] INT_R_X23Y123/LH12 N3 VBRK_X61Y128/VBRK_LH12 -dout[14] INT_R_X23Y125/LH12 P1 VBRK_X61Y131/VBRK_LH12 -dout[15] INT_R_X23Y127/LH12 L1 VBRK_X61Y133/VBRK_LH12 -dout[16] INT_L_X2Y133/SW6BEG0 A18 VBRK_X9Y139/VBRK_SW4A0 diff --git a/artix7/ppips_gtp_channel_0.db b/artix7/ppips_gtp_channel_0.db new file mode 100644 index 0000000..b334f0b --- /dev/null +++ b/artix7/ppips_gtp_channel_0.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_0.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_0.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_0_mid_left.db b/artix7/ppips_gtp_channel_0_mid_left.db new file mode 100644 index 0000000..f17dbd8 --- /dev/null +++ b/artix7/ppips_gtp_channel_0_mid_left.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_0_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_0_mid_right.db b/artix7/ppips_gtp_channel_0_mid_right.db new file mode 100644 index 0000000..ab4b943 --- /dev/null +++ b/artix7/ppips_gtp_channel_0_mid_right.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_0_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_1.db b/artix7/ppips_gtp_channel_1.db new file mode 100644 index 0000000..07a0ab1 --- /dev/null +++ b/artix7/ppips_gtp_channel_1.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_1.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_1.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_1_mid_left.db b/artix7/ppips_gtp_channel_1_mid_left.db new file mode 100644 index 0000000..1ca3707 --- /dev/null +++ b/artix7/ppips_gtp_channel_1_mid_left.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_1_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_1_mid_right.db b/artix7/ppips_gtp_channel_1_mid_right.db new file mode 100644 index 0000000..d809506 --- /dev/null +++ b/artix7/ppips_gtp_channel_1_mid_right.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_1_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_2.db b/artix7/ppips_gtp_channel_2.db new file mode 100644 index 0000000..0c384ed --- /dev/null +++ b/artix7/ppips_gtp_channel_2.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_2.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_2.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_2_mid_left.db b/artix7/ppips_gtp_channel_2_mid_left.db new file mode 100644 index 0000000..1403e8c --- /dev/null +++ b/artix7/ppips_gtp_channel_2_mid_left.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_2_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_2_mid_right.db b/artix7/ppips_gtp_channel_2_mid_right.db new file mode 100644 index 0000000..abdc6e7 --- /dev/null +++ b/artix7/ppips_gtp_channel_2_mid_right.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_2_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_3.db b/artix7/ppips_gtp_channel_3.db new file mode 100644 index 0000000..d544403 --- /dev/null +++ b/artix7/ppips_gtp_channel_3.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_3.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_3.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_3_mid_left.db b/artix7/ppips_gtp_channel_3_mid_left.db new file mode 100644 index 0000000..f1da2cc --- /dev/null +++ b/artix7/ppips_gtp_channel_3_mid_left.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_3_MID_LEFT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_channel_3_mid_right.db b/artix7/ppips_gtp_channel_3_mid_right.db new file mode 100644 index 0000000..38fc343 --- /dev/null +++ b/artix7/ppips_gtp_channel_3_mid_right.db @@ -0,0 +1,346 @@ +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_CFGRESET.GTPE2_CTRL1_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DMONFIFORESET.GTPE2_IMUX44_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DMONITORCLK.GTPE2_CLK1_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPCLK.GTPE2_CLK0_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPEN.GTPE2_IMUX44_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPWE.GTPE2_IMUX28_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_EYESCANMODE.GTPE2_IMUX2_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_EYESCANRESET.GTPE2_IMUX45_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_EYESCANTRIGGER.GTPE2_IMUX31_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRESETSEL.GTPE2_CTRL0_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRXRESET.GTPE2_CTRL0_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTTXRESET.GTPE2_CTRL0_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RESETOVRD.GTPE2_IMUX41_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RX8B10BEN.GTPE2_IMUX45_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXBUFRESET.GTPE2_CTRL1_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDRFREQRESET.GTPE2_CTRL0_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDRHOLD.GTPE2_IMUX30_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDROVRDEN.GTPE2_IMUX14_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESET.GTPE2_CTRL1_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCDRRESETRSV.GTPE2_CTRL1_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDEN.GTPE2_IMUX17_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDMASTER.GTPE2_IMUX30_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDSLAVE.GTPE2_IMUX30_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCOMMADETEN.GTPE2_IMUX44_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDDIEN.GTPE2_IMUX8_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDFEXYDEN.GTPE2_IMUX45_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDLYBYPASS.GTPE2_IMUX32_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDLYEN.GTPE2_IMUX28_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDLYOVRDEN.GTPE2_IMUX41_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXDLYSRESET.GTPE2_CTRL0_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXGEARBOXSLIP.GTPE2_IMUX6_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFHOLD.GTPE2_IMUX43_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMHFOVRDEN.GTPE2_IMUX27_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFHOLD.GTPE2_IMUX5_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMLFOVRDEN.GTPE2_IMUX3_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMOSINTNTRLEN.GTPE2_IMUX7_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXLPMRESET.GTPE2_CTRL0_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXMCOMMAALIGNEN.GTPE2_IMUX41_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOOBRESET.GTPE2_CTRL1_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSCALRESET.GTPE2_IMUX46_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSHOLD.GTPE2_IMUX29_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTEN.GTPE2_IMUX15_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTHOLD.GTPE2_IMUX1_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTNTRLEN.GTPE2_IMUX36_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTOVRDEN.GTPE2_IMUX0_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTPD.GTPE2_IMUX3_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTSTROBE.GTPE2_IMUX32_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTTESTOVRDEN.GTPE2_IMUX5_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSOVRDEN.GTPE2_IMUX13_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPCOMMAALIGNEN.GTPE2_IMUX40_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPCSRESET.GTPE2_IMUX46_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGN.GTPE2_IMUX14_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHALIGNEN.GTPE2_IMUX41_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYPD.GTPE2_IMUX8_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHDLYRESET.GTPE2_CTRL1_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPHOVRDEN.GTPE2_IMUX14_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPMARESET.GTPE2_CTRL1_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPOLARITY.GTPE2_IMUX27_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPRBSCNTRESET.GTPE2_IMUX13_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXRATEMODE.GTPE2_IMUX2_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSLIDE.GTPE2_IMUX42_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYNCALLIN.GTPE2_IMUX36_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYNCIN.GTPE2_IMUX7_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYNCMODE.GTPE2_IMUX40_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXUSERRDY.GTPE2_IMUX6_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK.GTPE2_CLK0_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_SETERRSTATUS.GTPE2_IMUX34_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_SIGVALIDCLK.GTPE2_CLK1_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BEN.GTPE2_IMUX0_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCOMINIT.GTPE2_IMUX2_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCOMSAS.GTPE2_IMUX27_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCOMWAKE.GTPE2_IMUX3_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDEEMPH.GTPE2_IMUX35_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDETECTRX.GTPE2_IMUX39_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFPD.GTPE2_IMUX37_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYBYPASS.GTPE2_IMUX44_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYEN.GTPE2_IMUX14_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYHOLD.GTPE2_IMUX11_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYOVRDEN.GTPE2_IMUX12_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYSRESET.GTPE2_IMUX45_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDLYUPDOWN.GTPE2_IMUX43_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXELECIDLE.GTPE2_IMUX39_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXINHIBIT.GTPE2_IMUX32_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPCSRESET.GTPE2_IMUX46_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPDELECIDLEMODE.GTPE2_IMUX14_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGN.GTPE2_IMUX25_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHALIGNEN.GTPE2_IMUX33_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYPD.GTPE2_IMUX37_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYRESET.GTPE2_IMUX36_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHDLYTSTCLK.GTPE2_CLK1_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHINIT.GTPE2_IMUX27_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPHOVRDEN.GTPE2_IMUX44_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMEN.GTPE2_IMUX42_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMOVRDEN.GTPE2_IMUX10_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMPD.GTPE2_IMUX46_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSEL.GTPE2_IMUX8_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPISOPD.GTPE2_IMUX45_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPMARESET.GTPE2_CTRL1_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOLARITY.GTPE2_IMUX30_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSORINV.GTPE2_IMUX30_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRBSFORCEERR.GTPE2_IMUX14_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSORINV.GTPE2_IMUX32_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXRATEMODE.GTPE2_IMUX11_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSTARTSEQ.GTPE2_IMUX3_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSWING.GTPE2_IMUX38_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYNCALLIN.GTPE2_IMUX44_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYNCIN.GTPE2_IMUX7_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYNCMODE.GTPE2_IMUX13_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXUSERRDY.GTPE2_IMUX31_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK.GTPE2_CLK0_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD0.GTPE2_CLK1_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_CLKRSVD1.GTPE2_CLK1_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR0.GTPE2_IMUX39_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR1.GTPE2_IMUX38_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR2.GTPE2_IMUX35_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR3.GTPE2_IMUX34_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR4.GTPE2_IMUX39_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR5.GTPE2_IMUX38_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR6.GTPE2_IMUX35_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR7.GTPE2_IMUX34_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPADDR8.GTPE2_IMUX2_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI0.GTPE2_IMUX45_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI1.GTPE2_IMUX10_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI2.GTPE2_IMUX13_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI3.GTPE2_IMUX32_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI4.GTPE2_IMUX7_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI5.GTPE2_IMUX38_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI6.GTPE2_IMUX6_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI7.GTPE2_IMUX3_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI8.GTPE2_IMUX34_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI9.GTPE2_IMUX45_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI10.GTPE2_IMUX33_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI11.GTPE2_IMUX32_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI12.GTPE2_IMUX37_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI13.GTPE2_IMUX36_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI14.GTPE2_IMUX17_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_DRPDI15.GTPE2_IMUX16_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD0.GTPE2_IMUX42_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD1.GTPE2_IMUX42_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD2.GTPE2_IMUX42_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD3.GTPE2_IMUX42_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD4.GTPE2_IMUX42_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD5.GTPE2_IMUX42_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD6.GTPE2_IMUX42_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD7.GTPE2_IMUX42_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD8.GTPE2_IMUX26_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD9.GTPE2_IMUX26_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD10.GTPE2_IMUX26_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD11.GTPE2_IMUX26_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD12.GTPE2_IMUX26_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD13.GTPE2_IMUX26_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD14.GTPE2_IMUX26_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_GTRSVD15.GTPE2_IMUX26_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK0.GTPE2_IMUX43_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK1.GTPE2_IMUX46_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_LOOPBACK2.GTPE2_IMUX47_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN0.GTPE2_IMUX25_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN1.GTPE2_IMUX25_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN2.GTPE2_IMUX25_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN3.GTPE2_IMUX25_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN4.GTPE2_IMUX25_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN5.GTPE2_IMUX25_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN6.GTPE2_IMUX25_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN7.GTPE2_IMUX25_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN8.GTPE2_IMUX9_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN9.GTPE2_IMUX9_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN10.GTPE2_IMUX9_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN11.GTPE2_IMUX9_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN12.GTPE2_IMUX9_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN13.GTPE2_IMUX9_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN14.GTPE2_IMUX9_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PCSRSVDIN15.GTPE2_IMUX9_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN0.GTPE2_IMUX37_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN1.GTPE2_IMUX37_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN2.GTPE2_IMUX10_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN3.GTPE2_IMUX5_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_PMARSVDIN4.GTPE2_IMUX3_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST0.GTPE2_IMUX0_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST1.GTPE2_IMUX1_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST2.GTPE2_IMUX4_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST3.GTPE2_IMUX5_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST4.GTPE2_IMUX34_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST5.GTPE2_IMUX6_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST6.GTPE2_IMUX41_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST7.GTPE2_IMUX44_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST8.GTPE2_IMUX29_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST9.GTPE2_IMUX11_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST10.GTPE2_IMUX0_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST11.GTPE2_IMUX17_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST12.GTPE2_IMUX36_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXADAPTSELTEST13.GTPE2_IMUX21_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI0.GTPE2_IMUX18_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI1.GTPE2_IMUX19_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI2.GTPE2_IMUX22_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDI3.GTPE2_IMUX23_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL0.GTPE2_IMUX1_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL1.GTPE2_IMUX4_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXCHBONDLEVEL2.GTPE2_IMUX5_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE0.GTPE2_IMUX0_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXELECIDLEMODE1.GTPE2_IMUX1_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG0.GTPE2_IMUX38_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG1.GTPE2_IMUX6_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG2.GTPE2_IMUX35_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTCFG3.GTPE2_IMUX46_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID00.GTPE2_IMUX15_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID01.GTPE2_IMUX28_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID02.GTPE2_IMUX10_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOSINTID03.GTPE2_IMUX11_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL0.GTPE2_IMUX4_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL1.GTPE2_IMUX5_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXOUTCLKSEL2.GTPE2_IMUX2_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPD0.GTPE2_IMUX30_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPD1.GTPE2_IMUX28_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL0.GTPE2_IMUX22_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL1.GTPE2_IMUX38_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXPRBSSEL2.GTPE2_IMUX23_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXRATE0.GTPE2_IMUX15_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXRATE1.GTPE2_IMUX14_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXRATE2.GTPE2_IMUX11_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL0.GTPE2_IMUX45_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXSYSCLKSEL1.GTPE2_IMUX42_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_RXUSRCLK2.GTPE2_CLK0_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN0.GTPE2_IMUX45_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN1.GTPE2_IMUX40_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN2.GTPE2_IMUX40_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN3.GTPE2_IMUX40_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN4.GTPE2_IMUX40_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN5.GTPE2_IMUX40_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN6.GTPE2_IMUX40_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN7.GTPE2_IMUX40_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN8.GTPE2_IMUX40_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN9.GTPE2_IMUX40_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN10.GTPE2_IMUX13_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN11.GTPE2_IMUX24_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN12.GTPE2_IMUX24_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN13.GTPE2_IMUX24_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN14.GTPE2_IMUX24_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN15.GTPE2_IMUX24_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN16.GTPE2_IMUX24_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN17.GTPE2_IMUX24_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN18.GTPE2_IMUX24_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TSTIN19.GTPE2_IMUX24_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS0.GTPE2_IMUX15_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS1.GTPE2_IMUX15_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS2.GTPE2_IMUX15_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TX8B10BBYPASS3.GTPE2_IMUX31_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL0.GTPE2_IMUX12_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL1.GTPE2_IMUX13_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXBUFDIFFCTRL2.GTPE2_IMUX10_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE0.GTPE2_IMUX29_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE1.GTPE2_IMUX29_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE2.GTPE2_IMUX29_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPMODE3.GTPE2_IMUX12_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL0.GTPE2_IMUX8_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL1.GTPE2_IMUX8_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL2.GTPE2_IMUX8_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARDISPVAL3.GTPE2_IMUX46_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK0.GTPE2_IMUX31_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK1.GTPE2_IMUX31_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK2.GTPE2_IMUX31_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXCHARISK3.GTPE2_IMUX47_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA0.GTPE2_IMUX18_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA1.GTPE2_IMUX19_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA2.GTPE2_IMUX22_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA3.GTPE2_IMUX23_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA4.GTPE2_IMUX16_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA5.GTPE2_IMUX17_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA6.GTPE2_IMUX20_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA7.GTPE2_IMUX21_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA8.GTPE2_IMUX18_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA9.GTPE2_IMUX19_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA10.GTPE2_IMUX22_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA11.GTPE2_IMUX23_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA12.GTPE2_IMUX16_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA13.GTPE2_IMUX17_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA14.GTPE2_IMUX20_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA15.GTPE2_IMUX21_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA16.GTPE2_IMUX18_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA17.GTPE2_IMUX19_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA18.GTPE2_IMUX22_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA19.GTPE2_IMUX23_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA20.GTPE2_IMUX16_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA21.GTPE2_IMUX17_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA22.GTPE2_IMUX20_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA23.GTPE2_IMUX21_2 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA24.GTPE2_IMUX8_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA25.GTPE2_IMUX41_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA26.GTPE2_IMUX44_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA27.GTPE2_IMUX29_10 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA28.GTPE2_IMUX16_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA29.GTPE2_IMUX17_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA30.GTPE2_IMUX20_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDATA31.GTPE2_IMUX21_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL0.GTPE2_IMUX7_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL1.GTPE2_IMUX6_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL2.GTPE2_IMUX3_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXDIFFCTRL3.GTPE2_IMUX2_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXHEADER0.GTPE2_IMUX39_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXHEADER1.GTPE2_IMUX31_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXHEADER2.GTPE2_IMUX39_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR0.GTPE2_IMUX5_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR1.GTPE2_IMUX4_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR2.GTPE2_IMUX1_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR3.GTPE2_IMUX0_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR4.GTPE2_IMUX5_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR5.GTPE2_IMUX4_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMAINCURSOR6.GTPE2_IMUX1_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN0.GTPE2_IMUX39_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN1.GTPE2_IMUX38_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXMARGIN2.GTPE2_IMUX35_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL0.GTPE2_IMUX5_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL1.GTPE2_IMUX4_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXOUTCLKSEL2.GTPE2_IMUX1_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPD0.GTPE2_IMUX38_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPD1.GTPE2_IMUX35_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE0.GTPE2_IMUX8_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE1.GTPE2_IMUX41_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE2.GTPE2_IMUX13_9 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE3.GTPE2_IMUX35_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPIPPMSTEPSIZE4.GTPE2_IMUX22_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR0.GTPE2_IMUX7_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR1.GTPE2_IMUX6_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR2.GTPE2_IMUX3_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR3.GTPE2_IMUX2_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPOSTCURSOR4.GTPE2_IMUX7_3 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL0.GTPE2_IMUX3_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL1.GTPE2_IMUX6_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRBSSEL2.GTPE2_IMUX7_8 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR0.GTPE2_IMUX7_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR1.GTPE2_IMUX6_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR2.GTPE2_IMUX3_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR3.GTPE2_IMUX2_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXPRECURSOR4.GTPE2_IMUX7_7 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXRATE0.GTPE2_IMUX47_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXRATE1.GTPE2_IMUX46_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXRATE2.GTPE2_IMUX43_6 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE0.GTPE2_IMUX35_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE1.GTPE2_IMUX27_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE2.GTPE2_IMUX35_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE3.GTPE2_IMUX27_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE4.GTPE2_IMUX8_1 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE5.GTPE2_IMUX16_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSEQUENCE6.GTPE2_IMUX8_0 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL0.GTPE2_IMUX28_5 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXSYSCLKSEL1.GTPE2_IMUX28_4 always +GTP_CHANNEL_3_MID_RIGHT.GTPE2_CHANNEL_TXUSRCLK2.GTPE2_CLK0_5 always diff --git a/artix7/ppips_gtp_common.db b/artix7/ppips_gtp_common.db new file mode 100644 index 0000000..6d7b59e --- /dev/null +++ b/artix7/ppips_gtp_common.db @@ -0,0 +1,84 @@ +GTP_COMMON.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always +GTP_COMMON.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always +GTP_COMMON.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always +GTP_COMMON.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always +GTP_COMMON.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always +GTP_COMMON.GTPE2_COMMON_BGRCALOVRDENB.GTPE2_IMUX42_5 always +GTP_COMMON.GTPE2_COMMON_DRPCLK.GTPE2_CLK1_5 always +GTP_COMMON.GTPE2_COMMON_DRPEN.GTPE2_IMUX22_3 always +GTP_COMMON.GTPE2_COMMON_DRPWE.GTPE2_IMUX35_1 always +GTP_COMMON.GTPE2_COMMON_PLL0LOCKDETCLK.GTPE2_CLK0_1 always +GTP_COMMON.GTPE2_COMMON_PLL0LOCKEN.GTPE2_IMUX42_4 always +GTP_COMMON.GTPE2_COMMON_PLL0PD.GTPE2_IMUX42_3 always +GTP_COMMON.GTPE2_COMMON_PLL0RESET.GTPE2_CTRL0_3 always +GTP_COMMON.GTPE2_COMMON_PLL1LOCKDETCLK.GTPE2_CLK1_1 always +GTP_COMMON.GTPE2_COMMON_PLL1LOCKEN.GTPE2_IMUX42_2 always +GTP_COMMON.GTPE2_COMMON_PLL1PD.GTPE2_IMUX42_1 always +GTP_COMMON.GTPE2_COMMON_PLL1RESET.GTPE2_CTRL1_3 always +GTP_COMMON.GTPE2_COMMON_RCALENB.GTPE2_IMUX3_5 always +GTP_COMMON.GTPE2_COMMON_BGRCALOVRD0.GTPE2_IMUX45_5 always +GTP_COMMON.GTPE2_COMMON_BGRCALOVRD1.GTPE2_IMUX45_4 always +GTP_COMMON.GTPE2_COMMON_BGRCALOVRD2.GTPE2_IMUX45_3 always +GTP_COMMON.GTPE2_COMMON_BGRCALOVRD3.GTPE2_IMUX45_2 always +GTP_COMMON.GTPE2_COMMON_BGRCALOVRD4.GTPE2_IMUX45_1 always +GTP_COMMON.GTPE2_COMMON_DRPADDR0.GTPE2_IMUX35_5 always +GTP_COMMON.GTPE2_COMMON_DRPADDR1.GTPE2_IMUX27_5 always +GTP_COMMON.GTPE2_COMMON_DRPADDR2.GTPE2_IMUX35_4 always +GTP_COMMON.GTPE2_COMMON_DRPADDR3.GTPE2_IMUX27_4 always +GTP_COMMON.GTPE2_COMMON_DRPADDR4.GTPE2_IMUX35_3 always +GTP_COMMON.GTPE2_COMMON_DRPADDR5.GTPE2_IMUX27_3 always +GTP_COMMON.GTPE2_COMMON_DRPADDR6.GTPE2_IMUX35_2 always +GTP_COMMON.GTPE2_COMMON_DRPADDR7.GTPE2_IMUX27_2 always +GTP_COMMON.GTPE2_COMMON_DRPDI0.GTPE2_IMUX38_5 always +GTP_COMMON.GTPE2_COMMON_DRPDI1.GTPE2_IMUX30_5 always +GTP_COMMON.GTPE2_COMMON_DRPDI2.GTPE2_IMUX38_4 always +GTP_COMMON.GTPE2_COMMON_DRPDI3.GTPE2_IMUX30_4 always +GTP_COMMON.GTPE2_COMMON_DRPDI4.GTPE2_IMUX38_3 always +GTP_COMMON.GTPE2_COMMON_DRPDI5.GTPE2_IMUX30_3 always +GTP_COMMON.GTPE2_COMMON_DRPDI6.GTPE2_IMUX38_2 always +GTP_COMMON.GTPE2_COMMON_DRPDI7.GTPE2_IMUX30_2 always +GTP_COMMON.GTPE2_COMMON_DRPDI8.GTPE2_IMUX38_1 always +GTP_COMMON.GTPE2_COMMON_DRPDI9.GTPE2_IMUX30_1 always +GTP_COMMON.GTPE2_COMMON_DRPDI10.GTPE2_IMUX22_2 always +GTP_COMMON.GTPE2_COMMON_DRPDI11.GTPE2_IMUX14_2 always +GTP_COMMON.GTPE2_COMMON_DRPDI12.GTPE2_IMUX22_5 always +GTP_COMMON.GTPE2_COMMON_DRPDI13.GTPE2_IMUX14_5 always +GTP_COMMON.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always +GTP_COMMON.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always +GTP_COMMON.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always +GTP_COMMON.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always +GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always +GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always +GTP_COMMON.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always +GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always +GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always +GTP_COMMON.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD13.GTPE2_IMUX24_4 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD14.GTPE2_IMUX32_3 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD15.GTPE2_IMUX24_3 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD16.GTPE2_IMUX32_2 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD17.GTPE2_IMUX24_2 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD18.GTPE2_IMUX32_1 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD19.GTPE2_IMUX24_1 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD20.GTPE2_IMUX5_5 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD21.GTPE2_IMUX5_4 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD22.GTPE2_IMUX5_3 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD23.GTPE2_IMUX5_2 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD24.GTPE2_IMUX5_1 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD110.GTPE2_IMUX40_5 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD111.GTPE2_IMUX40_4 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD112.GTPE2_IMUX0_5 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD113.GTPE2_IMUX0_4 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD114.GTPE2_IMUX0_3 always +GTP_COMMON.GTPE2_COMMON_PLLRSVD115.GTPE2_IMUX0_2 always +GTP_COMMON.GTPE2_COMMON_PMARSVD0.GTPE2_IMUX20_5 always +GTP_COMMON.GTPE2_COMMON_PMARSVD1.GTPE2_IMUX20_4 always +GTP_COMMON.GTPE2_COMMON_PMARSVD2.GTPE2_IMUX20_3 always +GTP_COMMON.GTPE2_COMMON_PMARSVD3.GTPE2_IMUX20_2 always +GTP_COMMON.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always +GTP_COMMON.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always +GTP_COMMON.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always +GTP_COMMON.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always diff --git a/artix7/ppips_gtp_common_mid_left.db b/artix7/ppips_gtp_common_mid_left.db new file mode 100644 index 0000000..36acb7c --- /dev/null +++ b/artix7/ppips_gtp_common_mid_left.db @@ -0,0 +1,84 @@ +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always +GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRDENB.GTPE2_IMUX42_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPCLK.GTPE2_CLK1_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPEN.GTPE2_IMUX22_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPWE.GTPE2_IMUX35_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0LOCKDETCLK.GTPE2_CLK0_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0LOCKEN.GTPE2_IMUX42_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0PD.GTPE2_IMUX42_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0RESET.GTPE2_CTRL0_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1LOCKDETCLK.GTPE2_CLK1_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1LOCKEN.GTPE2_IMUX42_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1PD.GTPE2_IMUX42_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1RESET.GTPE2_CTRL1_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_RCALENB.GTPE2_IMUX3_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD0.GTPE2_IMUX45_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD1.GTPE2_IMUX45_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD2.GTPE2_IMUX45_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD3.GTPE2_IMUX45_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_BGRCALOVRD4.GTPE2_IMUX45_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR0.GTPE2_IMUX35_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR1.GTPE2_IMUX27_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR2.GTPE2_IMUX35_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR3.GTPE2_IMUX27_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR4.GTPE2_IMUX35_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR5.GTPE2_IMUX27_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR6.GTPE2_IMUX35_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPADDR7.GTPE2_IMUX27_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI0.GTPE2_IMUX38_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI1.GTPE2_IMUX30_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI2.GTPE2_IMUX38_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI3.GTPE2_IMUX30_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI4.GTPE2_IMUX38_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI5.GTPE2_IMUX30_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI6.GTPE2_IMUX38_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI7.GTPE2_IMUX30_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI8.GTPE2_IMUX38_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI9.GTPE2_IMUX30_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI10.GTPE2_IMUX22_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI11.GTPE2_IMUX14_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI12.GTPE2_IMUX22_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI13.GTPE2_IMUX14_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD13.GTPE2_IMUX24_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD14.GTPE2_IMUX32_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD15.GTPE2_IMUX24_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD16.GTPE2_IMUX32_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD17.GTPE2_IMUX24_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD18.GTPE2_IMUX32_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD19.GTPE2_IMUX24_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD20.GTPE2_IMUX5_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD21.GTPE2_IMUX5_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD22.GTPE2_IMUX5_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD23.GTPE2_IMUX5_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD24.GTPE2_IMUX5_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD110.GTPE2_IMUX40_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD111.GTPE2_IMUX40_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD112.GTPE2_IMUX0_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD113.GTPE2_IMUX0_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD114.GTPE2_IMUX0_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLLRSVD115.GTPE2_IMUX0_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD0.GTPE2_IMUX20_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD1.GTPE2_IMUX20_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD2.GTPE2_IMUX20_3 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD3.GTPE2_IMUX20_2 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always +GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always diff --git a/artix7/ppips_gtp_common_mid_right.db b/artix7/ppips_gtp_common_mid_right.db new file mode 100644 index 0000000..3fb4779 --- /dev/null +++ b/artix7/ppips_gtp_common_mid_right.db @@ -0,0 +1,84 @@ +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_0_CEB.GTPE2_IMUX3_1 always +GTP_COMMON_MID_RIGHT.IBUFDS_GTPE2_1_CEB.GTPE2_IMUX0_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGBYPASSB.GTPE2_IMUX27_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGMONITORENB.GTPE2_IMUX22_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGPDB.GTPE2_IMUX3_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRDENB.GTPE2_IMUX42_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPCLK.GTPE2_CLK1_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPEN.GTPE2_IMUX22_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPWE.GTPE2_IMUX35_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0LOCKDETCLK.GTPE2_CLK0_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0LOCKEN.GTPE2_IMUX42_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0PD.GTPE2_IMUX42_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0RESET.GTPE2_CTRL0_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1LOCKDETCLK.GTPE2_CLK1_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1LOCKEN.GTPE2_IMUX42_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1PD.GTPE2_IMUX42_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1RESET.GTPE2_CTRL1_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_RCALENB.GTPE2_IMUX3_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD0.GTPE2_IMUX45_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD1.GTPE2_IMUX45_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD2.GTPE2_IMUX45_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD3.GTPE2_IMUX45_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_BGRCALOVRD4.GTPE2_IMUX45_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR0.GTPE2_IMUX35_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR1.GTPE2_IMUX27_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR2.GTPE2_IMUX35_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR3.GTPE2_IMUX27_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR4.GTPE2_IMUX35_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR5.GTPE2_IMUX27_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR6.GTPE2_IMUX35_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPADDR7.GTPE2_IMUX27_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI0.GTPE2_IMUX38_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI1.GTPE2_IMUX30_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI2.GTPE2_IMUX38_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI3.GTPE2_IMUX30_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI4.GTPE2_IMUX38_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI5.GTPE2_IMUX30_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI6.GTPE2_IMUX38_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI7.GTPE2_IMUX30_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI8.GTPE2_IMUX38_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI9.GTPE2_IMUX30_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI10.GTPE2_IMUX22_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI11.GTPE2_IMUX14_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI12.GTPE2_IMUX22_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI13.GTPE2_IMUX14_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI14.GTPE2_IMUX22_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_DRPDI15.GTPE2_IMUX14_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTGREFCLK0.GTPE2_CLK0_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_GTGREFCLK1.GTPE2_CLK1_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL0.GTPE2_IMUX2_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL1.GTPE2_IMUX2_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL0REFCLKSEL2.GTPE2_IMUX2_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL0.GTPE2_IMUX2_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL1.GTPE2_IMUX2_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLL1REFCLKSEL2.GTPE2_IMUX41_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD10.GTPE2_IMUX32_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD11.GTPE2_IMUX24_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD12.GTPE2_IMUX32_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD13.GTPE2_IMUX24_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD14.GTPE2_IMUX32_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD15.GTPE2_IMUX24_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD16.GTPE2_IMUX32_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD17.GTPE2_IMUX24_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD18.GTPE2_IMUX32_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD19.GTPE2_IMUX24_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD20.GTPE2_IMUX5_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD21.GTPE2_IMUX5_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD22.GTPE2_IMUX5_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD23.GTPE2_IMUX5_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD24.GTPE2_IMUX5_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD110.GTPE2_IMUX40_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD111.GTPE2_IMUX40_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD112.GTPE2_IMUX0_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD113.GTPE2_IMUX0_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD114.GTPE2_IMUX0_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PLLRSVD115.GTPE2_IMUX0_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD0.GTPE2_IMUX20_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD1.GTPE2_IMUX20_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD2.GTPE2_IMUX20_3 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD3.GTPE2_IMUX20_2 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD4.GTPE2_IMUX20_1 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD5.GTPE2_IMUX41_5 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD6.GTPE2_IMUX41_4 always +GTP_COMMON_MID_RIGHT.GTPE2_COMMON_PMARSVD7.GTPE2_IMUX41_2 always diff --git a/artix7/ppips_gtp_int_interface.db b/artix7/ppips_gtp_int_interface.db new file mode 100644 index 0000000..0f88d75 --- /dev/null +++ b/artix7/ppips_gtp_int_interface.db @@ -0,0 +1,48 @@ +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT0.GTPE2_INT_INTERFACE_IMUX0 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT1.GTPE2_INT_INTERFACE_IMUX1 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT2.GTPE2_INT_INTERFACE_IMUX2 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT3.GTPE2_INT_INTERFACE_IMUX3 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT4.GTPE2_INT_INTERFACE_IMUX4 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT5.GTPE2_INT_INTERFACE_IMUX5 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT6.GTPE2_INT_INTERFACE_IMUX6 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT7.GTPE2_INT_INTERFACE_IMUX7 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT8.GTPE2_INT_INTERFACE_IMUX8 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT9.GTPE2_INT_INTERFACE_IMUX9 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT10.GTPE2_INT_INTERFACE_IMUX10 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT11.GTPE2_INT_INTERFACE_IMUX11 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT12.GTPE2_INT_INTERFACE_IMUX12 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT13.GTPE2_INT_INTERFACE_IMUX13 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT14.GTPE2_INT_INTERFACE_IMUX14 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT15.GTPE2_INT_INTERFACE_IMUX15 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT16.GTPE2_INT_INTERFACE_IMUX16 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT17.GTPE2_INT_INTERFACE_IMUX17 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT18.GTPE2_INT_INTERFACE_IMUX18 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT19.GTPE2_INT_INTERFACE_IMUX19 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT20.GTPE2_INT_INTERFACE_IMUX20 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT21.GTPE2_INT_INTERFACE_IMUX21 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT22.GTPE2_INT_INTERFACE_IMUX22 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT23.GTPE2_INT_INTERFACE_IMUX23 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT24.GTPE2_INT_INTERFACE_IMUX24 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT25.GTPE2_INT_INTERFACE_IMUX25 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT26.GTPE2_INT_INTERFACE_IMUX26 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT27.GTPE2_INT_INTERFACE_IMUX27 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT28.GTPE2_INT_INTERFACE_IMUX28 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT29.GTPE2_INT_INTERFACE_IMUX29 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT30.GTPE2_INT_INTERFACE_IMUX30 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT31.GTPE2_INT_INTERFACE_IMUX31 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT32.GTPE2_INT_INTERFACE_IMUX32 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT33.GTPE2_INT_INTERFACE_IMUX33 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT34.GTPE2_INT_INTERFACE_IMUX34 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT35.GTPE2_INT_INTERFACE_IMUX35 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT36.GTPE2_INT_INTERFACE_IMUX36 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT37.GTPE2_INT_INTERFACE_IMUX37 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT38.GTPE2_INT_INTERFACE_IMUX38 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT39.GTPE2_INT_INTERFACE_IMUX39 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT40.GTPE2_INT_INTERFACE_IMUX40 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT41.GTPE2_INT_INTERFACE_IMUX41 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT42.GTPE2_INT_INTERFACE_IMUX42 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT43.GTPE2_INT_INTERFACE_IMUX43 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT44.GTPE2_INT_INTERFACE_IMUX44 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT45.GTPE2_INT_INTERFACE_IMUX45 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT46.GTPE2_INT_INTERFACE_IMUX46 always +GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_OUT47.GTPE2_INT_INTERFACE_IMUX47 always diff --git a/artix7/segbits_int_l.origin_info.db b/artix7/segbits_int_l.origin_info.db index 315d82a..adb181a 100644 --- a/artix7/segbits_int_l.origin_info.db +++ b/artix7/segbits_int_l.origin_info.db @@ -2253,7 +2253,7 @@ INT_L.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36 INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39 INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36 INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37 -INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36 +INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36 INT_L.NE6BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_53 04_54 INT_L.NE6BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_53 07_53 INT_L.NE6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_52 07_53 @@ -3302,7 +3302,7 @@ INT_L.SW6BEG1.LOGIC_OUTS_L19 origin:050-pip-seed 06_28 07_29 INT_L.SW6BEG1.LOGIC_OUTS_L23 origin:050-pip-seed 04_30 06_28 INT_L.SW6BEG1.LV_L9 origin:056-pip-rem 04_30 05_28 INT_L.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29 -INT_L.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28 +INT_L.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28 INT_L.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29 INT_L.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31 INT_L.SW6BEG1.NW6END2 origin:050-pip-seed 05_31 06_28 @@ -3323,7 +3323,7 @@ INT_L.SW6BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 06_44 07_45 INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44 INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45 -INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44 +INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44 INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47 INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44 INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45 @@ -3348,7 +3348,7 @@ INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61 INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60 INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60 INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61 -INT_L.SW6BEG3.SE6END3 origin:056-pip-rem 04_61 06_60 +INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60 INT_L.SW6BEG3.SS2END3 origin:050-pip-seed 03_60 03_61 INT_L.SW6BEG3.SS6END3 origin:050-pip-seed 03_61 06_60 INT_L.SW6BEG3.SW2END3 origin:050-pip-seed 02_61 03_61 diff --git a/artix7/segbits_int_r.origin_info.db b/artix7/segbits_int_r.origin_info.db index a3d7b1e..ff8d7a3 100644 --- a/artix7/segbits_int_r.origin_info.db +++ b/artix7/segbits_int_r.origin_info.db @@ -237,7 +237,7 @@ INT_R.FAN_ALT0.FAN_BOUNCE4 origin:050-pip-seed !22_00 20_00 23_00 24_00 25_00 INT_R.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00 INT_R.FAN_ALT0.LOGIC_OUTS0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00 INT_R.FAN_ALT0.LOGIC_OUTS12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00 -INT_R.FAN_ALT0.LOGIC_OUTS22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00 +INT_R.FAN_ALT0.LOGIC_OUTS22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00 INT_R.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00 INT_R.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00 INT_R.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00 @@ -328,11 +328,11 @@ INT_R.FAN_ALT3.WR1END3 origin:050-pip-seed !23_56 16_56 22_56 24_56 25_56 INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56 INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08 INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08 -INT_R.FAN_ALT4.FAN_BOUNCE2 origin:056-pip-rem !23_08 20_08 22_08 24_08 25_08 +INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08 -INT_R.FAN_ALT4.LOGIC_OUTS18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08 +INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 INT_R.FAN_ALT4.SR1BEG_S0 origin:050-pip-seed !23_08 19_09 22_08 24_08 25_08 INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08 INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08 @@ -2253,7 +2253,7 @@ INT_R.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36 INT_R.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39 INT_R.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36 INT_R.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37 -INT_R.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36 +INT_R.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36 INT_R.NE6BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_53 04_54 INT_R.NE6BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_53 07_53 INT_R.NE6BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_52 07_53 @@ -3281,7 +3281,7 @@ INT_R.SW6BEG0.LOGIC_OUTS12 origin:050-pip-seed 03_12 07_13 INT_R.SW6BEG0.LOGIC_OUTS18 origin:050-pip-seed 04_14 06_12 INT_R.SW6BEG0.LOGIC_OUTS22 origin:050-pip-seed 06_12 07_13 INT_R.SW6BEG0.EE2END0 origin:050-pip-seed 03_12 04_13 -INT_R.SW6BEG0.EE4END0 origin:056-pip-rem 04_13 05_12 +INT_R.SW6BEG0.EE4END0 origin:050-pip-seed 04_13 05_12 INT_R.SW6BEG0.LH12 origin:056-pip-rem 05_12 07_13 INT_R.SW6BEG0.LV0 origin:056-pip-rem 04_14 05_12 INT_R.SW6BEG0.NW2END1 origin:050-pip-seed 02_13 05_15 @@ -3603,7 +3603,7 @@ INT_R.WW4BEG2.LOGIC_OUTS20 origin:050-pip-seed 04_34 06_32 INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32 INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33 INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35 -INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35 +INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35 INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35 INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32 INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33 diff --git a/artix7/segbits_liob33.db b/artix7/segbits_liob33.db index 940d83b..4d9f02a 100644 --- a/artix7/segbits_liob33.db +++ b/artix7/segbits_liob33.db @@ -5,43 +5,42 @@ LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 38_120 38_122 39_121 39_123 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 38_120 38_122 !39_121 39_123 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 38_120 !38_122 !39_121 39_123 LIOB33.IOB_Y0.INTERMDISABLE.I 39_89 -LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 38_118 39_65 39_75 39_97 !39_101 39_113 39_119 39_125 -LIOB33.IOB_Y0.LVDS_25.IN 38_86 39_87 -LIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 39_65 39_75 !39_101 -LIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_112 !38_118 38_126 39_65 39_117 39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 !38_112 38_118 !38_126 39_65 39_75 39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 !38_110 !38_112 !38_126 39_65 39_75 !39_101 !39_105 !39_109 !39_117 !39_127 +LIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 +LIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_117 39_119 !39_125 !39_127 LIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93 -LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_118 39_65 !39_75 !39_97 39_101 39_113 39_119 39_125 -LIOB33.IOB_Y0.TMDS_33.IN 38_86 !39_87 -LIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 39_65 !39_75 39_101 +LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 39_101 39_113 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.TMDS_33.IN_DIFF 38_86 !39_85 !39_87 +LIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 !38_110 !38_112 !38_126 39_65 !39_75 39_101 !39_105 !39_109 !39_117 !39_127 LIOB33.IOB_Y0.ZIBUF_LOW_PWR 38_84 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 38_112 38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_86 39_85 !39_87 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 39_95 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 39_119 !39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 -LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 39_127 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 38_112 !38_118 38_126 39_65 39_113 39_117 39_119 !39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 !39_127 LIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN 38_86 39_85 39_87 -LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_112 38_118 !38_126 39_65 39_117 !39_119 !39_125 39_127 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 39_127 LIOB33.IOB_Y0.SSTL135_SSTL15.IN !38_86 !39_85 39_87 -LIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 LIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST !38_106 38_110 39_105 39_107 39_109 39_111 LIOB33.IOB_Y1.IBUFDISABLE.I 39_45 LIOB33.IOB_Y1.IN_TERM.NONE !38_04 !38_06 !39_05 !39_07 diff --git a/artix7/segbits_liob33.origin_info.db b/artix7/segbits_liob33.origin_info.db index b07739c..022593c 100644 --- a/artix7/segbits_liob33.origin_info.db +++ b/artix7/segbits_liob33.origin_info.db @@ -5,43 +5,42 @@ LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_120 38_122 39_121 39_12 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !39_121 38_120 38_122 39_123 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_122 !39_121 38_120 39_123 LIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89 -LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !39_101 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 -LIOB33.IOB_Y0.LVDS_25.IN origin:030-iob 38_86 39_87 -LIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !39_101 38_102 38_64 38_74 38_76 38_98 39_65 39_75 -LIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_112 !38_118 !39_125 !39_127 38_126 38_64 39_117 39_119 39_65 +LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !38_112 !38_126 !39_101 !39_117 !39_127 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 +LIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !38_110 !38_112 !38_126 !39_101 !39_105 !39_109 !39_117 !39_127 38_102 38_64 38_74 38_76 38_98 39_65 39_75 +LIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 +LIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_126 38_64 39_117 39_119 39_65 LIOB33.IOB_Y0.PULLTYPE.KEEPER origin:030-iob !39_93 38_92 38_94 LIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94 LIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93 -LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 -LIOB33.IOB_Y0.TMDS_33.IN origin:030-iob !39_87 38_86 -LIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_74 !38_76 !38_98 !39_75 38_64 39_101 39_65 +LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_117 !39_127 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 +LIOB33.IOB_Y0.TMDS_33.IN_DIFF origin:030-iob !39_85 !39_87 38_86 +LIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_110 !38_112 !38_126 !38_74 !38_76 !38_98 !39_105 !39_109 !39_117 !39_127 !39_75 38_64 39_101 39_65 LIOB33.IOB_Y0.ZIBUF_LOW_PWR origin:030-iob 38_84 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 38_112 38_118 38_126 38_64 39_113 39_125 39_65 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 38_112 38_126 38_64 39_113 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_125 39_65 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_126 38_64 39_113 39_127 39_65 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !39_87 38_86 39_85 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 39_95 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 38_112 38_64 39_113 39_119 39_65 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 38_112 38_64 39_113 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_113 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !39_119 !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_118 !39_117 !39_127 38_112 38_126 38_64 39_113 39_119 39_125 39_65 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_118 !39_117 !39_119 38_112 38_126 38_64 39_113 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_118 !39_125 !39_127 38_112 38_126 38_64 39_113 39_117 39_119 39_65 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 !39_127 38_112 38_64 39_113 39_65 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !39_119 !39_125 !39_127 38_112 38_118 38_126 38_64 39_113 39_117 39_65 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_119 39_65 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_64 39_113 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_118 38_64 39_113 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_65 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_126 38_64 39_113 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_117 39_119 39_65 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_65 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_65 LIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_86 39_85 39_87 -LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_112 !38_126 !39_119 !39_125 38_118 38_64 39_117 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_112 !38_126 !39_117 !39_119 38_118 38_64 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_112 !38_118 !39_117 !39_127 38_126 38_64 39_119 39_125 39_65 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_112 !38_118 !39_117 !39_119 38_126 38_64 39_125 39_127 39_65 -LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_118 38_64 39_117 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_118 38_64 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_126 38_64 39_119 39_125 39_65 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_126 38_64 39_125 39_127 39_65 +LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 LIOB33.IOB_Y0.SSTL135_SSTL15.IN origin:030-iob !38_86 !39_85 39_87 -LIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 LIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111 LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 LIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07 diff --git a/artix7/segbits_pcie_int_interface_l.db b/artix7/segbits_pcie_int_interface_l.db index 979c2a3..d5a0564 100644 --- a/artix7/segbits_pcie_int_interface_l.db +++ b/artix7/segbits_pcie_int_interface_l.db @@ -16,6 +16,8 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L_D PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L_DELAY15 26_58 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L_DELAY16 26_03 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L_DELAY17 26_11 +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L_DELAY18 26_19 +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L_DELAY19 26_27 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L_DELAY20 26_35 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L_DELAY32 27_05 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L_DELAY33 27_13 diff --git a/artix7/segbits_pcie_int_interface_l.origin_info.db b/artix7/segbits_pcie_int_interface_l.origin_info.db index 466d7c5..08c50a9 100644 --- a/artix7/segbits_pcie_int_interface_l.origin_info.db +++ b/artix7/segbits_pcie_int_interface_l.origin_info.db @@ -16,6 +16,8 @@ PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT14.PCIE_INT_INTERFACE_IMUX_L_D PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT15.PCIE_INT_INTERFACE_IMUX_L_DELAY15 origin:062-pcie-int-pips 26_58 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT16.PCIE_INT_INTERFACE_IMUX_L_DELAY16 origin:062-pcie-int-pips 26_03 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT17.PCIE_INT_INTERFACE_IMUX_L_DELAY17 origin:062-pcie-int-pips 26_11 +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT18.PCIE_INT_INTERFACE_IMUX_L_DELAY18 origin:062-pcie-int-pips 26_19 +PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT19.PCIE_INT_INTERFACE_IMUX_L_DELAY19 origin:062-pcie-int-pips 26_27 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT20.PCIE_INT_INTERFACE_IMUX_L_DELAY20 origin:062-pcie-int-pips 26_35 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT32.PCIE_INT_INTERFACE_IMUX_L_DELAY32 origin:062-pcie-int-pips 27_05 PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_OUT33.PCIE_INT_INTERFACE_IMUX_L_DELAY33 origin:062-pcie-int-pips 27_13 diff --git a/artix7/segbits_riob33.db b/artix7/segbits_riob33.db index 9e24932..a4b4403 100644 --- a/artix7/segbits_riob33.db +++ b/artix7/segbits_riob33.db @@ -5,43 +5,42 @@ RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 38_120 38_122 39_121 39_123 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 38_120 38_122 !39_121 39_123 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 38_120 !38_122 !39_121 39_123 RIOB33.IOB_Y0.INTERMDISABLE.I 39_89 -RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 38_118 39_65 39_75 39_97 !39_101 39_113 39_119 39_125 -RIOB33.IOB_Y0.LVDS_25.IN 38_86 39_87 -RIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 39_65 39_75 !39_101 -RIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_112 !38_118 38_126 39_65 39_117 39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 !38_112 38_118 !38_126 39_65 39_75 39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 !38_110 !38_112 !38_126 39_65 39_75 !39_101 !39_105 !39_109 !39_117 !39_127 +RIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 +RIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_117 39_119 !39_125 !39_127 RIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93 -RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_118 39_65 !39_75 !39_97 39_101 39_113 39_119 39_125 -RIOB33.IOB_Y0.TMDS_33.IN 38_86 !39_87 -RIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 39_65 !39_75 39_101 +RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 39_101 39_113 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.TMDS_33.IN_DIFF 38_86 !39_85 !39_87 +RIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 !38_110 !38_112 !38_126 39_65 !39_75 39_101 !39_105 !39_109 !39_117 !39_127 RIOB33.IOB_Y0.ZIBUF_LOW_PWR 38_84 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 38_112 38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_86 39_85 !39_87 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 39_95 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 39_119 !39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 -RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 39_127 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 38_112 !38_118 38_126 39_65 39_113 39_117 39_119 !39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 !39_127 RIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN 38_86 39_85 39_87 -RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_112 38_118 !38_126 39_65 39_117 !39_119 !39_125 39_127 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 39_127 RIOB33.IOB_Y0.SSTL135_SSTL15.IN !38_86 !39_85 39_87 -RIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 RIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST !38_106 38_110 39_105 39_107 39_109 39_111 RIOB33.IOB_Y1.IBUFDISABLE.I 39_45 RIOB33.IOB_Y1.IN_TERM.NONE !38_04 !38_06 !39_05 !39_07 diff --git a/artix7/segbits_riob33.origin_info.db b/artix7/segbits_riob33.origin_info.db index d2b5b14..95c9159 100644 --- a/artix7/segbits_riob33.origin_info.db +++ b/artix7/segbits_riob33.origin_info.db @@ -5,43 +5,42 @@ RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_120 38_122 39_121 39_12 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !39_121 38_120 38_122 39_123 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_122 !39_121 38_120 39_123 RIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89 -RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !39_101 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 -RIOB33.IOB_Y0.LVDS_25.IN origin:030-iob 38_86 39_87 -RIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !39_101 38_102 38_64 38_74 38_76 38_98 39_65 39_75 -RIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_112 !38_118 !39_125 !39_127 38_126 38_64 39_117 39_119 39_65 +RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !38_112 !38_126 !39_101 !39_117 !39_127 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 +RIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !38_110 !38_112 !38_126 !39_101 !39_105 !39_109 !39_117 !39_127 38_102 38_64 38_74 38_76 38_98 39_65 39_75 +RIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 +RIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_126 38_64 39_117 39_119 39_65 RIOB33.IOB_Y0.PULLTYPE.KEEPER origin:030-iob !39_93 38_92 38_94 RIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94 RIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93 -RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 -RIOB33.IOB_Y0.TMDS_33.IN origin:030-iob !39_87 38_86 -RIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_74 !38_76 !38_98 !39_75 38_64 39_101 39_65 +RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_117 !39_127 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 +RIOB33.IOB_Y0.TMDS_33.IN_DIFF origin:030-iob !39_85 !39_87 38_86 +RIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_110 !38_112 !38_126 !38_74 !38_76 !38_98 !39_105 !39_109 !39_117 !39_127 !39_75 38_64 39_101 39_65 RIOB33.IOB_Y0.ZIBUF_LOW_PWR origin:030-iob 38_84 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 38_112 38_118 38_126 38_64 39_113 39_125 39_65 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 38_112 38_126 38_64 39_113 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_125 39_65 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_126 38_64 39_113 39_127 39_65 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !39_87 38_86 39_85 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 39_95 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 38_112 38_64 39_113 39_119 39_65 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 38_112 38_64 39_113 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_113 39_125 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !39_119 !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_118 !39_117 !39_127 38_112 38_126 38_64 39_113 39_119 39_125 39_65 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_118 !39_117 !39_119 38_112 38_126 38_64 39_113 39_125 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_118 !39_125 !39_127 38_112 38_126 38_64 39_113 39_117 39_119 39_65 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 !39_127 38_112 38_64 39_113 39_65 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !39_119 !39_125 !39_127 38_112 38_118 38_126 38_64 39_113 39_117 39_65 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_119 39_65 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_64 39_113 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_118 38_64 39_113 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_65 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_126 38_64 39_113 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_117 39_119 39_65 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_65 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_65 RIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_86 39_85 39_87 -RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_112 !38_126 !39_119 !39_125 38_118 38_64 39_117 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_112 !38_126 !39_117 !39_119 38_118 38_64 39_125 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_112 !38_118 !39_117 !39_127 38_126 38_64 39_119 39_125 39_65 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_112 !38_118 !39_117 !39_119 38_126 38_64 39_125 39_127 39_65 -RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_118 38_64 39_117 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_118 38_64 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_126 38_64 39_119 39_125 39_65 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_126 38_64 39_125 39_127 39_65 +RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 RIOB33.IOB_Y0.SSTL135_SSTL15.IN origin:030-iob !38_86 !39_85 39_87 -RIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 RIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111 RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 RIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07 diff --git a/kintex7/segbits_int_l.origin_info.db b/kintex7/segbits_int_l.origin_info.db index a42a1c9..2ce0735 100644 --- a/kintex7/segbits_int_l.origin_info.db +++ b/kintex7/segbits_int_l.origin_info.db @@ -1937,7 +1937,7 @@ INT_L.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56 INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59 INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56 INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59 -INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59 +INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59 INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21 INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21 INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21 @@ -2273,7 +2273,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53 -INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52 +INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17 INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17 INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17 @@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00 -INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03 +INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03 @@ -3323,7 +3323,7 @@ INT_L.SW6BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 06_44 07_45 INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44 INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45 -INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44 +INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44 INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47 INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44 INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45 @@ -3345,7 +3345,7 @@ INT_L.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63 INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60 INT_L.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63 INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61 -INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60 +INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60 INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60 INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61 INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60 diff --git a/kintex7/segbits_int_r.origin_info.db b/kintex7/segbits_int_r.origin_info.db index 43e1106..a2da8b9 100644 --- a/kintex7/segbits_int_r.origin_info.db +++ b/kintex7/segbits_int_r.origin_info.db @@ -3344,7 +3344,7 @@ INT_R.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63 INT_R.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60 INT_R.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63 INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61 -INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60 +INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60 INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60 INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61 INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61 @@ -3603,7 +3603,7 @@ INT_R.WW4BEG2.LOGIC_OUTS20 origin:050-pip-seed 04_34 06_32 INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32 INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33 INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35 -INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35 +INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35 INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35 INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32 INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33 diff --git a/kintex7/segbits_liob33.db b/kintex7/segbits_liob33.db index 940d83b..4d9f02a 100644 --- a/kintex7/segbits_liob33.db +++ b/kintex7/segbits_liob33.db @@ -5,43 +5,42 @@ LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 38_120 38_122 39_121 39_123 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 38_120 38_122 !39_121 39_123 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 38_120 !38_122 !39_121 39_123 LIOB33.IOB_Y0.INTERMDISABLE.I 39_89 -LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 38_118 39_65 39_75 39_97 !39_101 39_113 39_119 39_125 -LIOB33.IOB_Y0.LVDS_25.IN 38_86 39_87 -LIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 39_65 39_75 !39_101 -LIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_112 !38_118 38_126 39_65 39_117 39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 !38_112 38_118 !38_126 39_65 39_75 39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 !38_110 !38_112 !38_126 39_65 39_75 !39_101 !39_105 !39_109 !39_117 !39_127 +LIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 +LIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_117 39_119 !39_125 !39_127 LIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93 -LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_118 39_65 !39_75 !39_97 39_101 39_113 39_119 39_125 -LIOB33.IOB_Y0.TMDS_33.IN 38_86 !39_87 -LIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 39_65 !39_75 39_101 +LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 39_101 39_113 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.TMDS_33.IN_DIFF 38_86 !39_85 !39_87 +LIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 !38_110 !38_112 !38_126 39_65 !39_75 39_101 !39_105 !39_109 !39_117 !39_127 LIOB33.IOB_Y0.ZIBUF_LOW_PWR 38_84 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 38_112 38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_86 39_85 !39_87 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 39_95 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 39_119 !39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 -LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 39_127 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 38_112 !38_118 38_126 39_65 39_113 39_117 39_119 !39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 !39_127 LIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN 38_86 39_85 39_87 -LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_112 38_118 !38_126 39_65 39_117 !39_119 !39_125 39_127 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 39_127 LIOB33.IOB_Y0.SSTL135_SSTL15.IN !38_86 !39_85 39_87 -LIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 LIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST !38_106 38_110 39_105 39_107 39_109 39_111 LIOB33.IOB_Y1.IBUFDISABLE.I 39_45 LIOB33.IOB_Y1.IN_TERM.NONE !38_04 !38_06 !39_05 !39_07 diff --git a/kintex7/segbits_liob33.origin_info.db b/kintex7/segbits_liob33.origin_info.db index b07739c..022593c 100644 --- a/kintex7/segbits_liob33.origin_info.db +++ b/kintex7/segbits_liob33.origin_info.db @@ -5,43 +5,42 @@ LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_120 38_122 39_121 39_12 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !39_121 38_120 38_122 39_123 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_122 !39_121 38_120 39_123 LIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89 -LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !39_101 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 -LIOB33.IOB_Y0.LVDS_25.IN origin:030-iob 38_86 39_87 -LIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !39_101 38_102 38_64 38_74 38_76 38_98 39_65 39_75 -LIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_112 !38_118 !39_125 !39_127 38_126 38_64 39_117 39_119 39_65 +LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !38_112 !38_126 !39_101 !39_117 !39_127 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 +LIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !38_110 !38_112 !38_126 !39_101 !39_105 !39_109 !39_117 !39_127 38_102 38_64 38_74 38_76 38_98 39_65 39_75 +LIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 +LIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_126 38_64 39_117 39_119 39_65 LIOB33.IOB_Y0.PULLTYPE.KEEPER origin:030-iob !39_93 38_92 38_94 LIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94 LIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93 -LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 -LIOB33.IOB_Y0.TMDS_33.IN origin:030-iob !39_87 38_86 -LIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_74 !38_76 !38_98 !39_75 38_64 39_101 39_65 +LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_117 !39_127 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 +LIOB33.IOB_Y0.TMDS_33.IN_DIFF origin:030-iob !39_85 !39_87 38_86 +LIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_110 !38_112 !38_126 !38_74 !38_76 !38_98 !39_105 !39_109 !39_117 !39_127 !39_75 38_64 39_101 39_65 LIOB33.IOB_Y0.ZIBUF_LOW_PWR origin:030-iob 38_84 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 38_112 38_118 38_126 38_64 39_113 39_125 39_65 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 38_112 38_126 38_64 39_113 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_125 39_65 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_126 38_64 39_113 39_127 39_65 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !39_87 38_86 39_85 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 39_95 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 38_112 38_64 39_113 39_119 39_65 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 38_112 38_64 39_113 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_113 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !39_119 !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_118 !39_117 !39_127 38_112 38_126 38_64 39_113 39_119 39_125 39_65 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_118 !39_117 !39_119 38_112 38_126 38_64 39_113 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_118 !39_125 !39_127 38_112 38_126 38_64 39_113 39_117 39_119 39_65 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 !39_127 38_112 38_64 39_113 39_65 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !39_119 !39_125 !39_127 38_112 38_118 38_126 38_64 39_113 39_117 39_65 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_119 39_65 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_64 39_113 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_118 38_64 39_113 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_65 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_126 38_64 39_113 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_117 39_119 39_65 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_65 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_65 LIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_86 39_85 39_87 -LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_112 !38_126 !39_119 !39_125 38_118 38_64 39_117 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_112 !38_126 !39_117 !39_119 38_118 38_64 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_112 !38_118 !39_117 !39_127 38_126 38_64 39_119 39_125 39_65 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_112 !38_118 !39_117 !39_119 38_126 38_64 39_125 39_127 39_65 -LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_118 38_64 39_117 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_118 38_64 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_126 38_64 39_119 39_125 39_65 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_126 38_64 39_125 39_127 39_65 +LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 LIOB33.IOB_Y0.SSTL135_SSTL15.IN origin:030-iob !38_86 !39_85 39_87 -LIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 LIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111 LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 LIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07 diff --git a/kintex7/segbits_riob33.db b/kintex7/segbits_riob33.db index 9e24932..a4b4403 100644 --- a/kintex7/segbits_riob33.db +++ b/kintex7/segbits_riob33.db @@ -5,43 +5,42 @@ RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 38_120 38_122 39_121 39_123 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 38_120 38_122 !39_121 39_123 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 38_120 !38_122 !39_121 39_123 RIOB33.IOB_Y0.INTERMDISABLE.I 39_89 -RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 38_118 39_65 39_75 39_97 !39_101 39_113 39_119 39_125 -RIOB33.IOB_Y0.LVDS_25.IN 38_86 39_87 -RIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 39_65 39_75 !39_101 -RIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_112 !38_118 38_126 39_65 39_117 39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 !38_112 38_118 !38_126 39_65 39_75 39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 !38_110 !38_112 !38_126 39_65 39_75 !39_101 !39_105 !39_109 !39_117 !39_127 +RIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 +RIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_117 39_119 !39_125 !39_127 RIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93 -RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_118 39_65 !39_75 !39_97 39_101 39_113 39_119 39_125 -RIOB33.IOB_Y0.TMDS_33.IN 38_86 !39_87 -RIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 39_65 !39_75 39_101 +RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 39_101 39_113 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.TMDS_33.IN_DIFF 38_86 !39_85 !39_87 +RIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 !38_110 !38_112 !38_126 39_65 !39_75 39_101 !39_105 !39_109 !39_117 !39_127 RIOB33.IOB_Y0.ZIBUF_LOW_PWR 38_84 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 38_112 38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_86 39_85 !39_87 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 39_95 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 39_119 !39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 -RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 39_127 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 38_112 !38_118 38_126 39_65 39_113 39_117 39_119 !39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 !39_127 RIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN 38_86 39_85 39_87 -RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_112 38_118 !38_126 39_65 39_117 !39_119 !39_125 39_127 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 39_127 RIOB33.IOB_Y0.SSTL135_SSTL15.IN !38_86 !39_85 39_87 -RIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 RIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST !38_106 38_110 39_105 39_107 39_109 39_111 RIOB33.IOB_Y1.IBUFDISABLE.I 39_45 RIOB33.IOB_Y1.IN_TERM.NONE !38_04 !38_06 !39_05 !39_07 diff --git a/kintex7/segbits_riob33.origin_info.db b/kintex7/segbits_riob33.origin_info.db index d2b5b14..95c9159 100644 --- a/kintex7/segbits_riob33.origin_info.db +++ b/kintex7/segbits_riob33.origin_info.db @@ -5,43 +5,42 @@ RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_120 38_122 39_121 39_12 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !39_121 38_120 38_122 39_123 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_122 !39_121 38_120 39_123 RIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89 -RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !39_101 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 -RIOB33.IOB_Y0.LVDS_25.IN origin:030-iob 38_86 39_87 -RIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !39_101 38_102 38_64 38_74 38_76 38_98 39_65 39_75 -RIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_112 !38_118 !39_125 !39_127 38_126 38_64 39_117 39_119 39_65 +RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !38_112 !38_126 !39_101 !39_117 !39_127 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 +RIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !38_110 !38_112 !38_126 !39_101 !39_105 !39_109 !39_117 !39_127 38_102 38_64 38_74 38_76 38_98 39_65 39_75 +RIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 +RIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_126 38_64 39_117 39_119 39_65 RIOB33.IOB_Y0.PULLTYPE.KEEPER origin:030-iob !39_93 38_92 38_94 RIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94 RIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93 -RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 -RIOB33.IOB_Y0.TMDS_33.IN origin:030-iob !39_87 38_86 -RIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_74 !38_76 !38_98 !39_75 38_64 39_101 39_65 +RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_117 !39_127 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 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+RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 39_95 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 38_112 38_64 39_113 39_119 39_65 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 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+++ /dev/null @@ -1,73 +0,0 @@ -# [Zynq Harnesses](.) - -Current using Project X-Ray requires a bitstream "harness" which connects IO -into the ROI. - -Once you have the "harness" bitstream, you can place and route designs using -only open source tools despite Project X-Ray still not understand how to -configure the complete bitstream and IO tiles. - ---- - -# Boards - -Currently supported boards are listed below, they are; - * [Zybo Z7-10](#Zybo%2Z7-10) - -## [Zybo Z7-10](zybo) - - * FPGA Part: `XC7Z010-1CLG400C` - * Cost: $USD 199.00 - * [Buy Zybo Z7 from Digilent](https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/) - -**Only** the Zybo Z7-10 version of the board is currently supported. - -Both the original Zybo and the Zybo Z7-20 are **not** supported. - - -Description from the [Digilent website](https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/); -> The Zybo Z7 is a feature-rich, ready-to-use embedded software and digital -> circuit development board built around the Xilinx Zynq-7000 family. This is -> the second generation update to the popular Zybo that was released in 2012. -> The Zynq family is based on the Xilinx All Programmable System-on-Chip (AP -> SoC) architecture, which tightly integrates a dual-core ARM Cortex-A9 -> processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. -> The Zybo Z7 surrounds the Zynq with a rich set of multimedia and connectivity -> peripherals to create a formidable single-board computer, even before -> considering the flexibility and power added by the FPGA. The Zybo Z7's -> video-capable feature set, including a MIPI CSI-2 compatible Pcam connector, -> HDMI input, HDMI output, and high DDR3L bandwidth, was chosen to make it an -> affordable solution for the high end embedded vision applications that Xilinx -> FPGAs are popular for. Attaching additional hardware is made easy by the Zybo -> Z7's Pmod connectors, allowing access to Digilent's catalog of over 70 Pmod -> peripheral boards, including motor controllers, sensors, displays, and more. - -Supported harness configurations; - * [SWBUT](#swbut) - ---- - -# Configurations - -Currently supported boards are listed below, they are; - * [SWBUT](#swbut) - * [PMOD](#pmod) - -## SWBUT - -Harness which maps a board's switches, buttons and LEDs into the region of -interest (plus clock). - -Supported boards; - * [Arty A7-35T](../../artix7/harness/README.md#Arty%20A7-35T) - * [Basys 3](../../artix7/harness/README.md#Basys%203) - * [Zybo Z7-10](#Zybo%2Z7-10) - -## PMOD - -Harness which maps a board's PMOD connectors into the region of interest (plus -a clock). - -Supported boards; - * [Arty A7-35T](../../artix7/harness/README.md#Arty%20A7-35T) - diff --git a/zynq7/harness/zybo/swbut/design.bit b/zynq7/harness/zybo/swbut/design.bit deleted file mode 100644 index e59cc86..0000000 Binary files a/zynq7/harness/zybo/swbut/design.bit and /dev/null differ diff --git a/zynq7/harness/zybo/swbut/design.dcp b/zynq7/harness/zybo/swbut/design.dcp deleted file mode 100644 index e5484bb..0000000 Binary files a/zynq7/harness/zybo/swbut/design.dcp and /dev/null differ diff --git a/zynq7/harness/zybo/swbut/design.json b/zynq7/harness/zybo/swbut/design.json deleted file mode 100644 index 60480ce..0000000 --- a/zynq7/harness/zybo/swbut/design.json +++ /dev/null @@ -1,483 +0,0 @@ -{ - "info": { - "GRID_X_MAX": 118, - "GRID_X_MIN": 83, - "GRID_Y_MAX": 51, - "GRID_Y_MIN": 0 - }, - "ports": [ - { - "name": "clk", - "node": "CLK_HROW_TOP_R_X82Y78/CLK_HROW_CK_BUFHCLK_R0", - "pin": "K17", - "wire": "HCLK_VBRK_X83Y78/HCLK_VBRK_CK_BUFHCLK0" - }, - { - "name": "din[0]", - "node": "INT_R_X31Y53/WW2BEG1", - "pin": "J15", - "wire": "VBRK_X118Y56/VBRK_WW2END1", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_2", - "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_3", - "INT_INTERFACE_L_X30Y53/INT_INTERFACE_WW2END1", - "INT_L_X30Y50/NE6BEG1", - "INT_L_X30Y50/WW2END0", - "INT_L_X30Y53/WW2A1", - "INT_R_X31Y50/EE2BEG0", - "INT_R_X31Y50/LOGIC_OUTS18", - "INT_R_X31Y50/NE6A1", - "INT_R_X31Y50/WW2A0", - "INT_R_X31Y51/NE6B1", - "INT_R_X31Y52/NE6C1", - "INT_R_X31Y53/NE6D1", - "INT_R_X31Y53/SR1END1", - "INT_R_X31Y53/WW2BEG1", - "INT_R_X31Y54/NE6E1", - "INT_R_X31Y54/NW6END1", - "INT_R_X31Y54/SR1BEG1", - "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_EE2BEG0", - "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_LOGIC_OUTS_B18", - "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_WW2A0", - "IO_INT_INTERFACE_R_X31Y54/INT_INTERFACE_NE4C1", - "IO_INT_INTERFACE_R_X31Y54/INT_INTERFACE_NW4END1", - "RIOB33_SING_X31Y50/IOB_IBUF0", - "RIOI3_SING_X31Y50/IOI_ILOGIC0_O", - "RIOI3_SING_X31Y50/IOI_LOGIC_OUTS18_0", - "RIOI3_SING_X31Y50/RIOI_I0", - "RIOI3_SING_X31Y50/RIOI_IBUF0", - "RIOI3_SING_X31Y50/RIOI_ILOGIC0_D", - "R_TERM_INT_X125Y53/R_TERM_INT_WW2A0", - "R_TERM_INT_X125Y53/TERM_INT_LOGIC_OUTS_L_B18", - "R_TERM_INT_X125Y57/R_TERM_INT_NW4END1" - ] - }, - { - "name": "din[1]", - "node": "INT_R_X31Y56/WW2BEG1", - "pin": "G15", - "wire": "VBRK_X118Y59/VBRK_WW2END1", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_5", - "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_6", - "INT_INTERFACE_L_X30Y56/INT_INTERFACE_WW2END1", - "INT_L_X30Y56/WW2A1", - "INT_L_X30Y57/ER1BEG1", - "INT_L_X30Y57/SW6END0", - "INT_R_X31Y56/SL1END1", - "INT_R_X31Y56/WW2BEG1", - "INT_R_X31Y57/ER1END1", - "INT_R_X31Y57/SL1BEG1", - "INT_R_X31Y57/SW6E0", - "INT_R_X31Y58/SW6D0", - "INT_R_X31Y59/SW6C0", - "INT_R_X31Y60/SW6B0", - "INT_R_X31Y61/LOGIC_OUTS18", - "INT_R_X31Y61/SE6BEG0", - "INT_R_X31Y61/SW6A0", - "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_LOGIC_OUTS_B18", - "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_SE4BEG0", - "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_SW4A0", - "RIOB33_X31Y61/IOB_IBUF1", - "RIOI3_X31Y61/IOI_ILOGIC1_O", - "RIOI3_X31Y61/IOI_LOGIC_OUTS18_0", - "RIOI3_X31Y61/RIOI_I1", - "RIOI3_X31Y61/RIOI_IBUF1", - "RIOI3_X31Y61/RIOI_ILOGIC1_D", - "R_TERM_INT_X125Y64/R_TERM_INT_SW4A0", - "R_TERM_INT_X125Y64/TERM_INT_LOGIC_OUTS_L_B18" - ] - }, - { - "name": "din[2]", - "node": "INT_R_X31Y59/WW2BEG1", - "pin": "K18", - "wire": "VBRK_X118Y62/VBRK_WW2END1", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_8", - "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_9", - "HCLK_R_X123Y78/HCLK_LV16", - "INT_INTERFACE_L_X30Y59/INT_INTERFACE_WW2END1", - "INT_L_X30Y59/WW2A1", - "INT_R_X31Y58/LV0", - "INT_R_X31Y59/LV1", - "INT_R_X31Y59/SS2END1", - "INT_R_X31Y59/WW2BEG1", - "INT_R_X31Y60/LV2", - "INT_R_X31Y60/SS2A1", - "INT_R_X31Y61/LV3", - "INT_R_X31Y61/SS2BEG1", - "INT_R_X31Y61/SS6END1", - "INT_R_X31Y62/LV4", - "INT_R_X31Y62/SS6E1", - "INT_R_X31Y63/LV5", - "INT_R_X31Y63/SS6D1", - "INT_R_X31Y64/LV6", - "INT_R_X31Y64/SS6C1", - "INT_R_X31Y65/LV7", - "INT_R_X31Y65/SS6B1", - "INT_R_X31Y66/LV8", - "INT_R_X31Y66/SS6A1", - "INT_R_X31Y67/LV9", - "INT_R_X31Y67/SS6BEG1", - "INT_R_X31Y68/LV10", - "INT_R_X31Y69/LV11", - "INT_R_X31Y70/LV12", - "INT_R_X31Y71/LV13", - "INT_R_X31Y72/LV14", - "INT_R_X31Y73/LV15", - "INT_R_X31Y74/LV16", - "INT_R_X31Y75/LOGIC_OUTS18", - "INT_R_X31Y75/LV17", - "INT_R_X31Y75/NR1BEG0", - "INT_R_X31Y76/LV18", - "INT_R_X31Y76/NR1END0", - "IO_INT_INTERFACE_R_X31Y75/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X31Y75/INT_INTERFACE_LOGIC_OUTS_B18", - "RIOB33_X31Y75/IOB_IBUF1", - "RIOI3_X31Y75/IOI_ILOGIC1_O", - "RIOI3_X31Y75/IOI_LOGIC_OUTS18_0", - "RIOI3_X31Y75/RIOI_I1", - "RIOI3_X31Y75/RIOI_IBUF1", - "RIOI3_X31Y75/RIOI_ILOGIC1_D", - "R_TERM_INT_X125Y79/TERM_INT_LOGIC_OUTS_L_B18" - ] - }, - { - "name": "din[3]", - "node": "INT_R_X31Y62/WW2BEG1", - "pin": "K19", - "wire": "VBRK_X118Y65/VBRK_WW2END1", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_11", - "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_12", - "HCLK_L_X122Y78/HCLK_LV16", - "INT_INTERFACE_L_X30Y62/INT_INTERFACE_WW2END1", - "INT_L_X30Y58/LV_L0", - "INT_L_X30Y59/LV_L1", - "INT_L_X30Y60/LV_L2", - "INT_L_X30Y61/LV_L3", - "INT_L_X30Y62/LV_L4", - "INT_L_X30Y62/WW2A1", - "INT_L_X30Y63/LV_L5", - "INT_L_X30Y64/LV_L6", - "INT_L_X30Y65/LV_L7", - "INT_L_X30Y66/LV_L8", - "INT_L_X30Y67/LV_L9", - "INT_L_X30Y67/SE6BEG1", - "INT_L_X30Y68/LV_L10", - "INT_L_X30Y69/LV_L11", - "INT_L_X30Y70/LV_L12", - "INT_L_X30Y71/LV_L13", - "INT_L_X30Y72/LV_L14", - "INT_L_X30Y73/LV_L15", - "INT_L_X30Y74/LV_L16", - "INT_L_X30Y75/LV_L17", - "INT_L_X30Y76/LV_L18", - "INT_L_X30Y76/SW6END0", - "INT_R_X31Y62/SL1END1", - "INT_R_X31Y62/WW2BEG1", - "INT_R_X31Y63/SE6E1", - "INT_R_X31Y63/SL1BEG1", - "INT_R_X31Y63/SW6END1", - "INT_R_X31Y64/SE6D1", - "INT_R_X31Y65/SE6C1", - "INT_R_X31Y66/SE6B1", - "INT_R_X31Y67/SE6A1", - "INT_R_X31Y76/SW6E0", - "INT_R_X31Y77/SW6D0", - "INT_R_X31Y78/SW6C0", - "INT_R_X31Y79/SW6B0", - "INT_R_X31Y80/LOGIC_OUTS18", - "INT_R_X31Y80/SE6BEG0", - "INT_R_X31Y80/SW6A0", - "IO_INT_INTERFACE_R_X31Y63/INT_INTERFACE_SE4C1", - "IO_INT_INTERFACE_R_X31Y63/INT_INTERFACE_SW4END1", - "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_LOGIC_OUTS18", - "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_LOGIC_OUTS_B18", - "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_SE4BEG0", - "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_SW4A0", - "RIOB33_X31Y79/IOB_IBUF0", - "RIOI3_X31Y79/IOI_ILOGIC0_O", - "RIOI3_X31Y79/IOI_LOGIC_OUTS18_1", - "RIOI3_X31Y79/RIOI_I0", - "RIOI3_X31Y79/RIOI_IBUF0", - "RIOI3_X31Y79/RIOI_ILOGIC0_D", - "R_TERM_INT_X125Y66/R_TERM_INT_SW4END1", - "R_TERM_INT_X125Y84/R_TERM_INT_SW4A0", - "R_TERM_INT_X125Y84/TERM_INT_LOGIC_OUTS_L_B18" - ] - }, - { - "name": "dout[0]", - "node": "INT_R_X29Y81/EE2BEG0", - "pin": "H15", - "wire": "VBRK_X118Y85/VBRK_EE2BEG0", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y85/CMT_FIFO_EE2BEG0_6", - "CMT_TOP_L_UPPER_B_X119Y83/CMT_TOP_EE2BEG0_6", - "INT_INTERFACE_L_X30Y81/INT_INTERFACE_EE2BEG0", - "INT_L_X30Y81/EE2A0", - "INT_R_X31Y81/EE2END0" - ] - }, - { - "name": "dout[1]", - "node": "INT_R_X29Y84/EE2BEG0", - "pin": "E17", - "wire": "VBRK_X118Y88/VBRK_EE2BEG0", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y85/CMT_FIFO_EE2BEG0_9", - "CMT_TOP_L_UPPER_B_X119Y83/CMT_TOP_EE2BEG0_9", - "INT_INTERFACE_L_X30Y84/INT_INTERFACE_EE2BEG0", - "INT_L_X30Y84/EE2A0", - "INT_R_X31Y84/EE2END0" - ] - }, - { - "name": "dout[2]", - "node": "INT_R_X29Y87/EE2BEG0", - "pin": "M14", - "wire": "VBRK_X118Y91/VBRK_EE2BEG0", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_0", - "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_0", - "INT_INTERFACE_L_X30Y87/INT_INTERFACE_EE2BEG0", - "INT_L_X30Y87/EE2A0", - "INT_R_X31Y87/EE2END0" - ] - }, - { - "name": "dout[3]", - "node": "INT_R_X29Y90/EE2BEG0", - "pin": "M15", - "wire": "VBRK_X118Y94/VBRK_EE2BEG0", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_3", - "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_3", - "INT_INTERFACE_L_X30Y90/INT_INTERFACE_EE2BEG0", - "INT_L_X30Y90/EE2A0", - "INT_R_X31Y90/EE2END0" - ] - }, - { - "name": "dout[4]", - "node": "INT_R_X29Y93/EE2BEG0", - "pin": "D18", - "wire": "VBRK_X118Y97/VBRK_EE2BEG0", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_6", - "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_6", - "INT_INTERFACE_L_X30Y93/INT_INTERFACE_EE2BEG0", - "INT_L_X30Y93/EE2A0", - "INT_R_X31Y93/EE2END0" - ] - }, - { - "name": "dout[5]", - "node": "INT_R_X29Y96/EE2BEG0", - "pin": "G14", - "wire": "VBRK_X118Y100/VBRK_EE2BEG0", - "wires_outside_roi": [ - "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_9", - "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_9", - "INT_INTERFACE_L_X30Y96/INT_INTERFACE_EE2BEG0", - "INT_L_X30Y96/EE2A0", - "INT_R_X31Y96/EE2END0" - ] - } - ], - "required_features": [ - "", - "CFG_CENTER_MID_X67Y32.ALWAYS_ON_PROP1", - "CFG_CENTER_MID_X67Y32.ALWAYS_ON_PROP2", - "CFG_CENTER_MID_X67Y32.ALWAYS_ON_PROP3", - "CLK_BUFG_REBUF_X82Y38.GCLK16_ENABLE_BELOW", - "CLK_BUFG_REBUF_X82Y65.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT", - "CLK_BUFG_REBUF_X82Y65.GCLK16_ENABLE_ABOVE", - "CLK_BUFG_REBUF_X82Y65.GCLK16_ENABLE_BELOW", - "CLK_BUFG_REBUF_X82Y90.GCLK16_ENABLE_ABOVE", - "CLK_BUFG_TOP_R_X82Y53.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE", - "CLK_BUFG_TOP_R_X82Y53.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED", - "CLK_BUFG_TOP_R_X82Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0", - "CLK_BUFG_TOP_R_X82Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3", - "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O", - "CLK_HROW_TOP_R_X82Y78.BUFHCE.BUFHCE_X1Y0.IN_USE", - "CLK_HROW_TOP_R_X82Y78.BUFHCE.BUFHCE_X1Y0.ZINV_CE", - "CLK_HROW_TOP_R_X82Y78.CLK_HROW_CK_IN_R0_ACTIVE", - "CLK_HROW_TOP_R_X82Y78.CLK_HROW_CK_MUX_OUT_R0.CLK_HROW_R_CK_GCLK16", - "CLK_HROW_TOP_R_X82Y78.CLK_HROW_R_CK_GCLK16_ACTIVE", - "CLK_HROW_TOP_R_X82Y78.CLK_HROW_TOP_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0", - "HCLK_CMT_L_X119Y78.HCLK_CMT_CCIO0_ACTIVE", - "HCLK_CMT_L_X119Y78.HCLK_CMT_CCIO0_USED", - "HCLK_CMT_L_X119Y78.HCLK_CMT_CK_BUFHCLK0_USED", - "HCLK_CMT_L_X119Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0", - "INT_L_X30Y50.NE6BEG1.WW2END0", - "INT_L_X30Y53.ER1BEG1.SW2END0", - "INT_L_X30Y54.ER1BEG1.SW2END0", - "INT_L_X30Y57.ER1BEG1.SW6END0", - "INT_L_X30Y62.ER1BEG1.SW2END0", - "INT_L_X30Y67.SE6BEG1.LV_L9", - "INT_L_X30Y76.LV_L18.SW6END0", - "INT_L_X30Y88.NN6BEG0.NW6END0", - "INT_L_X30Y94.EE2BEG0.NN6END0", - "INT_R_X31Y50.EE2BEG0.LOGIC_OUTS18", - "INT_R_X31Y53.IMUX34.ER1END1", - "INT_R_X31Y53.WW2BEG1.SR1END1", - "INT_R_X31Y54.IMUX34.ER1END1", - "INT_R_X31Y54.SR1BEG1.NW6END1", - "INT_R_X31Y54.SW2BEG0.SS6END0", - "INT_R_X31Y55.SW2BEG0.SS6END0", - "INT_R_X31Y56.WW2BEG1.SL1END1", - "INT_R_X31Y57.SL1BEG1.ER1END1", - "INT_R_X31Y59.WW2BEG1.SS2END1", - "INT_R_X31Y60.SS6BEG0.SS6END0", - "INT_R_X31Y61.SE6BEG0.LOGIC_OUTS18", - "INT_R_X31Y61.SS2BEG1.SS6END1", - "INT_R_X31Y61.SS6BEG0.SS6END0", - "INT_R_X31Y62.IMUX34.ER1END1", - "INT_R_X31Y62.WW2BEG1.SL1END1", - "INT_R_X31Y63.SL1BEG1.SW6END1", - "INT_R_X31Y63.SW2BEG0.SS6END0", - "INT_R_X31Y66.SS6BEG0.SS6END0", - "INT_R_X31Y67.SS6BEG0.SS6END0", - "INT_R_X31Y67.SS6BEG1.LV9", - "INT_R_X31Y69.SS6BEG0.SS6END0", - "INT_R_X31Y72.SS6BEG0.SS6END0", - "INT_R_X31Y73.SS6BEG0.SS6END0", - "INT_R_X31Y75.NR1BEG0.LOGIC_OUTS18", - "INT_R_X31Y75.SS6BEG0.SS6END0", - "INT_R_X31Y76.LV18.NR1END0", - "INT_R_X31Y78.SS6BEG0.SS6END0", - "INT_R_X31Y79.SS6BEG0.SS6END0", - "INT_R_X31Y80.SE6BEG0.LOGIC_OUTS18", - "INT_R_X31Y81.SS6BEG0.EE2END0", - "INT_R_X31Y84.NE6BEG0.EE2END0", - "INT_R_X31Y84.SS6BEG0.SS6END0", - "INT_R_X31Y85.SS6BEG0.SS2END0", - "INT_R_X31Y87.SS2BEG0.EE2END0", - "INT_R_X31Y90.SS6BEG0.EE2END0", - "INT_R_X31Y93.BYP_ALT0.EE2END0", - "INT_R_X31Y93.IMUX34.BYP_BOUNCE0", - "INT_R_X31Y94.IMUX34.WW2END0", - "INT_R_X31Y96.NN2BEG0.EE2END0", - "INT_R_X31Y98.NN2BEG0.NN2END0", - "INT_R_X31Y99.IMUX34.SR1BEG_S0", - "INT_R_X31Y99.SR1BEG_S0.SS2END3", - "RIOB33_SING_X31Y50.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_SING_X31Y50.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY", - "RIOB33_SING_X31Y50.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_SING_X31Y50.IOB_Y0.PULLTYPE.NONE", - "RIOB33_SING_X31Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_SING_X31Y99.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_SING_X31Y99.IOB_Y1.PULLTYPE.NONE", - "RIOB33_X31Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X31Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY", - "RIOB33_X31Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X31Y43.IOB_Y0.PULLTYPE.PULLUP", - "RIOB33_X31Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X31Y43.IOB_Y1.PULLTYPE.PULLDOWN", - "RIOB33_X31Y53.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_X31Y53.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_X31Y53.IOB_Y0.PULLTYPE.NONE", - "RIOB33_X31Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_X31Y53.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_X31Y53.IOB_Y1.PULLTYPE.NONE", - "RIOB33_X31Y61.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_X31Y61.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_X31Y61.IOB_Y0.PULLTYPE.NONE", - "RIOB33_X31Y61.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X31Y61.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY", - "RIOB33_X31Y61.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X31Y61.IOB_Y1.PULLTYPE.NONE", - "RIOB33_X31Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X31Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY", - "RIOB33_X31Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X31Y75.IOB_Y0.PULLTYPE.NONE", - "RIOB33_X31Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X31Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY", - "RIOB33_X31Y75.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X31Y75.IOB_Y1.PULLTYPE.NONE", - "RIOB33_X31Y79.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X31Y79.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY", - "RIOB33_X31Y79.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN", - "RIOB33_X31Y79.IOB_Y0.PULLTYPE.NONE", - "RIOB33_X31Y79.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST", - "RIOB33_X31Y79.IOB_Y1.PULLTYPE.PULLDOWN", - "RIOB33_X31Y93.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_X31Y93.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_X31Y93.IOB_Y0.PULLTYPE.NONE", - "RIOB33_X31Y93.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW", - "RIOB33_X31Y93.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16", - "RIOB33_X31Y93.IOB_Y1.PULLTYPE.NONE", - "RIOI3_SING_X31Y50.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_SING_X31Y50.ILOGIC_Y0.ZINV_D", - "RIOI3_SING_X31Y99.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_SING_X31Y99.OLOGIC_Y1.OMUX.D1", - "RIOI3_SING_X31Y99.OLOGIC_Y1.OQUSED", - "RIOI3_SING_X31Y99.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_TBYTESRC_X31Y93.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_TBYTESRC_X31Y93.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y0.OMUX.D1", - "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y0.OQUSED", - "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y1.OMUX.D1", - "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y1.OQUSED", - "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_X31Y53.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X31Y53.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X31Y53.OLOGIC_Y0.OMUX.D1", - "RIOI3_X31Y53.OLOGIC_Y0.OQUSED", - "RIOI3_X31Y53.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_X31Y53.OLOGIC_Y1.OMUX.D1", - "RIOI3_X31Y53.OLOGIC_Y1.OQUSED", - "RIOI3_X31Y53.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_X31Y61.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X31Y61.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X31Y61.ILOGIC_Y1.ZINV_D", - "RIOI3_X31Y61.OLOGIC_Y0.OMUX.D1", - "RIOI3_X31Y61.OLOGIC_Y0.OQUSED", - "RIOI3_X31Y61.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF", - "RIOI3_X31Y75.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X31Y75.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X31Y75.ILOGIC_Y0.ZINV_D", - "RIOI3_X31Y75.ILOGIC_Y1.ZINV_D", - "RIOI3_X31Y79.IDELAY_Y0.IDELAY_TYPE_FIXED", - "RIOI3_X31Y79.IDELAY_Y1.IDELAY_TYPE_FIXED", - "RIOI3_X31Y79.ILOGIC_Y0.ZINV_D" - ] -} diff --git a/zynq7/harness/zybo/swbut/design.txt b/zynq7/harness/zybo/swbut/design.txt deleted file mode 100644 index 7366226..0000000 --- a/zynq7/harness/zybo/swbut/design.txt +++ /dev/null @@ -1,12 +0,0 @@ -name node pin wire -clk CLK_HROW_TOP_R_X82Y78/CLK_HROW_CK_BUFHCLK_R0 K17 HCLK_VBRK_X83Y78/HCLK_VBRK_CK_BUFHCLK0 -din[0] INT_R_X31Y53/WW2BEG1 J15 VBRK_X118Y56/VBRK_WW2END1 -din[1] INT_R_X31Y56/WW2BEG1 G15 VBRK_X118Y59/VBRK_WW2END1 -din[2] INT_R_X31Y59/WW2BEG1 K18 VBRK_X118Y62/VBRK_WW2END1 -din[3] INT_R_X31Y62/WW2BEG1 K19 VBRK_X118Y65/VBRK_WW2END1 -dout[0] INT_R_X29Y81/EE2BEG0 H15 VBRK_X118Y85/VBRK_EE2BEG0 -dout[1] INT_R_X29Y84/EE2BEG0 E17 VBRK_X118Y88/VBRK_EE2BEG0 -dout[2] INT_R_X29Y87/EE2BEG0 M14 VBRK_X118Y91/VBRK_EE2BEG0 -dout[3] INT_R_X29Y90/EE2BEG0 M15 VBRK_X118Y94/VBRK_EE2BEG0 -dout[4] INT_R_X29Y93/EE2BEG0 D18 VBRK_X118Y97/VBRK_EE2BEG0 -dout[5] INT_R_X29Y96/EE2BEG0 G14 VBRK_X118Y100/VBRK_EE2BEG0 diff --git a/zynq7/segbits_int_l.origin_info.db b/zynq7/segbits_int_l.origin_info.db index 91c522c..2324bd7 100644 --- a/zynq7/segbits_int_l.origin_info.db +++ b/zynq7/segbits_int_l.origin_info.db @@ -393,7 +393,7 @@ INT_L.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56 INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08 INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08 INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 -INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08 +INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 @@ -1937,7 +1937,7 @@ INT_L.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56 INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59 INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56 INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59 -INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59 +INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59 INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21 INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21 INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21 @@ -2273,7 +2273,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53 -INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52 +INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17 INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17 INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17 @@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00 -INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03 +INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03 @@ -3345,7 +3345,7 @@ INT_L.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63 INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60 INT_L.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63 INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61 -INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60 +INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60 INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60 INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61 INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60 @@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 04_34 06_32 INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32 INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33 INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35 -INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35 +INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35 INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35 INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32 INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33 diff --git a/zynq7/segbits_int_r.origin_info.db b/zynq7/segbits_int_r.origin_info.db index 4283207..e91f19b 100644 --- a/zynq7/segbits_int_r.origin_info.db +++ b/zynq7/segbits_int_r.origin_info.db @@ -329,7 +329,7 @@ INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56 INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08 INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08 INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 -INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08 +INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 @@ -705,7 +705,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40 INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43 INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40 INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43 -INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43 +INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43 INT_R.EE4BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_57 07_57 INT_R.EE4BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_57 04_58 INT_R.EE4BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_56 04_58 @@ -2273,7 +2273,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52 INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55 INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52 INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53 -INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52 +INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52 INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17 INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17 INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17 @@ -3623,7 +3623,7 @@ INT_R.WW4BEG3.LOGIC_OUTS21 origin:050-pip-seed 06_48 07_49 INT_R.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48 INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49 INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51 -INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51 +INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51 INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51 INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48 INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49 diff --git a/zynq7/segbits_liob33.db b/zynq7/segbits_liob33.db index cc77648..4d9f02a 100644 --- a/zynq7/segbits_liob33.db +++ b/zynq7/segbits_liob33.db @@ -5,43 +5,42 @@ LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 38_120 38_122 39_121 39_123 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 38_120 38_122 !39_121 39_123 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 38_120 !38_122 !39_121 39_123 LIOB33.IOB_Y0.INTERMDISABLE.I 39_89 -LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 38_118 39_65 39_75 39_97 !39_101 39_113 39_119 39_125 -LIOB33.IOB_Y0.LVDS_25.IN 38_86 39_87 -LIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 39_65 39_75 !39_101 -LIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_112 !38_118 38_126 39_65 39_117 39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 !38_112 38_118 !38_126 39_65 39_75 39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 !38_110 !38_112 !38_126 39_65 39_75 !39_101 !39_105 !39_109 !39_117 !39_127 +LIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 +LIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_117 39_119 !39_125 !39_127 LIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93 -LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_118 39_65 !39_75 !39_97 39_101 39_113 39_119 39_125 -LIOB33.IOB_Y0.TMDS_33.IN 38_86 !39_87 -LIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 39_65 !39_75 39_101 +LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 39_101 39_113 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.TMDS_33.IN_DIFF 38_86 !39_85 !39_87 +LIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 !38_110 !38_112 !38_126 39_65 !39_75 39_101 !39_105 !39_109 !39_117 !39_127 LIOB33.IOB_Y0.ZIBUF_LOW_PWR 38_84 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 38_112 38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_86 39_85 !39_87 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 39_95 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 39_119 !39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 -LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 39_127 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 38_112 !38_118 38_126 39_65 39_113 39_117 39_119 !39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 !39_127 LIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN 38_86 39_85 39_87 -LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_112 38_118 !38_126 39_65 39_117 !39_119 !39_125 39_127 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127 -LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_117 !39_119 !39_125 39_127 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 39_119 39_125 !39_127 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 39_127 LIOB33.IOB_Y0.SSTL135_SSTL15.IN !38_86 !39_85 39_87 -LIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 LIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST !38_106 38_110 39_105 39_107 39_109 39_111 LIOB33.IOB_Y1.IBUFDISABLE.I 39_45 LIOB33.IOB_Y1.IN_TERM.NONE !38_04 !38_06 !39_05 !39_07 @@ -59,7 +58,7 @@ LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_ LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_33 !39_63 +LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32 LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63 @@ -77,7 +76,6 @@ LIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 38_00 !38_02 !38_08 38_10 38_62 !39_01 39_09 !3 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 38_00 38_02 !38_08 !38_10 38_62 !39_01 39_09 !39_15 39_63 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 -LIOB33.IOB_Y1.SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 39_33 !39_63 LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41 LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 diff --git a/zynq7/segbits_liob33.origin_info.db b/zynq7/segbits_liob33.origin_info.db index b3b6685..022593c 100644 --- a/zynq7/segbits_liob33.origin_info.db +++ b/zynq7/segbits_liob33.origin_info.db @@ -5,43 +5,42 @@ LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_120 38_122 39_121 39_12 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !39_121 38_120 38_122 39_123 LIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_122 !39_121 38_120 39_123 LIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89 -LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !39_101 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 -LIOB33.IOB_Y0.LVDS_25.IN origin:030-iob 38_86 39_87 -LIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !39_101 38_102 38_64 38_74 38_76 38_98 39_65 39_75 -LIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_112 !38_118 !39_125 !39_127 38_126 38_64 39_117 39_119 39_65 +LIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !38_112 !38_126 !39_101 !39_117 !39_127 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 +LIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !38_110 !38_112 !38_126 !39_101 !39_105 !39_109 !39_117 !39_127 38_102 38_64 38_74 38_76 38_98 39_65 39_75 +LIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 +LIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_126 38_64 39_117 39_119 39_65 LIOB33.IOB_Y0.PULLTYPE.KEEPER origin:030-iob !39_93 38_92 38_94 LIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94 LIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93 LIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93 -LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 -LIOB33.IOB_Y0.TMDS_33.IN origin:030-iob !39_87 38_86 -LIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_74 !38_76 !38_98 !39_75 38_64 39_101 39_65 +LIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_117 !39_127 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 +LIOB33.IOB_Y0.TMDS_33.IN_DIFF origin:030-iob !39_85 !39_87 38_86 +LIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_110 !38_112 !38_126 !38_74 !38_76 !38_98 !39_105 !39_109 !39_117 !39_127 !39_75 38_64 39_101 39_65 LIOB33.IOB_Y0.ZIBUF_LOW_PWR origin:030-iob 38_84 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 38_112 38_118 38_126 38_64 39_113 39_125 39_65 -LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 38_112 38_126 38_64 39_113 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_125 39_65 +LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_126 38_64 39_113 39_127 39_65 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !39_87 38_86 39_85 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109 LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 39_95 -LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 38_112 38_64 39_113 39_119 39_65 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 38_112 38_64 39_113 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_113 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !39_119 !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_118 !39_117 !39_127 38_112 38_126 38_64 39_113 39_119 39_125 39_65 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_118 !39_117 !39_119 38_112 38_126 38_64 39_113 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_118 !39_125 !39_127 38_112 38_126 38_64 39_113 39_117 39_119 39_65 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 !39_127 38_112 38_64 39_113 39_65 -LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !39_119 !39_125 !39_127 38_112 38_118 38_126 38_64 39_113 39_117 39_65 +LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_119 39_65 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_64 39_113 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_118 38_64 39_113 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_65 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_126 38_64 39_113 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_117 39_119 39_65 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_65 +LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_65 LIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_86 39_85 39_87 -LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_112 !38_126 !39_119 !39_125 38_118 38_64 39_117 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_112 !38_126 !39_117 !39_119 38_118 38_64 39_125 39_127 39_65 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_112 !38_118 !39_117 !39_127 38_126 38_64 39_119 39_125 39_65 -LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_112 !38_118 !39_117 !39_119 38_126 38_64 39_125 39_127 39_65 -LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_118 38_64 39_117 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_118 38_64 39_125 39_127 39_65 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_126 38_64 39_119 39_125 39_65 +LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_126 38_64 39_125 39_127 39_65 +LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 LIOB33.IOB_Y0.SSTL135_SSTL15.IN origin:030-iob !38_86 !39_85 39_87 -LIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 LIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111 LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 LIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07 @@ -59,7 +58,7 @@ LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_33 !39_63 38_02 38_08 38_14 39_09 +LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21 LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32 LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63 @@ -77,7 +76,6 @@ LIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 origin:030-iob !38_02 !38_08 !39_01 !39_15 38_0 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_08 !38_10 !39_01 !39_15 38_00 38_02 38_62 39_09 39_63 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !39_15 38_02 38_08 38_62 39_01 39_63 LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63 -LIOB33.IOB_Y1.SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 39_33 LIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40 LIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41 diff --git a/zynq7/segbits_riob33.db b/zynq7/segbits_riob33.db index 0e355eb..a4b4403 100644 --- a/zynq7/segbits_riob33.db +++ b/zynq7/segbits_riob33.db @@ -5,43 +5,42 @@ RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 38_120 38_122 39_121 39_123 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 38_120 38_122 !39_121 39_123 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 38_120 !38_122 !39_121 39_123 RIOB33.IOB_Y0.INTERMDISABLE.I 39_89 -RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 38_118 39_65 39_75 39_97 !39_101 39_113 39_119 39_125 -RIOB33.IOB_Y0.LVDS_25.IN 38_86 39_87 -RIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 39_65 39_75 !39_101 -RIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_112 !38_118 38_126 39_65 39_117 39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED 38_64 38_74 38_76 38_98 38_100 38_102 !38_112 38_118 !38_126 39_65 39_75 39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVDS_25.OUT 38_64 38_74 38_76 38_98 38_102 !38_110 !38_112 !38_126 39_65 39_75 !39_101 !39_105 !39_109 !39_117 !39_127 +RIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 +RIOB33.IOB_Y0.LVTTL.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_117 39_119 !39_125 !39_127 RIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93 -RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_118 39_65 !39_75 !39_97 39_101 39_113 39_119 39_125 -RIOB33.IOB_Y0.TMDS_33.IN 38_86 !39_87 -RIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 39_65 !39_75 39_101 +RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 39_101 39_113 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.TMDS_33.IN_DIFF 38_86 !39_85 !39_87 +RIOB33.IOB_Y0.TMDS_33.OUT 38_64 !38_74 !38_76 !38_98 !38_102 !38_110 !38_112 !38_126 39_65 !39_75 39_101 !39_105 !39_109 !39_117 !39_127 RIOB33.IOB_Y0.ZIBUF_LOW_PWR 38_84 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 38_112 38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_86 39_85 !39_87 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 39_95 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 39_119 !39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127 -RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 39_127 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 38_112 !38_118 38_126 39_65 39_113 39_117 39_119 !39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 !39_127 RIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN 38_86 39_85 39_87 -RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_112 38_118 !38_126 39_65 39_117 !39_119 !39_125 39_127 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127 -RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_117 !39_119 !39_125 39_127 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 39_119 39_125 !39_127 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 !39_117 !39_119 39_125 39_127 +RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 39_127 RIOB33.IOB_Y0.SSTL135_SSTL15.IN !38_86 !39_85 39_87 -RIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF 38_86 !39_85 39_87 RIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST !38_106 38_110 39_105 39_107 39_109 39_111 RIOB33.IOB_Y1.IBUFDISABLE.I 39_45 RIOB33.IOB_Y1.IN_TERM.NONE !38_04 !38_06 !39_05 !39_07 @@ -59,7 +58,7 @@ RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_ RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_33 !39_63 +RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32 RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63 @@ -77,7 +76,6 @@ RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 38_00 !38_02 !38_08 38_10 38_62 !39_01 39_09 !3 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 38_00 38_02 !38_08 !38_10 38_62 !39_01 39_09 !39_15 39_63 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 !38_00 38_02 38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 38_00 38_02 !38_08 !38_10 38_62 39_01 !39_09 !39_15 39_63 -RIOB33.IOB_Y1.SSTL15.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 39_33 !39_63 RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED 38_00 !38_02 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.SSTL135_SSTL15.IN 38_40 !38_42 !39_41 RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF 38_40 !38_42 39_41 diff --git a/zynq7/segbits_riob33.origin_info.db b/zynq7/segbits_riob33.origin_info.db index ca4fd48..95c9159 100644 --- a/zynq7/segbits_riob33.origin_info.db +++ b/zynq7/segbits_riob33.origin_info.db @@ -5,43 +5,42 @@ RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_120 38_122 39_121 39_12 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !39_121 38_120 38_122 39_123 RIOB33.IOB_Y0.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_122 !39_121 38_120 39_123 RIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89 -RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !39_101 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 -RIOB33.IOB_Y0.LVDS_25.IN origin:030-iob 38_86 39_87 -RIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !39_101 38_102 38_64 38_74 38_76 38_98 39_65 39_75 -RIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_112 !38_118 !39_125 !39_127 38_126 38_64 39_117 39_119 39_65 +RIOB33.IOB_Y0.LVDS_25.DRIVE.I_FIXED origin:030-iob !38_112 !38_126 !39_101 !39_117 !39_127 38_100 38_102 38_118 38_64 38_74 38_76 38_98 39_113 39_119 39_125 39_65 39_75 39_97 +RIOB33.IOB_Y0.LVDS_25.OUT origin:030-iob !38_110 !38_112 !38_126 !39_101 !39_105 !39_109 !39_117 !39_127 38_102 38_64 38_74 38_76 38_98 39_65 39_75 +RIOB33.IOB_Y0.LVDS_25_SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 +RIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_126 38_64 39_117 39_119 39_65 RIOB33.IOB_Y0.PULLTYPE.KEEPER origin:030-iob !39_93 38_92 38_94 RIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94 RIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93 RIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93 -RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 -RIOB33.IOB_Y0.TMDS_33.IN origin:030-iob !39_87 38_86 -RIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_74 !38_76 !38_98 !39_75 38_64 39_101 39_65 +RIOB33.IOB_Y0.TMDS_33.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_117 !39_127 !39_75 !39_97 38_118 38_64 39_101 39_113 39_119 39_125 39_65 +RIOB33.IOB_Y0.TMDS_33.IN_DIFF origin:030-iob !39_85 !39_87 38_86 +RIOB33.IOB_Y0.TMDS_33.OUT origin:030-iob !38_102 !38_110 !38_112 !38_126 !38_74 !38_76 !38_98 !39_105 !39_109 !39_117 !39_127 !39_75 38_64 39_101 39_65 RIOB33.IOB_Y0.ZIBUF_LOW_PWR origin:030-iob 38_84 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 38_112 38_118 38_126 38_64 39_113 39_125 39_65 -RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 38_112 38_126 38_64 39_113 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_125 39_65 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_126 38_64 39_113 39_127 39_65 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !39_87 38_86 39_85 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_107 !39_109 !39_111 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109 RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 39_95 -RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 38_112 38_64 39_113 39_119 39_65 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 38_112 38_64 39_113 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_113 39_125 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !39_119 !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_118 !39_117 !39_127 38_112 38_126 38_64 39_113 39_119 39_125 39_65 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_118 !39_117 !39_119 38_112 38_126 38_64 39_113 39_125 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_118 !39_125 !39_127 38_112 38_126 38_64 39_113 39_117 39_119 39_65 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 !39_127 38_112 38_64 39_113 39_65 -RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !39_119 !39_125 !39_127 38_112 38_118 38_126 38_64 39_113 39_117 39_65 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_119 39_65 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_64 39_113 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_118 38_64 39_113 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS15_SSTL15.DRIVE.I16_I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_65 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_126 38_64 39_113 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_117 39_119 39_65 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_65 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_65 RIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_86 39_85 39_87 -RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_112 !38_126 !39_119 !39_125 38_118 38_64 39_117 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_112 !38_126 !39_117 !39_119 38_118 38_64 39_125 39_127 39_65 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_112 !38_118 !39_117 !39_127 38_126 38_64 39_119 39_125 39_65 -RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_112 !38_118 !39_117 !39_119 38_126 38_64 39_125 39_127 39_65 -RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_75 !39_97 38_118 38_64 39_117 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_118 38_64 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_126 38_64 39_119 39_125 39_65 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_100 !38_102 !38_112 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_126 38_64 39_125 39_127 39_65 +RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_125 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65 RIOB33.IOB_Y0.SSTL135_SSTL15.IN origin:030-iob !38_86 !39_85 39_87 -RIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87 RIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111 RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 RIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07 @@ -59,7 +58,7 @@ RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21 -RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_33 !39_63 38_02 38_08 38_14 39_09 +RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32 RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63 @@ -77,7 +76,6 @@ RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 origin:030-iob !38_02 !38_08 !39_01 !39_15 38_0 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_08 !38_10 !39_01 !39_15 38_00 38_02 38_62 39_09 39_63 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 !39_15 38_02 38_08 38_62 39_01 39_63 RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !39_09 !39_15 38_00 38_02 38_62 39_01 39_63 -RIOB33.IOB_Y1.SSTL15.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09 39_33 RIOB33.IOB_Y1.SSTL135.DRIVE.I_FIXED origin:030-iob !38_02 38_00 38_08 38_10 38_14 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.SSTL135_SSTL15.IN origin:030-iob !38_42 !39_41 38_40 RIOB33.IOB_Y1.SSTL135_SSTL15.IN_DIFF origin:030-iob !38_42 38_40 39_41