diff --git a/Info.md b/Info.md index 80ee1bf..8f186bb 100644 --- a/Info.md +++ b/Info.md @@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING). # Details -Last updated on Mon 11 May 2020 11:45:04 PM UTC (2020-05-11T23:45:04+00:00). +Last updated on Mon 11 May 2020 11:47:34 PM UTC (2020-05-11T23:47:34+00:00). Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [7ddd5f88](https://github.com/SymbiFlow/prjxray/commit/7ddd5f88e60c9876a6d7171b343c1c855239dc85). @@ -504,6 +504,16 @@ Results have checksums; * [`626d9e188a1c4874f7ac657e82c64df8d52f819624e8ee4f9ed9e557d85ad3f2 ./artix7/timings/carry4_slicem.sdf`](./artix7/timings/carry4_slicem.sdf) * [`fd31d66077f869d01f13d9fabbd0dcd38b4aab0322179ecf9ac190a3b70c5456 ./artix7/timings/slicel.sdf`](./artix7/timings/slicel.sdf) * [`3d2da5714d8c81165fa51403fb719b3ddd9e7ea7ab79280ae4e157d11a29172e ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf) + * [`3f202fefbd0f36761f08eb58737a42754c65c965968174421df0374198e31daa ./artix7/xc7a100tcsg324-1/package_pins.csv`](./artix7/xc7a100tcsg324-1/package_pins.csv) + * [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02 ./artix7/xc7a100tcsg324-1/part.json`](./artix7/xc7a100tcsg324-1/part.json) + * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tcsg324-1/part.yaml`](./artix7/xc7a100tcsg324-1/part.yaml) + * [`9cf701615e6f9ed6e89d86738f10ebb9d5bf1a233f1e3251315b2f9159f73391 ./artix7/xc7a100tcsg324-1/tileconn.json`](./artix7/xc7a100tcsg324-1/tileconn.json) + * [`58d35b8327cb31c6db0333149f48a833956d9e03738ff31a8e47aa426fbe545f ./artix7/xc7a100tcsg324-1/tilegrid.json`](./artix7/xc7a100tcsg324-1/tilegrid.json) + * [`bf25d62e58330960eb582f0b3b99196bd59df046db0d7de5330634b64cd397ad ./artix7/xc7a100tfgg676-1/package_pins.csv`](./artix7/xc7a100tfgg676-1/package_pins.csv) + * [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb ./artix7/xc7a100tfgg676-1/part.json`](./artix7/xc7a100tfgg676-1/part.json) + * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg676-1/part.yaml`](./artix7/xc7a100tfgg676-1/part.yaml) + * [`9cf701615e6f9ed6e89d86738f10ebb9d5bf1a233f1e3251315b2f9159f73391 ./artix7/xc7a100tfgg676-1/tileconn.json`](./artix7/xc7a100tfgg676-1/tileconn.json) + * [`58d35b8327cb31c6db0333149f48a833956d9e03738ff31a8e47aa426fbe545f ./artix7/xc7a100tfgg676-1/tilegrid.json`](./artix7/xc7a100tfgg676-1/tilegrid.json) * [`72dd638f5c8f6c36e74765915c01b2fa28e3c28b2c0afd91871ab7b0490a14f3 ./artix7/xc7a200tffg1156-1/package_pins.csv`](./artix7/xc7a200tffg1156-1/package_pins.csv) * [`fe44ca57c10c7b804357ded2cdea392c008b7b4d5a82ad917fa3148a756e4e42 ./artix7/xc7a200tffg1156-1/part.json`](./artix7/xc7a200tffg1156-1/part.json) * [`a3d493aef436b9978b2ed1c98c4e1364ab9eb096f824e19acd7cce3f7d920e97 ./artix7/xc7a200tffg1156-1/part.yaml`](./artix7/xc7a200tffg1156-1/part.yaml) diff --git a/artix7/xc7a100tcsg324-1/package_pins.csv b/artix7/xc7a100tcsg324-1/package_pins.csv new file mode 100644 index 0000000..2057141 --- /dev/null +++ b/artix7/xc7a100tcsg324-1/package_pins.csv @@ -0,0 +1,213 @@ +pin,bank,site,tile,pin_function +A1,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35 +A3,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35 +A4,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35 +A5,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35 +A6,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35 +A8,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16 +A9,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16 +A10,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16 +A11,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_15 +A13,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15 +A14,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15 +A15,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD10P_15 +A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD10N_15 +A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD11N_15 +B1,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35 +B2,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35 +B3,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35 +B4,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35 +B6,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35 +B7,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35 +B8,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16 +B9,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16 +B11,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15 +B12,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15 +B13,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15 +B14,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15 +B16,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15 +B17,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15 +B18,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15 +C1,35,IOB_X1Y117,RIOB33_X57Y117,IO_L16N_T2_35 +C2,35,IOB_X1Y118,RIOB33_X57Y117,IO_L16P_T2_35 +C4,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35 +C5,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35 +C6,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35 +C7,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35 +C9,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16 +C10,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16 +C11,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16 +C12,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15 +C14,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15 +C15,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15 +C16,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15 +C17,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15 +D2,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35 +D3,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35 +D4,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35 +D5,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35 +D7,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35 +D8,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35 +D9,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16 +D10,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16 +D12,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15 +D13,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15 +D14,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15 +D15,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_15 +D17,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15 +D18,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15 +E1,35,IOB_X1Y113,RIOB33_X57Y113,IO_L18N_T2_35 +E2,35,IOB_X1Y122,RIOB33_X57Y121,IO_L14P_T2_SRCC_35 +E3,35,IOB_X1Y126,RIOB33_X57Y125,IO_L12P_T1_MRCC_35 +E5,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35 +E6,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35 +E7,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35 +E15,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_15 +E16,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_15 +E17,15,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_A28_15 +E18,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15 +F1,35,IOB_X1Y114,RIOB33_X57Y113,IO_L18P_T2_35 +F3,35,IOB_X1Y123,RIOB33_X57Y123,IO_L13N_T2_MRCC_35 +F4,35,IOB_X1Y124,RIOB33_X57Y123,IO_L13P_T2_MRCC_35 +F5,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35 +F6,35,IOB_X1Y111,RIOB33_X57Y111,IO_L19N_T3_VREF_35 +F13,15,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_AD9P_15 +F14,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD9N_15 +F15,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15 +F16,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15 +F18,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15 +G1,35,IOB_X1Y115,RIOB33_X57Y115,IO_L17N_T2_35 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new file mode 100644 index 0000000..44833bb --- /dev/null +++ b/artix7/xc7a100tcsg324-1/part.yaml @@ -0,0 +1,499 @@ +! +idcode: 0x3631093 +global_clock_regions: + top: ! + rows: + 0: ! + configuration_buses: + CLB_IO_CLK: ! + configuration_columns: + 0: ! + frame_count: 42 + 1: ! + frame_count: 30 + 2: ! + frame_count: 36 + 3: ! + frame_count: 36 + 4: ! + frame_count: 36 + 5: ! + frame_count: 36 + 6: ! + frame_count: 28 + 7: ! + frame_count: 36 + 8: ! + frame_count: 36 + 9: ! + frame_count: 28 + 10: ! + frame_count: 36 + 11: ! + frame_count: 36 + 12: ! + frame_count: 36 + 13: ! + frame_count: 36 + 14: ! + frame_count: 36 + 15: ! + frame_count: 36 + 16: ! + frame_count: 36 + 17: ! + frame_count: 36 + 18: ! + frame_count: 30 + 19: ! + frame_count: 36 + 20: ! + frame_count: 36 + 21: ! + frame_count: 36 + 22: ! + frame_count: 36 + 23: ! + frame_count: 36 + 24: ! + frame_count: 36 + 25: ! + frame_count: 36 + 26: ! + frame_count: 36 + 27: ! + frame_count: 36 + 28: ! + frame_count: 36 + 29: ! + frame_count: 36 + 30: ! + frame_count: 36 + 31: ! + frame_count: 30 + 32: ! + frame_count: 36 + 33: ! + frame_count: 36 + 34: ! + frame_count: 36 + 35: ! + frame_count: 28 + 36: ! + frame_count: 36 + 37: ! + frame_count: 36 + 38: ! + frame_count: 28 + 39: ! + frame_count: 36 + 40: ! + frame_count: 36 + 41: ! + frame_count: 36 + 42: ! + frame_count: 36 + 43: ! + frame_count: 36 + 44: ! + frame_count: 28 + 45: ! + frame_count: 36 + 46: ! + frame_count: 36 + 47: ! + frame_count: 36 + 48: ! + frame_count: 28 + 49: ! + frame_count: 36 + 50: ! + frame_count: 36 + 51: ! + frame_count: 28 + 52: ! + frame_count: 36 + 53: ! + frame_count: 36 + 54: ! + frame_count: 36 + 55: ! + frame_count: 36 + 56: ! + frame_count: 30 + 57: ! + frame_count: 42 + BLOCK_RAM: ! + configuration_columns: + 0: ! + frame_count: 128 + 1: ! + frame_count: 128 + 2: ! + frame_count: 128 + 3: ! + frame_count: 128 + 1: ! + configuration_buses: + CLB_IO_CLK: ! + configuration_columns: + 0: ! + frame_count: 42 + 1: ! + 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"wire_pairs": [ + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_CLB" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CLB_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CLB_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CLB_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CLB_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CLB_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CLB_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CLB_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CLB_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CLB_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CLB_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CLB_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CLB_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CLB_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CLB_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CLB_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CLB_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CLB_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CLB_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CLB_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CLB_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CLB_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CLB_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CLB_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CLB_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CLB_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CLB_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CLB_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CLB_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CLB_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CLB_CK_IN13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_CLB_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_CLB_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_CLB_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_CLB_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L_BOT_UTURN" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_R" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_R_BOT_UTURN" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VFRAME" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VFRAME_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VFRAME_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_FIFO_L" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_CLK_0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_MUX_CLK_1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_MUX_CLK_2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_MUX_CLK_3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_MUX_CLK_4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_MUX_CLK_5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_MUX_CLK_6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_MUX_CLK_7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_MUX_CLK_8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_MUX_CLK_9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_MUX_CLK_10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_MUX_CLK_11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_MUX_CLK_12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_MUX_CLK_13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_FIFO_L" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_FEEDTHRU_1" + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_1_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_1_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_1_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_1_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_1_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_1_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_1_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_1_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_1_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_1_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_FEEDTHRU_1_CK_BUFHCLK10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_FEEDTHRU_1_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_FEEDTHRU_1_CK_BUFRCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_FEEDTHRU_1_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + "HCLK_FEEDTHRU_1_CK_BUFRCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK3", + "HCLK_FEEDTHRU_1_CK_BUFRCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN0", + "HCLK_FEEDTHRU_1_CK_IN0" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN1", + "HCLK_FEEDTHRU_1_CK_IN1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN2", + "HCLK_FEEDTHRU_1_CK_IN2" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN3", + "HCLK_FEEDTHRU_1_CK_IN3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN4", + "HCLK_FEEDTHRU_1_CK_IN4" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN5", + "HCLK_FEEDTHRU_1_CK_IN5" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN6", + "HCLK_FEEDTHRU_1_CK_IN6" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN7", + "HCLK_FEEDTHRU_1_CK_IN7" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN8", + "HCLK_FEEDTHRU_1_CK_IN8" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN9", + "HCLK_FEEDTHRU_1_CK_IN9" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN10", + "HCLK_FEEDTHRU_1_CK_IN10" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN11", + "HCLK_FEEDTHRU_1_CK_IN11" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN12", + "HCLK_FEEDTHRU_1_CK_IN12" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN13", + "HCLK_FEEDTHRU_1_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_FEEDTHRU_2" + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_2_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_2_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_2_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_2_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_2_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_2_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_2_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_2_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_2_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_FEEDTHRU_2_CK_BUFHCLK10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_FEEDTHRU_2_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_FEEDTHRU_2_CK_BUFRCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_FEEDTHRU_2_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + 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"HCLK_INT_INTERFACE_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + 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"HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_CK_IN6" + ], + [ + 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"HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_VFRAME" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_INT_INTERFACE_CK_IN7", + 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"HCLK_IOI_CK_BUFHCLK7" + ], + [ + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOI_CK_BUFHCLK8" + ], + [ + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOI_CK_BUFHCLK9" + ], + [ + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOI_CK_BUFHCLK10" + ], + [ + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOI_CK_BUFHCLK11" + ], + [ + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOI_CK_BUFRCLK0" + ], + [ + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFRCLK1" + ], + [ + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOI_CK_BUFRCLK2" + ], + [ + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOI_CK_BUFRCLK3" + ], + [ + "HCLK_IOB_PERFCLK0", + "HCLK_IOI_IOCLK_PLL0" + ], + [ + "HCLK_IOB_PERFCLK1", + "HCLK_IOI_IOCLK_PLL1" + ], + [ + "HCLK_IOB_PERFCLK2", + "HCLK_IOI_IOCLK_PLL2" + ], + [ + "HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_IOB", + "HCLK_IOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOI_CK_BUFHCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOI_CK_BUFHCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK2", 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"HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_IOI3", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_IOI3", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "HCLK_IOI3", + "LIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_TOP0", + "LIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "LIOI_I2GCLK_TOP1" + ], + [ + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" + ], + [ + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" + ], + [ + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" + ], + [ + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" + ], + [ + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" + ], + [ + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" + ], + [ + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" + ], + [ + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ] + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "tile_types": [ + "HCLK_IOI3", + "LIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_BOT0", + "LIOI_I2GCLK_BOT1" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "LIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ], + [ + "HCLK_IOI_IDELAYCTRL_RDY", + "IOI_IDELAYCTRL_RDY" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX2", + "IOI_IMUX_RC2" + ], + [ + "HCLK_IOI_RCLK_IMUX3", + "IOI_IMUX_RC3" + ], + [ + "HCLK_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2" + ], + [ + "HCLK_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3" + ], + [ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "HCLK_IOI3", + "RIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_TOP0", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "RIOI_I2GCLK_TOP1" + ], + [ + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" + ], + [ + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" + ], + [ + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" + ], + [ + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" + ], + [ + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" + ], + [ + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" + ], + [ + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" + ], + [ + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ] + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "tile_types": [ + "HCLK_IOI3", + "RIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_BOT0", + "RIOI_I2GCLK_BOT1" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ], 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[ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_L", + "HCLK_R" + ], + "wire_pairs": [ + [ + "HCLK_CCIO0", + "HCLK_CCIO0" + ], + [ + "HCLK_CCIO1", + "HCLK_CCIO1" + ], + [ + "HCLK_CCIO2", + "HCLK_CCIO2" + ], + [ + "HCLK_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" 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}, + "44": { + "frame_count": 28 + }, + "45": { + "frame_count": 36 + }, + "46": { + "frame_count": 36 + }, + "47": { + "frame_count": 36 + }, + "48": { + "frame_count": 28 + }, + "49": { + "frame_count": 36 + }, + "50": { + "frame_count": 36 + }, + "51": { + "frame_count": 32 + } + } + } + } + } + } + } + }, + "idcode": 56823955, + "iobanks": { + "0": "X1Y130", + "13": "X1Y26", + "14": "X1Y78", + "15": "X1Y130", + "16": "X1Y182", + "34": "X146Y78", + "35": "X146Y130" + } +} diff --git a/artix7/xc7a100tfgg676-1/part.yaml b/artix7/xc7a100tfgg676-1/part.yaml new file mode 100644 index 0000000..44833bb --- /dev/null +++ b/artix7/xc7a100tfgg676-1/part.yaml @@ -0,0 +1,499 @@ +! +idcode: 0x3631093 +global_clock_regions: + top: ! + rows: + 0: ! + configuration_buses: + CLB_IO_CLK: ! + configuration_columns: + 0: ! + frame_count: 42 + 1: ! + frame_count: 30 + 2: ! + frame_count: 36 + 3: ! + frame_count: 36 + 4: ! + frame_count: 36 + 5: ! + frame_count: 36 + 6: ! + frame_count: 28 + 7: ! + frame_count: 36 + 8: ! + frame_count: 36 + 9: ! + frame_count: 28 + 10: ! + frame_count: 36 + 11: ! + frame_count: 36 + 12: ! + frame_count: 36 + 13: ! + frame_count: 36 + 14: ! + frame_count: 36 + 15: ! + frame_count: 36 + 16: ! + frame_count: 36 + 17: ! + frame_count: 36 + 18: ! + frame_count: 30 + 19: ! + frame_count: 36 + 20: ! + frame_count: 36 + 21: ! + frame_count: 36 + 22: ! + frame_count: 36 + 23: ! + frame_count: 36 + 24: ! + frame_count: 36 + 25: ! + frame_count: 36 + 26: ! + frame_count: 36 + 27: ! + frame_count: 36 + 28: ! + frame_count: 36 + 29: ! + frame_count: 36 + 30: ! + frame_count: 36 + 31: ! + frame_count: 30 + 32: ! + frame_count: 36 + 33: ! + frame_count: 36 + 34: ! + frame_count: 36 + 35: ! + frame_count: 28 + 36: ! + frame_count: 36 + 37: ! + frame_count: 36 + 38: ! + frame_count: 28 + 39: ! + frame_count: 36 + 40: ! + frame_count: 36 + 41: ! + frame_count: 36 + 42: ! + frame_count: 36 + 43: ! + frame_count: 36 + 44: ! + frame_count: 28 + 45: ! + frame_count: 36 + 46: ! + frame_count: 36 + 47: ! + frame_count: 36 + 48: ! + frame_count: 28 + 49: ! + frame_count: 36 + 50: ! + frame_count: 36 + 51: ! + frame_count: 28 + 52: ! + frame_count: 36 + 53: ! + frame_count: 36 + 54: ! + frame_count: 36 + 55: ! + frame_count: 36 + 56: ! + frame_count: 30 + 57: ! + frame_count: 42 + BLOCK_RAM: ! + configuration_columns: + 0: ! + frame_count: 128 + 1: ! + frame_count: 128 + 2: ! + frame_count: 128 + 3: ! + frame_count: 128 + 1: ! + configuration_buses: + CLB_IO_CLK: ! + configuration_columns: + 0: ! + frame_count: 42 + 1: ! + frame_count: 30 + 2: ! + frame_count: 36 + 3: ! + frame_count: 36 + 4: ! + frame_count: 36 + 5: ! + frame_count: 36 + 6: ! + frame_count: 28 + 7: ! + frame_count: 36 + 8: ! + frame_count: 36 + 9: ! + frame_count: 28 + 10: ! + frame_count: 36 + 11: ! + frame_count: 36 + 12: ! + frame_count: 36 + 13: ! + frame_count: 36 + 14: ! + frame_count: 36 + 15: ! + frame_count: 36 + 16: ! + frame_count: 36 + 17: ! + frame_count: 36 + 18: ! + frame_count: 30 + 19: ! + frame_count: 36 + 20: ! + frame_count: 36 + 21: ! + frame_count: 36 + 22: ! + frame_count: 36 + 23: ! + frame_count: 36 + 24: ! + frame_count: 36 + 25: ! + frame_count: 36 + 26: ! + frame_count: 36 + 27: ! + frame_count: 36 + 28: ! + frame_count: 36 + 29: ! + frame_count: 36 + 30: ! + frame_count: 36 + 31: ! + frame_count: 30 + 32: ! + frame_count: 36 + 33: ! + frame_count: 36 + 34: ! + frame_count: 36 + 35: ! + frame_count: 28 + 36: ! + frame_count: 36 + 37: ! + frame_count: 36 + 38: ! + frame_count: 28 + 39: ! + frame_count: 36 + 40: ! + frame_count: 36 + 41: ! + frame_count: 36 + 42: ! + frame_count: 36 + 43: ! + frame_count: 36 + 44: ! + frame_count: 28 + 45: ! + frame_count: 36 + 46: ! + frame_count: 36 + 47: ! + frame_count: 36 + 48: ! + frame_count: 28 + 49: ! + frame_count: 36 + 50: ! + frame_count: 36 + 51: ! + frame_count: 32 + BLOCK_RAM: ! + configuration_columns: + 0: ! + frame_count: 128 + 1: ! + frame_count: 128 + 2: ! + frame_count: 128 + bottom: ! + rows: + 0: ! + configuration_buses: + CLB_IO_CLK: ! + configuration_columns: + 0: ! + frame_count: 42 + 1: ! + frame_count: 30 + 2: ! + frame_count: 36 + 3: ! + frame_count: 36 + 4: ! + frame_count: 36 + 5: ! + frame_count: 36 + 6: ! + frame_count: 28 + 7: ! + frame_count: 36 + 8: ! + frame_count: 36 + 9: ! + frame_count: 28 + 10: ! + frame_count: 36 + 11: ! + frame_count: 36 + 12: ! + frame_count: 36 + 13: ! + frame_count: 36 + 14: ! + frame_count: 36 + 15: ! + frame_count: 36 + 16: ! + frame_count: 36 + 17: ! + frame_count: 36 + 18: ! + frame_count: 30 + 19: ! + frame_count: 36 + 20: ! + frame_count: 36 + 21: ! + frame_count: 36 + 22: ! + frame_count: 36 + 23: ! + frame_count: 36 + 24: ! + frame_count: 36 + 25: ! + frame_count: 36 + 26: ! + frame_count: 36 + 27: ! + frame_count: 36 + 28: ! + frame_count: 36 + 29: ! + frame_count: 36 + 30: ! + frame_count: 36 + 31: ! + frame_count: 30 + 32: ! + frame_count: 36 + 33: ! + frame_count: 36 + 34: ! + frame_count: 36 + 35: ! + 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"BRAM_WR1END3_0", + "CLBLM_WR1END3" + ], + [ + "BRAM_WW2A0_0", + "CLBLM_WW2A0" + ], + [ + "BRAM_WW2A1_0", + "CLBLM_WW2A1" + ], + [ + "BRAM_WW2A2_0", + "CLBLM_WW2A2" + ], + [ + "BRAM_WW2A3_0", + "CLBLM_WW2A3" + ], + [ + "BRAM_WW2END0_0", + "CLBLM_WW2END0" + ], + [ + "BRAM_WW2END1_0", + "CLBLM_WW2END1" + ], + [ + "BRAM_WW2END2_0", + "CLBLM_WW2END2" + ], + [ + "BRAM_WW2END3_0", + "CLBLM_WW2END3" + ], + [ + "BRAM_WW4A0_0", + "CLBLM_WW4A0" + ], + [ + "BRAM_WW4A1_0", + "CLBLM_WW4A1" + ], + [ + "BRAM_WW4A2_0", + "CLBLM_WW4A2" + ], + [ + "BRAM_WW4A3_0", + "CLBLM_WW4A3" + ], + [ + "BRAM_WW4B0_0", + "CLBLM_WW4B0" + ], + [ + "BRAM_WW4B1_0", + "CLBLM_WW4B1" + ], + [ + "BRAM_WW4B2_0", + "CLBLM_WW4B2" + ], + [ + "BRAM_WW4B3_0", + "CLBLM_WW4B3" + ], + [ + "BRAM_WW4C0_0", + "CLBLM_WW4C0" + ], + [ + "BRAM_WW4C1_0", + "CLBLM_WW4C1" + ], + [ + "BRAM_WW4C2_0", + "CLBLM_WW4C2" + ], + [ + "BRAM_WW4C3_0", + "CLBLM_WW4C3" + ], + [ + "BRAM_WW4END0_0", + "CLBLM_WW4END0" + ], + [ + "BRAM_WW4END1_0", + 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], + [ + "BRKH_CLK_R_CK_GCLK23", + "CLK_BUFG_CK_GCLK23" + ], + [ + "BRKH_CLK_R_CK_GCLK24", + "CLK_BUFG_CK_GCLK24" + ], + [ + "BRKH_CLK_R_CK_GCLK25", + "CLK_BUFG_CK_GCLK25" + ], + [ + "BRKH_CLK_R_CK_GCLK26", + "CLK_BUFG_CK_GCLK26" + ], + [ + "BRKH_CLK_R_CK_GCLK27", + "CLK_BUFG_CK_GCLK27" + ], + [ + "BRKH_CLK_R_CK_GCLK28", + "CLK_BUFG_CK_GCLK28" + ], + [ + "BRKH_CLK_R_CK_GCLK29", + "CLK_BUFG_CK_GCLK29" + ], + [ + "BRKH_CLK_R_CK_GCLK30", + "CLK_BUFG_CK_GCLK30" + ], + [ + "BRKH_CLK_R_CK_GCLK31", + "CLK_BUFG_CK_GCLK31" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "BRKH_CLK", + "CLK_BUFG_TOP_R" + ], + "wire_pairs": [ + [ + "BRKH_CLK_R_CK_GCLK0", + "CLK_BUFG_CK_GCLK0" + ], + [ + "BRKH_CLK_R_CK_GCLK1", + "CLK_BUFG_CK_GCLK1" + ], + [ + "BRKH_CLK_R_CK_GCLK2", + "CLK_BUFG_CK_GCLK2" + ], + [ + "BRKH_CLK_R_CK_GCLK3", + "CLK_BUFG_CK_GCLK3" + ], + [ + "BRKH_CLK_R_CK_GCLK4", + "CLK_BUFG_CK_GCLK4" + ], + [ + "BRKH_CLK_R_CK_GCLK5", + "CLK_BUFG_CK_GCLK5" + ], + [ + "BRKH_CLK_R_CK_GCLK6", + "CLK_BUFG_CK_GCLK6" + ], + [ + "BRKH_CLK_R_CK_GCLK7", + "CLK_BUFG_CK_GCLK7" + ], + [ + "BRKH_CLK_R_CK_GCLK8", + "CLK_BUFG_CK_GCLK8" + ], + [ + "BRKH_CLK_R_CK_GCLK9", + "CLK_BUFG_CK_GCLK9" + ], + [ + "BRKH_CLK_R_CK_GCLK10", + "CLK_BUFG_CK_GCLK10" + ], + [ + "BRKH_CLK_R_CK_GCLK11", + "CLK_BUFG_CK_GCLK11" + ], + [ + "BRKH_CLK_R_CK_GCLK12", + "CLK_BUFG_CK_GCLK12" + ], + [ + "BRKH_CLK_R_CK_GCLK13", + "CLK_BUFG_CK_GCLK13" + ], + [ + "BRKH_CLK_R_CK_GCLK14", + "CLK_BUFG_CK_GCLK14" + ], + [ + "BRKH_CLK_R_CK_GCLK15", + "CLK_BUFG_CK_GCLK15" + ], + [ + "BRKH_CLK_R_CK_GCLK16", + "CLK_BUFG_CK_GCLK16" + ], + [ + "BRKH_CLK_R_CK_GCLK17", + "CLK_BUFG_CK_GCLK17" + ], + [ + "BRKH_CLK_R_CK_GCLK18", + "CLK_BUFG_CK_GCLK18" + ], + [ + "BRKH_CLK_R_CK_GCLK19", + "CLK_BUFG_CK_GCLK19" + ], + [ + "BRKH_CLK_R_CK_GCLK20", + "CLK_BUFG_CK_GCLK20" + ], + [ + "BRKH_CLK_R_CK_GCLK21", + "CLK_BUFG_CK_GCLK21" + ], + [ + "BRKH_CLK_R_CK_GCLK22", + "CLK_BUFG_CK_GCLK22" + ], + [ + "BRKH_CLK_R_CK_GCLK23", + "CLK_BUFG_CK_GCLK23" + ], + [ + "BRKH_CLK_R_CK_GCLK24", + "CLK_BUFG_CK_GCLK24" + ], + [ + "BRKH_CLK_R_CK_GCLK25", + "CLK_BUFG_CK_GCLK25" + ], + [ + "BRKH_CLK_R_CK_GCLK26", + "CLK_BUFG_CK_GCLK26" + ], + [ + "BRKH_CLK_R_CK_GCLK27", + "CLK_BUFG_CK_GCLK27" + ], + [ + "BRKH_CLK_R_CK_GCLK28", + "CLK_BUFG_CK_GCLK28" + ], + [ + "BRKH_CLK_R_CK_GCLK29", + "CLK_BUFG_CK_GCLK29" + ], + [ + "BRKH_CLK_R_CK_GCLK30", + "CLK_BUFG_CK_GCLK30" + ], + [ + "BRKH_CLK_R_CK_GCLK31", + "CLK_BUFG_CK_GCLK31" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "BRKH_CLK", + "CLK_FEED" + ], + "wire_pairs": [ + [ + "BRKH_CLK_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "BRKH_CLK_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "BRKH_CLK_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "BRKH_CLK_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "BRKH_CLK_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "BRKH_CLK_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "BRKH_CLK_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "BRKH_CLK_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "BRKH_CLK_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "BRKH_CLK_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "BRKH_CLK_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "BRKH_CLK_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "BRKH_CLK_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "BRKH_CLK_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "BRKH_CLK_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "BRKH_CLK_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "BRKH_CLK_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "BRKH_CLK_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "BRKH_CLK_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "BRKH_CLK_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "BRKH_CLK_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "BRKH_CLK_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "BRKH_CLK_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "BRKH_CLK_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "BRKH_CLK_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "BRKH_CLK_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "BRKH_CLK_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "BRKH_CLK_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "BRKH_CLK_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "BRKH_CLK_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "BRKH_CLK_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "BRKH_CLK_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "BRKH_CLK_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ] + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "tile_types": [ + "BRKH_CLK", + "CLK_FEED" + ], + "wire_pairs": [ + [ + "BRKH_CLK_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ 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"wire_pairs": [ + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_CLB" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CLB_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CLB_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CLB_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CLB_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CLB_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CLB_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CLB_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CLB_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CLB_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CLB_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CLB_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CLB_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CLB_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CLB_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CLB_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CLB_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CLB_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CLB_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CLB_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CLB_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CLB_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CLB_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CLB_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CLB_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CLB_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CLB_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CLB_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CLB_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CLB_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CLB_CK_IN13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_CLB_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_CLB_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_CLB_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_CLB_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L_BOT_UTURN" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_R" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_R_BOT_UTURN" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VFRAME" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VFRAME_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VFRAME_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_FIFO_L" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_CLK_0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_MUX_CLK_1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_MUX_CLK_2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_MUX_CLK_3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_MUX_CLK_4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_MUX_CLK_5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_MUX_CLK_6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_MUX_CLK_7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_MUX_CLK_8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_MUX_CLK_9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_MUX_CLK_10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_MUX_CLK_11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_MUX_CLK_12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_MUX_CLK_13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_FIFO_L" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_FEEDTHRU_1" + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_1_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_1_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_1_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_1_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_1_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_1_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_1_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_1_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_1_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_1_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_FEEDTHRU_1_CK_BUFHCLK10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_FEEDTHRU_1_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_FEEDTHRU_1_CK_BUFRCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_FEEDTHRU_1_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + "HCLK_FEEDTHRU_1_CK_BUFRCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK3", + "HCLK_FEEDTHRU_1_CK_BUFRCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN0", + "HCLK_FEEDTHRU_1_CK_IN0" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN1", + "HCLK_FEEDTHRU_1_CK_IN1" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN2", + "HCLK_FEEDTHRU_1_CK_IN2" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN3", + "HCLK_FEEDTHRU_1_CK_IN3" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN4", + "HCLK_FEEDTHRU_1_CK_IN4" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN5", + "HCLK_FEEDTHRU_1_CK_IN5" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN6", + "HCLK_FEEDTHRU_1_CK_IN6" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN7", + "HCLK_FEEDTHRU_1_CK_IN7" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN8", + "HCLK_FEEDTHRU_1_CK_IN8" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN9", + "HCLK_FEEDTHRU_1_CK_IN9" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN10", + "HCLK_FEEDTHRU_1_CK_IN10" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN11", + "HCLK_FEEDTHRU_1_CK_IN11" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN12", + "HCLK_FEEDTHRU_1_CK_IN12" + ], + [ + "HCLK_FEEDTHRU_1_CK_IN13", + "HCLK_FEEDTHRU_1_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_FEEDTHRU_2" + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_2_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_2_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_2_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_2_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_2_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_2_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_2_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_2_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_2_CK_BUFHCLK9" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_FEEDTHRU_2_CK_BUFHCLK10" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_FEEDTHRU_2_CK_BUFHCLK11" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_FEEDTHRU_2_CK_BUFRCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_FEEDTHRU_2_CK_BUFRCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + 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"HCLK_INT_INTERFACE_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + 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"HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_CK_IN6" + ], + [ + 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"HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_VFRAME" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_INT_INTERFACE_CK_IN7", + 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"HCLK_IOI_CK_BUFHCLK7" + ], + [ + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOI_CK_BUFHCLK8" + ], + [ + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOI_CK_BUFHCLK9" + ], + [ + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOI_CK_BUFHCLK10" + ], + [ + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOI_CK_BUFHCLK11" + ], + [ + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOI_CK_BUFRCLK0" + ], + [ + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFRCLK1" + ], + [ + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOI_CK_BUFRCLK2" + ], + [ + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOI_CK_BUFRCLK3" + ], + [ + "HCLK_IOB_PERFCLK0", + "HCLK_IOI_IOCLK_PLL0" + ], + [ + "HCLK_IOB_PERFCLK1", + "HCLK_IOI_IOCLK_PLL1" + ], + [ + "HCLK_IOB_PERFCLK2", + "HCLK_IOI_IOCLK_PLL2" + ], + [ + "HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_IOB", + "HCLK_IOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOI_CK_BUFHCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOI_CK_BUFHCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK2", 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"HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_IOI3", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_IOI3", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "HCLK_IOI3", + "LIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_TOP0", + "LIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "LIOI_I2GCLK_TOP1" + ], + [ + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" + ], + [ + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" + ], + [ + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" + ], + [ + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" + ], + [ + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" + ], + [ + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" + ], + [ + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" + ], + [ + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ] + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "tile_types": [ + "HCLK_IOI3", + "LIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_BOT0", + "LIOI_I2GCLK_BOT1" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "LIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ], + [ + "HCLK_IOI_IDELAYCTRL_RDY", + "IOI_IDELAYCTRL_RDY" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX2", + "IOI_IMUX_RC2" + ], + [ + "HCLK_IOI_RCLK_IMUX3", + "IOI_IMUX_RC3" + ], + [ + "HCLK_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2" + ], + [ + "HCLK_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3" + ], + [ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "HCLK_IOI3", + "RIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_TOP0", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "RIOI_I2GCLK_TOP1" + ], + [ + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" + ], + [ + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" + ], + [ + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" + ], + [ + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" + ], + [ + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" + ], + [ + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" + ], + [ + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" + ], + [ + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ] + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "tile_types": [ + "HCLK_IOI3", + "RIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_BOT0", + "RIOI_I2GCLK_BOT1" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ], 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[ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_L", + "HCLK_R" + ], + "wire_pairs": [ + [ + "HCLK_CCIO0", + "HCLK_CCIO0" + ], + [ + "HCLK_CCIO1", + "HCLK_CCIO1" + ], + [ + "HCLK_CCIO2", + "HCLK_CCIO2" + ], + [ + "HCLK_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" 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