diff --git a/Info.md b/Info.md index a95ee8e..715d719 100644 --- a/Info.md +++ b/Info.md @@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING). # Details -Last updated on Fri Dec 7 05:19:28 UTC 2018 (2018-12-07T05:19:28+00:00). +Last updated on Fri Dec 7 06:43:38 UTC 2018 (2018-12-07T06:43:38+00:00). Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-1084-gafe50c6](https://github.com/SymbiFlow/prjxray/commit/afe50c68c464c0cd4a3fa92b6a07c9abbe41682f). @@ -176,7 +176,7 @@ Results have checksums; * [`db8c88384575a7e0562692550bdba7a4089ea5fabe451bf58403d3a85af419a0 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json) * [`4d6130cb2604efae8ca5d628b95be2549083c16c639d335bdc906924e37ec28c ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json) * [`dbf0ff3b27d1fac02572351765f1b17b3e950ed4e8fe95ac6bcd71012e4f7b2d ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json) - * [`6ae28ffd57cb4c4f7a731e0ea8e37173f079db2cfe275f05b526ba261db5d234 ./artix7/tileconn.json`](./artix7/tileconn.json) + * [`22ec794e0d8e263d117dcc3606363c042b4cb186a14f4da81efbaa75d86037f3 ./artix7/tileconn.json`](./artix7/tileconn.json) * [`3dcf45da1b1f6d0b0f4867c6cabd17366a383652f09b6838e3f906a4b5d1a677 ./artix7/tilegrid.json`](./artix7/tilegrid.json) * [`a93b4be2b2832d1a9240b892f6d8db469f3d9cf6229cc6856a197e854f4abc8a ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json) * [`fff3e640e286158767fc484ec932d0ce7eba48c1168798c11c7779426a846004 ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json) @@ -411,7 +411,7 @@ Results have checksums; * [`db8c88384575a7e0562692550bdba7a4089ea5fabe451bf58403d3a85af419a0 ./kintex7/site_type_TIEOFF.json`](./kintex7/site_type_TIEOFF.json) * [`4d6130cb2604efae8ca5d628b95be2549083c16c639d335bdc906924e37ec28c ./kintex7/site_type_USR_ACCESS.json`](./kintex7/site_type_USR_ACCESS.json) * [`dbf0ff3b27d1fac02572351765f1b17b3e950ed4e8fe95ac6bcd71012e4f7b2d ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json) - * [`46f7c8b9fcb943f16d55e233c5ac3c31089e55b1ccb89b8c38c18cb068af6111 ./kintex7/tileconn.json`](./kintex7/tileconn.json) + * [`eaea5154fc105272fef0c39faebac6089fb5a10bd9c4c6dea50332639f04380b ./kintex7/tileconn.json`](./kintex7/tileconn.json) * [`eeef94852cdce206d5958d0d2e5754459cfb2e7c843c12871718bea8e202daa3 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json) * [`a93b4be2b2832d1a9240b892f6d8db469f3d9cf6229cc6856a197e854f4abc8a ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json) * [`fff3e640e286158767fc484ec932d0ce7eba48c1168798c11c7779426a846004 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json) diff --git a/artix7/tileconn.json b/artix7/tileconn.json index 1376e0d..a8d0080 100644 --- a/artix7/tileconn.json +++ b/artix7/tileconn.json @@ -1,1417 +1,16461 @@ [ + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "BRAM_INT_INTERFACE_L", + "BRAM_L" + ], + "wire_pairs": [ + [ + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_0" + ], + [ + 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"BRAM_WW4END3_0" ] ] }, { "grid_deltas": [ 1, - -3 + 1 ], "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" + "BRAM_INT_INTERFACE_R", + "BRAM_R" ], "wire_pairs": [ [ - "CLK_HROW_WW4END3_6", - "VBRK_WW4END3" + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_1" ], [ - "CLK_HROW_NW4END2_6", - "VBRK_NW4END2" + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_1" ], [ - "CLK_HROW_SW2A1_6", - "VBRK_SW2A1" + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_1" ], [ - "CLK_HROW_SW2A3_6", - "VBRK_SW2A3" + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_1" ], [ - "CLK_HROW_WW2END0_6", - "VBRK_WW2END0" + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_1" ], [ - "CLK_HROW_MONITOR_P_6", - "VBRK_MONITOR_P" + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_1" ], [ - "CLK_HROW_ER1BEG1_6", - "VBRK_ER1BEG1" + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_1" ], [ - "CLK_HROW_EE4B3_6", - "VBRK_EE4B3" + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_1" ], [ - "CLK_HROW_EE4B0_6", - "VBRK_EE4B0" + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_1" ], [ - "CLK_HROW_WW4A1_6", - "VBRK_WW4A1" + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_1" ], [ - "CLK_HROW_WW4B1_6", - "VBRK_WW4B1" + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_1" ], [ - "CLK_HROW_NW2A0_6", - "VBRK_NW2A0" + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_1" ], [ - "CLK_HROW_EL1BEG2_6", - "VBRK_EL1BEG2" + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_1" ], [ - "CLK_HROW_WL1END0_6", - "VBRK_WL1END0" + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_1" ], [ - "CLK_HROW_LH7_6", - "VBRK_LH7" + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_1" ], [ - "CLK_HROW_EE4B2_6", - "VBRK_EE4B2" + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_1" ], [ - "CLK_HROW_EE2A1_6", - "VBRK_EE2A1" + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_1" ], [ - "CLK_HROW_WW4B2_6", - "VBRK_WW4B2" + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_1" ], [ - "CLK_HROW_EL1BEG1_6", - "VBRK_EL1BEG1" + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_1" ], [ - "CLK_HROW_ER1BEG0_6", - "VBRK_ER1BEG0" + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_1" ], [ - "CLK_HROW_SE2A3_6", - "VBRK_SE2A3" + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_1" ], [ - "CLK_HROW_EE2A2_6", - "VBRK_EE2A2" + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_1" ], [ - "CLK_HROW_SW2A2_6", - "VBRK_SW2A2" + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_1" ], [ - "CLK_HROW_EE2BEG0_6", - "VBRK_EE2BEG0" + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_1" ], [ - "CLK_HROW_WW2A1_6", - "VBRK_WW2A1" + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_1" ], [ - "CLK_HROW_SE4C1_6", - "VBRK_SE4C1" + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_1" ], [ - "CLK_HROW_WL1END2_6", - "VBRK_WL1END2" + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_1" ], [ - "CLK_HROW_NE4C2_6", - "VBRK_NE4C2" + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_1" ], [ - "CLK_HROW_WW2A2_6", - "VBRK_WW2A2" + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_1" ], [ - "CLK_HROW_EE4A1_6", - "VBRK_EE4A1" + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_1" ], [ - "CLK_HROW_EE2A3_6", - "VBRK_EE2A3" + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_1" ], [ - "CLK_HROW_WL1END1_6", - "VBRK_WL1END1" + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_1" ], [ - "CLK_HROW_NW2A1_6", - "VBRK_NW2A1" + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_1" ], [ - "CLK_HROW_SW2A0_6", - "VBRK_SW2A0" + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_1" ], [ - "CLK_HROW_WW4END1_6", - "VBRK_WW4END1" + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_1" ], [ - "CLK_HROW_EE4B1_6", - "VBRK_EE4B1" + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_1" ], [ - "CLK_HROW_LH3_6", - "VBRK_LH3" + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_1" ], [ - "CLK_HROW_EE4C1_6", - "VBRK_EE4C1" + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_1" ], [ - "CLK_HROW_SE4C3_6", - "VBRK_SE4C3" + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_1" ], [ - "CLK_HROW_SE2A2_6", - "VBRK_SE2A2" + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_1" ], [ - "CLK_HROW_SW4END3_6", - "VBRK_SW4END3" + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_1" ], [ - "CLK_HROW_SW4END2_6", - "VBRK_SW4END2" + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_1" ], [ - "CLK_HROW_WW2END1_6", - "VBRK_WW2END1" + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_1" ], [ - "CLK_HROW_SE4BEG3_6", - "VBRK_SE4BEG3" + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_1" ], [ - "CLK_HROW_WW4END0_6", - "VBRK_WW4END0" + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_1" ], [ - "CLK_HROW_SE4C0_6", - "VBRK_SE4C0" + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_1" ], [ - "CLK_HROW_WW4END2_6", - "VBRK_WW4END2" + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_1" ], [ - "CLK_HROW_SE4C2_6", - "VBRK_SE4C2" + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_1" ], [ - "CLK_HROW_EE2BEG1_6", - "VBRK_EE2BEG1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX0", + "BRAM_IMUX0_UTURN_1" ], [ - "CLK_HROW_NW4A2_6", - "VBRK_NW4A2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX1", + "BRAM_IMUX1_UTURN_1" ], [ - "CLK_HROW_WW4A2_6", - "VBRK_WW4A2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX2", + "BRAM_IMUX2_UTURN_1" ], [ - "CLK_HROW_NW4A3_6", - "VBRK_NW4A3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX3", + "BRAM_IMUX3_UTURN_1" ], [ - "CLK_HROW_EE4A0_6", - "VBRK_EE4A0" + "INT_INTERFACE_BRAM_UTURN_R_IMUX4", + "BRAM_IMUX4_UTURN_1" ], [ - "CLK_HROW_SE4BEG1_6", - "VBRK_SE4BEG1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX5", + "BRAM_IMUX5_UTURN_1" ], [ - "CLK_HROW_WW4A3_6", - "VBRK_WW4A3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX6", + "BRAM_IMUX6_UTURN_1" ], [ - "CLK_HROW_NE2A2_6", - "VBRK_NE2A2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX7", + "BRAM_IMUX7_UTURN_1" ], [ - "CLK_HROW_NW2A2_6", - "VBRK_NW2A2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX8", + "BRAM_IMUX8_UTURN_1" ], [ - "CLK_HROW_NE4BEG2_6", - "VBRK_NE4BEG2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX9", + "BRAM_IMUX9_UTURN_1" ], [ - "CLK_HROW_LH8_6", - "VBRK_LH8" + "INT_INTERFACE_BRAM_UTURN_R_IMUX10", + "BRAM_IMUX10_UTURN_1" ], [ - "CLK_HROW_SW4END1_6", - "VBRK_SW4END1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX11", + "BRAM_IMUX11_UTURN_1" ], [ - "CLK_HROW_NE4C3_6", - "VBRK_NE4C3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX12", + "BRAM_IMUX12_UTURN_1" ], [ - "CLK_HROW_LH9_6", - "VBRK_LH9" + "INT_INTERFACE_BRAM_UTURN_R_IMUX13", + "BRAM_IMUX13_UTURN_1" ], [ - "CLK_HROW_EE4BEG3_6", - "VBRK_EE4BEG3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX14", + "BRAM_IMUX14_UTURN_1" ], [ - "CLK_HROW_WW2END3_6", - "VBRK_WW2END3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX15", + "BRAM_IMUX15_UTURN_1" ], [ - "CLK_HROW_WW4C2_6", - "VBRK_WW4C2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX16", + "BRAM_IMUX16_UTURN_1" ], [ - "CLK_HROW_LH12_6", - "VBRK_LH12" + "INT_INTERFACE_BRAM_UTURN_R_IMUX17", + "BRAM_IMUX17_UTURN_1" ], [ - "CLK_HROW_WR1END1_6", - "VBRK_WR1END1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX18", + "BRAM_IMUX18_UTURN_1" ], [ - "CLK_HROW_WW4B0_6", - "VBRK_WW4B0" + "INT_INTERFACE_BRAM_UTURN_R_IMUX19", + "BRAM_IMUX19_UTURN_1" ], [ - "CLK_HROW_WW4A0_6", - "VBRK_WW4A0" + "INT_INTERFACE_BRAM_UTURN_R_IMUX20", + "BRAM_IMUX20_UTURN_1" ], [ - "CLK_HROW_EL1BEG3_6", - "VBRK_EL1BEG3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX21", + "BRAM_IMUX21_UTURN_1" ], [ - "CLK_HROW_EE4A3_6", - "VBRK_EE4A3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX22", + "BRAM_IMUX22_UTURN_1" ], [ - "CLK_HROW_NW4A1_6", - "VBRK_NW4A1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX23", + "BRAM_IMUX23_UTURN_1" ], [ - "CLK_HROW_SE4BEG2_6", - "VBRK_SE4BEG2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX24", + "BRAM_IMUX24_UTURN_1" ], [ - "CLK_HROW_WW2A0_6", - "VBRK_WW2A0" + "INT_INTERFACE_BRAM_UTURN_R_IMUX25", + "BRAM_IMUX25_UTURN_1" ], [ - "CLK_HROW_WW4B3_6", - "VBRK_WW4B3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX26", + "BRAM_IMUX26_UTURN_1" ], [ - "CLK_HROW_WW4C3_6", - "VBRK_WW4C3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX27", + "BRAM_IMUX27_UTURN_1" ], [ - "CLK_HROW_LH11_6", - "VBRK_LH11" + "INT_INTERFACE_BRAM_UTURN_R_IMUX28", + "BRAM_IMUX28_UTURN_1" ], [ - "CLK_HROW_NE4BEG0_6", - "VBRK_NE4BEG0" + "INT_INTERFACE_BRAM_UTURN_R_IMUX29", + "BRAM_IMUX29_UTURN_1" ], [ - "CLK_HROW_NW2A3_6", - "VBRK_NW2A3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX30", + "BRAM_IMUX30_UTURN_1" ], [ - "CLK_HROW_NE2A1_6", - "VBRK_NE2A1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX31", + "BRAM_IMUX31_UTURN_1" ], [ - "CLK_HROW_SE2A1_6", - "VBRK_SE2A1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX32", + "BRAM_IMUX32_UTURN_1" ], [ - "CLK_HROW_NW4END1_6", - "VBRK_NW4END1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX33", + "BRAM_IMUX33_UTURN_1" ], [ - "CLK_HROW_SW4A3_6", - "VBRK_SW4A3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX34", + "BRAM_IMUX34_UTURN_1" ], [ - "CLK_HROW_SW4END0_6", - "VBRK_SW4END0" + "INT_INTERFACE_BRAM_UTURN_R_IMUX35", + "BRAM_IMUX35_UTURN_1" ], [ - "CLK_HROW_EE4C3_6", - "VBRK_EE4C3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX36", + "BRAM_IMUX36_UTURN_1" ], [ - "CLK_HROW_SE2A0_6", - "VBRK_SE2A0" + "INT_INTERFACE_BRAM_UTURN_R_IMUX37", + "BRAM_IMUX37_UTURN_1" ], [ - "CLK_HROW_EE4C0_6", - "VBRK_EE4C0" + "INT_INTERFACE_BRAM_UTURN_R_IMUX38", + "BRAM_IMUX38_UTURN_1" ], [ - "CLK_HROW_WW4C0_6", - "VBRK_WW4C0" + "INT_INTERFACE_BRAM_UTURN_R_IMUX39", + "BRAM_IMUX39_UTURN_1" ], [ - "CLK_HROW_EE4A2_6", - "VBRK_EE4A2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX40", + "BRAM_IMUX40_UTURN_1" ], [ - "CLK_HROW_ER1BEG3_6", - "VBRK_ER1BEG3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX41", + "BRAM_IMUX41_UTURN_1" ], [ - "CLK_HROW_WW2END2_6", - "VBRK_WW2END2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX42", + "BRAM_IMUX42_UTURN_1" ], [ - "CLK_HROW_NE4BEG1_6", - "VBRK_NE4BEG1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX43", + "BRAM_IMUX43_UTURN_1" ], [ - "CLK_HROW_NE4C1_6", - "VBRK_NE4C1" + "INT_INTERFACE_BRAM_UTURN_R_IMUX44", + "BRAM_IMUX44_UTURN_1" ], [ - "CLK_HROW_EE4C2_6", - "VBRK_EE4C2" + "INT_INTERFACE_BRAM_UTURN_R_IMUX45", + "BRAM_IMUX45_UTURN_1" ], [ - "CLK_HROW_NW4END3_6", - "VBRK_NW4END3" + "INT_INTERFACE_BRAM_UTURN_R_IMUX46", + "BRAM_IMUX46_UTURN_1" ], [ - "CLK_HROW_LH6_6", - "VBRK_LH6" + "INT_INTERFACE_BRAM_UTURN_R_IMUX47", + "BRAM_IMUX47_UTURN_1" ], [ - "CLK_HROW_NW4A0_6", - "VBRK_NW4A0" + "INT_INTERFACE_BYP0", + "BRAM_BYP0_1" ], [ - "CLK_HROW_LH4_6", - "VBRK_LH4" + "INT_INTERFACE_BYP1", + "BRAM_BYP1_1" ], [ - "CLK_HROW_WW4C1_6", - "VBRK_WW4C1" + "INT_INTERFACE_BYP2", + "BRAM_BYP2_1" ], [ - "CLK_HROW_NE4BEG3_6", - "VBRK_NE4BEG3" + "INT_INTERFACE_BYP3", + "BRAM_BYP3_1" ], [ - "CLK_HROW_SW4A0_6", - "VBRK_SW4A0" + "INT_INTERFACE_BYP4", + "BRAM_BYP4_1" ], [ - "CLK_HROW_ER1BEG2_6", - "VBRK_ER1BEG2" + "INT_INTERFACE_BYP5", + "BRAM_BYP5_1" ], [ - "CLK_HROW_MONITOR_N_6", - "VBRK_MONITOR_N" + "INT_INTERFACE_BYP6", + "BRAM_BYP6_1" ], [ - "CLK_HROW_NW4END0_6", - "VBRK_NW4END0" + "INT_INTERFACE_BYP7", + "BRAM_BYP7_1" ], [ - "CLK_HROW_NE4C0_6", - "VBRK_NE4C0" + "INT_INTERFACE_CLK0", + "BRAM_CLK0_1" ], [ - "CLK_HROW_EL1BEG0_6", - "VBRK_EL1BEG0" + "INT_INTERFACE_CLK1", + "BRAM_CLK1_1" ], [ - "CLK_HROW_WW2A3_6", - "VBRK_WW2A3" + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_1" ], [ - "CLK_HROW_WR1END3_6", - "VBRK_WR1END3" + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_1" ], [ - "CLK_HROW_LH1_6", - "VBRK_LH1" + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_1" ], [ - "CLK_HROW_EE2A0_6", - "VBRK_EE2A0" + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_1" ], [ - "CLK_HROW_LH10_6", - "VBRK_LH10" + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_1" ], [ - "CLK_HROW_EE4BEG1_6", - "VBRK_EE4BEG1" + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_1" ], [ - "CLK_HROW_NE2A3_6", - "VBRK_NE2A3" + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_1" ], [ - "CLK_HROW_LH2_6", - "VBRK_LH2" + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_1" ], [ - "CLK_HROW_WR1END2_6", - "VBRK_WR1END2" + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_1" ], [ - "CLK_HROW_EE4BEG2_6", - "VBRK_EE4BEG2" + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_1" ], [ - "CLK_HROW_LH5_6", - "VBRK_LH5" + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_1" ], [ - "CLK_HROW_WL1END3_6", - "VBRK_WL1END3" + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_1" ], [ - "CLK_HROW_EE2BEG3_6", - "VBRK_EE2BEG3" + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_1" ], [ - "CLK_HROW_NE2A0_6", - "VBRK_NE2A0" + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_1" ], [ - "CLK_HROW_WR1END0_6", - "VBRK_WR1END0" + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_1" ], [ - "CLK_HROW_SW4A2_6", - "VBRK_SW4A2" + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_1" ], [ - "CLK_HROW_SE4BEG0_6", - "VBRK_SE4BEG0" + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_1" ], [ - "CLK_HROW_EE4BEG0_6", - "VBRK_EE4BEG0" + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_1" ], [ - "CLK_HROW_EE2BEG2_6", - "VBRK_EE2BEG2" + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_1" ], [ - "CLK_HROW_SW4A1_6", - "VBRK_SW4A1" + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_1" + ], + [ + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_1" + ], + [ + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_1" + ], + [ + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_1" + ], + [ + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_1" + ], + [ + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_1" + ], + [ + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_1" + ], + [ + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_1" + ], + [ + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_1" + ], + [ + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_1" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_1" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_1" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_1" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_1" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_1" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_1" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_1" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_1" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_1" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_1" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_1" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_1" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_1" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_1" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_1" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_1" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_1" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_1" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_1" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_1" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_1" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_1" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_1" + ], + [ + "INT_INTERFACE_LH11", + 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"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_FIFO36_CASCADEOUTA_1", + "HCLK_BRAM_CASCADEA_L" + ], + [ + "BRAM_FIFO36_CASCADEOUTB_1", + "HCLK_BRAM_CASCADEB_L" + ] + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "tile_types": [ + "BRAM_L", + "HCLK_BRAM" + ], + "wire_pairs": [ + [ + "BRAM_CASCINBOT_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_FIFO36_CASCADEINA", + "HCLK_BRAM_CASCADEA_L" + ], + [ + "BRAM_FIFO36_CASCADEINB", + "HCLK_BRAM_CASCADEB_L" + ], + [ + "BRAM_PMVBRAM_O", + "HCLK_BRAM_PMVBRAM_O" + ], + [ + "BRAM_PMVBRAM_ODIV2", + "HCLK_BRAM_PMVBRAM_ODIV2" + ], + [ + "BRAM_PMVBRAM_ODIV4", + "HCLK_BRAM_PMVBRAM_ODIV4" + ], + [ + "BRAM_PMVBRAM_SELECT1", + "HCLK_BRAM_PMVBRAM_SELECT1" + ], + [ + "BRAM_PMVBRAM_SELECT2", + "HCLK_BRAM_PMVBRAM_SELECT2" + ], + [ + "BRAM_PMVBRAM_SELECT3", + "HCLK_BRAM_PMVBRAM_SELECT3" + ], + [ + "BRAM_PMVBRAM_SELECT4", + "HCLK_BRAM_PMVBRAM_SELECT4" ] ] }, @@ -1426,220 +16470,124 @@ ], "wire_pairs": [ [ - "BRAM_EE4C3_4", - "VBRK_EE4C3" + "BRAM_EE2A0_4", + "VBRK_EE2A0" ], [ - "BRAM_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "BRAM_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "BRAM_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "BRAM_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "BRAM_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "BRAM_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "BRAM_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "BRAM_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "BRAM_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "BRAM_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "BRAM_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "BRAM_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "BRAM_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "BRAM_LH12_4", - "VBRK_LH12" - ], - [ - "BRAM_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "BRAM_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "BRAM_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "BRAM_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "BRAM_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "BRAM_LH1_4", - "VBRK_LH1" - ], - [ - "BRAM_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "BRAM_LH3_4", - "VBRK_LH3" - ], - [ - "BRAM_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "BRAM_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "BRAM_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "BRAM_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "BRAM_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "BRAM_LH7_4", - "VBRK_LH7" - ], - [ - "BRAM_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "BRAM_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "BRAM_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "BRAM_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "BRAM_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "BRAM_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "BRAM_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "BRAM_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "BRAM_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "BRAM_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "BRAM_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "BRAM_LH5_4", - "VBRK_LH5" - ], - [ - "BRAM_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "BRAM_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "BRAM_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "BRAM_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "BRAM_SW4A1_4", - "VBRK_SW4A1" + "BRAM_EE2A1_4", + "VBRK_EE2A1" ], [ "BRAM_EE2A2_4", "VBRK_EE2A2" ], [ - "BRAM_EE2BEG3_4", - "VBRK_EE2BEG3" + "BRAM_EE2A3_4", + "VBRK_EE2A3" + ], + [ + "BRAM_EE2BEG0_4", + "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_4", "VBRK_EE2BEG1" ], [ - "BRAM_WW4C2_4", - "VBRK_WW4C2" + "BRAM_EE2BEG2_4", + "VBRK_EE2BEG2" ], [ - "BRAM_WW4END3_4", - "VBRK_WW4END3" + "BRAM_EE2BEG3_4", + "VBRK_EE2BEG3" ], [ - "BRAM_LH2_4", - "VBRK_LH2" + "BRAM_EE4A0_4", + "VBRK_EE4A0" ], [ - "BRAM_WW2A0_4", - "VBRK_WW2A0" + "BRAM_EE4A1_4", + "VBRK_EE4A1" ], [ - "BRAM_WW2END0_4", - "VBRK_WW2END0" + "BRAM_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "BRAM_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "BRAM_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "BRAM_EE4B1_4", + "VBRK_EE4B1" + ], + [ + "BRAM_EE4B2_4", + "VBRK_EE4B2" + ], + [ + "BRAM_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "BRAM_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "BRAM_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "BRAM_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "BRAM_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "BRAM_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "BRAM_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "BRAM_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "BRAM_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "BRAM_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "BRAM_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "BRAM_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "BRAM_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "BRAM_ER1BEG1_4", + "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_4", @@ -1650,157 +16598,269 @@ "VBRK_ER1BEG3" ], [ - "BRAM_WW2END3_4", - "VBRK_WW2END3" + "BRAM_LH1_4", + "VBRK_LH1" ], [ - "BRAM_SE2A1_4", - "VBRK_SE2A1" + "BRAM_LH2_4", + "VBRK_LH2" ], [ - "BRAM_EE2BEG0_4", - "VBRK_EE2BEG0" + "BRAM_LH3_4", + "VBRK_LH3" ], [ - "BRAM_SE2A2_4", - "VBRK_SE2A2" + "BRAM_LH4_4", + "VBRK_LH4" ], [ - "BRAM_SE4BEG2_4", - "VBRK_SE4BEG2" + "BRAM_LH5_4", + "VBRK_LH5" ], [ - "BRAM_WW4C3_4", - "VBRK_WW4C3" + "BRAM_LH6_4", + "VBRK_LH6" ], [ - "BRAM_EE4C2_4", - "VBRK_EE4C2" + "BRAM_LH7_4", + "VBRK_LH7" ], [ - "BRAM_WW4B1_4", - "VBRK_WW4B1" + "BRAM_LH8_4", + "VBRK_LH8" ], [ - "BRAM_EE4A0_4", - "VBRK_EE4A0" + "BRAM_LH9_4", + "VBRK_LH9" ], [ - "BRAM_NE4C0_4", - "VBRK_NE4C0" + "BRAM_LH10_4", + "VBRK_LH10" ], [ - "BRAM_NE2A2_4", - "VBRK_NE2A2" + "BRAM_LH11_4", + "VBRK_LH11" ], [ - "BRAM_WW4A1_4", - "VBRK_WW4A1" + "BRAM_LH12_4", + "VBRK_LH12" ], [ - "BRAM_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "BRAM_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "BRAM_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "BRAM_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "BRAM_NE4BEG0_4", - "VBRK_NE4BEG0" + "BRAM_MONITOR_N_4", + "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_4", "VBRK_MONITOR_P" ], [ - "BRAM_WR1END3_4", - "VBRK_WR1END3" + "BRAM_NE2A0_4", + "VBRK_NE2A0" ], [ - "BRAM_SW2A0_4", - "VBRK_SW2A0" + "BRAM_NE2A1_4", + "VBRK_NE2A1" ], [ - "BRAM_NE4C3_4", - "VBRK_NE4C3" + "BRAM_NE2A2_4", + "VBRK_NE2A2" ], [ - "BRAM_EE4A1_4", - "VBRK_EE4A1" + "BRAM_NE2A3_4", + "VBRK_NE2A3" ], [ - "BRAM_WW4C0_4", - "VBRK_WW4C0" + "BRAM_NE4BEG0_4", + "VBRK_NE4BEG0" ], [ - "BRAM_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "BRAM_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "BRAM_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "BRAM_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "BRAM_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "BRAM_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "BRAM_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "BRAM_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "BRAM_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "BRAM_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "BRAM_EE2A1_4", - "VBRK_EE2A1" + "BRAM_NE4BEG1_4", + "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_4", "VBRK_NE4BEG2" ], [ - "BRAM_ER1BEG0_4", - "VBRK_ER1BEG0" + "BRAM_NE4BEG3_4", + "VBRK_NE4BEG3" ], [ - "BRAM_EE4B2_4", - "VBRK_EE4B2" + "BRAM_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "BRAM_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "BRAM_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "BRAM_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "BRAM_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "BRAM_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "BRAM_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "BRAM_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "BRAM_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "BRAM_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "BRAM_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "BRAM_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "BRAM_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "BRAM_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "BRAM_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "BRAM_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "BRAM_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "BRAM_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "BRAM_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "BRAM_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "BRAM_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "BRAM_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "BRAM_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "BRAM_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "BRAM_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "BRAM_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "BRAM_SE4C2_4", + "VBRK_SE4C2" ], [ "BRAM_SE4C3_4", "VBRK_SE4C3" ], + [ + "BRAM_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "BRAM_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "BRAM_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "BRAM_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "BRAM_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "BRAM_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "BRAM_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "BRAM_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "BRAM_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "BRAM_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "BRAM_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "BRAM_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "BRAM_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "BRAM_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "BRAM_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "BRAM_WL1END3_4", + "VBRK_WL1END3" + ], [ "BRAM_WR1END0_4", "VBRK_WR1END0" @@ -1810,1008 +16870,2316 @@ "VBRK_WR1END1" ], [ - "BRAM_LH4_4", - "VBRK_LH4" + "BRAM_WR1END2_4", + "VBRK_WR1END2" ], [ - "BRAM_LH9_4", - "VBRK_LH9" + "BRAM_WR1END3_4", + "VBRK_WR1END3" ], [ - "BRAM_SE2A0_4", - "VBRK_SE2A0" + "BRAM_WW2A0_4", + "VBRK_WW2A0" ], [ - "BRAM_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "BRAM_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "BRAM_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "BRAM_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "BRAM_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "BRAM_LH6_4", - "VBRK_LH6" - ], - [ - "BRAM_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "BRAM_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "BRAM_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "BRAM_LH10_4", - "VBRK_LH10" - ], - [ - "BRAM_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "BRAM_LH8_4", - "VBRK_LH8" + "BRAM_WW2A1_4", + "VBRK_WW2A1" ], [ "BRAM_WW2A2_4", "VBRK_WW2A2" ], + [ + "BRAM_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "BRAM_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "BRAM_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "BRAM_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "BRAM_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "BRAM_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "BRAM_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "BRAM_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "BRAM_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "BRAM_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "BRAM_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "BRAM_WW4B2_4", + "VBRK_WW4B2" + ], [ "BRAM_WW4B3_4", "VBRK_WW4B3" ], [ - "BRAM_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "BRAM_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "BRAM_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "BRAM_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "BRAM_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "BRAM_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "BRAM_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "BRAM_LH11_4", - "VBRK_LH11" - ], - [ - "BRAM_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "BRAM_NW4END2_4", - "VBRK_NW4END2" + "BRAM_WW4C0_4", + "VBRK_WW4C0" ], [ "BRAM_WW4C1_4", "VBRK_WW4C1" ], [ - "BRAM_WL1END2_4", - "VBRK_WL1END2" + "BRAM_WW4C2_4", + "VBRK_WW4C2" ], [ - "BRAM_EE4C0_4", - "VBRK_EE4C0" + "BRAM_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "BRAM_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "BRAM_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "BRAM_WW4END3_4", + "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, - -4 + -3 ], "tile_types": [ - "DSP_R", - "INT_INTERFACE_R" + "BRAM_L", + "VBRK" ], "wire_pairs": [ [ - "DSP_SE4BEG0_4", - "INT_INTERFACE_SE4BEG0" + "BRAM_EE2A0_3", + "VBRK_EE2A0" ], [ - "DSP_WW4A3_4", - "INT_INTERFACE_WW4A3" + "BRAM_EE2A1_3", + "VBRK_EE2A1" ], [ - "DSP_LOGIC_OUTS_B17_4", - "INT_INTERFACE_LOGIC_OUTS_B17" + "BRAM_EE2A2_3", + "VBRK_EE2A2" ], [ - "DSP_LOGIC_OUTS_B13_4", - "INT_INTERFACE_LOGIC_OUTS_B13" + "BRAM_EE2A3_3", + "VBRK_EE2A3" ], [ - "DSP_EE2A1_4", - "INT_INTERFACE_EE2A1" + "BRAM_EE2BEG0_3", + "VBRK_EE2BEG0" ], [ - "DSP_SW2A1_4", - "INT_INTERFACE_SW2A1" + "BRAM_EE2BEG1_3", + "VBRK_EE2BEG1" ], [ - "DSP_SE2A1_4", - "INT_INTERFACE_SE2A1" + "BRAM_EE2BEG2_3", + "VBRK_EE2BEG2" ], [ - "DSP_WW4B1_4", - "INT_INTERFACE_WW4B1" + "BRAM_EE2BEG3_3", + "VBRK_EE2BEG3" ], [ - "DSP_LOGIC_OUTS_B1_4", - "INT_INTERFACE_LOGIC_OUTS_B1" + "BRAM_EE4A0_3", + "VBRK_EE4A0" ], [ - "DSP_WL1END0_4", - "INT_INTERFACE_WL1END0" + "BRAM_EE4A1_3", + "VBRK_EE4A1" ], [ - "DSP_NW4A0_4", - "INT_INTERFACE_NW4A0" + "BRAM_EE4A2_3", + "VBRK_EE4A2" ], [ - "DSP_EL1BEG1_4", - "INT_INTERFACE_EL1BEG1" + "BRAM_EE4A3_3", + "VBRK_EE4A3" ], [ - "DSP_EE4C1_4", - "INT_INTERFACE_EE4C1" + "BRAM_EE4B0_3", + "VBRK_EE4B0" ], [ - "DSP_SE2A0_4", - "INT_INTERFACE_SE2A0" + "BRAM_EE4B1_3", + "VBRK_EE4B1" ], [ - "DSP_SE2A3_4", - "INT_INTERFACE_SE2A3" + "BRAM_EE4B2_3", + "VBRK_EE4B2" ], [ - "DSP_WW4END0_4", - "INT_INTERFACE_WW4END0" + "BRAM_EE4B3_3", + "VBRK_EE4B3" ], [ - "DSP_SW4A3_4", - "INT_INTERFACE_SW4A3" + "BRAM_EE4BEG0_3", + "VBRK_EE4BEG0" ], [ - "DSP_LOGIC_OUTS_B7_4", - "INT_INTERFACE_LOGIC_OUTS_B7" + "BRAM_EE4BEG1_3", + "VBRK_EE4BEG1" ], [ - "DSP_SW4A1_4", - "INT_INTERFACE_SW4A1" + "BRAM_EE4BEG2_3", + "VBRK_EE4BEG2" ], [ - "DSP_WW2A0_4", - "INT_INTERFACE_WW2A0" + "BRAM_EE4BEG3_3", + "VBRK_EE4BEG3" ], [ - "DSP_NW2A2_4", - "INT_INTERFACE_NW2A2" + "BRAM_EE4C0_3", + "VBRK_EE4C0" ], [ - "DSP_IMUX2_4", - "INT_INTERFACE_IMUX2" + "BRAM_EE4C1_3", + "VBRK_EE4C1" ], [ - "DSP_IMUX42_4", - "INT_INTERFACE_IMUX42" + "BRAM_EE4C2_3", + "VBRK_EE4C2" ], [ - "DSP_SE4C1_4", - "INT_INTERFACE_SE4C1" + "BRAM_EE4C3_3", + "VBRK_EE4C3" ], [ - "DSP_WW4C3_4", - "INT_INTERFACE_WW4C3" + "BRAM_EL1BEG0_3", + "VBRK_EL1BEG0" ], [ - "DSP_EE4C0_4", - "INT_INTERFACE_EE4C0" + "BRAM_EL1BEG1_3", + "VBRK_EL1BEG1" ], [ - "DSP_FAN6_4", - "INT_INTERFACE_FAN6" + "BRAM_EL1BEG2_3", + "VBRK_EL1BEG2" ], [ - "DSP_IMUX7_4", - "INT_INTERFACE_IMUX7" + "BRAM_EL1BEG3_3", + "VBRK_EL1BEG3" ], [ - "DSP_IMUX0_4", - "INT_INTERFACE_IMUX0" + "BRAM_ER1BEG0_3", + "VBRK_ER1BEG0" ], [ - "DSP_IMUX32_4", - "INT_INTERFACE_IMUX32" + "BRAM_ER1BEG1_3", + "VBRK_ER1BEG1" ], [ - "DSP_IMUX14_4", - "INT_INTERFACE_IMUX14" + "BRAM_ER1BEG2_3", + "VBRK_ER1BEG2" ], [ - "DSP_WW2A1_4", - "INT_INTERFACE_WW2A1" + "BRAM_ER1BEG3_3", + "VBRK_ER1BEG3" ], [ - "DSP_EE4A3_4", - "INT_INTERFACE_EE4A3" + "BRAM_LH1_3", + "VBRK_LH1" ], [ - "DSP_FAN7_4", - "INT_INTERFACE_FAN7" + "BRAM_LH2_3", + "VBRK_LH2" ], [ - "DSP_EE4C3_4", - "INT_INTERFACE_EE4C3" + "BRAM_LH3_3", + "VBRK_LH3" ], [ - "DSP_WR1END2_4", - "INT_INTERFACE_WR1END2" + "BRAM_LH4_3", + "VBRK_LH4" ], [ - "DSP_EE4B1_4", - "INT_INTERFACE_EE4B1" + "BRAM_LH5_3", + "VBRK_LH5" ], [ - "DSP_WW4B2_4", - "INT_INTERFACE_WW4B2" + "BRAM_LH6_3", + "VBRK_LH6" ], [ - "DSP_WW2END3_4", - "INT_INTERFACE_WW2END3" + "BRAM_LH7_3", + "VBRK_LH7" ], [ - "DSP_NW4END1_4", - "INT_INTERFACE_NW4END1" + "BRAM_LH8_3", + "VBRK_LH8" ], [ - "DSP_IMUX4_4", - "INT_INTERFACE_IMUX4" + "BRAM_LH9_3", + "VBRK_LH9" ], [ - "DSP_EE4A0_4", - "INT_INTERFACE_EE4A0" + "BRAM_LH10_3", + "VBRK_LH10" ], [ - "DSP_SW4END1_4", - "INT_INTERFACE_SW4END1" + "BRAM_LH11_3", + "VBRK_LH11" ], [ - "DSP_LH3_4", - "INT_INTERFACE_LH3" + "BRAM_LH12_3", + "VBRK_LH12" ], [ - "DSP_NW2A1_4", - "INT_INTERFACE_NW2A1" + "BRAM_MONITOR_N_3", + "VBRK_MONITOR_N" ], [ - "DSP_NW4A3_4", - "INT_INTERFACE_NW4A3" + "BRAM_MONITOR_P_3", + "VBRK_MONITOR_P" ], [ - "DSP_SW4A2_4", - "INT_INTERFACE_SW4A2" + "BRAM_NE2A0_3", + "VBRK_NE2A0" ], [ - "DSP_WW2END1_4", - "INT_INTERFACE_WW2END1" + "BRAM_NE2A1_3", + "VBRK_NE2A1" ], [ - "DSP_CTRL0_4", - "INT_INTERFACE_CTRL0" + "BRAM_NE2A2_3", + "VBRK_NE2A2" ], [ - "DSP_EL1BEG3_4", - "INT_INTERFACE_EL1BEG3" + "BRAM_NE2A3_3", + "VBRK_NE2A3" ], [ - "DSP_IMUX31_4", - "INT_INTERFACE_IMUX31" + "BRAM_NE4BEG0_3", + "VBRK_NE4BEG0" ], [ - "DSP_IMUX11_4", - "INT_INTERFACE_IMUX11" + "BRAM_NE4BEG1_3", + "VBRK_NE4BEG1" ], [ - "DSP_SE4BEG2_4", - "INT_INTERFACE_SE4BEG2" + "BRAM_NE4BEG2_3", + "VBRK_NE4BEG2" ], [ - "DSP_IMUX15_4", - "INT_INTERFACE_IMUX15" + "BRAM_NE4BEG3_3", + "VBRK_NE4BEG3" ], [ - "DSP_BYP0_4", - "INT_INTERFACE_BYP0" + "BRAM_NE4C0_3", + "VBRK_NE4C0" ], [ - "DSP_SW4A0_4", - "INT_INTERFACE_SW4A0" + "BRAM_NE4C1_3", + "VBRK_NE4C1" ], [ - "DSP_IMUX44_4", - "INT_INTERFACE_IMUX44" + "BRAM_NE4C2_3", + "VBRK_NE4C2" ], [ - "DSP_IMUX27_4", - "INT_INTERFACE_IMUX27" + "BRAM_NE4C3_3", + "VBRK_NE4C3" ], [ - "DSP_WW2END2_4", - "INT_INTERFACE_WW2END2" + "BRAM_NW2A0_3", + "VBRK_NW2A0" ], [ - "DSP_LH6_4", - "INT_INTERFACE_LH6" + "BRAM_NW2A1_3", + "VBRK_NW2A1" ], [ - "DSP_IMUX45_4", - "INT_INTERFACE_IMUX45" + "BRAM_NW2A2_3", + "VBRK_NW2A2" ], [ - "DSP_WR1END0_4", - "INT_INTERFACE_WR1END0" + "BRAM_NW2A3_3", + "VBRK_NW2A3" ], [ - "DSP_WW4C2_4", - "INT_INTERFACE_WW4C2" + "BRAM_NW4A0_3", + "VBRK_NW4A0" ], [ - "DSP_NW2A0_4", - "INT_INTERFACE_NW2A0" + "BRAM_NW4A1_3", + "VBRK_NW4A1" ], [ - "DSP_EE4BEG2_4", - "INT_INTERFACE_EE4BEG2" + "BRAM_NW4A2_3", + "VBRK_NW4A2" ], [ - "DSP_LOGIC_OUTS_B23_4", - "INT_INTERFACE_LOGIC_OUTS_B23" + "BRAM_NW4A3_3", + "VBRK_NW4A3" ], [ - "DSP_SW2A3_4", - "INT_INTERFACE_SW2A3" + "BRAM_NW4END0_3", + "VBRK_NW4END0" ], [ - "DSP_WW4B0_4", - "INT_INTERFACE_WW4B0" + "BRAM_NW4END1_3", + "VBRK_NW4END1" ], [ - "DSP_WW4C0_4", - "INT_INTERFACE_WW4C0" + "BRAM_NW4END2_3", + "VBRK_NW4END2" ], [ - "DSP_SE4BEG1_4", - "INT_INTERFACE_SE4BEG1" + "BRAM_NW4END3_3", + "VBRK_NW4END3" ], [ - "DSP_WW2A3_4", - "INT_INTERFACE_WW2A3" + "BRAM_SE2A0_3", + "VBRK_SE2A0" ], [ - "DSP_IMUX16_4", - "INT_INTERFACE_IMUX16" + "BRAM_SE2A1_3", + "VBRK_SE2A1" ], [ - "DSP_WW4END1_4", - "INT_INTERFACE_WW4END1" + "BRAM_SE2A2_3", + "VBRK_SE2A2" ], [ - "DSP_IMUX18_4", - "INT_INTERFACE_IMUX18" + "BRAM_SE2A3_3", + "VBRK_SE2A3" ], [ - "DSP_WL1END2_4", - "INT_INTERFACE_WL1END2" + "BRAM_SE4BEG0_3", + "VBRK_SE4BEG0" ], [ - "DSP_NW4END3_4", - "INT_INTERFACE_NW4END3" + "BRAM_SE4BEG1_3", + "VBRK_SE4BEG1" ], [ - "DSP_NW4A1_4", - "INT_INTERFACE_NW4A1" + "BRAM_SE4BEG2_3", + "VBRK_SE4BEG2" ], [ - "DSP_IMUX21_4", - "INT_INTERFACE_IMUX21" + "BRAM_SE4BEG3_3", + "VBRK_SE4BEG3" ], [ - "DSP_IMUX41_4", - "INT_INTERFACE_IMUX41" + "BRAM_SE4C0_3", + "VBRK_SE4C0" ], [ - "DSP_IMUX24_4", - "INT_INTERFACE_IMUX24" + "BRAM_SE4C1_3", + "VBRK_SE4C1" ], [ - "DSP_ER1BEG3_4", - "INT_INTERFACE_ER1BEG3" + "BRAM_SE4C2_3", + "VBRK_SE4C2" ], [ - "DSP_IMUX29_4", - "INT_INTERFACE_IMUX29" + "BRAM_SE4C3_3", + "VBRK_SE4C3" ], [ - "DSP_NE4C3_4", - "INT_INTERFACE_NE4C3" + "BRAM_SW2A0_3", + "VBRK_SW2A0" ], [ - "DSP_IMUX33_4", - "INT_INTERFACE_IMUX33" + "BRAM_SW2A1_3", + "VBRK_SW2A1" ], [ - "DSP_WR1END1_4", - "INT_INTERFACE_WR1END1" + "BRAM_SW2A2_3", + "VBRK_SW2A2" ], [ - "DSP_EE2A2_4", - "INT_INTERFACE_EE2A2" + "BRAM_SW2A3_3", + "VBRK_SW2A3" ], [ - "DSP_NE4BEG0_4", - "INT_INTERFACE_NE4BEG0" + "BRAM_SW4A0_3", + "VBRK_SW4A0" ], [ - "DSP_IMUX9_4", - "INT_INTERFACE_IMUX9" + "BRAM_SW4A1_3", + "VBRK_SW4A1" ], [ - "DSP_CTRL1_4", - "INT_INTERFACE_CTRL1" + "BRAM_SW4A2_3", + "VBRK_SW4A2" ], [ - "DSP_SW2A2_4", - "INT_INTERFACE_SW2A2" + "BRAM_SW4A3_3", + "VBRK_SW4A3" ], [ - "DSP_WW4B3_4", - "INT_INTERFACE_WW4B3" + "BRAM_SW4END0_3", + "VBRK_SW4END0" ], [ - "DSP_NW4END0_4", - "INT_INTERFACE_NW4END0" + "BRAM_SW4END1_3", + "VBRK_SW4END1" ], [ - "DSP_LOGIC_OUTS_B10_4", - "INT_INTERFACE_LOGIC_OUTS_B10" + "BRAM_SW4END2_3", + "VBRK_SW4END2" ], [ - "DSP_SE4BEG3_4", - "INT_INTERFACE_SE4BEG3" + "BRAM_SW4END3_3", + "VBRK_SW4END3" ], [ - "DSP_EE2A3_4", - "INT_INTERFACE_EE2A3" + "BRAM_WL1END0_3", + "VBRK_WL1END0" ], [ - "DSP_LOGIC_OUTS_B22_4", - "INT_INTERFACE_LOGIC_OUTS_B22" + "BRAM_WL1END1_3", + "VBRK_WL1END1" ], [ - "DSP_EE4B0_4", - "INT_INTERFACE_EE4B0" + "BRAM_WL1END2_3", + "VBRK_WL1END2" ], [ - "DSP_LOGIC_OUTS_B18_4", - "INT_INTERFACE_LOGIC_OUTS_B18" + "BRAM_WL1END3_3", + "VBRK_WL1END3" ], [ - "DSP_IMUX23_4", - "INT_INTERFACE_IMUX23" + "BRAM_WR1END0_3", + "VBRK_WR1END0" ], [ - "DSP_IMUX10_4", - "INT_INTERFACE_IMUX10" + "BRAM_WR1END1_3", + "VBRK_WR1END1" ], [ - "DSP_LOGIC_OUTS_B0_4", - "INT_INTERFACE_LOGIC_OUTS_B0" + "BRAM_WR1END2_3", + "VBRK_WR1END2" ], [ - "DSP_NW4END2_4", - "INT_INTERFACE_NW4END2" + "BRAM_WR1END3_3", + "VBRK_WR1END3" ], [ - "DSP_LH8_4", - "INT_INTERFACE_LH8" + "BRAM_WW2A0_3", + "VBRK_WW2A0" ], [ - "DSP_NE4C0_4", - "INT_INTERFACE_NE4C0" + "BRAM_WW2A1_3", + "VBRK_WW2A1" ], [ - "DSP_LOGIC_OUTS_B14_4", - "INT_INTERFACE_LOGIC_OUTS_B14" + "BRAM_WW2A2_3", + "VBRK_WW2A2" ], [ - "DSP_IMUX20_4", - "INT_INTERFACE_IMUX20" + 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"VBRK_WW2A1" + ], + [ + "BRAM_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "BRAM_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "BRAM_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "BRAM_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "BRAM_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "BRAM_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "BRAM_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "BRAM_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "BRAM_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "BRAM_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "BRAM_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "BRAM_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "BRAM_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "BRAM_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "BRAM_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "BRAM_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "BRAM_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "BRAM_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "BRAM_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "BRAM_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "BRAM_WW4END3_0", + "VBRK_WW4END3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -5 + ], + "tile_types": [ + "BRAM_R", + "BRAM_R" + ], + "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRAM_CASCOUT_ADDRARDADDRU0" ], [ - "DSP_EL1BEG2_4", - "INT_INTERFACE_EL1BEG2" + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRARDADDRU1" ], [ - "DSP_NE2A0_4", - "INT_INTERFACE_NE2A0" + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRAM_CASCOUT_ADDRARDADDRU2" ], [ - "DSP_IMUX28_4", - "INT_INTERFACE_IMUX28" + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRAM_CASCOUT_ADDRARDADDRU3" ], [ - "DSP_IMUX25_4", - "INT_INTERFACE_IMUX25" + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_CASCOUT_ADDRARDADDRU4" ], [ - "DSP_IMUX34_4", - "INT_INTERFACE_IMUX34" + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRAM_CASCOUT_ADDRARDADDRU5" ], [ - "DSP_NE4C1_4", - "INT_INTERFACE_NE4C1" + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRAM_CASCOUT_ADDRARDADDRU6" ], [ - "DSP_EE2BEG1_4", - "INT_INTERFACE_EE2BEG1" + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7" ], [ - "DSP_IMUX39_4", - "INT_INTERFACE_IMUX39" + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRAM_CASCOUT_ADDRARDADDRU8" ], [ - "DSP_FAN2_4", - "INT_INTERFACE_FAN2" + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRARDADDRU9" ], [ - "DSP_EE4A2_4", - "INT_INTERFACE_EE4A2" + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRAM_CASCOUT_ADDRARDADDRU10" ], [ - "DSP_NW2A3_4", - "INT_INTERFACE_NW2A3" + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU11" ], [ - "DSP_IMUX37_4", - "INT_INTERFACE_IMUX37" + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU12" ], [ - "DSP_IMUX12_4", - "INT_INTERFACE_IMUX12" + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU13" ], [ - "DSP_CLK0_4", - "INT_INTERFACE_CLK0" + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_CASCOUT_ADDRARDADDRU14" ], [ - "DSP_WL1END3_4", - "INT_INTERFACE_WL1END3" + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRAM_CASCOUT_ADDRBWRADDRU0" ], [ - "DSP_SE4C0_4", - "INT_INTERFACE_SE4C0" + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU1" ], [ - "DSP_NE2A1_4", - "INT_INTERFACE_NE2A1" + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRAM_CASCOUT_ADDRBWRADDRU2" ], [ - "DSP_NE4C2_4", - "INT_INTERFACE_NE4C2" + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3" ], [ - "DSP_LOGIC_OUTS_B3_4", - "INT_INTERFACE_LOGIC_OUTS_B3" + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRAM_CASCOUT_ADDRBWRADDRU4" ], [ - "DSP_LH11_4", - "INT_INTERFACE_LH11" + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU5" ], [ - "DSP_CLK1_4", - "INT_INTERFACE_CLK1" + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRAM_CASCOUT_ADDRBWRADDRU6" ], [ - "DSP_EE4C2_4", - "INT_INTERFACE_EE4C2" + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRAM_CASCOUT_ADDRBWRADDRU7" ], [ - "DSP_IMUX1_4", - "INT_INTERFACE_IMUX1" + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU8" ], [ - "DSP_WW2A2_4", - "INT_INTERFACE_WW2A2" + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU9" ], [ - "DSP_SE4C3_4", - "INT_INTERFACE_SE4C3" + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRAM_CASCOUT_ADDRBWRADDRU10" ], [ - "DSP_BYP2_4", - "INT_INTERFACE_BYP2" + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRAM_CASCOUT_ADDRBWRADDRU11" ], [ - "DSP_EL1BEG0_4", - "INT_INTERFACE_EL1BEG0" + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRAM_CASCOUT_ADDRBWRADDRU12" ], [ - "DSP_EE2A0_4", - "INT_INTERFACE_EE2A0" + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU13" ], [ - "DSP_EE4A1_4", - "INT_INTERFACE_EE4A1" + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRAM_CASCOUT_ADDRBWRADDRU14" ], [ - "DSP_NE4BEG2_4", - "INT_INTERFACE_NE4BEG2" + "BRAM_PMVBRAM_O", + "BRAM_PMVBRAM_O_1" ], [ - "DSP_FAN5_4", - "INT_INTERFACE_FAN5" + "BRAM_PMVBRAM_ODIV2", + "BRAM_PMVBRAM_ODIV2_1" ], [ - "DSP_FAN0_4", - "INT_INTERFACE_FAN0" + "BRAM_PMVBRAM_O_1", + "BRAM_PMVBRAM_O_2" ] ] }, @@ -2821,1873 +19189,397 @@ 5 ], "tile_types": [ - "CMT_TOP_R_UPPER_B", - "HCLK_CMT" + "BRAM_R", + "BRAM_R" ], "wire_pairs": [ [ - "CMT_PHY_CONTROL_IRANKB1", - "HCLK_CMT_PHY_CONTROL_IRANKB1" + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRAM_CASCOUT_ADDRARDADDRU0" ], [ - "CMT_PHY_CONTROL_OBURSTPENDING1", - "HCLK_CMT_OBURSTPENDING1" + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRARDADDRU1" ], [ - "CMT_PHASER_UP_PHASERREF_BELOW1", - "HCLK_CMT_PHASEREF_BELOW1" + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRAM_CASCOUT_ADDRARDADDRU2" ], [ - "CMT_PHASER_TOP_SYNC_BB", - "HCLK_CMT_PHY_SYNC_BB" + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRAM_CASCOUT_ADDRARDADDRU3" ], [ - "CMT_R_TOP_UPPER_B_CLKPLL2", - "HCLK_CMT_MUX_CLK_PLL2" + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRAM_CASCOUT_ADDRARDADDRU4" ], [ - "CMT_PHY_CONTROL_OBURSTPENDING0", - "HCLK_CMT_OBURSTPENDING0" + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRAM_CASCOUT_ADDRARDADDRU5" ], [ - "CMT_PHY_CONTROL_IBURSTPENDING1", - "HCLK_CMT_IBURSTPENDING1" + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRAM_CASCOUT_ADDRARDADDRU6" ], [ - "CMT_R_TOP_UPPER_B_CLKIN2", - "HCLK_CMT_MUX_PLLE2_CLKIN2" + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7" ], [ - "CMT_PHASER_OUT_C_OCLK", - "HCLK_CMT_PHASEROUTC_OCLK" + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRAM_CASCOUT_ADDRARDADDRU8" ], [ - "CMT_R_TOP_UPPER_B_CLKINT_2", - "HCLK_CMT_MUX_CLKINT_2" + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRARDADDRU9" ], [ - "CMT_PHASER_IN_C_ICLK", - "HCLK_CMT_PHASERINC_ICLK" + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRAM_CASCOUT_ADDRARDADDRU10" ], [ - "CMT_PHASER_IN_C_RCLK2", - "HCLK_CMT_PHASERIN_RCLK2" + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU11" ], [ - "PLL_CLK_FREQBB_REBUFOUT1", - "HCLK_CMT_FREQ_REF_NS1" + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU12" ], [ - "CMT_PHASER_OUT_C_OCLKDIV", - "HCLK_CMT_PHASEROUTC_OCLKDIV" + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU13" ], [ - "CMT_FREQ_PHASER_REFMUX_1", - "HCLK_CMT_FREQ_PHASER_REFMUX_1" + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRAM_CASCOUT_ADDRARDADDRU14" ], [ - "PLL_CLK_FREQBB_REBUFOUT3", - "HCLK_CMT_FREQ_REF_NS3" + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRAM_CASCOUT_ADDRBWRADDRU0" ], [ - "CMT_PHASER_OUT_D_OCLKDIV", - "HCLK_CMT_PHASEROUTD_OCLKDIV" + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU1" ], [ - "CMT_PHASER_UP_PHASERREF1", - "HCLK_CMT_BUFMR_PHASEREF1" + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRAM_CASCOUT_ADDRBWRADDRU2" ], [ - "CMT_R_TOP_UPPER_B_CLKPLL0", - "HCLK_CMT_MUX_CLK_PLL0" + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3" ], [ - "CMT_FREQ_PHASER_REFMUX_0", - "HCLK_CMT_FREQ_PHASER_REFMUX_0" + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRAM_CASCOUT_ADDRBWRADDRU4" ], [ - "CMT_PHY_CONTROL_IRANKA0", - "HCLK_CMT_PHY_CONTROL_IRANKA0" + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU5" ], [ - "PLL_CLK_FREQBB_REBUFOUT2", - "HCLK_CMT_FREQ_REF_NS2" + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRAM_CASCOUT_ADDRBWRADDRU6" ], [ - "CMT_PHASER_UP_BUFMRCE_CE0", - "HCLK_CMT_BUFMR_CE0" + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRAM_CASCOUT_ADDRBWRADDRU7" ], [ - "CMT_PHY_CONTROL_IBURSTPENDING0", - "HCLK_CMT_IBURSTPENDING0" + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU8" ], [ - "CMT_PHY_CONTROL_ECALIB0", - "HCLK_CMT_ECALIB0" + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU9" ], [ - "CMT_PHASER_OUT_D_OCLK", - "HCLK_CMT_PHASEROUTD_OCLK" + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRAM_CASCOUT_ADDRBWRADDRU10" ], [ - "CMT_PHASER_UP_PHASERREF_ABOVE0", - "HCLK_CMT_PHASEREF_ABOVE0" + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRAM_CASCOUT_ADDRBWRADDRU11" ], [ - "CMT_PHASER_UP_PHASERREF_BELOW0", - "HCLK_CMT_PHASEREF_BELOW0" + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRAM_CASCOUT_ADDRBWRADDRU12" ], [ - "CMT_PHASER_IN_D_ICLKDIV", - "HCLK_CMT_PHASERIND_ICLKDIV" + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU13" ], [ - "CMT_R_TOP_UPPER_B_CLKPLL4", - "HCLK_CMT_MUX_CLK_PLL4" + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRAM_CASCOUT_ADDRBWRADDRU14" ], [ - "CMT_R_TOP_UPPER_B_CLKINT_3", - "HCLK_CMT_MUX_CLKINT_3" + "BRAM_FIFO36_CASCADEINA", + "BRAM_FIFO36_CASCADEOUTA_1" ], [ - "CMT_PHASER_IN_D_RCLK3", - "HCLK_CMT_PHASERIN_RCLK3" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL3", - "HCLK_CMT_MUX_CLK_PLL3" - ], - [ - "CMT_PHASER_IN_C_ICLKDIV", - "HCLK_CMT_PHASERINC_ICLKDIV" - ], - [ - "CMT_PHASER_REF_CLKOUT_TOHCLK", - "HCLK_CMT_PREF_CLKOUT" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL5", - "HCLK_CMT_MUX_CLK_PLL5" - ], - [ - "CMT_PHASER_IN_D_ICLK", - "HCLK_CMT_PHASERIND_ICLK" - ], - [ - "CMT_R_TOP_UPPER_B_CLKIN1", - "HCLK_CMT_MUX_PLLE2_CLKIN1" - ], - [ - "CMT_PHY_CONTROL_IRANKA1", - "HCLK_CMT_PHY_CONTROL_IRANKA1" - ], - [ - "CMT_FREQ_PHASER_REFMUX_2", - "HCLK_CMT_FREQ_PHASER_REFMUX_2" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL7", - "HCLK_CMT_MUX_CLK_PLL7" - ], - [ - "CMT_PHY_CONTROL_ECALIB1", - "HCLK_CMT_ECALIB1" - ], - [ - "CMT_PHASER_UP_BUFMRCE_CE1", - "HCLK_CMT_BUFMR_CE1" - ], - [ - "CMT_PHASER_UP_PHASERREF0", - "HCLK_CMT_BUFMR_PHASEREF0" - ], - [ - "CMT_PHASER_UP_PHASERREF_ABOVE1", - "HCLK_CMT_PHASEREF_ABOVE1" - ], - [ - "PLL_CLK_FREQBB_REBUFOUT0", - "HCLK_CMT_FREQ_REF_NS0" - ], - [ - "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "HCLK_CMT_PREF_TMUXOUT" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL1", - "HCLK_CMT_MUX_CLK_PLL1" - ], - [ - "CMT_PHASER_OUT_C_OCLK1X_90", - "HCLK_CMT_PHASEROUTC_OCLK1X_90" - ], - [ - "CMT_R_TOP_UPPER_B_CLKFBIN", - "HCLK_CMT_MUX_PLLE2_CLKFBIN" - ], - [ - "CMT_PHY_CONTROL_IRANKB0", - "HCLK_CMT_PHY_CONTROL_IRANKB0" - ], - [ - "CMT_PHASER_OUT_D_OCLK1X_90", - "HCLK_CMT_PHASEROUTD_OCLK1X_90" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL6", - "HCLK_CMT_MUX_CLK_PLL6" + "BRAM_FIFO36_CASCADEINB", + "BRAM_FIFO36_CASCADEOUTB_1" ] ] }, { "grid_deltas": [ - -1, - -8 + 0, + -5 ], "tile_types": [ - "CMT_PMV_L", - "CMT_TOP_L_LOWER_B" + "BRAM_R", + "BRKH_BRAM" ], "wire_pairs": [ [ - "CMT_PMV_WW4C0", - "CMT_TOP_WW4C0_0" + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ - "CMT_PMV_IMUX18", - "CMT_TOP_IMUX18_0" + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ - "CMT_PMV_IMUX11", - "CMT_TOP_IMUX11_0" + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ - "CMT_PMV_IMUX3", - "CMT_TOP_IMUX3_0" + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ - "CMT_PMV_LH9", - "CMT_TOP_LH9_0" + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ - "CMT_PMV_FAN0", - "CMT_TOP_FAN0_0" + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ - "CMT_PMV_NW4END3", - "CMT_TOP_NW4END3_0" + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ - "CMT_PMV_IMUX5", - "CMT_TOP_IMUX5_0" + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ - "CMT_PMV_WL1END1", - "CMT_TOP_WL1END1_0" + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ - "CMT_PMV_SE4BEG2", - "CMT_TOP_SE4BEG2_0" + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ - "CMT_PMV_EL1BEG0", - "CMT_TOP_EL1BEG0_0" + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ - "CMT_PMV_EE2A3", - "CMT_TOP_EE2A3_0" + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ - "CMT_PMV_WW4C3", - "CMT_TOP_WW4C3_0" + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ - "CMT_PMV_EL1BEG2", - "CMT_TOP_EL1BEG2_0" + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ - "CMT_PMV_WW2A3", - "CMT_TOP_WW2A3_0" + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ - "CMT_PMV_NE2A2", - "CMT_TOP_NE2A2_0" + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ - "CMT_PMV_IMUX32", - "CMT_TOP_IMUX32_0" + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ - "CMT_PMV_EE4A0", - "CMT_TOP_EE4A0_0" + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ - "CMT_PMV_LOGIC_OUTS18", - "CMT_TOP_LOGIC_OUTS_L_B18_0" + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ - "CMT_PMV_FAN7", - "CMT_TOP_FAN7_0" + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ - "CMT_PMV_IMUX47", - "CMT_TOP_IMUX47_0" + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ - "CMT_PMV_NE2A0", - "CMT_TOP_NE2A0_0" + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ - "CMT_PMV_EE4BEG1", - "CMT_TOP_EE4BEG1_0" + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ - "CMT_PMV_SW2A1", - "CMT_TOP_SW2A1_0" + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ - "CMT_PMV_IMUX43", - "CMT_TOP_IMUX43_0" + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ - "CMT_PMV_EE4B1", - "CMT_TOP_EE4B1_0" + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ - "CMT_PMV_IMUX20", - "CMT_TOP_IMUX20_0" + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ - "CMT_PMV_IMUX4", - "CMT_TOP_IMUX4_0" + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ - "CMT_PMV_WW4B3", - "CMT_TOP_WW4B3_0" + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ - "CMT_PMV_EE2BEG1", - "CMT_TOP_EE2BEG1_0" + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ - "CMT_PMV_LH12", - "CMT_TOP_LH12_0" + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ - "CMT_PMV_BYP2", - "CMT_TOP_BYP2_0" + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ - "CMT_PMV_EE4BEG2", - "CMT_TOP_EE4BEG2_0" + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ - "CMT_PMV_IMUX45", - "CMT_TOP_IMUX45_0" + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ - "CMT_PMV_IMUX22", - "CMT_TOP_IMUX22_0" + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ - "CMT_PMV_BYP3", - "CMT_TOP_BYP3_0" + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ - "CMT_PMV_SE4C0", - "CMT_TOP_SE4C0_0" + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ - "CMT_PMV_EE4A3", - "CMT_TOP_EE4A3_0" + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ - "CMT_PMV_WR1END2", - "CMT_TOP_WR1END2_0" + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ - "CMT_PMV_NE4C1", - "CMT_TOP_NE4C1_0" + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ - "CMT_PMV_WL1END3", - "CMT_TOP_WL1END3_0" + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ - "CMT_PMV_LH11", - "CMT_TOP_LH11_0" + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ - "CMT_PMV_BYP7", - "CMT_TOP_BYP7_0" + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ - "CMT_PMV_WW4END2", - "CMT_TOP_WW4END2_0" + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ - "CMT_PMV_IMUX25", - "CMT_TOP_IMUX25_0" + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ - "CMT_PMV_IMUX21", - "CMT_TOP_IMUX21_0" + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ - "CMT_PMV_LOGIC_OUTS13", - "CMT_TOP_LOGIC_OUTS_L_B13_0" + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ - "CMT_PMV_LH8", - "CMT_TOP_LH8_0" + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ - "CMT_PMV_ER1BEG3", - "CMT_TOP_ER1BEG3_0" + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ - "CMT_PMV_IMUX8", - "CMT_TOP_IMUX8_0" + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ - "CMT_PMV_NE2A3", - "CMT_TOP_NE2A3_0" + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ - "CMT_PMV_EE4C2", - "CMT_TOP_EE4C2_0" + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ - "CMT_PMV_IMUX24", - "CMT_TOP_IMUX24_0" + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ - "CMT_PMV_WW4A1", - "CMT_TOP_WW4A1_0" + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ - "CMT_PMV_IMUX35", - "CMT_TOP_IMUX35_0" + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ - "CMT_PMV_IMUX19", - "CMT_TOP_IMUX19_0" + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ - "CMT_PMV_BYP4", - "CMT_TOP_BYP4_0" + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ - "CMT_PMV_LH10", - "CMT_TOP_LH10_0" + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ - "CMT_PMV_ER1BEG0", - "CMT_TOP_ER1BEG0_0" + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ - "CMT_PMV_LOGIC_OUTS2", - "CMT_TOP_LOGIC_OUTS_L_B2_0" + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ - "CMT_PMV_EE4C0", - "CMT_TOP_EE4C0_0" + "BRAM_FIFO36_CASCADEOUTA_1", + "BRKH_BRAM_CASCADEA_R" ], [ - "CMT_PMV_EE4A1", - "CMT_TOP_EE4A1_0" - ], - [ - "CMT_PMV_IMUX38", - "CMT_TOP_IMUX38_0" - ], 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"CMT_PMV_SW4END1", - "CMT_TOP_SW4END1_0" - ], - [ - "CMT_PMV_EE4BEG3", - "CMT_TOP_EE4BEG3_0" - ], - [ - "CMT_PMV_IMUX36", - "CMT_TOP_IMUX36_0" - ], - [ - "CMT_PMV_NW4A1", - "CMT_TOP_NW4A1_0" - ], - [ - "CMT_PMV_NW2A0", - "CMT_TOP_NW2A0_0" - ], - [ - "CMT_PMV_IMUX31", - "CMT_TOP_IMUX31_0" - ], - [ - "CMT_PMV_LOGIC_OUTS16", - "CMT_TOP_LOGIC_OUTS_L_B16_0" - ], - [ - "CMT_PMV_LOGIC_OUTS5", - "CMT_TOP_LOGIC_OUTS_L_B5_0" - ], - [ - "CMT_PMV_SE4C3", - "CMT_TOP_SE4C3_0" - ], - [ - "CMT_PMV_FAN3", - "CMT_TOP_FAN3_0" - ], - [ - "CMT_PMV_EE4B3", - "CMT_TOP_EE4B3_0" - ], - [ - "CMT_PMV_NE4BEG0", - "CMT_TOP_NE4BEG0_0" - ], - [ - "CMT_PMV_BYP6", - "CMT_TOP_BYP6_0" - ], - [ - "CMT_PMV_SW2A3", - "CMT_TOP_SW2A3_0" - ], - [ - "CMT_PMV_LH6", - "CMT_TOP_LH6_0" - ], - [ - "CMT_PMV_LOGIC_OUTS23", - "CMT_TOP_LOGIC_OUTS_L_B23_0" - ], - [ - "CMT_PMV_WW2A0", - "CMT_TOP_WW2A0_0" - ], - [ - "CMT_PMV_FAN2", - "CMT_TOP_FAN2_0" - ], - [ - "CMT_PMV_EE2BEG2", - "CMT_TOP_EE2BEG2_0" - ], - [ - "CMT_PMV_SE2A1", - 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"CMT_PMV_EE4C1", - "CMT_TOP_EE4C1_0" - ], - [ - "L_TERM_INT_PHASER_TO_IO_OCLKDIV", - "CMT_TOP_OCLKDIV_0" - ], - [ - "CMT_PMV_NW4A3", - "CMT_TOP_NW4A3_0" - ], - [ - "CMT_PMV_IMUX41", - "CMT_TOP_IMUX41_0" - ], - [ - "CMT_PMV_SW4A3", - "CMT_TOP_SW4A3_0" - ], - [ - "CMT_PMV_IMUX6", - "CMT_TOP_IMUX6_0" - ], - [ - "CMT_PMV_EE2BEG3", - "CMT_TOP_EE2BEG3_0" - ], - [ - "CMT_PMV_EE4BEG0", - "CMT_TOP_EE4BEG0_0" - ], - [ - "CMT_PMV_CTRL0", - "CMT_TOP_CTRL0_0" - ], - [ - "CMT_PMV_WW4B1", - "CMT_TOP_WW4B1_0" - ], - [ - "CMT_PMV_EE2BEG0", - "CMT_TOP_EE2BEG0_0" - ], - [ - "CMT_PMV_EL1BEG1", - "CMT_TOP_EL1BEG1_0" - ], - [ - "CMT_PMV_LOGIC_OUTS8", - "CMT_TOP_LOGIC_OUTS_L_B8_0" - ], - [ - "CMT_PMV_EE4A2", - "CMT_TOP_EE4A2_0" - ], - [ - "CMT_PMV_IMUX12", - "CMT_TOP_IMUX12_0" - ], - [ - "CMT_PMV_EE2A2", - "CMT_TOP_EE2A2_0" - ], - [ - "CMT_PMV_FAN4", - "CMT_TOP_FAN4_0" - ], - [ - "CMT_PMV_LH4", - "CMT_TOP_LH4_0" - ], - [ - "CMT_PMV_LOGIC_OUTS19", - "CMT_TOP_LOGIC_OUTS_L_B19_0" - ], - [ - "CMT_PMV_IMUX37", - "CMT_TOP_IMUX37_0" - ], - [ - "CMT_PMV_WW2A1", - "CMT_TOP_WW2A1_0" - ], - [ - "CMT_PMV_NE4C3", - "CMT_TOP_NE4C3_0" - ], - [ - "CMT_PMV_EE2A1", - "CMT_TOP_EE2A1_0" - ], - [ - "CMT_PMV_NW2A1", - "CMT_TOP_NW2A1_0" - ], - [ - "CMT_PMV_SW4A0", - "CMT_TOP_SW4A0_0" - ], - [ - "CMT_PMV_IMUX28", - "CMT_TOP_IMUX28_0" - ], - [ - "CMT_PMV_IMUX26", - "CMT_TOP_IMUX26_0" - ], - [ - "CMT_PMV_WW4B0", - "CMT_TOP_WW4B0_0" - ], - [ - "CMT_PMV_SE4BEG1", - "CMT_TOP_SE4BEG1_0" - ], - [ - "CMT_PMV_IMUX42", - "CMT_TOP_IMUX42_0" - ], - [ - "CMT_PMV_IMUX27", - "CMT_TOP_IMUX27_0" - ], - [ - "CMT_PMV_SE2A2", - "CMT_TOP_SE2A2_0" - ], - [ - "CMT_PMV_SE2A0", - "CMT_TOP_SE2A0_0" - ], - [ - "CMT_PMV_WW4A3", - "CMT_TOP_WW4A3_0" - ], - [ - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "CMT_TOP_ICLKDIV_0" - ], - [ - "CMT_PMV_NE4BEG1", - "CMT_TOP_NE4BEG1_0" - ], - [ - "CMT_PMV_IMUX40", - "CMT_TOP_IMUX40_0" - ], - [ - "CMT_PMV_WR1END1", - "CMT_TOP_WR1END1_0" - ], - [ - "CMT_PMV_LOGIC_OUTS10", - "CMT_TOP_LOGIC_OUTS_L_B10_0" - ], - [ - "CMT_PMV_IMUX15", - "CMT_TOP_IMUX15_0" - ], - [ - "CMT_PMV_NW4END0", - "CMT_TOP_NW4END0_0" - ], - [ - "CMT_PMV_IMUX34", - "CMT_TOP_IMUX34_0" - ], - [ - "CMT_PMV_WW4C1", - "CMT_TOP_WW4C1_0" - ], - [ - "CMT_PMV_EL1BEG3", - "CMT_TOP_EL1BEG3_0" - ], - [ - "CMT_PMV_IMUX44", - "CMT_TOP_IMUX44_0" - ], - [ - "CMT_PMV_WW4END3", - "CMT_TOP_WW4END3_0" - ], - [ - "CMT_PMV_NW4END1", - "CMT_TOP_NW4END1_0" - ], - [ - "CMT_PMV_WW2END2", - "CMT_TOP_WW2END2_0" - ], - [ - "CMT_PMV_CTRL1", - "CMT_TOP_CTRL1_0" - ], - [ - "CMT_PMV_IMUX39", - "CMT_TOP_IMUX39_0" - ], - [ - "CMT_PMV_LH7", - "CMT_TOP_LH7_0" - ], - [ - "CMT_PMV_IMUX33", - "CMT_TOP_IMUX33_0" - ], - [ - "CMT_PMV_LH2", - "CMT_TOP_LH2_0" - ], - [ - "CMT_PMV_SE4BEG0", - "CMT_TOP_SE4BEG0_0" - ], - [ - "CMT_PMV_LOGIC_OUTS20", - "CMT_TOP_LOGIC_OUTS_L_B20_0" - ], - [ - "CMT_PMV_LOGIC_OUTS22", - "CMT_TOP_LOGIC_OUTS_L_B22_0" - ], - [ - "CMT_PMV_SW4END2", - "CMT_TOP_SW4END2_0" - ], - [ - "CMT_PMV_WW4END1", - "CMT_TOP_WW4END1_0" - ], - [ - "L_TERM_INT_PHASER_TO_IO_OCLK", - "CMT_TOP_OCLK_0" - ], - [ - "CMT_PMV_EE4B2", - "CMT_TOP_EE4B2_0" - ], - [ - "CMT_PMV_NW2A2", - "CMT_TOP_NW2A2_0" - ], - [ - "CMT_PMV_FAN6", - "CMT_TOP_FAN6_0" - ], - [ - "CMT_PMV_NE4BEG3", - "CMT_TOP_NE4BEG3_0" - ], - [ - "CMT_PMV_NE2A1", - "CMT_TOP_NE2A1_0" - ], - [ - "CMT_PMV_LOGIC_OUTS15", - "CMT_TOP_LOGIC_OUTS_L_B15_0" - ], - [ - "CMT_PMV_IMUX1", - "CMT_TOP_IMUX1_0" - ], - [ - "CMT_PMV_SW4END0", - "CMT_TOP_SW4END0_0" - ], - [ - "CMT_PMV_SW4END3", - "CMT_TOP_SW4END3_0" - ], - [ - "CMT_PMV_SE4C1", - "CMT_TOP_SE4C1_0" - ], - [ - "CMT_PMV_IMUX2", - "CMT_TOP_IMUX2_0" - ], - [ - "CMT_PMV_IMUX16", - "CMT_TOP_IMUX16_0" - ], - [ - "CMT_PMV_WW2END0", - "CMT_TOP_WW2END0_0" - ], - [ - "CMT_PMV_WW4END0", - "CMT_TOP_WW4END0_0" - ], - [ - "CMT_PMV_LH1", - "CMT_TOP_LH1_0" - ], - [ - "CMT_PMV_IMUX10", - "CMT_TOP_IMUX10_0" - ], - [ - "CMT_PMV_SE2A3", - "CMT_TOP_SE2A3_0" - ], - [ - "CMT_PMV_NW4A2", - "CMT_TOP_NW4A2_0" - ], - [ - "CMT_PMV_IMUX7", - "CMT_TOP_IMUX7_0" - ], - [ - "CMT_PMV_NW4A0", - "CMT_TOP_NW4A0_0" - ], - [ - "CMT_PMV_WW4A0", - "CMT_TOP_WW4A0_0" - ], - [ - "CMT_PMV_SW4A1", - "CMT_TOP_SW4A1_0" - ], - [ - "CMT_PMV_CLK1", - "CMT_TOP_CLK1_0" - ], - [ - "CMT_PMV_IMUX17", - "CMT_TOP_IMUX17_0" - ], - [ - "CMT_PMV_WR1END0", - "CMT_TOP_WR1END0_0" - ], - [ - "CMT_PMV_LH5", - "CMT_TOP_LH5_0" - ], - [ - "CMT_PMV_IMUX29", - "CMT_TOP_IMUX29_0" - ], - [ - "CMT_PMV_WL1END2", - "CMT_TOP_WL1END2_0" - ], - [ - "CMT_PMV_CLK0", - "CMT_TOP_CLK0_0" - ], - [ - "CMT_PMV_IMUX30", - "CMT_TOP_IMUX30_0" - ], - [ - "CMT_PMV_IMUX9", - "CMT_TOP_IMUX9_0" - ], - [ - "CMT_PMV_BYP5", - "CMT_TOP_BYP5_0" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_PMV2_SVT", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_FEED_EE2BEG1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_FEED_NW4END3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_PMV_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_FEED_WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_LOGIC_OUTS9_0", - "INT_INTERFACE_LOGIC_OUTS_B9" - ], - [ - "CLK_FEED_EE4BEG1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_FEED_NE2A3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_PMV_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_NE2A2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_FEED_WW4B2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_FEED_NW4A2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_PMV_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_FEED_WR1END0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_FEED_NE4C3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_FEED_EE4A2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_FEED_EL1BEG1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_FEED_NE4C0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_PMV_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_FEED_WL1END2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_FEED_NW2A2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_PMV_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_FEED_NW4END1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_FEED_LH7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_FEED_SW4A3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_PMV_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_PMV_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_FEED_WW4END3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_FEED_WR1END1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_PMV_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_FEED_SE4C0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_FEED_EE4B3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_FEED_SW4A1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_FEED_LH9", - "INT_INTERFACE_LH9" - ], - [ - "CLK_PMV_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_FEED_NW2A1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_FEED_EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_FEED_SW4END1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_FEED_NE4C1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_FEED_SW2A1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_FEED_SW4END3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_FEED_SE4C1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_FEED_LH3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_PMV_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_FEED_WR1END2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_FEED_SE4BEG3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_FEED_LH1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_PMV_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_PMV_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_FEED_NW4A1", - "INT_INTERFACE_NW4A1" - ], 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"CLK_PMV_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_FEED_EL1BEG0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_FEED_EE4B1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_FEED_SE4BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_PMV_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_FEED_WW4B1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_FEED_EE2BEG0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_FEED_WW4C2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_FEED_ER1BEG2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_FEED_LH2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_FEED_SE4BEG1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_PMV_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_PMV_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_FEED_EE4A3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_FEED_EL1BEG3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_FEED_LH4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_FEED_LH5", - "INT_INTERFACE_LH5" - ], - [ - "CLK_FEED_SE2A3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_PMV_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_FEED_WW4A3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_FEED_LH11", - "INT_INTERFACE_LH11" - ], - [ - "CLK_FEED_SE2A0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_FEED_NW4A3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_FEED_WW4END1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_FEED_EL1BEG2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_FEED_WL1END1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_FEED_SW4A0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_FEED_WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_FEED_SW4END2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_PMV_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_FEED_WW2END2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_FEED_WL1END3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_FEED_WR1END3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_FEED_SE4C3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_FEED_LH8", - "INT_INTERFACE_LH8" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_SE2A1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_FEED_EE4B2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_FEED_NW4END0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_FEED_EE4B0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_FEED_EE2BEG3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_FEED_SW2A0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_FEED_WW4C1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_FEED_WW4B0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_PMV_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_FEED_SE4C2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_FEED_SW2A2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_FEED_EE2A1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_FEED_ER1BEG0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_FEED_WW4A2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_FEED_EE4A0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_PMV_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_LOGIC_OUTS19_0", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_FEED_NE4C2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_FEED_NW4END2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_FEED_EE2A0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_FEED_NE4BEG1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_FEED_WW2A3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_FEED_SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_FEED_WW4END0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_FEED_WW2A2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_FEED_EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_FEED_NE4BEG2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_PMV_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_FEED_WW4C0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_FEED_SE4BEG2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_FEED_NW2A3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_FEED_EE2BEG2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_FEED_WW2END1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_FEED_NE4BEG3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_FEED_WW2A1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_FEED_EE4BEG3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_FEED_NE4BEG0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_PMV_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_FEED_EE4BEG0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_FEED_WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_PMV_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_FEED_SE2A2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_FEED_EE4BEG2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_PMV_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_FEED_SW4A2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_FEED_NW4A0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_FEED_NW2A0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_FEED_LH10", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_PMV_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_FEED_EE4C0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_FEED_EE2A3", - "INT_INTERFACE_EE2A3" + "BRAM_FIFO36_CASCADEOUTB_1", + "BRKH_BRAM_CASCADEB_R" ] ] }, @@ -4697,13297 +19589,1321 @@ 1 ], "tile_types": [ - "BRKH_CLB", - "CLBLM_R" + "BRAM_R", + "BRKH_BRAM" ], "wire_pairs": [ [ - "BRKH_CLB_COUT1_R", - "CLBLM_M_COUT_N" + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ - "BRKH_CLB_COUT0_R", - "CLBLM_L_COUT_N" + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_FIFO36_CASCADEINA", + "BRKH_BRAM_CASCADEA_R" + ], + [ + "BRAM_FIFO36_CASCADEINB", + "BRKH_BRAM_CASCADEB_R" ] ] }, { "grid_deltas": [ - -1, - -3 + 0, + -5 ], "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" + "BRAM_R", + "HCLK_BRAM" ], "wire_pairs": [ [ - "CLK_PMV_WW2END2_3", - "INT_INTERFACE_WW2END2" + "BRAM_CASCINTOP_ADDRARDADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ - "CLK_PMV_EE4C2_3", - "INT_INTERFACE_EE4C2" + "BRAM_CASCINTOP_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ - "CLK_PMV_EE2A0_3", - "INT_INTERFACE_EE2A0" + "BRAM_CASCINTOP_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ - "CLK_PMV_EE4C0_3", - "INT_INTERFACE_EE4C0" + "BRAM_CASCINTOP_ADDRARDADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ - "CLK_PMV_WW4END2_3", - "INT_INTERFACE_WW4END2" + "BRAM_CASCINTOP_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ - "CLK_PMV_LH4_3", - "INT_INTERFACE_LH4" + "BRAM_CASCINTOP_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ - "CLK_PMV_NE4C0_3", - "INT_INTERFACE_NE4C0" + "BRAM_CASCINTOP_ADDRARDADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ - "CLK_PMV_NE4C1_3", - "INT_INTERFACE_NE4C1" + "BRAM_CASCINTOP_ADDRARDADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ - "CLK_PMV_WL1END0_3", - "INT_INTERFACE_WL1END0" + "BRAM_CASCINTOP_ADDRARDADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ - "CLK_PMV_IMUX11_3", - "INT_INTERFACE_IMUX11" + "BRAM_CASCINTOP_ADDRARDADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ - "CLK_PMV_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" + "BRAM_CASCINTOP_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ - "CLK_PMV_WR1END2_3", - "INT_INTERFACE_WR1END2" + "BRAM_CASCINTOP_ADDRARDADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ - "CLK_PMV_EE2A2_3", - "INT_INTERFACE_EE2A2" + "BRAM_CASCINTOP_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ - "CLK_PMV_EE4A3_3", - "INT_INTERFACE_EE4A3" + "BRAM_CASCINTOP_ADDRARDADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ - "CLK_PMV_SE4BEG2_3", - "INT_INTERFACE_SE4BEG2" + "BRAM_CASCINTOP_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ - "CLK_PMV_IMUX18_3", - "INT_INTERFACE_IMUX18" + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ - "CLK_PMV_IMUX46_3", - "INT_INTERFACE_IMUX46" + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ - "CLK_PMV_WW2A1_3", - "INT_INTERFACE_WW2A1" + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ - "CLK_PMV_IMUX17_3", - "INT_INTERFACE_IMUX17" + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ - "CLK_PMV_EE4BEG0_3", - "INT_INTERFACE_EE4BEG0" + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ - "CLK_PMV_IMUX43_3", - "INT_INTERFACE_IMUX43" + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ - "CLK_PMV_WW2A0_3", - "INT_INTERFACE_WW2A0" + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ - "CLK_PMV_IMUX3_3", - "INT_INTERFACE_IMUX3" + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ - "CLK_PMV_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ - "CLK_PMV_IMUX25_3", - "INT_INTERFACE_IMUX25" + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ - "CLK_PMV_WW4A1_3", - "INT_INTERFACE_WW4A1" + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ - "CLK_PMV_IMUX40_3", - "INT_INTERFACE_IMUX40" + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ - "CLK_PMV_BYP1_3", - "INT_INTERFACE_BYP1" + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ - "CLK_PMV_SW4A3_3", - "INT_INTERFACE_SW4A3" + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ - "CLK_PMV_WW4B0_3", - "INT_INTERFACE_WW4B0" + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ - "CLK_PMV_LH7_3", - "INT_INTERFACE_LH7" + "BRAM_CASCOUT_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ - "CLK_PMV_NE2A0_3", - "INT_INTERFACE_NE2A0" + "BRAM_CASCOUT_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ - "CLK_PMV_SE4C1_3", - "INT_INTERFACE_SE4C1" + "BRAM_CASCOUT_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ - "CLK_PMV_SW4A0_3", - "INT_INTERFACE_SW4A0" + "BRAM_CASCOUT_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ - "CLK_PMV_IMUX16_3", - "INT_INTERFACE_IMUX16" + "BRAM_CASCOUT_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ - "CLK_PMV_IMUX20_3", - "INT_INTERFACE_IMUX20" + "BRAM_CASCOUT_ADDRARDADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ - "CLK_PMV_IMUX39_3", - "INT_INTERFACE_IMUX39" + "BRAM_CASCOUT_ADDRARDADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ - "CLK_PMV_IMUX31_3", - "INT_INTERFACE_IMUX31" + "BRAM_CASCOUT_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ - "CLK_PMV_NE2A2_3", - "INT_INTERFACE_NE2A2" + "BRAM_CASCOUT_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ - "CLK_PMV_WW4C1_3", - "INT_INTERFACE_WW4C1" + "BRAM_CASCOUT_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ - "CLK_PMV_SW2A0_3", - "INT_INTERFACE_SW2A0" + "BRAM_CASCOUT_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ - "CLK_PMV_IMUX4_3", - "INT_INTERFACE_IMUX4" + "BRAM_CASCOUT_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ - "CLK_PMV_WW4B2_3", - "INT_INTERFACE_WW4B2" + "BRAM_CASCOUT_ADDRARDADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ - "CLK_PMV_EE4A1_3", - "INT_INTERFACE_EE4A1" + "BRAM_CASCOUT_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ - "CLK_PMV_WW4END0_3", - "INT_INTERFACE_WW4END0" + "BRAM_CASCOUT_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ - "CLK_PMV_EE4A0_3", - "INT_INTERFACE_EE4A0" + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ - "CLK_PMV_IMUX1_3", - "INT_INTERFACE_IMUX1" + "BRAM_CASCOUT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ - "CLK_PMV_LH11_3", - "INT_INTERFACE_LH11" + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ - "CLK_PMV_IMUX8_3", - "INT_INTERFACE_IMUX8" + "BRAM_CASCOUT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ - "CLK_PMV_WW4END3_3", - "INT_INTERFACE_WW4END3" + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ - "CLK_PMV_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ - "CLK_PMV_IMUX41_3", - "INT_INTERFACE_IMUX41" + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ - "CLK_PMV_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" + "BRAM_CASCOUT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ - "CLK_PMV_IMUX19_3", - "INT_INTERFACE_IMUX19" + "BRAM_CASCOUT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ - "CLK_PMV_WR1END0_3", - "INT_INTERFACE_WR1END0" + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ - "CLK_PMV_IMUX36_3", - "INT_INTERFACE_IMUX36" + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ - "CLK_PMV_LH12_3", - "INT_INTERFACE_LH12" + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ - "CLK_PMV_BYP4_3", - "INT_INTERFACE_BYP4" + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ - "CLK_PMV_IMUX15_3", - "INT_INTERFACE_IMUX15" + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ - "CLK_PMV_SW4END1_3", - "INT_INTERFACE_SW4END1" + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ - "CLK_PMV_IMUX22_3", - "INT_INTERFACE_IMUX22" + "BRAM_FIFO36_CASCADEOUTA_1", + "HCLK_BRAM_CASCADEA_R" ], [ - "CLK_PMV_IMUX30_3", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_PMV_WW2END0_3", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_PMV_NW2A0_3", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_PMV_WW2END1_3", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_PMV_NW2A1_3", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_EE4B3_3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_NE4C2_3", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_PMV_SE2A3_3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_PMV_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_PMV_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_PMV_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_PMV_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_PMV_SE4C0_3", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_PMV_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_PMV_BYP7_3", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_WR1END1_3", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_PMV_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_PMV_SW2A1_3", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_PMV_LOGIC_OUTS1_3", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_PMV_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_PMV_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_NE4BEG3_3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_SE2A2_3", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_IMUX45_3", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_IMUX37_3", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_PMV_IMUX38_3", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_PMV_WW4B3_3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_IMUX7_3", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_IMUX14_3", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_PMV_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_PMV_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_IMUX35_3", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_PMV_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_WW4A2_3", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_PMV_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_PMV_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_PMV_IMUX6_3", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_PMV_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_PMV_SW2A2_3", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_PMV_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_PMV_IMUX9_3", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_LOGIC_OUTS9_3", - "INT_INTERFACE_LOGIC_OUTS_B9" - ], - [ - "CLK_PMV_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_PMV_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_PMV_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_PMV_WW4C3_3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_PMV_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_CLK1_3", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_IMUX27_3", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_PMV_SE4BEG1_3", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_PMV_WL1END3_3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_PMV_LOGIC_OUTS13_3", - "INT_INTERFACE_LOGIC_OUTS_B13" - ], - [ - "CLK_PMV_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_PMV_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_PMV_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_IMUX5_3", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_LH9_3", - "INT_INTERFACE_LH9" - ], + "BRAM_FIFO36_CASCADEOUTB_1", + "HCLK_BRAM_CASCADEB_R" + ] + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "tile_types": [ + "BRAM_R", + "HCLK_BRAM" + ], + "wire_pairs": [ [ - "CLK_PMV_IMUX42_3", - "INT_INTERFACE_IMUX42" + "BRAM_CASCINBOT_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ - "CLK_PMV_SW4A2_3", - "INT_INTERFACE_SW4A2" + "BRAM_CASCINBOT_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ - "CLK_PMV_NW2A3_3", - "INT_INTERFACE_NW2A3" + "BRAM_CASCINBOT_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ - "CLK_PMV_IMUX13_3", - "INT_INTERFACE_IMUX13" + "BRAM_CASCINBOT_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ - "CLK_PMV_LH8_3", - "INT_INTERFACE_LH8" + "BRAM_CASCINBOT_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ - "CLK_PMV_FAN4_3", - "INT_INTERFACE_FAN4" + "BRAM_CASCINBOT_ADDRARDADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ - "CLK_PMV_IMUX10_3", - "INT_INTERFACE_IMUX10" + "BRAM_CASCINBOT_ADDRARDADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ - "CLK_PMV_IMUX21_3", - "INT_INTERFACE_IMUX21" + "BRAM_CASCINBOT_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ - "CLK_PMV_IMUX26_3", - "INT_INTERFACE_IMUX26" + "BRAM_CASCINBOT_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ - "CLK_PMV_EE4B0_3", - "INT_INTERFACE_EE4B0" + "BRAM_CASCINBOT_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ - "CLK_PMV_FAN7_3", - "INT_INTERFACE_FAN7" + "BRAM_CASCINBOT_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ - "CLK_PMV_WW4B1_3", - "INT_INTERFACE_WW4B1" + "BRAM_CASCINBOT_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ - "CLK_PMV_NW4END2_3", - "INT_INTERFACE_NW4END2" + "BRAM_CASCINBOT_ADDRARDADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ - "CLK_PMV_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" + "BRAM_CASCINBOT_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ - "CLK_PMV_NE2A1_3", - "INT_INTERFACE_NE2A1" + "BRAM_CASCINBOT_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ - "CLK_PMV_SW4END0_3", - "INT_INTERFACE_SW4END0" + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ - "CLK_PMV_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ - "CLK_PMV_EE4C3_3", - "INT_INTERFACE_EE4C3" + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ - "CLK_PMV_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ - "CLK_PMV_NE4C3_3", - "INT_INTERFACE_NE4C3" + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ - "CLK_PMV_NW4END1_3", - "INT_INTERFACE_NW4END1" + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ - "CLK_PMV_IMUX0_3", - "INT_INTERFACE_IMUX0" + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ - "CLK_PMV_NE2A3_3", - "INT_INTERFACE_NE2A3" + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ - "CLK_PMV_NW4A3_3", - "INT_INTERFACE_NW4A3" + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ - "CLK_PMV_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ - "CLK_PMV_CTRL1_3", - "INT_INTERFACE_CTRL1" + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ - "CLK_PMV_SW4A1_3", - "INT_INTERFACE_SW4A1" + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ - "CLK_PMV_IMUX24_3", - "INT_INTERFACE_IMUX24" + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ - "CLK_PMV_WW2END3_3", - "INT_INTERFACE_WW2END3" + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ - "CLK_PMV_BYP0_3", - "INT_INTERFACE_BYP0" + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ - "CLK_PMV_WL1END2_3", - "INT_INTERFACE_WL1END2" + "BRAM_CASCOUT_ADDRARDADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ - "CLK_PMV_SE2A1_3", - "INT_INTERFACE_SE2A1" + "BRAM_CASCOUT_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ - "CLK_PMV_SE4C2_3", - "INT_INTERFACE_SE4C2" + "BRAM_CASCOUT_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ - "CLK_PMV_WL1END1_3", - "INT_INTERFACE_WL1END1" + "BRAM_CASCOUT_ADDRARDADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ - "CLK_PMV_LH1_3", - "INT_INTERFACE_LH1" + "BRAM_CASCOUT_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ - "CLK_PMV_NW2A2_3", - "INT_INTERFACE_NW2A2" + "BRAM_CASCOUT_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ - "CLK_PMV_WW2A3_3", - "INT_INTERFACE_WW2A3" + "BRAM_CASCOUT_ADDRARDADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ - "CLK_PMV_BYP6_3", - "INT_INTERFACE_BYP6" + "BRAM_CASCOUT_ADDRARDADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ - "CLK_PMV_NW4END0_3", - "INT_INTERFACE_NW4END0" + "BRAM_CASCOUT_ADDRARDADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ - "CLK_PMV_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" + "BRAM_CASCOUT_ADDRARDADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ - "CLK_PMV_SE4C3_3", - "INT_INTERFACE_SE4C3" + "BRAM_CASCOUT_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ - "CLK_PMV_EE2A3_3", - "INT_INTERFACE_EE2A3" + "BRAM_CASCOUT_ADDRARDADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ - "CLK_PMV_CLK0_3", - "INT_INTERFACE_CLK0" + "BRAM_CASCOUT_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ - "CLK_PMV_FAN0_3", - "INT_INTERFACE_FAN0" + "BRAM_CASCOUT_ADDRARDADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ - "CLK_PMV_EE4B2_3", - "INT_INTERFACE_EE4B2" + "BRAM_CASCOUT_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ - "CLK_PMV_IMUX47_3", - "INT_INTERFACE_IMUX47" + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ - "CLK_PMV_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" + "BRAM_CASCOUT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ - "CLK_PMV_NW4A2_3", - "INT_INTERFACE_NW4A2" + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ - "CLK_PMV_FAN3_3", - "INT_INTERFACE_FAN3" + "BRAM_CASCOUT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ - "CLK_PMV_FAN5_3", - "INT_INTERFACE_FAN5" + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ - "CLK_PMV_IMUX32_3", - "INT_INTERFACE_IMUX32" + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ - "CLK_PMV_WW2A2_3", - "INT_INTERFACE_WW2A2" + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ - "CLK_PMV_IMUX44_3", - "INT_INTERFACE_IMUX44" + "BRAM_CASCOUT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ - "CLK_PMV_BYP3_3", - "INT_INTERFACE_BYP3" + "BRAM_CASCOUT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ - "CLK_PMV_WW4C0_3", - "INT_INTERFACE_WW4C0" + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ - "CLK_PMV_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ - "CLK_PMV_EE4B1_3", - "INT_INTERFACE_EE4B1" + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ - "CLK_PMV_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ - "CLK_PMV_BYP5_3", - "INT_INTERFACE_BYP5" + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ - "CLK_PMV_EE4C1_3", - "INT_INTERFACE_EE4C1" + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ - "CLK_PMV_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" + "BRAM_FIFO36_CASCADEINA", + "HCLK_BRAM_CASCADEA_R" ], [ - "CLK_PMV_FAN6_3", - "INT_INTERFACE_FAN6" + "BRAM_FIFO36_CASCADEINB", + "HCLK_BRAM_CASCADEB_R" ], [ - "CLK_PMV_NW4END3_3", - "INT_INTERFACE_NW4END3" + "BRAM_PMVBRAM_O", + "HCLK_BRAM_PMVBRAM_O" ], [ - "CLK_PMV_SW4END2_3", - "INT_INTERFACE_SW4END2" + "BRAM_PMVBRAM_ODIV2", + "HCLK_BRAM_PMVBRAM_ODIV2" ], [ - "CLK_PMV_WW4C2_3", - "INT_INTERFACE_WW4C2" + "BRAM_PMVBRAM_ODIV4", + "HCLK_BRAM_PMVBRAM_ODIV4" ], [ - "CLK_PMV_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" + "BRAM_PMVBRAM_SELECT1", + "HCLK_BRAM_PMVBRAM_SELECT1" ], [ - "CLK_PMV_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" + "BRAM_PMVBRAM_SELECT2", + "HCLK_BRAM_PMVBRAM_SELECT2" ], [ - "CLK_PMV_EE2A1_3", - "INT_INTERFACE_EE2A1" + "BRAM_PMVBRAM_SELECT3", + "HCLK_BRAM_PMVBRAM_SELECT3" ], [ - "CLK_PMV_IMUX33_3", - "INT_INTERFACE_IMUX33" + "BRAM_PMVBRAM_SELECT4", + "HCLK_BRAM_PMVBRAM_SELECT4" ] ] }, { "grid_deltas": [ 1, - -3 + -4 ], "tile_types": [ - "CFG_CENTER_MID", - "VFRAME" - ], - "wire_pairs": [ - [ - "CFG_CENTER_IMUX27_13", - "VFRAME_IMUX27" - ], - [ - "CFG_CENTER_NW2A0_13", - "VFRAME_NW2A0" - ], - [ - "CFG_CENTER_WW4END3_13", - "VFRAME_WW4END3" - ], - [ - "CFG_CENTER_IMUX5_13", - "VFRAME_IMUX5" - ], - [ - "CFG_CENTER_BYP6_13", - "VFRAME_BYP6" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B23_13", - "VFRAME_LOGIC_OUTS_B23" - ], - [ - "CFG_CENTER_IMUX25_13", - "VFRAME_IMUX25" - ], - [ - "CFG_CENTER_SW4END2_13", - "VFRAME_SW4END2" - ], - [ - "CFG_CENTER_LH8_13", - "VFRAME_LH8" - ], - [ - "CFG_CENTER_WL1END1_13", - "VFRAME_WL1END1" - ], - [ - "CFG_CENTER_LH6_13", - "VFRAME_LH6" - ], - [ - "CFG_CENTER_WR1END1_13", - "VFRAME_WR1END1" - ], - [ - "CFG_CENTER_SW4END0_13", - "VFRAME_SW4END0" - ], - [ - "CFG_CENTER_BYP3_13", - "VFRAME_BYP3" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B17_13", - "VFRAME_LOGIC_OUTS_B17" - ], - [ - "CFG_CENTER_NE2A2_13", - "VFRAME_NE2A2" - ], - [ - "CFG_CENTER_ER1BEG3_13", - "VFRAME_ER1BEG3" - ], - [ - "CFG_CENTER_WW4END0_13", - "VFRAME_WW4END0" - ], - [ - "CFG_CENTER_BYP2_13", - "VFRAME_BYP2" - ], - [ - "CFG_CENTER_EL1BEG0_13", - "VFRAME_EL1BEG0" - ], - [ - "CFG_CENTER_SE4BEG2_13", - "VFRAME_SE4BEG2" - ], - [ - "CFG_CENTER_NW4A2_13", - "VFRAME_NW4A2" - ], - [ - "CFG_CENTER_SE4C0_13", - "VFRAME_SE4C0" - ], - [ - "CFG_CENTER_LH5_13", - "VFRAME_LH5" - ], - [ - "CFG_CENTER_IMUX17_13", - "VFRAME_IMUX17" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B15_13", - "VFRAME_LOGIC_OUTS_B15" - ], - [ - "CFG_CENTER_EE4B1_13", - "VFRAME_EE4B1" - ], - [ - "CFG_CENTER_SW4A1_13", - "VFRAME_SW4A1" - ], - [ - "CFG_CENTER_EE4C0_13", - "VFRAME_EE4C0" - ], - [ - "CFG_CENTER_NE2A3_13", - "VFRAME_NE2A3" - ], - [ - "CFG_CENTER_WW4END1_13", - "VFRAME_WW4END1" - ], - [ - "CFG_CENTER_IMUX16_13", - "VFRAME_IMUX16" - ], - [ - "CFG_CENTER_EE2A0_13", - "VFRAME_EE2A0" - ], - [ - "CFG_CENTER_IMUX22_13", - "VFRAME_IMUX22" - ], - [ - "CFG_CENTER_IMUX31_13", - "VFRAME_IMUX31" - ], - [ - "CFG_CENTER_EE4BEG0_13", - "VFRAME_EE4BEG0" - ], - [ - "CFG_CENTER_NE4C2_13", - "VFRAME_NE4C2" - ], - [ - "CFG_CENTER_SE2A2_13", - "VFRAME_SE2A2" - ], - [ - "CFG_CENTER_CLK0_13", - "VFRAME_CLK0" - ], - [ - "CFG_CENTER_NW4END3_13", - "VFRAME_NW4END3" - ], - [ - "CFG_CENTER_EE4BEG2_13", - "VFRAME_EE4BEG2" - ], - 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"IOI_IMUX22_1", - "TERM_INT_IMUX22" - ], - [ - "IOI_LOGIC_OUTS7_1", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_FAN3_1", - "TERM_INT_FAN3" - ], - [ - "IOI_LOGIC_OUTS5_1", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_PHASER_TO_IO_OCLK_0", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_LOGIC_OUTS20_1", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_IMUX47_1", - "TERM_INT_IMUX47" - ], - [ - "IOI_IMUX17_1", - "TERM_INT_IMUX17" - ], - [ - "IOI_LOGIC_OUTS15_1", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_BLOCK_OUTS2_1", - "TERM_INT_BLOCK_OUTS_L_B2" - ], - [ - "IOI_PHASER_TO_IO_ICLK_0", - "L_TERM_INT_PHASER_TO_IO_ICLK" - ], - [ - "IOI_BYP4_1", - "TERM_INT_BYP4" - ], - [ - "IOI_IMUX45_1", - "TERM_INT_IMUX45" - ], - [ - "IOI_FAN7_1", - "TERM_INT_FAN7" - ], - [ - "IOI_BYP0_1", - "TERM_INT_BYP0" - ], - [ - "IOI_IMUX23_1", - "TERM_INT_IMUX23" - ], - [ - "IOI_LOGIC_OUTS1_1", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_IMUX25_1", - "TERM_INT_IMUX25" - ], - [ - "IOI_LOGIC_OUTS9_1", - "TERM_INT_LOGIC_OUTS_L_B9" - ], - [ - "IOI_LOGIC_OUTS2_1", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "IOI_IMUX6_1", - "TERM_INT_IMUX6" - ], - [ - "IOI_BYP6_1", - "TERM_INT_BYP6" - ], - [ - "IOI_IMUX41_1", - "TERM_INT_IMUX41" - ] - ] - }, - { - "grid_deltas": [ - 0, - -2 - ], - "tile_types": [ - "RIOI3", - "RIOI3_TBYTETERM" - ], - "wire_pairs": [ - [ - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1" - ], - [ - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1" - ], - [ - "IOI_IOCLK3", - "IOI_IOCLK3" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK4" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK1" - ], - [ - "IOI_IOCLK0", - "IOI_IOCLK0" - ], - [ - "IOI_IOCLK1", - "IOI_IOCLK1" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_RCLK_FORIO3" - ], - [ - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CE3" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK3" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK2" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO2" - ], - [ - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE2" - ], - [ - "IOI_IOCLK2", - "IOI_IOCLK2" - ], - [ - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK0" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO1" - ], - [ - "IOI_IMUX_RC2", - "IOI_IMUX_RC0" - ], - [ - "IOI_IMUX_RC3", - "IOI_IMUX_RC1" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_LEAF_GCLK5" - ], - [ - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO0" - ] - ] - }, - { - "grid_deltas": [ - -1, - -3 - ], - "tile_types": [ - "GTP_COMMON", - "HCLK_TERM_GTX" - ], - "wire_pairs": [ - [ - "GTPE2_COMMON_MGT_CLK3", - "HCLK_TERM_GTX_CK_IN7" - ], - [ - "GTPE2_COMMON_MGT_CLK0", - "HCLK_TERM_GTX_CK_IN4" - ], - [ - "GTPE2_COMMON_MGT_CLK6", - "HCLK_TERM_GTX_CK_IN10" - ], - [ - "GTPE2_COMMON_MGT_CLK4", - "HCLK_TERM_GTX_CK_IN8" - ], - [ - "GTPE2_COMMON_MGT_CLK7", - "HCLK_TERM_GTX_CK_IN11" - ], - [ - "GTPE2_COMMON_MGT_CLK9", - "HCLK_TERM_GTX_CK_IN13" - ], - [ - "GTPE2_COMMON_MGT_CLK2", - "HCLK_TERM_GTX_CK_IN6" - ], - [ - "GTPE2_COMMON_MGT_CLK5", - "HCLK_TERM_GTX_CK_IN9" - ], - [ - "GTPE2_COMMON_MGT_CLK1", - "HCLK_TERM_GTX_CK_IN5" - ], - [ - "GTPE2_COMMON_MGT_CLK8", - "HCLK_TERM_GTX_CK_IN12" - ] - ] - }, - { - "grid_deltas": [ - -1, - 3 - ], - "tile_types": [ - "CMT_TOP_L_LOWER_B", + "BRAM_R", "VBRK" ], "wire_pairs": [ [ - "CMT_TOP_NW4A0_5", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_SW4A0_5", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_NW4A1_5", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_EE2A0_5", + "BRAM_EE2A0_4", "VBRK_EE2A0" ], [ - "CMT_TOP_EE4A0_5", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_EE4BEG0_5", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW4A3_5", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_LH6_5", - "VBRK_LH6" - ], - [ - "CMT_TOP_NW4A2_5", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_WR1END0_5", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_NE4BEG1_5", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_WL1END3_5", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_SE4BEG0_5", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_SW2A0_5", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_WL1END1_5", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_NW4END3_5", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW4C2_5", - "VBRK_WW4C2" - ], - [ - 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], - [ - "CMT_TOP_ER1BEG1_5", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_SE4BEG1_5", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_EE4C0_5", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_NW2A1_5", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_NW4END1_5", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_NW4END2_5", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_WW4A2_5", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_NE2A3_5", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_LH7_5", - "VBRK_LH7" - ], - [ - "CMT_TOP_NW2A3_5", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_NE4C1_5", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_EE4C3_5", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_LH3_5", - "VBRK_LH3" - ], - [ - "CMT_TOP_LH2_5", - "VBRK_LH2" - ], - [ - "CMT_TOP_EE4B0_5", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_EE4BEG1_5", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_LH1_5", - "VBRK_LH1" - ], - [ - "CMT_TOP_WW4C0_5", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_WW2END3_5", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_ER1BEG0_5", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_SE4C2_5", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_NE4C2_5", - "VBRK_NE4C2" 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"VBRK_WW4END1" - ], - [ - "CMT_TOP_WW2A3_5", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE2BEG2_5", + "BRAM_EE2BEG2_4", "VBRK_EE2BEG2" ], [ - "CMT_TOP_EE4B1_5", + "BRAM_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "BRAM_EE4A0_4", + "VBRK_EE4A0" + ], + [ + "BRAM_EE4A1_4", + "VBRK_EE4A1" + ], + [ + "BRAM_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "BRAM_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "BRAM_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "BRAM_EE4B1_4", "VBRK_EE4B1" ], [ - "CMT_TOP_SE4BEG3_5", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_NE2A1_5", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_SW4END2_5", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WW2END1_5", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_ER1BEG3_5", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_ER1BEG2_5", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_SE2A3_5", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_WW4C1_5", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_NE4BEG3_5", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_MONITOR_N_5", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_NE4BEG2_5", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_LH8_5", - "VBRK_LH8" - ], - [ - "CMT_TOP_SE4C1_5", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_WR1END1_5", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_NE2A2_5", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_SW2A2_5", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_EL1BEG0_5", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WW2A1_5", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_NW2A2_5", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_SE2A2_5", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_EE4B2_5", + "BRAM_EE4B2_4", "VBRK_EE4B2" ], [ - "CMT_TOP_SW4END0_5", + "BRAM_EE4B3_4", + "VBRK_EE4B3" + ], + [ + "BRAM_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "BRAM_EE4BEG1_4", + "VBRK_EE4BEG1" + ], + [ + "BRAM_EE4BEG2_4", + "VBRK_EE4BEG2" + ], + [ + "BRAM_EE4BEG3_4", + "VBRK_EE4BEG3" + ], + [ + "BRAM_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "BRAM_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "BRAM_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "BRAM_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "BRAM_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "BRAM_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "BRAM_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "BRAM_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "BRAM_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "BRAM_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "BRAM_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "BRAM_LH1_4", + "VBRK_LH1" + ], + [ + "BRAM_LH2_4", + "VBRK_LH2" + ], + [ + "BRAM_LH3_4", + "VBRK_LH3" + ], + [ + "BRAM_LH4_4", + "VBRK_LH4" + ], + [ + "BRAM_LH5_4", + "VBRK_LH5" + ], + [ + "BRAM_LH6_4", + "VBRK_LH6" + ], + [ + "BRAM_LH7_4", + "VBRK_LH7" + ], + [ + "BRAM_LH8_4", + "VBRK_LH8" + ], + [ + "BRAM_LH9_4", + "VBRK_LH9" + ], + [ + "BRAM_LH10_4", + "VBRK_LH10" + ], + [ + "BRAM_LH11_4", + "VBRK_LH11" + ], + [ + "BRAM_LH12_4", + "VBRK_LH12" + ], + [ + "BRAM_MONITOR_N_4", + "VBRK_MONITOR_N" + ], + [ + "BRAM_MONITOR_P_4", + "VBRK_MONITOR_P" + ], + [ + "BRAM_NE2A0_4", + "VBRK_NE2A0" + ], + [ + "BRAM_NE2A1_4", + "VBRK_NE2A1" + ], + [ + "BRAM_NE2A2_4", + "VBRK_NE2A2" + ], + [ + "BRAM_NE2A3_4", + "VBRK_NE2A3" + ], + [ + "BRAM_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "BRAM_NE4BEG1_4", + "VBRK_NE4BEG1" + ], + [ + "BRAM_NE4BEG2_4", + "VBRK_NE4BEG2" + ], + [ + "BRAM_NE4BEG3_4", + "VBRK_NE4BEG3" + ], + [ + "BRAM_NE4C0_4", + "VBRK_NE4C0" + ], + [ + "BRAM_NE4C1_4", + "VBRK_NE4C1" + ], + [ + "BRAM_NE4C2_4", + "VBRK_NE4C2" + ], + [ + "BRAM_NE4C3_4", + "VBRK_NE4C3" + ], + [ + "BRAM_NW2A0_4", + "VBRK_NW2A0" + ], + [ + "BRAM_NW2A1_4", + "VBRK_NW2A1" + ], + [ + "BRAM_NW2A2_4", + "VBRK_NW2A2" + ], + [ + "BRAM_NW2A3_4", + "VBRK_NW2A3" + ], + [ + "BRAM_NW4A0_4", + "VBRK_NW4A0" + ], + [ + "BRAM_NW4A1_4", + "VBRK_NW4A1" + ], + [ + "BRAM_NW4A2_4", + "VBRK_NW4A2" + ], + [ + "BRAM_NW4A3_4", + "VBRK_NW4A3" + ], + [ + "BRAM_NW4END0_4", + "VBRK_NW4END0" + ], + [ + "BRAM_NW4END1_4", + "VBRK_NW4END1" + ], + [ + "BRAM_NW4END2_4", + "VBRK_NW4END2" + ], + [ + "BRAM_NW4END3_4", + "VBRK_NW4END3" + ], + [ + "BRAM_SE2A0_4", + "VBRK_SE2A0" + ], + [ + "BRAM_SE2A1_4", + "VBRK_SE2A1" + ], + [ + "BRAM_SE2A2_4", + "VBRK_SE2A2" + ], + [ + "BRAM_SE2A3_4", + "VBRK_SE2A3" + ], + [ + "BRAM_SE4BEG0_4", + "VBRK_SE4BEG0" + ], + [ + "BRAM_SE4BEG1_4", + "VBRK_SE4BEG1" + ], + [ + "BRAM_SE4BEG2_4", + "VBRK_SE4BEG2" + ], + [ + "BRAM_SE4BEG3_4", + "VBRK_SE4BEG3" + ], + [ + "BRAM_SE4C0_4", + "VBRK_SE4C0" + ], + [ + "BRAM_SE4C1_4", + "VBRK_SE4C1" + ], + [ + "BRAM_SE4C2_4", + "VBRK_SE4C2" + ], + [ + "BRAM_SE4C3_4", + "VBRK_SE4C3" + ], + [ + "BRAM_SW2A0_4", + "VBRK_SW2A0" + ], + [ + "BRAM_SW2A1_4", + "VBRK_SW2A1" + ], + [ + "BRAM_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "BRAM_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "BRAM_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "BRAM_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "BRAM_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "BRAM_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "BRAM_SW4END0_4", "VBRK_SW4END0" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_FEEDTHRU_1", - "HCLK_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_FEEDTHRU_2_CK_IN11" ], [ - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_FEEDTHRU_2_CK_IN7" + "BRAM_SW4END1_4", + "VBRK_SW4END1" ], [ - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_FEEDTHRU_2_CK_IN1" + "BRAM_SW4END2_4", + "VBRK_SW4END2" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_FEEDTHRU_2_CK_BUFHCLK2" + "BRAM_SW4END3_4", + "VBRK_SW4END3" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_FEEDTHRU_2_CK_BUFHCLK0" + "BRAM_WL1END0_4", + "VBRK_WL1END0" ], [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_FEEDTHRU_2_CK_BUFRCLK1" + "BRAM_WL1END1_4", + "VBRK_WL1END1" ], [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_FEEDTHRU_2_CK_BUFRCLK0" + "BRAM_WL1END2_4", + "VBRK_WL1END2" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_FEEDTHRU_2_CK_BUFHCLK8" + "BRAM_WL1END3_4", + "VBRK_WL1END3" ], [ - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_FEEDTHRU_2_CK_IN0" + "BRAM_WR1END0_4", + "VBRK_WR1END0" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_FEEDTHRU_2_CK_BUFHCLK10" + "BRAM_WR1END1_4", + "VBRK_WR1END1" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_FEEDTHRU_2_CK_BUFHCLK7" + "BRAM_WR1END2_4", + "VBRK_WR1END2" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_FEEDTHRU_2_CK_BUFHCLK5" + "BRAM_WR1END3_4", + "VBRK_WR1END3" ], [ - "HCLK_FEEDTHRU_1_CK_IN9", - "HCLK_FEEDTHRU_2_CK_IN9" + "BRAM_WW2A0_4", + "VBRK_WW2A0" ], [ - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_FEEDTHRU_2_CK_IN13" + "BRAM_WW2A1_4", + "VBRK_WW2A1" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_FEEDTHRU_2_CK_BUFHCLK3" + "BRAM_WW2A2_4", + "VBRK_WW2A2" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_FEEDTHRU_2_CK_BUFHCLK11" + "BRAM_WW2A3_4", + "VBRK_WW2A3" ], [ - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_FEEDTHRU_2_CK_IN10" + "BRAM_WW2END0_4", + "VBRK_WW2END0" ], [ - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_FEEDTHRU_2_CK_IN6" + "BRAM_WW2END1_4", + "VBRK_WW2END1" ], [ - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_FEEDTHRU_2_CK_IN2" + "BRAM_WW2END2_4", + "VBRK_WW2END2" ], [ - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_FEEDTHRU_2_CK_IN4" + "BRAM_WW2END3_4", + "VBRK_WW2END3" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_FEEDTHRU_2_CK_BUFHCLK6" + "BRAM_WW4A0_4", + "VBRK_WW4A0" ], [ - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_FEEDTHRU_2_CK_IN3" + "BRAM_WW4A1_4", + "VBRK_WW4A1" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_FEEDTHRU_2_CK_BUFHCLK4" + "BRAM_WW4A2_4", + "VBRK_WW4A2" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_FEEDTHRU_2_CK_BUFHCLK1" + "BRAM_WW4A3_4", + "VBRK_WW4A3" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_FEEDTHRU_2_CK_BUFHCLK9" + "BRAM_WW4B0_4", + "VBRK_WW4B0" ], [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_FEEDTHRU_2_CK_BUFRCLK2" + "BRAM_WW4B1_4", + "VBRK_WW4B1" ], [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_FEEDTHRU_2_CK_BUFRCLK3" + "BRAM_WW4B2_4", + "VBRK_WW4B2" ], [ - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_FEEDTHRU_2_CK_IN12" + "BRAM_WW4B3_4", + "VBRK_WW4B3" ], [ - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_FEEDTHRU_2_CK_IN5" + "BRAM_WW4C0_4", + "VBRK_WW4C0" ], [ - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_FEEDTHRU_2_CK_IN8" + "BRAM_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "BRAM_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "BRAM_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "BRAM_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "BRAM_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "BRAM_WW4END3_4", + "VBRK_WW4END3" ] ] }, @@ -18002,96 +20918,236 @@ ], "wire_pairs": [ [ - "BRAM_EE4A2_3", - "VBRK_EE4A2" + "BRAM_EE2A0_3", + "VBRK_EE2A0" ], [ - "BRAM_LH2_3", - "VBRK_LH2" + "BRAM_EE2A1_3", + "VBRK_EE2A1" ], [ - "BRAM_WW4C0_3", - "VBRK_WW4C0" + "BRAM_EE2A2_3", + "VBRK_EE2A2" ], [ - "BRAM_ER1BEG0_3", - "VBRK_ER1BEG0" + "BRAM_EE2A3_3", + "VBRK_EE2A3" ], [ - "BRAM_MONITOR_N_3", - "VBRK_MONITOR_N" - ], - [ - "BRAM_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "BRAM_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "BRAM_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "BRAM_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "BRAM_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "BRAM_LH5_3", - "VBRK_LH5" - ], - [ - "BRAM_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "BRAM_SW4END0_3", - "VBRK_SW4END0" + "BRAM_EE2BEG0_3", + "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_3", "VBRK_EE2BEG1" ], [ - "BRAM_WW4B2_3", - "VBRK_WW4B2" + "BRAM_EE2BEG2_3", + "VBRK_EE2BEG2" ], [ - "BRAM_NE4BEG2_3", - "VBRK_NE4BEG2" + "BRAM_EE2BEG3_3", + "VBRK_EE2BEG3" + ], + [ + "BRAM_EE4A0_3", + "VBRK_EE4A0" + ], + [ + "BRAM_EE4A1_3", + "VBRK_EE4A1" + ], + [ + "BRAM_EE4A2_3", + "VBRK_EE4A2" + ], + [ + "BRAM_EE4A3_3", + "VBRK_EE4A3" + ], + [ + "BRAM_EE4B0_3", + "VBRK_EE4B0" ], [ "BRAM_EE4B1_3", "VBRK_EE4B1" ], [ - "BRAM_SE4C2_3", - "VBRK_SE4C2" + "BRAM_EE4B2_3", + "VBRK_EE4B2" + ], + [ + "BRAM_EE4B3_3", + "VBRK_EE4B3" + ], + [ + "BRAM_EE4BEG0_3", + "VBRK_EE4BEG0" + ], + [ + "BRAM_EE4BEG1_3", + "VBRK_EE4BEG1" + ], + [ + "BRAM_EE4BEG2_3", + "VBRK_EE4BEG2" + ], + [ + "BRAM_EE4BEG3_3", + "VBRK_EE4BEG3" + ], + [ + "BRAM_EE4C0_3", + "VBRK_EE4C0" + ], + [ + "BRAM_EE4C1_3", + "VBRK_EE4C1" + ], + [ + "BRAM_EE4C2_3", + "VBRK_EE4C2" + ], + [ + "BRAM_EE4C3_3", + "VBRK_EE4C3" + ], + [ + "BRAM_EL1BEG0_3", + "VBRK_EL1BEG0" + ], + [ + "BRAM_EL1BEG1_3", + "VBRK_EL1BEG1" + ], + [ + "BRAM_EL1BEG2_3", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EL1BEG3_3", + "VBRK_EL1BEG3" + ], + [ + "BRAM_ER1BEG0_3", + "VBRK_ER1BEG0" + ], + [ + "BRAM_ER1BEG1_3", + "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_3", "VBRK_ER1BEG2" ], [ - "BRAM_WL1END3_3", - "VBRK_WL1END3" + "BRAM_ER1BEG3_3", + "VBRK_ER1BEG3" ], [ - "BRAM_SW2A2_3", - "VBRK_SW2A2" + "BRAM_LH1_3", + "VBRK_LH1" ], [ - "BRAM_SE4BEG0_3", - "VBRK_SE4BEG0" + "BRAM_LH2_3", + "VBRK_LH2" ], [ - "BRAM_WW4A2_3", - "VBRK_WW4A2" + "BRAM_LH3_3", + "VBRK_LH3" + ], + [ + "BRAM_LH4_3", + "VBRK_LH4" + ], + [ + "BRAM_LH5_3", + "VBRK_LH5" + ], + [ + "BRAM_LH6_3", + "VBRK_LH6" + ], + [ + "BRAM_LH7_3", + "VBRK_LH7" + ], + [ + "BRAM_LH8_3", + "VBRK_LH8" + ], + [ + "BRAM_LH9_3", + "VBRK_LH9" + ], + [ + "BRAM_LH10_3", + "VBRK_LH10" + ], + [ + "BRAM_LH11_3", + "VBRK_LH11" + ], + [ + "BRAM_LH12_3", + "VBRK_LH12" + ], + [ + "BRAM_MONITOR_N_3", + "VBRK_MONITOR_N" + ], + [ + "BRAM_MONITOR_P_3", + "VBRK_MONITOR_P" + ], + [ + "BRAM_NE2A0_3", + "VBRK_NE2A0" + ], + [ + "BRAM_NE2A1_3", + "VBRK_NE2A1" + ], + [ + "BRAM_NE2A2_3", + "VBRK_NE2A2" + ], + [ + "BRAM_NE2A3_3", + "VBRK_NE2A3" + ], + [ + "BRAM_NE4BEG0_3", + "VBRK_NE4BEG0" + ], + [ + "BRAM_NE4BEG1_3", + "VBRK_NE4BEG1" + ], + [ + "BRAM_NE4BEG2_3", + "VBRK_NE4BEG2" + ], + [ + "BRAM_NE4BEG3_3", + "VBRK_NE4BEG3" + ], + [ + "BRAM_NE4C0_3", + "VBRK_NE4C0" + ], + [ + "BRAM_NE4C1_3", + "VBRK_NE4C1" + ], + [ + "BRAM_NE4C2_3", + "VBRK_NE4C2" + ], + [ + "BRAM_NE4C3_3", + "VBRK_NE4C3" ], [ "BRAM_NW2A0_3", @@ -18101,45293 +21157,269 @@ "BRAM_NW2A1_3", "VBRK_NW2A1" ], - [ - "BRAM_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "BRAM_SE2A2_3", - "VBRK_SE2A2" - ], - [ - "BRAM_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "BRAM_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "BRAM_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "BRAM_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "BRAM_LH1_3", - "VBRK_LH1" - ], - [ - "BRAM_LH11_3", - "VBRK_LH11" - ], - [ - "BRAM_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "BRAM_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "BRAM_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "BRAM_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "BRAM_WW4C2_3", - "VBRK_WW4C2" - ], - [ - "BRAM_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "BRAM_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "BRAM_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "BRAM_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "BRAM_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "BRAM_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "BRAM_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "BRAM_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "BRAM_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "BRAM_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "BRAM_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "BRAM_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "BRAM_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "BRAM_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "BRAM_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "BRAM_WL1END2_3", - "VBRK_WL1END2" - ], - [ - "BRAM_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "BRAM_LH3_3", - "VBRK_LH3" - ], - [ - "BRAM_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "BRAM_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "BRAM_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "BRAM_SW2A0_3", - "VBRK_SW2A0" - ], - [ - "BRAM_WW4C1_3", - "VBRK_WW4C1" - ], - [ - "BRAM_EE2A1_3", - "VBRK_EE2A1" - ], [ "BRAM_NW2A2_3", "VBRK_NW2A2" ], - [ - "BRAM_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "BRAM_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "BRAM_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "BRAM_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "BRAM_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "BRAM_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "BRAM_LH8_3", - "VBRK_LH8" - ], - [ - "BRAM_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "BRAM_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "BRAM_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "BRAM_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "BRAM_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "BRAM_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "BRAM_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "BRAM_WW4B0_3", - "VBRK_WW4B0" - ], [ "BRAM_NW2A3_3", "VBRK_NW2A3" ], - [ - "BRAM_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "BRAM_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "BRAM_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "BRAM_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "BRAM_EL1BEG3_3", - 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"CMT_TOP_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_LH1_2", - "VBRK_LH1" - ], - [ - "CMT_TOP_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_LH3_2", - "VBRK_LH3" - ], - [ - "CMT_TOP_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_LH4_2", - "VBRK_LH4" - ], - [ - "CMT_TOP_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_SW4A3_2", - "VBRK_SW4A3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_INT_INTERFACE", - "HCLK_TERM" - ], - "wire_pairs": [ - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_TERM_CK_BUFRCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_TERM_CK_BUFHCLK11" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_TERM_CK_BUFHCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_TERM_CK_BUFHCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_TERM_CK_BUFHCLK0" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_TERM_PERFCLK3" - ], - [ - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_TERM_CCIO3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_TERM_CK_BUFHCLK6" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_TERM_PERFCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_TERM_CK_BUFHCLK9" - ], - [ - "HCLK_INT_INTERFACE_CCIO0", - "HCLK_TERM_CCIO0" - ], - [ - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_TERM_CCIO2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_TERM_CK_BUFRCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_TERM_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_TERM_CK_BUFRCLK0" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_TERM_PERFCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_TERM_CK_BUFHCLK5" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_TERM_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_TERM_CK_BUFHCLK1" - ], - [ - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_TERM_CCIO1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_TERM_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_TERM_PERFCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_TERM_CK_BUFHCLK10" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_TERM_CK_BUFHCLK4" - ] - ] - }, - { - "grid_deltas": [ - 0, - 5 - ], - "tile_types": [ - "DSP_R", - "DSP_R" - ], - "wire_pairs": [ - [ - "DSP_0_ACIN5", - "DSP_ACOUT5" - ], - [ - "DSP_0_PCIN0", - "DSP_PCOUT0" - ], - [ - "DSP_0_PCIN30", - "DSP_PCOUT30" - ], - [ - "DSP_0_ACIN20", - "DSP_ACOUT20" - ], - [ - "DSP_0_PCIN26", - "DSP_PCOUT26" - ], - [ - "DSP_0_PCIN27", - "DSP_PCOUT27" - ], - [ - "DSP_0_PCIN12", - "DSP_PCOUT12" - ], - [ - "DSP_0_BCIN0", - "DSP_BCOUT0" - ], - [ - "DSP_0_PCIN35", - "DSP_PCOUT35" - ], - [ - "DSP_0_PCIN24", - "DSP_PCOUT24" - ], - [ - "DSP_0_ACIN2", - "DSP_ACOUT2" - ], - [ - "DSP_0_ACIN8", - "DSP_ACOUT8" - ], - [ - "DSP_0_PCIN8", - "DSP_PCOUT8" - ], - [ - "DSP_0_PCIN14", - "DSP_PCOUT14" - ], - [ - "DSP_0_PCIN5", - "DSP_PCOUT5" - ], - [ - "DSP_0_BCIN3", - "DSP_BCOUT3" - ], - [ - "DSP_0_ACIN3", - "DSP_ACOUT3" - ], - [ - "DSP_0_BCIN7", - "DSP_BCOUT7" - ], - [ - "DSP_0_PCIN40", - "DSP_PCOUT40" - ], - [ - "DSP_0_ACIN12", - "DSP_ACOUT12" - ], - [ - "DSP_0_ACIN6", - "DSP_ACOUT6" - ], - [ - "DSP_0_PCIN16", - "DSP_PCOUT16" - ], - [ - "DSP_0_BCIN10", - "DSP_BCOUT10" - ], - [ - "DSP_0_ACIN1", - "DSP_ACOUT1" - ], - [ - "DSP_0_PCIN25", - "DSP_PCOUT25" - ], - [ - "DSP_0_PCIN17", - "DSP_PCOUT17" - ], - [ - "DSP_0_PCIN19", - "DSP_PCOUT19" - ], - [ - "DSP_0_PCIN6", - "DSP_PCOUT6" - ], - [ - "DSP_0_ACIN7", - "DSP_ACOUT7" - ], - [ - "DSP_0_PCIN2", - "DSP_PCOUT2" - ], - [ - "DSP_0_ACIN17", - "DSP_ACOUT17" - ], - [ - "DSP_0_PCIN22", - "DSP_PCOUT22" - ], - [ - "DSP_0_PCIN31", - "DSP_PCOUT31" - ], - [ - "DSP_0_PCIN15", - "DSP_PCOUT15" - ], - [ - "DSP_0_PCIN28", - "DSP_PCOUT28" - ], - [ - "DSP_0_BCIN6", - "DSP_BCOUT6" - ], - [ - "DSP_0_BCIN14", - "DSP_BCOUT14" - ], - [ - "DSP_0_PCIN41", - "DSP_PCOUT41" - ], - [ - "DSP_0_ACIN10", - "DSP_ACOUT10" - ], - [ - "DSP_0_BCIN4", - "DSP_BCOUT4" - ], - [ - "DSP_0_PCIN7", - "DSP_PCOUT7" - ], - [ - "DSP_0_MULTSIGNIN", - "DSP_MULTSIGNOUT" - ], - [ - "DSP_0_BCIN15", - "DSP_BCOUT15" - ], - [ - "DSP_0_ACIN23", - "DSP_ACOUT23" - ], - [ - "DSP_0_BCIN11", - "DSP_BCOUT11" - ], - [ - "DSP_0_ACIN13", - "DSP_ACOUT13" - ], - [ - "DSP_0_PCIN3", - "DSP_PCOUT3" - ], - [ - "DSP_0_PCIN9", - "DSP_PCOUT9" - ], - [ - "DSP_0_PCIN11", - "DSP_PCOUT11" - ], - [ - "DSP_0_ACIN0", - "DSP_ACOUT0" - ], - [ - "DSP_0_PCIN20", - "DSP_PCOUT20" - ], - [ - "DSP_0_PCIN38", - "DSP_PCOUT38" - ], - [ - "DSP_0_ACIN14", - "DSP_ACOUT14" - ], - [ - "DSP_0_PCIN4", - "DSP_PCOUT4" - ], - [ - "DSP_0_ACIN15", - "DSP_ACOUT15" - ], - [ - "DSP_0_PCIN47", - "DSP_PCOUT47" - ], - [ - "DSP_0_BCIN8", - "DSP_BCOUT8" - ], - [ - "DSP_0_ACIN18", - "DSP_ACOUT18" - ], - [ - "DSP_0_ACIN27", - "DSP_ACOUT27" - ], - [ - "DSP_0_ACIN25", - "DSP_ACOUT25" - ], - [ - "DSP_0_BCIN17", - "DSP_BCOUT17" - ], - [ - "DSP_0_BCIN1", - "DSP_BCOUT1" - ], - [ - "DSP_0_ACIN4", - "DSP_ACOUT4" - ], - [ - "DSP_0_PCIN34", - "DSP_PCOUT34" - ], - [ - "DSP_0_ACIN19", - "DSP_ACOUT19" - ], - [ - "DSP_0_ACIN11", - "DSP_ACOUT11" - ], - [ - "DSP_0_ACIN26", - "DSP_ACOUT26" - ], - [ - "DSP_0_PCIN21", - "DSP_PCOUT21" - ], - [ - "DSP_0_PCIN45", - "DSP_PCOUT45" - ], - [ - "DSP_0_PCIN37", - "DSP_PCOUT37" - ], - [ - "DSP_0_PCIN29", - "DSP_PCOUT29" - ], - [ - "DSP_0_PCIN39", - "DSP_PCOUT39" - ], - [ - "DSP_0_ACIN9", - "DSP_ACOUT9" - ], - [ - "DSP_0_PCIN42", - "DSP_PCOUT42" - ], - [ - "DSP_0_ACIN24", - "DSP_ACOUT24" - ], - [ - "DSP_0_BCIN9", - "DSP_BCOUT9" - ], - [ - "DSP_0_PCIN10", - "DSP_PCOUT10" - ], - [ - "DSP_0_PCIN33", - "DSP_PCOUT33" - ], - [ - "DSP_0_PCIN18", - "DSP_PCOUT18" - ], - [ - "DSP_0_PCIN13", - "DSP_PCOUT13" - ], - [ - "DSP_0_BCIN13", - "DSP_BCOUT13" - ], - [ - "DSP_0_ACIN29", - "DSP_ACOUT29" - ], - [ - "DSP_0_BCIN2", - "DSP_BCOUT2" - ], - [ - "DSP_0_BCIN12", - "DSP_BCOUT12" - ], - [ - "DSP_0_ACIN16", - "DSP_ACOUT16" - ], - [ - "DSP_0_ACIN21", - "DSP_ACOUT21" - ], - [ - "DSP_0_PCIN44", - "DSP_PCOUT44" - ], - [ - "DSP_0_ACIN22", - "DSP_ACOUT22" - ], - [ - "DSP_0_BCIN16", - "DSP_BCOUT16" - ], - [ - "DSP_0_PCIN46", - "DSP_PCOUT46" - ], - [ - "DSP_0_BCIN5", - "DSP_BCOUT5" - ], - [ - "DSP_0_PCIN36", - "DSP_PCOUT36" - ], - [ - "DSP_0_ACIN28", - "DSP_ACOUT28" - ], - [ - "DSP_0_PCIN23", - "DSP_PCOUT23" - ], - [ - "DSP_0_PCIN32", - "DSP_PCOUT32" - ], - [ - "DSP_0_CARRYCASCIN", - "DSP_CARRYCASCOUT" - ], - [ - "DSP_0_PCIN43", - "DSP_PCOUT43" - ], - [ - "DSP_0_PCIN1", - "DSP_PCOUT1" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "DSP_R", - "HCLK_DSP_R" - ], - "wire_pairs": [ - [ - "DSP_0_PCIN25", - "HCLK_DSP_PCIN25" - ], - [ - "DSP_0_BCIN17", - "HCLK_DSP_BCIN17" - ], - [ - "DSP_0_PCIN43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_0_PCIN13", - "HCLK_DSP_PCIN13" - ], - [ - "DSP_0_PCIN2", - "HCLK_DSP_PCIN2" - ], - [ - "DSP_0_ACIN8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_0_ACIN13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_0_ACIN3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_0_ACIN25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_0_BCIN12", - "HCLK_DSP_BCIN12" - ], - [ - "DSP_0_ACIN2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_0_BCIN13", - "HCLK_DSP_BCIN13" - ], - [ - "DSP_0_ACIN28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_0_ACIN16", - "HCLK_DSP_ACIN16" - ], - [ - "DSP_0_PCIN45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_0_PCIN11", - "HCLK_DSP_PCIN11" - ], - [ - "DSP_0_BCIN1", - "HCLK_DSP_BCIN1" - ], - [ - "DSP_0_PCIN37", - "HCLK_DSP_PCIN37" - ], - [ - "DSP_0_PCIN28", - "HCLK_DSP_PCIN28" - ], - [ - "DSP_0_PCIN29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_0_PCIN30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_0_PCIN15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_0_BCIN10", - "HCLK_DSP_BCIN10" - ], - [ - "DSP_0_BCIN16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_0_PCIN6", - "HCLK_DSP_PCIN6" - ], - [ - "DSP_0_BCIN2", - "HCLK_DSP_BCIN2" - ], - [ - "DSP_0_ACIN10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_0_PCIN47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_0_ACIN27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_0_ACIN9", - "HCLK_DSP_ACIN9" - ], - [ - "DSP_0_ACIN18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_0_PCIN5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_0_PCIN9", - "HCLK_DSP_PCIN9" - ], - [ - "DSP_0_PCIN42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_0_PCIN31", - "HCLK_DSP_PCIN31" - ], - [ - "DSP_0_PCIN10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_0_PCIN0", - "HCLK_DSP_PCIN0" - ], - [ - "DSP_0_PCIN40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_0_PCIN33", - "HCLK_DSP_PCIN33" - ], - [ - "DSP_0_CARRYCASCIN", - "HCLK_DSP_CARRYCASCIN" - ], - [ - "DSP_0_ACIN20", - "HCLK_DSP_ACIN20" - ], - [ - "DSP_0_ACIN14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_0_ACIN6", - "HCLK_DSP_ACIN6" - ], - [ - "DSP_0_PCIN20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_0_PCIN22", - "HCLK_DSP_PCIN22" - ], - [ - "DSP_0_PCIN18", - "HCLK_DSP_PCIN18" - ], - [ - "DSP_0_PCIN36", - "HCLK_DSP_PCIN36" - ], - [ - "DSP_0_PCIN38", - "HCLK_DSP_PCIN38" - ], - [ - "DSP_0_BCIN14", - "HCLK_DSP_BCIN14" - ], - [ - "DSP_0_PCIN1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_0_ACIN1", - "HCLK_DSP_ACIN1" - ], - [ - "DSP_0_ACIN24", - "HCLK_DSP_ACIN24" - ], - [ - "DSP_0_ACIN11", - "HCLK_DSP_ACIN11" - ], - [ - "DSP_0_PCIN41", - "HCLK_DSP_PCIN41" - ], - [ - "DSP_0_ACIN19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_0_PCIN14", - "HCLK_DSP_PCIN14" - ], - [ - "DSP_0_ACIN0", - "HCLK_DSP_ACIN0" - ], - [ - "DSP_0_PCIN24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_0_BCIN3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_0_PCIN8", - "HCLK_DSP_PCIN8" - ], - [ - "DSP_0_PCIN21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_0_PCIN4", - "HCLK_DSP_PCIN4" - ], - [ - "DSP_0_PCIN26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_0_ACIN15", - "HCLK_DSP_ACIN15" - ], - [ - "DSP_0_ACIN23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_0_BCIN6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_0_ACIN5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_0_PCIN17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_0_PCIN7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_0_BCIN0", - "HCLK_DSP_BCIN0" - ], - [ - "DSP_0_BCIN9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_0_ACIN26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_0_ACIN29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_0_ACIN12", - "HCLK_DSP_ACIN12" - ], - [ - "DSP_0_BCIN4", - "HCLK_DSP_BCIN4" - ], - [ - "DSP_0_PCIN32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_0_ACIN7", - "HCLK_DSP_ACIN7" - ], - [ - "DSP_0_PCIN19", - "HCLK_DSP_PCIN19" - ], - [ - "DSP_0_BCIN8", - "HCLK_DSP_BCIN8" - ], - [ - "DSP_0_ACIN17", - "HCLK_DSP_ACIN17" - ], - [ - "DSP_0_PCIN39", - "HCLK_DSP_PCIN39" - ], - [ - "DSP_0_ACIN22", - "HCLK_DSP_ACIN22" - ], - [ - "DSP_0_ACIN4", - "HCLK_DSP_ACIN4" - ], - [ - "DSP_0_BCIN7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_0_BCIN15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_0_ACIN21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_0_PCIN27", - "HCLK_DSP_PCIN27" - ], - [ - "DSP_0_PCIN35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_0_BCIN5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_0_PCIN16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_0_PCIN34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_0_MULTSIGNIN", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_0_BCIN11", - "HCLK_DSP_BCIN11" - ], - [ - "DSP_0_PCIN46", - "HCLK_DSP_PCIN46" - ], - [ - "DSP_0_PCIN3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_0_PCIN23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_0_PCIN44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_0_PCIN12", - "HCLK_DSP_PCIN12" - ] - ] - }, - { - "grid_deltas": [ - 0, - 4 - ], - "tile_types": [ - "BRKH_CLK", - "CLK_BUFG_BOT_R" - ], - "wire_pairs": [ - [ - "BRKH_CLK_R_CK_GCLK8", - "CLK_BUFG_CK_GCLK8" - ], - [ - "BRKH_CLK_R_CK_GCLK22", - "CLK_BUFG_CK_GCLK22" - ], - [ - "BRKH_CLK_R_CK_GCLK23", - "CLK_BUFG_CK_GCLK23" - ], - [ - "BRKH_CLK_R_CK_GCLK2", - "CLK_BUFG_CK_GCLK2" - ], - [ - "BRKH_CLK_R_CK_GCLK11", - "CLK_BUFG_CK_GCLK11" - ], - [ - "BRKH_CLK_R_CK_GCLK31", - "CLK_BUFG_CK_GCLK31" - ], - [ - "BRKH_CLK_R_CK_GCLK24", - "CLK_BUFG_CK_GCLK24" - ], - [ - "BRKH_CLK_R_CK_GCLK15", - "CLK_BUFG_CK_GCLK15" - ], - [ - "BRKH_CLK_R_CK_GCLK13", - "CLK_BUFG_CK_GCLK13" - ], - [ - "BRKH_CLK_R_CK_GCLK30", - "CLK_BUFG_CK_GCLK30" - ], - [ - "BRKH_CLK_R_CK_GCLK25", - "CLK_BUFG_CK_GCLK25" - ], - [ - "BRKH_CLK_R_CK_GCLK27", - "CLK_BUFG_CK_GCLK27" - ], - [ - "BRKH_CLK_R_CK_GCLK0", - "CLK_BUFG_CK_GCLK0" - ], - [ - "BRKH_CLK_R_CK_GCLK28", - "CLK_BUFG_CK_GCLK28" - ], - [ - "BRKH_CLK_R_CK_GCLK26", - "CLK_BUFG_CK_GCLK26" - ], - [ - "BRKH_CLK_R_CK_GCLK18", - "CLK_BUFG_CK_GCLK18" - ], - [ - "BRKH_CLK_R_CK_GCLK12", - "CLK_BUFG_CK_GCLK12" - ], - [ - "BRKH_CLK_R_CK_GCLK7", - "CLK_BUFG_CK_GCLK7" - ], - [ - "BRKH_CLK_R_CK_GCLK3", - "CLK_BUFG_CK_GCLK3" - ], - [ - "BRKH_CLK_R_CK_GCLK4", - "CLK_BUFG_CK_GCLK4" - ], - [ - "BRKH_CLK_R_CK_GCLK1", - "CLK_BUFG_CK_GCLK1" - ], - [ - "BRKH_CLK_R_CK_GCLK9", - "CLK_BUFG_CK_GCLK9" - ], - [ - "BRKH_CLK_R_CK_GCLK20", - "CLK_BUFG_CK_GCLK20" - ], - [ - "BRKH_CLK_R_CK_GCLK21", - "CLK_BUFG_CK_GCLK21" - ], - [ - "BRKH_CLK_R_CK_GCLK17", - "CLK_BUFG_CK_GCLK17" - ], - [ - "BRKH_CLK_R_CK_GCLK6", - "CLK_BUFG_CK_GCLK6" - ], - [ - "BRKH_CLK_R_CK_GCLK5", - "CLK_BUFG_CK_GCLK5" - ], - [ - "BRKH_CLK_R_CK_GCLK10", - "CLK_BUFG_CK_GCLK10" - ], - [ - "BRKH_CLK_R_CK_GCLK16", - "CLK_BUFG_CK_GCLK16" - ], - [ - "BRKH_CLK_R_CK_GCLK19", - "CLK_BUFG_CK_GCLK19" - ], - [ - "BRKH_CLK_R_CK_GCLK29", - "CLK_BUFG_CK_GCLK29" - ], - [ - "BRKH_CLK_R_CK_GCLK14", - "CLK_BUFG_CK_GCLK14" - ] - ] - }, - { - "grid_deltas": [ - 1, - -2 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_LH5_3", - "VBRK_LH5" - ], - [ - "CMT_TOP_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_LH1_3", - "VBRK_LH1" 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"HCLK_CMT_PHASEREF_BELOW0" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL4", - "HCLK_CMT_MUX_CLK_PLL4" - ], - [ - "CMT_PHASER_IN_D_RCLK3", - "HCLK_CMT_PHASERIN_RCLK3" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL3", - "HCLK_CMT_MUX_CLK_PLL3" - ], - [ - "CMT_PHASER_REF_CLKOUT_TOHCLK", - "HCLK_CMT_PREF_CLKOUT" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL5", - "HCLK_CMT_MUX_CLK_PLL5" - ], - [ - "CMT_R_TOP_UPPER_B_CLKIN1", - "HCLK_CMT_MUX_PLLE2_CLKIN1" - ], - [ - "CMT_PHY_CONTROL_IRANKA1", - "HCLK_CMT_PHY_CONTROL_IRANKA1" - ], - [ - "CMT_FREQ_PHASER_REFMUX_2", - "HCLK_CMT_FREQ_PHASER_REFMUX_2" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL7", - "HCLK_CMT_MUX_CLK_PLL7" - ], - [ - "CMT_PHY_CONTROL_ECALIB1", - "HCLK_CMT_ECALIB1" - ], - [ - "CMT_PHASER_UP_BUFMRCE_CE1", - "HCLK_CMT_BUFMR_CE1" - ], - [ - "CMT_PHASER_UP_PHASERREF_ABOVE1", - "HCLK_CMT_PHASEREF_ABOVE1" - ], - [ - "CMT_PHASER_UP_PHASERREF0", - "HCLK_CMT_BUFMR_PHASEREF0" - ], - [ - "PLL_CLK_FREQBB_REBUFOUT0", - "HCLK_CMT_FREQ_REF_NS0" - ], - [ - "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "HCLK_CMT_PREF_TMUXOUT" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL1", - "HCLK_CMT_MUX_CLK_PLL1" - ], - [ - "CMT_R_TOP_UPPER_B_CLKFBIN", - "HCLK_CMT_MUX_PLLE2_CLKFBIN" - ], - [ - "CMT_PHY_CONTROL_IRANKB0", - "HCLK_CMT_PHY_CONTROL_IRANKB0" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL6", - "HCLK_CMT_MUX_CLK_PLL6" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "DSP_R", - "HCLK_DSP_R" - ], - "wire_pairs": [ - [ - "DSP_PCOUT20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_ACOUT14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_PCOUT8", - "HCLK_DSP_PCIN8" - ], - [ - "DSP_PCOUT41", - "HCLK_DSP_PCIN41" - ], - [ - "DSP_PCOUT25", - "HCLK_DSP_PCIN25" - ], - [ - "DSP_ACOUT17", - "HCLK_DSP_ACIN17" - ], - [ - "DSP_BCOUT2", - "HCLK_DSP_BCIN2" - ], - [ - "DSP_PCOUT26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_ACOUT27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_ACOUT19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_BCOUT4", - "HCLK_DSP_BCIN4" - ], - [ - "DSP_BCOUT17", - "HCLK_DSP_BCIN17" - ], - [ - "DSP_BCOUT11", - "HCLK_DSP_BCIN11" - ], - [ - "DSP_PCOUT19", - "HCLK_DSP_PCIN19" - ], - [ - "DSP_PCOUT30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_ACOUT7", - "HCLK_DSP_ACIN7" - ], - [ - "DSP_ACOUT8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_PCOUT39", - "HCLK_DSP_PCIN39" - ], - [ - "DSP_PCOUT17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_PCOUT29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_ACOUT28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_PCOUT40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_PCOUT23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_PCOUT6", - "HCLK_DSP_PCIN6" - ], - [ - "DSP_PCOUT0", - "HCLK_DSP_PCIN0" - ], - [ - "DSP_ACOUT24", - "HCLK_DSP_ACIN24" - ], - [ - "DSP_ACOUT12", - "HCLK_DSP_ACIN12" - ], - [ - "DSP_BCOUT13", - "HCLK_DSP_BCIN13" - ], - [ - "DSP_PCOUT27", - "HCLK_DSP_PCIN27" - ], - [ - "DSP_PCOUT3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_ACOUT1", - "HCLK_DSP_ACIN1" - ], - [ - "DSP_PCOUT24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_PCOUT28", - "HCLK_DSP_PCIN28" - ], - [ - "DSP_PCOUT43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_ACOUT21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_PCOUT15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_PCOUT1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_PCOUT33", - "HCLK_DSP_PCIN33" - ], - [ - "DSP_BCOUT10", - "HCLK_DSP_BCIN10" - ], - [ - "DSP_ACOUT9", - "HCLK_DSP_ACIN9" - ], - [ - "DSP_PCOUT9", - "HCLK_DSP_PCIN9" - ], - [ - "DSP_BCOUT16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_BCOUT0", - "HCLK_DSP_BCIN0" - ], - [ - "DSP_PCOUT12", - "HCLK_DSP_PCIN12" - ], - [ - "DSP_ACOUT29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_PCOUT46", - "HCLK_DSP_PCIN46" - ], - [ - "DSP_PCOUT36", - "HCLK_DSP_PCIN36" - ], - [ - "DSP_ACOUT26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_ACOUT23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_PCOUT35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_PCOUT16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_ACOUT25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_PCOUT13", - "HCLK_DSP_PCIN13" - ], - [ - "DSP_PCOUT44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_BCOUT5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_CARRYCASCOUT", - "HCLK_DSP_CARRYCASCIN" - ], - [ - "DSP_MULTSIGNOUT", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_PCOUT22", - "HCLK_DSP_PCIN22" - ], - [ - "DSP_ACOUT15", - "HCLK_DSP_ACIN15" - ], - [ - "DSP_ACOUT18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_ACOUT13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_BCOUT3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_PCOUT7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_ACOUT2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_ACOUT11", - "HCLK_DSP_ACIN11" - ], - [ - "DSP_BCOUT8", - "HCLK_DSP_BCIN8" - ], - [ - "DSP_ACOUT6", - "HCLK_DSP_ACIN6" - ], - [ - "DSP_ACOUT10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_BCOUT12", - "HCLK_DSP_BCIN12" - ], - [ - "DSP_BCOUT6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_BCOUT1", - "HCLK_DSP_BCIN1" - ], - [ - "DSP_PCOUT18", - "HCLK_DSP_PCIN18" - ], - [ - "DSP_PCOUT2", - "HCLK_DSP_PCIN2" - ], - [ - "DSP_PCOUT32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_PCOUT38", - "HCLK_DSP_PCIN38" - ], - [ - "DSP_ACOUT22", - "HCLK_DSP_ACIN22" - ], - [ - "DSP_PCOUT5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_PCOUT21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_PCOUT34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_BCOUT9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_BCOUT15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_BCOUT14", - "HCLK_DSP_BCIN14" - ], - [ - "DSP_ACOUT0", - "HCLK_DSP_ACIN0" - ], - [ - "DSP_PCOUT11", - "HCLK_DSP_PCIN11" - ], - [ - "DSP_BCOUT7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_PCOUT10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_PCOUT42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_ACOUT20", - "HCLK_DSP_ACIN20" - ], - [ - "DSP_PCOUT4", - "HCLK_DSP_PCIN4" - ], - [ - "DSP_PCOUT45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_PCOUT14", - "HCLK_DSP_PCIN14" - ], - [ - "DSP_ACOUT3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_PCOUT47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_ACOUT4", - "HCLK_DSP_ACIN4" - ], - [ - "DSP_PCOUT31", - "HCLK_DSP_PCIN31" - ], - [ - "DSP_PCOUT37", - "HCLK_DSP_PCIN37" - ], - [ - "DSP_ACOUT5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_ACOUT16", - "HCLK_DSP_ACIN16" - ] - ] - }, - { - "grid_deltas": [ - -1, - 5 - ], - "tile_types": [ - "GTP_CHANNEL_0", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTPE2_LOGIC_OUTS_B8_0", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTPE2_IMUX43_0", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_LOGIC_OUTS_B19_0", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_IMUX12_0", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_LOGIC_OUTS_B13_0", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_CLK1_0", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX23_0", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX46_0", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_FAN3_0", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX3_0", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_LOGIC_OUTS_B15_0", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_BYP1_0", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_BYP6_0", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX18_0", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX19_0", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX22_0", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX4_0", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX0_0", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX13_0", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX17_0", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX34_0", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX27_0", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX45_0", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX29_0", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B12_0", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_IMUX16_0", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX44_0", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX42_0", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX31_0", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX36_0", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_LOGIC_OUTS_B23_0", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_CLK0_0", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX30_0", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX9_0", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_BYP0_0", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX24_0", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_LOGIC_OUTS_B20_0", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_LOGIC_OUTS_B9_0", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_CTRL1_0", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX8_0", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX2_0", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX40_0", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX33_0", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_BYP7_0", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX5_0", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX21_0", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX7_0", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_LOGIC_OUTS_B11_0", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTPE2_IMUX28_0", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX1_0", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_LOGIC_OUTS_B14_0", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_LOGIC_OUTS_B16_0", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_LOGIC_OUTS_B10_0", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_BYP3_0", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX6_0", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX37_0", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX39_0", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX14_0", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX20_0", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX10_0", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX11_0", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX26_0", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_BYP2_0", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_FAN6_0", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_FAN0_0", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX38_0", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX32_0", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_BYP4_0", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX15_0", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_CTRL0_0", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_FAN2_0", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_FAN4_0", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX47_0", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX41_0", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_FAN5_0", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_FAN1_0", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX25_0", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX35_0", - "VBRK_EXT_IMUX35" - ], - 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"VFRAME_IMUX23" - ], - [ - "CFG_CENTER_WW2END3_4", - "VFRAME_WW2END3" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B23_4", - "VFRAME_LOGIC_OUTS_B23" - ], - [ - "CFG_CENTER_WW4END0_4", - "VFRAME_WW4END0" - ], - [ - "CFG_CENTER_IMUX46_4", - "VFRAME_IMUX46" - ], - [ - "CFG_CENTER_IMUX27_4", - "VFRAME_IMUX27" - ], - [ - "CFG_CENTER_NE2A0_4", - "VFRAME_NE2A0" - ], - [ - "CFG_CENTER_NE4C2_4", - "VFRAME_NE4C2" - ], - [ - "CFG_CENTER_SW4END3_4", - "VFRAME_SW4END3" - ], - [ - "CFG_CENTER_WW4B2_4", - "VFRAME_WW4B2" - ], - [ - "CFG_CENTER_IMUX40_4", - "VFRAME_IMUX40" - ], - [ - "CFG_CENTER_WW4A0_4", - "VFRAME_WW4A0" - ], - [ - "CFG_CENTER_EE4C1_4", - "VFRAME_EE4C1" - ], - [ - "CFG_CENTER_IMUX4_4", - "VFRAME_IMUX4" - ], - [ - "CFG_CENTER_SW4END0_4", - "VFRAME_SW4END0" - ], - [ - "CFG_CENTER_WR1END2_4", - "VFRAME_WR1END2" - ], - [ - "CFG_CENTER_WR1END1_4", - "VFRAME_WR1END1" - ], - [ - "CFG_CENTER_IMUX8_4", - "VFRAME_IMUX8" - ], - [ - "CFG_CENTER_NW4END1_4", - "VFRAME_NW4END1" - ], - [ - "CFG_CENTER_WW2A1_4", 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"VFRAME_IMUX13" - ], - [ - "CFG_CENTER_WL1END2_4", - "VFRAME_WL1END2" - ], - [ - "CFG_CENTER_NE4BEG0_4", - "VFRAME_NE4BEG0" - ], - [ - "CFG_CENTER_IMUX28_4", - "VFRAME_IMUX28" - ], - [ - "CFG_CENTER_LH8_4", - "VFRAME_LH8" - ], - [ - "CFG_CENTER_IMUX10_4", - "VFRAME_IMUX10" - ], - [ - "CFG_CENTER_EE4B2_4", - "VFRAME_EE4B2" - ], - [ - "CFG_CENTER_NE4BEG3_4", - "VFRAME_NE4BEG3" - ], - [ - "CFG_CENTER_IMUX41_4", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_NW4A2_4", - "VFRAME_NW4A2" - ], - [ - "CFG_CENTER_EE2A3_4", - "VFRAME_EE2A3" - ], - [ - "CFG_CENTER_IMUX36_4", - "VFRAME_IMUX36" - ], - [ - "CFG_CENTER_EE4C2_4", - "VFRAME_EE4C2" - ], - [ - "CFG_CENTER_IMUX19_4", - "VFRAME_IMUX19" - ], - [ - "CFG_CENTER_IMUX18_4", - "VFRAME_IMUX18" - ], - [ - "CFG_CENTER_FAN1_4", - "VFRAME_FAN1" - ], - [ - "CFG_CENTER_IMUX33_4", - "VFRAME_IMUX33" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_CLB", - "HCLK_L" - ], - "wire_pairs": [ - [ - "HCLK_CLB_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_CK_IN2", - "HCLK_CK_IN2" - ], - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CLB_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK2" - ], - [ - "HCLK_CLB_CK_IN1", - "HCLK_CK_IN1" - ], - [ - "HCLK_CLB_PERFCLK2", - "HCLK_INT_PERFCLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ], - [ - "HCLK_CLB_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - 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"INT_INTERFACE_LH4", - "LH3" - ], - [ - "INT_INTERFACE_IMUX1", - "IMUX_L1" - ], - [ - "INT_INTERFACE_NE4BEG2", - "NE6A2" - ], - [ - "INT_INTERFACE_WW2A0", - "WW2BEG0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L18", - "LOGIC_OUTS_L18" - ], - [ - "INT_INTERFACE_IMUX22", - "IMUX_L22" - ], - [ - "INT_INTERFACE_WW2END1", - "WW2A1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L17", - "LOGIC_OUTS_L17" - ], - [ - "INT_INTERFACE_IMUX40", - "IMUX_L40" - ], - [ - "INT_INTERFACE_LH2", - "LH1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L23", - "LOGIC_OUTS_L23" - ], - [ - "INT_INTERFACE_NE4C0", - "NE6END0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L15", - "LOGIC_OUTS_L15" - ], - [ - "INT_INTERFACE_SW4A3", - "SW6BEG3" - ], - [ - "INT_INTERFACE_IMUX8", - "IMUX_L8" - ], - [ - "INT_INTERFACE_WW4C2", - "WW4B2" - ], - [ - "INT_INTERFACE_NE4C3", - "NE6END3" - ], - [ - "INT_INTERFACE_IMUX21", - "IMUX_L21" - ], - [ - "INT_INTERFACE_SE4C2", - "SE6END2" - ], - [ - "INT_INTERFACE_IMUX9", - "IMUX_L9" - ], - [ - "INT_INTERFACE_BYP1", - "BYP_L1" - ], - [ - "INT_INTERFACE_WW4B1", - "WW4A1" - ], - [ - "INT_INTERFACE_IMUX5", - "IMUX_L5" - ], - [ - "INT_INTERFACE_NW4A0", - "NW6BEG0" - ], - [ - "INT_INTERFACE_IMUX31", - "IMUX_L31" - ], - [ - "INT_INTERFACE_NW4END1", - "NW6E1" - ], - [ - "INT_INTERFACE_SE4BEG0", - "SE6A0" - ], - [ - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_PHASER_TO_IO_ICLK" - ], - [ - "INT_INTERFACE_WW4C1", - "WW4B1" - ], - [ - "INT_INTERFACE_IMUX15", - "IMUX_L15" - ], - [ - "INT_INTERFACE_IMUX16", - "IMUX_L16" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L14", - "LOGIC_OUTS_L14" - ], - [ - "INT_INTERFACE_EE4B3", - "EE4C3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L22", - "LOGIC_OUTS_L22" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "BRKH_CLK", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "BRKH_CLK_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "BRKH_CLK_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "BRKH_CLK_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "BRKH_CLK_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "BRKH_CLK_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "BRKH_CLK_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "BRKH_CLK_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "BRKH_CLK_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "BRKH_CLK_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "BRKH_CLK_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "BRKH_CLK_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "BRKH_CLK_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "BRKH_CLK_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "BRKH_CLK_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "BRKH_CLK_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "BRKH_CLK_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "BRKH_CLK_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "BRKH_CLK_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "BRKH_CLK_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "BRKH_CLK_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "BRKH_CLK_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "BRKH_CLK_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "BRKH_CLK_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "BRKH_CLK_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "BRKH_CLK_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "BRKH_CLK_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "BRKH_CLK_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "BRKH_CLK_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "BRKH_CLK_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "BRKH_CLK_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "BRKH_CLK_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "BRKH_CLK_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_BRAM", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "HCLK_BRAM_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_BRAM_CK_IN9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_BRAM_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_BRAM_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_BRAM_CK_IN0", - "HCLK_VBRK_MUX_CLK0" - ], - [ - "HCLK_BRAM_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_BRAM_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_BRAM_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_BRAM_CK_IN3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_BRAM_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_BRAM_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_BRAM_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_BRAM_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_BRAM_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_BRAM_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_BRAM_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "HCLK_BRAM_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_BRAM_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_BRAM_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_BRAM_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_BRAM_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_BRAM_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_BRAM_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_BRAM_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_BRAM_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_BRAM_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_BRAM_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_BRAM_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_BRAM_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_BRAM_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ] - ] - }, - { - "grid_deltas": [ - -1, - -1 - ], - "tile_types": [ - "GTP_CHANNEL_1", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTPE2_BYP5_6", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX17_6", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX40_6", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX16_6", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX0_6", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B7_6", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX36_6", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_IMUX26_6", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B6_6", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_LOGIC_OUTS_B14_6", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX44_6", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_LOGIC_OUTS_B13_6", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX35_6", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX13_6", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX38_6", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX8_6", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_FAN5_6", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_BYP4_6", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX9_6", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_BYP0_6", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_BYP6_6", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_LOGIC_OUTS_B5_6", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_IMUX33_6", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX6_6", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_LOGIC_OUTS_B4_6", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_BYP2_6", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_LOGIC_OUTS_B17_6", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX31_6", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_FAN6_6", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX47_6", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX20_6", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_FAN2_6", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX1_6", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_IMUX11_6", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_LOGIC_OUTS_B23_6", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_LOGIC_OUTS_B15_6", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_CLK1_6", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX14_6", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX37_6", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_BYP1_6", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX19_6", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_CTRL0_6", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_LOGIC_OUTS_B3_6", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_IMUX41_6", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX3_6", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_LOGIC_OUTS_B22_6", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_LOGIC_OUTS_B0_6", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_LOGIC_OUTS_B9_6", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX5_6", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX15_6", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX25_6", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_FAN0_6", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_LOGIC_OUTS_B10_6", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_LOGIC_OUTS_B19_6", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_IMUX2_6", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX34_6", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX45_6", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX10_6", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX12_6", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX24_6", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_CLK0_6", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_LOGIC_OUTS_B21_6", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_IMUX30_6", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX39_6", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX32_6", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_FAN4_6", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_LOGIC_OUTS_B2_6", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_IMUX42_6", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX46_6", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_LOGIC_OUTS_B12_6", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_IMUX28_6", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_BYP3_6", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX23_6", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX27_6", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_CTRL1_6", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX7_6", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX4_6", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_BYP7_6", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX18_6", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_FAN7_6", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX43_6", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_LOGIC_OUTS_B1_6", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_FAN1_6", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX29_6", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX21_6", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_FAN3_6", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX22_6", - "VBRK_EXT_IMUX22" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMV2" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_GCLK31", - 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"TERM_INT_LOGIC_OUTS_L_B14" - ], - [ - "IOI_CLK1_0", - "TERM_INT_CLK1" - ], - [ - "IOI_IMUX42_0", - "TERM_INT_IMUX42" - ], - [ - "IOI_IMUX13_0", - "TERM_INT_IMUX13" - ], - [ - "IOI_IMUX37_0", - "TERM_INT_IMUX37" - ], - [ - "IOI_IMUX39_0", - "TERM_INT_IMUX39" - ], - [ - "IOI_IMUX5_0", - "TERM_INT_IMUX5" - ], - [ - "IOI_LOGIC_OUTS11_0", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "IOI_IMUX27_0", - "TERM_INT_IMUX27" - ], - [ - "IOI_IMUX41_0", - "TERM_INT_IMUX41" - ], - [ - "IOI_LOGIC_OUTS23_0", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "IOI_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_LOGIC_OUTS8_0", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_IMUX1_0", - "TERM_INT_IMUX1" - ], - [ - "IOI_LOGIC_OUTS19_0", - "TERM_INT_LOGIC_OUTS_L_B19" - ], - [ - "IOI_IMUX38_0", - "TERM_INT_IMUX38" - ], - [ - "IOI_IMUX46_0", - "TERM_INT_IMUX46" - ], - [ - "IOI_BYP5_0", - "TERM_INT_BYP5" - ], - [ - "IOI_IMUX7_0", - "TERM_INT_IMUX7" - ], - [ - "IOI_IMUX3_0", - "TERM_INT_IMUX3" - ], - [ - "IOI_IMUX15_0", - "TERM_INT_IMUX15" - ], - [ - "IOI_BLOCK_OUTS2_0", - "TERM_INT_BLOCK_OUTS_L_B2" - ], - [ - "IOI_FAN1_0", - "TERM_INT_FAN1" - ], - [ - "IOI_PHASER_TO_IO_OCLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "IOI_IMUX40_0", - "TERM_INT_IMUX40" - ], - [ - "IOI_IMUX14_0", - "TERM_INT_IMUX14" - ], - [ - "IOI_IMUX28_0", - "TERM_INT_IMUX28" - ], - [ - "IOI_MONITOR_N", - "TERM_INT_MONITOR_N" - ], - [ - "IOI_IMUX17_0", - "TERM_INT_IMUX17" - ], - [ - "IOI_BYP6_0", - "TERM_INT_BYP6" - ], - [ - "IOI_LOGIC_OUTS18_0", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "IOI_IMUX32_0", - "TERM_INT_IMUX32" - ], - [ - "IOI_CTRL0_0", - "TERM_INT_CTRL0" - ], - [ - "IOI_LOGIC_OUTS0_0", - "TERM_INT_LOGIC_OUTS_L_B0" - ], - [ - "IOI_IMUX12_0", - "TERM_INT_IMUX12" - ], - [ - "IOI_IMUX44_0", - "TERM_INT_IMUX44" - ], - [ - "IOI_FAN5_0", - "TERM_INT_FAN5" - ], - [ - "IOI_IMUX20_0", - "TERM_INT_IMUX20" - ], - [ - "IOI_IMUX35_0", - "TERM_INT_IMUX35" - ], - [ - "IOI_BYP4_0", - "TERM_INT_BYP4" - ], - [ - "IOI_LOGIC_OUTS1_0", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_IMUX25_0", - "TERM_INT_IMUX25" - ], - [ - "IOI_IMUX31_0", - "TERM_INT_IMUX31" - ], - [ - "IOI_IMUX34_0", - "TERM_INT_IMUX34" - ], - [ - "IOI_BYP0_0", - "TERM_INT_BYP0" - ], - [ - "IOI_MONITOR_P", - "TERM_INT_MONITOR_P" - ], - [ - "IOI_FAN0_0", - "TERM_INT_FAN0" - ], - [ - "IOI_LOGIC_OUTS20_0", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_IMUX26_0", - "TERM_INT_IMUX26" - ], - [ - "IOI_IMUX6_0", - "TERM_INT_IMUX6" - ], - [ - "IOI_IMUX10_0", - "TERM_INT_IMUX10" - ], - [ - "IOI_LOGIC_OUTS2_0", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "IOI_BYP7_0", - "TERM_INT_BYP7" - ], - [ - "IOI_LOGIC_OUTS7_0", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_IMUX29_0", - "TERM_INT_IMUX29" - ], - [ - "IOI_IMUX4_0", - "TERM_INT_IMUX4" - ], - [ - "IOI_IMUX47_0", - "TERM_INT_IMUX47" - ], - [ - "IOI_IMUX45_0", - "TERM_INT_IMUX45" - ], - [ - "IOI_IMUX33_0", - "TERM_INT_IMUX33" - ], - [ - "IOI_FAN3_0", - "TERM_INT_FAN3" - ], - [ - "IOI_IMUX23_0", - "TERM_INT_IMUX23" - ], - [ - "IOI_LOGIC_OUTS5_0", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_BYP2_0", - "TERM_INT_BYP2" - ], - [ - "IOI_IMUX24_0", - "TERM_INT_IMUX24" - ], - [ - "IOI_LOGIC_OUTS10_0", - "TERM_INT_LOGIC_OUTS_L_B10" - ], - [ - "IOI_CLK0_0", - "TERM_INT_CLK0" - ], - [ - "IOI_IMUX16_0", - "TERM_INT_IMUX16" - ], - [ - "IOI_FAN2_0", - "TERM_INT_FAN2" - ], - [ - "IOI_IMUX0_0", - "TERM_INT_IMUX0" - ], - [ - "IOI_LOGIC_OUTS3_0", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_IMUX21_0", - "TERM_INT_IMUX21" - ], - [ - "IOI_LOGIC_OUTS15_0", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_FAN6_0", - "TERM_INT_FAN6" - ], - [ - "IOI_IMUX30_0", - "TERM_INT_IMUX30" - ], - [ - "IOI_BYP1_0", - "TERM_INT_BYP1" - ], - [ - "IOI_CTRL1_0", - "TERM_INT_CTRL1" - ], - [ - "IOI_IMUX9_0", - "TERM_INT_IMUX9" - ], - [ - "IOI_IMUX22_0", - "TERM_INT_IMUX22" - ], - [ - "IOI_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" - ], - [ - "IOI_BLOCK_OUTS0_0", - "TERM_INT_BLOCK_OUTS_L_B0" - ], - [ - "IOI_IMUX2_0", - "TERM_INT_IMUX2" - ], - [ - "IOI_LOGIC_OUTS9_0", - "TERM_INT_LOGIC_OUTS_L_B9" - ], - [ - "IOI_BYP3_0", - "TERM_INT_BYP3" - ], - [ - "IOI_FAN4_0", - "TERM_INT_FAN4" - ], - [ - "IOI_IMUX18_0", - "TERM_INT_IMUX18" - ], - [ - "IOI_IMUX8_0", - "TERM_INT_IMUX8" - ], - [ - "IOI_IMUX36_0", - "TERM_INT_IMUX36" - ], - [ - "IOI_IMUX19_0", - "TERM_INT_IMUX19" - ], - [ - "IOI_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLK" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "IO_INT_INTERFACE_R", - "R_TERM_INT" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_IMUX32", - "TERM_INT_IMUX32" - ], - [ - "INT_INTERFACE_IMUX29", - "TERM_INT_IMUX29" - ], - [ - "INT_INTERFACE_WW4END0", - "R_TERM_INT_WW4END0" - ], - [ - "INT_INTERFACE_SW2A0", - "R_TERM_INT_SW2A0" - ], - [ - "INT_INTERFACE_WW4B0", - "R_TERM_INT_WW4B0" - ], - [ - "INT_INTERFACE_BYP4", - "TERM_INT_BYP4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B22", - "TERM_INT_LOGIC_OUTS_L_B22" - ], - [ - "INT_INTERFACE_IMUX27", - "TERM_INT_IMUX27" - ], - [ - "INT_INTERFACE_NE4BEG3", - "R_TERM_INT_NW4A3" - ], - [ - "INT_INTERFACE_IMUX16", - "TERM_INT_IMUX16" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B11", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" - ], - [ - "INT_INTERFACE_WR1END3", - "R_TERM_INT_WR1END3" - ], - [ - "INT_INTERFACE_IMUX41", - "TERM_INT_IMUX41" - ], - [ - "INT_INTERFACE_IMUX20", - "TERM_INT_IMUX20" - ], - [ - "INT_INTERFACE_CTRL0", - "TERM_INT_CTRL0" - ], - [ - "INT_INTERFACE_MONITOR_N", - "TERM_INT_MONITOR_N" - ], - [ - "INT_INTERFACE_IMUX38", - "TERM_INT_IMUX38" - ], - [ - "INT_INTERFACE_IMUX10", - "TERM_INT_IMUX10" - ], - [ - "INT_INTERFACE_EE4C0", - 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"VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX25_2", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX18_2", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_LOGIC_OUTS_B9_2", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX20_2", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX4_2", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX3_2", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX44_2", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX36_2", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_IMUX21_2", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX9_2", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_BYP0_2", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_LOGIC_OUTS_B16_2", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_BYP5_2", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX24_2", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_IMUX31_2", - "VBRK_EXT_IMUX31" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_EE2A1_0", - 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"CLK_BUFG_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_BUFG_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_SW4END2_0", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_BUFG_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_0", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_0", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_BUFG_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_BUFG_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_BUFG_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_BUFG_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_BUFG_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_0", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_0", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_BUFG_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_BUFG_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_BUFG_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_BUFG_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_BUFG_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_BUFG_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_BUFG_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_BUFG_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_0", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_BUFG_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_BUFG_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_BUFG_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NW4END2_0", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "CLK_BUFG_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_BUFG_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_WL1END2_0", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_WR1END3_0", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_0", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_BUFG_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_BUFG_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_BUFG_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SE2A0_0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_0", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_BUFG_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_BUFG_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_BUFG_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_BUFG_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_LH9_0", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_SW4END0_0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_SE4C0_0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_BUFG_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_BUFG_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_BUFG_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_BUFG_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_BUFG_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ] - ] - }, - { - "grid_deltas": [ - 1, - 3 - ], - "tile_types": [ - "CMT_TOP_R_UPPER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WR1END3_1", - "VBRK_WR1END3" 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"CMT_TOP_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_LH6_1", - "VBRK_LH6" - ], - [ - "CMT_TOP_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_NE4BEG0_1", - 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"VBRK_LH2" - ], - [ - "CMT_TOP_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_LH1_1", - "VBRK_LH1" - ], - [ - "CMT_TOP_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WW4A3_1", "VBRK_WW4A3" ], [ - "CMT_TOP_LH11_1", - "VBRK_LH11" + "BRAM_WW4B0_3", + "VBRK_WW4B0" ], [ - "CMT_TOP_LH5_1", - "VBRK_LH5" + "BRAM_WW4B1_3", + "VBRK_WW4B1" ], [ - "CMT_TOP_EE4BEG3_1", - "VBRK_EE4BEG3" + "BRAM_WW4B2_3", + "VBRK_WW4B2" ], [ - "CMT_TOP_EE2BEG3_1", - "VBRK_EE2BEG3" + "BRAM_WW4B3_3", + "VBRK_WW4B3" ], [ - "CMT_TOP_WL1END1_1", - "VBRK_WL1END1" + "BRAM_WW4C0_3", + "VBRK_WW4C0" ], [ - "CMT_TOP_EE4A0_1", - "VBRK_EE4A0" + "BRAM_WW4C1_3", + "VBRK_WW4C1" ], [ - "CMT_TOP_ER1BEG3_1", - "VBRK_ER1BEG3" + "BRAM_WW4C2_3", + "VBRK_WW4C2" ], [ - "CMT_TOP_NW4A2_1", - "VBRK_NW4A2" + "BRAM_WW4C3_3", + "VBRK_WW4C3" ], [ - "CMT_TOP_LH9_1", - "VBRK_LH9" + "BRAM_WW4END0_3", + "VBRK_WW4END0" ], [ - "CMT_TOP_EE4B1_1", - "VBRK_EE4B1" + "BRAM_WW4END1_3", + "VBRK_WW4END1" ], [ - "CMT_TOP_WW2END2_1", - "VBRK_WW2END2" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "RIOI3", - "RIOI3_SING" - ], - "wire_pairs": [ - [ - "IOI_IOCLK1", - "IOI_SING_IOCLK1" - ], - [ - "IOI_IOCLK0", - "IOI_SING_IOCLK0" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_SING_LEAF_GCLK5" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_SING_RCLK_FORIO1" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_SING_LEAF_GCLK4" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_SING_LEAF_GCLK2" - ], - [ - "IOI_RCLK_FORIO0", - "IOI_SING_RCLK_FORIO0" - ], - [ - "IOI_IOCLK3", - "IOI_SING_IOCLK3" - ], - [ - "IOI_RCLK_FORIO3", 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"LOGIC_OUTS21", - "INT_INTERFACE_LOGIC_OUTS21" - ], - [ - "CLK1", - "INT_INTERFACE_CLK1" - ], - [ - "WR1END0", - "INT_INTERFACE_WR1END0" - ], - [ - "LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS8" - ], - [ - "WW4B0", - "INT_INTERFACE_WW4B0" - ], - [ - "LH11", - "INT_INTERFACE_LH11" - ], - [ - "LOGIC_OUTS5", - "INT_INTERFACE_LOGIC_OUTS5" - ], - [ - "FAN2", - "INT_INTERFACE_FAN2" - ], - [ - "IMUX19", - "PCIE_INT_INTERFACE_IMUX19" - ], - [ - "NW2END1", - "INT_INTERFACE_NW2A1" - ], - [ - "SE6BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "NE6E0", - "INT_INTERFACE_NE4C0" - ], - [ - "IMUX6", - "PCIE_INT_INTERFACE_IMUX6" - ], - [ - "WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "LOGIC_OUTS14", - "INT_INTERFACE_LOGIC_OUTS14" - ], - [ - "LH9", - "INT_INTERFACE_LH9" - ], - [ - "IMUX47", - "PCIE_INT_INTERFACE_IMUX47" - ], - [ - "IMUX43", - "PCIE_INT_INTERFACE_IMUX43" - ], - [ - "NE6BEG0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "BYP2", - "INT_INTERFACE_BYP2" - ], - [ - "EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "EE2BEG1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "WW4A2", - "INT_INTERFACE_WW4A2" - ], - [ - "EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "IMUX44", - "PCIE_INT_INTERFACE_IMUX44" - ], - [ - "IMUX46", - "PCIE_INT_INTERFACE_IMUX46" - ], - [ - "FAN3", - "INT_INTERFACE_FAN3" - ], - [ - "LOGIC_OUTS17", - "INT_INTERFACE_LOGIC_OUTS17" - ], - [ - "LOGIC_OUTS7", - "INT_INTERFACE_LOGIC_OUTS7" - ], - [ - "LH1", - "INT_INTERFACE_LH1" - ], - [ - "IMUX24", - "PCIE_INT_INTERFACE_IMUX24" - ], - [ - "IMUX10", - "PCIE_INT_INTERFACE_IMUX10" - ], - [ - "IMUX27", - "PCIE_INT_INTERFACE_IMUX27" - ], - [ - "LOGIC_OUTS20", - "INT_INTERFACE_LOGIC_OUTS20" - ], - [ - "IMUX45", - "PCIE_INT_INTERFACE_IMUX45" - ], - [ - "EE2BEG2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "IMUX30", - "PCIE_INT_INTERFACE_IMUX30" - ], - [ - "SE2A2", - "INT_INTERFACE_SE2A2" - ], - [ - "WW4B2", - "INT_INTERFACE_WW4B2" - ], - [ - "WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "SW6END2", - "INT_INTERFACE_SW4END2" - ], - [ - "LH3", - "INT_INTERFACE_LH3" - ], - [ - "NE6BEG2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "EE4A3", - "INT_INTERFACE_EE4A3" - ], - [ - "NE6E3", - "INT_INTERFACE_NE4C3" - ], - [ - "WW4B3", - "INT_INTERFACE_WW4B3" - ], - [ - "WW2A3", - "INT_INTERFACE_WW2A3" - ], - [ - "LH6", - "INT_INTERFACE_LH6" - ], - [ - "LOGIC_OUTS11", - "INT_INTERFACE_LOGIC_OUTS11" - ], - [ - "NW6A0", - "INT_INTERFACE_NW4A0" - ], - [ - "LH4", - "INT_INTERFACE_LH4" - ], - [ - "CTRL1", - "INT_INTERFACE_CTRL1" - ], - [ - "IMUX28", - "PCIE_INT_INTERFACE_IMUX28" - ], - [ - "IMUX32", - "PCIE_INT_INTERFACE_IMUX32" - ], - [ - "EE4BEG3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "FAN5", - "INT_INTERFACE_FAN5" - ], - [ - "NW6END2", - "INT_INTERFACE_NW4END2" - ], - [ - "LH12", - "INT_INTERFACE_LH12" - ], - [ - "NW6A3", - "INT_INTERFACE_NW4A3" - ], - [ - "EE4B1", - "INT_INTERFACE_EE4B1" - ], - [ - "EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "WL1END2", - "INT_INTERFACE_WL1END2" - ], - [ - "WW2END2", - "INT_INTERFACE_WW2END2" - ], - [ - "WW4B1", - "INT_INTERFACE_WW4B1" - ], - [ - "NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "EE2BEG0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "SW2END3", - "INT_INTERFACE_SW2A3" - ], - [ - "IMUX18", - "PCIE_INT_INTERFACE_IMUX18" - ], - [ - "ER1BEG1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "WL1END3", - "INT_INTERFACE_WL1END3" - ], - [ - "LH10", - "INT_INTERFACE_LH10" - ], - [ - "EE2A3", - "INT_INTERFACE_EE2A3" - ], - [ - "WW4END0", - "INT_INTERFACE_WW4END0" - ], - [ - "LOGIC_OUTS9", - "INT_INTERFACE_LOGIC_OUTS9" - ], - [ - "IMUX33", - "PCIE_INT_INTERFACE_IMUX33" - ], - [ - "IMUX15", - "PCIE_INT_INTERFACE_IMUX15" - ], - [ - "WW2A1", - "INT_INTERFACE_WW2A1" - ], - [ - "LOGIC_OUTS23", - "INT_INTERFACE_LOGIC_OUTS23" - ], - [ - "NE6BEG1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "NW6END1", - "INT_INTERFACE_NW4END1" - ], - [ - "IMUX12", - "PCIE_INT_INTERFACE_IMUX12" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_BUFG_REBUF_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_BUFG_REBUF_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_BUFG_REBUF_SW4END0_0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_BUFG_REBUF_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_BUFG_REBUF_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_BUFG_REBUF_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_BUFG_REBUF_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_BUFG_REBUF_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "CLK_BUFG_REBUF_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_BUFG_REBUF_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_BUFG_REBUF_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_BUFG_REBUF_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_BUFG_REBUF_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_REBUF_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_BUFG_REBUF_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_BUFG_REBUF_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_BUFG_REBUF_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_BUFG_REBUF_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_REBUF_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_REBUF_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_BUFG_REBUF_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_BUFG_REBUF_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_BUFG_REBUF_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_BUFG_REBUF_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_BUFG_REBUF_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_BUFG_REBUF_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_REBUF_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_BUFG_REBUF_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_REBUF_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_BUFG_REBUF_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "CLK_BUFG_REBUF_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_BUFG_REBUF_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_BUFG_REBUF_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_BUFG_REBUF_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_BUFG_REBUF_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_BUFG_REBUF_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_BUFG_REBUF_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_BUFG_REBUF_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_BUFG_REBUF_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_REBUF_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_BUFG_REBUF_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_BUFG_REBUF_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_REBUF_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_BUFG_REBUF_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_BUFG_REBUF_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_BUFG_REBUF_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_BUFG_REBUF_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_BUFG_REBUF_WR1END3_0", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_BUFG_REBUF_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_BUFG_REBUF_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_BUFG_REBUF_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_BUFG_REBUF_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_REBUF_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_BUFG_REBUF_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_BUFG_REBUF_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_BUFG_REBUF_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_BUFG_REBUF_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_BUFG_REBUF_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_BUFG_REBUF_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_BUFG_REBUF_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_BUFG_REBUF_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_BUFG_REBUF_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_BUFG_REBUF_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_BUFG_REBUF_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_BUFG_REBUF_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_BUFG_REBUF_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_BUFG_REBUF_SE2A0_0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_BUFG_REBUF_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_BUFG_REBUF_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_BUFG_REBUF_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_BUFG_REBUF_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_BUFG_REBUF_SE4C0_0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_BUFG_REBUF_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_BUFG_REBUF_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_BUFG_REBUF_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_REBUF_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_BUFG_REBUF_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_BUFG_REBUF_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_BUFG_REBUF_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_BUFG_REBUF_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_BUFG_REBUF_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_BUFG_REBUF_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_REBUF_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_BUFG_REBUF_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_BUFG_REBUF_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_BUFG_REBUF_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_BUFG_REBUF_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_BUFG_REBUF_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_BUFG_REBUF_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_BUFG_REBUF_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_BUFG_REBUF_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_BUFG_REBUF_SW4END2_0", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_BUFG_REBUF_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_BUFG_REBUF_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_BUFG_REBUF_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_BUFG_REBUF_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_BUFG_REBUF_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_BUFG_REBUF_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_REBUF_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_BUFG_REBUF_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_BUFG_REBUF_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_BUFG_REBUF_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_BUFG_REBUF_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_BUFG_REBUF_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_REBUF_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_REBUF_WL1END2_0", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_BUFG_REBUF_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_BUFG_REBUF_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_BUFG_REBUF_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_BUFG_REBUF_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_BUFG_REBUF_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_BUFG_REBUF_LH9_0", - "INT_INTERFACE_LH9" - ], - [ - "CLK_BUFG_REBUF_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_BUFG_REBUF_LH1_0", - "INT_INTERFACE_LH1" - ], - [ - "CLK_BUFG_REBUF_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_BUFG_REBUF_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_BUFG_REBUF_NW4END2_0", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_BUFG_REBUF_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_BUFG_REBUF_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_BUFG_REBUF_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_BUFG_REBUF_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_BUFG_REBUF_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" + "BRAM_WW4END2_3", + "VBRK_WW4END2" ], [ - "CLK_BUFG_REBUF_NW4A2_0", - "INT_INTERFACE_NW4A2" + "BRAM_WW4END3_3", + "VBRK_WW4END3" ] ] }, @@ -63397,11193 +21429,749 @@ -2 ], "tile_types": [ - "CLK_HROW_BOT_R", + "BRAM_R", "VBRK" ], "wire_pairs": [ [ - "CLK_HROW_EE4B1_5", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE2A0_5", + "BRAM_EE2A0_2", "VBRK_EE2A0" ], [ - "CLK_HROW_LH8_5", - "VBRK_LH8" - ], - [ - "CLK_HROW_SE4BEG3_5", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2END2_5", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_SW2A1_5", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_WL1END0_5", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_NW4END2_5", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_SE2A0_5", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WW4END2_5", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NW4END0_5", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_NW4A0_5", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_ER1BEG3_5", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE2BEG0_5", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4END0_5", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NE2A1_5", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG3_5", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WW4A1_5", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_WW4A2_5", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE4A1_5", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NW2A1_5", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_WW2END3_5", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_LH1_5", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4B2_5", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH3_5", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH7_5", - "VBRK_LH7" - ], - [ - "CLK_HROW_WW4A0_5", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_SW4A1_5", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_LH11_5", - "VBRK_LH11" - ], - [ - "CLK_HROW_NE4C2_5", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW4B3_5", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4C0_5", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_NW2A0_5", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WW4C2_5", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_EE4C1_5", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_EE4BEG3_5", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_LH2_5", - "VBRK_LH2" - ], - [ - "CLK_HROW_SW4A3_5", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WL1END3_5", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_NE2A3_5", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4C2_5", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_EE2A1_5", + "BRAM_EE2A1_2", "VBRK_EE2A1" ], [ - "CLK_HROW_ER1BEG0_5", - "VBRK_ER1BEG0" + "BRAM_EE2A2_2", + "VBRK_EE2A2" ], [ - "CLK_HROW_WR1END0_5", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4C0_5", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW4C1_5", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_NE4C3_5", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WR1END3_5", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_WW4C3_5", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_SE4BEG2_5", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SE4BEG0_5", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NE4C1_5", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NE4BEG2_5", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_EE2BEG2_5", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SW2A2_5", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4C3_5", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_SW4END0_5", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW4B2_5", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_WW2A1_5", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WL1END2_5", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_EE2BEG3_5", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WL1END1_5", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NE4BEG0_5", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_EE2A3_5", + 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- "PCIE_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "PCIE_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "PCIE_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "PCIE_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "PCIE_IMUX42_R_1", - "PCIE_INT_INTERFACE_IMUX_OUT42" - ], - [ - "PCIE_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "PCIE_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "PCIE_LOGIC_OUTS_B4_R_1", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "PCIE_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "PCIE_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "PCIE_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "PCIE_IMUX17_R_1", - "PCIE_INT_INTERFACE_IMUX_OUT17" - ], - [ - "PCIE_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "PCIE_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "PCIE_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "PCIE_FAN6_R_1", - "INT_INTERFACE_FAN6" - ], - [ - "PCIE_BYP4_R_1", - "INT_INTERFACE_BYP4" - ], - [ - "PCIE_IMUX3_R_1", - "PCIE_INT_INTERFACE_IMUX_OUT3" - ], - [ - "PCIE_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "PCIE_LOGIC_OUTS_B0_R_1", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "PCIE_LOGIC_OUTS_B11_R_1", - "INT_INTERFACE_LOGIC_OUTS_B11" - ], - [ - "PCIE_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "PCIE_IMUX5_R_1", - "PCIE_INT_INTERFACE_IMUX_OUT5" - ], - [ - "PCIE_IMUX13_R_1", - "PCIE_INT_INTERFACE_IMUX_OUT13" - ], - [ - "PCIE_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "PCIE_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "PCIE_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "PCIE_FAN5_R_1", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_FAN3_R_1", - "INT_INTERFACE_FAN3" - ], - [ - "PCIE_IMUX32_R_1", - "PCIE_INT_INTERFACE_IMUX_OUT32" - ] - ] - }, - { - "grid_deltas": [ - 1, - -2 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_EE4B1_5", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE2A0_5", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_LH8_5", - "VBRK_LH8" - ], - [ - "CLK_HROW_SE4BEG3_5", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2END2_5", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_SW2A1_5", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_WL1END0_5", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_NW4END2_5", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_SE2A0_5", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WW4END2_5", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NW4END0_5", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_NW4A0_5", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_ER1BEG3_5", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE2BEG0_5", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4END0_5", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NE2A1_5", + "BRAM_NE2A1_2", "VBRK_NE2A1" ], [ - "CLK_HROW_NE4BEG3_5", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WW4A1_5", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_WW4A2_5", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE4A1_5", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NW2A1_5", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_WW2END3_5", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_LH1_5", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4B2_5", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH3_5", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH7_5", - "VBRK_LH7" - ], - [ - "CLK_HROW_WW4A0_5", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_SW4A1_5", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_LH11_5", - "VBRK_LH11" - ], - [ - "CLK_HROW_NE4C2_5", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW4B3_5", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4C0_5", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_NW2A0_5", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WW4C2_5", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_EE4C1_5", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_EE4BEG3_5", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_LH2_5", - "VBRK_LH2" - ], - [ - "CLK_HROW_SW4A3_5", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WL1END3_5", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_NE2A3_5", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4C2_5", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_EE2A1_5", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_ER1BEG0_5", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WR1END0_5", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4C0_5", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW4C1_5", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_NE4C3_5", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WR1END3_5", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_WW4C3_5", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_SE4BEG2_5", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SE4BEG0_5", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NE4C1_5", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NE4BEG2_5", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_EE2BEG2_5", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SW2A2_5", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4C3_5", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_SW4END0_5", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW4B2_5", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_WW2A1_5", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WL1END2_5", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_EE2BEG3_5", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WL1END1_5", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NE4BEG0_5", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_EE2A3_5", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_EL1BEG1_5", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE4A3_5", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_SE4C1_5", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_LH10_5", - "VBRK_LH10" - ], - [ - "CLK_HROW_NE4BEG1_5", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WR1END2_5", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_NW4END3_5", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4A0_5", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_LH4_5", - "VBRK_LH4" - ], - [ - "CLK_HROW_SE2A3_5", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_WW2A2_5", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_LH5_5", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW2A3_5", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WW2A0_5", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4BEG1_5", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_NW4A2_5", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4END1_5", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SE4BEG1_5", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_EL1BEG3_5", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE2A2_5", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NW2A2_5", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WW2END1_5", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_NW4END1_5", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EE4BEG2_5", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EE4B3_5", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_SW4END2_5", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WW4B0_5", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SE4C2_5", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_ER1BEG2_5", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_NE2A2_5", + "BRAM_NE2A2_2", "VBRK_NE2A2" ], [ - "CLK_HROW_NW2A3_5", - "VBRK_NW2A3" + "BRAM_NE2A3_2", + "VBRK_NE2A3" ], [ - "CLK_HROW_LH12_5", - "VBRK_LH12" + "BRAM_NE4BEG0_2", + "VBRK_NE4BEG0" ], [ - "CLK_HROW_LH9_5", - "VBRK_LH9" + "BRAM_NE4BEG1_2", + "VBRK_NE4BEG1" ], [ - "CLK_HROW_EE4BEG0_5", - "VBRK_EE4BEG0" + "BRAM_NE4BEG2_2", + "VBRK_NE4BEG2" ], [ - "CLK_HROW_NE4C0_5", + "BRAM_NE4BEG3_2", + "VBRK_NE4BEG3" + ], + [ + "BRAM_NE4C0_2", "VBRK_NE4C0" ], [ - "CLK_HROW_SE2A1_5", - "VBRK_SE2A1" + "BRAM_NE4C1_2", + "VBRK_NE4C1" ], [ - "CLK_HROW_LH6_5", - "VBRK_LH6" + "BRAM_NE4C2_2", + "VBRK_NE4C2" ], [ - "CLK_HROW_EE4A2_5", - "VBRK_EE4A2" + "BRAM_NE4C3_2", + "VBRK_NE4C3" ], [ - "CLK_HROW_EE4A0_5", - "VBRK_EE4A0" + "BRAM_NW2A0_2", + "VBRK_NW2A0" ], [ - "CLK_HROW_EL1BEG0_5", - "VBRK_EL1BEG0" + "BRAM_NW2A1_2", + "VBRK_NW2A1" ], [ - "CLK_HROW_WW2A3_5", - "VBRK_WW2A3" + "BRAM_NW2A2_2", + "VBRK_NW2A2" ], [ - "CLK_HROW_SW4END3_5", - "VBRK_SW4END3" + "BRAM_NW2A3_2", + "VBRK_NW2A3" ], [ - "CLK_HROW_SE4C3_5", - "VBRK_SE4C3" + "BRAM_NW4A0_2", + "VBRK_NW4A0" ], [ - "CLK_HROW_WW4END3_5", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SE2A2_5", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_ER1BEG1_5", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_NW4A3_5", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW2END0_5", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SW2A0_5", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_NW4A1_5", + "BRAM_NW4A1_2", "VBRK_NW4A1" ], [ - "CLK_HROW_WW4B1_5", - "VBRK_WW4B1" + "BRAM_NW4A2_2", + "VBRK_NW4A2" ], [ - "CLK_HROW_EE4C0_5", - "VBRK_EE4C0" + "BRAM_NW4A3_2", + "VBRK_NW4A3" ], [ - "CLK_HROW_SW4A2_5", + "BRAM_NW4END0_2", + "VBRK_NW4END0" + ], + [ + "BRAM_NW4END1_2", + "VBRK_NW4END1" + ], + [ + "BRAM_NW4END2_2", + "VBRK_NW4END2" + ], + [ + "BRAM_NW4END3_2", + "VBRK_NW4END3" + ], + [ + "BRAM_SE2A0_2", + "VBRK_SE2A0" + ], + [ + "BRAM_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "BRAM_SE2A2_2", + "VBRK_SE2A2" + ], + [ + "BRAM_SE2A3_2", + "VBRK_SE2A3" + ], + [ + "BRAM_SE4BEG0_2", + "VBRK_SE4BEG0" + ], + [ + "BRAM_SE4BEG1_2", + "VBRK_SE4BEG1" + ], + [ + "BRAM_SE4BEG2_2", + "VBRK_SE4BEG2" + ], + [ + "BRAM_SE4BEG3_2", + "VBRK_SE4BEG3" + ], + [ + "BRAM_SE4C0_2", + "VBRK_SE4C0" + ], + [ + "BRAM_SE4C1_2", + "VBRK_SE4C1" + ], + [ + "BRAM_SE4C2_2", + "VBRK_SE4C2" + ], + [ + "BRAM_SE4C3_2", + "VBRK_SE4C3" + ], + [ + "BRAM_SW2A0_2", + "VBRK_SW2A0" + ], + [ + "BRAM_SW2A1_2", + "VBRK_SW2A1" + ], + [ + "BRAM_SW2A2_2", + "VBRK_SW2A2" + ], + [ + "BRAM_SW2A3_2", + "VBRK_SW2A3" + ], + [ + "BRAM_SW4A0_2", + "VBRK_SW4A0" + ], + [ + "BRAM_SW4A1_2", + "VBRK_SW4A1" + ], + [ + "BRAM_SW4A2_2", "VBRK_SW4A2" ], [ - "CLK_HROW_WW4A3_5", - "VBRK_WW4A3" + "BRAM_SW4A3_2", + "VBRK_SW4A3" ], [ - "CLK_HROW_EE2BEG1_5", - "VBRK_EE2BEG1" + "BRAM_SW4END0_2", + "VBRK_SW4END0" ], [ - "CLK_HROW_EE4B0_5", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WR1END1_5", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NE2A0_5", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_SW4END1_5", + "BRAM_SW4END1_2", "VBRK_SW4END1" ], [ - "CLK_HROW_EL1BEG2_5", - "VBRK_EL1BEG2" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "INT_INTERFACE_R", - "INT_R" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_LOGIC_OUTS19", - "LOGIC_OUTS19" - ], - [ - "INT_INTERFACE_EE4B0", - "EE4B0" - ], - [ - "INT_INTERFACE_BYP6", - "BYP6" - ], - [ - "INT_INTERFACE_ER1BEG2", - "ER1BEG2" - ], - [ - "INT_INTERFACE_SW4END1", - "SW6END1" - ], - [ - "INT_INTERFACE_WR1END0", - "WR1END0" - ], - [ - "INT_INTERFACE_LH12", - "LH12" - ], - [ - "INT_INTERFACE_SE4BEG2", - "SE6BEG2" - ], - [ - "INT_INTERFACE_NW2A1", - "NW2END1" - ], - [ - "INT_INTERFACE_EE2BEG0", - "EE2BEG0" - ], - [ - "INT_INTERFACE_WW4A3", - "WW4A3" - ], - [ - "INT_INTERFACE_IMUX46", - "IMUX46" - ], - [ - "INT_INTERFACE_EE2A2", - "EE2A2" - ], - [ - "INT_INTERFACE_NW2A3", - "NW2END3" - ], - [ - "INT_INTERFACE_SE2A0", - "SE2A0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS14", - "LOGIC_OUTS14" - ], - [ - "INT_INTERFACE_BYP7", - "BYP7" - ], - [ - "INT_INTERFACE_WW2END3", - "WW2END3" - ], - [ - "INT_INTERFACE_WL1END1", - "WL1END1" - ], - [ - "INT_INTERFACE_NE4BEG1", - "NE6BEG1" - ], - [ - "INT_INTERFACE_NW4END1", - "NW6END1" - ], - [ - "INT_INTERFACE_WW2END2", - "WW2END2" - ], - [ - "INT_INTERFACE_FAN7", - "FAN7" - ], - [ - "INT_INTERFACE_LOGIC_OUTS8", - "LOGIC_OUTS8" - ], - [ - "INT_INTERFACE_SE2A3", - "SE2A3" - ], - [ - "INT_INTERFACE_EE4A2", - "EE4A2" - ], - [ - "INT_INTERFACE_IMUX23", - "IMUX23" - ], - [ - "INT_INTERFACE_LOGIC_OUTS7", - "LOGIC_OUTS7" - ], - [ - "INT_INTERFACE_SE2A2", - "SE2A2" - ], - [ - "INT_INTERFACE_SE4C0", - "SE6E0" - ], - [ - "INT_INTERFACE_BYP3", - "BYP3" - ], - [ - "INT_INTERFACE_IMUX32", - "IMUX32" - ], - [ - "INT_INTERFACE_LOGIC_OUTS6", - "LOGIC_OUTS6" - ], - [ - "INT_INTERFACE_SE2A1", - "SE2A1" - ], - [ - "INT_INTERFACE_WW4END3", - "WW4END3" - ], - [ - "INT_INTERFACE_IMUX37", - "IMUX37" - ], - [ - "INT_INTERFACE_IMUX31", - "IMUX31" - ], - [ - "INT_INTERFACE_IMUX19", - "IMUX19" - ], - [ - "INT_INTERFACE_WW4C0", - "WW4C0" - ], - [ - "L_INT_INTER_DQS_IOTOPHASER", - "INT_DQS_IOTOPHASER" - ], - [ - "INT_INTERFACE_IMUX33", - "IMUX33" - ], - [ - "INT_INTERFACE_SW4END0", - "SW6END0" - ], - [ - "INT_INTERFACE_LH8", - "LH8" - ], - [ - "INT_INTERFACE_WW4B2", - "WW4B2" - ], - [ - "INT_INTERFACE_IMUX39", - "IMUX39" - ], - [ - "INT_INTERFACE_WW4END2", - "WW4END2" - ], - [ - "INT_INTERFACE_LH10", - "LH10" - ], - [ - "INT_INTERFACE_FAN6", - "FAN6" - ], - [ - "INT_INTERFACE_SE4C3", - "SE6E3" - ], - [ - "INT_INTERFACE_WL1END2", - "WL1END2" - ], - [ - "INT_INTERFACE_EE2A0", - "EE2A0" - ], - [ - "INT_INTERFACE_NW2A0", - "NW2END0" - ], - [ - "INT_INTERFACE_LH2", - "LH2" - ], - [ - "INT_INTERFACE_SW2A0", - "SW2END0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS4", - "LOGIC_OUTS4" - ], - [ - "INT_INTERFACE_SE4BEG0", - "SE6BEG0" - ], - [ - "INT_INTERFACE_IMUX38", - "IMUX38" - ], - [ - "INT_INTERFACE_LOGIC_OUTS2", - "LOGIC_OUTS2" - ], - [ - "INT_INTERFACE_SW4A0", - "SW6A0" - ], - [ - "INT_INTERFACE_IMUX11", - "IMUX11" - ], - [ - "INT_INTERFACE_WW4B0", - "WW4B0" - ], - [ - "INT_INTERFACE_WW4END1", - "WW4END1" - ], - [ - "INT_INTERFACE_WR1END3", - "WR1END3" - ], - [ - "INT_INTERFACE_IMUX17", - "IMUX17" - ], - [ - "INT_INTERFACE_EE4A0", - "EE4A0" - ], - [ - "INT_INTERFACE_WW2END0", - "WW2END0" - ], - [ - "INT_INTERFACE_SW4END2", - "SW6END2" - ], - [ - "INT_INTERFACE_IMUX36", - "IMUX36" - ], - [ - "INT_INTERFACE_LOGIC_OUTS13", - "LOGIC_OUTS13" - ], - [ - "INT_INTERFACE_NW4A2", - "NW6A2" - ], - [ - "INT_INTERFACE_SW4A1", - "SW6A1" - ], - [ - "INT_INTERFACE_IMUX22", - "IMUX22" - ], - [ - "INT_INTERFACE_IMUX42", - "IMUX42" - ], - [ - "INT_INTERFACE_FAN3", - "FAN3" - ], - [ - "INT_INTERFACE_EL1BEG1", - "EL1BEG1" - ], - [ - "INT_INTERFACE_WW4B1", - "WW4B1" - ], - [ - "INT_INTERFACE_IMUX35", - "IMUX35" - ], - [ - "INT_INTERFACE_FAN1", - "FAN1" - ], - [ - "INT_INTERFACE_LH11", - "LH11" - ], - [ - "INT_INTERFACE_IMUX20", - "IMUX20" - ], - [ - "INT_INTERFACE_BYP0", - "BYP0" - ], - [ - "INT_INTERFACE_IMUX0", - "IMUX0" - ], - [ - "INT_INTERFACE_MONITOR_N", - "MONITOR_N" - ], - [ - "INT_INTERFACE_WW4B3", - "WW4B3" - ], - [ - "INT_INTERFACE_NW4A3", - "NW6A3" - ], - [ - "INT_INTERFACE_CLK1", - "CLK1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS15", - "LOGIC_OUTS15" - ], - [ - "INT_INTERFACE_NW2A2", - "NW2END2" - ], - [ - "INT_INTERFACE_EE4BEG3", - "EE4BEG3" - ], - [ - "INT_INTERFACE_IMUX2", - "IMUX2" - ], - [ - "INT_INTERFACE_FAN5", - "FAN5" - ], - [ - "INT_INTERFACE_LOGIC_OUTS1", - "LOGIC_OUTS1" - ], - [ - "INT_INTERFACE_ER1BEG0", - "ER1BEG0" - ], - [ - "INT_INTERFACE_NE4C1", - "NE6E1" - ], - [ - "INT_INTERFACE_WL1END3", - "WL1END3" - ], - [ - "INT_INTERFACE_EE4BEG1", - "EE4BEG1" - ], - [ - "INT_INTERFACE_FAN0", - "FAN0" - ], - [ - "INT_INTERFACE_EE4B1", - "EE4B1" - ], - [ - "INT_INTERFACE_IMUX18", - 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- "SE6BEG1" - ], - [ - "INT_INTERFACE_IMUX28", - "IMUX28" - ], - [ - "INT_INTERFACE_EL1BEG2", - "EL1BEG2" - ], - [ - "INT_INTERFACE_NE2A0", - "NE2A0" - ], - [ - "INT_INTERFACE_WW4C3", - "WW4C3" - ], - [ - "INT_INTERFACE_IMUX25", - "IMUX25" - ], - [ - "INT_INTERFACE_IMUX34", - "IMUX34" - ], - [ - "INT_INTERFACE_LH9", - "LH9" - ], - [ - "INT_INTERFACE_LOGIC_OUTS22", - "LOGIC_OUTS22" - ], - [ - "INT_INTERFACE_LOGIC_OUTS16", - "LOGIC_OUTS16" - ], - [ - "INT_INTERFACE_LOGIC_OUTS9", - "LOGIC_OUTS9" - ], - [ - "INT_INTERFACE_LH4", - "LH4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS3", - "LOGIC_OUTS3" - ], - [ - "INT_INTERFACE_SE4BEG3", - "SE6BEG3" - ], - [ - "INT_INTERFACE_IMUX14", - "IMUX14" - ], - [ - "INT_INTERFACE_CTRL1", - "CTRL1" - ], - [ - "INT_INTERFACE_WW4A0", - "WW4A0" - ], - [ - "INT_INTERFACE_NW4END0", - "NW6END0" - ], - [ - "INT_INTERFACE_WW4C2", - "WW4C2" - ], - [ - "INT_INTERFACE_EE4A3", - "EE4A3" - ], - [ - "INT_INTERFACE_IMUX45", - "IMUX45" - ], - [ - "INT_INTERFACE_BYP4", - "BYP4" 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"INT_INTERFACE_SW2A0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS11_0", - "INT_INTERFACE_LOGIC_OUTS_B11" - ], - [ - "CMT_FIFO_L_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CMT_FIFO_WW4END1_0", - "INT_INTERFACE_WW4END1" - ] - ] - }, - { - "grid_deltas": [ - -1, -1 ], "tile_types": [ - "BRAM_L", + "BRAM_R", "VBRK" ], "wire_pairs": [ [ - "BRAM_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "BRAM_LH7_1", - "VBRK_LH7" + "BRAM_EE2A0_1", + "VBRK_EE2A0" ], [ "BRAM_EE2A1_1", "VBRK_EE2A1" ], [ - "BRAM_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "BRAM_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "BRAM_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "BRAM_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "BRAM_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "BRAM_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "BRAM_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "BRAM_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "BRAM_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "BRAM_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "BRAM_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "BRAM_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - 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"BRAM_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "BRAM_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "BRAM_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "BRAM_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "BRAM_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "BRAM_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "BRAM_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "BRAM_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "BRAM_NW4END1_1", - "VBRK_NW4END1" + "BRAM_EE2BEG1_1", + "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_1", "VBRK_EE2BEG2" ], + [ + "BRAM_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "BRAM_EE4A0_1", + "VBRK_EE4A0" + ], + [ + "BRAM_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "BRAM_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "BRAM_EE4A3_1", + "VBRK_EE4A3" + ], + [ + "BRAM_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "BRAM_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "BRAM_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "BRAM_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "BRAM_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "BRAM_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "BRAM_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "BRAM_EE4BEG3_1", + "VBRK_EE4BEG3" + ], [ "BRAM_EE4C0_1", "VBRK_EE4C0" ], [ - "BRAM_WW2END3_1", - "VBRK_WW2END3" + "BRAM_EE4C1_1", + "VBRK_EE4C1" ], [ - "BRAM_NE2A2_1", - "VBRK_NE2A2" + "BRAM_EE4C2_1", + "VBRK_EE4C2" ], [ - "BRAM_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "BRAM_LH4_1", - "VBRK_LH4" + "BRAM_EE4C3_1", + "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_1", "VBRK_EL1BEG0" ], + [ + "BRAM_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "BRAM_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "BRAM_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "BRAM_ER1BEG1_1", + "VBRK_ER1BEG1" + ], + [ + "BRAM_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "BRAM_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "BRAM_LH1_1", + "VBRK_LH1" + ], + [ + "BRAM_LH2_1", + "VBRK_LH2" + ], + [ + "BRAM_LH3_1", + "VBRK_LH3" + ], + [ + "BRAM_LH4_1", + "VBRK_LH4" + ], + [ + "BRAM_LH5_1", + "VBRK_LH5" + ], + [ + "BRAM_LH6_1", + "VBRK_LH6" + ], + [ + "BRAM_LH7_1", + "VBRK_LH7" + ], + [ + "BRAM_LH8_1", + "VBRK_LH8" + ], + [ + "BRAM_LH9_1", + "VBRK_LH9" + ], + [ + "BRAM_LH10_1", + "VBRK_LH10" + ], [ "BRAM_LH11_1", "VBRK_LH11" ], [ - "BRAM_EE2A2_1", - "VBRK_EE2A2" + "BRAM_LH12_1", + "VBRK_LH12" ], [ - "BRAM_NW4END3_1", - "VBRK_NW4END3" + "BRAM_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "BRAM_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "BRAM_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "BRAM_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "BRAM_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "BRAM_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "BRAM_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "BRAM_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "BRAM_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "BRAM_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "BRAM_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "BRAM_NE4C1_1", + "VBRK_NE4C1" ], [ "BRAM_NE4C2_1", @@ -74594,1636 +22182,792 @@ "VBRK_NE4C3" ], [ - "BRAM_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "BRAM_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "BRAM_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "BRAM_WW4B0_1", - "VBRK_WW4B0" + "BRAM_NW2A0_1", + "VBRK_NW2A0" ], [ "BRAM_NW2A1_1", "VBRK_NW2A1" ], - [ - "BRAM_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "BRAM_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "BRAM_LH9_1", - "VBRK_LH9" - ], - [ - "BRAM_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "BRAM_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "BRAM_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "BRAM_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "BRAM_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "BRAM_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "BRAM_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "BRAM_LH6_1", - "VBRK_LH6" - ], - [ - "BRAM_EE2BEG0_1", - "VBRK_EE2BEG0" - ], [ "BRAM_NW2A2_1", "VBRK_NW2A2" ], [ - "BRAM_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "BRAM_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "BRAM_LH12_1", - "VBRK_LH12" - ], - [ - "BRAM_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "BRAM_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "BRAM_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "BRAM_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "BRAM_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "BRAM_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "BRAM_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "BRAM_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "BRAM_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "BRAM_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "BRAM_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "BRAM_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "BRAM_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "BRAM_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "BRAM_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "BRAM_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "BRAM_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "BRAM_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "BRAM_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "BRAM_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "BRAM_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "BRAM_LH1_1", - "VBRK_LH1" - ], - [ - "BRAM_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "BRAM_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "BRAM_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "BRAM_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "BRAM_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "BRAM_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "BRAM_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "BRAM_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "BRAM_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "BRAM_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "BRAM_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "BRAM_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "BRAM_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "BRAM_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "BRAM_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "BRAM_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "BRAM_EE2BEG1_1", - "VBRK_EE2BEG1" + "BRAM_NW2A3_1", + "VBRK_NW2A3" ], [ "BRAM_NW4A0_1", "VBRK_NW4A0" ], [ - "BRAM_EE4BEG3_1", - "VBRK_EE4BEG3" + "BRAM_NW4A1_1", + "VBRK_NW4A1" ], [ - "BRAM_SW4END0_1", - "VBRK_SW4END0" + "BRAM_NW4A2_1", + "VBRK_NW4A2" ], [ - "BRAM_WR1END0_1", - "VBRK_WR1END0" + "BRAM_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "BRAM_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "BRAM_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "BRAM_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "BRAM_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "BRAM_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "BRAM_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "BRAM_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "BRAM_SE2A3_1", + "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_1", "VBRK_SE4BEG0" ], [ - "BRAM_LH5_1", - "VBRK_LH5" + "BRAM_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "BRAM_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "BRAM_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "BRAM_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "BRAM_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "BRAM_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "BRAM_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "BRAM_SW2A0_1", + "VBRK_SW2A0" + ], + [ + "BRAM_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "BRAM_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "BRAM_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "BRAM_SW4A0_1", + "VBRK_SW4A0" + ], + [ + "BRAM_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "BRAM_SW4A2_1", + "VBRK_SW4A2" + ], + [ + "BRAM_SW4A3_1", + "VBRK_SW4A3" + ], + [ + "BRAM_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "BRAM_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "BRAM_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "BRAM_SW4END3_1", + "VBRK_SW4END3" ], [ "BRAM_WL1END0_1", "VBRK_WL1END0" ], [ - "BRAM_LH3_1", - "VBRK_LH3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CMT_TOP_L_UPPER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_LH5_4", - "VBRK_LH5" - ], - [ - "CMT_TOP_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_LH11_4", - "VBRK_LH11" - ], - [ - "CMT_TOP_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_LH9_4", - "VBRK_LH9" - ], - [ - "CMT_TOP_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_LH12_4", - "VBRK_LH12" - ], - [ - "CMT_TOP_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NE2A2_4", - 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"VBRK_SW4END2" ], [ - "CFG_CENTER_SW4END3_4", - "VFRAME_SW4END3" + "BRAM_SW4END3_0", + "VBRK_SW4END3" ], [ - "CFG_CENTER_LOGIC_OUTS_B10_4", - "VFRAME_LOGIC_OUTS_B10" + "BRAM_WL1END0_0", + "VBRK_WL1END0" ], [ - "CFG_CENTER_LOGIC_OUTS_B12_4", - "VFRAME_LOGIC_OUTS_B12" + "BRAM_WL1END1_0", + "VBRK_WL1END1" ], [ - "CFG_CENTER_IMUX40_4", - "VFRAME_IMUX40" + "BRAM_WL1END2_0", + "VBRK_WL1END2" ], [ - "CFG_CENTER_WW4B2_4", - "VFRAME_WW4B2" + "BRAM_WL1END3_0", + "VBRK_WL1END3" ], [ - "CFG_CENTER_WW4A0_4", - "VFRAME_WW4A0" + "BRAM_WR1END0_0", + "VBRK_WR1END0" ], [ - "CFG_CENTER_EE4C1_4", - "VFRAME_EE4C1" + "BRAM_WR1END1_0", + "VBRK_WR1END1" ], [ - "CFG_CENTER_IMUX4_4", - "VFRAME_IMUX4" + "BRAM_WR1END2_0", + "VBRK_WR1END2" ], [ - "CFG_CENTER_SW4END0_4", - "VFRAME_SW4END0" + "BRAM_WR1END3_0", + "VBRK_WR1END3" ], [ - "CFG_CENTER_WR1END2_4", - "VFRAME_WR1END2" + "BRAM_WW2A0_0", + "VBRK_WW2A0" ], [ - "CFG_CENTER_WR1END1_4", - "VFRAME_WR1END1" + "BRAM_WW2A1_0", + "VBRK_WW2A1" ], [ - "CFG_CENTER_IMUX8_4", - "VFRAME_IMUX8" + "BRAM_WW2A2_0", + "VBRK_WW2A2" ], [ - "CFG_CENTER_NW4END1_4", - "VFRAME_NW4END1" + "BRAM_WW2A3_0", + "VBRK_WW2A3" ], [ - "CFG_CENTER_WW2A1_4", - "VFRAME_WW2A1" + "BRAM_WW2END0_0", + "VBRK_WW2END0" ], [ - "CFG_CENTER_WW4A3_4", - "VFRAME_WW4A3" + "BRAM_WW2END1_0", + "VBRK_WW2END1" ], [ - "CFG_CENTER_EE2BEG1_4", - "VFRAME_EE2BEG1" + "BRAM_WW2END2_0", + "VBRK_WW2END2" ], [ - "CFG_CENTER_NE4C0_4", - "VFRAME_NE4C0" + "BRAM_WW2END3_0", + "VBRK_WW2END3" ], [ - "CFG_CENTER_LH12_4", - "VFRAME_LH12" + "BRAM_WW4A0_0", + "VBRK_WW4A0" ], [ - "CFG_CENTER_LOGIC_OUTS_B14_4", - "VFRAME_LOGIC_OUTS_B14" + "BRAM_WW4A1_0", + "VBRK_WW4A1" ], [ - "CFG_CENTER_SW4A0_4", - "VFRAME_SW4A0" + "BRAM_WW4A2_0", + "VBRK_WW4A2" ], [ - "CFG_CENTER_IMUX7_4", - "VFRAME_IMUX7" + "BRAM_WW4A3_0", + "VBRK_WW4A3" ], [ - "CFG_CENTER_SW4A2_4", - "VFRAME_SW4A2" + "BRAM_WW4B0_0", + "VBRK_WW4B0" ], [ - "CFG_CENTER_WW4B0_4", - "VFRAME_WW4B0" + "BRAM_WW4B1_0", + "VBRK_WW4B1" ], [ - "CFG_CENTER_BYP0_4", - "VFRAME_BYP0" + "BRAM_WW4B2_0", + "VBRK_WW4B2" ], [ - "CFG_CENTER_EE4A3_4", - "VFRAME_EE4A3" + "BRAM_WW4B3_0", + "VBRK_WW4B3" ], [ - "CFG_CENTER_EE4BEG0_4", - "VFRAME_EE4BEG0" + "BRAM_WW4C0_0", + "VBRK_WW4C0" ], [ - "CFG_CENTER_BYP1_4", - "VFRAME_BYP1" + "BRAM_WW4C1_0", + "VBRK_WW4C1" ], [ - "CFG_CENTER_LH10_4", - "VFRAME_LH10" + "BRAM_WW4C2_0", + "VBRK_WW4C2" ], [ - "CFG_CENTER_SE4C1_4", - "VFRAME_SE4C1" + "BRAM_WW4C3_0", + "VBRK_WW4C3" ], [ - "CFG_CENTER_IMUX25_4", - "VFRAME_IMUX25" + "BRAM_WW4END0_0", + "VBRK_WW4END0" ], [ - "CFG_CENTER_IMUX29_4", - "VFRAME_IMUX29" + "BRAM_WW4END1_0", + "VBRK_WW4END1" ], [ - "CFG_CENTER_SW2A0_4", - "VFRAME_SW2A0" + "BRAM_WW4END2_0", + "VBRK_WW4END2" ], [ - "CFG_CENTER_LOGIC_OUTS_B18_4", - "VFRAME_LOGIC_OUTS_B18" - ], - [ - "CFG_CENTER_SE2A0_4", - "VFRAME_SE2A0" - ], - [ - "CFG_CENTER_BYP6_4", - "VFRAME_BYP6" - ], - [ - "CFG_CENTER_LH9_4", - "VFRAME_LH9" - ], - [ - "CFG_CENTER_EE4BEG3_4", - "VFRAME_EE4BEG3" - ], - [ - "CFG_CENTER_CLK0_4", - "VFRAME_CLK0" - ], - [ - "CFG_CENTER_SE4C0_4", - "VFRAME_SE4C0" - ], - [ - "CFG_CENTER_SW2A1_4", - "VFRAME_SW2A1" - ], - [ - "CFG_CENTER_WR1END0_4", - "VFRAME_WR1END0" - ], - [ - "CFG_CENTER_IMUX9_4", - "VFRAME_IMUX9" - ], - [ - "CFG_CENTER_IMUX47_4", - "VFRAME_IMUX47" - ], - [ - "CFG_CENTER_NW2A1_4", - "VFRAME_NW2A1" - ], - [ - "CFG_CENTER_WW2A0_4", - "VFRAME_WW2A0" - ], - [ - "CFG_CENTER_NW4END3_4", - "VFRAME_NW4END3" - ], - [ - "CFG_CENTER_SW4END2_4", - "VFRAME_SW4END2" - ], - [ - "CFG_CENTER_SE4C3_4", - "VFRAME_SE4C3" - ], - [ - "CFG_CENTER_NW4A3_4", - "VFRAME_NW4A3" - ], - [ - "CFG_CENTER_SE2A2_4", - "VFRAME_SE2A2" - ], - [ - "CFG_CENTER_FAN5_4", - "VFRAME_FAN5" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B22_4", - "VFRAME_LOGIC_OUTS_B22" - ], - [ - "CFG_CENTER_NE4C3_4", - "VFRAME_NE4C3" - ], - [ - "CFG_CENTER_IMUX35_4", - "VFRAME_IMUX35" - ], - [ - "CFG_CENTER_ER1BEG1_4", - "VFRAME_ER1BEG1" - ], - [ - "CFG_CENTER_EE4C0_4", - "VFRAME_EE4C0" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B21_4", - "VFRAME_LOGIC_OUTS_B21" - ], - [ - "CFG_CENTER_IMUX42_4", - "VFRAME_IMUX42" - ], - [ - "CFG_CENTER_NE2A2_4", - "VFRAME_NE2A2" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B13_4", - "VFRAME_LOGIC_OUTS_B13" - ], - [ - "CFG_CENTER_IMUX2_4", - "VFRAME_IMUX2" - ], - [ - "CFG_CENTER_WW4C1_4", - "VFRAME_WW4C1" - ], - [ - "CFG_CENTER_BYP3_4", - "VFRAME_BYP3" - ], - [ - "CFG_CENTER_NW2A3_4", - "VFRAME_NW2A3" - ], - [ - "CFG_CENTER_WR1END3_4", - "VFRAME_WR1END3" - ], - [ - "CFG_CENTER_IMUX31_4", - "VFRAME_IMUX31" - ], - [ - "CFG_CENTER_SW2A2_4", - "VFRAME_SW2A2" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B11_4", - "VFRAME_LOGIC_OUTS_B11" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B19_4", - "VFRAME_LOGIC_OUTS_B19" - ], - [ - "CFG_CENTER_IMUX3_4", - "VFRAME_IMUX3" - ], - [ - "CFG_CENTER_FAN7_4", - "VFRAME_FAN7" - ], - [ - "CFG_CENTER_NW4END0_4", - "VFRAME_NW4END0" - ], - [ - "CFG_CENTER_NW2A0_4", - "VFRAME_NW2A0" - ], - [ - "CFG_CENTER_WL1END3_4", - "VFRAME_WL1END3" - ], - [ - "CFG_CENTER_EE4B0_4", - "VFRAME_EE4B0" - ], - [ - "CFG_CENTER_ER1BEG2_4", - "VFRAME_ER1BEG2" - ], - [ - "CFG_CENTER_EE2BEG2_4", - "VFRAME_EE2BEG2" - ], - [ - "CFG_CENTER_IMUX44_4", - "VFRAME_IMUX44" - ], - [ - "CFG_CENTER_WW4A2_4", - "VFRAME_WW4A2" - ], - [ - "CFG_CENTER_IMUX39_4", - "VFRAME_IMUX39" - ], - [ - "CFG_CENTER_LH3_4", - "VFRAME_LH3" - ], - [ - "CFG_CENTER_EE2A2_4", - "VFRAME_EE2A2" - ], - [ - "CFG_CENTER_WW2A2_4", - "VFRAME_WW2A2" - ], - [ - "CFG_CENTER_NE4C1_4", - "VFRAME_NE4C1" - ], - [ - "CFG_CENTER_WW4C2_4", - "VFRAME_WW4C2" - ], - [ - "CFG_CENTER_EL1BEG0_4", - "VFRAME_EL1BEG0" - ], - [ - "CFG_CENTER_SW2A3_4", - "VFRAME_SW2A3" - ], - [ - "CFG_CENTER_IMUX34_4", - "VFRAME_IMUX34" - ], - [ - "CFG_CENTER_IMUX0_4", - "VFRAME_IMUX0" - ], - [ - "CFG_CENTER_IMUX15_4", - "VFRAME_IMUX15" - ], - [ - "CFG_CENTER_EE2BEG0_4", - "VFRAME_EE2BEG0" - ], - [ - "CFG_CENTER_LH1_4", - "VFRAME_LH1" - ], - [ - "CFG_CENTER_EE4A1_4", - "VFRAME_EE4A1" - ], - [ - "CFG_CENTER_IMUX32_4", - "VFRAME_IMUX32" - ], - [ - "CFG_CENTER_IMUX20_4", - "VFRAME_IMUX20" - ], - [ - "CFG_CENTER_IMUX45_4", - "VFRAME_IMUX45" - ], - [ - "CFG_CENTER_IMUX38_4", - "VFRAME_IMUX38" - ], - [ - "CFG_CENTER_IMUX13_4", - "VFRAME_IMUX13" - ], - [ - "CFG_CENTER_WL1END2_4", - "VFRAME_WL1END2" - ], - [ - "CFG_CENTER_NE4BEG0_4", - "VFRAME_NE4BEG0" - ], - [ - "CFG_CENTER_IMUX28_4", - "VFRAME_IMUX28" - ], - [ - "CFG_CENTER_LH8_4", - "VFRAME_LH8" - ], - [ - "CFG_CENTER_IMUX10_4", - "VFRAME_IMUX10" - ], - [ - "CFG_CENTER_EE4B2_4", - "VFRAME_EE4B2" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B16_4", - "VFRAME_LOGIC_OUTS_B16" - ], - [ - "CFG_CENTER_NE4BEG3_4", - "VFRAME_NE4BEG3" - ], - [ - "CFG_CENTER_IMUX41_4", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_NW4A2_4", - "VFRAME_NW4A2" - ], - [ - "CFG_CENTER_EE2A3_4", - "VFRAME_EE2A3" - ], - [ - "CFG_CENTER_IMUX36_4", - "VFRAME_IMUX36" - ], - [ - "CFG_CENTER_EE4C2_4", - "VFRAME_EE4C2" - ], - [ - "CFG_CENTER_IMUX19_4", - "VFRAME_IMUX19" - ], - [ - "CFG_CENTER_IMUX18_4", - "VFRAME_IMUX18" - ], - [ - "CFG_CENTER_FAN1_4", - "VFRAME_FAN1" - ], - [ - "CFG_CENTER_IMUX33_4", - "VFRAME_IMUX33" + "BRAM_WW4END3_0", + "VBRK_WW4END3" ] ] }, @@ -76238,352 +22982,72 @@ ], "wire_pairs": [ [ - "B_TERM_UTURN_INT_SW2BEG3", - "NW2A0" - ], - [ - "B_TERM_UTURN_INT_SE6A0", - "NE6B3" - ], - [ - "B_TERM_UTURN_INT_LV_L9", - "LV_L10" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "FAN_BOUNCE2" - ], - [ - "B_TERM_UTURN_INT_SE6D3", - "NE6E0" - ], - [ - "B_TERM_UTURN_INT_SR1BEG2", - "NL1END1" - ], - [ - "B_TERM_UTURN_INT_LVB_L0", - "LVB_L1" - ], - [ - "B_TERM_UTURN_INT_SS6C1", - "SS6C1" - ], - [ - "B_TERM_UTURN_INT_SS6B3", - "SS6B3" - ], - [ - "B_TERM_UTURN_INT_SL1BEG3", - "NR1END0" - ], - [ - "B_TERM_UTURN_INT_SE2BEG1", - "NE2A2" - ], - [ - "B_TERM_UTURN_INT_SS2BEG1", - "NN2A2" - ], - [ - "B_TERM_UTURN_INT_SS6BEG3", - "NN6A0" - ], - [ - "B_TERM_UTURN_INT_SS6D1", - "SS6D1" - ], - [ - "B_TERM_UTURN_INT_LV_L5", - "LV_L14" - ], - [ - "B_TERM_UTURN_INT_SW6D0", - "SW6D0" - ], - [ - "B_TERM_UTURN_INT_SW6B1", - "SW6B1" - ], - [ - "B_TERM_UTURN_INT_SL1BEG0", - "NR1END3" - ], - [ - "B_TERM_UTURN_INT_SW6A3", - "NW6B0" - ], - [ - "B_TERM_UTURN_INT_SS6E2", - "SS6E2" - ], - [ - "B_TERM_UTURN_INT_SW6D1", - "NW6E2" - ], - [ - "B_TERM_UTURN_INT_SS2A3", - "NN2END0" - ], - [ - "B_TERM_UTURN_INT_SR1BEG1", - "SR1BEG1" - ], - [ - "B_TERM_UTURN_INT_SW2BEG1", - "SW2BEG1" - ], - [ - "B_TERM_UTURN_INT_SE6C0", - "NE6D3" - ], - [ - "B_TERM_UTURN_INT_LVB_L5", - "LVB_L6" - ], - [ - "B_TERM_UTURN_INT_LV_L8", - "LV_L11" - ], - [ - "B_TERM_UTURN_INT_SE6D1", - "NE6E2" - ], - [ - "B_TERM_UTURN_INT_SS6D2", - "NN6E1" - ], - [ - "B_TERM_UTURN_INT_SW6A2", - "NW6B1" - ], - [ - "B_TERM_UTURN_INT_SS6C0", - "NN6D3" - ], - [ - "B_TERM_UTURN_INT_SW6C0", - "NW6D3" - ], - [ - "B_TERM_UTURN_INT_SS6E3", - "NN6END0" - ], - [ - "B_TERM_UTURN_INT_SE2BEG0", - "NE2A3" - ], - [ - "B_TERM_UTURN_INT_SW6D2", - "SW6D2" - ], - [ - "B_TERM_UTURN_INT_SS6BEG1", - "SS6BEG1" - ], - [ - "B_TERM_UTURN_INT_SS6BEG0", - "NN6A3" - ], - [ - "B_TERM_UTURN_INT_SE6A0", - "SE6A0" - ], - [ - "B_TERM_UTURN_INT_SE6C3", - "SE6C3" - ], - [ - "B_TERM_UTURN_INT_SE6B2", - "NE6C1" - ], - [ - "B_TERM_UTURN_INT_LV_L4", - "LV_L4" - ], - [ - "B_TERM_UTURN_INT_SS6B2", - "NN6C1" - ], - [ - "B_TERM_UTURN_INT_SL1BEG3", - "SL1BEG3" - ], - [ - "B_TERM_UTURN_INT_SS6E1", - "SS6E1" - ], - [ - "B_TERM_UTURN_INT_SE2BEG1", - "SE2BEG1" - ], - [ - "B_TERM_UTURN_INT_SE6C3", - "NE6D0" - ], - [ - "B_TERM_UTURN_INT_WR1END0", - "WR1END0" - ], - [ - "B_TERM_UTURN_INT_SW6B3", - "SW6B3" - ], - [ - "B_TERM_UTURN_INT_SE6B3", - "NE6C0" - ], - [ - "B_TERM_UTURN_INT_SS6A3", - "NN6B0" - ], - [ - "B_TERM_UTURN_INT_ER1END_N3_3", - "ER1END_N3_3" - ], - [ - "B_TERM_UTURN_INT_WR1END0", - "WL1END_N1_3" - ], - [ - "B_TERM_UTURN_INT_SW6A0", - "NW6B3" - ], - [ - "B_TERM_UTURN_INT_SW6B2", - "SW6B2" - ], - [ - "B_TERM_UTURN_INT_SS6C2", - "NN6D1" - ], - [ - "B_TERM_UTURN_INT_SW2BEG1", - "NW2A2" - ], - [ - "B_TERM_UTURN_INT_SW2BEG0", - "SW2BEG0" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "BYP_BOUNCE_N3_3" - ], - [ - "B_TERM_UTURN_INT_SS2BEG2", - "SS2BEG2" - ], - [ - "B_TERM_UTURN_INT_SE6D3", - "SE6D3" - ], - [ - "B_TERM_UTURN_INT_SE6C2", - "NE6D1" - ], - [ - "B_TERM_UTURN_INT_SS2BEG1", - "SS2BEG1" - ], - [ - "B_TERM_UTURN_INT_SS6A1", - "SS6A1" - ], - [ - "B_TERM_UTURN_INT_ER1END_N3_3", - "EL1END0" - ], - [ - "B_TERM_UTURN_INT_SL1BEG1", - "NR1END2" - ], - [ - "B_TERM_UTURN_INT_SS6C3", - "SS6C3" - ], - [ - "B_TERM_UTURN_INT_SW6END_N0_3", - "NW6END0" - ], - [ - "B_TERM_UTURN_INT_SW6C1", - "SW6C1" - ], - [ - "B_TERM_UTURN_INT_SS6D3", - "SS6D3" - ], - [ - "B_TERM_UTURN_INT_LV_L8", - "LV_L8" - ], - [ - "B_TERM_UTURN_INT_SE6B3", - "SE6B3" - ], - [ - "B_TERM_UTURN_INT_SW6B2", - "NW6C1" - ], - [ - "B_TERM_UTURN_INT_SW2BEG2", - "NW2A1" - ], - [ - "B_TERM_UTURN_INT_LV_L3", - "LV_L16" - ], - [ - "B_TERM_UTURN_INT_SW6C2", - "SW6C2" - ], - [ - "B_TERM_UTURN_INT_LV_L7", - "LV_L12" - ], - [ - "B_TERM_UTURN_INT_SS6E1", - "NN6END2" - ], - [ - "B_TERM_UTURN_INT_SW6B0", - "NW6C3" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE0", - "BYP_BOUNCE_N3_7" - ], - [ - "B_TERM_UTURN_INT_SE2BEG2", - "SE2BEG2" - ], - [ - "B_TERM_UTURN_INT_SS6BEG2", - "SS6BEG2" - ], - [ - "B_TERM_UTURN_INT_SE6C1", - "SE6C1" + "B_TERM_UTURN_INT_ER1BEG0", + "EL1BEG_N3" ], [ "B_TERM_UTURN_INT_ER1BEG0", "ER1BEG0" ], [ - "B_TERM_UTURN_INT_LV_L2", - "LV_L2" + "B_TERM_UTURN_INT_ER1END_N3_3", + "EL1END0" ], [ - "B_TERM_UTURN_INT_LV_L6", - "LV_L13" + "B_TERM_UTURN_INT_ER1END_N3_3", + "ER1END_N3_3" ], [ - "B_TERM_UTURN_INT_LV_L6", - "LV_L6" + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "BYP_BOUNCE_N3_7" ], [ - "B_TERM_UTURN_INT_SE6A3", - "SE6A3" + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "FAN_BOUNCE0" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "BYP_BOUNCE_N3_3" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "FAN_BOUNCE2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "BYP_BOUNCE_N3_6" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "FAN_BOUNCE4" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "BYP_BOUNCE_N3_2" + ], + [ + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "FAN_BOUNCE6" + ], + [ + "B_TERM_UTURN_INT_LVB_L0", + "LVB_L1" + ], + [ + "B_TERM_UTURN_INT_LVB_L0", + "LVB_L12" + ], + [ + "B_TERM_UTURN_INT_LVB_L1", + "LVB_L2" + ], + [ + "B_TERM_UTURN_INT_LVB_L1", + "LVB_L11" + ], + [ + "B_TERM_UTURN_INT_LVB_L2", + "LVB_L3" ], [ "B_TERM_UTURN_INT_LVB_L2", @@ -76593,3065 +23057,13321 @@ "B_TERM_UTURN_INT_LVB_L3", "LVB_L4" ], - [ - "B_TERM_UTURN_INT_SS2A2", - "SS2A2" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "FAN_BOUNCE4" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE0", - "FAN_BOUNCE0" - ], - [ - "B_TERM_UTURN_INT_SL1BEG1", - "SL1BEG1" - ], - [ - "B_TERM_UTURN_INT_SS2BEG0", - "SS2BEG0" - ], - [ - "B_TERM_UTURN_INT_SS2A0", - "NN2END3" - ], - [ - "B_TERM_UTURN_INT_SS6BEG3", - "SS6BEG3" - ], - [ - "B_TERM_UTURN_INT_SS6A3", - "SS6A3" - ], - [ - "B_TERM_UTURN_INT_SS6E3", - "SS6E3" - ], - [ - "B_TERM_UTURN_INT_SR1BEG3", - "SR1BEG3" - ], - [ - "B_TERM_UTURN_INT_SS6E0", - "NN6END3" - ], - [ - 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"BRKH_CLK_R_CK_GCLK7", + "CLK_BUFG_CK_GCLK7" + ], + [ + "BRKH_CLK_R_CK_GCLK8", + "CLK_BUFG_CK_GCLK8" + ], + [ + "BRKH_CLK_R_CK_GCLK9", + "CLK_BUFG_CK_GCLK9" + ], + [ + "BRKH_CLK_R_CK_GCLK10", + "CLK_BUFG_CK_GCLK10" + ], + [ + "BRKH_CLK_R_CK_GCLK11", + "CLK_BUFG_CK_GCLK11" + ], + [ + "BRKH_CLK_R_CK_GCLK12", + "CLK_BUFG_CK_GCLK12" + ], + [ + "BRKH_CLK_R_CK_GCLK13", + "CLK_BUFG_CK_GCLK13" + ], + [ + "BRKH_CLK_R_CK_GCLK14", + "CLK_BUFG_CK_GCLK14" + ], + [ + "BRKH_CLK_R_CK_GCLK15", + "CLK_BUFG_CK_GCLK15" + ], + [ + "BRKH_CLK_R_CK_GCLK16", + "CLK_BUFG_CK_GCLK16" + ], + [ + "BRKH_CLK_R_CK_GCLK17", + "CLK_BUFG_CK_GCLK17" + ], + [ + "BRKH_CLK_R_CK_GCLK18", + "CLK_BUFG_CK_GCLK18" + ], + [ + "BRKH_CLK_R_CK_GCLK19", + "CLK_BUFG_CK_GCLK19" + ], + [ + "BRKH_CLK_R_CK_GCLK20", + "CLK_BUFG_CK_GCLK20" + ], + [ + "BRKH_CLK_R_CK_GCLK21", + "CLK_BUFG_CK_GCLK21" + ], + [ + "BRKH_CLK_R_CK_GCLK22", + "CLK_BUFG_CK_GCLK22" + ], + [ + "BRKH_CLK_R_CK_GCLK23", + "CLK_BUFG_CK_GCLK23" + ], + [ + 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], [ - "INT_FEEDTHRU_2_EE4A2", - "MONITOR_EE4A2_5" + "BRKH_DSP_BCIN7", + "DSP_BCOUT7" ], [ - "INT_FEEDTHRU_2_WW4B3", - "MONITOR_WW4B3_5" + "BRKH_DSP_BCIN8", + "DSP_BCOUT8" ], [ - "INT_FEEDTHRU_2_ER1BEG0", - "MONITOR_ER1BEG0_5" + "BRKH_DSP_BCIN9", + "DSP_BCOUT9" ], [ - "INT_FEEDTHRU_2_NW4A2", - "MONITOR_NW4A2_5" + "BRKH_DSP_BCIN10", + "DSP_BCOUT10" ], [ - "INT_FEEDTHRU_2_LH11", - "MONITOR_LH11_5" + "BRKH_DSP_BCIN11", + "DSP_BCOUT11" ], [ - "INT_FEEDTHRU_2_SE4BEG0", - "MONITOR_SE4BEG0_5" + "BRKH_DSP_BCIN12", + "DSP_BCOUT12" ], [ - "INT_FEEDTHRU_2_EL1BEG0", - "MONITOR_EL1BEG0_5" + "BRKH_DSP_BCIN13", + "DSP_BCOUT13" ], [ - "INT_FEEDTHRU_2_ER1BEG3", - "MONITOR_ER1BEG3_5" + "BRKH_DSP_BCIN14", + "DSP_BCOUT14" ], [ - "INT_FEEDTHRU_2_WW4A2", - "MONITOR_WW4A2_5" + "BRKH_DSP_BCIN15", + "DSP_BCOUT15" ], [ - "INT_FEEDTHRU_2_WW4END0", - "MONITOR_WW4END0_5" + "BRKH_DSP_BCIN16", + "DSP_BCOUT16" ], [ - "INT_FEEDTHRU_2_WL1END3", - "MONITOR_WL1END3_5" + "BRKH_DSP_BCIN17", + "DSP_BCOUT17" ], [ - "INT_FEEDTHRU_2_SE4BEG3", - "MONITOR_SE4BEG3_5" + "BRKH_DSP_CARRYCASCIN", + "DSP_CARRYCASCOUT" ], [ - "INT_FEEDTHRU_2_EE4B1", - "MONITOR_EE4B1_5" + "BRKH_DSP_MULTSIGNIN", + "DSP_MULTSIGNOUT" ], [ - "INT_FEEDTHRU_2_SW2A1", - "MONITOR_SW2A1_5" + "BRKH_DSP_PCIN0", + "DSP_PCOUT0" ], [ - "INT_FEEDTHRU_2_LH9", - "MONITOR_LH9_5" + "BRKH_DSP_PCIN1", + "DSP_PCOUT1" ], [ - "INT_FEEDTHRU_2_SE4C1", - "MONITOR_SE4C1_5" + "BRKH_DSP_PCIN2", + "DSP_PCOUT2" ], [ - "INT_FEEDTHRU_2_EE4C0", - "MONITOR_EE4C0_5" + "BRKH_DSP_PCIN3", + "DSP_PCOUT3" ], [ - "INT_FEEDTHRU_2_EL1BEG1", - "MONITOR_EL1BEG1_5" + "BRKH_DSP_PCIN4", + "DSP_PCOUT4" ], [ - "INT_FEEDTHRU_2_WW2END1", - "MONITOR_WW2END1_5" + "BRKH_DSP_PCIN5", + "DSP_PCOUT5" ], [ - "INT_FEEDTHRU_2_SW2A0", - "MONITOR_SW2A0_5" + "BRKH_DSP_PCIN6", + "DSP_PCOUT6" ], [ - "INT_FEEDTHRU_2_WW2END3", - "MONITOR_WW2END3_5" + "BRKH_DSP_PCIN7", + "DSP_PCOUT7" ], [ - "INT_FEEDTHRU_2_WW4END3", - "MONITOR_WW4END3_5" + "BRKH_DSP_PCIN8", + "DSP_PCOUT8" ], [ - "INT_FEEDTHRU_2_EE2A0", - "MONITOR_EE2A0_5" + "BRKH_DSP_PCIN9", + "DSP_PCOUT9" ], [ - "INT_FEEDTHRU_2_ER1BEG2", - "MONITOR_ER1BEG2_5" + "BRKH_DSP_PCIN10", + "DSP_PCOUT10" ], [ - "INT_FEEDTHRU_2_EE4B3", - "MONITOR_EE4B3_5" + "BRKH_DSP_PCIN11", + "DSP_PCOUT11" ], [ - "INT_FEEDTHRU_2_SW4END3", - "MONITOR_SW4END3_5" + "BRKH_DSP_PCIN12", + "DSP_PCOUT12" ], [ - "INT_FEEDTHRU_2_WW4C3", - "MONITOR_WW4C3_5" + "BRKH_DSP_PCIN13", + "DSP_PCOUT13" ], [ - "INT_FEEDTHRU_2_EE2BEG2", - "MONITOR_EE2BEG2_5" + "BRKH_DSP_PCIN14", + "DSP_PCOUT14" ], [ - "INT_FEEDTHRU_2_NW2A1", - "MONITOR_NW2A1_5" + "BRKH_DSP_PCIN15", + "DSP_PCOUT15" ], [ - "INT_FEEDTHRU_2_LH4", - "MONITOR_LH4_5" + "BRKH_DSP_PCIN16", + "DSP_PCOUT16" ], [ - "INT_FEEDTHRU_2_SW4A3", - "MONITOR_SW4A3_5" + "BRKH_DSP_PCIN17", + "DSP_PCOUT17" ], [ - "INT_FEEDTHRU_2_EE4BEG1", - "MONITOR_EE4BEG1_5" + "BRKH_DSP_PCIN18", + "DSP_PCOUT18" ], [ - "INT_FEEDTHRU_2_WR1END3", - "MONITOR_WR1END3_5" + "BRKH_DSP_PCIN19", + "DSP_PCOUT19" ], [ - "INT_FEEDTHRU_2_WW4B2", - "MONITOR_WW4B2_5" + "BRKH_DSP_PCIN20", + "DSP_PCOUT20" ], [ - "INT_FEEDTHRU_2_SW4A1", - "MONITOR_SW4A1_5" + "BRKH_DSP_PCIN21", + "DSP_PCOUT21" ], [ - "INT_FEEDTHRU_2_NW4A1", - "MONITOR_NW4A1_5" + "BRKH_DSP_PCIN22", + "DSP_PCOUT22" ], [ - "INT_FEEDTHRU_2_NW2A0", - "MONITOR_NW2A0_5" + "BRKH_DSP_PCIN23", + "DSP_PCOUT23" ], [ - "INT_FEEDTHRU_2_WW2A2", - "MONITOR_WW2A2_5" + "BRKH_DSP_PCIN24", + "DSP_PCOUT24" ], [ - "INT_FEEDTHRU_2_NE4C0", - "MONITOR_NE4C0_5" + "BRKH_DSP_PCIN25", + "DSP_PCOUT25" ], [ - "INT_FEEDTHRU_2_SW2A3", - "MONITOR_SW2A3_5" + "BRKH_DSP_PCIN26", + "DSP_PCOUT26" ], [ - "INT_FEEDTHRU_2_WW2END0", - "MONITOR_WW2END0_5" + "BRKH_DSP_PCIN27", + "DSP_PCOUT27" ], [ - "INT_FEEDTHRU_2_EE2BEG3", - "MONITOR_EE2BEG3_5" + "BRKH_DSP_PCIN28", + "DSP_PCOUT28" ], [ - "INT_FEEDTHRU_2_SE4BEG2", - "MONITOR_SE4BEG2_5" + "BRKH_DSP_PCIN29", + "DSP_PCOUT29" ], [ - "INT_FEEDTHRU_2_NE2A2", - "MONITOR_NE2A2_5" + "BRKH_DSP_PCIN30", + "DSP_PCOUT30" ], [ - "INT_FEEDTHRU_2_EE4A1", - "MONITOR_EE4A1_5" + "BRKH_DSP_PCIN31", + "DSP_PCOUT31" ], [ - "INT_FEEDTHRU_2_WW4C1", - "MONITOR_WW4C1_5" + "BRKH_DSP_PCIN32", + "DSP_PCOUT32" ], [ - "INT_FEEDTHRU_2_NW2A3", - "MONITOR_NW2A3_5" + "BRKH_DSP_PCIN33", + "DSP_PCOUT33" ], [ - "INT_FEEDTHRU_2_SE4C2", - "MONITOR_SE4C2_5" + "BRKH_DSP_PCIN34", + "DSP_PCOUT34" ], [ - "INT_FEEDTHRU_2_NW4END2", - "MONITOR_NW4END2_5" + "BRKH_DSP_PCIN35", + "DSP_PCOUT35" ], [ - "INT_FEEDTHRU_2_NE4BEG3", - "MONITOR_NE4BEG3_5" + "BRKH_DSP_PCIN36", + "DSP_PCOUT36" ], [ - "INT_FEEDTHRU_2_SE4C3", - "MONITOR_SE4C3_5" + "BRKH_DSP_PCIN37", + "DSP_PCOUT37" ], [ - "INT_FEEDTHRU_2_LH1", - "MONITOR_LH1_5" + "BRKH_DSP_PCIN38", + "DSP_PCOUT38" ], [ - "INT_FEEDTHRU_2_SE4BEG1", - "MONITOR_SE4BEG1_5" + "BRKH_DSP_PCIN39", + "DSP_PCOUT39" ], [ - "INT_FEEDTHRU_2_WL1END0", - "MONITOR_WL1END0_5" + "BRKH_DSP_PCIN40", + "DSP_PCOUT40" ], [ - "INT_FEEDTHRU_2_LH7", - "MONITOR_LH7_5" + "BRKH_DSP_PCIN41", + "DSP_PCOUT41" ], [ - "INT_FEEDTHRU_2_WR1END1", - "MONITOR_WR1END1_5" + "BRKH_DSP_PCIN42", + "DSP_PCOUT42" ], [ - "INT_FEEDTHRU_2_LH5", - "MONITOR_LH5_5" + "BRKH_DSP_PCIN43", + "DSP_PCOUT43" ], [ - "INT_FEEDTHRU_2_NW4END0", - "MONITOR_NW4END0_5" + "BRKH_DSP_PCIN44", + "DSP_PCOUT44" ], [ - "INT_FEEDTHRU_2_WR1END0", - "MONITOR_WR1END0_5" + "BRKH_DSP_PCIN45", + "DSP_PCOUT45" ], [ - "INT_FEEDTHRU_2_EE4BEG0", - "MONITOR_EE4BEG0_5" + "BRKH_DSP_PCIN46", + "DSP_PCOUT46" ], [ - "INT_FEEDTHRU_2_SE2A0", - "MONITOR_SE2A0_5" - ], - [ - "INT_FEEDTHRU_2_NE4C3", - "MONITOR_NE4C3_5" - ], - [ - "INT_FEEDTHRU_2_EE4BEG3", - "MONITOR_EE4BEG3_5" - ], - [ - "INT_FEEDTHRU_2_SW4A0", - "MONITOR_SW4A0_5" - ], - [ - "INT_FEEDTHRU_2_EE4A3", - "MONITOR_EE4A3_5" - ], - [ - "INT_FEEDTHRU_2_SW4END1", - "MONITOR_SW4END1_5" - ], - [ - "INT_FEEDTHRU_2_WW4END1", - "MONITOR_WW4END1_5" - ], - [ - "INT_FEEDTHRU_2_NW2A2", - "MONITOR_NW2A2_5" - ], - [ - "INT_FEEDTHRU_2_EE4B0", - "MONITOR_EE4B0_5" - ], - [ - "INT_FEEDTHRU_2_NE2A3", - "MONITOR_NE2A3_5" - ], - [ - "INT_FEEDTHRU_2_LH12", - "MONITOR_LH12_5" - ], - [ - "INT_FEEDTHRU_2_NW4END3", - "MONITOR_NW4END3_5" - ], - [ - "INT_FEEDTHRU_2_WR1END2", - "MONITOR_WR1END2_5" - ], - [ - "INT_FEEDTHRU_2_LH6", - "MONITOR_LH6_5" - ], - [ - "INT_FEEDTHRU_2_NE2A1", - "MONITOR_NE2A1_5" - ], - [ - "INT_FEEDTHRU_2_EL1BEG3", - "MONITOR_EL1BEG3_5" - ], - [ - "INT_FEEDTHRU_2_EE2A3", - "MONITOR_EE2A3_5" - ], - [ - "INT_FEEDTHRU_2_EL1BEG2", - "MONITOR_EL1BEG2_5" - ], - [ - "INT_FEEDTHRU_2_WW4A1", - "MONITOR_WW4A1_5" - ], - [ - "INT_FEEDTHRU_2_NE4BEG1", - "MONITOR_NE4BEG1_5" - ], - [ - "INT_FEEDTHRU_2_NW4END1", - "MONITOR_NW4END1_5" - ], - [ - "INT_FEEDTHRU_2_EE4C3", - "MONITOR_EE4C3_5" - ], - [ - "INT_FEEDTHRU_2_NE4BEG0", - "MONITOR_NE4BEG0_5" - ], - [ - "INT_FEEDTHRU_2_WW4B1", - "MONITOR_WW4B1_5" - ], - [ - "INT_FEEDTHRU_2_EE4BEG2", - "MONITOR_EE4BEG2_5" - ], - [ - "INT_FEEDTHRU_2_SW4A2", - "MONITOR_SW4A2_5" - ], - [ - "INT_FEEDTHRU_2_SW4END0", - "MONITOR_SW4END0_5" + "BRKH_DSP_PCIN47", + "DSP_PCOUT47" ] ] }, { "grid_deltas": [ - 1, - -3 + 0, + -1 ], "tile_types": [ - "CLK_BUFG_TOP_R", - "VBRK" + "BRKH_DSP_R", + "DSP_R" ], "wire_pairs": [ [ - "CLK_HROW_LH4_3", - "VBRK_LH4" + "BRKH_DSP_ACIN0", + "DSP_0_ACIN0" ], [ - "CLK_HROW_EL1BEG2_3", - "VBRK_EL1BEG2" + "BRKH_DSP_ACIN1", + "DSP_0_ACIN1" ], [ - "CLK_HROW_SE2A2_3", - "VBRK_SE2A2" + "BRKH_DSP_ACIN2", + "DSP_0_ACIN2" ], [ - "CLK_HROW_MONITOR_N_3", - "VBRK_MONITOR_N" + "BRKH_DSP_ACIN3", + "DSP_0_ACIN3" ], [ - "CLK_HROW_WW2A0_3", - "VBRK_WW2A0" + "BRKH_DSP_ACIN4", + "DSP_0_ACIN4" ], [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" + "BRKH_DSP_ACIN5", + "DSP_0_ACIN5" ], [ - "CLK_HROW_NE4C1_3", - "VBRK_NE4C1" + "BRKH_DSP_ACIN6", + "DSP_0_ACIN6" ], [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" + "BRKH_DSP_ACIN7", + "DSP_0_ACIN7" ], [ - "CLK_HROW_EE4BEG2_3", - "VBRK_EE4BEG2" + "BRKH_DSP_ACIN8", + "DSP_0_ACIN8" ], [ - "CLK_HROW_WW4C1_3", - "VBRK_WW4C1" + "BRKH_DSP_ACIN9", + "DSP_0_ACIN9" ], [ - "CLK_HROW_WW4B0_3", - "VBRK_WW4B0" + "BRKH_DSP_ACIN10", + "DSP_0_ACIN10" ], [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" + "BRKH_DSP_ACIN11", + "DSP_0_ACIN11" ], [ - "CLK_HROW_LH2_3", - "VBRK_LH2" + "BRKH_DSP_ACIN12", + "DSP_0_ACIN12" ], [ - "CLK_HROW_WW2END1_3", - "VBRK_WW2END1" + "BRKH_DSP_ACIN13", + "DSP_0_ACIN13" ], [ - "CLK_HROW_EE4B3_3", - "VBRK_EE4B3" + "BRKH_DSP_ACIN14", + "DSP_0_ACIN14" ], [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" + "BRKH_DSP_ACIN15", + "DSP_0_ACIN15" ], [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" + "BRKH_DSP_ACIN16", + "DSP_0_ACIN16" ], [ - "CLK_HROW_SW2A0_3", - "VBRK_SW2A0" + "BRKH_DSP_ACIN17", + "DSP_0_ACIN17" ], [ - "CLK_HROW_EL1BEG1_3", - "VBRK_EL1BEG1" + "BRKH_DSP_ACIN18", + "DSP_0_ACIN18" ], [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" + "BRKH_DSP_ACIN19", + "DSP_0_ACIN19" ], [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" + "BRKH_DSP_ACIN20", + "DSP_0_ACIN20" ], [ - "CLK_HROW_EE4A0_3", - "VBRK_EE4A0" + "BRKH_DSP_ACIN21", + "DSP_0_ACIN21" ], [ - "CLK_HROW_EL1BEG0_3", - "VBRK_EL1BEG0" + "BRKH_DSP_ACIN22", + "DSP_0_ACIN22" ], [ - "CLK_HROW_LH9_3", - "VBRK_LH9" + "BRKH_DSP_ACIN23", + "DSP_0_ACIN23" ], [ - "CLK_HROW_NW2A2_3", - "VBRK_NW2A2" + "BRKH_DSP_ACIN24", + "DSP_0_ACIN24" ], [ - "CLK_HROW_EE2A2_3", - "VBRK_EE2A2" + "BRKH_DSP_ACIN25", + "DSP_0_ACIN25" ], [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" + "BRKH_DSP_ACIN26", + "DSP_0_ACIN26" ], [ - "CLK_HROW_WW4C2_3", - "VBRK_WW4C2" + "BRKH_DSP_ACIN27", + "DSP_0_ACIN27" ], [ - "CLK_HROW_NE4BEG2_3", - "VBRK_NE4BEG2" + "BRKH_DSP_ACIN28", + "DSP_0_ACIN28" ], [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" + "BRKH_DSP_ACIN29", + "DSP_0_ACIN29" ], [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" + "BRKH_DSP_BCIN0", + "DSP_0_BCIN0" ], [ - "CLK_HROW_EE4B0_3", - "VBRK_EE4B0" + "BRKH_DSP_BCIN1", + "DSP_0_BCIN1" ], [ - "CLK_HROW_WW2A3_3", - "VBRK_WW2A3" + "BRKH_DSP_BCIN2", + "DSP_0_BCIN2" ], [ - "CLK_HROW_WR1END2_3", - "VBRK_WR1END2" + "BRKH_DSP_BCIN3", + "DSP_0_BCIN3" ], [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" + "BRKH_DSP_BCIN4", + "DSP_0_BCIN4" ], [ - "CLK_HROW_NE4C0_3", - "VBRK_NE4C0" + "BRKH_DSP_BCIN5", + "DSP_0_BCIN5" ], [ - "CLK_HROW_LH7_3", - "VBRK_LH7" + "BRKH_DSP_BCIN6", + "DSP_0_BCIN6" ], [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" + "BRKH_DSP_BCIN7", + "DSP_0_BCIN7" ], [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" + "BRKH_DSP_BCIN8", + "DSP_0_BCIN8" ], [ - "CLK_HROW_EE4C2_3", - "VBRK_EE4C2" + "BRKH_DSP_BCIN9", + "DSP_0_BCIN9" ], [ - "CLK_HROW_NE4C3_3", - "VBRK_NE4C3" + "BRKH_DSP_BCIN10", + "DSP_0_BCIN10" ], [ - "CLK_HROW_WW2A1_3", - "VBRK_WW2A1" + "BRKH_DSP_BCIN11", + "DSP_0_BCIN11" ], [ - "CLK_HROW_EE4C3_3", - "VBRK_EE4C3" + "BRKH_DSP_BCIN12", + "DSP_0_BCIN12" ], [ - "CLK_HROW_NE2A3_3", - "VBRK_NE2A3" + "BRKH_DSP_BCIN13", + "DSP_0_BCIN13" ], [ - "CLK_HROW_SE4BEG3_3", - "VBRK_SE4BEG3" + "BRKH_DSP_BCIN14", + "DSP_0_BCIN14" ], [ - "CLK_HROW_EE2A0_3", - "VBRK_EE2A0" + "BRKH_DSP_BCIN15", + "DSP_0_BCIN15" ], [ - "CLK_HROW_LH1_3", - "VBRK_LH1" + "BRKH_DSP_BCIN16", + "DSP_0_BCIN16" ], [ - "CLK_HROW_NW4A2_3", - "VBRK_NW4A2" + "BRKH_DSP_BCIN17", + "DSP_0_BCIN17" ], [ - "CLK_HROW_LH11_3", - "VBRK_LH11" + "BRKH_DSP_CARRYCASCIN", + "DSP_0_CARRYCASCIN" ], [ - "CLK_HROW_WW4END3_3", - "VBRK_WW4END3" + "BRKH_DSP_MULTSIGNIN", + "DSP_0_MULTSIGNIN" ], [ - "CLK_HROW_SE4C3_3", - "VBRK_SE4C3" + "BRKH_DSP_PCIN0", + "DSP_0_PCIN0" ], [ - "CLK_HROW_WW4END2_3", - "VBRK_WW4END2" + "BRKH_DSP_PCIN1", + "DSP_0_PCIN1" ], [ - "CLK_HROW_SW4END2_3", - "VBRK_SW4END2" + "BRKH_DSP_PCIN2", + "DSP_0_PCIN2" ], [ - "CLK_HROW_NW2A3_3", - "VBRK_NW2A3" + "BRKH_DSP_PCIN3", + "DSP_0_PCIN3" ], [ - "CLK_HROW_WW4END1_3", - "VBRK_WW4END1" + "BRKH_DSP_PCIN4", + "DSP_0_PCIN4" ], [ - "CLK_HROW_EE2BEG2_3", - "VBRK_EE2BEG2" + "BRKH_DSP_PCIN5", + "DSP_0_PCIN5" ], [ - "CLK_HROW_EE4BEG3_3", - "VBRK_EE4BEG3" + "BRKH_DSP_PCIN6", + "DSP_0_PCIN6" ], [ - "CLK_HROW_SE2A1_3", - "VBRK_SE2A1" + "BRKH_DSP_PCIN7", + "DSP_0_PCIN7" ], [ - "CLK_HROW_NE4C2_3", - "VBRK_NE4C2" + "BRKH_DSP_PCIN8", + "DSP_0_PCIN8" ], [ - "CLK_HROW_WL1END0_3", - "VBRK_WL1END0" + "BRKH_DSP_PCIN9", + "DSP_0_PCIN9" ], [ - "CLK_HROW_SW4END1_3", - "VBRK_SW4END1" + "BRKH_DSP_PCIN10", + "DSP_0_PCIN10" ], [ - "CLK_HROW_NW4END2_3", - "VBRK_NW4END2" + "BRKH_DSP_PCIN11", + "DSP_0_PCIN11" ], [ - "CLK_HROW_WW2END3_3", - "VBRK_WW2END3" + "BRKH_DSP_PCIN12", + "DSP_0_PCIN12" ], [ - "CLK_HROW_SE4BEG2_3", - "VBRK_SE4BEG2" + "BRKH_DSP_PCIN13", + "DSP_0_PCIN13" ], [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" + "BRKH_DSP_PCIN14", + "DSP_0_PCIN14" ], [ - "CLK_HROW_NE2A1_3", - "VBRK_NE2A1" + "BRKH_DSP_PCIN15", + "DSP_0_PCIN15" ], [ - "CLK_HROW_WW4B2_3", - "VBRK_WW4B2" + "BRKH_DSP_PCIN16", + "DSP_0_PCIN16" ], [ - "CLK_HROW_NE4BEG0_3", - "VBRK_NE4BEG0" + "BRKH_DSP_PCIN17", + "DSP_0_PCIN17" ], [ - "CLK_HROW_EL1BEG3_3", - "VBRK_EL1BEG3" + "BRKH_DSP_PCIN18", + "DSP_0_PCIN18" ], [ - "CLK_HROW_ER1BEG3_3", - "VBRK_ER1BEG3" + "BRKH_DSP_PCIN19", + "DSP_0_PCIN19" ], [ - "CLK_HROW_SE2A3_3", - "VBRK_SE2A3" + "BRKH_DSP_PCIN20", + "DSP_0_PCIN20" ], [ - "CLK_HROW_SW4A1_3", - "VBRK_SW4A1" + "BRKH_DSP_PCIN21", + "DSP_0_PCIN21" ], [ - "CLK_HROW_ER1BEG0_3", - "VBRK_ER1BEG0" + "BRKH_DSP_PCIN22", + "DSP_0_PCIN22" ], [ - "CLK_HROW_EE4C1_3", - "VBRK_EE4C1" + "BRKH_DSP_PCIN23", + "DSP_0_PCIN23" ], [ - "CLK_HROW_WL1END3_3", - "VBRK_WL1END3" + "BRKH_DSP_PCIN24", + "DSP_0_PCIN24" ], [ - "CLK_HROW_EE2A1_3", - "VBRK_EE2A1" + "BRKH_DSP_PCIN25", + "DSP_0_PCIN25" ], [ - "CLK_HROW_NW4END3_3", - "VBRK_NW4END3" + "BRKH_DSP_PCIN26", + "DSP_0_PCIN26" ], [ - "CLK_HROW_LH10_3", - "VBRK_LH10" + "BRKH_DSP_PCIN27", + "DSP_0_PCIN27" ], [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" + "BRKH_DSP_PCIN28", + "DSP_0_PCIN28" ], [ - "CLK_HROW_EE4B2_3", - "VBRK_EE4B2" + "BRKH_DSP_PCIN29", + "DSP_0_PCIN29" ], [ - "CLK_HROW_EE2BEG0_3", - "VBRK_EE2BEG0" + "BRKH_DSP_PCIN30", + "DSP_0_PCIN30" ], [ - "CLK_HROW_SE4C1_3", - "VBRK_SE4C1" + "BRKH_DSP_PCIN31", + "DSP_0_PCIN31" ], [ - "CLK_HROW_EE4A1_3", - "VBRK_EE4A1" + "BRKH_DSP_PCIN32", + "DSP_0_PCIN32" ], [ - "CLK_HROW_WW2A2_3", - "VBRK_WW2A2" + "BRKH_DSP_PCIN33", + "DSP_0_PCIN33" ], [ - "CLK_HROW_EE4B1_3", - "VBRK_EE4B1" + "BRKH_DSP_PCIN34", + "DSP_0_PCIN34" ], [ - "CLK_HROW_NE2A0_3", - "VBRK_NE2A0" + "BRKH_DSP_PCIN35", + "DSP_0_PCIN35" ], [ - "CLK_HROW_NW2A1_3", - "VBRK_NW2A1" + "BRKH_DSP_PCIN36", + "DSP_0_PCIN36" ], [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" + "BRKH_DSP_PCIN37", + "DSP_0_PCIN37" ], [ - "CLK_HROW_LH8_3", - "VBRK_LH8" + "BRKH_DSP_PCIN38", + "DSP_0_PCIN38" ], [ - "CLK_HROW_SW4A2_3", - "VBRK_SW4A2" + "BRKH_DSP_PCIN39", + "DSP_0_PCIN39" ], [ - "CLK_HROW_NW4END0_3", - "VBRK_NW4END0" + "BRKH_DSP_PCIN40", + "DSP_0_PCIN40" ], [ - "CLK_HROW_EE4BEG1_3", - "VBRK_EE4BEG1" + "BRKH_DSP_PCIN41", + "DSP_0_PCIN41" ], [ - "CLK_HROW_NW4A3_3", - "VBRK_NW4A3" + "BRKH_DSP_PCIN42", + "DSP_0_PCIN42" ], [ - "CLK_HROW_WW4A3_3", - "VBRK_WW4A3" + "BRKH_DSP_PCIN43", + "DSP_0_PCIN43" ], [ - "CLK_HROW_WR1END0_3", - "VBRK_WR1END0" + "BRKH_DSP_PCIN44", + "DSP_0_PCIN44" ], [ - "CLK_HROW_SE4BEG1_3", - "VBRK_SE4BEG1" + "BRKH_DSP_PCIN45", + "DSP_0_PCIN45" ], [ - "CLK_HROW_WW4C3_3", - "VBRK_WW4C3" + "BRKH_DSP_PCIN46", + "DSP_0_PCIN46" ], [ - "CLK_HROW_LH6_3", - "VBRK_LH6" - ], - [ - "CLK_HROW_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_LH12_3", - "VBRK_LH12" - ], - [ - "CLK_HROW_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_MONITOR_P_3", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_WL1END2_3", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_LH5_3", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW4B1_3", - "VBRK_WW4B1" + "BRKH_DSP_PCIN47", + "DSP_0_PCIN47" ] ] }, { "grid_deltas": [ - 1, - 0 + 0, + 5 ], "tile_types": [ - "MONITOR_TOP", - "VFRAME" + "BRKH_DSP_R", + "DSP_R" ], "wire_pairs": [ [ - "MONITOR_EE4C1_0", - "VFRAME_EE4C1" + "BRKH_DSP_ACIN0", + "DSP_ACOUT0" ], [ - "MONITOR_LH4_0", - "VFRAME_LH4" + "BRKH_DSP_ACIN1", + "DSP_ACOUT1" ], [ - "MONITOR_BYP7_0", - "VFRAME_BYP7" + "BRKH_DSP_ACIN2", + "DSP_ACOUT2" ], [ - "MONITOR_LH10_0", - "VFRAME_LH10" + "BRKH_DSP_ACIN3", + "DSP_ACOUT3" ], [ - "MONITOR_NE2A0_0", - "VFRAME_NE2A0" + "BRKH_DSP_ACIN4", + "DSP_ACOUT4" ], [ - "MONITOR_WW4C0_0", - "VFRAME_WW4C0" + "BRKH_DSP_ACIN5", + "DSP_ACOUT5" ], [ - "MONITOR_FAN1_0", - "VFRAME_FAN1" + "BRKH_DSP_ACIN6", + "DSP_ACOUT6" ], [ - "MONITOR_EE4C2_0", - "VFRAME_EE4C2" + "BRKH_DSP_ACIN7", + "DSP_ACOUT7" ], [ - "MONITOR_IMUX37_0", - "VFRAME_IMUX37" + "BRKH_DSP_ACIN8", + "DSP_ACOUT8" ], [ - "MONITOR_IMUX18_0", - "VFRAME_IMUX18" + "BRKH_DSP_ACIN9", + "DSP_ACOUT9" ], [ - "MONITOR_EL1BEG2_0", - "VFRAME_EL1BEG2" + "BRKH_DSP_ACIN10", + "DSP_ACOUT10" ], [ - "MONITOR_WW2END2_0", - "VFRAME_WW2END2" + "BRKH_DSP_ACIN11", + "DSP_ACOUT11" ], [ - "MONITOR_NE2A3_0", - "VFRAME_NE2A3" + "BRKH_DSP_ACIN12", + "DSP_ACOUT12" ], [ - "MONITOR_SE2A1_0", - "VFRAME_SE2A1" + "BRKH_DSP_ACIN13", + "DSP_ACOUT13" ], [ - "MONITOR_NE4C1_0", - "VFRAME_NE4C1" + "BRKH_DSP_ACIN14", + "DSP_ACOUT14" ], [ - "MONITOR_NW2A0_0", - "VFRAME_NW2A0" + "BRKH_DSP_ACIN15", + "DSP_ACOUT15" ], [ - "MONITOR_EE2BEG3_0", - "VFRAME_EE2BEG3" + "BRKH_DSP_ACIN16", + "DSP_ACOUT16" ], [ - "MONITOR_EE2A0_0", - "VFRAME_EE2A0" + "BRKH_DSP_ACIN17", + "DSP_ACOUT17" ], [ - "MONITOR_IMUX41_0", - "VFRAME_IMUX41" + "BRKH_DSP_ACIN18", + "DSP_ACOUT18" ], [ - "MONITOR_IMUX5_0", - "VFRAME_IMUX5" + "BRKH_DSP_ACIN19", + "DSP_ACOUT19" ], [ - "MONITOR_IMUX1_0", - "VFRAME_IMUX1" + "BRKH_DSP_ACIN20", + "DSP_ACOUT20" ], [ - "MONITOR_NE4BEG1_0", - "VFRAME_NE4BEG1" + "BRKH_DSP_ACIN21", + "DSP_ACOUT21" ], [ - "MONITOR_BYP0_0", - "VFRAME_BYP0" + "BRKH_DSP_ACIN22", + "DSP_ACOUT22" ], [ - "MONITOR_WL1END0_0", - "VFRAME_WL1END0" + "BRKH_DSP_ACIN23", + "DSP_ACOUT23" ], [ - "MONITOR_LH7_0", - "VFRAME_LH7" + "BRKH_DSP_ACIN24", + "DSP_ACOUT24" ], [ - "MONITOR_BYP1_0", - "VFRAME_BYP1" + "BRKH_DSP_ACIN25", + "DSP_ACOUT25" ], [ - "MONITOR_WW4B1_0", - "VFRAME_WW4B1" + "BRKH_DSP_ACIN26", + "DSP_ACOUT26" ], [ - "MONITOR_WW4END0_0", - "VFRAME_WW4END0" + "BRKH_DSP_ACIN27", + "DSP_ACOUT27" ], [ - "MONITOR_WW2END3_0", - "VFRAME_WW2END3" + "BRKH_DSP_ACIN28", + "DSP_ACOUT28" ], [ - "MONITOR_SE4C2_0", - "VFRAME_SE4C2" + "BRKH_DSP_ACIN29", + "DSP_ACOUT29" ], [ - "MONITOR_NE4C2_0", - "VFRAME_NE4C2" + "BRKH_DSP_BCIN0", + "DSP_BCOUT0" ], [ - "MONITOR_SW4END2_0", - "VFRAME_SW4END2" + "BRKH_DSP_BCIN1", + "DSP_BCOUT1" ], [ - "MONITOR_WL1END1_0", - "VFRAME_WL1END1" + "BRKH_DSP_BCIN2", + "DSP_BCOUT2" ], [ - "MONITOR_NW2A3_0", - "VFRAME_NW2A3" + "BRKH_DSP_BCIN3", + "DSP_BCOUT3" ], [ - "MONITOR_BYP3_0", - "VFRAME_BYP3" + "BRKH_DSP_BCIN4", + "DSP_BCOUT4" ], [ - "MONITOR_IMUX17_0", - "VFRAME_IMUX17" + "BRKH_DSP_BCIN5", + "DSP_BCOUT5" ], [ - "MONITOR_LH6_0", - "VFRAME_LH6" + "BRKH_DSP_BCIN6", + "DSP_BCOUT6" ], [ - "MONITOR_IMUX12_0", - "VFRAME_IMUX12" + "BRKH_DSP_BCIN7", + "DSP_BCOUT7" ], [ - "MONITOR_WW4A3_0", - "VFRAME_WW4A3" + "BRKH_DSP_BCIN8", + "DSP_BCOUT8" ], [ - "MONITOR_ER1BEG0_0", - "VFRAME_ER1BEG0" + "BRKH_DSP_BCIN9", + "DSP_BCOUT9" ], [ - "MONITOR_LH2_0", - "VFRAME_LH2" + "BRKH_DSP_BCIN10", + "DSP_BCOUT10" ], [ - "MONITOR_IMUX35_0", - "VFRAME_IMUX35" + "BRKH_DSP_BCIN11", + "DSP_BCOUT11" ], [ - "MONITOR_WL1END3_0", - "VFRAME_WL1END3" + "BRKH_DSP_BCIN12", + "DSP_BCOUT12" ], [ - "MONITOR_NE4BEG3_0", - "VFRAME_NE4BEG3" + "BRKH_DSP_BCIN13", + "DSP_BCOUT13" ], [ - "MONITOR_SE4BEG1_0", - "VFRAME_SE4BEG1" + "BRKH_DSP_BCIN14", + "DSP_BCOUT14" ], [ - "MONITOR_IMUX33_0", - "VFRAME_IMUX33" + "BRKH_DSP_BCIN15", + "DSP_BCOUT15" ], [ - "MONITOR_LH12_0", - "VFRAME_LH12" + "BRKH_DSP_BCIN16", + "DSP_BCOUT16" ], [ - "MONITOR_CLK1_0", - "VFRAME_CLK1" + "BRKH_DSP_BCIN17", + "DSP_BCOUT17" ], [ - "MONITOR_CTRL1_0", - "VFRAME_CTRL1" + "BRKH_DSP_CARRYCASCIN", + "DSP_CARRYCASCOUT" ], [ - "MONITOR_IMUX7_0", - "VFRAME_IMUX7" + "BRKH_DSP_MULTSIGNIN", + "DSP_MULTSIGNOUT" ], [ - "MONITOR_NE4C0_0", - "VFRAME_NE4C0" + "BRKH_DSP_PCIN0", + "DSP_PCOUT0" ], [ - "MONITOR_SW2A3_0", - "VFRAME_SW2A3" + "BRKH_DSP_PCIN1", + "DSP_PCOUT1" ], [ - "MONITOR_SW2A2_0", - "VFRAME_SW2A2" + "BRKH_DSP_PCIN2", + "DSP_PCOUT2" ], [ - "MONITOR_SW2A0_0", - "VFRAME_SW2A0" + "BRKH_DSP_PCIN3", + "DSP_PCOUT3" ], [ - "MONITOR_FAN4_0", - "VFRAME_FAN4" + "BRKH_DSP_PCIN4", + "DSP_PCOUT4" ], [ - "MONITOR_IMUX6_0", - "VFRAME_IMUX6" + "BRKH_DSP_PCIN5", + "DSP_PCOUT5" ], [ - "MONITOR_WW2A0_0", - "VFRAME_WW2A0" + "BRKH_DSP_PCIN6", + "DSP_PCOUT6" ], [ - "MONITOR_NE4C3_0", - "VFRAME_NE4C3" + "BRKH_DSP_PCIN7", + "DSP_PCOUT7" ], [ - "MONITOR_BYP2_0", - "VFRAME_BYP2" + "BRKH_DSP_PCIN8", + "DSP_PCOUT8" ], [ - "MONITOR_IMUX46_0", - "VFRAME_IMUX46" + "BRKH_DSP_PCIN9", + "DSP_PCOUT9" ], [ - "MONITOR_IMUX4_0", - "VFRAME_IMUX4" + "BRKH_DSP_PCIN10", + "DSP_PCOUT10" ], [ - "MONITOR_NW4A3_0", - "VFRAME_NW4A3" + "BRKH_DSP_PCIN11", + "DSP_PCOUT11" ], [ - "MONITOR_WW4C2_0", - "VFRAME_WW4C2" + "BRKH_DSP_PCIN12", + "DSP_PCOUT12" ], [ - "MONITOR_SE4BEG3_0", - "VFRAME_SE4BEG3" + "BRKH_DSP_PCIN13", + "DSP_PCOUT13" ], [ - "MONITOR_WR1END2_0", - "VFRAME_WR1END2" + "BRKH_DSP_PCIN14", + "DSP_PCOUT14" ], [ - "MONITOR_WL1END2_0", - "VFRAME_WL1END2" + "BRKH_DSP_PCIN15", + "DSP_PCOUT15" ], [ - "MONITOR_WW2END0_0", - "VFRAME_WW2END0" + "BRKH_DSP_PCIN16", + "DSP_PCOUT16" ], [ - "MONITOR_IMUX27_0", - "VFRAME_IMUX27" + "BRKH_DSP_PCIN17", + "DSP_PCOUT17" ], [ - "MONITOR_NE4BEG2_0", - "VFRAME_NE4BEG2" + "BRKH_DSP_PCIN18", + "DSP_PCOUT18" ], [ - "MONITOR_IMUX29_0", - "VFRAME_IMUX29" + "BRKH_DSP_PCIN19", + "DSP_PCOUT19" ], [ - "MONITOR_EE4BEG2_0", - "VFRAME_EE4BEG2" + "BRKH_DSP_PCIN20", + "DSP_PCOUT20" ], [ - "MONITOR_EE2A2_0", - "VFRAME_EE2A2" + "BRKH_DSP_PCIN21", + "DSP_PCOUT21" ], [ - "MONITOR_EE2BEG2_0", - "VFRAME_EE2BEG2" + "BRKH_DSP_PCIN22", + "DSP_PCOUT22" ], [ - "MONITOR_IMUX43_0", - "VFRAME_IMUX43" + "BRKH_DSP_PCIN23", + "DSP_PCOUT23" ], [ - "MONITOR_WW4C3_0", - "VFRAME_WW4C3" + "BRKH_DSP_PCIN24", + "DSP_PCOUT24" ], [ - "MONITOR_IMUX9_0", - "VFRAME_IMUX9" + "BRKH_DSP_PCIN25", + "DSP_PCOUT25" ], [ - "MONITOR_SW4END0_0", - "VFRAME_SW4END0" + "BRKH_DSP_PCIN26", + "DSP_PCOUT26" ], [ - "MONITOR_NW4END0_0", - "VFRAME_NW4END0" + "BRKH_DSP_PCIN27", + "DSP_PCOUT27" ], [ - "MONITOR_EE2A3_0", - "VFRAME_EE2A3" + "BRKH_DSP_PCIN28", + "DSP_PCOUT28" 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+ "INT_FEEDTHRU_2_NE4C0" ], [ - "MONITOR_WW4C1_0", - "VFRAME_WW4C1" + "CFG_CENTER_NE4C1_16", + "INT_FEEDTHRU_2_NE4C1" ], [ - "MONITOR_LH3_0", - "VFRAME_LH3" + "CFG_CENTER_NE4C2_16", + "INT_FEEDTHRU_2_NE4C2" ], [ - "MONITOR_NW4END3_0", - "VFRAME_NW4END3" + "CFG_CENTER_NE4C3_16", + "INT_FEEDTHRU_2_NE4C3" ], [ - "MONITOR_SW4END3_0", - "VFRAME_SW4END3" + "CFG_CENTER_NW2A0_16", + "INT_FEEDTHRU_2_NW2A0" ], [ - "MONITOR_LH5_0", - "VFRAME_LH5" + "CFG_CENTER_NW2A1_16", + "INT_FEEDTHRU_2_NW2A1" ], [ - "MONITOR_WW4END3_0", - "VFRAME_WW4END3" + "CFG_CENTER_NW2A2_16", + "INT_FEEDTHRU_2_NW2A2" ], [ - "MONITOR_ER1BEG1_0", - "VFRAME_ER1BEG1" + "CFG_CENTER_NW2A3_16", + "INT_FEEDTHRU_2_NW2A3" ], [ - "MONITOR_IMUX32_0", - "VFRAME_IMUX32" + "CFG_CENTER_NW4A0_16", + "INT_FEEDTHRU_2_NW4A0" ], [ - "MONITOR_NW4END2_0", - "VFRAME_NW4END2" + "CFG_CENTER_NW4A1_16", + "INT_FEEDTHRU_2_NW4A1" ], [ - "MONITOR_IMUX45_0", - "VFRAME_IMUX45" + "CFG_CENTER_NW4A2_16", + "INT_FEEDTHRU_2_NW4A2" ], [ - "MONITOR_EE4B3_0", - "VFRAME_EE4B3" + "CFG_CENTER_NW4A3_16", + "INT_FEEDTHRU_2_NW4A3" ], [ - "MONITOR_WW4END1_0", - "VFRAME_WW4END1" + "CFG_CENTER_NW4END0_16", + "INT_FEEDTHRU_2_NW4END0" ], [ - "MONITOR_EE2A1_0", - "VFRAME_EE2A1" + "CFG_CENTER_NW4END1_16", + "INT_FEEDTHRU_2_NW4END1" ], [ - "MONITOR_IMUX24_0", - "VFRAME_IMUX24" + "CFG_CENTER_NW4END2_16", + "INT_FEEDTHRU_2_NW4END2" ], [ - "MONITOR_NW4A2_0", - "VFRAME_NW4A2" + "CFG_CENTER_NW4END3_16", + "INT_FEEDTHRU_2_NW4END3" ], [ - "MONITOR_IMUX26_0", - "VFRAME_IMUX26" + "CFG_CENTER_SE2A0_16", + "INT_FEEDTHRU_2_SE2A0" ], [ - "MONITOR_EE2BEG0_0", - "VFRAME_EE2BEG0" + "CFG_CENTER_SE2A1_16", + "INT_FEEDTHRU_2_SE2A1" ], [ - "MONITOR_IMUX40_0", - "VFRAME_IMUX40" + "CFG_CENTER_SE2A2_16", + "INT_FEEDTHRU_2_SE2A2" ], [ - "MONITOR_EE4B0_0", - "VFRAME_EE4B0" + "CFG_CENTER_SE2A3_16", + "INT_FEEDTHRU_2_SE2A3" ], [ - "MONITOR_EL1BEG0_0", - "VFRAME_EL1BEG0" + "CFG_CENTER_SE4BEG0_16", + "INT_FEEDTHRU_2_SE4BEG0" ], [ - "MONITOR_SE4C3_0", - "VFRAME_SE4C3" + "CFG_CENTER_SE4BEG1_16", + "INT_FEEDTHRU_2_SE4BEG1" ], [ - "MONITOR_EE4A0_0", - "VFRAME_EE4A0" + "CFG_CENTER_SE4BEG2_16", + "INT_FEEDTHRU_2_SE4BEG2" ], [ - "MONITOR_SW4END1_0", - "VFRAME_SW4END1" + "CFG_CENTER_SE4BEG3_16", + "INT_FEEDTHRU_2_SE4BEG3" ], [ - "MONITOR_LH9_0", - "VFRAME_LH9" + "CFG_CENTER_SE4C0_16", + "INT_FEEDTHRU_2_SE4C0" ], [ - "MONITOR_WR1END3_0", - "VFRAME_WR1END3" + "CFG_CENTER_SE4C1_16", + "INT_FEEDTHRU_2_SE4C1" ], [ - "MONITOR_IMUX20_0", - "VFRAME_IMUX20" + "CFG_CENTER_SE4C2_16", + "INT_FEEDTHRU_2_SE4C2" ], [ - "MONITOR_WW4B3_0", - "VFRAME_WW4B3" + "CFG_CENTER_SE4C3_16", + "INT_FEEDTHRU_2_SE4C3" ], [ - "MONITOR_EE4BEG0_0", - "VFRAME_EE4BEG0" + "CFG_CENTER_SW2A0_16", + "INT_FEEDTHRU_2_SW2A0" ], [ - "MONITOR_LH1_0", - "VFRAME_LH1" + "CFG_CENTER_SW2A1_16", + "INT_FEEDTHRU_2_SW2A1" ], [ - "MONITOR_IMUX23_0", - "VFRAME_IMUX23" + "CFG_CENTER_SW2A2_16", + "INT_FEEDTHRU_2_SW2A2" ], [ - "MONITOR_EE4B2_0", - "VFRAME_EE4B2" + "CFG_CENTER_SW2A3_16", + "INT_FEEDTHRU_2_SW2A3" ], [ - "MONITOR_IMUX36_0", - "VFRAME_IMUX36" + "CFG_CENTER_SW4A0_16", + "INT_FEEDTHRU_2_SW4A0" ], [ - "MONITOR_NW2A2_0", - "VFRAME_NW2A2" + "CFG_CENTER_SW4A1_16", + "INT_FEEDTHRU_2_SW4A1" ], [ - "MONITOR_ER1BEG2_0", - "VFRAME_ER1BEG2" + "CFG_CENTER_SW4A2_16", + "INT_FEEDTHRU_2_SW4A2" ], [ - "MONITOR_NW4A1_0", - "VFRAME_NW4A1" + "CFG_CENTER_SW4A3_16", + "INT_FEEDTHRU_2_SW4A3" ], [ - "MONITOR_FAN2_0", - "VFRAME_FAN2" + "CFG_CENTER_SW4END0_16", + "INT_FEEDTHRU_2_SW4END0" ], [ - "MONITOR_WW4A2_0", - "VFRAME_WW4A2" + "CFG_CENTER_SW4END1_16", + "INT_FEEDTHRU_2_SW4END1" ], [ - "MONITOR_EE4C0_0", - "VFRAME_EE4C0" + "CFG_CENTER_SW4END2_16", + "INT_FEEDTHRU_2_SW4END2" ], [ - "MONITOR_FAN6_0", - "VFRAME_FAN6" + "CFG_CENTER_SW4END3_16", + "INT_FEEDTHRU_2_SW4END3" ], [ - "MONITOR_BYP5_0", - "VFRAME_BYP5" + "CFG_CENTER_WL1END0_16", + "INT_FEEDTHRU_2_WL1END0" ], [ - "MONITOR_WW4A1_0", - "VFRAME_WW4A1" + "CFG_CENTER_WL1END1_16", + "INT_FEEDTHRU_2_WL1END1" ], [ - "MONITOR_EE4A1_0", - "VFRAME_EE4A1" + "CFG_CENTER_WL1END2_16", + "INT_FEEDTHRU_2_WL1END2" ], [ - "MONITOR_NE4BEG0_0", - "VFRAME_NE4BEG0" + "CFG_CENTER_WL1END3_16", + "INT_FEEDTHRU_2_WL1END3" ], [ - "MONITOR_NW4A0_0", - "VFRAME_NW4A0" + "CFG_CENTER_WR1END0_16", + "INT_FEEDTHRU_2_WR1END0" ], [ - "MONITOR_FAN3_0", - "VFRAME_FAN3" + "CFG_CENTER_WR1END1_16", + "INT_FEEDTHRU_2_WR1END1" ], [ - "MONITOR_SE2A0_0", - "VFRAME_SE2A0" + "CFG_CENTER_WR1END2_16", + "INT_FEEDTHRU_2_WR1END2" ], [ - "MONITOR_CLK0_0", - "VFRAME_CLK0" + "CFG_CENTER_WR1END3_16", + "INT_FEEDTHRU_2_WR1END3" ], [ - "MONITOR_WR1END1_0", - "VFRAME_WR1END1" + "CFG_CENTER_WW2A0_16", + "INT_FEEDTHRU_2_WW2A0" ], [ - "MONITOR_WW2END1_0", - "VFRAME_WW2END1" + "CFG_CENTER_WW2A1_16", + "INT_FEEDTHRU_2_WW2A1" ], [ - "MONITOR_LH11_0", - "VFRAME_LH11" + "CFG_CENTER_WW2A2_16", + "INT_FEEDTHRU_2_WW2A2" ], [ - "MONITOR_EE4BEG3_0", - "VFRAME_EE4BEG3" + "CFG_CENTER_WW2A3_16", + "INT_FEEDTHRU_2_WW2A3" ], [ - "MONITOR_IMUX10_0", - "VFRAME_IMUX10" + "CFG_CENTER_WW2END0_16", + "INT_FEEDTHRU_2_WW2END0" ], [ - "MONITOR_IMUX13_0", - "VFRAME_IMUX13" + "CFG_CENTER_WW2END1_16", + "INT_FEEDTHRU_2_WW2END1" ], [ - "MONITOR_SE4BEG2_0", - "VFRAME_SE4BEG2" + "CFG_CENTER_WW2END2_16", + "INT_FEEDTHRU_2_WW2END2" ], [ - "MONITOR_IMUX22_0", - "VFRAME_IMUX22" + "CFG_CENTER_WW2END3_16", + "INT_FEEDTHRU_2_WW2END3" ], [ - "MONITOR_EE4B1_0", - "VFRAME_EE4B1" + "CFG_CENTER_WW4A0_16", + "INT_FEEDTHRU_2_WW4A0" ], [ - "MONITOR_IMUX8_0", - "VFRAME_IMUX8" + "CFG_CENTER_WW4A1_16", + "INT_FEEDTHRU_2_WW4A1" ], [ - "MONITOR_SE2A3_0", - "VFRAME_SE2A3" + "CFG_CENTER_WW4A2_16", + "INT_FEEDTHRU_2_WW4A2" ], [ - "MONITOR_WW2A2_0", - "VFRAME_WW2A2" + "CFG_CENTER_WW4A3_16", + "INT_FEEDTHRU_2_WW4A3" ], [ - "MONITOR_HORIZ_VAUXP12", - "VFRAME_MONITOR_P" + "CFG_CENTER_WW4B0_16", + "INT_FEEDTHRU_2_WW4B0" ], [ - "MONITOR_NE2A2_0", - "VFRAME_NE2A2" + "CFG_CENTER_WW4B1_16", + "INT_FEEDTHRU_2_WW4B1" ], [ - "MONITOR_IMUX25_0", - "VFRAME_IMUX25" + "CFG_CENTER_WW4B2_16", + "INT_FEEDTHRU_2_WW4B2" ], [ - "MONITOR_IMUX2_0", - "VFRAME_IMUX2" + "CFG_CENTER_WW4B3_16", + "INT_FEEDTHRU_2_WW4B3" ], [ - "MONITOR_IMUX19_0", - "VFRAME_IMUX19" + "CFG_CENTER_WW4C0_16", + "INT_FEEDTHRU_2_WW4C0" ], [ - "MONITOR_FAN5_0", - "VFRAME_FAN5" + "CFG_CENTER_WW4C1_16", + "INT_FEEDTHRU_2_WW4C1" ], [ - "MONITOR_BYP6_0", - "VFRAME_BYP6" + "CFG_CENTER_WW4C2_16", + "INT_FEEDTHRU_2_WW4C2" ], [ - "MONITOR_IMUX39_0", - "VFRAME_IMUX39" + "CFG_CENTER_WW4C3_16", + "INT_FEEDTHRU_2_WW4C3" ], [ - "MONITOR_EE2BEG1_0", - "VFRAME_EE2BEG1" + "CFG_CENTER_WW4END0_16", + "INT_FEEDTHRU_2_WW4END0" ], [ - "MONITOR_NW4END1_0", - "VFRAME_NW4END1" + "CFG_CENTER_WW4END1_16", + "INT_FEEDTHRU_2_WW4END1" ], [ - "MONITOR_IMUX44_0", - "VFRAME_IMUX44" + "CFG_CENTER_WW4END2_16", + "INT_FEEDTHRU_2_WW4END2" ], [ - "MONITOR_ER1BEG3_0", - "VFRAME_ER1BEG3" + "CFG_CENTER_WW4END3_16", + "INT_FEEDTHRU_2_WW4END3" ] ] }, @@ -79661,90 +36381,5502 @@ -5 ], "tile_types": [ - "CFG_CENTER_TOP", + "CFG_CENTER_BOT", "INT_FEEDTHRU_2" ], "wire_pairs": [ [ - "CFG_CENTER_WL1END1_5", + "CFG_CENTER_EE2A0_15", + "INT_FEEDTHRU_2_EE2A0" + ], + [ + "CFG_CENTER_EE2A1_15", + "INT_FEEDTHRU_2_EE2A1" + ], + [ + "CFG_CENTER_EE2A2_15", + "INT_FEEDTHRU_2_EE2A2" + ], + [ + "CFG_CENTER_EE2A3_15", + "INT_FEEDTHRU_2_EE2A3" + ], + [ + "CFG_CENTER_EE2BEG0_15", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_EE2BEG1_15", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE2BEG2_15", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_EE2BEG3_15", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_EE4A0_15", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4A1_15", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE4A2_15", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4A3_15", + "INT_FEEDTHRU_2_EE4A3" + ], + [ + "CFG_CENTER_EE4B0_15", + "INT_FEEDTHRU_2_EE4B0" + ], + [ + "CFG_CENTER_EE4B1_15", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE4B2_15", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4B3_15", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE4BEG0_15", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG1_15", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG2_15", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_EE4BEG3_15", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EE4C0_15", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EE4C1_15", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4C2_15", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_EE4C3_15", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EL1BEG0_15", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EL1BEG1_15", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_EL1BEG2_15", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_15", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_ER1BEG0_15", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_ER1BEG1_15", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_ER1BEG2_15", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG3_15", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + 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"CFG_CENTER_WW2END3_5", "INT_FEEDTHRU_2_WW2END3" ], [ - "CFG_CENTER_NE2A0_5", - "INT_FEEDTHRU_2_NE2A0" - ], - [ - "CFG_CENTER_WW4A3_5", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_EE4C3_5", - "INT_FEEDTHRU_2_EE4C3" - ], - [ - "CFG_CENTER_ER1BEG1_5", - "INT_FEEDTHRU_2_ER1BEG1" - ], - [ - "CFG_CENTER_EL1BEG1_5", - "INT_FEEDTHRU_2_EL1BEG1" - ], - [ - "CFG_CENTER_SW2A2_5", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_SW4A3_5", - "INT_FEEDTHRU_2_SW4A3" - ], - [ - "CFG_CENTER_SE4BEG3_5", - "INT_FEEDTHRU_2_SE4BEG3" - ], - [ - "CFG_CENTER_LH2_5", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_WW4END1_5", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_SW2A1_5", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_LH8_5", - "INT_FEEDTHRU_2_LH8" - ], - [ - "CFG_CENTER_EE4B1_5", - "INT_FEEDTHRU_2_EE4B1" - ], - [ - "CFG_CENTER_EL1BEG3_5", - "INT_FEEDTHRU_2_EL1BEG3" - ], - [ - "CFG_CENTER_NE4BEG0_5", - "INT_FEEDTHRU_2_NE4BEG0" - ], - [ - "CFG_CENTER_ER1BEG3_5", - "INT_FEEDTHRU_2_ER1BEG3" - ], - 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+ [ + "CFG_CENTER_IMUX42_13", + "VFRAME_IMUX42" + ], + [ + "CFG_CENTER_IMUX43_13", + "VFRAME_IMUX43" + ], + [ + "CFG_CENTER_IMUX44_13", + "VFRAME_IMUX44" + ], + [ + "CFG_CENTER_IMUX45_13", + "VFRAME_IMUX45" + ], + [ + "CFG_CENTER_IMUX46_13", + "VFRAME_IMUX46" + ], + [ + "CFG_CENTER_IMUX47_13", + "VFRAME_IMUX47" + ], + [ + "CFG_CENTER_LH1_13", + "VFRAME_LH1" + ], + [ + "CFG_CENTER_LH2_13", + "VFRAME_LH2" + ], + [ + "CFG_CENTER_LH3_13", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_LH4_13", + "VFRAME_LH4" + ], + [ + "CFG_CENTER_LH5_13", + "VFRAME_LH5" + ], + [ + "CFG_CENTER_LH6_13", + "VFRAME_LH6" + ], + [ + "CFG_CENTER_LH7_13", + "VFRAME_LH7" + ], + [ + "CFG_CENTER_LH8_13", + "VFRAME_LH8" + ], + [ + "CFG_CENTER_LH9_13", + "VFRAME_LH9" + ], + [ + "CFG_CENTER_LH10_13", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_LH11_13", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_LH12_13", + "VFRAME_LH12" + ], + [ + "CFG_CENTER_NE2A0_13", + "VFRAME_NE2A0" + ], + [ + "CFG_CENTER_NE2A1_13", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_NE2A2_13", + "VFRAME_NE2A2" + ], + [ + "CFG_CENTER_NE2A3_13", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_NE4BEG0_13", + "VFRAME_NE4BEG0" + ], + [ + "CFG_CENTER_NE4BEG1_13", + "VFRAME_NE4BEG1" + ], + [ + "CFG_CENTER_NE4BEG2_13", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_NE4BEG3_13", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NE4C0_13", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_NE4C1_13", + "VFRAME_NE4C1" + ], + [ + "CFG_CENTER_NE4C2_13", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_NE4C3_13", + "VFRAME_NE4C3" + ], + [ + "CFG_CENTER_NW2A0_13", + "VFRAME_NW2A0" + ], + [ + "CFG_CENTER_NW2A1_13", + "VFRAME_NW2A1" + ], + [ + "CFG_CENTER_NW2A2_13", + "VFRAME_NW2A2" + ], + [ + "CFG_CENTER_NW2A3_13", + "VFRAME_NW2A3" + ], + [ + "CFG_CENTER_NW4A0_13", + "VFRAME_NW4A0" + ], + [ + "CFG_CENTER_NW4A1_13", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_NW4A2_13", + "VFRAME_NW4A2" + ], + [ + "CFG_CENTER_NW4A3_13", + "VFRAME_NW4A3" + ], + [ + "CFG_CENTER_NW4END0_13", + "VFRAME_NW4END0" + ], + [ + "CFG_CENTER_NW4END1_13", + "VFRAME_NW4END1" + ], + [ + "CFG_CENTER_NW4END2_13", + "VFRAME_NW4END2" + ], + [ + "CFG_CENTER_NW4END3_13", + "VFRAME_NW4END3" + ], + [ + "CFG_CENTER_SE2A0_13", + "VFRAME_SE2A0" + ], + [ + "CFG_CENTER_SE2A1_13", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_SE2A2_13", + "VFRAME_SE2A2" + ], + [ + "CFG_CENTER_SE2A3_13", + "VFRAME_SE2A3" + ], + [ + "CFG_CENTER_SE4BEG0_13", + "VFRAME_SE4BEG0" + ], + [ + "CFG_CENTER_SE4BEG1_13", + "VFRAME_SE4BEG1" + ], + [ + "CFG_CENTER_SE4BEG2_13", + "VFRAME_SE4BEG2" + ], + [ + "CFG_CENTER_SE4BEG3_13", + "VFRAME_SE4BEG3" + ], + [ + "CFG_CENTER_SE4C0_13", + "VFRAME_SE4C0" + ], + [ + "CFG_CENTER_SE4C1_13", + "VFRAME_SE4C1" + ], + [ + "CFG_CENTER_SE4C2_13", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_SE4C3_13", + "VFRAME_SE4C3" + ], + [ + "CFG_CENTER_SW2A0_13", + "VFRAME_SW2A0" + ], + [ + "CFG_CENTER_SW2A1_13", + "VFRAME_SW2A1" + ], + [ + "CFG_CENTER_SW2A2_13", + "VFRAME_SW2A2" + ], + [ + "CFG_CENTER_SW2A3_13", + "VFRAME_SW2A3" + ], + [ + "CFG_CENTER_SW4A0_13", + "VFRAME_SW4A0" + ], + [ + "CFG_CENTER_SW4A1_13", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_SW4A2_13", + "VFRAME_SW4A2" + ], + [ + "CFG_CENTER_SW4A3_13", + "VFRAME_SW4A3" + ], + [ + "CFG_CENTER_SW4END0_13", + "VFRAME_SW4END0" + ], + [ + "CFG_CENTER_SW4END1_13", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_SW4END2_13", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_SW4END3_13", + "VFRAME_SW4END3" + ], + [ + "CFG_CENTER_WL1END0_13", + "VFRAME_WL1END0" + ], + [ + "CFG_CENTER_WL1END1_13", + "VFRAME_WL1END1" + ], + [ + "CFG_CENTER_WL1END2_13", + "VFRAME_WL1END2" + ], + [ + "CFG_CENTER_WL1END3_13", + "VFRAME_WL1END3" + ], + [ + "CFG_CENTER_WR1END0_13", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_WR1END1_13", + "VFRAME_WR1END1" + ], + [ + "CFG_CENTER_WR1END2_13", + "VFRAME_WR1END2" + ], + [ + "CFG_CENTER_WR1END3_13", + "VFRAME_WR1END3" + ], + [ + "CFG_CENTER_WW2A0_13", + "VFRAME_WW2A0" + ], + [ + "CFG_CENTER_WW2A1_13", + "VFRAME_WW2A1" + ], + [ + "CFG_CENTER_WW2A2_13", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_WW2A3_13", + "VFRAME_WW2A3" + ], + [ + "CFG_CENTER_WW2END0_13", + "VFRAME_WW2END0" + ], + [ + "CFG_CENTER_WW2END1_13", + "VFRAME_WW2END1" + ], + [ + "CFG_CENTER_WW2END2_13", + "VFRAME_WW2END2" + ], + [ + "CFG_CENTER_WW2END3_13", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_WW4A0_13", + "VFRAME_WW4A0" + ], + [ + "CFG_CENTER_WW4A1_13", + "VFRAME_WW4A1" + ], + [ + "CFG_CENTER_WW4A2_13", + "VFRAME_WW4A2" + ], + [ + "CFG_CENTER_WW4A3_13", + "VFRAME_WW4A3" + ], + [ + "CFG_CENTER_WW4B0_13", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_WW4B1_13", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_WW4B2_13", + "VFRAME_WW4B2" + ], + [ + "CFG_CENTER_WW4B3_13", + "VFRAME_WW4B3" + ], + [ + "CFG_CENTER_WW4C0_13", + "VFRAME_WW4C0" + ], + [ + "CFG_CENTER_WW4C1_13", + "VFRAME_WW4C1" + ], + [ + "CFG_CENTER_WW4C2_13", + "VFRAME_WW4C2" + ], + [ + "CFG_CENTER_WW4C3_13", + "VFRAME_WW4C3" + ], + [ + "CFG_CENTER_WW4END0_13", + "VFRAME_WW4END0" + ], + [ + "CFG_CENTER_WW4END1_13", + "VFRAME_WW4END1" + ], + [ + "CFG_CENTER_WW4END2_13", + "VFRAME_WW4END2" + ], + [ + "CFG_CENTER_WW4END3_13", + "VFRAME_WW4END3" ] ] }, @@ -80825,609 +50025,51261 @@ -2 ], "tile_types": [ - "CLK_PMV", - "VBRK" + "CFG_CENTER_BOT", + "VFRAME" ], "wire_pairs": [ [ - "CLK_PMV_EL1BEG2_2", - "VBRK_EL1BEG2" + "CFG_CENTER_BYP0_12", + "VFRAME_BYP0" ], [ - "CLK_PMV_LH10_2", - "VBRK_LH10" + "CFG_CENTER_BYP1_12", + "VFRAME_BYP1" ], [ - "CLK_PMV_SW2A2_2", - "VBRK_SW2A2" + "CFG_CENTER_BYP2_12", + "VFRAME_BYP2" ], [ - "CLK_PMV_WW2END3_2", - "VBRK_WW2END3" + "CFG_CENTER_BYP3_12", + "VFRAME_BYP3" ], [ - "CLK_PMV_EE4BEG3_2", - "VBRK_EE4BEG3" + "CFG_CENTER_BYP4_12", + "VFRAME_BYP4" ], [ - "CLK_PMV_NW4A0_2", - "VBRK_NW4A0" + "CFG_CENTER_BYP5_12", + "VFRAME_BYP5" ], [ - "CLK_PMV_WW4B2_2", - "VBRK_WW4B2" + "CFG_CENTER_BYP6_12", + "VFRAME_BYP6" ], [ - "CLK_PMV_NE4C3_2", - "VBRK_NE4C3" + "CFG_CENTER_BYP7_12", + "VFRAME_BYP7" ], [ - "CLK_PMV_EE4BEG0_2", - "VBRK_EE4BEG0" + "CFG_CENTER_CLK0_12", + "VFRAME_CLK0" ], [ - "CLK_PMV_WW2A1_2", - "VBRK_WW2A1" + "CFG_CENTER_CLK1_12", + "VFRAME_CLK1" ], [ - "CLK_PMV_LH5_2", - "VBRK_LH5" + "CFG_CENTER_CTRL0_12", + "VFRAME_CTRL0" ], [ - "CLK_PMV_LH4_2", - "VBRK_LH4" + "CFG_CENTER_CTRL1_12", + "VFRAME_CTRL1" ], [ - "CLK_PMV_NW2A3_2", - "VBRK_NW2A3" + "CFG_CENTER_EE2A0_12", + "VFRAME_EE2A0" ], [ - "CLK_PMV_WR1END0_2", - "VBRK_WR1END0" + "CFG_CENTER_EE2A1_12", + "VFRAME_EE2A1" ], [ - "CLK_PMV_EE4C2_2", - "VBRK_EE4C2" + "CFG_CENTER_EE2A2_12", + "VFRAME_EE2A2" ], [ - "CLK_PMV_LH3_2", - "VBRK_LH3" + "CFG_CENTER_EE2A3_12", + "VFRAME_EE2A3" ], [ - "CLK_PMV_NW4END3_2", - "VBRK_NW4END3" + "CFG_CENTER_EE2BEG0_12", + "VFRAME_EE2BEG0" ], [ - "CLK_PMV_NE2A0_2", - "VBRK_NE2A0" + "CFG_CENTER_EE2BEG1_12", + "VFRAME_EE2BEG1" ], [ - "CLK_PMV_EE2BEG0_2", - "VBRK_EE2BEG0" + "CFG_CENTER_EE2BEG2_12", + "VFRAME_EE2BEG2" ], [ - "CLK_PMV_EE4BEG2_2", - "VBRK_EE4BEG2" + "CFG_CENTER_EE2BEG3_12", + "VFRAME_EE2BEG3" ], [ - "CLK_PMV_NW4A3_2", - "VBRK_NW4A3" + "CFG_CENTER_EE4A0_12", + "VFRAME_EE4A0" ], [ - "CLK_PMV_LH12_2", - "VBRK_LH12" + "CFG_CENTER_EE4A1_12", + "VFRAME_EE4A1" ], [ - "CLK_PMV_NE4C0_2", - "VBRK_NE4C0" + "CFG_CENTER_EE4A2_12", + "VFRAME_EE4A2" ], [ - "CLK_PMV_SE4BEG3_2", - "VBRK_SE4BEG3" + "CFG_CENTER_EE4A3_12", + "VFRAME_EE4A3" ], [ - "CLK_PMV_SE4BEG0_2", - "VBRK_SE4BEG0" + "CFG_CENTER_EE4B0_12", + "VFRAME_EE4B0" ], [ - "CLK_PMV_EE2A0_2", - "VBRK_EE2A0" + "CFG_CENTER_EE4B1_12", + "VFRAME_EE4B1" ], [ - "CLK_PMV_SE2A2_2", - "VBRK_SE2A2" + "CFG_CENTER_EE4B2_12", + "VFRAME_EE4B2" ], [ - "CLK_PMV_EE4C1_2", - "VBRK_EE4C1" + "CFG_CENTER_EE4B3_12", + "VFRAME_EE4B3" ], [ - "CLK_PMV_EE4A0_2", - "VBRK_EE4A0" + "CFG_CENTER_EE4BEG0_12", + "VFRAME_EE4BEG0" ], [ - "CLK_PMV_LH2_2", - "VBRK_LH2" + "CFG_CENTER_EE4BEG1_12", + "VFRAME_EE4BEG1" ], [ - "CLK_PMV_NW2A2_2", - "VBRK_NW2A2" + "CFG_CENTER_EE4BEG2_12", + "VFRAME_EE4BEG2" ], [ - "CLK_PMV_ER1BEG2_2", - "VBRK_ER1BEG2" + "CFG_CENTER_EE4BEG3_12", + "VFRAME_EE4BEG3" ], [ - "CLK_PMV_SW4END2_2", - "VBRK_SW4END2" + "CFG_CENTER_EE4C0_12", + "VFRAME_EE4C0" ], [ - "CLK_PMV_WW2A3_2", - "VBRK_WW2A3" + "CFG_CENTER_EE4C1_12", + "VFRAME_EE4C1" ], [ - "CLK_PMV_SE4C3_2", - "VBRK_SE4C3" + "CFG_CENTER_EE4C2_12", + "VFRAME_EE4C2" ], [ - "CLK_PMV_SE2A1_2", - "VBRK_SE2A1" + "CFG_CENTER_EE4C3_12", + "VFRAME_EE4C3" ], [ - "CLK_PMV_NW4END2_2", - "VBRK_NW4END2" + "CFG_CENTER_EL1BEG0_12", + "VFRAME_EL1BEG0" ], [ - "CLK_PMV_NE4BEG2_2", - "VBRK_NE4BEG2" + "CFG_CENTER_EL1BEG1_12", + "VFRAME_EL1BEG1" ], [ - "CLK_PMV_NW4A1_2", - "VBRK_NW4A1" + "CFG_CENTER_EL1BEG2_12", + "VFRAME_EL1BEG2" ], [ - "CLK_PMV_EE4C0_2", - "VBRK_EE4C0" + "CFG_CENTER_EL1BEG3_12", + "VFRAME_EL1BEG3" ], [ - "CLK_PMV_SW2A3_2", - "VBRK_SW2A3" + "CFG_CENTER_ER1BEG0_12", + "VFRAME_ER1BEG0" ], [ - "CLK_PMV_NE4C2_2", - "VBRK_NE4C2" + "CFG_CENTER_ER1BEG1_12", + "VFRAME_ER1BEG1" ], [ - "CLK_PMV_SW4END1_2", - "VBRK_SW4END1" + "CFG_CENTER_ER1BEG2_12", + "VFRAME_ER1BEG2" ], [ - "CLK_PMV_NE4BEG1_2", - "VBRK_NE4BEG1" + "CFG_CENTER_ER1BEG3_12", + "VFRAME_ER1BEG3" ], [ - "CLK_PMV_WR1END3_2", - "VBRK_WR1END3" + "CFG_CENTER_FAN0_12", + "VFRAME_FAN0" ], [ - "CLK_PMV_EE2BEG2_2", - "VBRK_EE2BEG2" + "CFG_CENTER_FAN1_12", + "VFRAME_FAN1" ], [ - "CLK_PMV_SW4A1_2", - "VBRK_SW4A1" + "CFG_CENTER_FAN2_12", + "VFRAME_FAN2" ], [ - "CLK_PMV_WW4A1_2", - "VBRK_WW4A1" + "CFG_CENTER_FAN3_12", + "VFRAME_FAN3" ], [ - "CLK_PMV_EE4A2_2", - "VBRK_EE4A2" + "CFG_CENTER_FAN4_12", + "VFRAME_FAN4" ], [ - "CLK_PMV_WW2A2_2", - "VBRK_WW2A2" + "CFG_CENTER_FAN5_12", + "VFRAME_FAN5" ], [ - "CLK_PMV_EE4B0_2", - "VBRK_EE4B0" + "CFG_CENTER_FAN6_12", + "VFRAME_FAN6" ], [ - "CLK_PMV_ER1BEG0_2", - "VBRK_ER1BEG0" + "CFG_CENTER_FAN7_12", + "VFRAME_FAN7" ], [ - "CLK_PMV_NW2A0_2", - "VBRK_NW2A0" + "CFG_CENTER_IMUX0_12", + "VFRAME_IMUX0" ], [ - "CLK_PMV_EE4B1_2", - "VBRK_EE4B1" + "CFG_CENTER_IMUX1_12", + "VFRAME_IMUX1" ], [ - "CLK_PMV_SW4A3_2", - "VBRK_SW4A3" + "CFG_CENTER_IMUX2_12", + "VFRAME_IMUX2" ], [ - "CLK_PMV_LH7_2", - "VBRK_LH7" + "CFG_CENTER_IMUX3_12", + "VFRAME_IMUX3" ], [ - "CLK_PMV_MONITOR_P_2", - "VBRK_MONITOR_P" + "CFG_CENTER_IMUX4_12", + "VFRAME_IMUX4" ], [ - "CLK_PMV_NE2A2_2", - "VBRK_NE2A2" + "CFG_CENTER_IMUX5_12", + "VFRAME_IMUX5" ], [ - "CLK_PMV_WR1END1_2", - "VBRK_WR1END1" + "CFG_CENTER_IMUX6_12", + "VFRAME_IMUX6" ], [ - "CLK_PMV_SW2A1_2", - "VBRK_SW2A1" + "CFG_CENTER_IMUX7_12", + "VFRAME_IMUX7" ], [ - "CLK_PMV_WW2A0_2", - "VBRK_WW2A0" + "CFG_CENTER_IMUX8_12", + "VFRAME_IMUX8" ], [ - "CLK_PMV_WW2END0_2", - "VBRK_WW2END0" + "CFG_CENTER_IMUX9_12", + "VFRAME_IMUX9" ], [ - "CLK_PMV_NW4A2_2", - "VBRK_NW4A2" + "CFG_CENTER_IMUX10_12", + "VFRAME_IMUX10" ], [ - "CLK_PMV_NW4END1_2", - "VBRK_NW4END1" + "CFG_CENTER_IMUX11_12", + "VFRAME_IMUX11" ], [ - "CLK_PMV_WW4END0_2", - "VBRK_WW4END0" + "CFG_CENTER_IMUX12_12", + "VFRAME_IMUX12" ], [ - "CLK_PMV_WW4C1_2", - "VBRK_WW4C1" + "CFG_CENTER_IMUX13_12", + "VFRAME_IMUX13" ], [ - "CLK_PMV_EE2BEG3_2", - "VBRK_EE2BEG3" + "CFG_CENTER_IMUX14_12", + "VFRAME_IMUX14" ], [ - "CLK_PMV_WL1END0_2", - "VBRK_WL1END0" + "CFG_CENTER_IMUX15_12", + "VFRAME_IMUX15" ], [ - "CLK_PMV_EE4B2_2", - "VBRK_EE4B2" + "CFG_CENTER_IMUX16_12", + "VFRAME_IMUX16" ], [ - "CLK_PMV_WR1END2_2", - "VBRK_WR1END2" + "CFG_CENTER_IMUX17_12", + "VFRAME_IMUX17" ], [ - "CLK_PMV_ER1BEG3_2", - "VBRK_ER1BEG3" + "CFG_CENTER_IMUX18_12", + "VFRAME_IMUX18" ], [ - "CLK_PMV_SW4A0_2", - "VBRK_SW4A0" + "CFG_CENTER_IMUX19_12", + "VFRAME_IMUX19" ], [ - "CLK_PMV_WW4END1_2", - "VBRK_WW4END1" + "CFG_CENTER_IMUX20_12", + "VFRAME_IMUX20" ], [ - "CLK_PMV_SW4END3_2", - "VBRK_SW4END3" + "CFG_CENTER_IMUX21_12", + "VFRAME_IMUX21" ], [ - "CLK_PMV_NE4BEG3_2", - "VBRK_NE4BEG3" + "CFG_CENTER_IMUX22_12", + "VFRAME_IMUX22" ], [ - "CLK_PMV_SE2A3_2", - "VBRK_SE2A3" + "CFG_CENTER_IMUX23_12", + "VFRAME_IMUX23" ], [ - "CLK_PMV_WW4C0_2", - "VBRK_WW4C0" + "CFG_CENTER_IMUX24_12", + "VFRAME_IMUX24" ], [ - "CLK_PMV_WW4B3_2", - "VBRK_WW4B3" + "CFG_CENTER_IMUX25_12", + "VFRAME_IMUX25" ], [ - "CLK_PMV_NW2A1_2", - "VBRK_NW2A1" + "CFG_CENTER_IMUX26_12", + "VFRAME_IMUX26" ], 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"CLBLL_L", + "HCLK_CLB" + ], + "wire_pairs": [ + [ + "CLBLL_LL_COUT_N", + "HCLK_CLB_COUT0_L" + ], + [ + "CLBLL_L_COUT_N", + "HCLK_CLB_COUT1_L" ] ] }, @@ -81441,1449 +101293,897 @@ "HCLK_CLB" ], "wire_pairs": [ - [ - "CLBLL_L_CIN", - "HCLK_CLB_COUT1_L" - ], [ "CLBLL_LL_CIN", "HCLK_CLB_COUT0_L" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "CLK_FEED", - "CLK_HROW_BOT_R" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_HROW_R_CK_GCLK9" ], [ - "CLK_FEED_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK23" + "CLBLL_L_CIN", + "HCLK_CLB_COUT1_L" ] ] }, { "grid_deltas": [ 1, - 2 + 0 ], "tile_types": [ - "CMT_TOP_R_LOWER_B", - "VBRK" + "CLBLL_L", + "INT_L" ], "wire_pairs": [ [ - "CMT_TOP_EE4A0_6", - "VBRK_EE4A0" + "CLBLL_BYP0", + "BYP_L0" ], [ - "CMT_TOP_WW4A1_6", - "VBRK_WW4A1" + "CLBLL_BYP1", + "BYP_L1" ], [ - "CMT_TOP_EE4C0_6", - "VBRK_EE4C0" + "CLBLL_BYP2", + "BYP_L2" ], [ - "CMT_TOP_NE4C0_6", - "VBRK_NE4C0" + "CLBLL_BYP3", + "BYP_L3" ], [ - "CMT_TOP_NW4A1_6", - "VBRK_NW4A1" + "CLBLL_BYP4", + "BYP_L4" ], [ - "CMT_TOP_WW4B2_6", - "VBRK_WW4B2" + "CLBLL_BYP5", + "BYP_L5" ], [ - "CMT_TOP_SE4BEG0_6", - "VBRK_SE4BEG0" + "CLBLL_BYP6", + "BYP_L6" ], [ - "CMT_TOP_WW2A3_6", - "VBRK_WW2A3" + "CLBLL_BYP7", + "BYP_L7" ], [ - "CMT_TOP_SW4A3_6", - "VBRK_SW4A3" + "CLBLL_CLK0", + "CLK_L0" ], [ - "CMT_TOP_EE2BEG1_6", - "VBRK_EE2BEG1" + "CLBLL_CLK1", + "CLK_L1" ], [ - "CMT_TOP_LH6_6", - "VBRK_LH6" + "CLBLL_CTRL0", + "CTRL_L0" ], [ - "CMT_TOP_LH9_6", - "VBRK_LH9" + "CLBLL_CTRL1", + "CTRL_L1" ], [ - "CMT_TOP_EE4B0_6", - "VBRK_EE4B0" + "CLBLL_EE2A0", + "EE2END0" ], [ - "CMT_TOP_ER1BEG3_6", - "VBRK_ER1BEG3" + "CLBLL_EE2A1", + "EE2END1" ], [ - "CMT_TOP_SW4END0_6", - "VBRK_SW4END0" + "CLBLL_EE2A2", + "EE2END2" ], [ - "CMT_TOP_WW4B1_6", - "VBRK_WW4B1" + "CLBLL_EE2A3", + "EE2END3" ], [ - "CMT_TOP_WW2A2_6", - "VBRK_WW2A2" + "CLBLL_EE2BEG0", + "EE2A0" ], [ - "CMT_TOP_WR1END1_6", - "VBRK_WR1END1" + "CLBLL_EE2BEG1", + "EE2A1" ], [ - "CMT_TOP_NW4A0_6", - "VBRK_NW4A0" + "CLBLL_EE2BEG2", + "EE2A2" ], [ - "CMT_TOP_EL1BEG2_6", - "VBRK_EL1BEG2" + "CLBLL_EE2BEG3", + "EE2A3" ], [ - "CMT_TOP_NE4BEG0_6", - "VBRK_NE4BEG0" + "CLBLL_EE4A0", + "EE4B0" ], [ - "CMT_TOP_EE2A1_6", - "VBRK_EE2A1" + "CLBLL_EE4A1", + "EE4B1" ], [ - "CMT_TOP_SW4A2_6", - "VBRK_SW4A2" + "CLBLL_EE4A2", + "EE4B2" ], [ - "CMT_TOP_EE4A1_6", - "VBRK_EE4A1" + "CLBLL_EE4A3", + "EE4B3" ], [ - "CMT_TOP_WW4END2_6", - "VBRK_WW4END2" + "CLBLL_EE4B0", + "EE4C0" ], [ - "CMT_TOP_EE2A2_6", - "VBRK_EE2A2" + "CLBLL_EE4B1", + "EE4C1" ], [ - "CMT_TOP_WW4A0_6", - "VBRK_WW4A0" + "CLBLL_EE4B2", + "EE4C2" ], [ - "CMT_TOP_ER1BEG2_6", - "VBRK_ER1BEG2" + "CLBLL_EE4B3", + "EE4C3" ], [ - "CMT_TOP_WW4A2_6", - "VBRK_WW4A2" + "CLBLL_EE4BEG0", + "EE4A0" ], [ - "CMT_TOP_NE4BEG3_6", - "VBRK_NE4BEG3" + "CLBLL_EE4BEG1", + "EE4A1" ], [ - "CMT_TOP_SW4END1_6", - "VBRK_SW4END1" + "CLBLL_EE4BEG2", + "EE4A2" ], [ - "CMT_TOP_NE4BEG2_6", - "VBRK_NE4BEG2" + "CLBLL_EE4BEG3", + "EE4A3" ], [ - "CMT_TOP_NW4END2_6", - "VBRK_NW4END2" + "CLBLL_EE4C0", + "EE4END0" ], [ - "CMT_TOP_LH2_6", - "VBRK_LH2" + "CLBLL_EE4C1", + "EE4END1" ], [ - "CMT_TOP_EE4A2_6", - "VBRK_EE4A2" + "CLBLL_EE4C2", + "EE4END2" ], [ - "CMT_TOP_NE2A0_6", - "VBRK_NE2A0" + "CLBLL_EE4C3", + "EE4END3" ], [ - "CMT_TOP_NE4C1_6", - "VBRK_NE4C1" + "CLBLL_EL1BEG0", + "EL1END0" ], [ - "CMT_TOP_NW4A2_6", - "VBRK_NW4A2" + "CLBLL_EL1BEG1", + "EL1END1" ], [ - "CMT_TOP_SW2A1_6", - "VBRK_SW2A1" + "CLBLL_EL1BEG2", + "EL1END2" ], [ - "CMT_TOP_WW4END1_6", - "VBRK_WW4END1" + "CLBLL_EL1BEG3", + "EL1END3" ], [ - "CMT_TOP_WW4END3_6", - "VBRK_WW4END3" + "CLBLL_ER1BEG0", + "ER1END0" ], [ - "CMT_TOP_EE4C3_6", - "VBRK_EE4C3" + "CLBLL_ER1BEG1", + "ER1END1" ], [ - "CMT_TOP_NW2A3_6", - "VBRK_NW2A3" + "CLBLL_ER1BEG2", + "ER1END2" ], [ - "CMT_TOP_SW4A0_6", - "VBRK_SW4A0" + "CLBLL_ER1BEG3", + "ER1END3" ], [ - "CMT_TOP_EE4BEG0_6", - "VBRK_EE4BEG0" + "CLBLL_FAN0", + "FAN_L0" ], [ - "CMT_TOP_NE4C2_6", - "VBRK_NE4C2" + "CLBLL_FAN1", + "FAN_L1" ], [ - "CMT_TOP_EE4BEG1_6", - "VBRK_EE4BEG1" + "CLBLL_FAN2", + "FAN_L2" ], [ - "CMT_TOP_EE2BEG3_6", - "VBRK_EE2BEG3" + "CLBLL_FAN3", + "FAN_L3" ], [ - "CMT_TOP_WW2END2_6", - "VBRK_WW2END2" + "CLBLL_FAN4", + "FAN_L4" ], [ - "CMT_TOP_LH1_6", - "VBRK_LH1" + "CLBLL_FAN5", + "FAN_L5" ], [ - "CMT_TOP_WR1END3_6", - "VBRK_WR1END3" + "CLBLL_FAN6", + "FAN_L6" ], [ - "CMT_TOP_WR1END0_6", - "VBRK_WR1END0" + "CLBLL_FAN7", + "FAN_L7" ], [ - "CMT_TOP_WW2END3_6", - "VBRK_WW2END3" + "CLBLL_IMUX0", + "IMUX_L0" ], [ - "CMT_TOP_WW4END0_6", - "VBRK_WW4END0" + "CLBLL_IMUX1", + "IMUX_L1" ], [ - "CMT_TOP_LH4_6", - "VBRK_LH4" + "CLBLL_IMUX2", + "IMUX_L2" ], [ - "CMT_TOP_SE2A2_6", - "VBRK_SE2A2" + "CLBLL_IMUX3", + "IMUX_L3" ], [ - "CMT_TOP_WW4A3_6", - "VBRK_WW4A3" + "CLBLL_IMUX4", + "IMUX_L4" ], [ - "CMT_TOP_SE4BEG1_6", - "VBRK_SE4BEG1" + "CLBLL_IMUX5", + "IMUX_L5" ], [ - "CMT_TOP_EE4C1_6", - "VBRK_EE4C1" + "CLBLL_IMUX6", + "IMUX_L6" ], [ - "CMT_TOP_NE2A1_6", - "VBRK_NE2A1" + "CLBLL_IMUX7", + "IMUX_L7" ], [ - "CMT_TOP_NE4BEG1_6", - "VBRK_NE4BEG1" + "CLBLL_IMUX8", + "IMUX_L8" ], [ - "CMT_TOP_NW2A2_6", - "VBRK_NW2A2" + "CLBLL_IMUX9", + "IMUX_L9" ], [ - "CMT_TOP_SW4END3_6", - "VBRK_SW4END3" + "CLBLL_IMUX10", + "IMUX_L10" ], [ - "CMT_TOP_SW2A0_6", - "VBRK_SW2A0" + "CLBLL_IMUX11", + "IMUX_L11" ], [ - "CMT_TOP_EE2A0_6", - "VBRK_EE2A0" + "CLBLL_IMUX12", + "IMUX_L12" ], [ - "CMT_TOP_EE4B2_6", - "VBRK_EE4B2" + "CLBLL_IMUX13", + "IMUX_L13" ], [ - "CMT_TOP_EE4C2_6", - "VBRK_EE4C2" + "CLBLL_IMUX14", + "IMUX_L14" ], [ - "CMT_TOP_NW4END1_6", - "VBRK_NW4END1" + "CLBLL_IMUX15", + "IMUX_L15" ], [ - "CMT_TOP_NW2A1_6", - "VBRK_NW2A1" + "CLBLL_IMUX16", + "IMUX_L16" ], [ - "CMT_TOP_SW2A2_6", - "VBRK_SW2A2" + "CLBLL_IMUX17", + "IMUX_L17" ], [ - "CMT_TOP_WW4C3_6", - "VBRK_WW4C3" + "CLBLL_IMUX18", + "IMUX_L18" ], [ - "CMT_TOP_WL1END1_6", - "VBRK_WL1END1" + "CLBLL_IMUX19", + "IMUX_L19" ], [ - "CMT_TOP_ER1BEG0_6", - "VBRK_ER1BEG0" + "CLBLL_IMUX20", + "IMUX_L20" ], [ - "CMT_TOP_SW2A3_6", - "VBRK_SW2A3" + "CLBLL_IMUX21", + "IMUX_L21" ], [ - "CMT_TOP_WW4B0_6", - "VBRK_WW4B0" + "CLBLL_IMUX22", + "IMUX_L22" ], [ - "CMT_TOP_EL1BEG0_6", - "VBRK_EL1BEG0" + "CLBLL_IMUX23", + "IMUX_L23" ], [ - "CMT_TOP_LH3_6", - "VBRK_LH3" + "CLBLL_IMUX24", + "IMUX_L24" ], [ - "CMT_TOP_NE4C3_6", - "VBRK_NE4C3" + "CLBLL_IMUX25", + "IMUX_L25" ], [ - "CMT_TOP_NW2A0_6", - "VBRK_NW2A0" + "CLBLL_IMUX26", + "IMUX_L26" ], [ - "CMT_TOP_SE4C0_6", - "VBRK_SE4C0" + "CLBLL_IMUX27", + "IMUX_L27" ], [ - "CMT_TOP_WL1END2_6", - "VBRK_WL1END2" + "CLBLL_IMUX28", + "IMUX_L28" ], [ - "CMT_TOP_EE4BEG2_6", - "VBRK_EE4BEG2" + "CLBLL_IMUX29", + "IMUX_L29" ], [ - "CMT_TOP_WW4B3_6", - "VBRK_WW4B3" + "CLBLL_IMUX30", + "IMUX_L30" ], [ - "CMT_TOP_WR1END2_6", - "VBRK_WR1END2" + "CLBLL_IMUX31", + "IMUX_L31" ], [ - "CMT_TOP_SE4BEG3_6", - "VBRK_SE4BEG3" + "CLBLL_IMUX32", + "IMUX_L32" ], [ - "CMT_TOP_NW4END3_6", - "VBRK_NW4END3" + "CLBLL_IMUX33", + "IMUX_L33" ], [ - "CMT_TOP_WW2A1_6", - "VBRK_WW2A1" + "CLBLL_IMUX34", + "IMUX_L34" ], [ - "CMT_TOP_WW2END0_6", - "VBRK_WW2END0" + "CLBLL_IMUX35", + "IMUX_L35" ], [ - "CMT_TOP_LH11_6", - "VBRK_LH11" + "CLBLL_IMUX36", + "IMUX_L36" ], [ - "CMT_TOP_LH10_6", - "VBRK_LH10" + "CLBLL_IMUX37", + "IMUX_L37" ], [ - "CMT_TOP_LH8_6", - "VBRK_LH8" + "CLBLL_IMUX38", + "IMUX_L38" ], [ - "CMT_TOP_NE2A3_6", - "VBRK_NE2A3" + "CLBLL_IMUX39", + "IMUX_L39" ], [ - "CMT_TOP_WW4C2_6", - "VBRK_WW4C2" + "CLBLL_IMUX40", + "IMUX_L40" ], [ - "CMT_TOP_SE2A1_6", - "VBRK_SE2A1" + "CLBLL_IMUX41", + "IMUX_L41" ], [ - "CMT_TOP_EL1BEG1_6", - "VBRK_EL1BEG1" + "CLBLL_IMUX42", + "IMUX_L42" ], [ - "CMT_TOP_SE4C1_6", - "VBRK_SE4C1" + "CLBLL_IMUX43", + "IMUX_L43" ], [ - "CMT_TOP_WL1END0_6", - "VBRK_WL1END0" + "CLBLL_IMUX44", + "IMUX_L44" ], [ - "CMT_TOP_SE2A3_6", - "VBRK_SE2A3" + "CLBLL_IMUX45", + "IMUX_L45" ], [ - "CMT_TOP_WW2A0_6", - "VBRK_WW2A0" + "CLBLL_IMUX46", + "IMUX_L46" ], [ - "CMT_TOP_NW4A3_6", - "VBRK_NW4A3" + "CLBLL_IMUX47", + "IMUX_L47" ], [ - "CMT_TOP_LH12_6", - "VBRK_LH12" + "CLBLL_LH1", + "LH0" ], [ - "CMT_TOP_EE4BEG3_6", - "VBRK_EE4BEG3" + "CLBLL_LH2", + "LH1" ], [ - "CMT_TOP_EE2A3_6", - "VBRK_EE2A3" + "CLBLL_LH3", + "LH2" ], [ - "CMT_TOP_SE4C3_6", - "VBRK_SE4C3" + "CLBLL_LH4", + "LH3" ], [ - "CMT_TOP_SE4BEG2_6", - "VBRK_SE4BEG2" + "CLBLL_LH5", + "LH4" ], [ - "CMT_TOP_ER1BEG1_6", - "VBRK_ER1BEG1" + "CLBLL_LH6", + "LH5" ], [ - "CMT_TOP_SW4END2_6", - "VBRK_SW4END2" + "CLBLL_LH7", + "LH6" ], [ - "CMT_TOP_LH5_6", - "VBRK_LH5" + "CLBLL_LH8", + "LH7" ], [ - "CMT_TOP_WW2END1_6", - "VBRK_WW2END1" + "CLBLL_LH9", + "LH8" ], [ - "CMT_TOP_EE4B1_6", - "VBRK_EE4B1" + "CLBLL_LH10", + "LH9" ], [ - "CMT_TOP_EE4B3_6", - "VBRK_EE4B3" + "CLBLL_LH11", + "LH10" ], [ - "CMT_TOP_WW4C1_6", - "VBRK_WW4C1" + "CLBLL_LH12", + "LH11" ], [ - "CMT_TOP_NW4END0_6", - "VBRK_NW4END0" + "CLBLL_LOGIC_OUTS0", + "LOGIC_OUTS_L0" ], [ - "CMT_TOP_SE4C2_6", - "VBRK_SE4C2" + "CLBLL_LOGIC_OUTS1", + "LOGIC_OUTS_L1" ], [ - "CMT_TOP_EE2BEG0_6", - "VBRK_EE2BEG0" + "CLBLL_LOGIC_OUTS2", + "LOGIC_OUTS_L2" ], [ - "CMT_TOP_EE4A3_6", - "VBRK_EE4A3" + "CLBLL_LOGIC_OUTS3", + "LOGIC_OUTS_L3" ], [ - "CMT_TOP_WW4C0_6", - "VBRK_WW4C0" + "CLBLL_LOGIC_OUTS4", + "LOGIC_OUTS_L4" ], [ - "CMT_TOP_SW4A1_6", - "VBRK_SW4A1" + "CLBLL_LOGIC_OUTS5", + "LOGIC_OUTS_L5" ], [ - "CMT_TOP_LH7_6", - "VBRK_LH7" + "CLBLL_LOGIC_OUTS6", + "LOGIC_OUTS_L6" ], [ - "CMT_TOP_EL1BEG3_6", - "VBRK_EL1BEG3" + "CLBLL_LOGIC_OUTS7", + "LOGIC_OUTS_L7" ], [ - "CMT_TOP_EE2BEG2_6", - "VBRK_EE2BEG2" + "CLBLL_LOGIC_OUTS8", + "LOGIC_OUTS_L8" ], [ - "CMT_TOP_SE2A0_6", - "VBRK_SE2A0" + "CLBLL_LOGIC_OUTS9", + "LOGIC_OUTS_L9" ], [ - "CMT_TOP_WL1END3_6", - "VBRK_WL1END3" + "CLBLL_LOGIC_OUTS10", + "LOGIC_OUTS_L10" ], [ - "CMT_TOP_NE2A2_6", - "VBRK_NE2A2" - ] - ] - }, - { - "grid_deltas": [ - -1, - 4 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH1_0", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_SW4END2_0", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_MONITOR_N_0", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NW4END2_0", - "INT_INTERFACE_NW4END2" + "CLBLL_LOGIC_OUTS11", + "LOGIC_OUTS_L11" ], [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" + "CLBLL_LOGIC_OUTS12", + "LOGIC_OUTS_L12" ], [ - "CLK_HROW_LH10_0", - "INT_INTERFACE_LH10" + "CLBLL_LOGIC_OUTS13", + "LOGIC_OUTS_L13" ], [ - "CLK_HROW_IMUX34_0", - "INT_INTERFACE_IMUX34" + "CLBLL_LOGIC_OUTS14", + "LOGIC_OUTS_L14" ], [ - "CLK_HROW_WL1END2_0", - "INT_INTERFACE_WL1END2" + "CLBLL_LOGIC_OUTS15", + "LOGIC_OUTS_L15" ], [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" + "CLBLL_LOGIC_OUTS16", + "LOGIC_OUTS_L16" ], [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" + "CLBLL_LOGIC_OUTS17", + "LOGIC_OUTS_L17" ], [ - "CLK_HROW_IMUX45_0", - "INT_INTERFACE_IMUX45" + "CLBLL_LOGIC_OUTS18", + "LOGIC_OUTS_L18" ], [ - "CLK_HROW_WR1END3_0", - "INT_INTERFACE_WR1END3" + "CLBLL_LOGIC_OUTS19", + "LOGIC_OUTS_L19" ], [ - "CLK_HROW_IMUX9_0", - "INT_INTERFACE_IMUX9" + "CLBLL_LOGIC_OUTS20", + "LOGIC_OUTS_L20" ], [ - "CLK_HROW_LH7_0", - "INT_INTERFACE_LH7" + "CLBLL_LOGIC_OUTS21", + "LOGIC_OUTS_L21" ], [ - "CLK_HROW_WW2A1_0", - "INT_INTERFACE_WW2A1" + "CLBLL_LOGIC_OUTS22", + "LOGIC_OUTS_L22" ], [ - "CLK_HROW_IMUX40_0", - "INT_INTERFACE_IMUX40" + "CLBLL_LOGIC_OUTS23", + "LOGIC_OUTS_L23" ], [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" + "CLBLL_MONITOR_N", + "MONITOR_N" ], [ - "CLK_HROW_WR1END0_0", - "INT_INTERFACE_WR1END0" + "CLBLL_MONITOR_P", + "MONITOR_P" ], [ - "CLK_HROW_IMUX42_0", - "INT_INTERFACE_IMUX42" + "CLBLL_NE2A0", + "NE2END0" ], [ - "CLK_HROW_IMUX17_0", - "INT_INTERFACE_IMUX17" + "CLBLL_NE2A1", + "NE2END1" ], [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" + "CLBLL_NE2A2", + "NE2END2" ], [ - "CLK_HROW_MONITOR_P_0", - "INT_INTERFACE_MONITOR_P" + "CLBLL_NE2A3", + "NE2END3" ], [ - "CLK_HROW_BYP7_0", - "INT_INTERFACE_BYP7" + "CLBLL_NE4BEG0", + "NE6A0" ], [ - "CLK_HROW_EE4A3_0", - "INT_INTERFACE_EE4A3" + "CLBLL_NE4BEG1", + "NE6A1" ], [ - "CLK_HROW_IMUX20_0", - "INT_INTERFACE_IMUX20" + "CLBLL_NE4BEG2", + "NE6A2" ], [ - "CLK_HROW_IMUX13_0", - "INT_INTERFACE_IMUX13" + "CLBLL_NE4BEG3", + "NE6A3" ], [ - "CLK_HROW_SE2A0_0", - "INT_INTERFACE_SE2A0" + "CLBLL_NE4C0", + "NE6END0" ], [ - "CLK_HROW_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" + "CLBLL_NE4C1", + "NE6END1" ], [ - "CLK_HROW_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" + "CLBLL_NE4C2", + "NE6END2" ], [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" + "CLBLL_NE4C3", + "NE6END3" ], [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" + "CLBLL_NW2A0", + "NW2A0" ], [ - "CLK_HROW_EE4B1_0", - "INT_INTERFACE_EE4B1" + "CLBLL_NW2A1", + "NW2A1" ], [ - "CLK_HROW_LH3_0", - "INT_INTERFACE_LH3" + "CLBLL_NW2A2", + "NW2A2" ], [ - "CLK_HROW_NE2A3_0", - "INT_INTERFACE_NE2A3" + "CLBLL_NW2A3", + "NW2A3" ], [ - "CLK_HROW_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" + "CLBLL_NW4A0", + "NW6BEG0" ], [ - "CLK_HROW_IMUX27_0", - "INT_INTERFACE_IMUX27" + "CLBLL_NW4A1", + "NW6BEG1" ], [ - "CLK_HROW_IMUX31_0", - "INT_INTERFACE_IMUX31" + "CLBLL_NW4A2", + "NW6BEG2" ], [ - "CLK_HROW_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" + "CLBLL_NW4A3", + "NW6BEG3" ], [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" + "CLBLL_NW4END0", + "NW6E0" ], [ - "CLK_HROW_IMUX47_0", - "INT_INTERFACE_IMUX47" + "CLBLL_NW4END1", + "NW6E1" ], [ - "CLK_HROW_IMUX1_0", - "INT_INTERFACE_IMUX1" + "CLBLL_NW4END2", + "NW6E2" ], [ - "CLK_HROW_IMUX38_0", - "INT_INTERFACE_IMUX38" + "CLBLL_NW4END3", + "NW6E3" ], [ - "CLK_HROW_IMUX12_0", - "INT_INTERFACE_IMUX12" + "CLBLL_SE2A0", + "SE2END0" ], [ - "CLK_HROW_NW4A3_0", - "INT_INTERFACE_NW4A3" + "CLBLL_SE2A1", + "SE2END1" ], [ - "CLK_HROW_WR1END2_0", - "INT_INTERFACE_WR1END2" + "CLBLL_SE2A2", + "SE2END2" ], [ - "CLK_HROW_IMUX39_0", - "INT_INTERFACE_IMUX39" + "CLBLL_SE2A3", + "SE2END3" ], [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" + "CLBLL_SE4BEG0", + "SE6A0" ], [ - "CLK_HROW_WW4B1_0", - "INT_INTERFACE_WW4B1" + "CLBLL_SE4BEG1", + "SE6A1" ], [ - "CLK_HROW_SE4C2_0", - "INT_INTERFACE_SE4C2" + "CLBLL_SE4BEG2", + "SE6A2" ], [ - "CLK_HROW_EE4C2_0", - "INT_INTERFACE_EE4C2" + "CLBLL_SE4BEG3", + "SE6A3" ], [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" + "CLBLL_SE4C0", + "SE6END0" ], [ - "CLK_HROW_IMUX3_0", - "INT_INTERFACE_IMUX3" + "CLBLL_SE4C1", + "SE6END1" ], [ - "CLK_HROW_EE4A0_0", - "INT_INTERFACE_EE4A0" + "CLBLL_SE4C2", + "SE6END2" ], [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" + "CLBLL_SE4C3", + "SE6END3" ], [ - "CLK_HROW_NW2A0_0", - "INT_INTERFACE_NW2A0" + "CLBLL_SW2A0", + "SW2A0" ], [ - "CLK_HROW_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" + "CLBLL_SW2A1", + "SW2A1" ], [ - "CLK_HROW_IMUX14_0", - "INT_INTERFACE_IMUX14" + "CLBLL_SW2A2", + "SW2A2" ], [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" + "CLBLL_SW2A3", + "SW2A3" ], [ - "CLK_HROW_IMUX23_0", - "INT_INTERFACE_IMUX23" + "CLBLL_SW4A0", + "SW6BEG0" ], [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" + "CLBLL_SW4A1", + "SW6BEG1" ], [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" + "CLBLL_SW4A2", + "SW6BEG2" ], [ - "CLK_HROW_LH9_0", - "INT_INTERFACE_LH9" + "CLBLL_SW4A3", + "SW6BEG3" ], [ - "CLK_HROW_SW4END0_0", - "INT_INTERFACE_SW4END0" + "CLBLL_SW4END0", + "SW6E0" ], [ - "CLK_HROW_IMUX10_0", - "INT_INTERFACE_IMUX10" + "CLBLL_SW4END1", + "SW6E1" ], [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" + "CLBLL_SW4END2", + "SW6E2" ], [ - "CLK_HROW_NE2A0_0", - "INT_INTERFACE_NE2A0" + "CLBLL_SW4END3", + "SW6E3" ], [ - "CLK_HROW_IMUX24_0", - "INT_INTERFACE_IMUX24" + "CLBLL_WL1END0", + "WL1BEG0" ], [ - "CLK_HROW_IMUX16_0", - "INT_INTERFACE_IMUX16" + "CLBLL_WL1END1", + "WL1BEG1" ], [ - "CLK_HROW_SE4C0_0", - "INT_INTERFACE_SE4C0" + "CLBLL_WL1END2", + "WL1BEG2" ], [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" + "CLBLL_WL1END3", + "WL1BEG3" ], [ - "CLK_HROW_FAN4_0", - "INT_INTERFACE_FAN4" + "CLBLL_WR1END0", + "WR1BEG0" ], [ - "CLK_HROW_FAN6_0", - "INT_INTERFACE_FAN6" + "CLBLL_WR1END1", + "WR1BEG1" ], [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" + "CLBLL_WR1END2", + "WR1BEG2" ], [ - "CLK_HROW_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" + "CLBLL_WR1END3", + "WR1BEG3" ], [ - "CLK_HROW_IMUX21_0", - "INT_INTERFACE_IMUX21" + "CLBLL_WW2A0", + "WW2BEG0" ], [ - "CLK_HROW_IMUX35_0", - "INT_INTERFACE_IMUX35" + "CLBLL_WW2A1", + "WW2BEG1" ], [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" + "CLBLL_WW2A2", + "WW2BEG2" ], [ - "CLK_HROW_IMUX33_0", - "INT_INTERFACE_IMUX33" + "CLBLL_WW2A3", + "WW2BEG3" ], [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" + "CLBLL_WW2END0", + "WW2A0" ], [ - "CLK_HROW_WW4END1_0", - "INT_INTERFACE_WW4END1" + "CLBLL_WW2END1", + "WW2A1" ], [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" + "CLBLL_WW2END2", + "WW2A2" ], [ - "CLK_HROW_IMUX26_0", - "INT_INTERFACE_IMUX26" + "CLBLL_WW2END3", + "WW2A3" ], [ - "CLK_HROW_WW4END0_0", - "INT_INTERFACE_WW4END0" + "CLBLL_WW4A0", + "WW4BEG0" ], [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" + "CLBLL_WW4A1", + "WW4BEG1" ], [ - "CLK_HROW_EE4B0_0", - "INT_INTERFACE_EE4B0" + "CLBLL_WW4A2", + "WW4BEG2" ], [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" + "CLBLL_WW4A3", + "WW4BEG3" ], [ - "CLK_HROW_IMUX32_0", - "INT_INTERFACE_IMUX32" + "CLBLL_WW4B0", + "WW4A0" ], [ - "CLK_HROW_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" + "CLBLL_WW4B1", + "WW4A1" ], [ - "CLK_HROW_IMUX29_0", - "INT_INTERFACE_IMUX29" + "CLBLL_WW4B2", + "WW4A2" ], [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" + "CLBLL_WW4B3", + "WW4A3" ], [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" + "CLBLL_WW4C0", + "WW4B0" ], [ - "CLK_HROW_IMUX25_0", - "INT_INTERFACE_IMUX25" + "CLBLL_WW4C1", + "WW4B1" ], [ - "CLK_HROW_IMUX18_0", - "INT_INTERFACE_IMUX18" + "CLBLL_WW4C2", + "WW4B2" ], [ - "CLK_HROW_IMUX8_0", - "INT_INTERFACE_IMUX8" + "CLBLL_WW4C3", + "WW4B3" ], [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" + "CLBLL_WW4END0", + "WW4C0" ], [ - "CLK_HROW_NW4A0_0", - "INT_INTERFACE_NW4A0" + "CLBLL_WW4END1", + "WW4C1" ], [ - "CLK_HROW_WW4C0_0", - "INT_INTERFACE_WW4C0" + "CLBLL_WW4END2", + "WW4C2" ], [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" + "CLBLL_WW4END3", + "WW4C3" ] ] }, @@ -82893,105 +102193,3005 @@ 0 ], "tile_types": [ - "HCLK_FIFO_L", - "HCLK_INT_INTERFACE" + "CLBLL_L", + "VBRK" ], "wire_pairs": [ [ - "HCLK_FIFO_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" + "CLBLL_EE2A0", + "VBRK_EE2A0" ], [ - "HCLK_FIFO_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" + "CLBLL_EE2A1", + "VBRK_EE2A1" ], [ - "HCLK_FIFO_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" + "CLBLL_EE2A2", + "VBRK_EE2A2" ], [ - "HCLK_FIFO_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" + "CLBLL_EE2A3", + "VBRK_EE2A3" ], [ - "HCLK_FIFO_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" + "CLBLL_EE2BEG0", + "VBRK_EE2BEG0" ], [ - "HCLK_FIFO_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" + "CLBLL_EE2BEG1", + "VBRK_EE2BEG1" ], [ - "HCLK_FIFO_CCIO0", - "HCLK_INT_INTERFACE_CCIO0" + "CLBLL_EE2BEG2", + "VBRK_EE2BEG2" ], [ - "HCLK_FIFO_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" + "CLBLL_EE2BEG3", + "VBRK_EE2BEG3" ], [ - "HCLK_FIFO_PERFCLK1", - "HCLK_INT_INTERFACE_PERFCLK1" + "CLBLL_EE4A0", + "VBRK_EE4A0" ], [ - "HCLK_FIFO_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" + "CLBLL_EE4A1", + "VBRK_EE4A1" ], [ - "HCLK_FIFO_PERFCLK2", - "HCLK_INT_INTERFACE_PERFCLK2" + "CLBLL_EE4A2", + "VBRK_EE4A2" ], [ - "HCLK_FIFO_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" + "CLBLL_EE4A3", + "VBRK_EE4A3" ], [ - "HCLK_FIFO_CCIO1", - "HCLK_INT_INTERFACE_CCIO1" + "CLBLL_EE4B0", + "VBRK_EE4B0" ], [ - "HCLK_FIFO_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" + "CLBLL_EE4B1", + "VBRK_EE4B1" ], [ - "HCLK_FIFO_PERFCLK0", - "HCLK_INT_INTERFACE_PERFCLK0" + "CLBLL_EE4B2", + "VBRK_EE4B2" ], [ - "HCLK_FIFO_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" + "CLBLL_EE4B3", + "VBRK_EE4B3" ], [ - "HCLK_FIFO_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" + "CLBLL_EE4BEG0", + "VBRK_EE4BEG0" ], [ - "HCLK_FIFO_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" + "CLBLL_EE4BEG1", + "VBRK_EE4BEG1" ], [ - "HCLK_FIFO_CCIO3", - "HCLK_INT_INTERFACE_CCIO3" + "CLBLL_EE4BEG2", + "VBRK_EE4BEG2" ], [ - "HCLK_FIFO_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" + "CLBLL_EE4BEG3", + "VBRK_EE4BEG3" ], [ - "HCLK_FIFO_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" + "CLBLL_EE4C0", + "VBRK_EE4C0" ], [ - "HCLK_FIFO_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" + "CLBLL_EE4C1", + "VBRK_EE4C1" ], [ - "HCLK_FIFO_CCIO2", - "HCLK_INT_INTERFACE_CCIO2" + "CLBLL_EE4C2", + "VBRK_EE4C2" ], [ - "HCLK_FIFO_PERFCLK3", - "HCLK_INT_INTERFACE_PERFCLK3" + "CLBLL_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLBLL_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLBLL_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLBLL_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLBLL_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLBLL_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLBLL_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + 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"PCIE_INT_INTERFACE_IMUX_OUT42" + "CLBLM_EE4A1", + "CLBLM_EE4A1" ], [ - "PCIE_IMUX32_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT32" + "CLBLM_EE4A2", + "CLBLM_EE4A2" ], [ - "PCIE_LOGIC_OUTS_B20_R_19", - "INT_INTERFACE_LOGIC_OUTS_B20" + "CLBLM_EE4A3", + "CLBLM_EE4A3" ], [ - "PCIE_IMUX11_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT11" + "CLBLM_EE4B0", + "CLBLM_EE4B0" ], [ - "PCIE_WW2A0_19", - "INT_INTERFACE_WW2A0" + "CLBLM_EE4B1", + "CLBLM_EE4B1" ], [ - "PCIE_IMUX9_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT9" + "CLBLM_EE4B2", + "CLBLM_EE4B2" ], [ - "PCIE_IMUX8_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT8" + "CLBLM_EE4B3", + "CLBLM_EE4B3" ], [ - "PCIE_NE2A3_19", - "INT_INTERFACE_NE2A3" + "CLBLM_EE4BEG0", + "CLBLM_EE4BEG0" ], [ - "PCIE_IMUX19_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT19" + "CLBLM_EE4BEG1", + "CLBLM_EE4BEG1" ], [ - "PCIE_BYP6_R_19", - "INT_INTERFACE_BYP6" + "CLBLM_EE4BEG2", + "CLBLM_EE4BEG2" ], [ - "PCIE_LOGIC_OUTS_B3_R_19", - "INT_INTERFACE_LOGIC_OUTS_B3" + "CLBLM_EE4BEG3", + "CLBLM_EE4BEG3" ], [ - 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"INT_INTERFACE_LOGIC_OUTS_B19" + "CLBLM_ER1BEG3", + "CLBLM_ER1BEG3" ], [ - "PCIE_NW2A2_19", - "INT_INTERFACE_NW2A2" + "CLBLM_LH1", + "CLBLM_LH1" ], [ - "PCIE_LH9_19", - "INT_INTERFACE_LH9" + "CLBLM_LH2", + "CLBLM_LH2" ], [ - "PCIE_WW2END2_19", - "INT_INTERFACE_WW2END2" + "CLBLM_LH3", + "CLBLM_LH3" ], [ - "PCIE_LOGIC_OUTS_B11_R_19", - "INT_INTERFACE_LOGIC_OUTS_B11" + "CLBLM_LH4", + "CLBLM_LH4" ], [ - "PCIE_WW4B3_19", - "INT_INTERFACE_WW4B3" + "CLBLM_LH5", + "CLBLM_LH5" ], [ - "PCIE_FAN3_R_19", - "INT_INTERFACE_FAN3" + "CLBLM_LH6", + "CLBLM_LH6" ], [ - "PCIE_SE4C2_19", - "INT_INTERFACE_SE4C2" + "CLBLM_LH7", + "CLBLM_LH7" ], [ - "PCIE_SW4END1_19", - "INT_INTERFACE_SW4END1" + "CLBLM_LH8", + "CLBLM_LH8" ], [ - "PCIE_LH11_19", - "INT_INTERFACE_LH11" + "CLBLM_LH9", + "CLBLM_LH9" ], [ - "PCIE_IMUX39_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT39" + "CLBLM_LH10", + "CLBLM_LH10" ], [ - "PCIE_BYP4_R_19", - "INT_INTERFACE_BYP4" + "CLBLM_LH11", + "CLBLM_LH11" ], [ - "PCIE_LOGIC_OUTS_B8_R_19", - "INT_INTERFACE_LOGIC_OUTS_B8" + "CLBLM_LH12", + "CLBLM_LH12" ], [ - "PCIE_IMUX2_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT2" + "CLBLM_MONITOR_N", + "CLBLM_MONITOR_N" ], [ - "PCIE_IMUX37_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT37" + "CLBLM_MONITOR_P", + "CLBLM_MONITOR_P" ], [ - "PCIE_WW4C2_19", - "INT_INTERFACE_WW4C2" + "CLBLM_NE2A0", + "CLBLM_NE2A0" ], [ - "PCIE_WW4END2_19", - "INT_INTERFACE_WW4END2" + "CLBLM_NE2A1", + "CLBLM_NE2A1" ], [ - "PCIE_ER1BEG3_19", - "INT_INTERFACE_ER1BEG3" + "CLBLM_NE2A2", + "CLBLM_NE2A2" ], [ - "PCIE_EE2BEG1_19", - "INT_INTERFACE_EE2BEG1" + "CLBLM_NE2A3", + "CLBLM_NE2A3" ], [ - "PCIE_EE4A1_19", - "INT_INTERFACE_EE4A1" + "CLBLM_NE4BEG0", + "CLBLM_NE4BEG0" ], [ - "PCIE_LH1_19", - "INT_INTERFACE_LH1" + "CLBLM_NE4BEG1", + "CLBLM_NE4BEG1" ], [ - "PCIE_IMUX3_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT3" + "CLBLM_NE4BEG2", + "CLBLM_NE4BEG2" ], [ - "PCIE_IMUX33_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT33" + "CLBLM_NE4BEG3", + "CLBLM_NE4BEG3" ], [ - "PCIE_FAN0_R_19", - "INT_INTERFACE_FAN0" + "CLBLM_NE4C0", + "CLBLM_NE4C0" ], [ - "PCIE_SE4BEG3_19", - "INT_INTERFACE_SE4BEG3" + "CLBLM_NE4C1", + "CLBLM_NE4C1" ], [ - "PCIE_BYP3_R_19", - "INT_INTERFACE_BYP3" + "CLBLM_NE4C2", + "CLBLM_NE4C2" ], [ - "PCIE_ER1BEG0_19", - "INT_INTERFACE_ER1BEG0" + "CLBLM_NE4C3", + "CLBLM_NE4C3" ], [ - "PCIE_IMUX14_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT14" + "CLBLM_NW2A0", + "CLBLM_NW2A0" ], [ - "PCIE_IMUX16_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT16" + "CLBLM_NW2A1", + "CLBLM_NW2A1" ], [ - "PCIE_EL1BEG2_19", - "INT_INTERFACE_EL1BEG2" + "CLBLM_NW2A2", + "CLBLM_NW2A2" ], [ - "PCIE_NW4A3_19", - "INT_INTERFACE_NW4A3" + "CLBLM_NW2A3", + "CLBLM_NW2A3" ], [ - "PCIE_LH2_19", - "INT_INTERFACE_LH2" + "CLBLM_NW4A0", + "CLBLM_NW4A0" ], [ - "PCIE_NW4A1_19", - "INT_INTERFACE_NW4A1" + "CLBLM_NW4A1", + "CLBLM_NW4A1" ], [ - "PCIE_EL1BEG3_19", - "INT_INTERFACE_EL1BEG3" + "CLBLM_NW4A2", + "CLBLM_NW4A2" ], [ - "PCIE_LH4_19", - "INT_INTERFACE_LH4" + "CLBLM_NW4A3", + "CLBLM_NW4A3" ], [ - "PCIE_IMUX41_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT41" + "CLBLM_NW4END0", + "CLBLM_NW4END0" ], [ - "PCIE_WL1END2_19", - "INT_INTERFACE_WL1END2" + "CLBLM_NW4END1", + "CLBLM_NW4END1" ], [ - "PCIE_EE2A0_19", - "INT_INTERFACE_EE2A0" + "CLBLM_NW4END2", + "CLBLM_NW4END2" ], [ - "PCIE_IMUX44_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT44" + "CLBLM_NW4END3", + "CLBLM_NW4END3" ], [ - "PCIE_EE4A2_19", - "INT_INTERFACE_EE4A2" + "CLBLM_SE2A0", + "CLBLM_SE2A0" ], [ - "PCIE_IMUX17_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT17" + "CLBLM_SE2A1", + "CLBLM_SE2A1" ], [ - "PCIE_FAN5_R_19", - "INT_INTERFACE_FAN5" + "CLBLM_SE2A2", + "CLBLM_SE2A2" ], [ - "PCIE_WW2END0_19", - "INT_INTERFACE_WW2END0" + "CLBLM_SE2A3", + "CLBLM_SE2A3" ], [ - "PCIE_LOGIC_OUTS_B0_R_19", - "INT_INTERFACE_LOGIC_OUTS_B0" + "CLBLM_SE4BEG0", + "CLBLM_SE4BEG0" ], [ - "PCIE_NE2A1_19", - "INT_INTERFACE_NE2A1" + "CLBLM_SE4BEG1", + "CLBLM_SE4BEG1" ], [ - "PCIE_LOGIC_OUTS_B10_R_19", - "INT_INTERFACE_LOGIC_OUTS_B10" + "CLBLM_SE4BEG2", + "CLBLM_SE4BEG2" ], [ - "PCIE_CTRL0_R_19", - "INT_INTERFACE_CTRL0" + "CLBLM_SE4BEG3", + "CLBLM_SE4BEG3" ], [ - "PCIE_IMUX13_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT13" + "CLBLM_SE4C0", + "CLBLM_SE4C0" ], [ - "PCIE_LOGIC_OUTS_B12_R_19", - "INT_INTERFACE_LOGIC_OUTS_B12" + "CLBLM_SE4C1", + "CLBLM_SE4C1" ], [ - "PCIE_EL1BEG0_19", - "INT_INTERFACE_EL1BEG0" + "CLBLM_SE4C2", + "CLBLM_SE4C2" ], [ - "PCIE_LH8_19", - "INT_INTERFACE_LH8" + "CLBLM_SE4C3", + "CLBLM_SE4C3" ], [ - "PCIE_WW4B2_19", - "INT_INTERFACE_WW4B2" + "CLBLM_SW2A0", + "CLBLM_SW2A0" ], [ - "PCIE_WW4C1_19", - "INT_INTERFACE_WW4C1" + "CLBLM_SW2A1", + "CLBLM_SW2A1" ], [ - "PCIE_WW4B1_19", - "INT_INTERFACE_WW4B1" + "CLBLM_SW2A2", + "CLBLM_SW2A2" ], [ - "PCIE_BYP1_R_19", - "INT_INTERFACE_BYP1" + "CLBLM_SW2A3", + "CLBLM_SW2A3" ], [ - "PCIE_LOGIC_OUTS_B7_R_19", - "INT_INTERFACE_LOGIC_OUTS_B7" + "CLBLM_SW4A0", + "CLBLM_SW4A0" ], [ - "PCIE_CLK0_R_19", - "INT_INTERFACE_CLK0" + "CLBLM_SW4A1", + "CLBLM_SW4A1" ], [ - "PCIE_NW4END1_19", - "INT_INTERFACE_NW4END1" + "CLBLM_SW4A2", + "CLBLM_SW4A2" ], [ - "PCIE_SE2A2_19", - "INT_INTERFACE_SE2A2" + "CLBLM_SW4A3", + "CLBLM_SW4A3" ], [ - "PCIE_SW4END2_19", - "INT_INTERFACE_SW4END2" + "CLBLM_SW4END0", + "CLBLM_SW4END0" ], [ - "PCIE_BYP2_R_19", - "INT_INTERFACE_BYP2" + "CLBLM_SW4END1", + "CLBLM_SW4END1" ], [ - "PCIE_IMUX47_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT47" + "CLBLM_SW4END2", + "CLBLM_SW4END2" ], [ - "PCIE_NE2A2_19", - "INT_INTERFACE_NE2A2" + "CLBLM_SW4END3", + "CLBLM_SW4END3" ], [ - "PCIE_WR1END0_19", - "INT_INTERFACE_WR1END0" + "CLBLM_WL1END0", + "CLBLM_WL1END0" ], [ - "PCIE_IMUX4_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT4" + "CLBLM_WL1END1", + "CLBLM_WL1END1" ], [ - "PCIE_IMUX18_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT18" + "CLBLM_WL1END2", + "CLBLM_WL1END2" ], [ - "PCIE_IMUX40_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT40" + "CLBLM_WL1END3", + "CLBLM_WL1END3" ], [ - "PCIE_EE2A2_19", - "INT_INTERFACE_EE2A2" + "CLBLM_WR1END0", + "CLBLM_WR1END0" ], [ - "PCIE_EE4B3_19", - "INT_INTERFACE_EE4B3" + "CLBLM_WR1END1", + "CLBLM_WR1END1" ], [ - "PCIE_SW2A0_19", - "INT_INTERFACE_SW2A0" + "CLBLM_WR1END2", + "CLBLM_WR1END2" ], [ - "PCIE_EE2BEG0_19", - "INT_INTERFACE_EE2BEG0" + "CLBLM_WR1END3", + "CLBLM_WR1END3" ], [ - "PCIE_SE2A1_19", - "INT_INTERFACE_SE2A1" + "CLBLM_WW2A0", + "CLBLM_WW2A0" ], [ - "PCIE_SE4BEG2_19", - "INT_INTERFACE_SE4BEG2" + "CLBLM_WW2A1", + "CLBLM_WW2A1" ], [ - "PCIE_WW4END1_19", - "INT_INTERFACE_WW4END1" + "CLBLM_WW2A2", + "CLBLM_WW2A2" ], [ - "PCIE_IMUX36_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT36" + "CLBLM_WW2A3", + "CLBLM_WW2A3" ], [ - "PCIE_WL1END1_19", - "INT_INTERFACE_WL1END1" + "CLBLM_WW2END0", + "CLBLM_WW2END0" ], [ - "PCIE_MONITOR_P_19", - "INT_INTERFACE_MONITOR_P" + "CLBLM_WW2END1", + "CLBLM_WW2END1" ], [ - "PCIE_NW4END0_19", - "INT_INTERFACE_NW4END0" + "CLBLM_WW2END2", + "CLBLM_WW2END2" ], [ - "PCIE_NE4BEG1_19", - "INT_INTERFACE_NE4BEG1" + "CLBLM_WW2END3", + "CLBLM_WW2END3" ], [ - "PCIE_WW4C0_19", - "INT_INTERFACE_WW4C0" + "CLBLM_WW4A0", + "CLBLM_WW4A0" ], [ - "PCIE_LH3_19", - "INT_INTERFACE_LH3" + "CLBLM_WW4A1", + "CLBLM_WW4A1" ], [ - "PCIE_LOGIC_OUTS_B18_R_19", - "INT_INTERFACE_LOGIC_OUTS_B18" + "CLBLM_WW4A2", + "CLBLM_WW4A2" ], [ - "PCIE_WW4A2_19", - "INT_INTERFACE_WW4A2" + "CLBLM_WW4A3", + "CLBLM_WW4A3" ], [ - "PCIE_IMUX24_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT24" + "CLBLM_WW4B0", + "CLBLM_WW4B0" ], [ - "PCIE_IMUX46_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT46" + "CLBLM_WW4B1", + "CLBLM_WW4B1" ], [ - "PCIE_SE2A0_19", - "INT_INTERFACE_SE2A0" + "CLBLM_WW4B2", + "CLBLM_WW4B2" ], [ - "PCIE_LH6_19", - "INT_INTERFACE_LH6" + "CLBLM_WW4B3", + "CLBLM_WW4B3" ], [ - "PCIE_LOGIC_OUTS_B5_R_19", - "INT_INTERFACE_LOGIC_OUTS_B5" + "CLBLM_WW4C0", + "CLBLM_WW4C0" ], [ - "PCIE_WW2A1_19", - "INT_INTERFACE_WW2A1" + "CLBLM_WW4C1", + "CLBLM_WW4C1" ], [ - "PCIE_NW4A0_19", - "INT_INTERFACE_NW4A0" + "CLBLM_WW4C2", + "CLBLM_WW4C2" ], [ - "PCIE_EE2BEG3_19", - "INT_INTERFACE_EE2BEG3" + "CLBLM_WW4C3", + "CLBLM_WW4C3" ], [ - "PCIE_IMUX0_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT0" + "CLBLM_WW4END0", + "CLBLM_WW4END0" ], [ - "PCIE_IMUX12_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT12" + "CLBLM_WW4END1", + "CLBLM_WW4END1" ], [ - "PCIE_LOGIC_OUTS_B14_R_19", - "INT_INTERFACE_LOGIC_OUTS_B14" + "CLBLM_WW4END2", + "CLBLM_WW4END2" ], [ - "PCIE_SW2A2_19", - "INT_INTERFACE_SW2A2" - ], - [ - "PCIE_EE4BEG3_19", - "INT_INTERFACE_EE4BEG3" - ], - [ - "PCIE_SE4BEG0_19", - "INT_INTERFACE_SE4BEG0" - ], - [ - "PCIE_NE4BEG0_19", - "INT_INTERFACE_NE4BEG0" - ], - [ - "PCIE_WR1END2_19", - "INT_INTERFACE_WR1END2" - ], - [ - "PCIE_WW2A3_19", - "INT_INTERFACE_WW2A3" - ], - [ - "PCIE_IMUX23_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT23" - ], - [ - "PCIE_EE4A3_19", - "INT_INTERFACE_EE4A3" - ], - [ - "PCIE_FAN1_R_19", - "INT_INTERFACE_FAN1" - ], - [ - "PCIE_LOGIC_OUTS_B23_R_19", - "INT_INTERFACE_LOGIC_OUTS_B23" - ], - [ - "PCIE_NE4BEG3_19", - "INT_INTERFACE_NE4BEG3" - ], - [ - "PCIE_LOGIC_OUTS_B17_R_19", - "INT_INTERFACE_LOGIC_OUTS_B17" - ], - [ - "PCIE_LOGIC_OUTS_B6_R_19", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "PCIE_EE4B0_19", - "INT_INTERFACE_EE4B0" - ], - [ - "PCIE_ER1BEG2_19", - "INT_INTERFACE_ER1BEG2" - ], - [ - "PCIE_EE4B2_19", - "INT_INTERFACE_EE4B2" - ], - [ - "PCIE_CTRL1_R_19", - "INT_INTERFACE_CTRL1" - ], - [ - "PCIE_WL1END0_19", - "INT_INTERFACE_WL1END0" - ], - [ - "PCIE_WW4END3_19", - "INT_INTERFACE_WW4END3" - ], - [ - "PCIE_LOGIC_OUTS_B4_R_19", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "PCIE_EE4C2_19", - "INT_INTERFACE_EE4C2" - ], - [ - "PCIE_LOGIC_OUTS_B22_R_19", - "INT_INTERFACE_LOGIC_OUTS_B22" - ], - [ - "PCIE_SW4END0_19", - "INT_INTERFACE_SW4END0" - ], - [ - "PCIE_IMUX21_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT21" - ], - [ - "PCIE_FAN2_R_19", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_SW2A3_19", - "INT_INTERFACE_SW2A3" - ], - [ - "PCIE_EE2BEG2_19", - "INT_INTERFACE_EE2BEG2" - ], - [ - "PCIE_EE4BEG0_19", - "INT_INTERFACE_EE4BEG0" - ], - [ - "PCIE_IMUX15_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT15" - ], - [ - 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"CMT_TOP_EE4B2_11", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_WW2A3_11", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_WW4A2_11", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_EE4BEG3_11", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_EE2A3_11", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_WW4C3_11", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_SE2A0_11", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_WL1END2_11", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_EE4C1_11", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_WW4C0_11", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_NE4C2_11", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_SE4C2_11", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_SW4A2_11", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_NE4BEG1_11", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_SE4BEG2_11", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_SW4A0_11", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_WL1END0_11", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_EE4B3_11", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_NW4A2_11", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_EE4A2_11", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_SE4BEG1_11", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_WW4C2_11", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_LH5_11", - "VBRK_LH5" - ], - [ - "CMT_TOP_NE2A0_11", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_NW2A1_11", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_NW4A1_11", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_NW4END3_11", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_EE2A1_11", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_WR1END0_11", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_SE2A2_11", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_NW4A0_11", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_EE4C2_11", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_SE4C3_11", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WR1END1_11", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_LH8_11", - "VBRK_LH8" - ], - [ - "CMT_TOP_NW4END1_11", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_NW2A3_11", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_EE4BEG0_11", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_SW2A0_11", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_EE2BEG0_11", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_SE4BEG0_11", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_SE4BEG3_11", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW2END2_11", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_NE2A1_11", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_EE4C3_11", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_WW4C1_11", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_WW2END0_11", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WR1END2_11", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_NE2A2_11", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_EE2BEG1_11", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_WW4A1_11", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_LH6_11", - "VBRK_LH6" - ], - [ - "CMT_TOP_WW2A0_11", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_NE4C0_11", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_NW4END0_11", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_EE4A3_11", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_LH4_11", - "VBRK_LH4" - ], - [ - "CMT_TOP_EE4BEG1_11", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_ER1BEG1_11", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EL1BEG2_11", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_NE4C1_11", - "VBRK_NE4C1" + "CLBLM_M_COUT_N", + "HCLK_CLB_COUT0_L" ] ] }, @@ -85813,17 +105757,17 @@ 1 ], "tile_types": [ - "CLBLL_R", - "CLBLL_R" + "CLBLM_L", + "HCLK_CLB" ], "wire_pairs": [ [ - "CLBLL_L_CIN", - "CLBLL_L_COUT_N" + "CLBLM_L_CIN", + "HCLK_CLB_COUT1_L" ], [ - "CLBLL_LL_CIN", - "CLBLL_LL_COUT_N" + "CLBLM_M_CIN", + "HCLK_CLB_COUT0_L" ] ] }, @@ -85833,17497 +105777,881 @@ 0 ], "tile_types": [ - "HCLK_L", - "HCLK_R" + "CLBLM_L", + "INT_L" ], "wire_pairs": [ - [ - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CK_INOUT_L5", - "HCLK_CK_OUTIN_R1" - ], - [ - "HCLK_CK_INOUT_L0", - "HCLK_CK_OUTIN_R4" - ], - [ - "HCLK_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_INT_PERFCLK1", - "HCLK_INT_PERFCLK1" - ], - [ - "HCLK_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CCIO0", - "HCLK_CCIO0" - ], - [ - "HCLK_CK_OUTIN_L2", - "HCLK_CK_INOUT_R2" - ], - [ - "HCLK_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK0" - ], - [ - "HCLK_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_CK_OUTIN_L4", - "HCLK_CK_INOUT_R4" - ], - [ - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_CK_OUTIN_L7", - "HCLK_CK_INOUT_R7" - ], - [ - "HCLK_CCIO2", - "HCLK_CCIO2" - ], - [ - "HCLK_CK_OUTIN_L6", - "HCLK_CK_INOUT_R6" - ], - [ - "HCLK_CK_OUTIN_L5", - "HCLK_CK_INOUT_R5" - ], - [ - "HCLK_INT_PERFCLK2", - "HCLK_INT_PERFCLK2" - ], - [ - "HCLK_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_CK_IN1", - "HCLK_CK_IN1" - ], - [ - "HCLK_CK_IN0", - "HCLK_CK_IN0" - ], - [ - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_CCIO3", - "HCLK_CCIO3" - ], - [ - "HCLK_CK_IN2", - "HCLK_CK_IN2" - ], - [ - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_CK_OUTIN_L0", - "HCLK_CK_INOUT_R0" - ], - [ - "HCLK_CK_INOUT_L2", - "HCLK_CK_OUTIN_R6" - ], - [ - "HCLK_CK_BUFRCLK3", - "HCLK_CK_BUFRCLK3" - ], - [ - "HCLK_CK_INOUT_L6", - "HCLK_CK_OUTIN_R2" - ], - [ - "HCLK_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CK_OUTIN_L3", - "HCLK_CK_INOUT_R3" - ], - [ - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CCIO1", - "HCLK_CCIO1" - ], - [ - "HCLK_CK_INOUT_L1", - "HCLK_CK_OUTIN_R5" - ], - [ - "HCLK_CK_IN3", - "HCLK_CK_IN3" - ], - [ - "HCLK_INT_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ], - [ - "HCLK_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK2" - ], - [ - "HCLK_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CK_INOUT_L4", - "HCLK_CK_OUTIN_R0" - ], - [ - "HCLK_CK_OUTIN_L1", - "HCLK_CK_INOUT_R1" - ], - [ - "HCLK_INT_PERFCLK3", - "HCLK_INT_PERFCLK3" - ], - [ - "HCLK_CK_INOUT_L3", - "HCLK_CK_OUTIN_R7" - ], - [ - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CK_INOUT_L7", - "HCLK_CK_OUTIN_R3" - ] - ] - }, - { - "grid_deltas": [ - -1, - -5 - ], - "tile_types": [ - "CFG_CENTER_MID", - "INT_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "CFG_CENTER_NE2A3_15", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_LH1_15", - "INT_FEEDTHRU_2_LH1" - ], - [ - "CFG_CENTER_WW4END2_15", - "INT_FEEDTHRU_2_WW4END2" - ], - [ - "CFG_CENTER_EE2BEG3_15", - "INT_FEEDTHRU_2_EE2BEG3" - ], - [ - "CFG_CENTER_NW2A1_15", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_NW4A1_15", - "INT_FEEDTHRU_2_NW4A1" - ], - [ - "CFG_CENTER_SE4BEG0_15", - "INT_FEEDTHRU_2_SE4BEG0" - ], - [ - "CFG_CENTER_EL1BEG0_15", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_EE2BEG2_15", - "INT_FEEDTHRU_2_EE2BEG2" - ], - [ - "CFG_CENTER_LH2_15", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_SE2A0_15", - "INT_FEEDTHRU_2_SE2A0" - ], - [ - "CFG_CENTER_EE4B1_15", - "INT_FEEDTHRU_2_EE4B1" - ], - [ - "CFG_CENTER_NW4A3_15", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_EE4A2_15", - "INT_FEEDTHRU_2_EE4A2" - ], - [ - "CFG_CENTER_ER1BEG2_15", - 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"VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_FAN3_5", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_CLK0_5", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_FAN2_5", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX4_5", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_FAN7_5", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX12_5", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX11_5", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_LOGIC_OUTS_B23_5", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_IMUX40_5", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_BYP3_5", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX16_5", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_FAN6_5", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX20_5", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX7_5", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX26_5", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX21_5", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_LOGIC_OUTS_B10_5", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_LOGIC_OUTS_B4_5", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_BYP0_5", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_BYP5_5", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX18_5", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX41_5", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_FAN1_5", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_BYP2_5", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX28_5", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX8_5", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX39_5", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX2_5", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_LOGIC_OUTS_B17_5", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_LOGIC_OUTS_B22_5", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX14_5", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX17_5", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX43_5", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX37_5", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX44_5", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX32_5", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B13_5", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX33_5", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_BYP1_5", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_LOGIC_OUTS_B2_5", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_FAN4_5", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX23_5", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX19_5", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX42_5", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX0_5", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B5_5", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_BYP7_5", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX1_5", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_BYP6_5", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX15_5", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX34_5", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_LOGIC_OUTS_B14_5", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_LOGIC_OUTS_B9_5", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_LOGIC_OUTS_B6_5", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX6_5", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_CTRL1_5", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX47_5", - "VBRK_EXT_IMUX47" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CLK_BUFG_REBUF_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "CLK_BUFG_REBUF_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "CLK_BUFG_REBUF_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CLK_BUFG_REBUF_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CLK_BUFG_REBUF_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CLK_BUFG_REBUF_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "CLK_BUFG_REBUF_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CLK_BUFG_REBUF_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "CLK_BUFG_REBUF_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "CLK_BUFG_REBUF_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CLK_BUFG_REBUF_LH5_0", - "VBRK_LH5" - ], - [ - "CLK_BUFG_REBUF_LH1_0", - "VBRK_LH1" - ], - [ - "CLK_BUFG_REBUF_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CLK_BUFG_REBUF_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CLK_BUFG_REBUF_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CLK_BUFG_REBUF_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "CLK_BUFG_REBUF_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CLK_BUFG_REBUF_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CLK_BUFG_REBUF_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "CLK_BUFG_REBUF_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "CLK_BUFG_REBUF_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "CLK_BUFG_REBUF_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CLK_BUFG_REBUF_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "CLK_BUFG_REBUF_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CLK_BUFG_REBUF_LH10_0", - "VBRK_LH10" - ], - [ - "CLK_BUFG_REBUF_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "CLK_BUFG_REBUF_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CLK_BUFG_REBUF_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "CLK_BUFG_REBUF_EE4A2_0", - "VBRK_EE4A2" - ], - [ - "CLK_BUFG_REBUF_LH12_0", - "VBRK_LH12" - ], - [ - "CLK_BUFG_REBUF_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CLK_BUFG_REBUF_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "CLK_BUFG_REBUF_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "CLK_BUFG_REBUF_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CLK_BUFG_REBUF_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CLK_BUFG_REBUF_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "CLK_BUFG_REBUF_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CLK_BUFG_REBUF_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "CLK_BUFG_REBUF_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CLK_BUFG_REBUF_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "CLK_BUFG_REBUF_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "CLK_BUFG_REBUF_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CLK_BUFG_REBUF_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CLK_BUFG_REBUF_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "CLK_BUFG_REBUF_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CLK_BUFG_REBUF_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "CLK_BUFG_REBUF_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CLK_BUFG_REBUF_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_BUFG_REBUF_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "CLK_BUFG_REBUF_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CLK_BUFG_REBUF_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CLK_BUFG_REBUF_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "CLK_BUFG_REBUF_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CLK_BUFG_REBUF_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CLK_BUFG_REBUF_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CLK_BUFG_REBUF_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_BUFG_REBUF_NW4A1_0", - "VBRK_NW4A1" - ], - [ - "CLK_BUFG_REBUF_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CLK_BUFG_REBUF_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "CLK_BUFG_REBUF_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CLK_BUFG_REBUF_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CLK_BUFG_REBUF_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "CLK_BUFG_REBUF_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "CLK_BUFG_REBUF_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CLK_BUFG_REBUF_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "CLK_BUFG_REBUF_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_BUFG_REBUF_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CLK_BUFG_REBUF_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "CLK_BUFG_REBUF_LH11_0", - "VBRK_LH11" - ], - [ - "CLK_BUFG_REBUF_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CLK_BUFG_REBUF_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CLK_BUFG_REBUF_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "CLK_BUFG_REBUF_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "CLK_BUFG_REBUF_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CLK_BUFG_REBUF_LH2_0", - "VBRK_LH2" - ], - [ - "CLK_BUFG_REBUF_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CLK_BUFG_REBUF_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CLK_BUFG_REBUF_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CLK_BUFG_REBUF_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CLK_BUFG_REBUF_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CLK_BUFG_REBUF_LH6_0", - "VBRK_LH6" - ], - [ - "CLK_BUFG_REBUF_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_BUFG_REBUF_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CLK_BUFG_REBUF_LH8_0", - "VBRK_LH8" - ], - [ - "CLK_BUFG_REBUF_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_BUFG_REBUF_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CLK_BUFG_REBUF_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CLK_BUFG_REBUF_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CLK_BUFG_REBUF_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "CLK_BUFG_REBUF_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "CLK_BUFG_REBUF_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "CLK_BUFG_REBUF_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CLK_BUFG_REBUF_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "CLK_BUFG_REBUF_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "CLK_BUFG_REBUF_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "CLK_BUFG_REBUF_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CLK_BUFG_REBUF_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CLK_BUFG_REBUF_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CLK_BUFG_REBUF_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_BUFG_REBUF_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_BUFG_REBUF_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CLK_BUFG_REBUF_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "CLK_BUFG_REBUF_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "CLK_BUFG_REBUF_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "CLK_BUFG_REBUF_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CLK_BUFG_REBUF_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "CLK_BUFG_REBUF_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CLK_BUFG_REBUF_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "CLK_BUFG_REBUF_LH7_0", - "VBRK_LH7" - ], - [ - "CLK_BUFG_REBUF_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "CLK_BUFG_REBUF_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CLK_BUFG_REBUF_LH9_0", - "VBRK_LH9" - ], - [ - "CLK_BUFG_REBUF_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "CLK_BUFG_REBUF_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "CLK_BUFG_REBUF_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CLK_BUFG_REBUF_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_BUFG_REBUF_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CLK_BUFG_REBUF_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "CLK_BUFG_REBUF_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "CLK_BUFG_REBUF_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CLK_BUFG_REBUF_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_BUFG_REBUF_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "CLK_BUFG_REBUF_EE4BEG2_0", - "VBRK_EE4BEG2" - ] - ] - }, - { - "grid_deltas": [ - 5, - 10 - ], - "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_L" - ], - "wire_pairs": [ - [ - "PCIE_IMUX44_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT44" - ], - [ - "PCIE_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "PCIE_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - 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"VBRK_EE4BEG0" - ], - [ - "CLBLM_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLBLM_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLBLM_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLBLM_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLBLM_LH4", - "VBRK_LH4" - ], - [ - "CLBLM_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLBLM_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLBLM_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLBLM_LH6", - "VBRK_LH6" - ], - [ - "CLBLM_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLBLM_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLBLM_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLBLM_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLBLM_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLBLM_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLBLM_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLBLM_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLBLM_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLBLM_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLBLM_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLBLM_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLBLM_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLBLM_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLBLM_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLBLM_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLBLM_LH7", - "VBRK_LH7" - ], - [ - "CLBLM_LH8", - "VBRK_LH8" + "CLBLM_MONITOR_P", + "MONITOR_P" ], [ "CLBLM_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLBLM_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLBLM_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLBLM_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLBLM_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLBLM_LH12", - "VBRK_LH12" - ], - [ - "CLBLM_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLBLM_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLBLM_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLBLM_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLBLM_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLBLM_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLBLM_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLBLM_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLBLM_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLBLM_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLBLM_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLBLM_LH1", - "VBRK_LH1" - ], - [ - "CLBLM_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLBLM_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLBLM_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLBLM_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLBLM_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLBLM_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLBLM_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLBLM_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLBLM_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLBLM_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLBLM_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLBLM_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLBLM_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLBLM_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLBLM_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLBLM_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLBLM_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLBLM_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLBLM_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLBLM_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLBLM_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLBLM_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLBLM_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLBLM_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLBLM_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLBLM_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLBLM_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLBLM_LH11", - "VBRK_LH11" - ], - [ - "CLBLM_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLBLM_WL1END0", - "VBRK_WL1END0" + "NE2END0" ], [ "CLBLM_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLBLM_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLBLM_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLBLM_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLBLM_LH5", - "VBRK_LH5" - ], - [ - "CLBLM_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLBLM_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLBLM_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLBLM_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLBLM_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLBLM_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLBLM_SW4A1", - "VBRK_SW4A1" + "NE2END1" ], [ "CLBLM_NE2A2", - "VBRK_NE2A2" + "NE2END2" + ], + [ + "CLBLM_NE2A3", + "NE2END3" + ], + [ + "CLBLM_NE4BEG0", + "NE6A0" + ], + [ + "CLBLM_NE4BEG1", + "NE6A1" + ], + [ + "CLBLM_NE4BEG2", + "NE6A2" + ], + [ + "CLBLM_NE4BEG3", + "NE6A3" + ], + [ + "CLBLM_NE4C0", + "NE6END0" + ], + [ + "CLBLM_NE4C1", + "NE6END1" + ], + [ + "CLBLM_NE4C2", + "NE6END2" + ], + [ + "CLBLM_NE4C3", + "NE6END3" + ], + [ + "CLBLM_NW2A0", + "NW2A0" + ], + [ + "CLBLM_NW2A1", + "NW2A1" + ], + [ + "CLBLM_NW2A2", + "NW2A2" + ], + [ + "CLBLM_NW2A3", + "NW2A3" + ], + [ + "CLBLM_NW4A0", + "NW6BEG0" + ], + [ + "CLBLM_NW4A1", + "NW6BEG1" + ], + [ + "CLBLM_NW4A2", + "NW6BEG2" + ], + [ + "CLBLM_NW4A3", + "NW6BEG3" + ], + [ + "CLBLM_NW4END0", + "NW6E0" + ], + [ + "CLBLM_NW4END1", + "NW6E1" + ], + [ + "CLBLM_NW4END2", + "NW6E2" + ], + [ + "CLBLM_NW4END3", + "NW6E3" + ], + [ + "CLBLM_SE2A0", + "SE2END0" + ], + [ + "CLBLM_SE2A1", + "SE2END1" + ], + [ + "CLBLM_SE2A2", + "SE2END2" + ], + [ + "CLBLM_SE2A3", + "SE2END3" + ], + [ + "CLBLM_SE4BEG0", + "SE6A0" + ], + [ + "CLBLM_SE4BEG1", + "SE6A1" + ], + [ + "CLBLM_SE4BEG2", + "SE6A2" + ], + [ + "CLBLM_SE4BEG3", + "SE6A3" + ], + [ + "CLBLM_SE4C0", + "SE6END0" + ], + [ + "CLBLM_SE4C1", + "SE6END1" + ], + [ + "CLBLM_SE4C2", + "SE6END2" + ], + [ + "CLBLM_SE4C3", + "SE6END3" + ], + [ + "CLBLM_SW2A0", + "SW2A0" + ], + [ + "CLBLM_SW2A1", + "SW2A1" + ], + [ + "CLBLM_SW2A2", + "SW2A2" + ], + [ + "CLBLM_SW2A3", + "SW2A3" + ], + [ + "CLBLM_SW4A0", + "SW6BEG0" + ], + [ + "CLBLM_SW4A1", + "SW6BEG1" + ], + [ + "CLBLM_SW4A2", + "SW6BEG2" + ], + [ + "CLBLM_SW4A3", + "SW6BEG3" + ], + [ + "CLBLM_SW4END0", + "SW6E0" + ], + [ + "CLBLM_SW4END1", + "SW6E1" + ], + [ + "CLBLM_SW4END2", + "SW6E2" + ], + [ + "CLBLM_SW4END3", + "SW6E3" + ], + [ + "CLBLM_WL1END0", + "WL1BEG0" + ], + [ + "CLBLM_WL1END1", + "WL1BEG1" + ], + [ + "CLBLM_WL1END2", + "WL1BEG2" + ], + [ + "CLBLM_WL1END3", + "WL1BEG3" + ], + [ + "CLBLM_WR1END0", + "WR1BEG0" + ], + [ + "CLBLM_WR1END1", + "WR1BEG1" + ], + [ + "CLBLM_WR1END2", + "WR1BEG2" + ], + [ + "CLBLM_WR1END3", + "WR1BEG3" + ], + [ + "CLBLM_WW2A0", + "WW2BEG0" + ], + [ + "CLBLM_WW2A1", + "WW2BEG1" + ], + [ + "CLBLM_WW2A2", + "WW2BEG2" + ], + [ + "CLBLM_WW2A3", + "WW2BEG3" + ], + [ + "CLBLM_WW2END0", + "WW2A0" + ], + [ + "CLBLM_WW2END1", + "WW2A1" + ], + [ + "CLBLM_WW2END2", + "WW2A2" + ], + [ + "CLBLM_WW2END3", + "WW2A3" + ], + [ + "CLBLM_WW4A0", + "WW4BEG0" + ], + [ + "CLBLM_WW4A1", + "WW4BEG1" + ], + [ + "CLBLM_WW4A2", + "WW4BEG2" ], [ "CLBLM_WW4A3", - "VBRK_WW4A3" + "WW4BEG3" ], [ - "CLBLM_LH9", - "VBRK_LH9" - ] - ] - }, - { - "grid_deltas": [ - 1, - 6 - ], - "tile_types": [ - "CFG_CENTER_MID", - "HCLK_VFRAME" - ], - "wire_pairs": [ - [ - "CFG_CENTER_CK_IN13", - "HCLK_VFRAME_CK_IN13" - ], - [ - "CFG_CENTER_CK_IN5", - "HCLK_VFRAME_CK_IN5" - ], - [ - "CFG_CENTER_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK4" - ], - [ - "CFG_CENTER_CK_BUFRCLK2", - "HCLK_VFRAME_CK_BUFRCLK2" - ], - [ - "CFG_CENTER_CK_BUFHCLK7", - "HCLK_VFRAME_CK_BUFHCLK7" - ], - [ - "CFG_CENTER_CK_BUFHCLK6", - "HCLK_VFRAME_CK_BUFHCLK6" - ], - [ - "CFG_CENTER_CK_BUFHCLK9", - "HCLK_VFRAME_CK_BUFHCLK9" - ], - [ - "CFG_CENTER_CK_BUFHCLK1", - "HCLK_VFRAME_CK_BUFHCLK1" - ], - [ - "CFG_CENTER_CK_BUFHCLK11", - "HCLK_VFRAME_CK_BUFHCLK11" - ], - [ - "CFG_CENTER_CK_IN7", - "HCLK_VFRAME_CK_IN7" - ], - [ - "CFG_CENTER_CK_IN3", - "HCLK_VFRAME_CK_IN3" - ], - [ - "CFG_CENTER_CK_IN6", - "HCLK_VFRAME_CK_IN6" - ], - [ - "CFG_CENTER_CK_IN1", - "HCLK_VFRAME_CK_IN1" - ], - [ - "CFG_CENTER_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFRCLK1" - ], - [ - "CFG_CENTER_CK_BUFRCLK0", - "HCLK_VFRAME_CK_BUFRCLK0" - ], - [ - "CFG_CENTER_CK_IN10", - "HCLK_VFRAME_CK_IN10" - ], - [ - "CFG_CENTER_CK_BUFHCLK5", - "HCLK_VFRAME_CK_BUFHCLK5" - ], - [ - "CFG_CENTER_CK_BUFHCLK3", - "HCLK_VFRAME_CK_BUFHCLK3" - ], - [ - "CFG_CENTER_CK_IN9", - "HCLK_VFRAME_CK_IN9" - ], - [ - "CFG_CENTER_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK8" - ], - [ - "CFG_CENTER_CK_IN2", - "HCLK_VFRAME_CK_IN2" - ], - [ - "CFG_CENTER_CK_BUFHCLK0", - "HCLK_VFRAME_CK_BUFHCLK0" - ], - [ - "CFG_CENTER_CK_IN8", - "HCLK_VFRAME_CK_IN8" - ], - [ - "CFG_CENTER_CK_IN12", - "HCLK_VFRAME_CK_IN12" - ], - [ - "CFG_CENTER_CK_BUFHCLK2", - "HCLK_VFRAME_CK_BUFHCLK2" - ], - [ - "CFG_CENTER_CK_BUFHCLK10", - "HCLK_VFRAME_CK_BUFHCLK10" - ], - [ - "CFG_CENTER_CK_IN11", - "HCLK_VFRAME_CK_IN11" - ], - [ - "CFG_CENTER_CK_BUFRCLK3", - "HCLK_VFRAME_CK_BUFRCLK3" - ], - [ - "CFG_CENTER_CK_IN4", - "HCLK_VFRAME_CK_IN4" - ], - [ - "CFG_CENTER_CK_IN0", - "HCLK_VFRAME_CK_IN0" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "CMT_TOP_L_LOWER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_SW2A2_10", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_NE2A2_10", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_NW2A2_10", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_EE2BEG3_10", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_SW4END3_10", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_EE4A0_10", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_WW4A2_10", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_WW4B1_10", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_SW4END1_10", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_LH8_10", - "VBRK_LH8" - ], - [ - "CMT_TOP_LH9_10", - "VBRK_LH9" - ], - [ - "CMT_TOP_WW4C1_10", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_LH10_10", - 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], - [ - "CMT_TOP_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WW4A3_1", - "VBRK_WW4A3" + "CLBLM_WW4B0", + "WW4A0" ], [ - "CMT_TOP_LH11_1", - "VBRK_LH11" + "CLBLM_WW4B1", + "WW4A1" ], [ - "CMT_TOP_LH5_1", - "VBRK_LH5" + "CLBLM_WW4B2", + "WW4A2" ], [ - "CMT_TOP_EE4BEG3_1", - "VBRK_EE4BEG3" + "CLBLM_WW4B3", + "WW4A3" ], [ - "CMT_TOP_EE2BEG3_1", - "VBRK_EE2BEG3" + "CLBLM_WW4C0", + "WW4B0" ], [ - "CMT_TOP_WL1END1_1", - "VBRK_WL1END1" + "CLBLM_WW4C1", + "WW4B1" ], [ - "CMT_TOP_EE4A0_1", - "VBRK_EE4A0" + "CLBLM_WW4C2", + "WW4B2" ], [ - "CMT_TOP_ER1BEG3_1", - "VBRK_ER1BEG3" + "CLBLM_WW4C3", + "WW4B3" ], [ - "CMT_TOP_NW4A2_1", - "VBRK_NW4A2" + "CLBLM_WW4END0", + "WW4C0" ], [ - "CMT_TOP_LH9_1", - "VBRK_LH9" + "CLBLM_WW4END1", + "WW4C1" ], [ - "CMT_TOP_EE4B1_1", - "VBRK_EE4B1" + "CLBLM_WW4END2", + "WW4C2" ], [ - "CMT_TOP_WW2END2_1", - "VBRK_WW2END2" + "CLBLM_WW4END3", + "WW4C3" ] ] }, @@ -103338,248 +106666,156 @@ ], "wire_pairs": [ [ - "CLBLM_ER1BEG3", - "VBRK_ER1BEG3" + "CLBLM_EE2A0", + "VBRK_EE2A0" ], [ - "CLBLM_WW4A2", - "VBRK_WW4A2" + "CLBLM_EE2A1", + "VBRK_EE2A1" ], [ - "CLBLM_WW4B3", - "VBRK_WW4B3" + "CLBLM_EE2A2", + "VBRK_EE2A2" ], [ - "CLBLM_WW4C2", - "VBRK_WW4C2" + "CLBLM_EE2A3", + "VBRK_EE2A3" ], [ - "CLBLM_LH10", - "VBRK_LH10" + "CLBLM_EE2BEG0", + "VBRK_EE2BEG0" ], [ - "CLBLM_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLBLM_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLBLM_LH2", - "VBRK_LH2" - ], - [ - "CLBLM_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLBLM_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLBLM_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLBLM_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLBLM_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLBLM_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLBLM_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLBLM_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLBLM_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLBLM_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLBLM_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLBLM_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLBLM_ER1BEG1", - "VBRK_ER1BEG1" + "CLBLM_EE2BEG1", + "VBRK_EE2BEG1" ], [ "CLBLM_EE2BEG2", "VBRK_EE2BEG2" ], [ - "CLBLM_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLBLM_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLBLM_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLBLM_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLBLM_EE4BEG2", - "VBRK_EE4BEG2" - ], - [ - "CLBLM_EE4B1", - "VBRK_EE4B1" - ], - [ - "CLBLM_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLBLM_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLBLM_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLBLM_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLBLM_LH3", - "VBRK_LH3" - ], - [ - "CLBLM_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLBLM_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLBLM_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLBLM_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLBLM_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLBLM_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLBLM_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLBLM_LH4", - "VBRK_LH4" - ], - [ - "CLBLM_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLBLM_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLBLM_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLBLM_LH6", - "VBRK_LH6" - ], - [ - "CLBLM_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLBLM_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLBLM_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLBLM_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLBLM_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLBLM_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLBLM_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLBLM_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLBLM_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLBLM_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLBLM_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLBLM_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLBLM_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLBLM_WW4A0", - "VBRK_WW4A0" + "CLBLM_EE2BEG3", + "VBRK_EE2BEG3" ], [ "CLBLM_EE4A0", "VBRK_EE4A0" ], [ - "CLBLM_WL1END1", - "VBRK_WL1END1" + "CLBLM_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLBLM_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLBLM_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLBLM_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLBLM_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLBLM_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLBLM_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLBLM_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLBLM_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLBLM_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLBLM_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLBLM_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLBLM_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLBLM_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLBLM_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLBLM_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLBLM_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLBLM_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLBLM_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLBLM_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLBLM_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLBLM_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLBLM_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLBLM_LH1", + "VBRK_LH1" + ], + [ + "CLBLM_LH2", + "VBRK_LH2" + ], + [ + "CLBLM_LH3", + "VBRK_LH3" + ], + [ + "CLBLM_LH4", + "VBRK_LH4" + ], + [ + "CLBLM_LH5", + "VBRK_LH5" + ], + [ + "CLBLM_LH6", + "VBRK_LH6" ], [ "CLBLM_LH7", @@ -103590,11668 +106826,368 @@ "VBRK_LH8" ], [ - "CLBLM_NE2A0", - "VBRK_NE2A0" + "CLBLM_LH9", + "VBRK_LH9" ], [ - "CLBLM_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLBLM_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLBLM_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLBLM_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLBLM_LH12", - "VBRK_LH12" - ], - [ - "CLBLM_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLBLM_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLBLM_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLBLM_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLBLM_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLBLM_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLBLM_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLBLM_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLBLM_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLBLM_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLBLM_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLBLM_LH1", - "VBRK_LH1" - ], - [ - "CLBLM_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLBLM_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLBLM_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLBLM_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLBLM_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLBLM_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLBLM_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLBLM_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLBLM_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLBLM_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLBLM_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLBLM_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLBLM_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLBLM_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLBLM_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLBLM_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLBLM_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLBLM_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLBLM_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLBLM_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLBLM_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLBLM_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLBLM_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLBLM_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLBLM_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLBLM_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLBLM_WL1END3", - "VBRK_WL1END3" + "CLBLM_LH10", + "VBRK_LH10" ], [ "CLBLM_LH11", "VBRK_LH11" ], [ - "CLBLM_SW4A3", - "VBRK_SW4A3" + "CLBLM_LH12", + "VBRK_LH12" ], [ - "CLBLM_WL1END0", - "VBRK_WL1END0" + "CLBLM_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "CLBLM_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "CLBLM_NE2A0", + "VBRK_NE2A0" ], [ "CLBLM_NE2A1", "VBRK_NE2A1" ], [ - "CLBLM_WR1END3", - "VBRK_WR1END3" + "CLBLM_NE2A2", + "VBRK_NE2A2" ], [ - "CLBLM_WW4B1", - "VBRK_WW4B1" + "CLBLM_NE2A3", + "VBRK_NE2A3" ], [ - "CLBLM_NW4END0", - "VBRK_NW4END0" + "CLBLM_NE4BEG0", + "VBRK_NE4BEG0" ], [ - "CLBLM_LH5", - "VBRK_LH5" + "CLBLM_NE4BEG1", + "VBRK_NE4BEG1" ], [ - "CLBLM_WR1END0", - "VBRK_WR1END0" + "CLBLM_NE4BEG2", + "VBRK_NE4BEG2" ], [ - "CLBLM_NW2A0", - "VBRK_NW2A0" + "CLBLM_NE4BEG3", + "VBRK_NE4BEG3" ], [ - "CLBLM_EE4BEG1", - "VBRK_EE4BEG1" + "CLBLM_NE4C0", + "VBRK_NE4C0" ], [ - "CLBLM_NW2A2", - "VBRK_NW2A2" + "CLBLM_NE4C1", + "VBRK_NE4C1" ], [ "CLBLM_NE4C2", "VBRK_NE4C2" ], + [ + "CLBLM_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLBLM_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLBLM_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLBLM_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLBLM_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLBLM_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLBLM_NW4A1", + "VBRK_NW4A1" + ], + [ + "CLBLM_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLBLM_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLBLM_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLBLM_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLBLM_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLBLM_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLBLM_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLBLM_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLBLM_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLBLM_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLBLM_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLBLM_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLBLM_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLBLM_SE4BEG3", + "VBRK_SE4BEG3" + ], [ "CLBLM_SE4C0", "VBRK_SE4C0" ], + [ + "CLBLM_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLBLM_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLBLM_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLBLM_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLBLM_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLBLM_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLBLM_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLBLM_SW4A0", + "VBRK_SW4A0" + ], [ "CLBLM_SW4A1", "VBRK_SW4A1" ], [ - "CLBLM_NE2A2", - "VBRK_NE2A2" + "CLBLM_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLBLM_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLBLM_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLBLM_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLBLM_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLBLM_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLBLM_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLBLM_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLBLM_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLBLM_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLBLM_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLBLM_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLBLM_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLBLM_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLBLM_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLBLM_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLBLM_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLBLM_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLBLM_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLBLM_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLBLM_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLBLM_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLBLM_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLBLM_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLBLM_WW4A2", + "VBRK_WW4A2" ], [ "CLBLM_WW4A3", "VBRK_WW4A3" ], [ - "CLBLM_LH9", - "VBRK_LH9" + "CLBLM_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLBLM_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLBLM_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLBLM_WW4B3", + "VBRK_WW4B3" + ], + [ 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"LIOI_DCI_T_TERM0" - ], - [ - "IOB_KEEPER_INT_EN_1", - "LIOI_KEEPER_INT_EN_1" - ], - [ - "IOB_O1", - "LIOI_O1" - ], - [ - "LIOB_IN_TERM1", - "LIOI_DCI_T_TERM1" - ], - [ - "IOB_IBUF_DISABLE0", - "LIOI_IBUF_DISABLE0" - ], - [ - "IOB_PU_INT_EN_0", - "LIOI_PU_INT_EN_0" - ], - [ - "IOB_IBUF1", - "LIOI_IBUF1" - ], - [ - "LIOB_MONITOR_N", - "IOI_MONITOR_N" - ], - [ - "IOB_PU_INT_EN_1", - "LIOI_PU_INT_EN_1" - ], - [ - "IOB_KEEPER_INT_EN_0", - "LIOI_KEEPER_INT_EN_0" - ], - [ - "IOB_O0", - "LIOI_O0" - ], - [ - "LIOB_MONITOR_P", - "IOI_MONITOR_P" - ], - [ - "IOB_T0", - "LIOI_T0" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "BRAM_INT_INTERFACE_L", - "INT_L" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_EE4B0", - "EE4C0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L3", - "LOGIC_OUTS_L3" - ], - [ - "INT_INTERFACE_NE2A3", - "NE2END3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L5", - "LOGIC_OUTS_L5" - ], - [ - "INT_INTERFACE_EE4A1", - "EE4B1" - ], - [ - "INT_INTERFACE_BYP2", - "BYP_L2" - ], - [ - "INT_INTERFACE_EE2A2", - "EE2END2" - ], - [ - "INT_INTERFACE_EE4BEG3", - "EE4A3" - ], - [ - "INT_INTERFACE_EE4A0", - "EE4B0" - ], - [ - "INT_INTERFACE_WW4B3", - "WW4A3" - ], - [ - "INT_INTERFACE_EE2A0", - "EE2END0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L2", - "LOGIC_OUTS_L2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L19", - "LOGIC_OUTS_L19" - ], - [ - "INT_INTERFACE_BRAM_IMUX26", - "IMUX_L26" - ], - [ - "INT_INTERFACE_WR1END1", - "WR1BEG1" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "IMUX_L32" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L1", - "LOGIC_OUTS_L1" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "IMUX_L38" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "IMUX_L8" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "IMUX_L41" - ], - [ - "INT_INTERFACE_SW2A2", - "SW2A2" - ], - [ - "INT_INTERFACE_SW4END2", - "SW6E2" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "IMUX_L1" - ], - [ - "INT_INTERFACE_NW4A2", - "NW6BEG2" - ], - [ - "INT_INTERFACE_BYP4", - "BYP_L4" - ], - [ - "INT_INTERFACE_BRAM_IMUX19", - "IMUX_L19" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "IMUX_L5" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "IMUX_L21" - ], - [ - "INT_INTERFACE_LH6", - "LH5" - ], - [ - "INT_INTERFACE_BRAM_IMUX42", - "IMUX_L42" - ], - [ - "INT_INTERFACE_WL1END0", - "WL1BEG0" - ], - [ - "INT_INTERFACE_SW2A3", - "SW2A3" - ], - [ - "INT_INTERFACE_WW4END0", - "WW4C0" - ], - [ - "INT_INTERFACE_BRAM_IMUX27", - "IMUX_L27" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L10", - "LOGIC_OUTS_L10" - ], - [ - "INT_INTERFACE_SE4BEG2", - "SE6A2" - ], - [ - "INT_INTERFACE_WW4A2", - "WW4BEG2" - ], - [ - "INT_INTERFACE_NE4BEG3", - "NE6A3" - ], - [ - "INT_INTERFACE_BRAM_IMUX16", - "IMUX_L16" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "IMUX_L15" - ], - [ - "INT_INTERFACE_NE4BEG1", - "NE6A1" - ], - [ - "INT_INTERFACE_BRAM_IMUX22", - "IMUX_L22" - ], - [ - "INT_INTERFACE_EE4C3", - "EE4END3" - ], - [ - "INT_INTERFACE_BRAM_IMUX35", - "IMUX_L35" - ], - [ - "INT_INTERFACE_BYP5", - "BYP_L5" - ], - [ - "INT_INTERFACE_SW4A1", - "SW6BEG1" - ], - [ - "INT_INTERFACE_WR1END3", - "WR1BEG3" - ], - [ - "INT_INTERFACE_WW2END0", - "WW2A0" - ], - [ - "INT_INTERFACE_NW2A2", - "NW2A2" - ], - [ - "INT_INTERFACE_ER1BEG3", - "ER1END3" - ], - [ - "INT_INTERFACE_SW4END3", - "SW6E3" - ], - [ - "INT_INTERFACE_SE2A0", - "SE2END0" - ], - [ - "INT_INTERFACE_WW2END3", - "WW2A3" - ], - [ - "INT_INTERFACE_SE4C1", - "SE6END1" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "IMUX_L6" - ], - [ - "INT_INTERFACE_LH7", - "LH6" - ], - [ - "INT_INTERFACE_WW2A1", - "WW2BEG1" - ], - [ - "INT_INTERFACE_FAN5", - "FAN_L5" - ], - [ - "INT_INTERFACE_LH8", - "LH7" - ], - [ - "INT_INTERFACE_BRAM_IMUX11", - "IMUX_L11" - ], - [ - "INT_INTERFACE_CTRL0", - "CTRL_L0" - ], - [ - "INT_INTERFACE_BRAM_IMUX30", - "IMUX_L30" - ], - [ - "INT_INTERFACE_EE4C1", - "EE4END1" - ], - [ - "INT_INTERFACE_NW4A1", - "NW6BEG1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L20", - "LOGIC_OUTS_L20" - ], - [ - "INT_INTERFACE_WL1END1", - "WL1BEG1" - ], - [ - "INT_INTERFACE_SE4C3", - "SE6END3" - ], - [ - "INT_INTERFACE_EE4B2", - "EE4C2" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - "IMUX_L47" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L9", - "LOGIC_OUTS_L9" - ], - [ - "INT_INTERFACE_EE2A1", - "EE2END1" - ], - [ - "INT_INTERFACE_WW2A2", - "WW2BEG2" - ], - [ - "INT_INTERFACE_NW2A1", - "NW2A1" - ], - [ - "INT_INTERFACE_NW4END3", - "NW6E3" - ], - [ - "INT_INTERFACE_EE4BEG2", - "EE4A2" - ], - [ - "INT_INTERFACE_BRAM_IMUX23", - "IMUX_L23" - ], - [ - "INT_INTERFACE_NW4END0", - "NW6E0" - ], - [ - "INT_INTERFACE_BRAM_IMUX10", - "IMUX_L10" - ], - [ - "INT_INTERFACE_EE4C2", - "EE4END2" - ], - [ - "INT_INTERFACE_WW2END2", - "WW2A2" - ], - [ - "INT_INTERFACE_SE2A2", - "SE2END2" - ], - [ - "INT_INTERFACE_BRAM_IMUX34", - "IMUX_L34" - ], - [ - "INT_INTERFACE_FAN3", - "FAN_L3" - ], - [ - "INT_INTERFACE_SW4A2", - "SW6BEG2" - ], - [ - "INT_INTERFACE_BYP0", - "BYP_L0" - ], - [ - "INT_INTERFACE_MONITOR_N", - "MONITOR_N" - ], - [ - "INT_INTERFACE_EE4BEG1", - "EE4A1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L4", - "LOGIC_OUTS_L4" - ], - [ - "INT_INTERFACE_EE2BEG2", - "EE2A2" - ], - [ - "INT_INTERFACE_LH9", - "LH8" - ], - [ - "INT_INTERFACE_BRAM_IMUX43", - "IMUX_L43" - ], - [ - "INT_INTERFACE_SE4BEG3", - "SE6A3" - ], - [ - "INT_INTERFACE_EE2BEG3", - "EE2A3" - ], - [ - "INT_INTERFACE_BRAM_IMUX33", - "IMUX_L33" - ], - [ - "INT_INTERFACE_EE2BEG0", - "EE2A0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L0", - "LOGIC_OUTS_L0" - ], - [ - "INT_INTERFACE_BYP7", - "BYP_L7" - ], - [ - "INT_INTERFACE_LH12", - "LH11" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L8", - "LOGIC_OUTS_L8" - ], - [ - "INT_INTERFACE_WR1END2", - "WR1BEG2" - ], - [ - "INT_INTERFACE_NW4A3", - "NW6BEG3" - ], - [ - "INT_INTERFACE_NE2A1", - "NE2END1" - ], - [ - "INT_INTERFACE_LH11", - "LH10" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L16", - "LOGIC_OUTS_L16" - ], - [ - "INT_INTERFACE_BRAM_IMUX45", - "IMUX_L45" - ], - [ - "INT_INTERFACE_LH3", - "LH2" - ], - [ - "INT_INTERFACE_NE2A2", - "NE2END2" - ], - [ - "INT_INTERFACE_NE4BEG0", - "NE6A0" - ], - [ - "INT_INTERFACE_WW4C0", - "WW4B0" - ], - [ - "INT_INTERFACE_LH1", - "LH0" - ], - [ - "INT_INTERFACE_FAN4", - "FAN_L4" - ], - [ - "INT_INTERFACE_SW4A0", - "SW6BEG0" - ], - [ - "INT_INTERFACE_SW2A1", - "SW2A1" - ], - [ - "INT_INTERFACE_BRAM_IMUX39", - "IMUX_L39" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L13", - "LOGIC_OUTS_L13" - ], - [ - "INT_INTERFACE_EE4A3", - "EE4B3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L11", - "LOGIC_OUTS_L11" - ], - [ - "INT_INTERFACE_WW4B0", - "WW4A0" - ], - [ - "INT_INTERFACE_WW4END2", - "WW4C2" - ], - [ - "INT_INTERFACE_NE2A0", - "NE2END0" - ], - [ - "INT_INTERFACE_SE4C0", - "SE6END0" - ], - [ - "INT_INTERFACE_FAN7", - "FAN_L7" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L7", - "LOGIC_OUTS_L7" - ], - [ - "INT_INTERFACE_SW4END1", - "SW6E1" - ], - [ - "INT_INTERFACE_EE4C0", - "EE4END0" - ], - [ - "INT_INTERFACE_EL1BEG2", - "EL1END2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L12", - "LOGIC_OUTS_L12" - ], - [ - "INT_INTERFACE_EE4BEG0", - "EE4A0" - ], - [ - "INT_INTERFACE_EL1BEG1", - "EL1END1" - ], - [ - "INT_INTERFACE_ER1BEG0", - "ER1END0" - ], - [ - "INT_INTERFACE_EE2BEG1", - "EE2A1" - ], - [ - "INT_INTERFACE_SE2A3", - "SE2END3" - ], - [ - "INT_INTERFACE_WL1END3", - "WL1BEG3" - ], - [ - "INT_INTERFACE_BRAM_IMUX18", - "IMUX_L18" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "IMUX_L25" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "IMUX_L14" - ], - [ - "INT_INTERFACE_ER1BEG2", - "ER1END2" - ], - [ - "INT_INTERFACE_CTRL1", - "CTRL_L1" - ], - [ - "INT_INTERFACE_NE4C2", - "NE6END2" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "IMUX_L37" - ], - [ - "INT_INTERFACE_BRAM_IMUX20", - "IMUX_L20" - ], - [ - "INT_INTERFACE_NW4END2", - "NW6E2" - ], - [ - "INT_INTERFACE_WW4A3", - "WW4BEG3" - ], - [ - "INT_INTERFACE_CLK1", - "CLK_L1" - ], - [ - "INT_INTERFACE_EE4A2", - "EE4B2" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "IMUX_L12" - ], - [ - "INT_INTERFACE_FAN6", - "FAN_L6" - ], - [ - "INT_INTERFACE_SE2A1", - "SE2END1" - ], - [ - "INT_INTERFACE_BRAM_IMUX36", - "IMUX_L36" - ], - [ - "INT_INTERFACE_MONITOR_P", - "MONITOR_P" - ], - [ - "INT_INTERFACE_BYP3", - "BYP_L3" - ], - [ - "INT_INTERFACE_EL1BEG3", - "EL1END3" - ], - [ - "INT_INTERFACE_ER1BEG1", - "ER1END1" - ], - [ - "INT_INTERFACE_BRAM_IMUX40", - "IMUX_L40" - ], - [ - "INT_INTERFACE_WW4A1", - "WW4BEG1" - ], - [ - "INT_INTERFACE_WL1END2", - "WL1BEG2" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "IMUX_L31" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L21", - "LOGIC_OUTS_L21" - ], - [ - "INT_INTERFACE_FAN0", - "FAN_L0" - ], - [ - "INT_INTERFACE_NE4C1", - "NE6END1" - ], - [ - "INT_INTERFACE_WW4END3", - "WW4C3" - ], - [ - "INT_INTERFACE_SW2A0", - "SW2A0" - ], - [ - "INT_INTERFACE_EE2A3", - "EE2END3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L6", - "LOGIC_OUTS_L6" - ], - [ - "INT_INTERFACE_WW4C3", - "WW4B3" - ], - [ - "INT_INTERFACE_NW2A0", - "NW2A0" - ], - [ - "INT_INTERFACE_NW2A3", - "NW2A3" - ], - [ - "INT_INTERFACE_FAN1", - "FAN_L1" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "IMUX_L4" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "IMUX_L17" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "IMUX_L28" - ], - [ - "INT_INTERFACE_FAN2", - "FAN_L2" - ], - [ - "INT_INTERFACE_BRAM_IMUX24", - "IMUX_L24" - ], - [ - "INT_INTERFACE_WW4END1", - "WW4C1" - ], - [ - "INT_INTERFACE_LH10", - "LH9" - ], - [ - "INT_INTERFACE_SE4BEG1", - "SE6A1" - ], - [ - "INT_INTERFACE_WW4A0", - "WW4BEG0" - ], - [ - "INT_INTERFACE_WR1END0", - "WR1BEG0" - ], - [ - "INT_INTERFACE_EL1BEG0", - "EL1END0" - ], - [ - "INT_INTERFACE_SW4END0", - "SW6E0" - ], - [ - "INT_INTERFACE_CLK0", - "CLK_L0" - ], - [ - "INT_INTERFACE_WW4B2", - "WW4A2" - ], - [ - "INT_INTERFACE_LH5", - "LH4" - ], - [ - "INT_INTERFACE_BYP6", - "BYP_L6" - ], - [ - "INT_INTERFACE_BRAM_IMUX0", - "IMUX_L0" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "IMUX_L3" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "IMUX_L44" - ], - [ - "INT_INTERFACE_EE4B1", - "EE4C1" - ], - [ - "INT_INTERFACE_WW2A3", - "WW2BEG3" - ], - [ - "INT_INTERFACE_LH4", - "LH3" - ], - [ - "INT_INTERFACE_NE4BEG2", - "NE6A2" - ], - [ - "INT_INTERFACE_BRAM_IMUX7", - "IMUX_L7" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L18", - "LOGIC_OUTS_L18" - ], - [ - "INT_INTERFACE_WW2A0", - "WW2BEG0" - ], - [ - "INT_INTERFACE_WW2END1", - "WW2A1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L17", - "LOGIC_OUTS_L17" - ], - [ - "INT_INTERFACE_NE4C0", - "NE6END0" - ], - [ - "INT_INTERFACE_LH2", - "LH1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L23", - "LOGIC_OUTS_L23" - ], - [ - "INT_INTERFACE_BRAM_IMUX13", - "IMUX_L13" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L15", - "LOGIC_OUTS_L15" - ], - [ - "INT_INTERFACE_SW4A3", - "SW6BEG3" - ], - [ - "INT_INTERFACE_BRAM_IMUX9", - "IMUX_L9" - ], - [ - "INT_INTERFACE_WW4C2", - "WW4B2" - ], - [ - "INT_INTERFACE_NE4C3", - "NE6END3" - ], - [ - "INT_INTERFACE_SE4C2", - "SE6END2" - ], - [ - "INT_INTERFACE_BYP1", - "BYP_L1" - ], - [ - "INT_INTERFACE_WW4B1", - "WW4A1" - ], - [ - "INT_INTERFACE_NW4A0", - "NW6BEG0" - ], - [ - "INT_INTERFACE_BRAM_IMUX29", - "IMUX_L29" - ], - [ - "INT_INTERFACE_NW4END1", - "NW6E1" - ], - [ - "INT_INTERFACE_SE4BEG0", - "SE6A0" - ], - [ - "INT_INTERFACE_WW4C1", - "WW4B1" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "IMUX_L46" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L14", - "LOGIC_OUTS_L14" - ], - [ - "INT_INTERFACE_EE4B3", - "EE4C3" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "IMUX_L2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L22", - "LOGIC_OUTS_L22" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_INT_INTERFACE", - "HCLK_L" - ], - "wire_pairs": [ - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_CK_BUFRCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_IN2", - "HCLK_CK_IN2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN1", - "HCLK_CK_IN1" - ], - [ - "HCLK_INT_INTERFACE_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_CK_IN0", - "HCLK_CK_IN0" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_INT_PERFCLK3" - ], - [ - "HCLK_INT_INTERFACE_CCIO0", - "HCLK_CCIO0" - ], - [ - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_CCIO2" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_INT_PERFCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_CCIO1" - ], - [ - "HCLK_INT_INTERFACE_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_INT_INTERFACE_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_INT_INTERFACE_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_INT_INTERFACE_CK_IN3", - "HCLK_CK_IN3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_INT_PERFCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK0" - ], - [ - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_CCIO3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_INT_INTERFACE_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_INT_INTERFACE_CK_IN5", - "HCLK_CK_IN5" + "CLBLM_M_CIN", + "CLBLM_M_COUT_N" ] ] }, @@ -115261,137 +107197,16645 @@ -1 ], "tile_types": [ - "BRKH_CLK", - "CLK_BUFG_TOP_R" + "CLBLM_R", + "HCLK_CLB" ], "wire_pairs": [ [ - "BRKH_CLK_R_CK_GCLK8", - "CLK_BUFG_CK_GCLK8" + "CLBLM_L_COUT_N", + "HCLK_CLB_COUT0_R" ], [ - "BRKH_CLK_R_CK_GCLK22", - "CLK_BUFG_CK_GCLK22" + "CLBLM_M_COUT_N", + "HCLK_CLB_COUT1_R" + ] + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "tile_types": [ + "CLBLM_R", + "HCLK_CLB" + ], + "wire_pairs": [ + [ + "CLBLM_L_CIN", + "HCLK_CLB_COUT0_R" ], [ - "BRKH_CLK_R_CK_GCLK23", - "CLK_BUFG_CK_GCLK23" + "CLBLM_M_CIN", + "HCLK_CLB_COUT1_R" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "CLBLM_R", + "INT_R" + ], + "wire_pairs": [ + [ + "CLBLM_BYP0", + "BYP0" ], [ - "BRKH_CLK_R_CK_GCLK2", - "CLK_BUFG_CK_GCLK2" + "CLBLM_BYP1", + "BYP1" ], [ - "BRKH_CLK_R_CK_GCLK11", - "CLK_BUFG_CK_GCLK11" + "CLBLM_BYP2", + "BYP2" ], [ - "BRKH_CLK_R_CK_GCLK31", - "CLK_BUFG_CK_GCLK31" + "CLBLM_BYP3", + "BYP3" ], [ - "BRKH_CLK_R_CK_GCLK24", - "CLK_BUFG_CK_GCLK24" + "CLBLM_BYP4", + "BYP4" ], [ - "BRKH_CLK_R_CK_GCLK15", - "CLK_BUFG_CK_GCLK15" + "CLBLM_BYP5", + "BYP5" ], [ - "BRKH_CLK_R_CK_GCLK13", - "CLK_BUFG_CK_GCLK13" + "CLBLM_BYP6", + "BYP6" ], [ - "BRKH_CLK_R_CK_GCLK30", - "CLK_BUFG_CK_GCLK30" + "CLBLM_BYP7", + "BYP7" ], [ - "BRKH_CLK_R_CK_GCLK25", - "CLK_BUFG_CK_GCLK25" + "CLBLM_CLK0", + "CLK0" ], [ - "BRKH_CLK_R_CK_GCLK27", - "CLK_BUFG_CK_GCLK27" + "CLBLM_CLK1", + "CLK1" ], [ - "BRKH_CLK_R_CK_GCLK0", - "CLK_BUFG_CK_GCLK0" + "CLBLM_CTRL0", + "CTRL0" ], [ - "BRKH_CLK_R_CK_GCLK28", - "CLK_BUFG_CK_GCLK28" + "CLBLM_CTRL1", + "CTRL1" ], [ - "BRKH_CLK_R_CK_GCLK26", - "CLK_BUFG_CK_GCLK26" + "CLBLM_EE2A0", + "EE2A0" ], [ - "BRKH_CLK_R_CK_GCLK18", - "CLK_BUFG_CK_GCLK18" + "CLBLM_EE2A1", + "EE2A1" ], [ - "BRKH_CLK_R_CK_GCLK12", - "CLK_BUFG_CK_GCLK12" + "CLBLM_EE2A2", + "EE2A2" ], [ - "BRKH_CLK_R_CK_GCLK7", - "CLK_BUFG_CK_GCLK7" + "CLBLM_EE2A3", + "EE2A3" ], [ - "BRKH_CLK_R_CK_GCLK3", - "CLK_BUFG_CK_GCLK3" + "CLBLM_EE2BEG0", + "EE2BEG0" ], [ - "BRKH_CLK_R_CK_GCLK4", - "CLK_BUFG_CK_GCLK4" + "CLBLM_EE2BEG1", + "EE2BEG1" ], [ - "BRKH_CLK_R_CK_GCLK1", - "CLK_BUFG_CK_GCLK1" + "CLBLM_EE2BEG2", + "EE2BEG2" ], [ - "BRKH_CLK_R_CK_GCLK9", - "CLK_BUFG_CK_GCLK9" + "CLBLM_EE2BEG3", + "EE2BEG3" ], [ - "BRKH_CLK_R_CK_GCLK20", - "CLK_BUFG_CK_GCLK20" + "CLBLM_EE4A0", + "EE4A0" ], [ - "BRKH_CLK_R_CK_GCLK21", - "CLK_BUFG_CK_GCLK21" + "CLBLM_EE4A1", + "EE4A1" ], [ - "BRKH_CLK_R_CK_GCLK17", - "CLK_BUFG_CK_GCLK17" + "CLBLM_EE4A2", + "EE4A2" ], [ - "BRKH_CLK_R_CK_GCLK6", - "CLK_BUFG_CK_GCLK6" + "CLBLM_EE4A3", + "EE4A3" ], [ - "BRKH_CLK_R_CK_GCLK5", - "CLK_BUFG_CK_GCLK5" + "CLBLM_EE4B0", + "EE4B0" ], [ - "BRKH_CLK_R_CK_GCLK10", - "CLK_BUFG_CK_GCLK10" + "CLBLM_EE4B1", + "EE4B1" ], [ - "BRKH_CLK_R_CK_GCLK16", - "CLK_BUFG_CK_GCLK16" + "CLBLM_EE4B2", + "EE4B2" ], [ - "BRKH_CLK_R_CK_GCLK19", - "CLK_BUFG_CK_GCLK19" + "CLBLM_EE4B3", + "EE4B3" ], [ - "BRKH_CLK_R_CK_GCLK29", - "CLK_BUFG_CK_GCLK29" + "CLBLM_EE4BEG0", + "EE4BEG0" ], [ - "BRKH_CLK_R_CK_GCLK14", - "CLK_BUFG_CK_GCLK14" + "CLBLM_EE4BEG1", + "EE4BEG1" + ], + [ + "CLBLM_EE4BEG2", + "EE4BEG2" + ], + [ + "CLBLM_EE4BEG3", + "EE4BEG3" + ], + [ + "CLBLM_EE4C0", + "EE4C0" + ], + [ + "CLBLM_EE4C1", + "EE4C1" + ], + [ + "CLBLM_EE4C2", + "EE4C2" + ], + [ + "CLBLM_EE4C3", + "EE4C3" + ], + [ + "CLBLM_EL1BEG0", + "EL1BEG0" + ], + [ + "CLBLM_EL1BEG1", + "EL1BEG1" + ], + [ + "CLBLM_EL1BEG2", + "EL1BEG2" + ], + [ + "CLBLM_EL1BEG3", + "EL1BEG3" + ], + [ + "CLBLM_ER1BEG0", + "ER1BEG0" + ], + [ + "CLBLM_ER1BEG1", + "ER1BEG1" + ], + [ + "CLBLM_ER1BEG2", + "ER1BEG2" + ], + [ + "CLBLM_ER1BEG3", + "ER1BEG3" + ], + [ + "CLBLM_FAN0", + "FAN0" + ], + [ + "CLBLM_FAN1", + "FAN1" + ], + [ + "CLBLM_FAN2", + "FAN2" + ], + [ + "CLBLM_FAN3", + "FAN3" + ], + [ + "CLBLM_FAN4", + "FAN4" + ], + [ + "CLBLM_FAN5", + "FAN5" + ], + [ + "CLBLM_FAN6", + "FAN6" + ], + [ + "CLBLM_FAN7", + "FAN7" + ], + [ + "CLBLM_IMUX0", + "IMUX0" + ], + [ + "CLBLM_IMUX1", + "IMUX1" + ], + [ + "CLBLM_IMUX2", + "IMUX2" + ], + [ + "CLBLM_IMUX3", + "IMUX3" + ], + [ + "CLBLM_IMUX4", + "IMUX4" + ], + [ + "CLBLM_IMUX5", + "IMUX5" + ], + [ + "CLBLM_IMUX6", + "IMUX6" + ], + [ + "CLBLM_IMUX7", + "IMUX7" + ], + [ + "CLBLM_IMUX8", + "IMUX8" + ], + [ + "CLBLM_IMUX9", + "IMUX9" + ], + [ + "CLBLM_IMUX10", + "IMUX10" + ], + [ + "CLBLM_IMUX11", + "IMUX11" + ], + [ + "CLBLM_IMUX12", + "IMUX12" + ], + [ + "CLBLM_IMUX13", + "IMUX13" + ], + [ + "CLBLM_IMUX14", + "IMUX14" + ], + [ + "CLBLM_IMUX15", + "IMUX15" + ], + [ + "CLBLM_IMUX16", + "IMUX16" + ], + [ + "CLBLM_IMUX17", + "IMUX17" + ], + [ + "CLBLM_IMUX18", + "IMUX18" + ], + [ + "CLBLM_IMUX19", + "IMUX19" + ], + [ + "CLBLM_IMUX20", + "IMUX20" + ], + [ + "CLBLM_IMUX21", + "IMUX21" + ], + [ + "CLBLM_IMUX22", + "IMUX22" + ], + [ + "CLBLM_IMUX23", + "IMUX23" + ], + [ + "CLBLM_IMUX24", + "IMUX24" + ], + [ + "CLBLM_IMUX25", + "IMUX25" + ], + [ + "CLBLM_IMUX26", + "IMUX26" + ], + [ + "CLBLM_IMUX27", + "IMUX27" + ], + [ + "CLBLM_IMUX28", + "IMUX28" + ], + [ + "CLBLM_IMUX29", + "IMUX29" + ], + [ + "CLBLM_IMUX30", + "IMUX30" + ], + [ + "CLBLM_IMUX31", + "IMUX31" + ], + [ + "CLBLM_IMUX32", + "IMUX32" + ], + [ + "CLBLM_IMUX33", + "IMUX33" + ], + [ + "CLBLM_IMUX34", + "IMUX34" + ], + [ + "CLBLM_IMUX35", + "IMUX35" + ], + [ + "CLBLM_IMUX36", + "IMUX36" + ], + [ + "CLBLM_IMUX37", + "IMUX37" + ], + [ + "CLBLM_IMUX38", + "IMUX38" + ], + [ + "CLBLM_IMUX39", + "IMUX39" + ], + [ + "CLBLM_IMUX40", + "IMUX40" + ], + [ + "CLBLM_IMUX41", + "IMUX41" + ], + [ + "CLBLM_IMUX42", + "IMUX42" + ], + [ + "CLBLM_IMUX43", + "IMUX43" + ], + [ + "CLBLM_IMUX44", + "IMUX44" + ], + [ + "CLBLM_IMUX45", + "IMUX45" + ], + [ + "CLBLM_IMUX46", + "IMUX46" + ], + [ + "CLBLM_IMUX47", + "IMUX47" + ], + [ + "CLBLM_LH1", + "LH1" + ], + [ + "CLBLM_LH2", + "LH2" + ], + [ + "CLBLM_LH3", + "LH3" + ], + [ + "CLBLM_LH4", + "LH4" + ], + [ + "CLBLM_LH5", + "LH5" + ], + [ + "CLBLM_LH6", + "LH6" + ], + [ + "CLBLM_LH7", + "LH7" + ], + [ + "CLBLM_LH8", + "LH8" + ], + [ + "CLBLM_LH9", + "LH9" + ], + [ + "CLBLM_LH10", + "LH10" + ], + [ + "CLBLM_LH11", + "LH11" + ], + [ + "CLBLM_LH12", + "LH12" + ], + [ + "CLBLM_LOGIC_OUTS0", + "LOGIC_OUTS0" + ], + [ + "CLBLM_LOGIC_OUTS1", + "LOGIC_OUTS1" + ], + [ + "CLBLM_LOGIC_OUTS2", + "LOGIC_OUTS2" + ], + [ + "CLBLM_LOGIC_OUTS3", + "LOGIC_OUTS3" + ], + [ + "CLBLM_LOGIC_OUTS4", + "LOGIC_OUTS4" + ], + [ + "CLBLM_LOGIC_OUTS5", + "LOGIC_OUTS5" + ], + [ + "CLBLM_LOGIC_OUTS6", + "LOGIC_OUTS6" + ], + [ + "CLBLM_LOGIC_OUTS7", + "LOGIC_OUTS7" + ], + [ + "CLBLM_LOGIC_OUTS8", + "LOGIC_OUTS8" + ], + [ + "CLBLM_LOGIC_OUTS9", + "LOGIC_OUTS9" + ], + [ + "CLBLM_LOGIC_OUTS10", + "LOGIC_OUTS10" + ], + [ + "CLBLM_LOGIC_OUTS11", + "LOGIC_OUTS11" + ], + [ + "CLBLM_LOGIC_OUTS12", + "LOGIC_OUTS12" + ], + [ + "CLBLM_LOGIC_OUTS13", + "LOGIC_OUTS13" + ], + [ + "CLBLM_LOGIC_OUTS14", + "LOGIC_OUTS14" + ], + [ + "CLBLM_LOGIC_OUTS15", + "LOGIC_OUTS15" + ], + [ + "CLBLM_LOGIC_OUTS16", + "LOGIC_OUTS16" + ], + [ + "CLBLM_LOGIC_OUTS17", + "LOGIC_OUTS17" + ], + [ + "CLBLM_LOGIC_OUTS18", + "LOGIC_OUTS18" + ], + [ + "CLBLM_LOGIC_OUTS19", + "LOGIC_OUTS19" + ], + [ + "CLBLM_LOGIC_OUTS20", + "LOGIC_OUTS20" + ], + [ + "CLBLM_LOGIC_OUTS21", + "LOGIC_OUTS21" + ], + [ + "CLBLM_LOGIC_OUTS22", + "LOGIC_OUTS22" + ], + [ + "CLBLM_LOGIC_OUTS23", + "LOGIC_OUTS23" + ], + [ + "CLBLM_MONITOR_N", + "MONITOR_N" + ], + [ + "CLBLM_MONITOR_P", + "MONITOR_P" + ], + [ + "CLBLM_NE2A0", + "NE2A0" + ], + [ + "CLBLM_NE2A1", + "NE2A1" + ], + [ + "CLBLM_NE2A2", + "NE2A2" + ], + [ + "CLBLM_NE2A3", + "NE2A3" + ], + [ + "CLBLM_NE4BEG0", + "NE6BEG0" + ], + [ + "CLBLM_NE4BEG1", + "NE6BEG1" + ], + [ + "CLBLM_NE4BEG2", + "NE6BEG2" + ], + [ + "CLBLM_NE4BEG3", + "NE6BEG3" + ], + [ + "CLBLM_NE4C0", + "NE6E0" + ], + [ + "CLBLM_NE4C1", + "NE6E1" + ], + [ + "CLBLM_NE4C2", + "NE6E2" + ], + [ + "CLBLM_NE4C3", + "NE6E3" + ], + [ + "CLBLM_NW2A0", + "NW2END0" + ], + [ + "CLBLM_NW2A1", + "NW2END1" + ], + [ + "CLBLM_NW2A2", + "NW2END2" + ], + [ + "CLBLM_NW2A3", + "NW2END3" + ], + [ + "CLBLM_NW4A0", + "NW6A0" + ], + [ + "CLBLM_NW4A1", + "NW6A1" + ], + [ + "CLBLM_NW4A2", + "NW6A2" + ], + [ + "CLBLM_NW4A3", + "NW6A3" + ], + [ + "CLBLM_NW4END0", + "NW6END0" + ], + [ + "CLBLM_NW4END1", + "NW6END1" + ], + [ + "CLBLM_NW4END2", + "NW6END2" + ], + [ + "CLBLM_NW4END3", + "NW6END3" + ], + [ + "CLBLM_SE2A0", + "SE2A0" + ], + [ + "CLBLM_SE2A1", + "SE2A1" + ], + [ + "CLBLM_SE2A2", + "SE2A2" + ], + [ + "CLBLM_SE2A3", + "SE2A3" + ], + [ + "CLBLM_SE4BEG0", + "SE6BEG0" + ], + [ + "CLBLM_SE4BEG1", + "SE6BEG1" + ], + [ + "CLBLM_SE4BEG2", + "SE6BEG2" + ], + [ + "CLBLM_SE4BEG3", + "SE6BEG3" + ], + [ + "CLBLM_SE4C0", + "SE6E0" + ], + [ + "CLBLM_SE4C1", + "SE6E1" + ], + [ + "CLBLM_SE4C2", + "SE6E2" + ], + [ + "CLBLM_SE4C3", + "SE6E3" + ], + [ + "CLBLM_SW2A0", + "SW2END0" + ], + [ + "CLBLM_SW2A1", + "SW2END1" + ], + [ + "CLBLM_SW2A2", + "SW2END2" + ], + [ + "CLBLM_SW2A3", + "SW2END3" + ], + [ + "CLBLM_SW4A0", + "SW6A0" + ], + [ + "CLBLM_SW4A1", + "SW6A1" + ], + [ + "CLBLM_SW4A2", + "SW6A2" + ], + [ + "CLBLM_SW4A3", + "SW6A3" + ], + [ + "CLBLM_SW4END0", + "SW6END0" + ], + [ + "CLBLM_SW4END1", + "SW6END1" + ], + [ + "CLBLM_SW4END2", + "SW6END2" + ], + [ + "CLBLM_SW4END3", + "SW6END3" + ], + [ + "CLBLM_WL1END0", + "WL1END0" + ], + [ + "CLBLM_WL1END1", + "WL1END1" + ], + [ + "CLBLM_WL1END2", + "WL1END2" + ], + [ + "CLBLM_WL1END3", + "WL1END3" + ], + [ + "CLBLM_WR1END0", + "WR1END0" + ], + [ + "CLBLM_WR1END1", + "WR1END1" + ], + [ + "CLBLM_WR1END2", + "WR1END2" + ], + [ + "CLBLM_WR1END3", + "WR1END3" + ], + [ + "CLBLM_WW2A0", + "WW2A0" + ], + [ + "CLBLM_WW2A1", + "WW2A1" + ], + [ + "CLBLM_WW2A2", + "WW2A2" + ], + [ + "CLBLM_WW2A3", + "WW2A3" + ], + [ + "CLBLM_WW2END0", + "WW2END0" + ], + [ + "CLBLM_WW2END1", + "WW2END1" + ], + [ + "CLBLM_WW2END2", + "WW2END2" + ], + [ + "CLBLM_WW2END3", + "WW2END3" + ], + [ + "CLBLM_WW4A0", + "WW4A0" + ], + [ + "CLBLM_WW4A1", + "WW4A1" + ], + [ + "CLBLM_WW4A2", + "WW4A2" + ], + [ + "CLBLM_WW4A3", + "WW4A3" + ], + [ + "CLBLM_WW4B0", + "WW4B0" + ], + [ + "CLBLM_WW4B1", + "WW4B1" + ], + [ + "CLBLM_WW4B2", + "WW4B2" + ], + [ + "CLBLM_WW4B3", + "WW4B3" + ], + [ + "CLBLM_WW4C0", + "WW4C0" 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"CLK_FEED_R_CK_BUFG_CASC3", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN21" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN31" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_HROW_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_HROW_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_HROW_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_HROW_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_HROW_R_CK_GCLK4" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_HROW_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_HROW_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_HROW_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_HROW_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_HROW_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_HROW_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_HROW_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_HROW_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_HROW_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_HROW_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_HROW_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_HROW_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_HROW_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_HROW_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_HROW_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_HROW_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_HROW_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_HROW_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_HROW_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_HROW_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_HROW_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_HROW_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_HROW_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_HROW_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_HROW_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_HROW_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_HROW_R_CK_GCLK31" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "CLK_FEED", + "CLK_MTBF2" + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" ] ] }, @@ -115405,17141 +123849,1905 @@ "CLK_PMV" ], "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_PMV_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_PMV_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_PMV_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_PMV_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_PMV_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_PMV_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_PMV_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_PMV_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_PMV_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_PMV_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_PMV_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_PMV_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_PMV_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_PMV_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_PMV_R_CK_GCLK19" - ], [ "CLK_FEED_R_CK_GCLK0", "CLK_PMV_R_CK_GCLK0" ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_PMV_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_PMV_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_PMV_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_PMV_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_PMV_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_PMV_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_PMV_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_PMV_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_PMV_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_PMV_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_PMV_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_PMV_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_PMV_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_PMV_R_CK_GCLK15" - ], [ "CLK_FEED_R_CK_GCLK1", "CLK_PMV_R_CK_GCLK1" ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_PMV_R_CK_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_PMV_R_CK_GCLK3" + ], [ "CLK_FEED_R_CK_GCLK4", "CLK_PMV_R_CK_GCLK4" - ] - ] - }, - { - "grid_deltas": [ - -1, - 1 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_WR1END2_3", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_SE4BEG1_3", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_WW4C1_3", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_EE2A1_3", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_WW2END2_3", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_EE4B2_3", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_IMUX9_3", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_NE2A2_3", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_SW2A1_3", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_SW4A3_3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX5_3", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_WW2A0_3", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_IMUX45_3", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SW4END2_3", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_SE2A3_3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_WW4B3_3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_IMUX41_3", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SE2A2_3", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE2A0_3", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4C0_3", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_NE2A3_3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_SE4C2_3", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_IMUX21_3", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX33_3", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX3_3", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_SW4A0_3", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_BYP1_3", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_FAN7_3", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_IMUX0_3", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_SW2A2_3", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_EE4A1_3", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NE2A1_3", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_IMUX40_3", - "INT_INTERFACE_IMUX40" - ], - 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- ], - [ - "CLK_HROW_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_EE4C3_3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_WL1END0_3", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_WW2A3_3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX8_3", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_CLK0_3", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW4C2_3", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_BYP7_3", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_BYP0_3", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_WW4A2_3", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NE2A0_3", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_SW4END0_3", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WL1END3_3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_IMUX18_3", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX30_3", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX38_3", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_SE2A1_3", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_SE4C3_3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_WW2END0_3", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_WW4END2_3", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_IMUX4_3", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_NE4BEG3_3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_IMUX37_3", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_WW4A1_3", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NW2A2_3", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_IMUX39_3", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_IMUX26_3", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_IMUX7_3", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_LH11_3", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_IMUX6_3", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_NW2A1_3", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE4B1_3", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EE4C1_3", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX10_3", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_EE4BEG0_3", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_FAN5_3", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_LH8_3", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_NE4C1_3", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_FAN3_3", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_SE4C1_3", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_WW4C0_3", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_WL1END1_3", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_NW4END3_3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_IMUX17_3", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX44_3", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_IMUX14_3", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_IMUX36_3", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW4END0_3", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_WW2A2_3", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_BYP3_3", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_IMUX1_3", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_IMUX22_3", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_WW2A1_3", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_NE4C3_3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_NW4END0_3", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WW4B2_3", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_WR1END0_3", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE4B0_3", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_EE2A3_3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_WW2END3_3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE4A0_3", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_IMUX19_3", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_SE4C0_3", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_LH7_3", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_SW4END1_3", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EE4B3_3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_BYP5_3", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_IMUX43_3", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_WR1END1_3", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_IMUX20_3", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_NE4C2_3", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX11_3", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_FAN0_3", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX25_3", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 4 - ], - "tile_types": [ - "CMT_TOP_L_UPPER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_LH7_0", - "VBRK_LH7" - ], - [ - "CMT_TOP_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_LH11_0", - "VBRK_LH11" - ], - [ - "CMT_TOP_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_EE2A1_0", - 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"FAN_L2" - ], - [ - "CLBLL_LOGIC_OUTS5", - "LOGIC_OUTS_L5" - ], - [ - "CLBLL_WW4END2", - "WW4C2" - ], - [ - "CLBLL_LOGIC_OUTS20", - "LOGIC_OUTS_L20" - ], - [ - "CLBLL_LOGIC_OUTS13", - "LOGIC_OUTS_L13" - ], - [ - "CLBLL_SW4A3", - "SW6BEG3" - ], - [ - "CLBLL_SW4END2", - "SW6E2" - ], - [ - "CLBLL_NE4C0", - "NE6END0" - ], - [ - "CLBLL_WW4B3", - "WW4A3" - ], - [ - "CLBLL_IMUX10", - "IMUX_L10" - ], - [ - "CLBLL_EE4B3", - "EE4C3" - ], - [ - "CLBLL_IMUX22", - "IMUX_L22" - ], - [ - "CLBLL_IMUX38", - "IMUX_L38" - ], - [ - "CLBLL_WW4B1", - "WW4A1" - ], - [ - "CLBLL_MONITOR_P", - "MONITOR_P" - ], - [ - "CLBLL_NE4BEG3", - "NE6A3" - ], - [ - "CLBLL_NE2A3", - "NE2END3" - ], - [ - "CLBLL_EL1BEG3", - "EL1END3" - ], - [ - "CLBLL_EE2BEG3", - "EE2A3" - ], - [ - "CLBLL_WW2END0", - "WW2A0" - ], - [ - "CLBLL_EL1BEG2", - "EL1END2" - ], - [ - "CLBLL_WW4A1", - "WW4BEG1" - ], - [ - "CLBLL_SE2A0", - "SE2END0" - ], - [ - "CLBLL_WW4A3", - "WW4BEG3" - ], - [ - "CLBLL_IMUX45", - "IMUX_L45" - ], - [ - "CLBLL_WW4A2", - "WW4BEG2" - ], - [ - "CLBLL_BYP3", - "BYP_L3" - ], - [ - "CLBLL_BYP4", - "BYP_L4" - ], - [ - "CLBLL_IMUX31", - "IMUX_L31" - ], - [ - "CLBLL_WW2END2", - "WW2A2" - ], - [ - "CLBLL_SE4C3", - "SE6END3" - ], - [ - "CLBLL_IMUX42", - "IMUX_L42" - ], - [ - "CLBLL_LH2", - "LH1" - ], - [ - "CLBLL_SE4BEG1", - "SE6A1" - ], - [ - "CLBLL_IMUX6", - "IMUX_L6" - ], - [ - "CLBLL_SE2A2", - "SE2END2" - ], - [ - "CLBLL_SW2A0", - "SW2A0" - ], - [ - "CLBLL_IMUX12", - "IMUX_L12" - ], - [ - "CLBLL_IMUX1", - "IMUX_L1" - ], - [ - "CLBLL_NE4BEG1", - "NE6A1" - ], - [ - "CLBLL_EE4C2", - "EE4END2" - ], - [ - "CLBLL_CLK1", - "CLK_L1" - ], - [ - "CLBLL_NW4A1", - "NW6BEG1" - ], - [ - "CLBLL_LOGIC_OUTS6", - "LOGIC_OUTS_L6" - ], - [ - "CLBLL_SE2A3", - "SE2END3" - ], - [ - "CLBLL_IMUX44", - "IMUX_L44" - ], - [ - "CLBLL_SE4BEG0", - "SE6A0" - ], - [ - "CLBLL_NW4END1", - "NW6E1" - ], - [ - "CLBLL_EL1BEG1", - "EL1END1" - ], - [ - "CLBLL_WW2END3", - "WW2A3" - ], - [ - "CLBLL_IMUX25", - "IMUX_L25" - ], - [ - "CLBLL_LOGIC_OUTS14", - "LOGIC_OUTS_L14" - ], - [ - "CLBLL_LOGIC_OUTS2", - "LOGIC_OUTS_L2" - ], - [ - "CLBLL_IMUX28", - "IMUX_L28" - ], - [ - "CLBLL_LH4", - "LH3" - ], - [ - "CLBLL_BYP6", - "BYP_L6" - ], - [ - "CLBLL_LOGIC_OUTS12", - "LOGIC_OUTS_L12" - ], - [ - "CLBLL_NW4A2", - "NW6BEG2" - ], - [ - "CLBLL_IMUX46", - "IMUX_L46" - ], - [ - "CLBLL_IMUX41", - "IMUX_L41" - ], - [ - "CLBLL_EE4BEG1", - "EE4A1" - ], - [ - "CLBLL_LOGIC_OUTS4", - "LOGIC_OUTS_L4" - ], - [ - "CLBLL_SW4A1", - "SW6BEG1" - ], - [ - "CLBLL_IMUX11", - "IMUX_L11" - ], - [ - "CLBLL_NW4END0", - "NW6E0" - ], - [ - "CLBLL_EE4B0", - "EE4C0" - ], - [ - "CLBLL_WW4C2", - "WW4B2" - ], - [ - "CLBLL_WR1END3", - "WR1BEG3" - ], - [ - "CLBLL_SE4C1", - "SE6END1" - ], - [ - "CLBLL_LOGIC_OUTS16", - "LOGIC_OUTS_L16" - ], - [ - "CLBLL_IMUX33", - "IMUX_L33" - ], - [ - "CLBLL_IMUX34", - "IMUX_L34" - ], - [ - "CLBLL_SW2A3", - "SW2A3" - ], - [ - "CLBLL_ER1BEG1", - "ER1END1" - ], - [ - "CLBLL_LH1", - "LH0" - ], - [ - "CLBLL_EE4BEG3", - "EE4A3" - ], - [ - "CLBLL_LH5", - "LH4" - ], - [ - "CLBLL_FAN4", - "FAN_L4" - ], - [ - "CLBLL_MONITOR_N", - "MONITOR_N" - ], - [ - "CLBLL_IMUX29", - "IMUX_L29" - ], - [ - "CLBLL_IMUX9", - "IMUX_L9" - ], - [ - "CLBLL_BYP2", - "BYP_L2" - ], - [ - "CLBLL_LOGIC_OUTS9", - "LOGIC_OUTS_L9" - ], - [ - "CLBLL_FAN0", - "FAN_L0" - ], - [ - "CLBLL_WR1END2", - "WR1BEG2" - ], - [ - "CLBLL_NE2A1", - "NE2END1" - ], - [ - "CLBLL_WW4A0", - "WW4BEG0" - ], - [ - "CLBLL_FAN1", - "FAN_L1" - ], - [ - "CLBLL_NW2A3", - "NW2A3" - ], - [ - "CLBLL_IMUX40", - "IMUX_L40" - ], - [ - "CLBLL_IMUX36", - "IMUX_L36" - ], - [ - "CLBLL_IMUX7", - "IMUX_L7" - ], - [ - "CLBLL_IMUX43", - "IMUX_L43" - ], - [ - "CLBLL_WW4B2", - "WW4A2" - ], - [ - "CLBLL_WW4END1", - "WW4C1" - ], - [ - "CLBLL_EE2A3", - "EE2END3" - ], - [ - "CLBLL_NW2A2", - "NW2A2" - ], - [ - "CLBLL_LOGIC_OUTS11", - "LOGIC_OUTS_L11" - ], - [ - "CLBLL_CTRL0", - "CTRL_L0" - ], - [ - "CLBLL_LOGIC_OUTS18", - "LOGIC_OUTS_L18" - ], - [ - "CLBLL_LOGIC_OUTS17", - "LOGIC_OUTS_L17" - ], - [ - "CLBLL_ER1BEG2", - "ER1END2" - ], - [ - "CLBLL_EE2A2", - "EE2END2" - ], - [ - "CLBLL_WW4END0", - "WW4C0" - ], - [ - "CLBLL_IMUX26", - "IMUX_L26" - ], - [ - "CLBLL_IMUX19", - "IMUX_L19" - ], - [ - "CLBLL_LH12", - "LH11" - ], - [ - "CLBLL_WW2A2", - "WW2BEG2" - ], - [ - "CLBLL_EE2BEG2", - "EE2A2" - ], - [ - "CLBLL_EE4A0", - "EE4B0" - ], - [ - "CLBLL_LH9", - "LH8" - ], - [ - "CLBLL_IMUX14", - "IMUX_L14" - ], - [ - "CLBLL_EE2BEG1", - "EE2A1" - ], - [ - "CLBLL_EE2BEG0", - "EE2A0" - ], - [ - "CLBLL_LH6", - "LH5" - ], - [ - "CLBLL_NE2A2", - "NE2END2" - ], - [ - "CLBLL_WW4B0", - "WW4A0" - ], - [ - "CLBLL_WR1END1", - "WR1BEG1" - ], - [ - "CLBLL_WL1END3", - "WL1BEG3" - ], - [ - "CLBLL_ER1BEG0", - "ER1END0" - ], - [ - "CLBLL_EE4C1", - "EE4END1" - ], - [ - "CLBLL_SE4BEG2", - "SE6A2" - ], - [ - "CLBLL_EE4B1", - "EE4C1" - ], - [ - "CLBLL_IMUX23", - "IMUX_L23" - ], - [ - "CLBLL_BYP7", - "BYP_L7" - ], - [ - "CLBLL_FAN3", - "FAN_L3" - ], - [ - "CLBLL_IMUX5", - "IMUX_L5" - ], - [ - "CLBLL_WW4C1", - "WW4B1" - ], - [ - "CLBLL_SW4END1", - "SW6E1" - ], - [ - "CLBLL_NE4BEG2", - "NE6A2" - ], - [ - "CLBLL_CLK0", - "CLK_L0" - ], - [ - "CLBLL_IMUX17", - "IMUX_L17" - ], - [ - "CLBLL_SW4A0", - "SW6BEG0" - ], - [ - "CLBLL_EE4A1", - "EE4B1" - ], - [ - "CLBLL_NE4BEG0", - "NE6A0" - ], - [ - "CLBLL_EE4A2", - "EE4B2" - ], - [ - "CLBLL_IMUX21", - "IMUX_L21" - ], - [ - "CLBLL_NW4END3", - "NW6E3" - ], - [ - "CLBLL_IMUX24", - "IMUX_L24" - ], - [ - "CLBLL_NW4A0", - "NW6BEG0" - ], - [ - "CLBLL_LH11", - "LH10" - ], - [ - "CLBLL_EE4B2", - "EE4C2" - ], - [ - "CLBLL_SE4BEG3", - "SE6A3" - ], - [ - "CLBLL_LH7", - "LH6" - ], - [ - "CLBLL_IMUX37", - "IMUX_L37" - ], - [ - "CLBLL_NW2A0", - "NW2A0" - ], - [ - "CLBLL_IMUX2", - "IMUX_L2" - ], - [ - "CLBLL_FAN5", - "FAN_L5" - ], - [ - "CLBLL_BYP0", - "BYP_L0" - ], - [ - "CLBLL_IMUX3", - "IMUX_L3" - ], - [ - "CLBLL_IMUX20", - "IMUX_L20" - ], - [ - "CLBLL_EL1BEG0", - "EL1END0" - ], - [ - "CLBLL_LOGIC_OUTS22", - "LOGIC_OUTS_L22" - ], - [ - "CLBLL_NE4C2", - "NE6END2" - ], - [ - "CLBLL_WW2A0", - "WW2BEG0" - ], - [ - "CLBLL_EE4BEG2", - "EE4A2" - ], - [ - "CLBLL_IMUX35", - "IMUX_L35" - ], - [ - "CLBLL_LOGIC_OUTS8", - "LOGIC_OUTS_L8" - ], - [ - "CLBLL_EE4BEG0", - "EE4A0" - ], - [ - "CLBLL_ER1BEG3", - "ER1END3" - ], - [ - "CLBLL_LH8", - "LH7" - ], - [ - "CLBLL_SW4A2", - "SW6BEG2" - ], - [ - "CLBLL_NE2A0", - "NE2END0" - ], - [ - "CLBLL_WW2A1", - "WW2BEG1" - ], - [ - "CLBLL_LOGIC_OUTS10", - "LOGIC_OUTS_L10" - ], - [ - "CLBLL_IMUX15", - "IMUX_L15" - ], - [ - "CLBLL_BYP5", - "BYP_L5" - ], - [ - "CLBLL_WW4C3", - "WW4B3" - ], - [ - "CLBLL_NE4C3", - "NE6END3" - ], - [ - "CLBLL_SE2A1", - "SE2END1" - ], - [ - "CLBLL_WL1END1", - "WL1BEG1" - ], - [ - "CLBLL_IMUX27", - "IMUX_L27" - ], - [ - "CLBLL_BYP1", - "BYP_L1" - ], - [ - "CLBLL_IMUX30", - "IMUX_L30" - ], - [ - "CLBLL_LOGIC_OUTS0", - "LOGIC_OUTS_L0" - ], - [ - "CLBLL_SW2A2", - "SW2A2" - ], - [ - "CLBLL_LOGIC_OUTS23", - "LOGIC_OUTS_L23" - ], - [ - "CLBLL_WW4END3", - "WW4C3" - ], - [ - "CLBLL_LOGIC_OUTS15", - "LOGIC_OUTS_L15" - ], - [ - "CLBLL_IMUX32", - "IMUX_L32" - ], - [ - "CLBLL_IMUX4", - "IMUX_L4" - ], - [ - "CLBLL_LOGIC_OUTS21", - "LOGIC_OUTS_L21" - ], - [ - "CLBLL_EE4C3", - "EE4END3" - ], - [ - "CLBLL_EE4A3", - "EE4B3" - ], - [ - "CLBLL_WW2A3", - "WW2BEG3" - ], - [ - "CLBLL_WW2END1", - "WW2A1" - ], - [ - "CLBLL_IMUX18", - "IMUX_L18" - ], - [ - "CLBLL_LOGIC_OUTS1", - "LOGIC_OUTS_L1" - ], - [ - "CLBLL_NW4A3", - "NW6BEG3" - ], - [ - "CLBLL_LOGIC_OUTS7", - "LOGIC_OUTS_L7" - ], - [ - "CLBLL_IMUX0", - "IMUX_L0" - ], - [ - "CLBLL_LH10", - "LH9" - ], - [ - "CLBLL_LOGIC_OUTS3", - "LOGIC_OUTS_L3" - ], - [ - "CLBLL_SW2A1", - "SW2A1" - ], - [ - "CLBLL_IMUX39", - "IMUX_L39" - ], - [ - "CLBLL_NW2A1", - "NW2A1" - ], - [ - "CLBLL_EE4C0", - "EE4END0" - ], - [ - "CLBLL_LOGIC_OUTS19", - "LOGIC_OUTS_L19" - ], - [ - "CLBLL_CTRL1", - "CTRL_L1" - ], - [ - "CLBLL_EE2A1", - "EE2END1" - ], - [ - "CLBLL_IMUX47", - "IMUX_L47" - ], - [ - "CLBLL_SW4END0", - "SW6E0" - ], - [ - "CLBLL_NW4END2", - "NW6E2" - ], - [ - "CLBLL_IMUX8", - "IMUX_L8" - ], - [ - "CLBLL_SW4END3", - "SW6E3" - ], - [ - "CLBLL_FAN6", - "FAN_L6" - ], - [ - "CLBLL_WR1END0", - "WR1BEG0" - ], - [ - "CLBLL_IMUX16", - "IMUX_L16" - ], - [ - "CLBLL_FAN7", - "FAN_L7" - ] - ] - }, - { - "grid_deltas": [ - 1, - 3 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_HROW_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_LH6_1", - "VBRK_LH6" - ], - [ - "CLK_HROW_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH1_1", - "VBRK_LH1" - ], - [ - "CLK_HROW_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_HROW_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_HROW_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_HROW_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 1 - ], - "tile_types": [ - "CMT_TOP_L_LOWER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_LH7_0", - "VBRK_LH7" - ], - [ - "CMT_TOP_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_LH11_0", - "VBRK_LH11" - ], - [ - "CMT_TOP_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_LH1_0", - "VBRK_LH1" - ], - [ - "CMT_TOP_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_LH12_0", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_LH8_0", - "VBRK_LH8" - ], - [ - "CMT_TOP_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_LH6_0", - "VBRK_LH6" - ], - [ - "CMT_TOP_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_LH2_0", - "VBRK_LH2" - ], - [ - "CMT_TOP_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_LH3_0", - "VBRK_LH3" - ], - [ - "CMT_TOP_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_LH4_0", - "VBRK_LH4" - ], - [ - "CMT_TOP_WR1END1_0", - "VBRK_WR1END1" - ], - [ - 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], - [ - "CMT_TOP_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_SW2A2_0", - "VBRK_SW2A2" - ], - [ - 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"VBRK_LH7" - ], - [ - "CLK_HROW_EE4B2_6", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE2A1_6", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_WW4B2_6", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EL1BEG1_6", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_ER1BEG0_6", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_SE2A3_6", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_EE2A2_6", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_SW2A2_6", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE2BEG0_6", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW2A1_6", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_SE4C1_6", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WL1END2_6", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_NE4C2_6", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW2A2_6", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4A1_6", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_EE2A3_6", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_WL1END1_6", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NW2A1_6", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SW2A0_6", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_WW4END1_6", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EE4B1_6", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_LH3_6", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE4C1_6", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_SE4C3_6", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_SE2A2_6", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_SW4END3_6", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SW4END2_6", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WW2END1_6", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_SE4BEG3_6", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW4END0_6", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SE4C0_6", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW4END2_6", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_SE4C2_6", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_EE2BEG1_6", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_NW4A2_6", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4A2_6", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_NW4A3_6", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_EE4A0_6", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_SE4BEG1_6", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WW4A3_6", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_NE2A2_6", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_NW2A2_6", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_NE4BEG2_6", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_LH8_6", - "VBRK_LH8" - ], - [ - "CLK_HROW_SW4END1_6", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NE4C3_6", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_LH9_6", - "VBRK_LH9" - ], - [ - "CLK_HROW_EE4BEG3_6", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW2END3_6", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_WW4C2_6", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_LH12_6", - "VBRK_LH12" - ], - [ - "CLK_HROW_WR1END1_6", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW4B0_6", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4A0_6", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EL1BEG3_6", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE4A3_6", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NW4A1_6", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_SE4BEG2_6", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_WW2A0_6", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WW4B3_6", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4C3_6", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_LH11_6", - "VBRK_LH11" - ], - [ - "CLK_HROW_NE4BEG0_6", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_NW2A3_6", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_NE2A1_6", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_SE2A1_6", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4END1_6", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_SW4A3_6", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_SW4END0_6", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE4C3_6", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_SE2A0_6", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4C0_6", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW4C0_6", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE4A2_6", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_ER1BEG3_6", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WW2END2_6", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_NE4BEG1_6", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_NE4C1_6", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_EE4C2_6", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NW4END3_6", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_LH6_6", - "VBRK_LH6" - ], - [ - "CLK_HROW_NW4A0_6", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_LH4_6", - "VBRK_LH4" - ], - [ - "CLK_HROW_WW4C1_6", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_NE4BEG3_6", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_SW4A0_6", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_ER1BEG2_6", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_MONITOR_N_6", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NW4END0_6", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_NE4C0_6", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EL1BEG0_6", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW2A3_6", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WR1END3_6", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_LH1_6", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE2A0_6", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_LH10_6", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE4BEG1_6", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_NE2A3_6", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_LH2_6", - "VBRK_LH2" - ], - [ - "CLK_HROW_WR1END2_6", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_EE4BEG2_6", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_LH5_6", - "VBRK_LH5" - ], - [ - "CLK_HROW_WL1END3_6", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE2BEG3_6", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NE2A0_6", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WR1END0_6", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SW4A2_6", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_SE4BEG0_6", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_EE4BEG0_6", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE2BEG2_6", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SW4A1_6", - "VBRK_SW4A1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -1 - ], - "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_PMV_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_PMV_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_PMV_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_PMV_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_PMV_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "CLK_PMV_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_PMV_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_PMV_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_PMV_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_PMV_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_PMV_IMUX39_1", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_PMV_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_PMV_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_PMV_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_PMV_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_PMV_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_PMV_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_PMV_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_PMV_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_PMV_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_PMV_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_PMV_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_PMV_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_PMV_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_PMV_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_PMV_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_PMV_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_PMV_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_PMV_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_PMV_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_PMV_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_PMV_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_PMV_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_PMV_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_PMV_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_PMV_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_PMV_ER1BEG0_1", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_PMV_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_PMV_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_PMV_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_PMV_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_PMV_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_PMV_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CLK_PMV_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_PMV_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_PMV_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_PMV_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_PMV_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_PMV_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_PMV_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_PMV_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_PMV_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_PMV_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_PMV_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_PMV_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_PMV_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_PMV_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_PMV_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_PMV_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX10_1", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_PMV_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_PMV_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_PMV_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_PMV_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_PMV_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_PMV_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_PMV_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_PMV_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_IMUX3_1", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_PMV_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_PMV_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_PMV_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_PMV_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_PMV_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_PMV_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_PMV_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_PMV_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - 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"INT_FEEDTHRU_2_EE2A1", - "MONITOR_EE2A1_7" - ], - [ - "INT_FEEDTHRU_2_WW4END2", - "MONITOR_WW4END2_7" - ], - [ - "INT_FEEDTHRU_2_WW4END1", - "MONITOR_WW4END1_7" - ], - [ - "INT_FEEDTHRU_2_WR1END0", - "MONITOR_WR1END0_7" - ], - [ - "INT_FEEDTHRU_2_WR1END2", - "MONITOR_WR1END2_7" - ], - [ - "INT_FEEDTHRU_2_SW2A1", - "MONITOR_SW2A1_7" - ], - [ - "INT_FEEDTHRU_2_WW2END2", - "MONITOR_WW2END2_7" - ], - [ - "INT_FEEDTHRU_2_SW4END1", - "MONITOR_SW4END1_7" - ], - [ - "INT_FEEDTHRU_2_SW4END2", - "MONITOR_SW4END2_7" - ], - [ - "INT_FEEDTHRU_2_WL1END0", - "MONITOR_WL1END0_7" - ], - [ - "INT_FEEDTHRU_2_WL1END1", - "MONITOR_WL1END1_7" - ], - [ - "INT_FEEDTHRU_2_EE2BEG1", - "MONITOR_EE2BEG1_7" - ], - [ - "INT_FEEDTHRU_2_WL1END2", - "MONITOR_WL1END2_7" - ], - [ - "INT_FEEDTHRU_2_EE4C0", - "MONITOR_EE4C0_7" - ], - [ - "INT_FEEDTHRU_2_EE4BEG3", - "MONITOR_EE4BEG3_7" - ], - [ - "INT_FEEDTHRU_2_EE2BEG0", - "MONITOR_EE2BEG0_7" - ], - [ - "INT_FEEDTHRU_2_EE2BEG2", - "MONITOR_EE2BEG2_7" - ], - [ - "INT_FEEDTHRU_2_SW2A3", - "MONITOR_SW2A3_7" - ], - [ - "INT_FEEDTHRU_2_EE4B3", - "MONITOR_EE4B3_7" - ], - [ - "INT_FEEDTHRU_2_EE4A3", - "MONITOR_EE4A3_7" - ], - [ - "INT_FEEDTHRU_2_LH6", - "MONITOR_LH6_7" - ], - [ - "INT_FEEDTHRU_2_NE4C2", - "MONITOR_NE4C2_7" - ], - [ - "INT_FEEDTHRU_2_WW4C1", - "MONITOR_WW4C1_7" - ], - [ - "INT_FEEDTHRU_2_NW2A3", - "MONITOR_NW2A3_7" - ], - [ - "INT_FEEDTHRU_2_WW2A0", - "MONITOR_WW2A0_7" - ], - [ - "INT_FEEDTHRU_2_NE2A0", - "MONITOR_NE2A0_7" - ], - [ - "INT_FEEDTHRU_2_LH10", - "MONITOR_LH10_7" - ], - [ - "INT_FEEDTHRU_2_LH1", - "MONITOR_LH1_7" - ], - [ - "INT_FEEDTHRU_2_NW4END3", - "MONITOR_NW4END3_7" - ], - [ - "INT_FEEDTHRU_2_WW4C3", - "MONITOR_WW4C3_7" - ], - [ - "INT_FEEDTHRU_2_NW4END2", - "MONITOR_NW4END2_7" - ], - [ - "INT_FEEDTHRU_2_EL1BEG1", - "MONITOR_EL1BEG1_7" - ], - [ - "INT_FEEDTHRU_2_EE4C1", - "MONITOR_EE4C1_7" - ], - [ - "INT_FEEDTHRU_2_SE2A3", - "MONITOR_SE2A3_7" - ], - [ - "INT_FEEDTHRU_2_SW2A0", - "MONITOR_SW2A0_7" - ], - [ - "INT_FEEDTHRU_2_WW4B0", - "MONITOR_WW4B0_7" - ], - [ - "INT_FEEDTHRU_2_EE2A3", - "MONITOR_EE2A3_7" - ], - [ - "INT_FEEDTHRU_2_NE2A2", - "MONITOR_NE2A2_7" - ], - [ - "INT_FEEDTHRU_2_WW2A2", - "MONITOR_WW2A2_7" - ], - [ - "INT_FEEDTHRU_2_SE4BEG0", - "MONITOR_SE4BEG0_7" - ], - [ - "INT_FEEDTHRU_2_SE4BEG3", - "MONITOR_SE4BEG3_7" - ], - [ - "INT_FEEDTHRU_2_NE4C3", - "MONITOR_NE4C3_7" - ], - [ - "INT_FEEDTHRU_2_SW4A0", - "MONITOR_SW4A0_7" - ], - [ - "INT_FEEDTHRU_2_NW4A2", - "MONITOR_NW4A2_7" - ], - [ - "INT_FEEDTHRU_2_LH12", - "MONITOR_LH12_7" - ], - [ - "INT_FEEDTHRU_2_ER1BEG1", - "MONITOR_ER1BEG1_7" - ], - [ - "INT_FEEDTHRU_2_EE4B0", - "MONITOR_EE4B0_7" - ], - [ - "INT_FEEDTHRU_2_LH2", - "MONITOR_LH2_7" - ], - [ - "INT_FEEDTHRU_2_EE4B1", - "MONITOR_EE4B1_7" - ], - [ - "INT_FEEDTHRU_2_SE4C3", - "MONITOR_SE4C3_7" - ], - [ - "INT_FEEDTHRU_2_NE2A1", - "MONITOR_NE2A1_7" - ], - [ - "INT_FEEDTHRU_2_NW4A1", - "MONITOR_NW4A1_7" - ], - [ - "INT_FEEDTHRU_2_SW4A2", - "MONITOR_SW4A2_7" - ], - [ - "INT_FEEDTHRU_2_SE4BEG2", - "MONITOR_SE4BEG2_7" - ], - [ - "INT_FEEDTHRU_2_SW4END0", - "MONITOR_SW4END0_7" - ], - [ - "INT_FEEDTHRU_2_EE2A2", - "MONITOR_EE2A2_7" - ], - [ - "INT_FEEDTHRU_2_SE4C1", - "MONITOR_SE4C1_7" - ], - [ - "INT_FEEDTHRU_2_NE4C1", - "MONITOR_NE4C1_7" - ], - [ - "INT_FEEDTHRU_2_LH8", - "MONITOR_LH8_7" - ], - [ - "INT_FEEDTHRU_2_ER1BEG2", - "MONITOR_ER1BEG2_7" - ], - [ - "INT_FEEDTHRU_2_LH9", - "MONITOR_LH9_7" - ], - [ - "INT_FEEDTHRU_2_WW4C0", - "MONITOR_WW4C0_7" - ], - [ - "INT_FEEDTHRU_2_NE4BEG0", - "MONITOR_NE4BEG0_7" - ], - [ - "INT_FEEDTHRU_2_EE4C2", - "MONITOR_EE4C2_7" - ], - [ - "INT_FEEDTHRU_2_NW4A0", - "MONITOR_NW4A0_7" - ], - [ - "INT_FEEDTHRU_2_WW4B1", - "MONITOR_WW4B1_7" - ], - [ - "INT_FEEDTHRU_2_WW4C2", - "MONITOR_WW4C2_7" - ], - [ - "INT_FEEDTHRU_2_SW4END3", - "MONITOR_SW4END3_7" - ], - [ - "INT_FEEDTHRU_2_WW2A3", - "MONITOR_WW2A3_7" - ], - [ - "INT_FEEDTHRU_2_EE4A1", - "MONITOR_EE4A1_7" - ], - [ - "INT_FEEDTHRU_2_WW4A2", - "MONITOR_WW4A2_7" + "CLK_FEED_R_CK_GCLK31", + "CLK_PMV_R_CK_GCLK31" ] ] }, { "grid_deltas": [ - -1, - -7 + 0, + -1 ], "tile_types": [ - "CMT_TOP_L_LOWER_T", - "VBRK" + "CLK_FEED", + "CLK_PMV2" ], "wire_pairs": [ [ - "CMT_TOP_EL1BEG1_8", - "VBRK_EL1BEG1" + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" ], [ - "CMT_TOP_NE2A0_8", - "VBRK_NE2A0" + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" ], [ - "CMT_TOP_EE4B2_8", - "VBRK_EE4B2" + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" ], [ - "CMT_TOP_NE4BEG3_8", - "VBRK_NE4BEG3" + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" ], [ - "CMT_TOP_NW4A1_8", - "VBRK_NW4A1" + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" ], [ - "CMT_TOP_WW4A1_8", - "VBRK_WW4A1" + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" ], [ - "CMT_TOP_LH2_8", - "VBRK_LH2" + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" ], [ - "CMT_TOP_NE2A1_8", - "VBRK_NE2A1" + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" ], [ - "CMT_TOP_SW4A2_8", - "VBRK_SW4A2" + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" ], [ - "CMT_TOP_SW4END1_8", - "VBRK_SW4END1" + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" ], [ - "CMT_TOP_NE4C1_8", - "VBRK_NE4C1" + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" ], [ - "CMT_TOP_WW4A2_8", - "VBRK_WW4A2" + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" ], [ - "CMT_TOP_ER1BEG3_8", - "VBRK_ER1BEG3" + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" ], [ - "CMT_TOP_EE2A0_8", - "VBRK_EE2A0" + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" ], [ - "CMT_TOP_NE2A3_8", - "VBRK_NE2A3" + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" ], [ - "CMT_TOP_SE2A1_8", - "VBRK_SE2A1" + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" ], [ - "CMT_TOP_WW2A0_8", - "VBRK_WW2A0" + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" ], [ - "CMT_TOP_EE4B0_8", - "VBRK_EE4B0" + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" ], [ - "CMT_TOP_EE4C0_8", - "VBRK_EE4C0" + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" ], [ - "CMT_TOP_ER1BEG0_8", - "VBRK_ER1BEG0" + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" ], [ - "CMT_TOP_WW2A1_8", - "VBRK_WW2A1" + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" ], [ - "CMT_TOP_EL1BEG0_8", - "VBRK_EL1BEG0" + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" ], [ - "CMT_TOP_WL1END3_8", - "VBRK_WL1END3" + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" ], [ - "CMT_TOP_EE4B3_8", - "VBRK_EE4B3" + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" ], [ - "CMT_TOP_NW4A2_8", - "VBRK_NW4A2" + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" ], [ - "CMT_TOP_LH6_8", - "VBRK_LH6" + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" ], [ - "CMT_TOP_EE4C2_8", - "VBRK_EE4C2" + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" ], [ - "CMT_TOP_EE4C3_8", - "VBRK_EE4C3" + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" ], [ - "CMT_TOP_SE4BEG2_8", - "VBRK_SE4BEG2" + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" ], [ - "CMT_TOP_EE2BEG1_8", - "VBRK_EE2BEG1" + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" ], [ - "CMT_TOP_ER1BEG2_8", - "VBRK_ER1BEG2" + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" ], [ - "CMT_TOP_EE4BEG1_8", - "VBRK_EE4BEG1" + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" ], [ - "CMT_TOP_NE4BEG2_8", - "VBRK_NE4BEG2" + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" ], [ - "CMT_TOP_SW2A1_8", - "VBRK_SW2A1" + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" ], [ - "CMT_TOP_NW4END1_8", - "VBRK_NW4END1" + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" ], [ - "CMT_TOP_SE4C1_8", - "VBRK_SE4C1" + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" ], [ - "CMT_TOP_NW4END0_8", - "VBRK_NW4END0" + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" ], [ - "CMT_TOP_NW4A0_8", - "VBRK_NW4A0" + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" ], [ - "CMT_TOP_NW2A1_8", - "VBRK_NW2A1" + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" ], [ - "CMT_TOP_EL1BEG2_8", - "VBRK_EL1BEG2" + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" ], [ - "CMT_TOP_WW4A3_8", - "VBRK_WW4A3" + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" ], [ - "CMT_TOP_NW4A3_8", - "VBRK_NW4A3" + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" ], [ - "CMT_TOP_LH7_8", - "VBRK_LH7" + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" ], [ - "CMT_TOP_EE2BEG0_8", - "VBRK_EE2BEG0" + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" ], [ - "CMT_TOP_SE4BEG3_8", - "VBRK_SE4BEG3" + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" ], [ - "CMT_TOP_WW4C2_8", - "VBRK_WW4C2" + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" ], [ - "CMT_TOP_SW2A2_8", - "VBRK_SW2A2" + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" ], [ - "CMT_TOP_WW4C1_8", - "VBRK_WW4C1" + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" ], [ - "CMT_TOP_WL1END2_8", - "VBRK_WL1END2" + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" ], [ - "CMT_TOP_WW2END0_8", - "VBRK_WW2END0" + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" ], [ - "CMT_TOP_SW4A0_8", - "VBRK_SW4A0" + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" ], [ - "CMT_TOP_NW2A0_8", - "VBRK_NW2A0" + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" ], [ - "CMT_TOP_WL1END0_8", - "VBRK_WL1END0" + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" ], [ - "CMT_TOP_EE4A3_8", - "VBRK_EE4A3" + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" ], [ - "CMT_TOP_WR1END0_8", - "VBRK_WR1END0" + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" ], [ - "CMT_TOP_EE4BEG3_8", - "VBRK_EE4BEG3" + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" ], [ - "CMT_TOP_ER1BEG1_8", - "VBRK_ER1BEG1" + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" ], [ - "CMT_TOP_NE4C3_8", - "VBRK_NE4C3" + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" ], [ - "CMT_TOP_NW4END2_8", - "VBRK_NW4END2" + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" ], [ - "CMT_TOP_SW4A1_8", - "VBRK_SW4A1" + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" ], [ - "CMT_TOP_EE2A1_8", - "VBRK_EE2A1" + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" ], [ - "CMT_TOP_LH4_8", - "VBRK_LH4" + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" ], [ - "CMT_TOP_WW4B3_8", - "VBRK_WW4B3" + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" ], [ - "CMT_TOP_SE4C0_8", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_SE2A3_8", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_SE4C3_8", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WL1END1_8", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_WW2END2_8", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_LH8_8", - "VBRK_LH8" - ], - [ - "CMT_TOP_EE4A1_8", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_WW2END1_8", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_WW2END3_8", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_WW4C0_8", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_EE4C1_8", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_EE2A3_8", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_LH3_8", - "VBRK_LH3" - ], - [ - "CMT_TOP_LH10_8", - "VBRK_LH10" - ], - [ - "CMT_TOP_WR1END1_8", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_NE4BEG1_8", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_WW2A2_8", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_EE4A2_8", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_NE4C2_8", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_EE2BEG3_8", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_NW4END3_8", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW4A0_8", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_LH12_8", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE4BEG2_8", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_WW4B0_8", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_SW4END0_8", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_WW4END1_8", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_EE4BEG0_8", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_NW2A2_8", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WW4END0_8", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_EE4B1_8", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_EE2A2_8", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_LH5_8", - "VBRK_LH5" - ], - [ - "CMT_TOP_NW2A3_8", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_NE4BEG0_8", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_SW2A0_8", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_WW4B1_8", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WW4B2_8", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_NE2A2_8", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_NE4C0_8", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_EE2BEG2_8", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_WR1END3_8", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW2A3_8", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_SE2A2_8", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_WW4END3_8", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_WW4C3_8", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_SE2A0_8", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_WW4END2_8", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_LH1_8", - "VBRK_LH1" - ], - [ - "CMT_TOP_SW4END2_8", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_SE4BEG0_8", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_WR1END2_8", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_LH9_8", - "VBRK_LH9" - ], - [ - "CMT_TOP_SW2A3_8", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_SE4C2_8", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_LH11_8", - "VBRK_LH11" - ], - [ - "CMT_TOP_SE4BEG1_8", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_EE4A0_8", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_SW4END3_8", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SW4A3_8", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_EL1BEG3_8", - "VBRK_EL1BEG3" + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ - -1, - 0 + 0, + 1 ], "tile_types": [ - "CMT_TOP_L_UPPER_T", - "VBRK" + "CLK_FEED", + "CLK_PMV2" ], "wire_pairs": [ [ - "CMT_TOP_SW4A0_5", - "VBRK_SW4A0" + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" ], [ - "CMT_TOP_NW4A0_5", - "VBRK_NW4A0" + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" ], [ - "CMT_TOP_NW4A1_5", - "VBRK_NW4A1" + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" ], [ - "CMT_TOP_EE2A0_5", - "VBRK_EE2A0" + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" ], [ - "CMT_TOP_EE4A0_5", - "VBRK_EE4A0" + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" ], [ - "CMT_TOP_EE4BEG0_5", - "VBRK_EE4BEG0" + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" ], [ - "CMT_TOP_WW4A3_5", - "VBRK_WW4A3" + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" ], [ - "CMT_TOP_LH6_5", - "VBRK_LH6" + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" ], [ - "CMT_TOP_NW4A2_5", - "VBRK_NW4A2" + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" ], [ - "CMT_TOP_WR1END0_5", - "VBRK_WR1END0" + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" ], [ - "CMT_TOP_NE4BEG1_5", - "VBRK_NE4BEG1" + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" ], [ - "CMT_TOP_WL1END3_5", - "VBRK_WL1END3" + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" ], [ - "CMT_TOP_SE4BEG0_5", - "VBRK_SE4BEG0" + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" ], [ - "CMT_TOP_SW2A0_5", - "VBRK_SW2A0" + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" ], [ - "CMT_TOP_WL1END1_5", - "VBRK_WL1END1" + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" ], [ - "CMT_TOP_NW4END3_5", - "VBRK_NW4END3" + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" ], [ - "CMT_TOP_WW4C2_5", - "VBRK_WW4C2" + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" ], [ - "CMT_TOP_WW4A1_5", - "VBRK_WW4A1" + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" ], [ - "CMT_TOP_NE4C3_5", - "VBRK_NE4C3" + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" ], [ - "CMT_TOP_EE2A3_5", - "VBRK_EE2A3" + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" ], [ - "CMT_TOP_EE4A1_5", - "VBRK_EE4A1" + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" ], [ - "CMT_TOP_WW2A0_5", - "VBRK_WW2A0" + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" ], [ - "CMT_TOP_SE2A0_5", - "VBRK_SE2A0" + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" ], [ - "CMT_TOP_SE4C0_5", - "VBRK_SE4C0" + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" ], [ - "CMT_TOP_WW4B2_5", - "VBRK_WW4B2" + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" ], [ - "CMT_TOP_NE4C0_5", - "VBRK_NE4C0" + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" ], [ - "CMT_TOP_SE4C3_5", - "VBRK_SE4C3" + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" ], [ - "CMT_TOP_SE2A1_5", - "VBRK_SE2A1" + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" ], [ - "CMT_TOP_EE2A2_5", - "VBRK_EE2A2" + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" ], [ - "CMT_TOP_WW4END2_5", - "VBRK_WW4END2" + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" ], [ - "CMT_TOP_WW4END0_5", - "VBRK_WW4END0" + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" ], [ - "CMT_TOP_WW2END2_5", - "VBRK_WW2END2" + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" ], [ - "CMT_TOP_WW4B1_5", - "VBRK_WW4B1" + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" ], [ - "CMT_TOP_LH5_5", - "VBRK_LH5" + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" ], [ - "CMT_TOP_WW4B3_5", - "VBRK_WW4B3" + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" ], [ - "CMT_TOP_EE4B3_5", - "VBRK_EE4B3" + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" ], [ - "CMT_TOP_EE4BEG2_5", - "VBRK_EE4BEG2" + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" ], [ - "CMT_TOP_EE2BEG0_5", - "VBRK_EE2BEG0" + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" ], [ - "CMT_TOP_EL1BEG1_5", - "VBRK_EL1BEG1" + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" ], [ - "CMT_TOP_ER1BEG1_5", - "VBRK_ER1BEG1" + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" ], [ - "CMT_TOP_SE4BEG1_5", - "VBRK_SE4BEG1" + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" ], [ - "CMT_TOP_EE4C0_5", - "VBRK_EE4C0" + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" ], [ - "CMT_TOP_NW2A1_5", - "VBRK_NW2A1" + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" ], [ - "CMT_TOP_NW4END1_5", - "VBRK_NW4END1" + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" ], [ - "CMT_TOP_NW4END2_5", - "VBRK_NW4END2" + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" ], [ - "CMT_TOP_WW4A2_5", - "VBRK_WW4A2" + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" ], [ - "CMT_TOP_NE2A3_5", - "VBRK_NE2A3" + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" ], [ - "CMT_TOP_LH7_5", - "VBRK_LH7" + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" ], [ - "CMT_TOP_NW2A3_5", - "VBRK_NW2A3" + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" ], [ - "CMT_TOP_NE4C1_5", - "VBRK_NE4C1" + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" ], [ - "CMT_TOP_EE4C3_5", - "VBRK_EE4C3" + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" ], [ - "CMT_TOP_LH3_5", - "VBRK_LH3" + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" ], [ - "CMT_TOP_LH2_5", - "VBRK_LH2" + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" ], [ - "CMT_TOP_EE4B0_5", - "VBRK_EE4B0" + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" ], [ - "CMT_TOP_EE4BEG1_5", - "VBRK_EE4BEG1" + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" ], [ - "CMT_TOP_LH1_5", - "VBRK_LH1" + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" ], [ - "CMT_TOP_WW4C0_5", - "VBRK_WW4C0" + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" ], [ - "CMT_TOP_WW2END3_5", - "VBRK_WW2END3" + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" ], [ - "CMT_TOP_ER1BEG0_5", - "VBRK_ER1BEG0" + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" ], [ - "CMT_TOP_SE4C2_5", - "VBRK_SE4C2" + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" ], [ - "CMT_TOP_NE4C2_5", - "VBRK_NE4C2" + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" ], [ - "CMT_TOP_EE2BEG1_5", - "VBRK_EE2BEG1" + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" ], [ - "CMT_TOP_NE2A0_5", - "VBRK_NE2A0" + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" ], [ - "CMT_TOP_EE4C2_5", - "VBRK_EE4C2" + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "CLK_FEED", + "CLK_PMV2_SVT" + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + 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"CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" ], [ - "CMT_TOP_NW4END0_5", - "VBRK_NW4END0" + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" ], [ - "CMT_TOP_WW4END3_5", - "VBRK_WW4END3" + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" ], [ - "CMT_TOP_EE4C1_5", - "VBRK_EE4C1" + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "CLK_FEED", + "CLK_TERM" + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_TERM_R_GCLK0" + ], + [ + "CLK_FEED_R_CK_GCLK1", + "CLK_TERM_R_GCLK1" + ], + [ + "CLK_FEED_R_CK_GCLK2", + "CLK_TERM_R_GCLK2" + ], + [ + "CLK_FEED_R_CK_GCLK3", + "CLK_TERM_R_GCLK3" + ], + [ + "CLK_FEED_R_CK_GCLK4", + "CLK_TERM_R_GCLK4" + ], + [ + "CLK_FEED_R_CK_GCLK5", + "CLK_TERM_R_GCLK5" + ], + [ + "CLK_FEED_R_CK_GCLK6", + "CLK_TERM_R_GCLK6" + ], + [ + "CLK_FEED_R_CK_GCLK7", + "CLK_TERM_R_GCLK7" + ], + [ + "CLK_FEED_R_CK_GCLK8", + "CLK_TERM_R_GCLK8" + ], + [ + "CLK_FEED_R_CK_GCLK9", + "CLK_TERM_R_GCLK9" + ], + [ + "CLK_FEED_R_CK_GCLK10", + "CLK_TERM_R_GCLK10" + ], + [ + "CLK_FEED_R_CK_GCLK11", + "CLK_TERM_R_GCLK11" + ], + [ + "CLK_FEED_R_CK_GCLK12", + "CLK_TERM_R_GCLK12" + ], + [ + "CLK_FEED_R_CK_GCLK13", + "CLK_TERM_R_GCLK13" + ], + [ + "CLK_FEED_R_CK_GCLK14", + "CLK_TERM_R_GCLK14" + ], + [ + "CLK_FEED_R_CK_GCLK15", + "CLK_TERM_R_GCLK15" + ], + [ + "CLK_FEED_R_CK_GCLK16", + "CLK_TERM_R_GCLK16" + ], + [ + "CLK_FEED_R_CK_GCLK17", + "CLK_TERM_R_GCLK17" + ], + [ + "CLK_FEED_R_CK_GCLK18", + "CLK_TERM_R_GCLK18" + ], + [ + "CLK_FEED_R_CK_GCLK19", + "CLK_TERM_R_GCLK19" + ], + [ + "CLK_FEED_R_CK_GCLK20", + "CLK_TERM_R_GCLK20" + ], + [ + "CLK_FEED_R_CK_GCLK21", + "CLK_TERM_R_GCLK21" + ], + [ + "CLK_FEED_R_CK_GCLK22", + "CLK_TERM_R_GCLK22" + ], + [ + "CLK_FEED_R_CK_GCLK23", + "CLK_TERM_R_GCLK23" + ], + [ + "CLK_FEED_R_CK_GCLK24", + "CLK_TERM_R_GCLK24" + ], + [ + "CLK_FEED_R_CK_GCLK25", + "CLK_TERM_R_GCLK25" + ], + [ + "CLK_FEED_R_CK_GCLK26", + "CLK_TERM_R_GCLK26" + ], + [ + "CLK_FEED_R_CK_GCLK27", + "CLK_TERM_R_GCLK27" + ], + [ + "CLK_FEED_R_CK_GCLK28", + "CLK_TERM_R_GCLK28" + ], + [ + "CLK_FEED_R_CK_GCLK29", + "CLK_TERM_R_GCLK29" + ], + [ + "CLK_FEED_R_CK_GCLK30", + "CLK_TERM_R_GCLK30" + ], + [ + "CLK_FEED_R_CK_GCLK31", + "CLK_TERM_R_GCLK31" + ] + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "tile_types": [ + "CLK_FEED", + "CLK_TERM" + ], + "wire_pairs": [ + [ + "CLK_FEED_R_CK_GCLK0", + "CLK_TERM_R_GCLK0" ], [ - "CMT_TOP_WW2END0_5", - "VBRK_WW2END0" + "CLK_FEED_R_CK_GCLK1", + "CLK_TERM_R_GCLK1" ], [ - "CMT_TOP_EE2A1_5", - "VBRK_EE2A1" + "CLK_FEED_R_CK_GCLK2", + "CLK_TERM_R_GCLK2" ], [ - "CMT_TOP_EL1BEG2_5", - "VBRK_EL1BEG2" + "CLK_FEED_R_CK_GCLK3", + "CLK_TERM_R_GCLK3" ], [ - "CMT_TOP_SE4BEG2_5", - "VBRK_SE4BEG2" + "CLK_FEED_R_CK_GCLK4", + "CLK_TERM_R_GCLK4" ], [ - "CMT_TOP_EE2BEG3_5", - "VBRK_EE2BEG3" + "CLK_FEED_R_CK_GCLK5", + "CLK_TERM_R_GCLK5" ], [ - "CMT_TOP_WW2A2_5", - "VBRK_WW2A2" + "CLK_FEED_R_CK_GCLK6", + "CLK_TERM_R_GCLK6" ], [ - "CMT_TOP_WW4END1_5", - "VBRK_WW4END1" + "CLK_FEED_R_CK_GCLK7", + "CLK_TERM_R_GCLK7" ], [ - "CMT_TOP_WW2A3_5", - "VBRK_WW2A3" + "CLK_FEED_R_CK_GCLK8", + "CLK_TERM_R_GCLK8" ], [ - "CMT_TOP_EE2BEG2_5", - "VBRK_EE2BEG2" + "CLK_FEED_R_CK_GCLK9", + "CLK_TERM_R_GCLK9" ], [ - "CMT_TOP_EE4B1_5", - "VBRK_EE4B1" + "CLK_FEED_R_CK_GCLK10", + "CLK_TERM_R_GCLK10" ], [ - "CMT_TOP_SE4BEG3_5", - "VBRK_SE4BEG3" + "CLK_FEED_R_CK_GCLK11", + "CLK_TERM_R_GCLK11" ], [ - "CMT_TOP_NE2A1_5", - "VBRK_NE2A1" + "CLK_FEED_R_CK_GCLK12", + "CLK_TERM_R_GCLK12" ], [ - "CMT_TOP_SW4END2_5", - "VBRK_SW4END2" + "CLK_FEED_R_CK_GCLK13", + "CLK_TERM_R_GCLK13" ], [ - "CMT_TOP_WW2END1_5", - "VBRK_WW2END1" + "CLK_FEED_R_CK_GCLK14", + "CLK_TERM_R_GCLK14" ], [ - "CMT_TOP_ER1BEG3_5", - "VBRK_ER1BEG3" + "CLK_FEED_R_CK_GCLK15", + "CLK_TERM_R_GCLK15" ], [ - "CMT_TOP_ER1BEG2_5", - "VBRK_ER1BEG2" + "CLK_FEED_R_CK_GCLK16", + "CLK_TERM_R_GCLK16" ], [ - "CMT_TOP_SE2A3_5", - "VBRK_SE2A3" + "CLK_FEED_R_CK_GCLK17", + "CLK_TERM_R_GCLK17" ], [ - "CMT_TOP_WW4C1_5", - "VBRK_WW4C1" + "CLK_FEED_R_CK_GCLK18", + "CLK_TERM_R_GCLK18" ], [ - "CMT_TOP_NE4BEG3_5", - "VBRK_NE4BEG3" + "CLK_FEED_R_CK_GCLK19", + "CLK_TERM_R_GCLK19" ], [ - "CMT_TOP_NE4BEG2_5", - "VBRK_NE4BEG2" + "CLK_FEED_R_CK_GCLK20", + "CLK_TERM_R_GCLK20" ], [ - "CMT_TOP_LH8_5", - "VBRK_LH8" + "CLK_FEED_R_CK_GCLK21", + "CLK_TERM_R_GCLK21" ], [ - "CMT_TOP_SE4C1_5", - "VBRK_SE4C1" + "CLK_FEED_R_CK_GCLK22", + "CLK_TERM_R_GCLK22" ], [ - "CMT_TOP_WR1END1_5", - "VBRK_WR1END1" + "CLK_FEED_R_CK_GCLK23", + "CLK_TERM_R_GCLK23" ], [ - "CMT_TOP_NE2A2_5", - "VBRK_NE2A2" + "CLK_FEED_R_CK_GCLK24", + "CLK_TERM_R_GCLK24" ], [ - "CMT_TOP_SW2A2_5", - "VBRK_SW2A2" + "CLK_FEED_R_CK_GCLK25", + "CLK_TERM_R_GCLK25" ], [ - "CMT_TOP_EL1BEG0_5", - "VBRK_EL1BEG0" + "CLK_FEED_R_CK_GCLK26", + "CLK_TERM_R_GCLK26" ], [ - "CMT_TOP_WW2A1_5", - "VBRK_WW2A1" + "CLK_FEED_R_CK_GCLK27", + "CLK_TERM_R_GCLK27" ], [ - "CMT_TOP_NW2A2_5", - "VBRK_NW2A2" + "CLK_FEED_R_CK_GCLK28", + "CLK_TERM_R_GCLK28" ], [ - "CMT_TOP_SE2A2_5", - "VBRK_SE2A2" + "CLK_FEED_R_CK_GCLK29", + "CLK_TERM_R_GCLK29" ], [ - "CMT_TOP_EE4B2_5", - "VBRK_EE4B2" + "CLK_FEED_R_CK_GCLK30", + "CLK_TERM_R_GCLK30" ], [ - "CMT_TOP_SW4END0_5", - "VBRK_SW4END0" + "CLK_FEED_R_CK_GCLK31", + "CLK_TERM_R_GCLK31" ] ] }, @@ -132554,860 +125762,508 @@ ], "wire_pairs": [ [ - "CLK_FEED_EE2BEG1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_FEED_NW4END3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_FEED_WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_FEED_EE4BEG1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_FEED_NE2A3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_NE2A2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_FEED_WW4B2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_FEED_NW4A2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_FEED_WR1END0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_FEED_NE4C3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_FEED_EE4A2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_FEED_EL1BEG1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_FEED_NE4C0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_FEED_WL1END2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_FEED_NW2A2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_FEED_NW4END1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_FEED_SW4A3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_FEED_LH7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_FEED_WW4END3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_FEED_WR1END1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_FEED_SE4C0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_FEED_EE4B3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_FEED_MONITOR_P", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_FEED_SW4A1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_FEED_LH9", - "INT_INTERFACE_LH9" - ], - [ - "CLK_FEED_NW2A1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_FEED_EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_FEED_SW4END1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_FEED_NE4C1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_FEED_SW2A1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_FEED_SW4END3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_FEED_SE4C1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_FEED_LH3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_FEED_WR1END2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_FEED_SE4BEG3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_FEED_LH1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_FEED_NW4A1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_FEED_LH6", - "INT_INTERFACE_LH6" - ], - [ - "CLK_FEED_ER1BEG1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_FEED_WW4B3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_FEED_NE2A0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_FEED_WW4A1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_FEED_LH12", - "INT_INTERFACE_LH12" - ], - [ - "CLK_FEED_WW4A0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_FEED_SW4END0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_FEED_EE4A1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_FEED_EL1BEG0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_FEED_EE4B1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_FEED_SE4BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_FEED_WW4B1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_FEED_EE2BEG0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_FEED_WW4C2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_FEED_ER1BEG2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_FEED_LH2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_FEED_SE4BEG1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_FEED_EE4A3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_FEED_EL1BEG3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_FEED_LH4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_FEED_SE2A3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_FEED_LH5", - "INT_INTERFACE_LH5" - ], - [ - "CLK_FEED_WW4A3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_FEED_LH11", - "INT_INTERFACE_LH11" - ], - [ - "CLK_FEED_SE2A0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_FEED_NW4A3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_FEED_WW4END1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_FEED_MONITOR_N", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_FEED_EL1BEG2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_FEED_WL1END1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_FEED_SW4A0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_FEED_WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_FEED_SW4END2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_FEED_WW2END2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_FEED_WL1END3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_FEED_WR1END3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_FEED_SE4C3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_FEED_LH8", - "INT_INTERFACE_LH8" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_EE4B2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_FEED_SE2A1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_FEED_NW4END0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_FEED_EE4B0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_FEED_EE2BEG3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_FEED_SW2A0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_FEED_WW4C1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_FEED_WW4B0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_FEED_SE4C2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_FEED_SW2A2", - "INT_INTERFACE_SW2A2" + "CLK_FEED_EE2A0", + "INT_INTERFACE_EE2A0" ], [ "CLK_FEED_EE2A1", "INT_INTERFACE_EE2A1" ], [ - "CLK_FEED_ER1BEG0", - "INT_INTERFACE_ER1BEG0" + "CLK_FEED_EE2A2", + "INT_INTERFACE_EE2A2" ], [ - "CLK_FEED_WW4A2", - "INT_INTERFACE_WW4A2" + "CLK_FEED_EE2A3", + "INT_INTERFACE_EE2A3" ], [ - "CLK_FEED_EE4A0", - "INT_INTERFACE_EE4A0" + "CLK_FEED_EE2BEG0", + "INT_INTERFACE_EE2BEG0" ], [ - "CLK_FEED_NE4C2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_FEED_NW4END2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_FEED_EE2A0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_FEED_NE4BEG1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_FEED_WW2A3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_FEED_SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_FEED_WW4END0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_FEED_WW2A2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_FEED_EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_FEED_NE4BEG2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_FEED_WW4C0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_FEED_SE4BEG2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_FEED_NW2A3", - "INT_INTERFACE_NW2A3" + "CLK_FEED_EE2BEG1", + "INT_INTERFACE_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "INT_INTERFACE_EE2BEG2" ], [ - "CLK_FEED_WW2END1", - "INT_INTERFACE_WW2END1" + "CLK_FEED_EE2BEG3", + "INT_INTERFACE_EE2BEG3" ], [ - "CLK_FEED_NE4BEG3", - "INT_INTERFACE_NE4BEG3" + "CLK_FEED_EE4A0", + "INT_INTERFACE_EE4A0" ], [ - "CLK_FEED_WW2A1", - "INT_INTERFACE_WW2A1" + "CLK_FEED_EE4A1", + "INT_INTERFACE_EE4A1" ], [ - "CLK_FEED_EE4BEG3", - "INT_INTERFACE_EE4BEG3" + "CLK_FEED_EE4A2", + "INT_INTERFACE_EE4A2" ], [ - "CLK_FEED_NE4BEG0", - "INT_INTERFACE_NE4BEG0" + "CLK_FEED_EE4A3", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_FEED_EE4B0", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_FEED_EE4B1", + "INT_INTERFACE_EE4B1" + ], + [ + "CLK_FEED_EE4B2", + "INT_INTERFACE_EE4B2" + ], + [ + "CLK_FEED_EE4B3", + "INT_INTERFACE_EE4B3" ], [ "CLK_FEED_EE4BEG0", "INT_INTERFACE_EE4BEG0" ], [ - "CLK_FEED_WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_FEED_SE2A2", - "INT_INTERFACE_SE2A2" + "CLK_FEED_EE4BEG1", + "INT_INTERFACE_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "INT_INTERFACE_EE4BEG2" ], [ - "CLK_FEED_SW4A2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_FEED_NW2A0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_FEED_NW4A0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_FEED_LH10", - "INT_INTERFACE_LH10" + "CLK_FEED_EE4BEG3", + "INT_INTERFACE_EE4BEG3" ], [ "CLK_FEED_EE4C0", "INT_INTERFACE_EE4C0" ], [ - "CLK_FEED_EE2A3", - "INT_INTERFACE_EE2A3" - ] - ] - }, - { - "grid_deltas": [ - -1, - -5 - ], - "tile_types": [ - "GTP_CHANNEL_1", - "VBRK_EXT" - ], - "wire_pairs": [ + "CLK_FEED_EE4C1", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_FEED_EE4C2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_FEED_EE4C3", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_FEED_EL1BEG0", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_FEED_EL1BEG1", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_FEED_EL1BEG2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_FEED_EL1BEG3", + "INT_INTERFACE_EL1BEG3" + ], + [ + "CLK_FEED_ER1BEG0", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_FEED_ER1BEG1", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_FEED_ER1BEG2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_FEED_ER1BEG3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_FEED_LH1", + "INT_INTERFACE_LH1" + ], + [ + "CLK_FEED_LH2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_FEED_LH3", + "INT_INTERFACE_LH3" + ], + [ + "CLK_FEED_LH4", + "INT_INTERFACE_LH4" + ], + [ + "CLK_FEED_LH5", + "INT_INTERFACE_LH5" + ], + [ + "CLK_FEED_LH6", + "INT_INTERFACE_LH6" + ], + [ + "CLK_FEED_LH7", + "INT_INTERFACE_LH7" + ], + [ + "CLK_FEED_LH8", + "INT_INTERFACE_LH8" + ], + [ + "CLK_FEED_LH9", + "INT_INTERFACE_LH9" + ], [ - "GTPE2_FAN0_10", - "VBRK_EXT_FAN0" + "CLK_FEED_LH10", + "INT_INTERFACE_LH10" ], [ - "GTPE2_IMUX9_10", - "VBRK_EXT_IMUX9" + "CLK_FEED_LH11", + "INT_INTERFACE_LH11" ], [ - "GTPE2_BYP7_10", - "VBRK_EXT_BYP7" + "CLK_FEED_LH12", + "INT_INTERFACE_LH12" ], [ - "GTPE2_IMUX17_10", - "VBRK_EXT_IMUX17" + "CLK_FEED_MONITOR_N", + "INT_INTERFACE_MONITOR_N" ], [ - "GTPE2_IMUX18_10", - "VBRK_EXT_IMUX18" + "CLK_FEED_MONITOR_P", + "INT_INTERFACE_MONITOR_P" ], [ - "GTPE2_IMUX34_10", - "VBRK_EXT_IMUX34" + "CLK_FEED_NE2A0", + "INT_INTERFACE_NE2A0" ], [ - "GTPE2_IMUX20_10", - "VBRK_EXT_IMUX20" + "CLK_FEED_NE2A1", + "INT_INTERFACE_NE2A1" ], [ - "GTPE2_IMUX8_10", - "VBRK_EXT_IMUX8" + "CLK_FEED_NE2A2", + "INT_INTERFACE_NE2A2" ], [ - "GTPE2_IMUX21_10", - "VBRK_EXT_IMUX21" + "CLK_FEED_NE2A3", + "INT_INTERFACE_NE2A3" ], [ - "GTPE2_IMUX0_10", - "VBRK_EXT_IMUX0" + "CLK_FEED_NE4BEG0", + "INT_INTERFACE_NE4BEG0" ], [ - "GTPE2_LOGIC_OUTS_B16_10", - "VBRK_EXT_LOGIC_OUTS_B16" + "CLK_FEED_NE4BEG1", + "INT_INTERFACE_NE4BEG1" ], [ - "GTPE2_CLK0_10", - "VBRK_EXT_CLK0" + "CLK_FEED_NE4BEG2", + "INT_INTERFACE_NE4BEG2" ], [ - "GTPE2_IMUX10_10", - "VBRK_EXT_IMUX10" + "CLK_FEED_NE4BEG3", + "INT_INTERFACE_NE4BEG3" ], [ - "GTPE2_FAN3_10", - "VBRK_EXT_FAN3" + "CLK_FEED_NE4C0", + "INT_INTERFACE_NE4C0" ], [ - "GTPE2_IMUX23_10", - "VBRK_EXT_IMUX23" + "CLK_FEED_NE4C1", + "INT_INTERFACE_NE4C1" ], [ - "GTPE2_IMUX42_10", - "VBRK_EXT_IMUX42" + "CLK_FEED_NE4C2", + "INT_INTERFACE_NE4C2" ], [ - "GTPE2_BYP5_10", - "VBRK_EXT_BYP5" + "CLK_FEED_NE4C3", + "INT_INTERFACE_NE4C3" ], [ - "GTPE2_BYP6_10", - "VBRK_EXT_BYP6" + "CLK_FEED_NW2A0", + "INT_INTERFACE_NW2A0" ], [ - "GTPE2_IMUX27_10", - "VBRK_EXT_IMUX27" + "CLK_FEED_NW2A1", + "INT_INTERFACE_NW2A1" ], [ - "GTPE2_IMUX26_10", - "VBRK_EXT_IMUX26" + "CLK_FEED_NW2A2", + "INT_INTERFACE_NW2A2" ], [ - "GTPE2_IMUX31_10", - "VBRK_EXT_IMUX31" + "CLK_FEED_NW2A3", + "INT_INTERFACE_NW2A3" ], [ - "GTPE2_IMUX12_10", - "VBRK_EXT_IMUX12" + "CLK_FEED_NW4A0", + "INT_INTERFACE_NW4A0" ], [ - "GTPE2_IMUX25_10", - "VBRK_EXT_IMUX25" + "CLK_FEED_NW4A1", + "INT_INTERFACE_NW4A1" ], [ - "GTPE2_LOGIC_OUTS_B5_10", - "VBRK_EXT_LOGIC_OUTS_B5" + "CLK_FEED_NW4A2", + "INT_INTERFACE_NW4A2" ], [ - "GTPE2_IMUX4_10", - "VBRK_EXT_IMUX4" + "CLK_FEED_NW4A3", + "INT_INTERFACE_NW4A3" ], [ - "GTPE2_BYP2_10", - "VBRK_EXT_BYP2" + "CLK_FEED_NW4END0", + "INT_INTERFACE_NW4END0" ], [ - "GTPE2_IMUX19_10", - "VBRK_EXT_IMUX19" + "CLK_FEED_NW4END1", + "INT_INTERFACE_NW4END1" ], [ - "GTPE2_IMUX7_10", - "VBRK_EXT_IMUX7" + "CLK_FEED_NW4END2", + "INT_INTERFACE_NW4END2" ], [ - "GTPE2_LOGIC_OUTS_B23_10", - "VBRK_EXT_LOGIC_OUTS_B23" + "CLK_FEED_NW4END3", + "INT_INTERFACE_NW4END3" ], [ - "GTPE2_FAN4_10", - "VBRK_EXT_FAN4" + "CLK_FEED_SE2A0", + "INT_INTERFACE_SE2A0" ], [ - "GTPE2_CTRL1_10", - "VBRK_EXT_CTRL1" + "CLK_FEED_SE2A1", + "INT_INTERFACE_SE2A1" ], [ - "GTPE2_CLK1_10", - "VBRK_EXT_CLK1" + "CLK_FEED_SE2A2", + "INT_INTERFACE_SE2A2" ], [ - "GTPE2_BYP4_10", - "VBRK_EXT_BYP4" + "CLK_FEED_SE2A3", + "INT_INTERFACE_SE2A3" ], [ - "GTPE2_LOGIC_OUTS_B14_10", - "VBRK_EXT_LOGIC_OUTS_B14" + "CLK_FEED_SE4BEG0", + "INT_INTERFACE_SE4BEG0" ], [ - "GTPE2_LOGIC_OUTS_B3_10", - "VBRK_EXT_LOGIC_OUTS_B3" + "CLK_FEED_SE4BEG1", + "INT_INTERFACE_SE4BEG1" ], [ - "GTPE2_IMUX6_10", - "VBRK_EXT_IMUX6" + "CLK_FEED_SE4BEG2", + "INT_INTERFACE_SE4BEG2" ], [ - "GTPE2_IMUX3_10", - "VBRK_EXT_IMUX3" + "CLK_FEED_SE4BEG3", + "INT_INTERFACE_SE4BEG3" ], [ - "GTPE2_IMUX1_10", - "VBRK_EXT_IMUX1" + "CLK_FEED_SE4C0", + "INT_INTERFACE_SE4C0" ], [ - "GTPE2_IMUX35_10", - "VBRK_EXT_IMUX35" + "CLK_FEED_SE4C1", + "INT_INTERFACE_SE4C1" ], [ - "GTPE2_BYP1_10", - "VBRK_EXT_BYP1" + "CLK_FEED_SE4C2", + "INT_INTERFACE_SE4C2" ], [ - "GTPE2_IMUX47_10", - "VBRK_EXT_IMUX47" + "CLK_FEED_SE4C3", + "INT_INTERFACE_SE4C3" ], [ - "GTPE2_FAN1_10", - "VBRK_EXT_FAN1" + "CLK_FEED_SW2A0", + "INT_INTERFACE_SW2A0" ], [ - "GTPE2_IMUX14_10", - "VBRK_EXT_IMUX14" + "CLK_FEED_SW2A1", + "INT_INTERFACE_SW2A1" ], [ - "GTPE2_IMUX43_10", - "VBRK_EXT_IMUX43" + "CLK_FEED_SW2A2", + "INT_INTERFACE_SW2A2" ], [ - "GTPE2_LOGIC_OUTS_B13_10", - "VBRK_EXT_LOGIC_OUTS_B13" + "CLK_FEED_SW2A3", + "INT_INTERFACE_SW2A3" ], [ - "GTPE2_IMUX32_10", - "VBRK_EXT_IMUX32" + "CLK_FEED_SW4A0", + "INT_INTERFACE_SW4A0" ], [ - "GTPE2_LOGIC_OUTS_B11_10", - "VBRK_EXT_LOGIC_OUTS_B11" + "CLK_FEED_SW4A1", + "INT_INTERFACE_SW4A1" ], [ - "GTPE2_IMUX13_10", - "VBRK_EXT_IMUX13" + "CLK_FEED_SW4A2", + "INT_INTERFACE_SW4A2" ], [ - "GTPE2_IMUX36_10", - "VBRK_EXT_IMUX36" + "CLK_FEED_SW4A3", + "INT_INTERFACE_SW4A3" ], [ - "GTPE2_CTRL0_10", - "VBRK_EXT_CTRL0" + "CLK_FEED_SW4END0", + "INT_INTERFACE_SW4END0" ], [ - "GTPE2_BYP0_10", - "VBRK_EXT_BYP0" + "CLK_FEED_SW4END1", + "INT_INTERFACE_SW4END1" ], [ - "GTPE2_IMUX40_10", - "VBRK_EXT_IMUX40" + "CLK_FEED_SW4END2", + "INT_INTERFACE_SW4END2" ], [ - "GTPE2_BYP3_10", - "VBRK_EXT_BYP3" + "CLK_FEED_SW4END3", + "INT_INTERFACE_SW4END3" ], [ - "GTPE2_IMUX37_10", - "VBRK_EXT_IMUX37" + "CLK_FEED_WL1END0", + "INT_INTERFACE_WL1END0" ], [ - "GTPE2_FAN6_10", - "VBRK_EXT_FAN6" + "CLK_FEED_WL1END1", + "INT_INTERFACE_WL1END1" ], [ - "GTPE2_IMUX33_10", - "VBRK_EXT_IMUX33" + "CLK_FEED_WL1END2", + "INT_INTERFACE_WL1END2" ], [ - "GTPE2_IMUX30_10", - "VBRK_EXT_IMUX30" + "CLK_FEED_WL1END3", + "INT_INTERFACE_WL1END3" ], [ - "GTPE2_LOGIC_OUTS_B9_10", - "VBRK_EXT_LOGIC_OUTS_B9" + "CLK_FEED_WR1END0", + "INT_INTERFACE_WR1END0" ], [ - "GTPE2_LOGIC_OUTS_B6_10", - "VBRK_EXT_LOGIC_OUTS_B6" + "CLK_FEED_WR1END1", + "INT_INTERFACE_WR1END1" ], [ - "GTPE2_IMUX16_10", - "VBRK_EXT_IMUX16" + "CLK_FEED_WR1END2", + "INT_INTERFACE_WR1END2" ], [ - "GTPE2_IMUX45_10", - "VBRK_EXT_IMUX45" + "CLK_FEED_WR1END3", + "INT_INTERFACE_WR1END3" ], [ - "GTPE2_LOGIC_OUTS_B1_10", - "VBRK_EXT_LOGIC_OUTS_B1" + "CLK_FEED_WW2A0", + "INT_INTERFACE_WW2A0" ], [ - "GTPE2_IMUX28_10", - "VBRK_EXT_IMUX28" + "CLK_FEED_WW2A1", + "INT_INTERFACE_WW2A1" ], [ - "GTPE2_IMUX39_10", - "VBRK_EXT_IMUX39" + "CLK_FEED_WW2A2", + "INT_INTERFACE_WW2A2" ], [ - "GTPE2_IMUX15_10", - "VBRK_EXT_IMUX15" + "CLK_FEED_WW2A3", + "INT_INTERFACE_WW2A3" ], [ - "GTPE2_FAN2_10", - "VBRK_EXT_FAN2" + "CLK_FEED_WW2END0", + "INT_INTERFACE_WW2END0" ], [ - "GTPE2_IMUX2_10", - "VBRK_EXT_IMUX2" + "CLK_FEED_WW2END1", + "INT_INTERFACE_WW2END1" ], [ - "GTPE2_IMUX11_10", - "VBRK_EXT_IMUX11" + "CLK_FEED_WW2END2", + "INT_INTERFACE_WW2END2" ], [ - "GTPE2_IMUX5_10", - "VBRK_EXT_IMUX5" + "CLK_FEED_WW2END3", + "INT_INTERFACE_WW2END3" ], [ - "GTPE2_FAN5_10", - "VBRK_EXT_FAN5" + "CLK_FEED_WW4A0", + "INT_INTERFACE_WW4A0" ], [ - "GTPE2_IMUX44_10", - "VBRK_EXT_IMUX44" + "CLK_FEED_WW4A1", + "INT_INTERFACE_WW4A1" ], [ - "GTPE2_IMUX29_10", - "VBRK_EXT_IMUX29" + "CLK_FEED_WW4A2", + "INT_INTERFACE_WW4A2" ], [ - "GTPE2_LOGIC_OUTS_B12_10", - "VBRK_EXT_LOGIC_OUTS_B12" + "CLK_FEED_WW4A3", + "INT_INTERFACE_WW4A3" ], [ - "GTPE2_LOGIC_OUTS_B2_10", - "VBRK_EXT_LOGIC_OUTS_B2" + "CLK_FEED_WW4B0", + "INT_INTERFACE_WW4B0" ], [ - "GTPE2_LOGIC_OUTS_B4_10", - "VBRK_EXT_LOGIC_OUTS_B4" + "CLK_FEED_WW4B1", + "INT_INTERFACE_WW4B1" ], [ - "GTPE2_IMUX22_10", - "VBRK_EXT_IMUX22" + "CLK_FEED_WW4B2", + "INT_INTERFACE_WW4B2" ], [ - "GTPE2_IMUX46_10", - "VBRK_EXT_IMUX46" + "CLK_FEED_WW4B3", + "INT_INTERFACE_WW4B3" ], [ - "GTPE2_LOGIC_OUTS_B22_10", - "VBRK_EXT_LOGIC_OUTS_B22" + "CLK_FEED_WW4C0", + "INT_INTERFACE_WW4C0" ], [ - "GTPE2_IMUX24_10", - "VBRK_EXT_IMUX24" + "CLK_FEED_WW4C1", + "INT_INTERFACE_WW4C1" ], [ - "GTPE2_LOGIC_OUTS_B19_10", - "VBRK_EXT_LOGIC_OUTS_B19" + "CLK_FEED_WW4C2", + "INT_INTERFACE_WW4C2" ], [ - "GTPE2_LOGIC_OUTS_B17_10", - "VBRK_EXT_LOGIC_OUTS_B17" + "CLK_FEED_WW4C3", + "INT_INTERFACE_WW4C3" ], [ - "GTPE2_LOGIC_OUTS_B0_10", - "VBRK_EXT_LOGIC_OUTS_B0" + "CLK_FEED_WW4END0", + "INT_INTERFACE_WW4END0" ], [ - "GTPE2_FAN7_10", - "VBRK_EXT_FAN7" + "CLK_FEED_WW4END1", + "INT_INTERFACE_WW4END1" ], [ - "GTPE2_IMUX38_10", - "VBRK_EXT_IMUX38" + "CLK_FEED_WW4END2", + "INT_INTERFACE_WW4END2" ], [ - "GTPE2_IMUX41_10", - "VBRK_EXT_IMUX41" + "CLK_FEED_WW4END3", + "INT_INTERFACE_WW4END3" ] ] }, @@ -133417,129 +126273,215589 @@ 0 ], "tile_types": [ - "HCLK_DSP_L", + "CLK_FEED", + "VBRK" + ], + "wire_pairs": [ + [ + "CLK_FEED_EE2A0", + "VBRK_EE2A0" + ], + [ + "CLK_FEED_EE2A1", + "VBRK_EE2A1" + ], + [ + "CLK_FEED_EE2A2", + "VBRK_EE2A2" + ], + [ + "CLK_FEED_EE2A3", + "VBRK_EE2A3" + ], + [ + "CLK_FEED_EE2BEG0", + "VBRK_EE2BEG0" + ], + [ + "CLK_FEED_EE2BEG1", + "VBRK_EE2BEG1" + ], + [ + "CLK_FEED_EE2BEG2", + "VBRK_EE2BEG2" + ], + [ + "CLK_FEED_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLK_FEED_EE4A0", + "VBRK_EE4A0" + ], + [ + "CLK_FEED_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLK_FEED_EE4A2", + "VBRK_EE4A2" + ], + [ + "CLK_FEED_EE4A3", + "VBRK_EE4A3" + ], + [ + "CLK_FEED_EE4B0", + "VBRK_EE4B0" + ], + [ + "CLK_FEED_EE4B1", + "VBRK_EE4B1" + ], + [ + "CLK_FEED_EE4B2", + "VBRK_EE4B2" + ], + [ + "CLK_FEED_EE4B3", + "VBRK_EE4B3" + ], + [ + "CLK_FEED_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLK_FEED_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLK_FEED_EE4BEG2", + "VBRK_EE4BEG2" + ], + [ + "CLK_FEED_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLK_FEED_EE4C0", + "VBRK_EE4C0" + ], + [ + "CLK_FEED_EE4C1", + "VBRK_EE4C1" + ], + [ + "CLK_FEED_EE4C2", + "VBRK_EE4C2" + ], + [ + "CLK_FEED_EE4C3", + "VBRK_EE4C3" + ], + [ + "CLK_FEED_EL1BEG0", + "VBRK_EL1BEG0" + ], + [ + "CLK_FEED_EL1BEG1", + "VBRK_EL1BEG1" + ], + [ + "CLK_FEED_EL1BEG2", + "VBRK_EL1BEG2" + ], + [ + "CLK_FEED_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLK_FEED_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLK_FEED_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLK_FEED_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLK_FEED_ER1BEG3", + "VBRK_ER1BEG3" + ], + [ + "CLK_FEED_LH1", + "VBRK_LH1" + ], + [ + "CLK_FEED_LH2", + "VBRK_LH2" + ], + [ + "CLK_FEED_LH3", + "VBRK_LH3" + ], + [ + "CLK_FEED_LH4", + "VBRK_LH4" + ], + [ + "CLK_FEED_LH5", + "VBRK_LH5" + ], + [ + "CLK_FEED_LH6", + "VBRK_LH6" + ], + [ + "CLK_FEED_LH7", + "VBRK_LH7" + ], + [ + "CLK_FEED_LH8", + "VBRK_LH8" + ], + [ + "CLK_FEED_LH9", + "VBRK_LH9" + ], + [ + "CLK_FEED_LH10", + "VBRK_LH10" + ], + [ + "CLK_FEED_LH11", + "VBRK_LH11" + ], + [ + "CLK_FEED_LH12", + "VBRK_LH12" + ], + [ + "CLK_FEED_MONITOR_N", + "VBRK_MONITOR_N" + ], + [ + "CLK_FEED_MONITOR_P", + "VBRK_MONITOR_P" + ], + [ + "CLK_FEED_NE2A0", + "VBRK_NE2A0" + ], + [ + "CLK_FEED_NE2A1", + "VBRK_NE2A1" + ], + [ + "CLK_FEED_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLK_FEED_NE2A3", + "VBRK_NE2A3" + ], + [ + "CLK_FEED_NE4BEG0", + "VBRK_NE4BEG0" + ], + [ + "CLK_FEED_NE4BEG1", + "VBRK_NE4BEG1" + ], + [ + "CLK_FEED_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLK_FEED_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLK_FEED_NE4C0", + "VBRK_NE4C0" + ], + [ + "CLK_FEED_NE4C1", + "VBRK_NE4C1" + ], + [ + "CLK_FEED_NE4C2", + "VBRK_NE4C2" + ], + [ + "CLK_FEED_NE4C3", + "VBRK_NE4C3" + ], + [ + "CLK_FEED_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLK_FEED_NW2A1", + "VBRK_NW2A1" + ], + [ + "CLK_FEED_NW2A2", + "VBRK_NW2A2" + ], + [ + "CLK_FEED_NW2A3", + "VBRK_NW2A3" + ], + [ + "CLK_FEED_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLK_FEED_NW4A1", + "VBRK_NW4A1" + ], + [ + "CLK_FEED_NW4A2", + "VBRK_NW4A2" + ], + [ + "CLK_FEED_NW4A3", + "VBRK_NW4A3" + ], + [ + "CLK_FEED_NW4END0", + "VBRK_NW4END0" + ], + [ + "CLK_FEED_NW4END1", + "VBRK_NW4END1" + ], + [ + "CLK_FEED_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLK_FEED_NW4END3", + "VBRK_NW4END3" + ], + [ + "CLK_FEED_SE2A0", + "VBRK_SE2A0" + ], + [ + "CLK_FEED_SE2A1", + "VBRK_SE2A1" + ], + [ + "CLK_FEED_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLK_FEED_SE2A3", + "VBRK_SE2A3" + ], + [ + "CLK_FEED_SE4BEG0", + "VBRK_SE4BEG0" + ], + [ + "CLK_FEED_SE4BEG1", + "VBRK_SE4BEG1" + ], + [ + "CLK_FEED_SE4BEG2", + "VBRK_SE4BEG2" + ], + [ + "CLK_FEED_SE4BEG3", + "VBRK_SE4BEG3" + ], + [ + "CLK_FEED_SE4C0", + "VBRK_SE4C0" + ], + [ + "CLK_FEED_SE4C1", + "VBRK_SE4C1" + ], + [ + "CLK_FEED_SE4C2", + "VBRK_SE4C2" + ], + [ + "CLK_FEED_SE4C3", + "VBRK_SE4C3" + ], + [ + "CLK_FEED_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLK_FEED_SW2A1", + "VBRK_SW2A1" + ], + [ + "CLK_FEED_SW2A2", + "VBRK_SW2A2" + ], + [ + "CLK_FEED_SW2A3", + "VBRK_SW2A3" + ], + [ + "CLK_FEED_SW4A0", + "VBRK_SW4A0" + ], + [ + "CLK_FEED_SW4A1", + "VBRK_SW4A1" + ], + [ + "CLK_FEED_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLK_FEED_SW4A3", + "VBRK_SW4A3" + ], + [ + "CLK_FEED_SW4END0", + "VBRK_SW4END0" + ], + [ + "CLK_FEED_SW4END1", + "VBRK_SW4END1" + ], + [ + "CLK_FEED_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLK_FEED_SW4END3", + "VBRK_SW4END3" + ], + [ + "CLK_FEED_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLK_FEED_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLK_FEED_WL1END2", + "VBRK_WL1END2" + ], + [ + "CLK_FEED_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLK_FEED_WR1END0", + "VBRK_WR1END0" + ], + [ + "CLK_FEED_WR1END1", + "VBRK_WR1END1" + ], + [ + "CLK_FEED_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLK_FEED_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLK_FEED_WW2A0", + "VBRK_WW2A0" + ], + [ + "CLK_FEED_WW2A1", + "VBRK_WW2A1" + ], + [ + "CLK_FEED_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLK_FEED_WW2A3", + "VBRK_WW2A3" + ], + [ + "CLK_FEED_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLK_FEED_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLK_FEED_WW2END2", + "VBRK_WW2END2" + ], + [ + "CLK_FEED_WW2END3", + "VBRK_WW2END3" + ], + [ + "CLK_FEED_WW4A0", + "VBRK_WW4A0" + ], + [ + "CLK_FEED_WW4A1", + "VBRK_WW4A1" + ], + [ + "CLK_FEED_WW4A2", + "VBRK_WW4A2" + ], + [ + "CLK_FEED_WW4A3", + "VBRK_WW4A3" + ], + [ + "CLK_FEED_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLK_FEED_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLK_FEED_WW4B2", + "VBRK_WW4B2" + ], + [ + "CLK_FEED_WW4B3", + "VBRK_WW4B3" + ], + [ + "CLK_FEED_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLK_FEED_WW4C1", + "VBRK_WW4C1" + ], + [ + "CLK_FEED_WW4C2", + "VBRK_WW4C2" + ], + [ + "CLK_FEED_WW4C3", + "VBRK_WW4C3" + ], + [ + "CLK_FEED_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLK_FEED_WW4END1", + "VBRK_WW4END1" + ], + [ + "CLK_FEED_WW4END2", + "VBRK_WW4END2" + ], + [ + "CLK_FEED_WW4END3", + "VBRK_WW4END3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "CLK_HROW_BOT_R", "HCLK_INT_INTERFACE" ], "wire_pairs": [ [ - "HCLK_DSP_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN7" - ], - [ - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], - [ - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "HCLK_DSP_CK_IN3", - "HCLK_INT_INTERFACE_CK_IN3" - ], - [ - "HCLK_DSP_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN11" - ], - [ - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "HCLK_DSP_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN5" - ], - [ - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_DSP_CK_BUFHCLK0", + "CLK_HROW_CK_BUFHCLK_L0", "HCLK_INT_INTERFACE_CK_BUFHCLK0" ], [ - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" + "CLK_HROW_CK_BUFHCLK_L1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" ], [ - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" + "CLK_HROW_CK_BUFHCLK_L2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" ], [ - "HCLK_DSP_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN10" + "CLK_HROW_CK_BUFHCLK_L3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" ], [ - "HCLK_DSP_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "HCLK_DSP_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN8" - ], - [ - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "HCLK_DSP_CK_BUFHCLK4", + "CLK_HROW_CK_BUFHCLK_L4", "HCLK_INT_INTERFACE_CK_BUFHCLK4" ], [ - "HCLK_DSP_CK_BUFHCLK10", + "CLK_HROW_CK_BUFHCLK_L5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "CLK_HROW_CK_BUFHCLK_L6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "CLK_HROW_CK_BUFHCLK_L7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "CLK_HROW_CK_BUFHCLK_L8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "CLK_HROW_CK_BUFHCLK_L9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "CLK_HROW_CK_BUFHCLK_L10", "HCLK_INT_INTERFACE_CK_BUFHCLK10" ], [ - "HCLK_DSP_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN9" + "CLK_HROW_CK_BUFHCLK_L11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" ], [ - "HCLK_DSP_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN13" + "CLK_HROW_CK_BUFRCLK_L0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" ], [ - "HCLK_DSP_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN4" + "CLK_HROW_CK_BUFRCLK_L1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" ], [ - "HCLK_DSP_CK_BUFRCLK2", + "CLK_HROW_CK_BUFRCLK_L2", "HCLK_INT_INTERFACE_CK_BUFRCLK2" ], [ - "HCLK_DSP_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN0" - ], - [ - "HCLK_DSP_CK_BUFRCLK3", + "CLK_HROW_CK_BUFRCLK_L3", "HCLK_INT_INTERFACE_CK_BUFRCLK3" ], [ - "HCLK_DSP_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN6" + "CLK_HROW_CK_IN_L0", + "HCLK_INT_INTERFACE_CK_IN0" ], [ - "HCLK_DSP_CK_IN2", + "CLK_HROW_CK_IN_L1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "CLK_HROW_CK_IN_L2", "HCLK_INT_INTERFACE_CK_IN2" ], [ - "HCLK_DSP_CK_IN1", + "CLK_HROW_CK_IN_L3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "CLK_HROW_CK_IN_L4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "CLK_HROW_CK_IN_L5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "CLK_HROW_CK_IN_L6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "CLK_HROW_CK_IN_L7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "CLK_HROW_CK_IN_L8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "CLK_HROW_CK_IN_L9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "CLK_HROW_CK_IN_L10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "CLK_HROW_CK_IN_L11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "CLK_HROW_CK_IN_L12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "CLK_HROW_CK_IN_L13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "CLK_HROW_CK_BUFHCLK_R0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "CLK_HROW_CK_BUFHCLK_R1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "CLK_HROW_CK_BUFHCLK_R2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "CLK_HROW_CK_BUFHCLK_R3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "CLK_HROW_CK_BUFHCLK_R4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "CLK_HROW_CK_BUFHCLK_R5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "CLK_HROW_CK_BUFHCLK_R6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "CLK_HROW_CK_BUFHCLK_R7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "CLK_HROW_CK_BUFHCLK_R8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "CLK_HROW_CK_BUFHCLK_R9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "CLK_HROW_CK_BUFHCLK_R10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "CLK_HROW_CK_BUFHCLK_R11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "CLK_HROW_CK_BUFRCLK_R0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "CLK_HROW_CK_BUFRCLK_R1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "CLK_HROW_CK_BUFRCLK_R2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "CLK_HROW_CK_BUFRCLK_R3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "CLK_HROW_CK_IN_R0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "CLK_HROW_CK_IN_R1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "CLK_HROW_CK_IN_R2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "CLK_HROW_CK_IN_R3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "CLK_HROW_CK_IN_R4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "CLK_HROW_CK_IN_R5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "CLK_HROW_CK_IN_R6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "CLK_HROW_CK_IN_R7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "CLK_HROW_CK_IN_R8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "CLK_HROW_CK_IN_R9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "CLK_HROW_CK_IN_R10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "CLK_HROW_CK_IN_R11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "CLK_HROW_CK_IN_R12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "CLK_HROW_CK_IN_R13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "tile_types": [ + "CLK_HROW_BOT_R", + "INT_INTERFACE_R" + ], + "wire_pairs": [ + [ + "CLK_HROW_BYP0_7", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_BYP1_7", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_BYP2_7", + "INT_INTERFACE_BYP2" + ], + [ + "CLK_HROW_BYP3_7", + "INT_INTERFACE_BYP3" + ], + [ + "CLK_HROW_BYP4_7", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_BYP5_7", + "INT_INTERFACE_BYP5" + ], + [ + "CLK_HROW_BYP6_7", + "INT_INTERFACE_BYP6" + ], + [ + "CLK_HROW_BYP7_7", + "INT_INTERFACE_BYP7" + ], + [ + "CLK_HROW_CLK0_7", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_CLK1_7", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_CTRL0_7", + "INT_INTERFACE_CTRL0" + ], + [ + "CLK_HROW_CTRL1_7", + "INT_INTERFACE_CTRL1" + ], + [ + "CLK_HROW_EE2A0_7", + "INT_INTERFACE_EE2A0" + ], + [ + "CLK_HROW_EE2A1_7", + "INT_INTERFACE_EE2A1" + ], + [ + "CLK_HROW_EE2A2_7", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_EE2A3_7", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_EE2BEG0_7", + "INT_INTERFACE_EE2BEG0" + ], + [ + "CLK_HROW_EE2BEG1_7", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_EE2BEG2_7", + "INT_INTERFACE_EE2BEG2" + ], + [ + "CLK_HROW_EE2BEG3_7", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_EE4A0_7", + "INT_INTERFACE_EE4A0" + ], + [ + "CLK_HROW_EE4A1_7", + "INT_INTERFACE_EE4A1" + ], + [ + "CLK_HROW_EE4A2_7", + "INT_INTERFACE_EE4A2" + ], + [ + "CLK_HROW_EE4A3_7", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_EE4B0_7", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_EE4B1_7", + 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"CLK_HROW_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_SE2A2_3", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4C1_3", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_LH2_3", - "VBRK_LH2" - ], - [ - "CLK_HROW_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SW2A0_3", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_LH9_3", - "VBRK_LH9" - ], - [ - "CLK_HROW_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW4C2_3", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_LH7_3", - "VBRK_LH7" - ], - [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_LH1_3", - "VBRK_LH1" - ], - [ - "CLK_HROW_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_LH11_3", - "VBRK_LH11" - ], - [ - "CLK_HROW_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_LH10_3", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH8_3", - "VBRK_LH8" - ], - [ - "CLK_HROW_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_LH6_3", - "VBRK_LH6" - ], - [ - "CLK_HROW_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_LH12_3", - "VBRK_LH12" - ], - [ - "CLK_HROW_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WL1END2_3", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_LH5_3", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW4B1_3", - "VBRK_WW4B1" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "DSP_L", - "HCLK_DSP_L" - ], - "wire_pairs": [ - [ - "DSP_PCOUT20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_ACOUT14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_PCOUT8", - "HCLK_DSP_PCIN8" - ], - [ - "DSP_PCOUT41", - "HCLK_DSP_PCIN41" - ], - [ - "DSP_PCOUT25", - "HCLK_DSP_PCIN25" - ], - [ - "DSP_ACOUT17", - "HCLK_DSP_ACIN17" - ], - [ - "DSP_BCOUT2", - "HCLK_DSP_BCIN2" - ], - [ - "DSP_PCOUT26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_ACOUT27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_ACOUT19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_BCOUT4", - "HCLK_DSP_BCIN4" - ], - [ - "DSP_BCOUT17", - "HCLK_DSP_BCIN17" - ], - [ - "DSP_BCOUT11", - "HCLK_DSP_BCIN11" - ], - [ - "DSP_PCOUT19", - "HCLK_DSP_PCIN19" - ], - [ - "DSP_PCOUT30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_ACOUT7", - "HCLK_DSP_ACIN7" - ], - [ - "DSP_ACOUT8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_PCOUT39", - "HCLK_DSP_PCIN39" - ], - [ - "DSP_PCOUT17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_PCOUT29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_ACOUT28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_PCOUT40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_PCOUT23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_PCOUT6", - "HCLK_DSP_PCIN6" - ], - [ - "DSP_PCOUT0", - "HCLK_DSP_PCIN0" - ], - [ - "DSP_ACOUT24", - "HCLK_DSP_ACIN24" - ], - [ - "DSP_ACOUT12", - "HCLK_DSP_ACIN12" - ], - [ - "DSP_BCOUT13", - "HCLK_DSP_BCIN13" - ], - [ - "DSP_PCOUT27", - "HCLK_DSP_PCIN27" - ], - [ - "DSP_PCOUT3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_ACOUT1", - "HCLK_DSP_ACIN1" - ], - [ - "DSP_PCOUT24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_PCOUT28", - "HCLK_DSP_PCIN28" - ], - [ - "DSP_PCOUT43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_ACOUT21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_PCOUT15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_PCOUT1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_PCOUT33", - "HCLK_DSP_PCIN33" - ], - [ - "DSP_BCOUT10", - "HCLK_DSP_BCIN10" - ], - [ - "DSP_ACOUT9", - "HCLK_DSP_ACIN9" - ], - [ - "DSP_PCOUT9", - "HCLK_DSP_PCIN9" - ], - [ - "DSP_BCOUT16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_BCOUT0", - "HCLK_DSP_BCIN0" - ], - [ - "DSP_PCOUT12", - "HCLK_DSP_PCIN12" - ], - [ - "DSP_ACOUT29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_PCOUT46", - "HCLK_DSP_PCIN46" - ], - [ - "DSP_PCOUT36", - "HCLK_DSP_PCIN36" - ], - [ - "DSP_ACOUT26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_ACOUT23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_PCOUT35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_PCOUT16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_ACOUT25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_PCOUT13", - "HCLK_DSP_PCIN13" - ], - [ - "DSP_PCOUT44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_BCOUT5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_CARRYCASCOUT", - "HCLK_DSP_CARRYCASCIN" - ], - [ - "DSP_MULTSIGNOUT", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_PCOUT22", - "HCLK_DSP_PCIN22" - ], - [ - "DSP_ACOUT15", - "HCLK_DSP_ACIN15" - ], - [ - "DSP_ACOUT18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_ACOUT13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_BCOUT3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_PCOUT7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_ACOUT2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_ACOUT11", - "HCLK_DSP_ACIN11" - ], - [ - "DSP_BCOUT8", - "HCLK_DSP_BCIN8" - ], - [ - "DSP_ACOUT6", - "HCLK_DSP_ACIN6" - ], - [ - "DSP_ACOUT10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_BCOUT12", - "HCLK_DSP_BCIN12" - ], - [ - "DSP_BCOUT6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_BCOUT1", - "HCLK_DSP_BCIN1" - ], - [ - "DSP_PCOUT18", - "HCLK_DSP_PCIN18" - ], - [ - "DSP_PCOUT2", - "HCLK_DSP_PCIN2" - ], - [ - "DSP_PCOUT32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_PCOUT38", - "HCLK_DSP_PCIN38" - ], - [ - "DSP_ACOUT22", - "HCLK_DSP_ACIN22" - ], - [ - "DSP_PCOUT5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_PCOUT21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_PCOUT34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_BCOUT9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_BCOUT15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_BCOUT14", - "HCLK_DSP_BCIN14" - ], - [ - "DSP_ACOUT0", - "HCLK_DSP_ACIN0" - ], - [ - "DSP_PCOUT11", - "HCLK_DSP_PCIN11" - ], - [ - "DSP_BCOUT7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_PCOUT10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_PCOUT42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_ACOUT20", - "HCLK_DSP_ACIN20" - ], - [ - "DSP_PCOUT4", - "HCLK_DSP_PCIN4" - ], - [ - "DSP_PCOUT45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_PCOUT14", - "HCLK_DSP_PCIN14" - ], - [ - "DSP_ACOUT3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_PCOUT47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_ACOUT4", - "HCLK_DSP_ACIN4" - ], - [ - "DSP_PCOUT31", - "HCLK_DSP_PCIN31" - ], - [ - "DSP_PCOUT37", - "HCLK_DSP_PCIN37" - ], - [ - "DSP_ACOUT5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_ACOUT16", - "HCLK_DSP_ACIN16" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "LIOB33", - "LIOI3" - ], - "wire_pairs": [ - [ - "IOB_T1", - "LIOI_T1" - ], - [ - "IOB_IBUF0", - "LIOI_IBUF0" - ], - [ - "IOB_DIFF_TERM_INT_EN", - "LIOI_DIFF_TERM_INT_EN" - ], - [ - "IOB_PD_INT_EN_0", - "LIOI_PD_INT_EN_0" - ], - [ - "IOB_IBUF_DISABLE1", - "LIOI_IBUF_DISABLE1" - ], - [ - "IOB_PD_INT_EN_1", - "LIOI_PD_INT_EN_1" - ], - [ - "LIOB_IN_TERM0", - "LIOI_DCI_T_TERM0" - ], - [ - "IOB_KEEPER_INT_EN_1", - "LIOI_KEEPER_INT_EN_1" - ], - [ - "IOB_O1", - "LIOI_O1" - ], - [ - "LIOB_IN_TERM1", - "LIOI_DCI_T_TERM1" - ], - [ - "IOB_IBUF_DISABLE0", - "LIOI_IBUF_DISABLE0" - ], - [ - "IOB_PU_INT_EN_0", - "LIOI_PU_INT_EN_0" - ], - [ - "LIOB_MONITOR_N", - "IOI_MONITOR_N" - ], - [ - "IOB_IBUF1", - "LIOI_IBUF1" - ], - [ - "IOB_PU_INT_EN_1", - "LIOI_PU_INT_EN_1" - ], - [ - "IOB_KEEPER_INT_EN_0", - "LIOI_KEEPER_INT_EN_0" - ], - [ - "IOB_O0", - "LIOI_O0" - ], - [ - "LIOB_MONITOR_P", - "IOI_MONITOR_P" - ], - [ - "IOB_T0", - "LIOI_T0" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "PCIE_INT_INTERFACE_R", - "PCIE_TOP" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_BYP0", - "PCIE_BYP0_R_0" - ], - [ - "INT_INTERFACE_CTRL1", - "PCIE_CTRL1_R_0" - ], - [ - "INT_INTERFACE_CLK0", - "PCIE_CLK0_R_0" - ], - [ - "INT_INTERFACE_NW2A2", - "PCIE_NW2A2_0" - ], - [ - "INT_INTERFACE_NE2A3", - "PCIE_NE2A3_0" - ], - [ - "INT_INTERFACE_WW4C3", - "PCIE_WW4C3_0" - ], - [ - "INT_INTERFACE_WW2A2", - "PCIE_WW2A2_0" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT43", - "PCIE_IMUX43_R_0" - ], - [ - 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"VBRK_LH11" - ], - [ - "CMT_TOP_NW4A0_10", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_NE2A1_10", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_SW4END0_10", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_LH1_10", - "VBRK_LH1" - ], - [ - "CMT_TOP_NW4A3_10", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_EE2A0_10", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_WW4B3_10", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WW4B0_10", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_EE2BEG2_10", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_WW4C3_10", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_WW4B2_10", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_WW2A0_10", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_LH2_10", - "VBRK_LH2" - ], - [ - "CMT_TOP_EE2BEG1_10", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_ER1BEG2_10", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_WL1END2_10", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_LH12_10", - "VBRK_LH12" - ], - [ - "CMT_TOP_WW2A3_10", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE2A2_10", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_EE4B2_10", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_WW2END3_10", - "VBRK_WW2END3" - ], - [ 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"CLK_BUFG_IMUX35_2", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_BUFG_IMUX3_2", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_FAN7_2", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_BYP5_2", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_EE2BEG0_2", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_BUFG_IMUX42_2", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_LH3_2", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_BUFG_IMUX44_2", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_BUFG_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_BUFG_IMUX20_2", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_LH12_2", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WR1END1_2", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_BUFG_IMUX19_2", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ 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], - [ - "CLK_HROW_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_BUFG_IMUX18_2", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_2", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_BUFG_IMUX46_2", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_BUFG_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_FAN5_2", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_2", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_HROW_ER1BEG2_2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_NW4END2_2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_NE4C1_2", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_2", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_HROW_SE4C0_2", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_WW2A2_2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_2", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_SE2A0_2", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SW4END1_2", - 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"CLK_BUFG_IMUX27_2", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_IMUX33_2", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_WW2A1_2", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_SE4C1_2", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_FAN1_2", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_LH1_2", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_EE4BEG0_2", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4END3_2", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EE4BEG3_2", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_SW2A1_2", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_BUFG_IMUX32_2", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_BUFG_IMUX9_2", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_WL1END2_2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_NE2A3_2", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_LH2_2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_LH9_2", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_EE4A0_2", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_BUFG_IMUX37_2", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4C3_2", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_LH6_2", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_SE4BEG3_2", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE4BEG2_2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_BYP0_2", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_BUFG_IMUX26_2", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_BYP1_2", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_BUFG_IMUX13_2", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_BUFG_IMUX31_2", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX47_2", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_NE2A1_2", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_BUFG_IMUX12_2", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_SE4BEG0_2", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_IMUX16_2", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_BUFG_IMUX39_2", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SE4C2_2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_WR1END3_2", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_FAN3_2", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_EE2A2_2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE2A0_2", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE2A1_2", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_WW4B2_2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_NE2A2_2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_SW2A3_2", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_BUFG_IMUX8_2", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WW2END0_2", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "CLK_BUFG_IMUX7_2", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_BUFG_IMUX15_2", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_FAN0_2", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_EE4B2_2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_2", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_WW4A2_2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_WW4END1_2", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_WW4END2_2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_SE4BEG1_2", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_WW4B0_2", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_BUFG_IMUX40_2", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_ER1BEG0_2", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_EE2BEG3_2", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_2", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_WL1END0_2", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_EE4C2_2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_EE4A2_2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_FAN2_2", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_EL1BEG2_2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW4A0_2", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NW4END3_2", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_NW4A1_2", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_EE4B1_2", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SW4A2_2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_CTRL1_2", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP7_2", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_BYP4_2", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_BUFG_IMUX29_2", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_BUFG_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_BUFG_IMUX30_2", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_WW4END3_2", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_NE4BEG2_2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_WR1END2_2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_BUFG_IMUX21_2", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_SE2A1_2", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_CLK0_2", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW2END3_2", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW2END2_2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_SW2A0_2", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_BUFG_IMUX2_2", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_BUFG_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "CLK_BUFG_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_SE2A2_2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_LH5_2", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_WR1END0_2", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE4BEG1_2", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_BUFG_IMUX24_2", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_FAN4_2", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_2", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_BUFG_IMUX43_2", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_NW4END0_2", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_WW4C1_2", - "INT_INTERFACE_WW4C1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "DSP_L", - "VBRK" - ], - "wire_pairs": [ - [ - "DSP_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "DSP_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "DSP_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "DSP_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "DSP_MONITOR_N_0", - "VBRK_MONITOR_N" - ], - [ - "DSP_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "DSP_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "DSP_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "DSP_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "DSP_EE4A2_0", - "VBRK_EE4A2" - ], - [ - "DSP_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "DSP_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "DSP_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "DSP_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "DSP_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "DSP_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "DSP_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "DSP_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "DSP_LH11_0", - "VBRK_LH11" - ], - [ - "DSP_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "DSP_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "DSP_LH7_0", - "VBRK_LH7" - ], - [ - "DSP_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "DSP_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "DSP_NW4A1_0", - "VBRK_NW4A1" - ], - [ - "DSP_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "DSP_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "DSP_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "DSP_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "DSP_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "DSP_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "DSP_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "DSP_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "DSP_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "DSP_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "DSP_LH10_0", - "VBRK_LH10" - ], - [ - "DSP_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "DSP_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "DSP_LH12_0", - "VBRK_LH12" - ], - [ - "DSP_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "DSP_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "DSP_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "DSP_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "DSP_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "DSP_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "DSP_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "DSP_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "DSP_MONITOR_P_0", - "VBRK_MONITOR_P" - ], - [ - "DSP_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "DSP_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "DSP_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "DSP_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "DSP_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "DSP_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "DSP_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "DSP_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "DSP_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "DSP_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "DSP_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "DSP_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "DSP_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "DSP_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "DSP_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "DSP_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "DSP_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "DSP_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "DSP_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "DSP_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "DSP_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "DSP_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "DSP_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "DSP_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "DSP_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "DSP_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "DSP_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "DSP_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "DSP_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "DSP_LH1_0", - "VBRK_LH1" - ], - [ - "DSP_LH9_0", - "VBRK_LH9" - ], - [ - "DSP_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "DSP_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "DSP_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "DSP_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "DSP_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "DSP_LH2_0", - "VBRK_LH2" - ], - [ - "DSP_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "DSP_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "DSP_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "DSP_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "DSP_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "DSP_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "DSP_LH5_0", - "VBRK_LH5" - ], - [ - "DSP_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "DSP_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "DSP_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "DSP_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "DSP_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "DSP_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "DSP_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "DSP_LH6_0", - "VBRK_LH6" - ], - [ - "DSP_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "DSP_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "DSP_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "DSP_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "DSP_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "DSP_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "DSP_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "DSP_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "DSP_LH8_0", - "VBRK_LH8" - ], - [ - "DSP_LH3_0", - "VBRK_LH3" - ], - [ - "DSP_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "DSP_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "DSP_LH4_0", - "VBRK_LH4" - ], - [ - "DSP_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "DSP_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "DSP_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "DSP_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "DSP_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "DSP_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "DSP_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "DSP_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "DSP_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "DSP_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "DSP_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "DSP_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "DSP_EE4C1_0", - "VBRK_EE4C1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "DSP_L", - "VBRK" - ], - "wire_pairs": [ - [ - "DSP_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "DSP_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "DSP_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "DSP_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "DSP_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "DSP_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "DSP_LH3_4", - "VBRK_LH3" - ], - [ - "DSP_LH12_4", - "VBRK_LH12" - ], - [ - "DSP_LH4_4", - "VBRK_LH4" - ], - [ - "DSP_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "DSP_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "DSP_LH6_4", - "VBRK_LH6" - ], - [ - "DSP_SE2A1_4", - "VBRK_SE2A1" - ], - [ - "DSP_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "DSP_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "DSP_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "DSP_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "DSP_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "DSP_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "DSP_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "DSP_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "DSP_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "DSP_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "DSP_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "DSP_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "DSP_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "DSP_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "DSP_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "DSP_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "DSP_EE4C0_4", - "VBRK_EE4C0" - ], - [ - "DSP_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "DSP_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "DSP_LH10_4", - "VBRK_LH10" - ], - [ - "DSP_LH2_4", - "VBRK_LH2" - ], - [ - "DSP_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "DSP_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "DSP_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "DSP_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "DSP_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "DSP_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "DSP_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "DSP_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "DSP_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "DSP_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "DSP_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "DSP_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "DSP_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "DSP_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "DSP_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "DSP_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "DSP_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "DSP_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "DSP_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "DSP_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "DSP_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "DSP_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "DSP_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "DSP_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "DSP_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "DSP_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "DSP_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "DSP_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "DSP_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "DSP_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "DSP_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "DSP_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "DSP_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "DSP_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "DSP_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "DSP_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "DSP_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "DSP_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "DSP_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "DSP_LH1_4", - "VBRK_LH1" - ], - [ - "DSP_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "DSP_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "DSP_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "DSP_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "DSP_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "DSP_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "DSP_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "DSP_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "DSP_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "DSP_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "DSP_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "DSP_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "DSP_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "DSP_LH5_4", - "VBRK_LH5" - ], - [ - "DSP_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "DSP_LH8_4", - "VBRK_LH8" - ], - [ - "DSP_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "DSP_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "DSP_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "DSP_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "DSP_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "DSP_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "DSP_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "DSP_LH7_4", - "VBRK_LH7" - ], - [ - "DSP_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "DSP_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "DSP_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "DSP_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "DSP_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "DSP_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "DSP_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "DSP_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "DSP_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "DSP_LH11_4", - "VBRK_LH11" - ], - [ - "DSP_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "DSP_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "DSP_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "DSP_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "DSP_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "DSP_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "DSP_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "DSP_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "DSP_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "DSP_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "DSP_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "DSP_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "DSP_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "DSP_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "DSP_LH9_4", - "VBRK_LH9" - ], - [ - "DSP_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "DSP_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "DSP_SE4C1_4", - "VBRK_SE4C1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_IOB", - "HCLK_IOI3" - ], - "wire_pairs": [ - [ - "HCLK_IOB_CK_BUFHCLK8", - "HCLK_IOI_CK_BUFHCLK8" - ], - [ - "HCLK_IOB_PERFCLK3", - "HCLK_IOI_IOCLK_PLL3" - ], - [ - "HCLK_IOB_CK_BUFHCLK6", - "HCLK_IOI_CK_BUFHCLK6" - ], - [ - "HCLK_IOB_PERFCLK2", - "HCLK_IOI_IOCLK_PLL2" - ], - [ - "HCLK_IOB_CK_BUFHCLK2", - "HCLK_IOI_CK_BUFHCLK2" - ], - [ - "HCLK_IOB_CK_BUFRCLK1", - "HCLK_IOI_CK_BUFRCLK1" - ], - [ - "HCLK_IOB_CK_BUFHCLK3", - "HCLK_IOI_CK_BUFHCLK3" - ], - [ - "HCLK_IOB_CK_BUFHCLK9", - "HCLK_IOI_CK_BUFHCLK9" - ], - [ - "HCLK_IOB_CK_BUFHCLK10", - "HCLK_IOI_CK_BUFHCLK10" - ], - [ - "HCLK_IOB_PERFCLK0", - "HCLK_IOI_IOCLK_PLL0" - ], - [ - "HCLK_IOB_CK_BUFHCLK11", - "HCLK_IOI_CK_BUFHCLK11" - ], - [ - "HCLK_IOB_CK_BUFRCLK0", - "HCLK_IOI_CK_BUFRCLK0" - ], - [ - "HCLK_IOB_CK_BUFHCLK0", - "HCLK_IOI_CK_BUFHCLK0" - ], - [ - "HCLK_IOB_CK_BUFHCLK1", - "HCLK_IOI_CK_BUFHCLK1" - ], - [ - "HCLK_IOB_CK_BUFRCLK3", - "HCLK_IOI_CK_BUFRCLK3" - ], - [ - "HCLK_IOB_CK_BUFHCLK7", - "HCLK_IOI_CK_BUFHCLK7" - ], - [ - "HCLK_IOB_CK_BUFRCLK2", - "HCLK_IOI_CK_BUFRCLK2" - ], - [ - "HCLK_IOB_CK_BUFHCLK4", - "HCLK_IOI_CK_BUFHCLK4" - ], - [ - "HCLK_IOB_PERFCLK1", - "HCLK_IOI_IOCLK_PLL1" - ], - [ - "HCLK_IOB_CK_BUFHCLK5", - "HCLK_IOI_CK_BUFHCLK5" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "BRAM_R", - "HCLK_BRAM" - ], - "wire_pairs": [ - [ - "BRAM_CASCINBOT_ADDRARDADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" - ], - [ - "BRAM_FIFO36_CASCADEINA", - "HCLK_BRAM_CASCADEA_R" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" - ], - [ - "BRAM_PMVBRAM_SELECT1", - "HCLK_BRAM_PMVBRAM_SELECT1" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" - ], - [ - "BRAM_PMVBRAM_ODIV4", - "HCLK_BRAM_PMVBRAM_ODIV4" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" - ], - [ - "BRAM_PMVBRAM_ODIV2", - "HCLK_BRAM_PMVBRAM_ODIV2" - ], - [ - "BRAM_PMVBRAM_SELECT2", - "HCLK_BRAM_PMVBRAM_SELECT2" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" - ], - [ - "BRAM_PMVBRAM_SELECT3", - "HCLK_BRAM_PMVBRAM_SELECT3" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" - ], - [ - "BRAM_PMVBRAM_SELECT4", - "HCLK_BRAM_PMVBRAM_SELECT4" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" - ], - [ - "BRAM_FIFO36_CASCADEINB", - "HCLK_BRAM_CASCADEB_R" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" - ], - [ - "BRAM_PMVBRAM_O", - "HCLK_BRAM_PMVBRAM_O" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "DSP_L", - "VBRK" - ], - "wire_pairs": [ - [ - "DSP_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "DSP_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "DSP_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "DSP_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "DSP_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "DSP_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "DSP_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "DSP_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "DSP_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "DSP_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "DSP_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "DSP_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "DSP_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "DSP_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "DSP_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "DSP_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "DSP_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "DSP_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "DSP_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "DSP_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "DSP_LH12_2", - "VBRK_LH12" - ], - [ - "DSP_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "DSP_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "DSP_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "DSP_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "DSP_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "DSP_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "DSP_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "DSP_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "DSP_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "DSP_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "DSP_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "DSP_LH9_2", - "VBRK_LH9" - ], - [ - "DSP_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "DSP_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "DSP_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "DSP_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "DSP_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "DSP_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "DSP_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "DSP_LH10_2", - "VBRK_LH10" - ], - [ - "DSP_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "DSP_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "DSP_LH2_2", - "VBRK_LH2" - ], - [ - "DSP_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "DSP_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "DSP_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "DSP_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "DSP_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "DSP_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "DSP_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "DSP_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "DSP_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "DSP_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "DSP_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "DSP_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "DSP_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "DSP_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "DSP_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "DSP_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "DSP_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "DSP_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "DSP_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "DSP_LH3_2", - "VBRK_LH3" - ], - [ - "DSP_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "DSP_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "DSP_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "DSP_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "DSP_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "DSP_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "DSP_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "DSP_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "DSP_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "DSP_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "DSP_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "DSP_LH4_2", - "VBRK_LH4" - ], - [ - "DSP_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "DSP_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "DSP_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "DSP_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "DSP_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "DSP_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "DSP_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "DSP_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "DSP_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "DSP_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "DSP_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "DSP_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "DSP_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "DSP_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "DSP_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "DSP_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "DSP_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "DSP_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "DSP_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "DSP_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "DSP_LH1_2", - "VBRK_LH1" - ], - [ - "DSP_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "DSP_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "DSP_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "DSP_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "DSP_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "DSP_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "DSP_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "DSP_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "DSP_LH8_2", - "VBRK_LH8" - ], - [ - "DSP_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "DSP_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "DSP_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "DSP_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "DSP_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "DSP_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "DSP_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "DSP_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "DSP_LH6_2", - "VBRK_LH6" - ], - [ - "DSP_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "DSP_LH5_2", - "VBRK_LH5" - ], - [ - "DSP_LH11_2", - "VBRK_LH11" - ], - [ - "DSP_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "DSP_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "DSP_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "DSP_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "DSP_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "DSP_LH7_2", - "VBRK_LH7" - ], - [ - "DSP_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "DSP_EE4BEG2_2", - "VBRK_EE4BEG2" - ] - ] - }, - { - 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] - }, - { - "grid_deltas": [ - -1, - 6 - ], - "tile_types": [ - "CFG_CENTER_MID", - "HCLK_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "CFG_CENTER_CK_IN10", - "HCLK_FEEDTHRU_2_CK_IN10" - ], - [ - "CFG_CENTER_CK_IN1", - "HCLK_FEEDTHRU_2_CK_IN1" - ], - [ - "CFG_CENTER_CK_BUFHCLK7", - "HCLK_FEEDTHRU_2_CK_BUFHCLK7" - ], - [ - "CFG_CENTER_CK_IN2", - "HCLK_FEEDTHRU_2_CK_IN2" - ], - [ - "CFG_CENTER_CK_IN9", - "HCLK_FEEDTHRU_2_CK_IN9" - ], - [ - "CFG_CENTER_CK_IN0", - "HCLK_FEEDTHRU_2_CK_IN0" - ], - [ - "CFG_CENTER_CK_BUFHCLK0", - "HCLK_FEEDTHRU_2_CK_BUFHCLK0" - ], - [ - "CFG_CENTER_CK_BUFHCLK11", - "HCLK_FEEDTHRU_2_CK_BUFHCLK11" - ], - [ - "CFG_CENTER_CK_BUFHCLK6", - "HCLK_FEEDTHRU_2_CK_BUFHCLK6" - ], - [ - "CFG_CENTER_CK_IN11", - "HCLK_FEEDTHRU_2_CK_IN11" - ], - [ - "CFG_CENTER_CK_BUFHCLK9", - "HCLK_FEEDTHRU_2_CK_BUFHCLK9" - ], - [ - "CFG_CENTER_CK_BUFHCLK2", - "HCLK_FEEDTHRU_2_CK_BUFHCLK2" - ], - [ - "CFG_CENTER_CK_IN5", - "HCLK_FEEDTHRU_2_CK_IN5" - ], - [ - "CFG_CENTER_CK_IN6", - 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"NW6C0" - ], - [ - "B_TERM_UTURN_INT_SE6D2", - "NE6E1" - ], - [ - "B_TERM_UTURN_INT_SE6D0", - "SE6D0" - ], - [ - "B_TERM_UTURN_INT_SE6D0", - "NE6E3" - ], - [ - "B_TERM_UTURN_INT_SE2BEG2", - "NE2A1" - ], - [ - "B_TERM_UTURN_INT_SW6A3", - "SW6A3" - ], - [ - "B_TERM_UTURN_INT_SW2BEG0", - "NW2A3" - ], - [ - "B_TERM_UTURN_INT_SS6D2", - "SS6D2" - ], - [ - "B_TERM_UTURN_INT_SS2A2", - "NN2END1" - ], - [ - "B_TERM_UTURN_INT_SS2BEG3", - "NN2A0" - ], - [ - "B_TERM_UTURN_INT_SE6B1", - "NE6C2" - ], - [ - "HCLK_LEAF_CLK_B_TOPL5", - "GCLK_L_B11" - ], - [ - "B_TERM_UTURN_INT_LV_L18", - "LV_L1" - ], - [ - "B_TERM_UTURN_INT_SL1BEG2", - "NR1END1" - ], - [ - "B_TERM_UTURN_INT_SE6C1", - "NE6D2" - ], - [ - "B_TERM_UTURN_INT_SS6BEG1", - "NN6A2" - ], - [ - "B_TERM_UTURN_INT_SW6A2", - "SW6A2" - ], - [ - "B_TERM_UTURN_INT_SW6B0", - "SW6B0" - ], - [ - "B_TERM_UTURN_INT_LV_L18", - "LV_L18" - ], - [ - "B_TERM_UTURN_INT_LVB_L4", - "LVB_L5" - ], - [ - "B_TERM_UTURN_INT_LVB_L2", - "LVB_L3" - ], - [ - "B_TERM_UTURN_INT_SE6A1", - "SE6A1" - ], - [ - "B_TERM_UTURN_INT_LVB_L4", - "LVB_L8" - ], - [ - "B_TERM_UTURN_INT_SS6D0", - "SS6D0" - ], - [ - "B_TERM_UTURN_INT_ER1BEG0", - "EL1BEG_N3" - ], - [ - "B_TERM_UTURN_INT_SR1BEG3", - "NL1END0" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "BYP_BOUNCE_N3_6" - ], - [ - "B_TERM_UTURN_INT_SS6BEG2", - "NN6A1" - ], - [ - "B_TERM_UTURN_INT_WR1BEG0", - "WL1BEG_N3" - ], - [ - "B_TERM_UTURN_INT_SL1BEG2", - "SL1BEG2" - ], - [ - "B_TERM_UTURN_INT_LV_L7", - "LV_L7" - ], - [ - "B_TERM_UTURN_INT_SS6D3", - "NN6E0" - ], - [ - "B_TERM_UTURN_INT_SE6C2", - "SE6C2" - ], - [ - "B_TERM_UTURN_INT_SL1BEG0", - "SL1BEG0" - ], - [ - "B_TERM_UTURN_INT_SE6A3", - "NE6B0" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "BYP_BOUNCE_N3_2" - ], - [ - "B_TERM_UTURN_INT_SS6C3", - "NN6D0" - ], - [ - "B_TERM_UTURN_INT_SS2A0", - "SS2A0" - ], - [ - "B_TERM_UTURN_INT_SS6BEG0", - "SS6BEG0" - ], - [ - "B_TERM_UTURN_INT_SS2BEG0", - "NN2A3" - ], - [ - "B_TERM_UTURN_INT_SE6A2", - "NE6B1" - ], - [ - "B_TERM_UTURN_INT_SE2BEG0", - "SE2BEG0" - ], - [ - "B_TERM_UTURN_INT_LV_L4", - "LV_L15" - ], - [ - "B_TERM_UTURN_INT_SE6C0", - "SE6C0" - ], - [ - "B_TERM_UTURN_INT_SW6A1", - "NW6B2" - ], - [ - "B_TERM_UTURN_INT_SS2A3", - "SS2A3" - ], - [ - "B_TERM_UTURN_INT_SE6D1", - "SE6D1" - ], - [ - "B_TERM_UTURN_INT_SW6END_N0_3", - "SW6END_N0_3" - ], - [ - "B_TERM_UTURN_INT_SE6B1", - "SE6B1" - ], - [ - "B_TERM_UTURN_INT_SW6C2", - "NW6D1" - ], - [ - "B_TERM_UTURN_INT_SW2BEG3", - "SW2BEG3" - ], - [ - "B_TERM_UTURN_INT_SE2BEG3", - "NE2A0" - ], - [ - "B_TERM_UTURN_INT_SS6D0", - "NN6E3" - ], - [ - "B_TERM_UTURN_INT_SE6D2", - "SE6D2" - ], - [ - "B_TERM_UTURN_INT_SW6D3", - "NW6E0" - ], - [ - "B_TERM_UTURN_INT_SS2A1", - "NN2END2" - ], - [ - "B_TERM_UTURN_INT_SS6D1", - "NN6E2" - ], - [ - "B_TERM_UTURN_INT_SW6D3", - "SW6D3" - ], - [ - "B_TERM_UTURN_INT_SS6B1", - "NN6C2" - ], - [ - "B_TERM_UTURN_INT_SE6B0", - "SE6B0" - ], - [ - "B_TERM_UTURN_INT_SS6C1", - "NN6D2" - ], - [ - "B_TERM_UTURN_INT_SS6A0", - "NN6B3" - ], - [ - "B_TERM_UTURN_INT_WR1BEG0", - "WR1BEG0" - ], - [ - "B_TERM_UTURN_INT_LV_L9", - "LV_L9" - ], - [ - "B_TERM_UTURN_INT_SS6C2", - "SS6C2" - ], - [ - "B_TERM_UTURN_INT_SS6C0", - "SS6C0" - ], - [ - "B_TERM_UTURN_INT_SR1BEG1", - "NL1END2" - ], - [ - "B_TERM_UTURN_INT_SW6C3", - "NW6D0" - ], - [ - "B_TERM_UTURN_INT_LVB_L0", - "LVB_L12" - ], - [ - "B_TERM_UTURN_INT_SW6C0", - "SW6C0" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "FAN_BOUNCE6" - ], - [ - "B_TERM_UTURN_INT_SS6E2", - "NN6END1" - ], - [ - "B_TERM_UTURN_INT_SW6C1", - "NW6D2" - ], - [ - "B_TERM_UTURN_INT_SR1BEG2", - "SR1BEG2" - ], - [ - "B_TERM_UTURN_INT_SW6D1", - "SW6D1" - ], - [ - "HCLK_LEAF_CLK_B_TOPL2", - "GCLK_L_B8" - ], - [ - "B_TERM_UTURN_INT_LVB_L1", - "LVB_L2" - ], - [ - "HCLK_LEAF_CLK_B_TOPL0", - "GCLK_L_B6" - ], - [ - "B_TERM_UTURN_INT_SW6C3", - "SW6C3" - ], - [ - "B_TERM_UTURN_INT_SS6B2", - "SS6B2" - ], - [ - "B_TERM_UTURN_INT_LVB_L1", - "LVB_L11" - ], - [ - "B_TERM_UTURN_INT_SS6B0", - "NN6C3" - ], - [ - "B_TERM_UTURN_INT_SS2BEG2", - "NN2A1" - ], - [ - "B_TERM_UTURN_INT_SS6A2", - "SS6A2" - ], - [ - "B_TERM_UTURN_INT_LV_L5", - "LV_L5" - ], - [ - "B_TERM_UTURN_INT_SS2A1", - "SS2A1" - ], - [ - "B_TERM_UTURN_INT_SS6E0", - "SS6E0" - ], - [ - "B_TERM_UTURN_INT_SS6A0", - "SS6A0" - ], - [ - "B_TERM_UTURN_INT_SE6A2", - "SE6A2" - ], - [ - "B_TERM_UTURN_INT_LV_L2", - "LV_L17" - ], - [ - "B_TERM_UTURN_INT_SS2BEG3", - "SS2BEG3" - ], - [ - "B_TERM_UTURN_INT_SS6A1", - "NN6B2" - ], - [ - "B_TERM_UTURN_INT_LVB_L5", - "LVB_L7" - ], - [ - "B_TERM_UTURN_INT_SW2BEG2", - "SW2BEG2" - ], - [ - "B_TERM_UTURN_INT_SW6A0", - "SW6A0" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "HCLK_R", - "INT_R" - ], - "wire_pairs": [ - [ - "HCLK_NE6B1", - "NE6B1" - ], - [ - "HCLK_SW6D2", - "SW6D2" - ], - [ - "HCLK_BYP_BOUNCE3", - "BYP_BOUNCE3" - ], - [ - "HCLK_NW2END_S0_0", - "NW2END_S0_0" - ], - [ - "HCLK_SS2END1", - "SS2END1" - ], - [ - "HCLK_SS6C1", - "SS6C1" - ], - [ - "HCLK_LV6", - "LV6" - ], - [ - "HCLK_LVB4", - "LVB3" - ], - [ - "HCLK_NN2BEG3", - "NN2BEG3" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END3" - ], - [ - "HCLK_NN6C3", - "NN6C3" - ], - [ - "HCLK_SE6D0", - "SE6D0" - ], - [ - "HCLK_SL1END0", - "SL1END0" - ], - [ - "HCLK_NE6A3", - "NE6A3" - ], - [ - "HCLK_SS6A0", - "SS6A0" - ], - [ - "HCLK_SS6D2", - "SS6D2" - ], - [ - "HCLK_SR1END_N3_3", - "SR1END3" - ], - [ - "HCLK_NE6B0", - "NE6B0" - ], - [ - "HCLK_NN6BEG1", - "NN6BEG1" - ], - [ - "HCLK_NE6B2", - "NE6B2" - ], - [ - "HCLK_SS2A0", - "SS2A0" - ], - [ - "HCLK_NN6B2", - "NN6B2" - ], - [ - "HCLK_SW6B0", - "SW6B0" - ], - [ - "HCLK_SS6END_N0_3", - "SS6END3" - ], - [ - "HCLK_NW2A3", - "NW2BEG3" - ], - [ - "HCLK_SW6C1", - "SW6C1" - ], - [ - "HCLK_SW6D1", - "SW6D1" - ], - [ - "HCLK_SE6E2", - "SE6E2" - ], - [ - "HCLK_SS6B2", - "SS6B2" - ], - [ - "HCLK_NN6A0", - "NN6A0" - ], - [ - "HCLK_NE6C1", - "NE6C1" - ], - [ - "HCLK_FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_0" - ], - [ - "HCLK_SE6B0", - "SE6B0" - ], - [ - "HCLK_NW6A0", - "NW6A0" - ], - [ - "HCLK_NE6A0", - "NE6A0" - ], - [ - "HCLK_LVB7", - "LVB6" - ], - [ - "HCLK_LEAF_CLK_B_BOT4", - "GCLK_B4" - ], - [ - "HCLK_SS6D1", - "SS6D1" - ], - [ - "HCLK_SS6END2", - "SS6END2" - ], - [ - "HCLK_SE6D1", - "SE6D1" - ], - [ - "HCLK_SW6E2", - "SW6E2" - ], - [ - "HCLK_NW2A1", - "NW2BEG1" - ], - [ - "HCLK_NW6B2", - "NW6B2" - ], - [ - "HCLK_NL1BEG2", - "NL1BEG2" - ], - [ - "HCLK_SW6C3", - "SW6C3" - ], - [ - "HCLK_NN2A0", - "NN2A0" - ], - [ - "HCLK_SS2END2", - "SS2END2" - ], - [ - "HCLK_SE6E0", - "SE6E0" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE2" - ], - [ - "HCLK_LVB1", - "LVB0" - ], - [ - "HCLK_SS6B0", - "SS6B0" - ], - [ - "HCLK_SE6B2", - "SE6B2" - ], - [ - "HCLK_NN2A1", - "NN2A1" - ], - [ - "HCLK_NW2A0", - "NW2BEG0" - ], - [ - "HCLK_WW4END_S0_0", - "WW4END_S0_0" - ], - [ - "HCLK_SS2END_N0_3", - "SS2END3" - ], - [ - "HCLK_SR1END1", - "SR1END1" - ], - [ - "HCLK_NE6D2", - "NE6D2" - ], - [ - "HCLK_NW6C1", - "NW6C1" - ], - [ - "HCLK_NW6D2", - "NW6D2" - ], - [ - "HCLK_LV5", - "LV5" - ], - [ - "HCLK_SL1END2", - "SL1END2" - ], - [ - "HCLK_LEAF_CLK_B_BOT5", - "GCLK_B5" - ], - [ - "HCLK_LV9", - "LV9" - ], - [ - "HCLK_SS6C3", - "SS6C3" - ], - [ - "HCLK_LV16", - "LV16" - ], - [ - "HCLK_NN6C2", - "NN6C2" - ], - [ - "HCLK_SS6C2", - "SS6C2" - ], - [ - "HCLK_SW2END0", - "SW2A0" - ], - [ - "HCLK_NN6B0", - "NN6B0" - ], - [ - "HCLK_SW6D0", - "SW6D0" - ], - [ - "HCLK_SS6B3", - "SS6B3" - ], - [ - "HCLK_NW6C3", - "NW6C3" - ], - [ - "HCLK_NR1BEG1", - "NR1BEG1" - ], - [ - "HCLK_NN6A2", - "NN6A2" - ], - [ - "HCLK_NE6C3", - "NE6C3" - ], - [ - "HCLK_SS6D3", - "SS6D3" - ], - [ - "HCLK_NW6B1", - "NW6B1" - ], - [ - "HCLK_NW6A2", - "NW6A2" - ], - [ - "HCLK_NW6D0", - "NW6D0" - ], - [ - "HCLK_NE6D3", - "NE6D3" - ], - [ - "HCLK_LVB12", - "LVB11" - ], - [ - "HCLK_SS6END3", - "SS6END3" - ], - [ - "HCLK_NN6B3", - "NN6B3" - ], - [ - "HCLK_LEAF_CLK_B_BOT3", - "GCLK_B3" - ], - [ - "HCLK_WL1BEG3", - "WL1BEG3" - ], - [ - "HCLK_LVB10", - "LVB9" - ], - [ - "HCLK_SS2END0", - "SS2END0" - ], - [ - "HCLK_LV13", - "LV13" - ], - [ - "HCLK_NE6A2", - "NE6A2" - ], - [ - "HCLK_SE6B3", - "SE6B3" - ], - [ - "HCLK_NN6A3", - "NN6A3" - ], - [ - "HCLK_NE2END_S3_0", - "NE2END_S3_0" - ], - [ - "HCLK_NE2BEG1", - "NE2BEG1" - ], - [ - "HCLK_NW6END_S0_0", - "NW6END_S0_0" - ], - [ - "HCLK_SS6C0", - "SS6C0" - ], - [ - "HCLK_LEAF_CLK_B_BOT1", - "GCLK_B1" - ], - [ - "HCLK_NN6E3", - "NN6E3" - ], - [ - "HCLK_ER1END3", - "ER1END3" - ], - [ - "HCLK_SE6C1", - "SE6C1" - ], - [ - "HCLK_SS6B1", - "SS6B1" - ], - [ - "HCLK_NR1BEG0", - "NR1BEG0" - ], - [ - "HCLK_NW6D1", - "NW6D1" - ], - [ - "HCLK_NE2BEG3", - "NE2BEG3" - ], - [ - "HCLK_NN6E0", - "NN6E0" - ], - [ - "HCLK_LV10", - "LV10" - ], - [ - "HCLK_NN6BEG0", - "NN6BEG0" - ], - [ - "HCLK_NN6D3", - "NN6D3" - ], - [ - "HCLK_NN6D1", - "NN6D1" - ], - [ - "HCLK_LEAF_CLK_B_BOT0", - "GCLK_B0" - ], - [ - "HCLK_NN2A2", - "NN2A2" - ], - [ - "HCLK_NW6C2", - "NW6C2" - ], - [ - "HCLK_NN2BEG1", - "NN2BEG1" - ], - [ - "HCLK_LV11", - "LV11" - ], - [ - "HCLK_SW6B1", - "SW6B1" - ], - [ - "HCLK_SW6E1", - "SW6E1" - ], - [ - "HCLK_NE6B3", - "NE6B3" - ], - [ - "HCLK_SR1END2", - "SR1END2" - ], - [ - "HCLK_WL1END3", - "WL1END3" - ], - [ - "HCLK_SL1END3", - "SL1END3" - ], - [ - "HCLK_SS6E0", - "SS6E0" - ], - [ - "HCLK_NW2A2", - "NW2BEG2" - ], - [ - "HCLK_SE6B1", - "SE6B1" - ], - [ - "HCLK_SW6C0", - "SW6C0" - ], - [ - "HCLK_NE6D0", - "NE6D0" - ], - [ - "HCLK_NN6C0", - "NN6C0" - ], - [ - "HCLK_FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_2" - ], - [ - "HCLK_NE6C2", - "NE6C2" - ], - [ - "HCLK_LV1", - "LV1" - ], - [ - "HCLK_LVB3", - "LVB2" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END_S1_0" - ], - [ - "HCLK_LVB5", - "LVB4" - ], - [ - "HCLK_NR1BEG2", - "NR1BEG2" - ], - [ - "HCLK_NE6D1", - "NE6D1" - ], - [ - "HCLK_NN2END_S2_0", - "NN2END_S2_0" - ], - [ - "HCLK_NN6D2", - "NN6D2" - ], - [ - "HCLK_LV7", - "LV7" - ], - [ - "HCLK_NW6C0", - "NW6C0" - ], - [ - "HCLK_SW6E0", - "SW6E0" - ], - [ - "HCLK_LV8", - "LV8" - ], - [ - "HCLK_NN2BEG0", - "NN2BEG0" - ], - [ - "HCLK_SS2A2", - "SS2A2" - ], - [ - "HCLK_SW2END1", - "SW2A1" - ], - [ - "HCLK_SL1END1", - "SL1END1" - ], - [ - "HCLK_SE2A3", - "SE2A3" - ], - [ - "HCLK_NL1BEG0", - "NL1BEG0" - ], - [ - "HCLK_NN6E1", - "NN6E1" - ], - [ - "HCLK_FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_4" - ], - [ - "HCLK_NE6A1", - "NE6A1" - ], - [ - "HCLK_SW6B3", - "SW6B3" - ], - [ - "HCLK_SS6A1", - "SS6A1" - ], - [ - "HCLK_SW6B2", - "SW6B2" - ], - [ - "HCLK_LV17", - "LV17" - ], - [ - "HCLK_NW6A3", - "NW6A3" - ], - [ - "HCLK_SE6E3", - "SE6E3" - ], - [ - "HCLK_SW6END3", - "SW6END3" - ], - [ - "HCLK_NN6A1", - "NN6A1" - ], - [ - "HCLK_SE6C3", - "SE6C3" - ], - [ - "HCLK_LVB6", - "LVB5" - ], - [ - "HCLK_ER1BEG_S0", - "ER1BEG_S0" - ], - [ - "HCLK_SE6C0", - "SE6C0" - ], - [ - "HCLK_SW6D3", - "SW6D3" - ], - [ - "HCLK_SW6E3", - "SW6E3" - ], - [ - "HCLK_NE2BEG2", - "NE2BEG2" - ], - [ - "HCLK_NW6B3", - "NW6B3" - ], - [ - "HCLK_NN6C1", - "NN6C1" - ], - [ - "HCLK_LV3", - "LV3" - ], - [ - "HCLK_SE6D3", - "SE6D3" - ], - [ - "HCLK_SW2END2", - "SW2A2" - ], - [ - "HCLK_NE6C0", - "NE6C0" - ], - [ - "HCLK_LV14", - "LV14" - ], - [ - "HCLK_FAN_BOUNCE_S3_6", - "FAN_BOUNCE_S3_6" - ], - [ - "HCLK_EL1BEG3", - "EL1BEG3" - ], - [ - "HCLK_SS6E1", - "SS6E1" - ], - [ - "HCLK_LV15", - "LV15" - ], - [ - "HCLK_SS2A3", - "SS2END3" - ], - [ - "HCLK_SS6A2", - "SS6A2" - ], - [ - "HCLK_SS6A3", - "SS6A3" - ], - [ - "HCLK_SS2BEG3", - "SS2A3" - ], - [ - "HCLK_NN6B1", - "NN6B1" - ], - [ - "HCLK_NN2BEG2", - "NN2BEG2" - ], - [ - "HCLK_LVB11", - "LVB10" - ], - [ - "HCLK_SS2A1", - "SS2A1" - ], - [ - "HCLK_LV4", - "LV4" - ], - [ - "HCLK_NW6D3", - "NW6D3" - ], - [ - "HCLK_NR1BEG3", - "NR1BEG3" - ], - [ - "HCLK_NE2BEG0", - "NE2BEG0" - ], - [ - "HCLK_NL1BEG1", - "NL1BEG1" - ], - [ - "HCLK_EL1END_S3_0", - "EL1END_S3_0" - ], - [ - "HCLK_LEAF_CLK_B_BOT2", - "GCLK_B2" - ], - [ - "HCLK_BYP_BOUNCE6", - "BYP_BOUNCE6" - ], - [ - "HCLK_BYP_BOUNCE7", - "BYP_BOUNCE7" - ], - [ - "HCLK_NN2A3", - "NN2A3" - ], - [ - "HCLK_SS6D0", - "SS6D0" - ], - [ - "HCLK_SE6E1", - "SE6E1" - ], - [ - "HCLK_SE6D2", - "SE6D2" - ], - [ - "HCLK_NW6B0", - "NW6B0" - ], - [ - "HCLK_NL1END_S3_0", - "NL1END_S3_0" - ], - [ - "HCLK_NN6D0", - "NN6D0" - ], - [ - "HCLK_LVB8", - "LVB7" - ], - [ - "HCLK_SE2A1", - "SE2A1" - ], - [ - "HCLK_SS6END1", - "SS6END1" - ], - [ - "HCLK_LVB9", - "LVB8" - ], - [ - "HCLK_NN6BEG3", - "NN6BEG3" - ], - [ - "HCLK_SE2A0", - "SE2A0" - ], - [ - "HCLK_SS6E2", - "SS6E2" - ], - [ - "HCLK_WR1BEG_S0", - "WR1BEG_S0" - ], - [ - "HCLK_NN6BEG2", - "NN6BEG2" - ], - [ - "HCLK_LV2", - "LV2" - ], - [ - "HCLK_NW6A1", - "NW6A1" - ], - [ - "HCLK_LV12", - "LV12" - ], - [ - "HCLK_SE6C2", - "SE6C2" - ], - [ - "HCLK_SS6END0", - "SS6END0" - ], - [ - "HCLK_SW6C2", - "SW6C2" - ], - [ - "HCLK_SW2A3", - "SW2A3" - ], - [ - "HCLK_SR1BEG3", - "SR1END3" - ], - [ - "HCLK_NN6END_S1_0", - "NN6END_S1_0" - ], - [ - "HCLK_SE2A2", - "SE2A2" - ], - [ - "HCLK_SS6E3", - "SS6E3" - ], - [ - "HCLK_WW2END3", - "WW2END3" - ], - [ - "HCLK_LV0", - "LV0" - ], - [ - "HCLK_NN6E2", - "NN6E2" - ], - [ - "HCLK_LVB2", - "LVB1" - ] - ] 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"INT_INTERFACE_BRAM_IMUX38", - "BRAM_IMUX38_4" - ], - [ - "INT_INTERFACE_BYP5", - "BRAM_BYP5_4" - ], - [ - "INT_INTERFACE_SE4C1", - "BRAM_SE4C1_4" - ], - [ - "INT_INTERFACE_FAN6", - "BRAM_FAN6_4" - ], - [ - "INT_INTERFACE_NW4END0", - "BRAM_NW4END0_4" - ], - [ - "INT_INTERFACE_LH4", - "BRAM_LH4_4" - ], - [ - "INT_INTERFACE_ER1BEG3", - "BRAM_ER1BEG3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX39", - "BRAM_IMUX39_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "BRAM_LOGIC_OUTS_B4_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "BRAM_LOGIC_OUTS_B9_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX24", - "BRAM_IMUX24_4" - ], - [ - "INT_INTERFACE_LH7", - "BRAM_LH7_4" - ], - [ - "INT_INTERFACE_NW2A3", - "BRAM_NW2A3_4" - ], - [ - "INT_INTERFACE_EE4C0", - "BRAM_EE4C0_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "BRAM_LOGIC_OUTS_B18_4" - ], - [ - "INT_INTERFACE_NW2A0", - "BRAM_NW2A0_4" - ], - [ - "INT_INTERFACE_EE4B2", - "BRAM_EE4B2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX35", - "BRAM_IMUX35_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX44", - "BRAM_IMUX44_UTURN_4" - ], - [ - "INT_INTERFACE_NW4A2", - "BRAM_NW4A2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "BRAM_IMUX10_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX20", - "BRAM_IMUX20_4" - ], - [ - "INT_INTERFACE_EE4C1", - "BRAM_EE4C1_4" - ], - [ - "INT_INTERFACE_EE4A2", - "BRAM_EE4A2_4" - ], - [ - "INT_INTERFACE_EE2A3", - "BRAM_EE2A3_4" - ], - [ - "INT_INTERFACE_LH12", - "BRAM_LH12_4" - ], - [ - "INT_INTERFACE_NW4A1", - "BRAM_NW4A1_4" - ], - [ - "INT_INTERFACE_EL1BEG0", - "BRAM_EL1BEG0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX16", - "BRAM_IMUX16_UTURN_4" - ], - [ - "INT_INTERFACE_SW4END0", - "BRAM_SW4END0_4" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "BRAM_LOGIC_OUTS_B0_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX43", - "BRAM_IMUX43_4" - ], - [ - "INT_INTERFACE_EE4BEG3", - "BRAM_EE4BEG3_4" - ], - [ - "INT_INTERFACE_BYP0", - "BRAM_BYP0_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX36", - "BRAM_IMUX36_4" - ], - [ - "INT_INTERFACE_FAN0", - "BRAM_FAN0_4" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "BRAM_LOGIC_OUTS_B20_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX13", - "BRAM_IMUX13_UTURN_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "BRAM_LOGIC_OUTS_B12_4" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_4" - ], - [ - "INT_INTERFACE_EE2BEG3", - "BRAM_EE2BEG3_4" - ], - [ - "INT_INTERFACE_WW4END1", - "BRAM_WW4END1_4" - ], - [ - "INT_INTERFACE_ER1BEG1", - "BRAM_ER1BEG1_4" - ], - [ - "INT_INTERFACE_EE2BEG0", - "BRAM_EE2BEG0_4" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX18", - "BRAM_IMUX18_UTURN_4" - ], - [ - "INT_INTERFACE_SW4A1", - "BRAM_SW4A1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX19", - "BRAM_IMUX19_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "BRAM_IMUX44_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX33", - "BRAM_IMUX33_4" - ], - [ - "INT_INTERFACE_SE4C3", - "BRAM_SE4C3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "BRAM_IMUX17_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "BRAM_LOGIC_OUTS_B19_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX5", - "BRAM_IMUX5_UTURN_4" - ], - [ - "INT_INTERFACE_NE4C3", - "BRAM_NE4C3_4" - ], - [ - "INT_INTERFACE_WW2A1", - "BRAM_WW2A1_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX0", - "BRAM_IMUX0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX0", - "BRAM_IMUX0_UTURN_4" - ], - [ - "INT_INTERFACE_CLK0", - "BRAM_CLK0_4" - ], - [ - "INT_INTERFACE_CTRL0", - "BRAM_CTRL0_4" - ], - [ - "INT_INTERFACE_WL1END2", - "BRAM_WL1END2_4" - ], - [ - "INT_INTERFACE_EE4B3", - "BRAM_EE4B3_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "BRAM_LOGIC_OUTS_B2_4" - ], - [ - "INT_INTERFACE_WR1END1", - "BRAM_WR1END1_4" - ], - [ - "INT_INTERFACE_NW2A2", - "BRAM_NW2A2_4" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "BRAM_LOGIC_OUTS_B8_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_4" - ], - [ - "INT_INTERFACE_EE4C3", - "BRAM_EE4C3_4" - ], - [ - "INT_INTERFACE_WL1END0", - "BRAM_WL1END0_4" - ], - [ - "INT_INTERFACE_SW2A2", - "BRAM_SW2A2_4" - ], - [ - "INT_INTERFACE_CTRL1", - "BRAM_CTRL1_4" - ], - [ - "INT_INTERFACE_BYP3", - "BRAM_BYP3_4" - ], - [ - "INT_INTERFACE_LH6", - "BRAM_LH6_4" - ], - [ - "INT_INTERFACE_EE4A1", - "BRAM_EE4A1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX2", - "BRAM_IMUX2_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX6", - "BRAM_IMUX6_UTURN_4" - ], - [ - "INT_INTERFACE_SE2A1", - "BRAM_SE2A1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX21", - "BRAM_IMUX21_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX17", - "BRAM_IMUX17_UTURN_4" - ], - [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX7", - "BRAM_IMUX7_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX41", - "BRAM_IMUX41_UTURN_4" - ], - [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_4" - ], - [ - "INT_INTERFACE_NE4C1", - "BRAM_NE4C1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX35", - "BRAM_IMUX35_UTURN_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "BRAM_LOGIC_OUTS_B11_4" - ], - [ - "INT_INTERFACE_NE4BEG2", - "BRAM_NE4BEG2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "BRAM_IMUX4_4" - ], - [ - "INT_INTERFACE_EL1BEG2", - "BRAM_EL1BEG2_4" - ], - [ - "INT_INTERFACE_NW4END3", - "BRAM_NW4END3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX19", - "BRAM_IMUX19_4" - ], - [ - "INT_INTERFACE_WW4B2", - "BRAM_WW4B2_4" - ], - [ - "INT_INTERFACE_EE2A0", - "BRAM_EE2A0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX46", - "BRAM_IMUX46_UTURN_4" - ], - [ - "INT_INTERFACE_NE2A3", - "BRAM_NE2A3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "BRAM_IMUX31_4" - ], - [ - "INT_INTERFACE_EE4BEG1", - "BRAM_EE4BEG1_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - "BRAM_IMUX47_4" - ] - ] - }, - { - "grid_deltas": [ - 1, - 1 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH4_3", - "VBRK_LH4" - ], - [ - "CLK_HROW_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_SE2A2_3", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4C1_3", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_LH2_3", - "VBRK_LH2" - ], - [ - "CLK_HROW_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SW2A0_3", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_LH9_3", - "VBRK_LH9" - ], - [ - "CLK_HROW_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW4C2_3", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_LH7_3", - "VBRK_LH7" - ], - [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_LH1_3", - "VBRK_LH1" - ], - [ - "CLK_HROW_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_LH11_3", - "VBRK_LH11" - ], - [ - "CLK_HROW_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_LH10_3", - "VBRK_LH10" - ], - [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH8_3", - "VBRK_LH8" - ], - [ - "CLK_HROW_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_LH6_3", - "VBRK_LH6" - ], - [ - "CLK_HROW_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_LH12_3", - "VBRK_LH12" - ], - [ - "CLK_HROW_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WL1END2_3", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_LH5_3", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW4B1_3", - "VBRK_WW4B1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 1 - ], - "tile_types": [ - "GTP_CHANNEL_0", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTPE2_CLK1_4", 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"INT_INTERFACE_SW4A3", - "BRAM_SW4A3_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "BRAM_LOGIC_OUTS_B1_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX43", - "BRAM_IMUX43_0" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX24", - "BRAM_IMUX24_UTURN_0" - ], - [ - "INT_INTERFACE_LH5", - "BRAM_LH5_0" - ], - [ - "INT_INTERFACE_SW4A1", - "BRAM_SW4A1_0" - ], - [ - "INT_INTERFACE_BYP2", - "BRAM_BYP2_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX7", - "BRAM_IMUX7_UTURN_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "BRAM_LOGIC_OUTS_B13_0" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_0" - ], - [ - "INT_INTERFACE_SW4A0", - "BRAM_SW4A0_0" - ], - [ - "INT_INTERFACE_NE2A2", - "BRAM_NE2A2_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX37", - "BRAM_IMUX37_UTURN_0" - ], - [ - "INT_INTERFACE_EL1BEG2", - "BRAM_EL1BEG2_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX32", - "BRAM_IMUX32_UTURN_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "BRAM_LOGIC_OUTS_B0_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "BRAM_LOGIC_OUTS_B23_0" - ], - [ - "INT_INTERFACE_WW2END2", - "BRAM_WW2END2_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "BRAM_LOGIC_OUTS_B2_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX25", - "BRAM_IMUX25_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_0" - ], - [ - "INT_INTERFACE_SE4C2", - "BRAM_SE4C2_0" - ], - [ - "INT_INTERFACE_BYP6", - "BRAM_BYP6_0" - ], - [ - "INT_INTERFACE_NE4BEG3", - "BRAM_NE4BEG3_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX19", - "BRAM_IMUX19_UTURN_0" - ], - [ - "INT_INTERFACE_CTRL0", - "BRAM_CTRL0_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "BRAM_IMUX32_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_0" - ], - [ - "INT_INTERFACE_SE4C3", - "BRAM_SE4C3_0" - ], - [ - "INT_INTERFACE_SE2A1", - "BRAM_SE2A1_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "BRAM_LOGIC_OUTS_B4_0" - ], - [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX44", - "BRAM_IMUX44_UTURN_0" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_0" - ], - [ - "INT_INTERFACE_EE2A0", - "BRAM_EE2A0_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "BRAM_LOGIC_OUTS_B6_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX29", - "BRAM_IMUX29_UTURN_0" - ], - [ - "INT_INTERFACE_FAN0", - "BRAM_FAN0_0" - ], - [ - "INT_INTERFACE_WW2A0", - "BRAM_WW2A0_0" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_0" - ], - [ - "INT_INTERFACE_NE2A0", - "BRAM_NE2A0_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX9", - "BRAM_IMUX9_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX43", - "BRAM_IMUX43_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX42", - "BRAM_IMUX42_UTURN_0" - ], - [ - "INT_INTERFACE_SE4BEG1", - "BRAM_SE4BEG1_0" - ], - [ - "INT_INTERFACE_EE4BEG2", - "BRAM_EE4BEG2_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "BRAM_LOGIC_OUTS_B16_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX12", - "BRAM_IMUX12_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX18", - "BRAM_IMUX18_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX36", - "BRAM_IMUX36_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX15", - "BRAM_IMUX15_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX18", - "BRAM_IMUX18_0" - ], - [ - "INT_INTERFACE_SW4A2", - "BRAM_SW4A2_0" - ], - [ - "INT_INTERFACE_NW2A0", - "BRAM_NW2A0_0" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "BRAM_IMUX44_0" - ], - [ - "INT_INTERFACE_EE4C2", - "BRAM_EE4C2_0" - ], - [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_0" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_0" - ], - [ - "INT_INTERFACE_WW4B1", - "BRAM_WW4B1_0" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_0" - ], - [ - "INT_INTERFACE_EE4B1", - "BRAM_EE4B1_0" - ], - [ - "INT_INTERFACE_NE2A1", - "BRAM_NE2A1_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX36", - "BRAM_IMUX36_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "BRAM_IMUX10_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX23", - "BRAM_IMUX23_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX10", - "BRAM_IMUX10_0" - ], - [ - "INT_INTERFACE_EE2A3", - "BRAM_EE2A3_0" - ], - [ - "INT_INTERFACE_EE4BEG3", - "BRAM_EE4BEG3_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX13", - "BRAM_IMUX13_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "BRAM_LOGIC_OUTS_B17_0" - ] - ] - }, - { - "grid_deltas": [ - -1, - 3 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_ER1BEG0_1", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE4B2_1", - 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"CLK_HROW_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_LH1_2", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_LH6_2", - "VBRK_LH6" - ], - [ - "CLK_HROW_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_LH4_2", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_LH8_2", - "VBRK_LH8" - ], - [ - "CLK_HROW_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_LH10_2", - "VBRK_LH10" - ], - [ - "CLK_HROW_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_LH2_2", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_LH9_2", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_LH12_2", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_LH5_2", - "VBRK_LH5" - ], - [ - "CLK_HROW_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WL1END2_2", - "VBRK_WL1END2" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "RIOB33", - "RIOI3_TBYTESRC" - ], - "wire_pairs": [ - [ - "IOB_KEEPER_INT_EN_1", - "RIOI_KEEPER_INT_EN_1" - ], - [ - "LIOB_IN_TERM1", - "RIOI_DCI_T_TERM1" - ], - [ - "IOB_IBUF1", - "RIOI_IBUF1" - ], - [ - "IOB_IBUF0", - "RIOI_IBUF0" - ], - [ - "RIOB_MONITOR_P", - "IOI_MONITOR_P" - ], - [ - "IOB_PD_INT_EN_0", - "RIOI_PD_INT_EN_0" - ], - [ - "IOB_IBUF_DISABLE1", - "RIOI_IBUF_DISABLE1" - ], - [ - "IOB_T0", - "RIOI_T0" - ], - [ - "IOB_KEEPER_INT_EN_0", - "RIOI_KEEPER_INT_EN_0" - ], - [ - "LIOB_IN_TERM0", - "RIOI_DCI_T_TERM0" - ], - [ - "IOB_O1", - "RIOI_O1" - ], - [ - "IOB_O0", - "RIOI_O0" - ], - [ - "RIOB_MONITOR_N", - "IOI_MONITOR_N" - ], - [ - "IOB_PD_INT_EN_1", - "RIOI_PD_INT_EN_1" - ], - [ - "IOB_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE0" - ], - [ - "IOB_PU_INT_EN_0", - "RIOI_PU_INT_EN_0" - ], - [ - "IOB_DIFF_TERM_INT_EN", - "RIOI_DIFF_TERM_INT_EN" - ], - [ - "IOB_PU_INT_EN_1", - "RIOI_PU_INT_EN_1" - ], - [ - "IOB_T1", - "RIOI_T1" - ] - ] - }, - { - "grid_deltas": [ - 5, - -9 - ], - "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_L" - ], - "wire_pairs": [ - [ - "PCIE_WW4END0_19", - "INT_INTERFACE_WW4END0" - ], - [ - "PCIE_EE4C1_19", - "INT_INTERFACE_EE4C1" - ], - [ - "PCIE_WW2END3_19", - "INT_INTERFACE_WW2END3" - ], - [ - "PCIE_LH5_19", - "INT_INTERFACE_LH5" - ], - [ - "PCIE_LOGIC_OUTS_B16_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B16" - ], - [ - "PCIE_IMUX11_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT11" - ], - [ - "PCIE_SW4A0_19", - "INT_INTERFACE_SW4A0" - ], - [ - "PCIE_IMUX1_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT1" - ], - [ - "PCIE_IMUX42_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT42" - ], - [ - "PCIE_WW2A0_19", - "INT_INTERFACE_WW2A0" - ], - [ - "PCIE_NE2A3_19", - "INT_INTERFACE_NE2A3" - ], - [ - "PCIE_LOGIC_OUTS_B5_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B5" - ], - [ - "PCIE_IMUX46_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT46" - ], - [ - "PCIE_CTRL0_L_19", - "INT_INTERFACE_CTRL0" - ], - [ - "PCIE_WL1END3_19", - "INT_INTERFACE_WL1END3" - ], - [ - "PCIE_IMUX38_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT38" - ], - [ - "PCIE_BYP6_L_19", - "INT_INTERFACE_BYP6" - ], - [ - "PCIE_EE4C3_19", - "INT_INTERFACE_EE4C3" - ], - [ - "PCIE_NE4BEG2_19", - "INT_INTERFACE_NE4BEG2" - ], - [ - "PCIE_WW2END1_19", - "INT_INTERFACE_WW2END1" - ], - [ - "PCIE_SW4A1_19", - "INT_INTERFACE_SW4A1" - ], - [ - "PCIE_FAN6_L_19", - "INT_INTERFACE_FAN6" - ], - [ - "PCIE_EE2A1_19", - "INT_INTERFACE_EE2A1" - ], - [ - "PCIE_EE4B1_19", - "INT_INTERFACE_EE4B1" - ], - [ - "PCIE_WW4C3_19", - "INT_INTERFACE_WW4C3" - ], - [ - "PCIE_SE4C1_19", - "INT_INTERFACE_SE4C1" - ], - [ - "PCIE_EL1BEG1_19", - "INT_INTERFACE_EL1BEG1" - ], - [ - "PCIE_LOGIC_OUTS_B7_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B7" - ], - [ - "PCIE_BYP3_L_19", - "INT_INTERFACE_BYP3" - ], - [ - "PCIE_IMUX9_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT9" - ], - [ - "PCIE_NW2A2_19", - "INT_INTERFACE_NW2A2" - ], - [ - "PCIE_LH9_19", - "INT_INTERFACE_LH9" - ], - [ - "PCIE_WW2END2_19", - "INT_INTERFACE_WW2END2" - ], - [ - "PCIE_FAN2_L_19", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_WW4B3_19", - "INT_INTERFACE_WW4B3" - ], - [ - "PCIE_SE4C2_19", - "INT_INTERFACE_SE4C2" - ], - [ - "PCIE_SW4END1_19", - "INT_INTERFACE_SW4END1" - ], - [ - "PCIE_LH11_19", - "INT_INTERFACE_LH11" - ], - [ - "PCIE_LOGIC_OUTS_B4_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B4" - ], - [ - "PCIE_FAN1_L_19", - "INT_INTERFACE_FAN1" - ], - [ - "PCIE_IMUX41_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT41" - ], - [ - "PCIE_IMUX20_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT20" - ], - [ - "PCIE_WW4C2_19", - "INT_INTERFACE_WW4C2" - ], - [ - "PCIE_IMUX43_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT43" - ], - [ - "PCIE_WW4END2_19", - "INT_INTERFACE_WW4END2" - ], - [ - "PCIE_IMUX29_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT29" - ], - [ - "PCIE_ER1BEG3_19", - "INT_INTERFACE_ER1BEG3" - ], - [ - "PCIE_EE2BEG1_19", - "INT_INTERFACE_EE2BEG1" - ], - [ - "PCIE_EE4A1_19", - "INT_INTERFACE_EE4A1" - ], - [ - "PCIE_CLK1_L_19", - "INT_INTERFACE_CLK1" - ], - [ - "PCIE_LH1_19", - "INT_INTERFACE_LH1" - ], - [ - "PCIE_IMUX47_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT47" - ], - [ - "PCIE_ER1BEG0_19", - "INT_INTERFACE_ER1BEG0" - ], - [ - "PCIE_SE4BEG3_19", - "INT_INTERFACE_SE4BEG3" - ], - [ - "PCIE_LOGIC_OUTS_B21_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B21" - ], - [ - "PCIE_IMUX44_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT44" - ], - [ - "PCIE_BYP4_L_19", - "INT_INTERFACE_BYP4" - ], - [ - "PCIE_EL1BEG2_19", - "INT_INTERFACE_EL1BEG2" - ], - [ - "PCIE_NW4A3_19", - "INT_INTERFACE_NW4A3" - ], - [ - "PCIE_IMUX10_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT10" - ], - [ - "PCIE_LH2_19", - "INT_INTERFACE_LH2" - ], - [ - "PCIE_IMUX6_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT6" - ], - [ - "PCIE_EL1BEG3_19", - "INT_INTERFACE_EL1BEG3" - ], - [ - "PCIE_LH4_19", - "INT_INTERFACE_LH4" - ], - [ - "PCIE_WL1END2_19", - "INT_INTERFACE_WL1END2" - ], - [ - "PCIE_NW4A1_19", - "INT_INTERFACE_NW4A1" - ], - [ - "PCIE_EE2A0_19", - "INT_INTERFACE_EE2A0" - ], - [ - "PCIE_EE4A2_19", - "INT_INTERFACE_EE4A2" - ], - [ - "PCIE_WW2END0_19", - "INT_INTERFACE_WW2END0" - ], - [ - "PCIE_NE2A1_19", - "INT_INTERFACE_NE2A1" - ], - [ - "PCIE_LOGIC_OUTS_B11_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "PCIE_BYP5_L_19", - "INT_INTERFACE_BYP5" - ], - [ - "PCIE_EL1BEG0_19", - "INT_INTERFACE_EL1BEG0" - ], - [ - "PCIE_LH8_19", - "INT_INTERFACE_LH8" - ], - [ - "PCIE_IMUX30_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT30" - ], - [ - "PCIE_LOGIC_OUTS_B13_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B13" - ], - [ - "PCIE_WW4B2_19", - "INT_INTERFACE_WW4B2" - ], - [ - "PCIE_FAN3_L_19", - "INT_INTERFACE_FAN3" - ], - [ - "PCIE_WW4C1_19", - "INT_INTERFACE_WW4C1" - ], - [ - "PCIE_WW4B1_19", - "INT_INTERFACE_WW4B1" - ], - [ - "PCIE_NW4END1_19", - "INT_INTERFACE_NW4END1" - ], - [ - "PCIE_BYP1_L_19", - "INT_INTERFACE_BYP1" - ], - [ - "PCIE_SE2A2_19", - "INT_INTERFACE_SE2A2" - ], - [ - "PCIE_SW4END2_19", - "INT_INTERFACE_SW4END2" - ], - [ - "PCIE_IMUX26_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT26" - ], - [ - "PCIE_NE2A2_19", - "INT_INTERFACE_NE2A2" - ], - [ - "PCIE_FAN5_L_19", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_BYP0_L_19", - "INT_INTERFACE_BYP0" - ], - [ - "PCIE_IMUX32_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT32" - ], - [ - "PCIE_WR1END0_19", - "INT_INTERFACE_WR1END0" - ], - [ - "PCIE_IMUX2_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT2" - ], - [ - "PCIE_EE4B3_19", - "INT_INTERFACE_EE4B3" - ], - [ - "PCIE_EE2A2_19", - "INT_INTERFACE_EE2A2" - ], - [ - "PCIE_SW2A0_19", - "INT_INTERFACE_SW2A0" - ], - [ - "PCIE_LOGIC_OUTS_B9_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B9" - ], - [ - "PCIE_EE2BEG0_19", - "INT_INTERFACE_EE2BEG0" - ], - [ - "PCIE_SE2A1_19", - "INT_INTERFACE_SE2A1" - ], - [ - "PCIE_SE4BEG2_19", - "INT_INTERFACE_SE4BEG2" - ], - [ - "PCIE_WW4END1_19", - "INT_INTERFACE_WW4END1" - ], - [ - "PCIE_WL1END1_19", - "INT_INTERFACE_WL1END1" - ], - [ - "PCIE_LOGIC_OUTS_B3_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B3" - ], - [ - "PCIE_MONITOR_P_19", - "INT_INTERFACE_MONITOR_P" - ], - [ - "PCIE_LOGIC_OUTS_B22_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B22" - ], - [ - "PCIE_IMUX35_L_19", - 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"CLK_BUFG_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_BUFG_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_BUFG_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_BUFG_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_BUFG_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_BUFG_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_BUFG_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_BUFG_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_BUFG_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_BUFG_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_BUFG_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_BUFG_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_BUFG_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_BUFG_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_BUFG_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_BUFG_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_BUFG_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_BUFG_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_BUFG_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_BUFG_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_BUFG_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_BUFG_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_BUFG_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_BUFG_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_BUFG_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_BUFG_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_BUFG_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_BUFG_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_BUFG_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_SW4END0_7", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EE4B1_7", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX7_7", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_NW4END3_7", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_LH5_7", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_IMUX9_7", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4BEG3_7", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_ER1BEG2_7", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_EE4C3_7", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_NW2A3_7", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_CTRL1_7", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP4_7", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_BYP7_7", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_CTRL0_7", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_NE4C2_7", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX16_7", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX19_7", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_EE4A2_7", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE4A1_7", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_EE2A0_7", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_SW4A2_7", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_LH6_7", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_IMUX22_7", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_SW4END1_7", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_NW2A2_7", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_SE4C0_7", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_IMUX4_7", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WL1END3_7", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_SW4A1_7", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_EE4C0_7", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_SW2A3_7", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_IMUX38_7", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX34_7", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_NE4C3_7", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX30_7", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_NE2A1_7", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_WW2END1_7", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_NE2A2_7", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_IMUX24_7", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_SE2A1_7", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX11_7", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_WR1END1_7", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_LH2_7", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_IMUX21_7", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX15_7", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_EE4A0_7", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_EE2BEG1_7", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_WW4C3_7", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_FAN1_7", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_WW2A3_7", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_NW4A2_7", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_LH11_7", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_SW2A2_7", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_EE4BEG0_7", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SE4BEG3_7", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_IMUX26_7", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_BYP0_7", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_WR1END3_7", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_EE4BEG1_7", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_IMUX17_7", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_LH1_7", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_WW4C1_7", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_IMUX13_7", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_SE4BEG2_7", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_SE4C3_7", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_NE4BEG2_7", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW2A1_7", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE4A3_7", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_WW2A1_7", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX36_7", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4B3_7", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX39_7", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SE4BEG1_7", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NW4END1_7", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_IMUX41_7", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SE4BEG0_7", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_WL1END1_7", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_NW4END2_7", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EL1BEG0_7", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_EE2BEG0_7", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_NE4BEG3_7", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_IMUX28_7", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_EE2A2_7", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_FAN3_7", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX12_7", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_WW4END3_7", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_SW4END2_7", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_BYP1_7", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SE2A2_7", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2END0_7", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_FAN6_7", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WR1END0_7", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_IMUX14_7", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_WW2A0_7", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SE2A3_7", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_WW2END3_7", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_IMUX33_7", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX45_7", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_CLK1_7", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_ER1BEG3_7", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_NW4A1_7", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_WW4A2_7", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_EE2A1_7", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_SW4END3_7", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EL1BEG2_7", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW4B3_7", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_LH9_7", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_EL1BEG3_7", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_EE2BEG3_7", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW4A3_7", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_NW4A0_7", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX32_7", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX3_7", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_CLK0_7", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW4A1_7", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW4C2_7", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW2A0_7", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_IMUX44_7", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH8_7", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_LH10_7", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_LH7_7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_FAN7_7", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW4C0_7", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_IMUX18_7", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_NE4C0_7", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW2A2_7", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_LH4_7", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_FAN4_7", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_IMUX43_7", - "INT_INTERFACE_IMUX43" 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"CLK_HROW_IMUX17_3", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX44_3", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_IMUX14_3", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_IMUX36_3", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW4END0_3", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_WW2A2_3", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_BYP3_3", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_IMUX1_3", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_IMUX22_3", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_WW2A1_3", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_NE4C3_3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_NW4END0_3", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WW4B2_3", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_WR1END0_3", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE4B0_3", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_EE2A3_3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_WW2END3_3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_IMUX19_3", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_EE4A0_3", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_SE4C0_3", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_LH7_3", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_SW4END1_3", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EE4B3_3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_BYP5_3", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_IMUX43_3", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_WR1END1_3", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_IMUX20_3", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_NE4C2_3", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX11_3", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_FAN0_3", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX25_3", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "CLK_MTBF2" - ], - "wire_pairs": [ - [ - "CLK_BUFG_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_BUFG_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_BUFG_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_BUFG_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_BUFG_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_BUFG_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_BUFG_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_BUFG_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_BUFG_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_BUFG_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_BUFG_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_BUFG_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_BUFG_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_BUFG_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_BUFG_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_BUFG_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_BUFG_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_BUFG_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_BUFG_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_BUFG_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_BUFG_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_BUFG_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_BUFG_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_BUFG_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_BUFG_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_BUFG_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_BUFG_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_BUFG_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_BUFG_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_BUFG_BOT_R_CK_MUXED5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_BUFG_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_BUFG_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_BUFG_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 1 - ], - "tile_types": [ - "GTP_CHANNEL_1", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTPE2_CLK1_4", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_BYP7_4", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX9_4", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX20_4", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_FAN0_4", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_LOGIC_OUTS_B20_4", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_BYP3_4", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_LOGIC_OUTS_B4_4", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_LOGIC_OUTS_B7_4", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_BYP4_4", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX24_4", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_IMUX17_4", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_FAN4_4", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_LOGIC_OUTS_B17_4", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_LOGIC_OUTS_B22_4", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_BYP0_4", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_CLK0_4", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_LOGIC_OUTS_B16_4", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_IMUX31_4", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX35_4", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_LOGIC_OUTS_B2_4", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_IMUX10_4", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_LOGIC_OUTS_B9_4", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_FAN5_4", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_IMUX0_4", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX42_4", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX37_4", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_CTRL0_4", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_FAN2_4", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX39_4", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX3_4", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_FAN7_4", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_CTRL1_4", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_LOGIC_OUTS_B13_4", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX28_4", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX22_4", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX46_4", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_LOGIC_OUTS_B12_4", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_IMUX38_4", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX12_4", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX32_4", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX23_4", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX14_4", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX4_4", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_FAN6_4", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX16_4", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_LOGIC_OUTS_B1_4", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX5_4", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_BYP1_4", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX34_4", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_LOGIC_OUTS_B21_4", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_IMUX13_4", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX47_4", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX8_4", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX11_4", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX25_4", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX18_4", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_FAN3_4", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_LOGIC_OUTS_B14_4", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX30_4", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B0_4", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_BYP5_4", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_BYP6_4", - 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"VBRK_EE4A0" - ], - [ - "CMT_TOP_WW4A1_6", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_EE4C0_6", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_NE4C0_6", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_NW4A1_6", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4B2_6", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_SE4BEG0_6", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_WW2A3_6", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_SW4A3_6", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_EE2BEG1_6", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_LH6_6", - "VBRK_LH6" - ], - [ - "CMT_TOP_LH9_6", - "VBRK_LH9" - ], - [ - "CMT_TOP_EE4B0_6", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_ER1BEG3_6", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_SW4END0_6", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_WW4B1_6", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WW2A2_6", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_WR1END1_6", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_NW4A0_6", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_EL1BEG2_6", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_NE4BEG0_6", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_EE2A1_6", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_SW4A2_6", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_EE4A1_6", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_WW4END2_6", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_EE2A2_6", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_WW4A0_6", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_ER1BEG2_6", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_WW4A2_6", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_NE4BEG3_6", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_SW4END1_6", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_NE4BEG2_6", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_NW4END2_6", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_LH2_6", - "VBRK_LH2" - ], - [ - "CMT_TOP_EE4A2_6", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_NE2A0_6", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_NE4C1_6", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_NW4A2_6", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_SW2A1_6", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_WW4END1_6", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_WW4END3_6", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_EE4C3_6", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NW2A3_6", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_SW4A0_6", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_EE4BEG0_6", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_NE4C2_6", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_EE4BEG1_6", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_EE2BEG3_6", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_WW2END2_6", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_LH1_6", - "VBRK_LH1" - ], - [ - "CMT_TOP_WR1END3_6", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WR1END0_6", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_WW2END3_6", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_WW4END0_6", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_LH4_6", - "VBRK_LH4" - ], - [ - "CMT_TOP_SE2A2_6", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_WW4A3_6", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_SE4BEG1_6", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_EE4C1_6", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_NE2A1_6", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_NE4BEG1_6", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_NW2A2_6", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_SW4END3_6", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SW2A0_6", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_EE2A0_6", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_EE4B2_6", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_EE4C2_6", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_NW4END1_6", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_NW2A1_6", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_SW2A2_6", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_WW4C3_6", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_WL1END1_6", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_ER1BEG0_6", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_SW2A3_6", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_WW4B0_6", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_EL1BEG0_6", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_LH3_6", - "VBRK_LH3" - ], - [ - "CMT_TOP_NE4C3_6", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_NW2A0_6", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_SE4C0_6", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_WL1END2_6", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_EE4BEG2_6", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_WW4B3_6", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WR1END2_6", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_SE4BEG3_6", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_NW4END3_6", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW2A1_6", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WW2END0_6", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_MONITOR_N_6", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_LH11_6", - "VBRK_LH11" - ], - [ - "CMT_TOP_LH8_6", - "VBRK_LH8" - ], - [ - "CMT_TOP_LH10_6", - "VBRK_LH10" - ], - [ - "CMT_TOP_NE2A3_6", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_WW4C2_6", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_SE2A1_6", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_EL1BEG1_6", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_SE4C1_6", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_WL1END0_6", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_SE2A3_6", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_WW2A0_6", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_NW4A3_6", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_LH12_6", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE4BEG3_6", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_EE2A3_6", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_SE4C3_6", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_SE4BEG2_6", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_ER1BEG1_6", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_SW4END2_6", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_LH5_6", - "VBRK_LH5" - ], - [ - "CMT_TOP_WW2END1_6", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_EE4B1_6", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_EE4B3_6", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_WW4C1_6", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_NW4END0_6", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_SE4C2_6", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_EE2BEG0_6", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_EE4A3_6", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_WW4C0_6", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_SW4A1_6", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_LH7_6", - "VBRK_LH7" - ], - [ - "CMT_TOP_EL1BEG3_6", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_EE2BEG2_6", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_SE2A0_6", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_WL1END3_6", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_NE2A2_6", - "VBRK_NE2A2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_IOB", - "HCLK_IOI3" - ], - "wire_pairs": [ - [ - "HCLK_IOB_CK_BUFHCLK8", - "HCLK_IOI_CK_BUFHCLK8" - ], - [ - "HCLK_IOB_PERFCLK3", - "HCLK_IOI_IOCLK_PLL3" - ], - [ - "HCLK_IOB_CK_BUFHCLK6", - "HCLK_IOI_CK_BUFHCLK6" - ], - [ - "HCLK_IOB_PERFCLK2", - "HCLK_IOI_IOCLK_PLL2" - ], - [ - "HCLK_IOB_CK_BUFRCLK1", - "HCLK_IOI_CK_BUFRCLK1" - ], - [ - "HCLK_IOB_CK_BUFHCLK2", - "HCLK_IOI_CK_BUFHCLK2" - ], - [ - "HCLK_IOB_CK_BUFRCLK0", - "HCLK_IOI_CK_BUFRCLK0" - ], - [ - "HCLK_IOB_CK_BUFHCLK9", - "HCLK_IOI_CK_BUFHCLK9" - ], - [ - "HCLK_IOB_CK_BUFHCLK10", - "HCLK_IOI_CK_BUFHCLK10" - ], - [ - "HCLK_IOB_PERFCLK0", - "HCLK_IOI_IOCLK_PLL0" - ], - [ - "HCLK_IOB_CK_BUFHCLK11", - "HCLK_IOI_CK_BUFHCLK11" - ], - [ - "HCLK_IOB_CK_BUFHCLK5", - "HCLK_IOI_CK_BUFHCLK5" - ], - [ - "HCLK_IOB_CK_BUFHCLK3", - "HCLK_IOI_CK_BUFHCLK3" - ], - [ - "HCLK_IOB_CK_BUFHCLK1", - "HCLK_IOI_CK_BUFHCLK1" - ], - [ - "HCLK_IOB_CK_BUFRCLK3", - "HCLK_IOI_CK_BUFRCLK3" - ], - [ - "HCLK_IOB_CK_BUFHCLK7", - "HCLK_IOI_CK_BUFHCLK7" - ], - [ - "HCLK_IOB_CK_BUFHCLK0", - "HCLK_IOI_CK_BUFHCLK0" - ], - [ - "HCLK_IOB_CK_BUFHCLK4", - "HCLK_IOI_CK_BUFHCLK4" - ], - [ - "HCLK_IOB_PERFCLK1", - "HCLK_IOI_IOCLK_PLL1" - ], - [ - "HCLK_IOB_CK_BUFRCLK2", - "HCLK_IOI_CK_BUFRCLK2" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_BUFG_IMUX11_2", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_WW4C0_2", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_IMUX17_2", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_BUFG_IMUX36_2", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_WW4C2_2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_BUFG_IMUX22_2", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_NW4A3_2", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_BUFG_IMUX45_2", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_BUFG_IMUX23_2", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_FAN6_2", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_SE2A3_2", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_SW4A1_2", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_BUFG_IMUX35_2", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_BUFG_IMUX3_2", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_FAN7_2", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_BYP5_2", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_EE2BEG0_2", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_BUFG_IMUX42_2", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_LH3_2", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_BUFG_IMUX44_2", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_BUFG_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_BUFG_IMUX20_2", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_LH12_2", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WR1END1_2", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_BUFG_IMUX19_2", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_NW2A0_2", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_NW4END1_2", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_EE4B0_2", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_LH4_2", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_BYP3_2", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_2", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_HROW_NE4BEG3_2", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_BUFG_IMUX6_2", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_BUFG_IMUX5_2", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_EE4B3_2", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_EE4C0_2", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_BYP6_2", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_LH11_2", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW4B3_2", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_NE4BEG0_2", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_WW2A0_2", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW2A3_2", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_BUFG_IMUX18_2", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_2", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_BUFG_IMUX46_2", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_BUFG_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_FAN5_2", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_2", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_HROW_ER1BEG2_2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_NW4END2_2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_NE4C1_2", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_2", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_HROW_SE4C0_2", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_WW2A2_2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_2", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_SE2A0_2", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_CTRL0_2", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_EL1BEG3_2", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_NW4A0_2", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_SE4BEG2_2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_NE2A0_2", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_IMUX0_2", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_SW4A3_2", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_BUFG_IMUX14_2", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_NW2A3_2", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_NE4C3_2", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_NW2A2_2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_EE2BEG1_2", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_WW4A3_2", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_WW2END1_2", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_LH10_2", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_SW4END0_2", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EE4A3_2", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_BUFG_IMUX27_2", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_IMUX33_2", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_WW2A1_2", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_SE4C1_2", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_FAN1_2", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_LH1_2", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_EE4BEG0_2", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4END3_2", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EE4BEG3_2", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_SW2A1_2", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_BUFG_IMUX32_2", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_BUFG_IMUX9_2", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_WL1END2_2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_NE2A3_2", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_LH2_2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_LH9_2", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_EE4A0_2", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_BUFG_IMUX37_2", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4C3_2", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_LH6_2", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_SE4BEG3_2", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE4BEG2_2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_BYP0_2", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_BUFG_IMUX26_2", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_BYP1_2", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_BUFG_IMUX13_2", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_BUFG_IMUX31_2", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX47_2", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_NE2A1_2", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_BUFG_IMUX12_2", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_SE4BEG0_2", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_IMUX16_2", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_BUFG_IMUX39_2", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SE4C2_2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_WR1END3_2", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_FAN3_2", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_EE2A2_2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE2A0_2", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE2A1_2", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_WW4B2_2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_NE2A2_2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_SW2A3_2", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_BUFG_IMUX8_2", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WW2END0_2", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "CLK_BUFG_IMUX7_2", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_BUFG_IMUX15_2", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_FAN0_2", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_EE4B2_2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_2", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_WW4A2_2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_WW4END1_2", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_WW4END2_2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_SE4BEG1_2", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_WW4B0_2", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_BUFG_IMUX40_2", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_ER1BEG0_2", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_EE2BEG3_2", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_2", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_WL1END0_2", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_EE4C2_2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_EE4A2_2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_FAN2_2", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_EL1BEG2_2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW4A0_2", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NW4END3_2", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_NW4A1_2", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_EE4B1_2", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SW4A2_2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_CTRL1_2", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP7_2", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_BYP4_2", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_BUFG_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_BUFG_IMUX29_2", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_BUFG_IMUX30_2", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_WW4END3_2", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_NE4BEG2_2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_WR1END2_2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_BUFG_IMUX21_2", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_SE2A1_2", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_CLK0_2", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW2END3_2", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW2END2_2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_SW2A0_2", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_BUFG_IMUX2_2", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_BUFG_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "CLK_BUFG_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_SE2A2_2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_LH5_2", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_WR1END0_2", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE4BEG1_2", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_BUFG_IMUX24_2", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_FAN4_2", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_2", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_BUFG_IMUX43_2", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_NW4END0_2", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_WW4C1_2", - "INT_INTERFACE_WW4C1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "IO_INT_INTERFACE_L", - "L_TERM_INT" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_IMUX32", - "TERM_INT_IMUX32" - ], - [ - "INT_INTERFACE_IMUX29", - "TERM_INT_IMUX29" - ], - [ - "INT_INTERFACE_SW2A0", - "L_TERM_INT_SW2BEG0" - ], - [ - "INT_INTERFACE_BYP4", - "TERM_INT_BYP4" - ], - [ - "INT_INTERFACE_ER1BEG2", - "L_TERM_INT_WR1BEG3" - ], - [ - "INT_INTERFACE_BLOCK_OUTS_L_B0", - "TERM_INT_BLOCK_OUTS_L_B0" - ], - [ - "INT_INTERFACE_IMUX27", - "TERM_INT_IMUX27" - ], - [ - "INT_INTERFACE_SW4A2", - "L_TERM_INT_SW4BEG2" - ], - [ - "INT_INTERFACE_WW4END3", - "L_TERM_INT_WW4C3" - ], - [ - "INT_INTERFACE_WW4C0", - "L_TERM_INT_WW4B0" - ], - [ - "INT_INTERFACE_WW4A1", - "L_TERM_INT_WW4BEG1" - ], - [ - "INT_INTERFACE_IMUX16", - "TERM_INT_IMUX16" - ], - [ - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" - ], - [ - "INT_INTERFACE_WW2END3", - "L_TERM_INT_WW2A3" - ], - [ - "INT_INTERFACE_IMUX41", - "TERM_INT_IMUX41" - ], - [ - "INT_INTERFACE_IMUX20", - "TERM_INT_IMUX20" - ], - [ - "INT_INTERFACE_CTRL0", - "TERM_INT_CTRL0" - ], - [ - "INT_INTERFACE_EE4A2", - "L_TERM_INT_WW4A2" - ], - [ - "INT_INTERFACE_MONITOR_N", - "TERM_INT_MONITOR_N" - ], - [ - "INT_INTERFACE_NE4BEG3", - "L_TERM_INT_NW4BEG3" - ], - [ - "INT_INTERFACE_SW2A1", - "L_TERM_INT_SW2BEG1" - ], - [ - "INT_INTERFACE_IMUX38", - "TERM_INT_IMUX38" - ], - [ - "INT_INTERFACE_IMUX10", - "TERM_INT_IMUX10" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "INT_INTERFACE_BYP6", - "TERM_INT_BYP6" - ], - [ - "INT_INTERFACE_IMUX33", - "TERM_INT_IMUX33" - ], - [ - "INT_INTERFACE_MONITOR_P", - "TERM_INT_MONITOR_P" - ], - [ - "INT_INTERFACE_LH1", - "L_TERM_INT_LH0" - ], - [ - "INT_INTERFACE_WL1END0", - "L_TERM_INT_WL1BEG0" - ], - [ - "INT_INTERFACE_NE4BEG1", - "L_TERM_INT_NW4BEG1" - ], - [ - "INT_INTERFACE_IMUX35", - "TERM_INT_IMUX35" - ], - [ - "INT_INTERFACE_EE4B3", - "L_TERM_INT_WW4B3" - ], - [ - "INT_INTERFACE_EE4C2", - "L_TERM_INT_WW4C2" - ], - [ - "INT_INTERFACE_NW4A3", - "L_TERM_INT_NW4BEG3" - ], - [ - "INT_INTERFACE_IMUX22", - "TERM_INT_IMUX22" - ], - [ - "INT_INTERFACE_EE4C0", - "L_TERM_INT_WW4C0" - ], - [ - "INT_INTERFACE_IMUX0", - "TERM_INT_IMUX0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "INT_INTERFACE_WW2A3", - "L_TERM_INT_WW2BEG3" - ], - [ - "INT_INTERFACE_IMUX5", - "TERM_INT_IMUX5" - ], - [ - "INT_INTERFACE_EE4B1", - "L_TERM_INT_WW4B1" - ], - [ - "INT_INTERFACE_IMUX43", - "TERM_INT_IMUX43" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "TERM_INT_LOGIC_OUTS_L_B19" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "INT_INTERFACE_WR1END3", - "L_TERM_INT_WL1BEG3" - ], - [ - "INT_INTERFACE_EL1BEG2", - "L_TERM_INT_WL1BEG2" - ], - [ - "INT_INTERFACE_NW4A2", - "L_TERM_INT_NW4BEG2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "TERM_INT_LOGIC_OUTS_L_B0" - ], - [ - "INT_INTERFACE_FAN4", - "TERM_INT_FAN4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "INT_INTERFACE_IMUX1", - "TERM_INT_IMUX1" - ], - [ - "INT_INTERFACE_NE2A1", - "L_TERM_INT_NW2BEG1" - ], - [ - "INT_INTERFACE_LH9", - "L_TERM_INT_LH3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "TERM_INT_LOGIC_OUTS_L_B13" - ], - [ - "L_INT_INTER_DQS_IOTOPHASER", - "L_TERM_INT_DQS_IOTOPHASER" - ], - [ - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "INT_INTERFACE_IMUX2", - "TERM_INT_IMUX2" - ], - [ - "INT_INTERFACE_FAN6", - "TERM_INT_FAN6" - ], - [ - "INT_INTERFACE_IMUX14", - "TERM_INT_IMUX14" - ], - [ - "INT_INTERFACE_CTRL1", - "TERM_INT_CTRL1" - ], - [ - "INT_INTERFACE_SW4END1", - "L_TERM_INT_SW4C1" - ], - [ - "INT_INTERFACE_IMUX25", - "TERM_INT_IMUX25" - ], - [ - "INT_INTERFACE_SW4A0", - "L_TERM_INT_SW4BEG0" - ], - [ - "INT_INTERFACE_EE4BEG1", - "L_TERM_INT_WW4BEG1" - ], - [ - "INT_INTERFACE_EE4B0", - "L_TERM_INT_WW4B0" - ], - [ - "INT_INTERFACE_WR1END2", - "L_TERM_INT_WR1BEG3" - ], - [ - "INT_INTERFACE_NW4END2", - "L_TERM_INT_NW4C2" - ], - [ - "INT_INTERFACE_EE4A3", - "L_TERM_INT_WW4A3" - ], - [ - "INT_INTERFACE_EE4C3", - "L_TERM_INT_WW4C3" - ], - [ - "INT_INTERFACE_NW2A2", - "L_TERM_INT_NW2BEG2" - ], - [ - "INT_INTERFACE_NW2A0", - "L_TERM_INT_NW2BEG0" - ], - [ - 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"CFG_CENTER_NE4BEG3_8", - "VFRAME_NE4BEG3" - ], - [ - "CFG_CENTER_NE4BEG0_8", - "VFRAME_NE4BEG0" - ], - [ - "CFG_CENTER_IMUX22_8", - "VFRAME_IMUX22" - ], - [ - "CFG_CENTER_IMUX14_8", - "VFRAME_IMUX14" - ], - [ - "CFG_CENTER_EL1BEG2_8", - "VFRAME_EL1BEG2" - ], - [ - "CFG_CENTER_NW4END1_8", - "VFRAME_NW4END1" - ], - [ - "CFG_CENTER_WW4B3_8", - "VFRAME_WW4B3" - ], - [ - "CFG_CENTER_IMUX39_8", - "VFRAME_IMUX39" - ], - [ - "CFG_CENTER_IMUX10_8", - "VFRAME_IMUX10" - ], - [ - "CFG_CENTER_EE4B1_8", - "VFRAME_EE4B1" - ], - [ - "CFG_CENTER_NE2A2_8", - "VFRAME_NE2A2" - ], - [ - "CFG_CENTER_LH10_8", - "VFRAME_LH10" - ], - [ - "CFG_CENTER_EE2BEG2_8", - "VFRAME_EE2BEG2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_PMV2_SVT", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_FEED_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLK_FEED_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLK_FEED_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLK_FEED_NE2A2", - "VBRK_NE2A2" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_LH3", - "VBRK_LH3" - ], - [ - "CLK_FEED_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLK_FEED_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLK_FEED_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLK_FEED_WW4C2", - "VBRK_WW4C2" - ], - [ - "CLK_FEED_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLK_FEED_EE4BEG2", - "VBRK_EE4BEG2" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLK_FEED_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLK_FEED_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLK_FEED_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLK_FEED_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_LH2", - "VBRK_LH2" - ], - [ - "CLK_FEED_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLK_FEED_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLK_FEED_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLK_FEED_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_LH12", - "VBRK_LH12" - ], - [ - "CLK_FEED_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLK_FEED_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLK_FEED_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLK_FEED_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLK_FEED_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_LH7", - "VBRK_LH7" - ], - [ - "CLK_FEED_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLK_FEED_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLK_FEED_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_LH8", - "VBRK_LH8" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLK_FEED_EE4B1", - "VBRK_EE4B1" - ], - [ - "CLK_FEED_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLK_FEED_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLK_FEED_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLK_FEED_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLK_FEED_ER1BEG2", - "VBRK_ER1BEG2" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "HCLK_INT_INTERFACE" - ], - "wire_pairs": [ - [ - "CLK_HROW_CK_IN_L2", - "HCLK_INT_INTERFACE_CK_IN2" - ], - [ - "CLK_HROW_CK_BUFRCLK_L0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "CLK_HROW_CK_BUFRCLK_L3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_L3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "CLK_HROW_CK_IN_L13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "CLK_HROW_CK_BUFHCLK_L9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "CLK_HROW_CK_BUFHCLK_L4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "CLK_HROW_CK_IN_L0", - "HCLK_INT_INTERFACE_CK_IN0" - ], - [ - "CLK_HROW_CK_BUFHCLK_L1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "CLK_HROW_CK_IN_L12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "CLK_HROW_CK_IN_L3", - "HCLK_INT_INTERFACE_CK_IN3" - ], - [ - "CLK_HROW_CK_BUFHCLK_L11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "CLK_HROW_CK_BUFRCLK_L1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "CLK_HROW_CK_BUFHCLK_L0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "CLK_HROW_CK_IN_L5", - "HCLK_INT_INTERFACE_CK_IN5" - ], - [ - "CLK_HROW_CK_IN_L1", - "HCLK_INT_INTERFACE_CK_IN1" - ], - [ - "CLK_HROW_CK_IN_L4", - "HCLK_INT_INTERFACE_CK_IN4" - ], - [ - "CLK_HROW_CK_IN_L10", - "HCLK_INT_INTERFACE_CK_IN10" - ], - [ - "CLK_HROW_CK_BUFRCLK_L2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "CLK_HROW_CK_BUFHCLK_L8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "CLK_HROW_CK_BUFHCLK_L6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ], - [ - 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], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ] - ] - }, - { - "grid_deltas": [ - 1, - 1 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_LH7_0", - "VBRK_LH7" - ], - [ - "CMT_TOP_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_LH11_0", - "VBRK_LH11" - ], - [ - "CMT_TOP_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_LH1_0", - "VBRK_LH1" - ], - [ - "CMT_TOP_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_LH12_0", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_LH8_0", - "VBRK_LH8" - ], - [ - "CMT_TOP_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_LH6_0", - "VBRK_LH6" - ], - [ - "CMT_TOP_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_LH2_0", - "VBRK_LH2" - ], - [ - "CMT_TOP_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_LH3_0", - "VBRK_LH3" - ], - [ - "CMT_TOP_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_LH4_0", - "VBRK_LH4" - ], - [ - "CMT_TOP_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_LH9_0", - "VBRK_LH9" - ], - [ - "CMT_TOP_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_EE4A2_0", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_LH10_0", - "VBRK_LH10" - ], - [ - "CMT_TOP_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_SW2A3_0", - "VBRK_SW2A3" - ], - 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"CLK_HROW_NE4BEG0_6", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_LH9_6", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_SW4END0_6", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_NE4C3_6", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX7_6", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WR1END2_6", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW2A1_6", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_WW2END0_6", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_WW4A1_6", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_FAN6_6", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WL1END0_6", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_IMUX31_6", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_IMUX10_6", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_LH5_6", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NE4BEG1_6", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE4C0_6", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_IMUX45_6", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_BYP4_6", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_EE2A2_6", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_IMUX46_6", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_WL1END3_6", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_EE4B3_6", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_BYP0_6", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_IMUX5_6", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX2_6", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_EE2BEG3_6", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_BYP3_6", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX11_6", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_IMUX23_6", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_IMUX22_6", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_EE4C2_6", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_IMUX27_6", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_IMUX26_6", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_IMUX8_6", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_EE2BEG0_6", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_IMUX18_6", - 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"CLK_HROW_CLK1_6", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_SE2A0_6", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_SW4A3_6", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX34_6", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_IMUX42_6", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_NW4END3_6", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_FAN2_6", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_IMUX38_6", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_MONITOR_N_6", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_LH6_6", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH1_6", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX6_6", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_IMUX15_6", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_CTRL1_6", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW4C0_6", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_BYP5_6", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_WW4C1_6", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_IMUX32_6", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_MONITOR_P_6", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_CTRL0_6", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX3_6", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_EL1BEG0_6", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_IMUX37_6", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_SE2A1_6", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE4A0_6", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_WW4A0_6", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_IMUX12_6", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_NE4BEG2_6", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_IMUX35_6", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_EE4C3_6", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE4B1_6", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SW2A0_6", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_WW2A3_6", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SE2A3_6", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_NW4A2_6", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_EE2A0_6", - "INT_INTERFACE_EE2A0" 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"INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NE2A2_6", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EL1BEG3_6", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_BYP6_6", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_EE4C1_6", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX29_6", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX9_6", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_ER1BEG2_6", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_FAN3_6", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX24_6", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WW4B0_6", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW2END3_6", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE4BEG2_6", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_IMUX33_6", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_ER1BEG3_6", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_SW2A2_6", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_ER1BEG1_6", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_FAN4_6", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_IMUX1_6", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_IMUX30_6", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_WW4B1_6", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE4B0_6", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_SW2A3_6", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SW4A2_6", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW4B2_6", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_SE4C3_6", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE4A1_6", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_WW4C3_6", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WL1END2_6", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_IMUX47_6", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_WW2END2_6", - "INT_INTERFACE_WW2END2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "LIOI3_TBYTETERM", - "L_TERM_INT" - ], - "wire_pairs": [ - [ - "IOI_IMUX43_0", - "TERM_INT_IMUX43" - ], - [ - "IOI_IMUX11_0", - "TERM_INT_IMUX11" - ], - [ - "IOI_FAN7_0", - "TERM_INT_FAN7" - ], - [ - "IOI_LOGIC_OUTS14_0", - "TERM_INT_LOGIC_OUTS_L_B14" - ], - [ - "IOI_CLK1_0", - "TERM_INT_CLK1" - ], - [ - "IOI_IMUX42_0", - "TERM_INT_IMUX42" - ], - [ - "IOI_IMUX13_0", - "TERM_INT_IMUX13" - ], - [ - "IOI_IMUX37_0", - "TERM_INT_IMUX37" - ], - [ - "IOI_IMUX39_0", - "TERM_INT_IMUX39" - ], - [ - "IOI_IMUX5_0", - "TERM_INT_IMUX5" - ], - [ - "IOI_LOGIC_OUTS11_0", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "IOI_IMUX27_0", - "TERM_INT_IMUX27" - ], - [ - "IOI_IMUX41_0", - "TERM_INT_IMUX41" - ], - [ - "IOI_LOGIC_OUTS23_0", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "IOI_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_LOGIC_OUTS8_0", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_IMUX1_0", - "TERM_INT_IMUX1" - ], - [ - "IOI_LOGIC_OUTS19_0", - "TERM_INT_LOGIC_OUTS_L_B19" - ], - [ - "IOI_IMUX38_0", - "TERM_INT_IMUX38" - ], - [ - "IOI_IMUX46_0", - "TERM_INT_IMUX46" - ], - [ - "IOI_BYP5_0", - "TERM_INT_BYP5" - ], - [ - "IOI_IMUX7_0", - "TERM_INT_IMUX7" - ], - [ - "IOI_BLOCK_OUTS2_0", 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"INT_INTERFACE_ER1BEG0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS11_1", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "CMT_FIFO_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS22_1", - "INT_INTERFACE_LOGIC_OUTS_L_B22" - ], - [ - "CMT_FIFO_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CMT_FIFO_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CMT_FIFO_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CMT_FIFO_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "CMT_FIFO_L_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CMT_FIFO_L_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CMT_FIFO_L_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CMT_FIFO_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CMT_FIFO_L_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "CMT_FIFO_WW4END2_1", - "INT_INTERFACE_WW4END2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 2 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE2BEG3_2", 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], - [ - "CLK_HROW_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_LH1_2", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_LH6_2", - "VBRK_LH6" - ], - [ - "CLK_HROW_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_EE4B2_2", - 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"CLK_HROW_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_LH5_2", - "VBRK_LH5" - ], - [ - "CLK_HROW_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WL1END2_2", - "VBRK_WL1END2" - ] - ] - }, - { - "grid_deltas": [ - 0, - -10 - ], - "tile_types": [ - "CFG_CENTER_MID", - "CFG_CENTER_TOP" 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"CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA31" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA11" - ], - [ - "CFG_CENTER_MID_ICAP1_CLK", - "CFG_CENTER_TOP_ICAP1_CLK" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA13" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA15" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA14" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA17" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA16" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA21" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA29" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA23" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA24" - ], - [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA12" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "CLBLL_L", - "HCLK_CLB" - ], - "wire_pairs": [ - [ - "CLBLL_L_COUT_N", - "HCLK_CLB_COUT1_L" - ], - [ - "CLBLL_LL_COUT_N", - "HCLK_CLB_COUT0_L" - ] - ] - }, - { - "grid_deltas": [ - -1, - -6 - ], - "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_WW2END1_6", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_PMV_IMUX0_6", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_PMV_SW4A2_6", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_LH7_6", - "INT_INTERFACE_LH7" - ], - [ - "CLK_PMV_EL1BEG2_6", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_PMV_NW4END0_6", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_EE2BEG0_6", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_IMUX10_6", - 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- "CLK_PMV_SE4C3_6", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_PMV_IMUX19_6", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_PMV_WW4B0_6", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_PMV_NW2A1_6", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_BYP1_6", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_SW4A1_6", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_PMV_NE4BEG3_6", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_IMUX40_6", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_PMV_IMUX11_6", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_WW4C3_6", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_LH4_6", - "INT_INTERFACE_LH4" - ], - [ - "CLK_PMV_NW4A1_6", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_PMV_IMUX3_6", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_EE4B1_6", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_IMUX5_6", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_EE4A0_6", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_PMV_IMUX21_6", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_NE2A3_6", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_PMV_FAN5_6", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_NW2A3_6", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_PMV_EE2A0_6", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_IMUX31_6", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_PMV_EE2BEG1_6", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_WW2A1_6", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_PMV_IMUX37_6", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_PMV_WW4END3_6", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_PMV_IMUX8_6", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_PMV_SW4A3_6", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_PMV_SW2A1_6", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_PMV_LH11_6", - "INT_INTERFACE_LH11" - ], - [ - "CLK_PMV_CTRL1_6", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_PMV_IMUX47_6", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_IMUX45_6", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_EE4C3_6", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_PMV_BYP3_6", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_IMUX2_6", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_IMUX46_6", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_PMV_IMUX17_6", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_CLK0_6", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_PMV_IMUX26_6", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_PMV_WL1END3_6", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_PMV_WR1END0_6", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_PMV_IMUX25_6", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_PMV_IMUX20_6", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_IMUX22_6", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_PMV_BYP7_6", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_FAN7_6", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_PMV_NE2A1_6", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_IMUX6_6", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_PMV_LH10_6", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_IMUX36_6", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_PMV_SW2A3_6", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_NE4C2_6", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_PMV_WW4A2_6", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX38_6", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_PMV_NW4A0_6", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_CLK1_6", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_SE2A1_6", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_WL1END0_6", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_PMV_WW4C2_6", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_EE4BEG2_6", - "INT_INTERFACE_EE4BEG2" + "GTPE2_CHANNEL_TXOUTCLK_3" ] ] }, @@ -277413,73 +341925,29 @@ -5 ], "tile_types": [ - "GTP_CHANNEL_3", + "GTP_CHANNEL_0", "VBRK_EXT" ], "wire_pairs": [ [ - "GTPE2_FAN0_10", - "VBRK_EXT_FAN0" + "GTPE2_BYP0_10", + "VBRK_EXT_BYP0" ], [ - "GTPE2_IMUX9_10", - "VBRK_EXT_IMUX9" + "GTPE2_BYP1_10", + "VBRK_EXT_BYP1" ], [ - "GTPE2_BYP7_10", - "VBRK_EXT_BYP7" + "GTPE2_BYP2_10", + "VBRK_EXT_BYP2" ], [ - "GTPE2_IMUX17_10", - "VBRK_EXT_IMUX17" + "GTPE2_BYP3_10", + "VBRK_EXT_BYP3" ], [ - "GTPE2_IMUX18_10", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX34_10", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX20_10", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX8_10", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX21_10", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX0_10", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B16_10", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_CLK0_10", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX10_10", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_FAN3_10", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX23_10", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX42_10", - "VBRK_EXT_IMUX42" + "GTPE2_BYP4_10", + "VBRK_EXT_BYP4" ], [ "GTPE2_BYP5_10", @@ -277490,25568 +341958,316 @@ "VBRK_EXT_BYP6" ], [ - "GTPE2_IMUX27_10", - "VBRK_EXT_IMUX27" + "GTPE2_BYP7_10", + "VBRK_EXT_BYP7" ], [ - "GTPE2_IMUX26_10", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX31_10", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX12_10", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX25_10", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_LOGIC_OUTS_B5_10", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_IMUX4_10", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_BYP2_10", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX19_10", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX7_10", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_LOGIC_OUTS_B23_10", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_FAN4_10", - "VBRK_EXT_FAN4" + "GTPE2_CLK0_10", + "VBRK_EXT_CLK0" ], [ "GTPE2_CLK1_10", "VBRK_EXT_CLK1" ], + [ + "GTPE2_CTRL0_10", + "VBRK_EXT_CTRL0" + ], [ "GTPE2_CTRL1_10", "VBRK_EXT_CTRL1" ], [ - "GTPE2_BYP4_10", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_LOGIC_OUTS_B14_10", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_LOGIC_OUTS_B3_10", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_IMUX6_10", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX3_10", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX1_10", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_IMUX35_10", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_BYP1_10", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX47_10", - "VBRK_EXT_IMUX47" + "GTPE2_FAN0_10", + "VBRK_EXT_FAN0" ], [ "GTPE2_FAN1_10", "VBRK_EXT_FAN1" ], - [ - "GTPE2_IMUX14_10", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX43_10", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_LOGIC_OUTS_B13_10", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX32_10", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B11_10", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTPE2_IMUX13_10", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX36_10", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_CTRL0_10", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_BYP0_10", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX40_10", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_BYP3_10", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX37_10", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_FAN6_10", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX33_10", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX30_10", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B9_10", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_LOGIC_OUTS_B6_10", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX16_10", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX45_10", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_LOGIC_OUTS_B1_10", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX28_10", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX39_10", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX15_10", - "VBRK_EXT_IMUX15" - ], [ "GTPE2_FAN2_10", "VBRK_EXT_FAN2" ], [ - "GTPE2_IMUX2_10", - "VBRK_EXT_IMUX2" + "GTPE2_FAN3_10", + "VBRK_EXT_FAN3" ], [ - "GTPE2_IMUX11_10", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX5_10", - "VBRK_EXT_IMUX5" + "GTPE2_FAN4_10", + "VBRK_EXT_FAN4" ], [ "GTPE2_FAN5_10", "VBRK_EXT_FAN5" ], [ - "GTPE2_IMUX44_10", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX29_10", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B12_10", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_LOGIC_OUTS_B2_10", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_LOGIC_OUTS_B4_10", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_IMUX22_10", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX46_10", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_LOGIC_OUTS_B22_10", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX24_10", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_LOGIC_OUTS_B19_10", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_LOGIC_OUTS_B17_10", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_LOGIC_OUTS_B0_10", - "VBRK_EXT_LOGIC_OUTS_B0" + "GTPE2_FAN6_10", + "VBRK_EXT_FAN6" ], [ "GTPE2_FAN7_10", "VBRK_EXT_FAN7" ], + [ + "GTPE2_IMUX0_10", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX1_10", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX2_10", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_10", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_10", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_10", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_10", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_10", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_10", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_10", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX10_10", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX11_10", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_10", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_10", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_10", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_10", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_10", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_10", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_10", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX19_10", + "VBRK_EXT_IMUX19" + ], + [ + "GTPE2_IMUX20_10", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_IMUX21_10", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX22_10", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX23_10", + "VBRK_EXT_IMUX23" + ], + [ + "GTPE2_IMUX24_10", + "VBRK_EXT_IMUX24" + ], + [ + "GTPE2_IMUX25_10", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX26_10", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX27_10", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX28_10", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_IMUX29_10", + "VBRK_EXT_IMUX29" + ], + [ + "GTPE2_IMUX30_10", + "VBRK_EXT_IMUX30" + ], + [ + "GTPE2_IMUX31_10", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_IMUX32_10", + "VBRK_EXT_IMUX32" + ], + [ + "GTPE2_IMUX33_10", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX34_10", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_IMUX35_10", + "VBRK_EXT_IMUX35" + ], + [ + "GTPE2_IMUX36_10", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX37_10", + "VBRK_EXT_IMUX37" + ], [ "GTPE2_IMUX38_10", "VBRK_EXT_IMUX38" ], [ - "GTPE2_IMUX41_10", - "VBRK_EXT_IMUX41" - ] - ] - }, - { - "grid_deltas": [ - 1, - 3 - ], - "tile_types": [ - "PCIE_INT_INTERFACE_R", - "PCIE_TOP" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_LOGIC_OUTS_B5", - "PCIE_LOGIC_OUTS_B5_R_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT35", - "PCIE_IMUX35_R_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT22", - "PCIE_IMUX22_R_3" - ], - [ - "INT_INTERFACE_EL1BEG2", - "PCIE_EL1BEG2_3" - ], - [ - "INT_INTERFACE_SW4A2", - "PCIE_SW4A2_3" - ], - [ - "INT_INTERFACE_WW4B3", - "PCIE_WW4B3_3" - ], - [ - "INT_INTERFACE_BYP6", - "PCIE_BYP6_R_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B11", - "PCIE_LOGIC_OUTS_B11_R_3" - ], - [ - "INT_INTERFACE_WL1END2", - "PCIE_WL1END2_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT28", - "PCIE_IMUX28_R_3" - ], - [ - "INT_INTERFACE_WR1END2", - "PCIE_WR1END2_3" - ], - [ - "INT_INTERFACE_ER1BEG2", - "PCIE_ER1BEG2_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT23", - "PCIE_IMUX23_R_3" - ], - [ - "INT_INTERFACE_WW4A2", - "PCIE_WW4A2_3" - ], - [ - "INT_INTERFACE_WW4C0", - "PCIE_WW4C0_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B21", - "PCIE_LOGIC_OUTS_B21_R_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT5", - "PCIE_IMUX5_R_3" - ], - [ - "INT_INTERFACE_NW4END3", - "PCIE_NW4END3_3" - ], - [ - "INT_INTERFACE_SW4END1", - "PCIE_SW4END1_3" - ], - [ - "INT_INTERFACE_WW4B1", - "PCIE_WW4B1_3" - ], - [ - "INT_INTERFACE_EE2BEG3", - "PCIE_EE2BEG3_3" - ], - [ - "INT_INTERFACE_FAN6", - "PCIE_FAN6_R_3" - ], - [ - "INT_INTERFACE_LH1", - "PCIE_LH1_3" - ], - [ - "INT_INTERFACE_WW2END1", - "PCIE_WW2END1_3" - ], - [ - "INT_INTERFACE_FAN3", - "PCIE_FAN3_R_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT14", - "PCIE_IMUX14_R_3" - ], - [ - "INT_INTERFACE_WL1END3", - "PCIE_WL1END3_3" - ], - [ - "INT_INTERFACE_WW4END1", - "PCIE_WW4END1_3" - ], - [ - "INT_INTERFACE_SE2A2", - "PCIE_SE2A2_3" - ], - [ - "INT_INTERFACE_EE2A1", - "PCIE_EE2A1_3" - ], - [ - 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"VBRK_NE2A0" - ], - [ - "CMT_TOP_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_WL1END0_4", - "VBRK_WL1END0" + "GTPE2_LOGIC_OUTS_B12_10", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "CMT_TOP_WR1END1_4", - "VBRK_WR1END1" + "GTPE2_LOGIC_OUTS_B13_10", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "CMT_TOP_SW4A0_4", - "VBRK_SW4A0" + "GTPE2_LOGIC_OUTS_B14_10", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "CMT_TOP_NW4END0_4", - "VBRK_NW4END0" + "GTPE2_LOGIC_OUTS_B16_10", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "CMT_TOP_WW4END1_4", - "VBRK_WW4END1" + "GTPE2_LOGIC_OUTS_B17_10", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "CMT_TOP_WW4END3_4", - "VBRK_WW4END3" + "GTPE2_LOGIC_OUTS_B19_10", + "VBRK_EXT_LOGIC_OUTS_B19" ], [ - "CMT_TOP_NE2A1_4", - "VBRK_NE2A1" + "GTPE2_LOGIC_OUTS_B22_10", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "CMT_TOP_SE4BEG3_4", - "VBRK_SE4BEG3" + "GTPE2_LOGIC_OUTS_B23_10", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }, @@ -303061,3737 +342277,713 @@ -4 ], "tile_types": [ - "CMT_TOP_L_UPPER_T", - "VBRK" + "GTP_CHANNEL_0", + "VBRK_EXT" ], "wire_pairs": [ [ - "CMT_TOP_NE4BEG3_9", - "VBRK_NE4BEG3" + "GTPE2_BYP0_9", + "VBRK_EXT_BYP0" ], [ - "CMT_TOP_WW4C3_9", - "VBRK_WW4C3" + "GTPE2_BYP1_9", + "VBRK_EXT_BYP1" ], [ - "CMT_TOP_LH10_9", - "VBRK_LH10" + "GTPE2_BYP2_9", + "VBRK_EXT_BYP2" ], [ - "CMT_TOP_WW4C0_9", - "VBRK_WW4C0" + "GTPE2_BYP3_9", + "VBRK_EXT_BYP3" ], [ - "CMT_TOP_NE4C2_9", - "VBRK_NE4C2" + "GTPE2_BYP4_9", + "VBRK_EXT_BYP4" ], [ - "CMT_TOP_SW4A2_9", - "VBRK_SW4A2" + "GTPE2_BYP5_9", + "VBRK_EXT_BYP5" ], [ - "CMT_TOP_NW4A0_9", - "VBRK_NW4A0" + "GTPE2_BYP6_9", + "VBRK_EXT_BYP6" ], [ - "CMT_TOP_EE2A1_9", - "VBRK_EE2A1" + "GTPE2_BYP7_9", + "VBRK_EXT_BYP7" ], [ - "CMT_TOP_WW2END0_9", - "VBRK_WW2END0" + "GTPE2_CLK0_9", + "VBRK_EXT_CLK0" ], [ - "CMT_TOP_LH3_9", - "VBRK_LH3" + "GTPE2_CLK1_9", + "VBRK_EXT_CLK1" ], [ - "CMT_TOP_LH1_9", - "VBRK_LH1" + "GTPE2_CTRL0_9", + "VBRK_EXT_CTRL0" ], [ - "CMT_TOP_SE4BEG3_9", - "VBRK_SE4BEG3" + "GTPE2_CTRL1_9", + "VBRK_EXT_CTRL1" ], [ - "CMT_TOP_NW4A1_9", - "VBRK_NW4A1" + "GTPE2_FAN0_9", + "VBRK_EXT_FAN0" ], [ - "CMT_TOP_WW2END2_9", - "VBRK_WW2END2" + "GTPE2_FAN1_9", + "VBRK_EXT_FAN1" ], [ - "CMT_TOP_SE4C3_9", - "VBRK_SE4C3" + "GTPE2_FAN2_9", + "VBRK_EXT_FAN2" ], [ - "CMT_TOP_SE4C1_9", - "VBRK_SE4C1" + "GTPE2_FAN3_9", + "VBRK_EXT_FAN3" ], [ - "CMT_TOP_SE4BEG0_9", - "VBRK_SE4BEG0" + "GTPE2_FAN4_9", + "VBRK_EXT_FAN4" ], [ - "CMT_TOP_EE2A0_9", - "VBRK_EE2A0" + "GTPE2_FAN5_9", + "VBRK_EXT_FAN5" ], [ - "CMT_TOP_EE2A3_9", - "VBRK_EE2A3" + "GTPE2_FAN6_9", + "VBRK_EXT_FAN6" ], [ - "CMT_TOP_NW2A0_9", - "VBRK_NW2A0" + "GTPE2_FAN7_9", + "VBRK_EXT_FAN7" ], [ - "CMT_TOP_NW4A3_9", - "VBRK_NW4A3" + "GTPE2_IMUX0_9", + "VBRK_EXT_IMUX0" ], [ - "CMT_TOP_NW4A2_9", - "VBRK_NW4A2" + "GTPE2_IMUX1_9", + "VBRK_EXT_IMUX1" ], [ - "CMT_TOP_NW4END3_9", - "VBRK_NW4END3" + "GTPE2_IMUX2_9", + "VBRK_EXT_IMUX2" ], [ - "CMT_TOP_LH11_9", - "VBRK_LH11" + "GTPE2_IMUX3_9", + "VBRK_EXT_IMUX3" ], [ - "CMT_TOP_WW4END1_9", - "VBRK_WW4END1" + "GTPE2_IMUX4_9", + "VBRK_EXT_IMUX4" ], [ - "CMT_TOP_NW2A1_9", - "VBRK_NW2A1" + "GTPE2_IMUX5_9", + "VBRK_EXT_IMUX5" ], [ - "CMT_TOP_WW4A0_9", - "VBRK_WW4A0" + "GTPE2_IMUX6_9", + "VBRK_EXT_IMUX6" ], [ - "CMT_TOP_EE4A2_9", - "VBRK_EE4A2" + "GTPE2_IMUX7_9", + "VBRK_EXT_IMUX7" ], [ - "CMT_TOP_WW2END1_9", - "VBRK_WW2END1" + "GTPE2_IMUX8_9", + "VBRK_EXT_IMUX8" ], [ - "CMT_TOP_WW4C1_9", - "VBRK_WW4C1" + "GTPE2_IMUX9_9", + "VBRK_EXT_IMUX9" ], [ - "CMT_TOP_WW4A3_9", - "VBRK_WW4A3" + "GTPE2_IMUX10_9", + "VBRK_EXT_IMUX10" ], [ - "CMT_TOP_EE4BEG3_9", - "VBRK_EE4BEG3" + "GTPE2_IMUX11_9", + "VBRK_EXT_IMUX11" ], [ - "CMT_TOP_WW4B0_9", - "VBRK_WW4B0" + "GTPE2_IMUX12_9", + "VBRK_EXT_IMUX12" ], [ - "CMT_TOP_WR1END1_9", - "VBRK_WR1END1" + "GTPE2_IMUX13_9", + "VBRK_EXT_IMUX13" ], [ - "CMT_TOP_ER1BEG2_9", - "VBRK_ER1BEG2" + "GTPE2_IMUX14_9", + "VBRK_EXT_IMUX14" ], [ - "CMT_TOP_WW4END3_9", - "VBRK_WW4END3" + "GTPE2_IMUX15_9", + "VBRK_EXT_IMUX15" ], [ - "CMT_TOP_WR1END3_9", - "VBRK_WR1END3" + "GTPE2_IMUX16_9", + "VBRK_EXT_IMUX16" ], [ - "CMT_TOP_WW4A1_9", - "VBRK_WW4A1" + "GTPE2_IMUX17_9", + "VBRK_EXT_IMUX17" ], [ - "CMT_TOP_LH8_9", - "VBRK_LH8" + "GTPE2_IMUX18_9", + "VBRK_EXT_IMUX18" ], [ - "CMT_TOP_SW4END2_9", - "VBRK_SW4END2" + "GTPE2_IMUX19_9", + "VBRK_EXT_IMUX19" ], [ - "CMT_TOP_WW4END2_9", - "VBRK_WW4END2" + "GTPE2_IMUX20_9", + "VBRK_EXT_IMUX20" ], [ - "CMT_TOP_SW4END3_9", - "VBRK_SW4END3" + "GTPE2_IMUX21_9", + "VBRK_EXT_IMUX21" ], [ - "CMT_TOP_WW2A2_9", - "VBRK_WW2A2" + "GTPE2_IMUX22_9", + "VBRK_EXT_IMUX22" ], [ - "CMT_TOP_WW2A3_9", - "VBRK_WW2A3" + "GTPE2_IMUX23_9", + "VBRK_EXT_IMUX23" ], [ - "CMT_TOP_EL1BEG2_9", - "VBRK_EL1BEG2" + "GTPE2_IMUX24_9", + "VBRK_EXT_IMUX24" ], [ - "CMT_TOP_WL1END3_9", - "VBRK_WL1END3" + "GTPE2_IMUX25_9", + "VBRK_EXT_IMUX25" ], [ - "CMT_TOP_WR1END2_9", - "VBRK_WR1END2" + "GTPE2_IMUX26_9", + "VBRK_EXT_IMUX26" ], [ - "CMT_TOP_SE4BEG2_9", - "VBRK_SE4BEG2" + "GTPE2_IMUX27_9", + "VBRK_EXT_IMUX27" ], [ - "CMT_TOP_NW4END1_9", - "VBRK_NW4END1" + "GTPE2_IMUX28_9", + "VBRK_EXT_IMUX28" ], [ - "CMT_TOP_NW2A2_9", - "VBRK_NW2A2" + "GTPE2_IMUX29_9", + "VBRK_EXT_IMUX29" ], [ - "CMT_TOP_SE2A3_9", - "VBRK_SE2A3" + "GTPE2_IMUX30_9", + "VBRK_EXT_IMUX30" ], [ - "CMT_TOP_EE4B0_9", - "VBRK_EE4B0" + "GTPE2_IMUX31_9", + "VBRK_EXT_IMUX31" ], [ - "CMT_TOP_SW4A1_9", - "VBRK_SW4A1" + "GTPE2_IMUX32_9", + "VBRK_EXT_IMUX32" ], [ - "CMT_TOP_SE2A2_9", - "VBRK_SE2A2" + "GTPE2_IMUX33_9", + "VBRK_EXT_IMUX33" ], [ - "CMT_TOP_WL1END0_9", - "VBRK_WL1END0" + "GTPE2_IMUX34_9", + "VBRK_EXT_IMUX34" ], [ - "CMT_TOP_NW2A3_9", - "VBRK_NW2A3" + "GTPE2_IMUX35_9", + "VBRK_EXT_IMUX35" ], [ - "CMT_TOP_WW4C2_9", - "VBRK_WW4C2" + "GTPE2_IMUX36_9", + "VBRK_EXT_IMUX36" ], [ - "CMT_TOP_NE4C3_9", - "VBRK_NE4C3" + "GTPE2_IMUX37_9", + "VBRK_EXT_IMUX37" ], [ - "CMT_TOP_SW4END1_9", - "VBRK_SW4END1" + "GTPE2_IMUX38_9", + "VBRK_EXT_IMUX38" ], [ - "CMT_TOP_NW4END2_9", - "VBRK_NW4END2" + "GTPE2_IMUX39_9", + "VBRK_EXT_IMUX39" ], [ - "CMT_TOP_SW2A2_9", - "VBRK_SW2A2" + "GTPE2_IMUX40_9", + "VBRK_EXT_IMUX40" ], [ - "CMT_TOP_ER1BEG3_9", - "VBRK_ER1BEG3" + "GTPE2_IMUX41_9", + "VBRK_EXT_IMUX41" ], [ - "CMT_TOP_NE2A1_9", - "VBRK_NE2A1" + "GTPE2_IMUX42_9", + "VBRK_EXT_IMUX42" ], [ - "CMT_TOP_EE4BEG2_9", - "VBRK_EE4BEG2" + "GTPE2_IMUX43_9", + "VBRK_EXT_IMUX43" ], [ - "CMT_TOP_SW2A0_9", - "VBRK_SW2A0" + "GTPE2_IMUX44_9", + "VBRK_EXT_IMUX44" ], [ - "CMT_TOP_LH7_9", - "VBRK_LH7" + "GTPE2_IMUX45_9", + "VBRK_EXT_IMUX45" ], [ - "CMT_TOP_WW2END3_9", - "VBRK_WW2END3" + "GTPE2_IMUX46_9", + "VBRK_EXT_IMUX46" ], [ - "CMT_TOP_NE4C0_9", - "VBRK_NE4C0" + "GTPE2_IMUX47_9", + "VBRK_EXT_IMUX47" ], [ - "CMT_TOP_EE4C3_9", - "VBRK_EE4C3" + "GTPE2_LOGIC_OUTS_B0_9", + "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "CMT_TOP_WW2A0_9", - "VBRK_WW2A0" + "GTPE2_LOGIC_OUTS_B1_9", + "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "CMT_TOP_WL1END1_9", - "VBRK_WL1END1" + "GTPE2_LOGIC_OUTS_B2_9", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ - "CMT_TOP_NE4BEG2_9", - "VBRK_NE4BEG2" + "GTPE2_LOGIC_OUTS_B3_9", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "CMT_TOP_SW4A0_9", - "VBRK_SW4A0" + "GTPE2_LOGIC_OUTS_B4_9", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "CMT_TOP_WW4END0_9", - "VBRK_WW4END0" + "GTPE2_LOGIC_OUTS_B5_9", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "CMT_TOP_SE2A1_9", - "VBRK_SE2A1" + "GTPE2_LOGIC_OUTS_B7_9", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "CMT_TOP_EE2BEG3_9", - "VBRK_EE2BEG3" + "GTPE2_LOGIC_OUTS_B9_9", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "CMT_TOP_EE2BEG1_9", - "VBRK_EE2BEG1" + "GTPE2_LOGIC_OUTS_B10_9", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "CMT_TOP_WR1END0_9", - "VBRK_WR1END0" + "GTPE2_LOGIC_OUTS_B12_9", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "CMT_TOP_WW4B1_9", - "VBRK_WW4B1" + "GTPE2_LOGIC_OUTS_B13_9", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "CMT_TOP_SW2A1_9", - "VBRK_SW2A1" + "GTPE2_LOGIC_OUTS_B14_9", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "CMT_TOP_NE4BEG1_9", - "VBRK_NE4BEG1" + "GTPE2_LOGIC_OUTS_B15_9", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "CMT_TOP_EE4C2_9", - "VBRK_EE4C2" + "GTPE2_LOGIC_OUTS_B16_9", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "CMT_TOP_ER1BEG1_9", - "VBRK_ER1BEG1" + "GTPE2_LOGIC_OUTS_B18_9", + "VBRK_EXT_LOGIC_OUTS_B18" ], [ - "CMT_TOP_EE2A2_9", - "VBRK_EE2A2" + "GTPE2_LOGIC_OUTS_B20_9", + "VBRK_EXT_LOGIC_OUTS_B20" ], [ - "CMT_TOP_LH9_9", - "VBRK_LH9" + "GTPE2_LOGIC_OUTS_B22_9", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "CMT_TOP_EE4B2_9", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_NE4BEG0_9", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_NW4END0_9", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_NE2A3_9", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_LH12_9", - "VBRK_LH12" - ], - [ - "CMT_TOP_EL1BEG1_9", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_EE2BEG0_9", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_SE4BEG1_9", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_NE4C1_9", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_EE4C1_9", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_LH4_9", - "VBRK_LH4" - ], - [ - "CMT_TOP_EE4A1_9", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_NE2A2_9", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_EE4B3_9", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_EE4BEG0_9", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_EL1BEG3_9", - "VBRK_EL1BEG3" - ], - [ - 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"CMT_TOP_LH7_8", - "VBRK_LH7" + "GTPE2_IMUX23_8", + "VBRK_EXT_IMUX23" ], [ - "CMT_TOP_EE2BEG0_8", - "VBRK_EE2BEG0" + "GTPE2_IMUX24_8", + "VBRK_EXT_IMUX24" ], [ - "CMT_TOP_SE4BEG3_8", - "VBRK_SE4BEG3" + "GTPE2_IMUX25_8", + "VBRK_EXT_IMUX25" ], [ - "CMT_TOP_WW4C2_8", - "VBRK_WW4C2" + "GTPE2_IMUX26_8", + "VBRK_EXT_IMUX26" ], [ - "CMT_TOP_SW2A2_8", - "VBRK_SW2A2" + "GTPE2_IMUX27_8", + "VBRK_EXT_IMUX27" ], [ - "CMT_TOP_WW4C1_8", - "VBRK_WW4C1" + "GTPE2_IMUX28_8", + "VBRK_EXT_IMUX28" ], [ - "CMT_TOP_WL1END2_8", - "VBRK_WL1END2" + "GTPE2_IMUX29_8", + "VBRK_EXT_IMUX29" ], [ - "CMT_TOP_WW2END0_8", - "VBRK_WW2END0" + "GTPE2_IMUX30_8", + "VBRK_EXT_IMUX30" ], [ - "CMT_TOP_SW4A0_8", - "VBRK_SW4A0" + "GTPE2_IMUX31_8", + "VBRK_EXT_IMUX31" ], [ - "CMT_TOP_NW2A0_8", - "VBRK_NW2A0" + "GTPE2_IMUX32_8", + "VBRK_EXT_IMUX32" ], [ - "CMT_TOP_WL1END0_8", - "VBRK_WL1END0" + "GTPE2_IMUX33_8", + "VBRK_EXT_IMUX33" ], [ - "CMT_TOP_EE4A3_8", - "VBRK_EE4A3" + "GTPE2_IMUX34_8", + "VBRK_EXT_IMUX34" ], [ - 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"IOI_BYP3_1", - "TERM_INT_BYP3" - ], - [ - "IOI_LOGIC_OUTS8_1", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_IMUX46_1", - "TERM_INT_IMUX46" - ], - [ - "IOI_BLOCK_OUTS0_1", - "TERM_INT_BLOCK_OUTS_L_B0" - ], - [ - "IOI_CLK0_1", - "TERM_INT_CLK0" - ], - [ - "IOI_LOGIC_OUTS19_1", - "TERM_INT_LOGIC_OUTS_L_B19" - ], - [ - "IOI_IMUX39_1", - "TERM_INT_IMUX39" - ], - [ - "IOI_IMUX42_1", - "TERM_INT_IMUX42" - ], - [ - "IOI_IMUX27_1", - "TERM_INT_IMUX27" - ], - [ - "IOI_IMUX12_1", - "TERM_INT_IMUX12" - ], - [ - "IOI_IMUX8_1", - "TERM_INT_IMUX8" - ], - [ - "IOI_IMUX14_1", - "TERM_INT_IMUX14" - ], - [ - "IOI_IMUX19_1", - "TERM_INT_IMUX19" - ], - [ - "IOI_BYP7_1", - "TERM_INT_BYP7" - ], - [ - "IOI_BYP2_1", - "TERM_INT_BYP2" - ], - [ - "IOI_LOGIC_OUTS3_1", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_LOGIC_OUTS0_1", - "TERM_INT_LOGIC_OUTS_L_B0" - ], - [ - "IOI_IMUX29_1", - "TERM_INT_IMUX29" - ], - [ - "IOI_IMUX10_1", - "TERM_INT_IMUX10" - ], - [ - "IOI_LOGIC_OUTS23_1", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "IOI_IMUX2_1", - "TERM_INT_IMUX2" - ], - [ - "IOI_BYP5_1", - "TERM_INT_BYP5" - ], - [ - "IOI_CTRL1_1", - "TERM_INT_CTRL1" - ], - [ - "IOI_FAN2_1", - "TERM_INT_FAN2" - ], - [ - "IOI_IMUX20_1", - "TERM_INT_IMUX20" - ], - [ - "IOI_BYP1_1", - "TERM_INT_BYP1" - ], - [ - "IOI_IMUX21_1", - "TERM_INT_IMUX21" - ], - [ - "IOI_IMUX26_1", - "TERM_INT_IMUX26" - ], - [ - "IOI_IMUX32_1", - "TERM_INT_IMUX32" - ], - [ - "IOI_IMUX35_1", - "TERM_INT_IMUX35" - ], - [ - "IOI_FAN6_1", - "TERM_INT_FAN6" - ], - [ - "IOI_IMUX36_1", - "TERM_INT_IMUX36" - ], - [ - "IOI_CTRL0_1", - "TERM_INT_CTRL0" - ], - [ - "IOI_IMUX18_1", - "TERM_INT_IMUX18" - ], - [ - "IOI_LOGIC_OUTS11_1", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "IOI_FAN5_1", - "TERM_INT_FAN5" - ], - [ - "IOI_PHASER_TO_IO_ICLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" - ], - [ - "IOI_IMUX9_1", - "TERM_INT_IMUX9" - ], - [ - "IOI_IMUX40_1", - "TERM_INT_IMUX40" - ], - [ - "IOI_IMUX3_1", - "TERM_INT_IMUX3" - ], - [ - "IOI_IMUX7_1", - "TERM_INT_IMUX7" - ], - [ - "IOI_IMUX0_1", - "TERM_INT_IMUX0" - ], - [ - "IOI_FAN0_1", - "TERM_INT_FAN0" - ], - [ - "IOI_IMUX37_1", - "TERM_INT_IMUX37" - ], - [ - "IOI_PHASER_TO_IO_OCLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "IOI_LOGIC_OUTS14_1", - "TERM_INT_LOGIC_OUTS_L_B14" - ], - [ - "IOI_FAN1_1", - "TERM_INT_FAN1" - ], - [ - "IOI_FAN4_1", - "TERM_INT_FAN4" - ], - [ - "IOI_IMUX1_1", - "TERM_INT_IMUX1" - ], - [ - "IOI_LOGIC_OUTS10_1", - "TERM_INT_LOGIC_OUTS_L_B10" - ], - [ - "IOI_IMUX33_1", - "TERM_INT_IMUX33" - ], - [ - "IOI_IMUX34_1", - "TERM_INT_IMUX34" - ], - [ - "IOI_IMUX4_1", - "TERM_INT_IMUX4" - ], - [ - "IOI_IMUX38_1", - "TERM_INT_IMUX38" - ], - [ - "IOI_IMUX15_1", - "TERM_INT_IMUX15" - ], - [ - "IOI_IMUX30_1", - "TERM_INT_IMUX30" - ], - [ - "IOI_IMUX11_1", - "TERM_INT_IMUX11" - ], - [ - "IOI_IMUX5_1", - "TERM_INT_IMUX5" - ], - [ - "IOI_IMUX28_1", - "TERM_INT_IMUX28" - ], - [ - "IOI_CLK1_1", - "TERM_INT_CLK1" - ], - [ - "IOI_IMUX16_1", - "TERM_INT_IMUX16" - ], - [ - "IOI_IMUX43_1", - "TERM_INT_IMUX43" - ], - [ - "IOI_IMUX31_1", - "TERM_INT_IMUX31" - ], - [ - "IOI_IMUX13_1", - "TERM_INT_IMUX13" - ], - [ - "IOI_IMUX44_1", - "TERM_INT_IMUX44" - ], - [ - "IOI_LOGIC_OUTS18_1", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "IOI_IMUX22_1", - "TERM_INT_IMUX22" - ], - [ - "IOI_LOGIC_OUTS7_1", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_FAN3_1", - "TERM_INT_FAN3" - ], - [ - "IOI_LOGIC_OUTS5_1", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_PHASER_TO_IO_OCLK_0", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_LOGIC_OUTS20_1", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_IMUX47_1", - "TERM_INT_IMUX47" - ], - [ - "IOI_IMUX17_1", - "TERM_INT_IMUX17" - ], - [ - "IOI_LOGIC_OUTS15_1", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_BLOCK_OUTS2_1", - "TERM_INT_BLOCK_OUTS_L_B2" - ], - [ - "IOI_PHASER_TO_IO_ICLK_0", - "L_TERM_INT_PHASER_TO_IO_ICLK" - ], - [ - "IOI_BYP4_1", - "TERM_INT_BYP4" - ], - [ - "IOI_IMUX45_1", - "TERM_INT_IMUX45" - ], - [ - "IOI_FAN7_1", - "TERM_INT_FAN7" - ], - [ - "IOI_BYP0_1", - "TERM_INT_BYP0" - ], - [ - "IOI_IMUX23_1", - "TERM_INT_IMUX23" - ], - [ - "IOI_LOGIC_OUTS1_1", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_IMUX25_1", - "TERM_INT_IMUX25" - ], - [ - "IOI_LOGIC_OUTS9_1", - "TERM_INT_LOGIC_OUTS_L_B9" - ], - [ - "IOI_LOGIC_OUTS2_1", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "IOI_IMUX6_1", - "TERM_INT_IMUX6" - ], - [ - "IOI_BYP6_1", - "TERM_INT_BYP6" - ], - [ - "IOI_IMUX41_1", - "TERM_INT_IMUX41" - ] - ] - }, - { - "grid_deltas": [ - 1, - -6 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW4A1_7", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_WW2A1_7", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WW4A0_7", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WW4C1_7", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_LH4_7", - "VBRK_LH4" - ], - [ - "CMT_TOP_WW4B1_7", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_LH5_7", - "VBRK_LH5" - ], - [ - "CMT_TOP_NE4BEG2_7", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_EE4BEG2_7", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_EL1BEG3_7", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_NE4BEG3_7", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_ER1BEG1_7", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_WW4END1_7", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_LH10_7", - "VBRK_LH10" - ], - [ - "CMT_TOP_EE4A3_7", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_SW2A1_7", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_EE4A2_7", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_SW4END2_7", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_SW4END3_7", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_NE2A3_7", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_NW4END0_7", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_SW4A1_7", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_WL1END2_7", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_WW2A0_7", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_LH3_7", - "VBRK_LH3" - ], - [ - "CMT_TOP_NW4END3_7", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW2END2_7", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_EE2BEG1_7", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_ER1BEG0_7", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NW2A3_7", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_LH6_7", - "VBRK_LH6" - ], - [ - "CMT_TOP_NE2A0_7", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_ER1BEG3_7", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_NE2A2_7", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_LH12_7", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE2BEG2_7", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_EE4C0_7", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_NE4BEG0_7", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_NW2A1_7", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_WW4A2_7", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_EE2A0_7", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_EE4C3_7", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_WR1END1_7", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_LH11_7", - "VBRK_LH11" - ], - [ - "CMT_TOP_NE4C0_7", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_EE4B0_7", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_NW4END1_7", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_WW2END1_7", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_NE2A1_7", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_LH9_7", - "VBRK_LH9" - ], - [ - "CMT_TOP_NW2A0_7", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_NW4A1_7", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4B2_7", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_WW2END3_7", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_NE4BEG1_7", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_WW4END3_7", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_EL1BEG2_7", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_SW2A0_7", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_MONITOR_P_7", - "VBRK_MONITOR_P" - ], - [ - "CMT_TOP_SW4A3_7", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_LH7_7", - "VBRK_LH7" - ], - [ - "CMT_TOP_EE4BEG0_7", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_EE2A2_7", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_SW4END0_7", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_EL1BEG0_7", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WL1END0_7", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_EE4B3_7", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_EE4B2_7", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_EE2A3_7", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_NE4C3_7", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SE2A0_7", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_LH8_7", - "VBRK_LH8" - ], - [ - "CMT_TOP_EE2BEG3_7", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_SW4A2_7", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_WW4A3_7", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_SE4BEG1_7", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_EE4C2_7", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_ER1BEG2_7", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_LH2_7", - "VBRK_LH2" - ], - [ - "CMT_TOP_EE4BEG1_7", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_WW4B3_7", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WW4END2_7", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_WW4B0_7", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_SE2A2_7", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_EE4A0_7", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_EE4B1_7", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_EE2BEG0_7", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_NW4A0_7", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_SE4BEG2_7", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_EL1BEG1_7", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_MONITOR_N_7", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_EE4C1_7", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_WL1END3_7", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_WR1END3_7", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_NW2A2_7", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WR1END2_7", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW4C0_7", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_EE2A1_7", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_SW4A0_7", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_SW2A3_7", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_NE4C1_7", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_SE4BEG3_7", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_SW4END1_7", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_SE2A1_7", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_LH1_7", - "VBRK_LH1" - ], - [ - "CMT_TOP_WW4C3_7", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_WR1END0_7", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_NW4END2_7", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_WW4END0_7", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_WW2A2_7", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_SE2A3_7", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_SE4BEG0_7", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_SE4C1_7", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_NE4C2_7", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_WW4C2_7", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_NW4A3_7", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_SE4C0_7", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_EE4BEG3_7", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_WW2A3_7", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE4A1_7", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_WL1END1_7", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_WW2END0_7", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_SW2A2_7", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_SE4C2_7", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_NW4A2_7", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_SE4C3_7", - "VBRK_SE4C3" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_FEEDTHRU_1", - "HCLK_VFRAME" - ], - "wire_pairs": [ - [ - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_VFRAME_CK_IN10" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFRCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_VFRAME_CK_IN7" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_VFRAME_CK_IN6" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_VFRAME_CK_BUFHCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK8" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_VFRAME_CK_IN3" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_VFRAME_CK_BUFRCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_VFRAME_CK_BUFHCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_VFRAME_CK_BUFHCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_VFRAME_CK_IN8" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN9", - "HCLK_VFRAME_CK_IN9" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_VFRAME_CK_IN5" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_VFRAME_CK_IN11" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_VFRAME_CK_BUFRCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_VFRAME_CK_IN12" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_VFRAME_CK_BUFHCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_VFRAME_CK_BUFHCLK10" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_VFRAME_CK_IN1" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_VFRAME_CK_BUFHCLK11" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_VFRAME_CK_BUFHCLK6" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_VFRAME_CK_IN0" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_VFRAME_CK_BUFHCLK5" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_VFRAME_CK_BUFRCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK4" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_VFRAME_CK_BUFHCLK9" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_VFRAME_CK_IN4" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_VFRAME_CK_BUFHCLK7" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_VFRAME_CK_IN2" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_VFRAME_CK_IN13" + "GTPE2_LOGIC_OUTS_B23_8", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }, @@ -306801,4469 +342993,349 @@ -2 ], "tile_types": [ - "GTP_CHANNEL_2", + "GTP_CHANNEL_0", "VBRK_EXT" ], "wire_pairs": [ [ - "GTPE2_IMUX39_7", - "VBRK_EXT_IMUX39" + "GTPE2_BYP0_7", + "VBRK_EXT_BYP0" ], [ "GTPE2_BYP1_7", "VBRK_EXT_BYP1" ], - [ - "GTPE2_BYP4_7", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_LOGIC_OUTS_B12_7", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_BYP6_7", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX45_7", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX37_7", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_LOGIC_OUTS_B5_7", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_LOGIC_OUTS_B1_7", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX14_7", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_FAN2_7", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX17_7", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX22_7", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX1_7", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_LOGIC_OUTS_B2_7", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_IMUX20_7", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX40_7", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX3_7", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX42_7", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_CLK0_7", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_LOGIC_OUTS_B7_7", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX31_7", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX21_7", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX30_7", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX6_7", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX46_7", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_BYP0_7", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX34_7", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX29_7", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B18_7", - "VBRK_EXT_LOGIC_OUTS_B18" - ], [ "GTPE2_BYP2_7", "VBRK_EXT_BYP2" ], - [ - "GTPE2_IMUX18_7", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_LOGIC_OUTS_B3_7", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_LOGIC_OUTS_B9_7", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_BYP5_7", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_FAN6_7", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX24_7", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_CTRL1_7", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX13_7", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_LOGIC_OUTS_B19_7", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_FAN7_7", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX10_7", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX8_7", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_FAN4_7", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX47_7", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX33_7", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_LOGIC_OUTS_B14_7", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX19_7", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX12_7", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX44_7", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_LOGIC_OUTS_B16_7", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_LOGIC_OUTS_B13_7", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX43_7", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX35_7", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_LOGIC_OUTS_B21_7", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_IMUX26_7", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B15_7", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_IMUX25_7", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_FAN1_7", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_FAN5_7", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_FAN0_7", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX11_7", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX38_7", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_FAN3_7", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX5_7", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX2_7", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX28_7", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX23_7", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX16_7", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX15_7", - "VBRK_EXT_IMUX15" - ], [ "GTPE2_BYP3_7", "VBRK_EXT_BYP3" ], + [ + "GTPE2_BYP4_7", + "VBRK_EXT_BYP4" + ], + [ + "GTPE2_BYP5_7", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_BYP6_7", + "VBRK_EXT_BYP6" + ], [ "GTPE2_BYP7_7", "VBRK_EXT_BYP7" ], [ - "GTPE2_IMUX36_7", - "VBRK_EXT_IMUX36" + "GTPE2_CLK0_7", + "VBRK_EXT_CLK0" ], [ - "GTPE2_IMUX0_7", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX9_7", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX41_7", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX32_7", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B0_7", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_IMUX4_7", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX27_7", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_LOGIC_OUTS_B6_7", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX7_7", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_LOGIC_OUTS_B4_7", - "VBRK_EXT_LOGIC_OUTS_B4" + "GTPE2_CLK1_7", + "VBRK_EXT_CLK1" ], [ "GTPE2_CTRL0_7", "VBRK_EXT_CTRL0" ], [ - "GTPE2_CLK1_7", - "VBRK_EXT_CLK1" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_FEEDTHRU_1", - "HCLK_FEEDTHRU_1" - ], - "wire_pairs": [ - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_FEEDTHRU_1_CK_BUFRCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_FEEDTHRU_1_CK_IN6" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_FEEDTHRU_1_CK_IN5" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_FEEDTHRU_1_CK_BUFHCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_FEEDTHRU_1_CK_IN11" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_FEEDTHRU_1_CK_IN7" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_FEEDTHRU_1_CK_BUFHCLK6" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_FEEDTHRU_1_CK_BUFHCLK5" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_FEEDTHRU_1_CK_IN13" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_FEEDTHRU_1_CK_BUFHCLK8" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_FEEDTHRU_1_CK_IN0" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_FEEDTHRU_1_CK_BUFHCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_FEEDTHRU_1_CK_IN8" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_FEEDTHRU_1_CK_BUFHCLK9" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_FEEDTHRU_1_CK_IN12" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_FEEDTHRU_1_CK_BUFRCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_FEEDTHRU_1_CK_IN1" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_FEEDTHRU_1_CK_BUFHCLK10" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_FEEDTHRU_1_CK_BUFHCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_FEEDTHRU_1_CK_BUFRCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_FEEDTHRU_1_CK_BUFHCLK7" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_FEEDTHRU_1_CK_BUFHCLK4" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_FEEDTHRU_1_CK_BUFRCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_FEEDTHRU_1_CK_BUFHCLK11" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN9", - "HCLK_FEEDTHRU_1_CK_IN9" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_FEEDTHRU_1_CK_BUFHCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_FEEDTHRU_1_CK_IN10" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_FEEDTHRU_1_CK_IN4" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_FEEDTHRU_1_CK_IN2" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_FEEDTHRU_1_CK_IN3" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_MTBF2", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_FEED_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLK_FEED_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLK_FEED_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLK_FEED_NE2A2", - "VBRK_NE2A2" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_LH3", - "VBRK_LH3" - ], - [ - "CLK_FEED_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLK_FEED_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLK_FEED_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLK_FEED_WW4C2", - "VBRK_WW4C2" - ], - [ - "CLK_FEED_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLK_FEED_EE4BEG2", - "VBRK_EE4BEG2" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLK_FEED_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLK_FEED_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLK_FEED_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLK_FEED_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLK_FEED_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_LH2", - "VBRK_LH2" - ], - [ - "CLK_FEED_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLK_FEED_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLK_FEED_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLK_FEED_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLK_FEED_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_LH12", - "VBRK_LH12" - ], - [ - "CLK_FEED_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLK_FEED_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLK_FEED_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLK_FEED_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLK_FEED_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_LH7", - "VBRK_LH7" - ], - [ - "CLK_FEED_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLK_FEED_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLK_FEED_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_LH8", - "VBRK_LH8" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_SW4END3", - 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"MONITOR_EE4B3_9", - "VFRAME_EE4B3" + "GTPE2_IMUX19_7", + "VBRK_EXT_IMUX19" ], [ - "MONITOR_IMUX14_9", - "VFRAME_IMUX14" + "GTPE2_IMUX20_7", + "VBRK_EXT_IMUX20" ], [ - "MONITOR_LH12_9", - "VFRAME_LH12" + "GTPE2_IMUX21_7", + "VBRK_EXT_IMUX21" ], [ - "MONITOR_EE4C1_9", - "VFRAME_EE4C1" + "GTPE2_IMUX22_7", + "VBRK_EXT_IMUX22" ], [ - "MONITOR_LH11_9", - "VFRAME_LH11" + "GTPE2_IMUX23_7", + "VBRK_EXT_IMUX23" ], [ - "MONITOR_IMUX26_9", - "VFRAME_IMUX26" + "GTPE2_IMUX24_7", + "VBRK_EXT_IMUX24" ], [ - "MONITOR_WW4B1_9", - "VFRAME_WW4B1" + "GTPE2_IMUX25_7", + "VBRK_EXT_IMUX25" ], [ - "MONITOR_IMUX1_9", - "VFRAME_IMUX1" + "GTPE2_IMUX26_7", + "VBRK_EXT_IMUX26" ], [ - "MONITOR_NE4C0_9", - "VFRAME_NE4C0" + "GTPE2_IMUX27_7", + "VBRK_EXT_IMUX27" ], [ - "MONITOR_WW4A0_9", - "VFRAME_WW4A0" + "GTPE2_IMUX28_7", + "VBRK_EXT_IMUX28" ], [ - "MONITOR_NE4BEG3_9", - "VFRAME_NE4BEG3" + "GTPE2_IMUX29_7", + "VBRK_EXT_IMUX29" ], [ - "MONITOR_ER1BEG2_9", - "VFRAME_ER1BEG2" + "GTPE2_IMUX30_7", + "VBRK_EXT_IMUX30" ], [ - "MONITOR_IMUX41_9", - "VFRAME_IMUX41" + "GTPE2_IMUX31_7", + "VBRK_EXT_IMUX31" ], [ - "MONITOR_CLK0_9", - "VFRAME_CLK0" + "GTPE2_IMUX32_7", + "VBRK_EXT_IMUX32" ], [ - "MONITOR_SW2A1_9", - "VFRAME_SW2A1" + "GTPE2_IMUX33_7", + "VBRK_EXT_IMUX33" ], [ - "MONITOR_LH10_9", - "VFRAME_LH10" + "GTPE2_IMUX34_7", + "VBRK_EXT_IMUX34" ], [ - "MONITOR_LH5_9", - "VFRAME_LH5" + "GTPE2_IMUX35_7", + "VBRK_EXT_IMUX35" ], [ - "MONITOR_WL1END2_9", - "VFRAME_WL1END2" + "GTPE2_IMUX36_7", + "VBRK_EXT_IMUX36" ], [ - "MONITOR_IMUX32_9", - "VFRAME_IMUX32" + "GTPE2_IMUX37_7", + "VBRK_EXT_IMUX37" ], [ - "MONITOR_SE2A0_9", - "VFRAME_SE2A0" + "GTPE2_IMUX38_7", + "VBRK_EXT_IMUX38" ], [ - "MONITOR_NE4C1_9", - "VFRAME_NE4C1" + "GTPE2_IMUX39_7", + "VBRK_EXT_IMUX39" ], [ - "MONITOR_FAN2_9", - "VFRAME_FAN2" + "GTPE2_IMUX40_7", + "VBRK_EXT_IMUX40" ], [ - "MONITOR_NE4C2_9", - "VFRAME_NE4C2" + "GTPE2_IMUX41_7", + "VBRK_EXT_IMUX41" ], [ - "MONITOR_IMUX12_9", - "VFRAME_IMUX12" + "GTPE2_IMUX42_7", + "VBRK_EXT_IMUX42" ], [ - "MONITOR_CTRL1_9", - "VFRAME_CTRL1" + "GTPE2_IMUX43_7", + "VBRK_EXT_IMUX43" ], [ - "MONITOR_IMUX44_9", - "VFRAME_IMUX44" + "GTPE2_IMUX44_7", + "VBRK_EXT_IMUX44" ], [ - "MONITOR_WW4END3_9", - "VFRAME_WW4END3" + "GTPE2_IMUX45_7", + "VBRK_EXT_IMUX45" ], [ - "MONITOR_EE4B0_9", - "VFRAME_EE4B0" + "GTPE2_IMUX46_7", + "VBRK_EXT_IMUX46" ], [ - "MONITOR_SW4END0_9", - "VFRAME_SW4END0" + "GTPE2_IMUX47_7", + "VBRK_EXT_IMUX47" ], [ - "MONITOR_WW2END3_9", - "VFRAME_WW2END3" + "GTPE2_LOGIC_OUTS_B0_7", + "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "MONITOR_LH8_9", - "VFRAME_LH8" + "GTPE2_LOGIC_OUTS_B1_7", + "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "MONITOR_EE2BEG3_9", - "VFRAME_EE2BEG3" + "GTPE2_LOGIC_OUTS_B2_7", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ - "MONITOR_SW4A2_9", - "VFRAME_SW4A2" + "GTPE2_LOGIC_OUTS_B3_7", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "MONITOR_WW4C2_9", - "VFRAME_WW4C2" + "GTPE2_LOGIC_OUTS_B4_7", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "MONITOR_IMUX17_9", - "VFRAME_IMUX17" + "GTPE2_LOGIC_OUTS_B5_7", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "MONITOR_NW4A1_9", - "VFRAME_NW4A1" + "GTPE2_LOGIC_OUTS_B6_7", + "VBRK_EXT_LOGIC_OUTS_B6" ], [ - "MONITOR_IMUX30_9", - "VFRAME_IMUX30" + "GTPE2_LOGIC_OUTS_B7_7", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "MONITOR_NE4BEG0_9", - "VFRAME_NE4BEG0" + "GTPE2_LOGIC_OUTS_B9_7", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "MONITOR_IMUX47_9", - "VFRAME_IMUX47" + "GTPE2_LOGIC_OUTS_B12_7", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "MONITOR_BYP1_9", - "VFRAME_BYP1" + "GTPE2_LOGIC_OUTS_B13_7", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "MONITOR_IMUX23_9", - "VFRAME_IMUX23" + "GTPE2_LOGIC_OUTS_B14_7", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "MONITOR_NW2A0_9", - "VFRAME_NW2A0" + "GTPE2_LOGIC_OUTS_B15_7", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "MONITOR_IMUX24_9", - "VFRAME_IMUX24" + "GTPE2_LOGIC_OUTS_B16_7", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "MONITOR_SE4BEG2_9", - "VFRAME_SE4BEG2" + "GTPE2_LOGIC_OUTS_B18_7", + "VBRK_EXT_LOGIC_OUTS_B18" ], [ - "MONITOR_WW4B3_9", - "VFRAME_WW4B3" + "GTPE2_LOGIC_OUTS_B19_7", + "VBRK_EXT_LOGIC_OUTS_B19" ], [ - "MONITOR_EL1BEG1_9", - "VFRAME_EL1BEG1" + "GTPE2_LOGIC_OUTS_B21_7", + "VBRK_EXT_LOGIC_OUTS_B21" ] ] }, @@ -311273,1053 +343345,357 @@ -1 ], "tile_types": [ - "GTP_CHANNEL_2", + "GTP_CHANNEL_0", "VBRK_EXT" ], "wire_pairs": [ - [ - "GTPE2_BYP5_6", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX17_6", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX40_6", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX16_6", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX0_6", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B7_6", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX36_6", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_IMUX26_6", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B6_6", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_LOGIC_OUTS_B14_6", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX44_6", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_LOGIC_OUTS_B13_6", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX35_6", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX13_6", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX38_6", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX8_6", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_FAN5_6", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_BYP4_6", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX9_6", - "VBRK_EXT_IMUX9" - ], [ "GTPE2_BYP0_6", "VBRK_EXT_BYP0" ], - [ - "GTPE2_BYP6_6", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_LOGIC_OUTS_B5_6", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_IMUX33_6", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX6_6", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_LOGIC_OUTS_B4_6", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_BYP2_6", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_LOGIC_OUTS_B17_6", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX31_6", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_FAN6_6", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX47_6", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX20_6", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_FAN2_6", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX1_6", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_IMUX11_6", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_LOGIC_OUTS_B23_6", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_LOGIC_OUTS_B15_6", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_CLK1_6", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX37_6", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX14_6", - "VBRK_EXT_IMUX14" - ], [ "GTPE2_BYP1_6", "VBRK_EXT_BYP1" ], [ - "GTPE2_IMUX19_6", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_CTRL0_6", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_LOGIC_OUTS_B3_6", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_IMUX41_6", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX3_6", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_LOGIC_OUTS_B22_6", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_LOGIC_OUTS_B0_6", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_LOGIC_OUTS_B9_6", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX5_6", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX15_6", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX25_6", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_FAN0_6", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_LOGIC_OUTS_B10_6", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_LOGIC_OUTS_B19_6", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_IMUX2_6", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX34_6", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX45_6", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX10_6", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX12_6", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX24_6", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_CLK0_6", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_LOGIC_OUTS_B21_6", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_IMUX30_6", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX39_6", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX32_6", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_FAN4_6", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_LOGIC_OUTS_B2_6", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_IMUX42_6", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX46_6", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_LOGIC_OUTS_B12_6", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_IMUX28_6", - "VBRK_EXT_IMUX28" + "GTPE2_BYP2_6", + "VBRK_EXT_BYP2" ], [ "GTPE2_BYP3_6", "VBRK_EXT_BYP3" ], [ - "GTPE2_IMUX23_6", - "VBRK_EXT_IMUX23" + "GTPE2_BYP4_6", + "VBRK_EXT_BYP4" ], [ - "GTPE2_IMUX27_6", - "VBRK_EXT_IMUX27" + "GTPE2_BYP5_6", + "VBRK_EXT_BYP5" ], [ - "GTPE2_CTRL1_6", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX7_6", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX4_6", - "VBRK_EXT_IMUX4" + "GTPE2_BYP6_6", + "VBRK_EXT_BYP6" ], [ "GTPE2_BYP7_6", "VBRK_EXT_BYP7" ], [ - "GTPE2_IMUX18_6", - "VBRK_EXT_IMUX18" + "GTPE2_CLK0_6", + "VBRK_EXT_CLK0" ], [ - "GTPE2_FAN7_6", - "VBRK_EXT_FAN7" + "GTPE2_CLK1_6", + "VBRK_EXT_CLK1" ], [ - "GTPE2_IMUX43_6", - "VBRK_EXT_IMUX43" + "GTPE2_CTRL0_6", + "VBRK_EXT_CTRL0" ], [ - "GTPE2_LOGIC_OUTS_B1_6", - "VBRK_EXT_LOGIC_OUTS_B1" + "GTPE2_CTRL1_6", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_FAN0_6", + "VBRK_EXT_FAN0" ], [ "GTPE2_FAN1_6", "VBRK_EXT_FAN1" ], [ - "GTPE2_IMUX29_6", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX21_6", - "VBRK_EXT_IMUX21" + "GTPE2_FAN2_6", + "VBRK_EXT_FAN2" ], [ "GTPE2_FAN3_6", "VBRK_EXT_FAN3" ], + [ + "GTPE2_FAN4_6", + "VBRK_EXT_FAN4" + ], + [ + "GTPE2_FAN5_6", + "VBRK_EXT_FAN5" + ], + [ + "GTPE2_FAN6_6", + "VBRK_EXT_FAN6" + ], + [ + "GTPE2_FAN7_6", + "VBRK_EXT_FAN7" + ], + [ + "GTPE2_IMUX0_6", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX1_6", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX2_6", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_6", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_6", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_6", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_6", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_6", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_6", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_6", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX10_6", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX11_6", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_6", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_6", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_6", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_6", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_6", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_6", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_6", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX19_6", + "VBRK_EXT_IMUX19" + ], + [ + "GTPE2_IMUX20_6", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_IMUX21_6", + "VBRK_EXT_IMUX21" + ], [ "GTPE2_IMUX22_6", "VBRK_EXT_IMUX22" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_CLB", - "HCLK_VFRAME" - ], - "wire_pairs": [ - [ - "HCLK_CLB_CK_IN0", - "HCLK_VFRAME_CK_IN0" - ], - [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_VFRAME_CK_BUFHCLK0" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_VFRAME_CK_BUFHCLK10" - ], - [ - "HCLK_CLB_CK_IN9", - "HCLK_VFRAME_CK_IN9" - ], - [ - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_VFRAME_CK_BUFRCLK2" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_VFRAME_CK_IN8" - ], - [ - "HCLK_CLB_CK_IN3", - "HCLK_VFRAME_CK_IN3" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_VFRAME_CK_IN10" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_VFRAME_CK_BUFHCLK3" - ], - [ - "HCLK_CLB_CK_IN1", - "HCLK_VFRAME_CK_IN1" - ], - [ - "HCLK_CLB_CK_IN2", - "HCLK_VFRAME_CK_IN2" - ], - [ - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK8" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_VFRAME_CK_IN4" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_VFRAME_CK_IN6" - ], - [ - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_VFRAME_CK_BUFHCLK7" - ], - [ - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFRCLK1" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_VFRAME_CK_IN13" - ], - [ - "HCLK_CLB_CK_IN7", - "HCLK_VFRAME_CK_IN7" - ], - [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_VFRAME_CK_BUFHCLK1" - ], - [ - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK4" - ], - [ - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_VFRAME_CK_BUFHCLK2" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_VFRAME_CK_IN5" - ], - [ - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_VFRAME_CK_BUFRCLK3" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_VFRAME_CK_IN12" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_VFRAME_CK_IN11" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_VFRAME_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_VFRAME_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_VFRAME_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_BUFRCLK0", - "HCLK_VFRAME_CK_BUFRCLK0" - ], - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_VFRAME_CK_BUFHCLK9" - ] - ] - }, - { - "grid_deltas": [ - 0, - 8 - ], - "tile_types": [ - "BRKH_CMT", - "CMT_TOP_R_UPPER_T" - ], - "wire_pairs": [ - [ - "BRKH_CMT_FREQ_REF_NS2", - "PLL_CLK_FREQ_BB_BUFOUT_NS2" - ], - [ - "BRKH_CMT_PHYCTRL_SYNC_BB", - "CMT_PLL_PHYCTRL_SYNC_BB_UP" - ], - [ - "BRKH_CMT_FREQ_REF_NS3", - "PLL_CLK_FREQ_BB_BUFOUT_NS3" - ], - [ - "BRKH_CMT_PHASEREF_BELOW0", - "CMT_PLL_PHASERREF0" - ], - [ - "BRKH_CMT_PHASEREF_BELOW1", - "CMT_PLL_PHASERREF1" - ], - [ - "BRKH_CMT_FREQ_REF_NS0", - "PLL_CLK_FREQ_BB_BUFOUT_NS0" - ], - [ - "BRKH_CMT_FREQ_REF_NS1", - "PLL_CLK_FREQ_BB_BUFOUT_NS1" - ], - [ - "BRKH_CMT_PHASEREF1", - "CMT_PLL_PHASERREF_ABOVE1" - ], - [ - "BRKH_CMT_PHASEREF0", - "CMT_PLL_PHASERREF_ABOVE0" - ] - ] - }, - { - "grid_deltas": [ - 1, - 1 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW4A1_7", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_WW2A1_7", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WW4A0_7", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WW4C1_7", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_LH4_7", - "VBRK_LH4" - ], - [ - "CMT_TOP_WW4B1_7", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_LH5_7", - "VBRK_LH5" - ], - [ - "CMT_TOP_NE4BEG2_7", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_EE4BEG2_7", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_EL1BEG3_7", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_NE4BEG3_7", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_ER1BEG1_7", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_WW4END1_7", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_LH10_7", - "VBRK_LH10" - ], - [ - "CMT_TOP_EE4A3_7", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_SW2A1_7", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_EE4A2_7", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_SW4END2_7", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_SW4END3_7", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_NE2A3_7", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_NW4END0_7", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_SW4A1_7", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_WL1END2_7", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_WW2A0_7", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_LH3_7", - "VBRK_LH3" - ], - [ - "CMT_TOP_NW4END3_7", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW2END2_7", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_EE2BEG1_7", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_ER1BEG0_7", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NW2A3_7", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_LH6_7", - "VBRK_LH6" - ], - [ - "CMT_TOP_NE2A0_7", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_ER1BEG3_7", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_NE2A2_7", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_LH12_7", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE2BEG2_7", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_EE4C0_7", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_NE4BEG0_7", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_NW2A1_7", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_WW4A2_7", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_EE2A0_7", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_EE4C3_7", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_WR1END1_7", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_LH11_7", - "VBRK_LH11" - ], - [ - "CMT_TOP_NE4C0_7", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_EE4B0_7", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_NW4END1_7", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_WW2END1_7", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_NE2A1_7", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_LH9_7", - "VBRK_LH9" - ], - [ - "CMT_TOP_NW2A0_7", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_NW4A1_7", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4B2_7", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_WW2END3_7", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_NE4BEG1_7", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_WW4END3_7", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_EL1BEG2_7", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_SW2A0_7", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_MONITOR_P_7", - "VBRK_MONITOR_P" - ], - [ - "CMT_TOP_SW4A3_7", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_LH7_7", - "VBRK_LH7" - ], - [ - "CMT_TOP_EE4BEG0_7", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_EE2A2_7", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_SW4END0_7", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_EL1BEG0_7", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WL1END0_7", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_EE4B3_7", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_EE4B2_7", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_EE2A3_7", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_NE4C3_7", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SE2A0_7", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_LH8_7", - "VBRK_LH8" - ], - [ - "CMT_TOP_EE2BEG3_7", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_SW4A2_7", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_WW4A3_7", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_SE4BEG1_7", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_EE4C2_7", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_ER1BEG2_7", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_LH2_7", - "VBRK_LH2" - ], - [ - "CMT_TOP_EE4BEG1_7", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_WW4B3_7", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WW4END2_7", - "VBRK_WW4END2" ], [ - "CMT_TOP_WW4B0_7", - "VBRK_WW4B0" + "GTPE2_IMUX23_6", + "VBRK_EXT_IMUX23" ], [ - "CMT_TOP_SE2A2_7", - "VBRK_SE2A2" + "GTPE2_IMUX24_6", + "VBRK_EXT_IMUX24" ], [ - "CMT_TOP_EE4A0_7", - "VBRK_EE4A0" + "GTPE2_IMUX25_6", + "VBRK_EXT_IMUX25" ], [ - "CMT_TOP_EE4B1_7", - "VBRK_EE4B1" + "GTPE2_IMUX26_6", + "VBRK_EXT_IMUX26" ], [ - "CMT_TOP_EE2BEG0_7", - "VBRK_EE2BEG0" + "GTPE2_IMUX27_6", + "VBRK_EXT_IMUX27" ], [ - "CMT_TOP_NW4A0_7", - "VBRK_NW4A0" + "GTPE2_IMUX28_6", + "VBRK_EXT_IMUX28" ], [ - "CMT_TOP_SE4BEG2_7", - "VBRK_SE4BEG2" + "GTPE2_IMUX29_6", + "VBRK_EXT_IMUX29" ], [ - "CMT_TOP_EL1BEG1_7", - "VBRK_EL1BEG1" + "GTPE2_IMUX30_6", + "VBRK_EXT_IMUX30" ], [ - "CMT_TOP_MONITOR_N_7", - "VBRK_MONITOR_N" + "GTPE2_IMUX31_6", + "VBRK_EXT_IMUX31" ], [ - "CMT_TOP_EE4C1_7", - "VBRK_EE4C1" + "GTPE2_IMUX32_6", + "VBRK_EXT_IMUX32" ], [ - "CMT_TOP_WL1END3_7", - "VBRK_WL1END3" + "GTPE2_IMUX33_6", + "VBRK_EXT_IMUX33" ], [ - "CMT_TOP_WR1END3_7", - "VBRK_WR1END3" + "GTPE2_IMUX34_6", + "VBRK_EXT_IMUX34" ], [ - "CMT_TOP_NW2A2_7", - "VBRK_NW2A2" + "GTPE2_IMUX35_6", + "VBRK_EXT_IMUX35" ], [ - "CMT_TOP_WR1END2_7", - "VBRK_WR1END2" + "GTPE2_IMUX36_6", + "VBRK_EXT_IMUX36" ], [ - "CMT_TOP_WW4C0_7", - "VBRK_WW4C0" + "GTPE2_IMUX37_6", + "VBRK_EXT_IMUX37" ], [ - "CMT_TOP_EE2A1_7", - "VBRK_EE2A1" + "GTPE2_IMUX38_6", + "VBRK_EXT_IMUX38" ], [ - "CMT_TOP_SW4A0_7", - "VBRK_SW4A0" + "GTPE2_IMUX39_6", + "VBRK_EXT_IMUX39" ], [ - "CMT_TOP_SW2A3_7", - "VBRK_SW2A3" + "GTPE2_IMUX40_6", + "VBRK_EXT_IMUX40" ], [ - "CMT_TOP_NE4C1_7", - "VBRK_NE4C1" + "GTPE2_IMUX41_6", + "VBRK_EXT_IMUX41" ], [ - "CMT_TOP_SE4BEG3_7", - "VBRK_SE4BEG3" + "GTPE2_IMUX42_6", + "VBRK_EXT_IMUX42" ], [ - "CMT_TOP_SW4END1_7", - "VBRK_SW4END1" + "GTPE2_IMUX43_6", + "VBRK_EXT_IMUX43" ], [ - "CMT_TOP_SE2A1_7", - "VBRK_SE2A1" + "GTPE2_IMUX44_6", + "VBRK_EXT_IMUX44" ], [ - "CMT_TOP_LH1_7", - "VBRK_LH1" + "GTPE2_IMUX45_6", + "VBRK_EXT_IMUX45" ], [ - "CMT_TOP_WW4C3_7", - "VBRK_WW4C3" + "GTPE2_IMUX46_6", + "VBRK_EXT_IMUX46" ], [ - "CMT_TOP_WR1END0_7", - "VBRK_WR1END0" + "GTPE2_IMUX47_6", + "VBRK_EXT_IMUX47" ], [ - "CMT_TOP_NW4END2_7", - "VBRK_NW4END2" + "GTPE2_LOGIC_OUTS_B0_6", + "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "CMT_TOP_WW4END0_7", - "VBRK_WW4END0" + "GTPE2_LOGIC_OUTS_B1_6", + "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "CMT_TOP_WW2A2_7", - "VBRK_WW2A2" + "GTPE2_LOGIC_OUTS_B2_6", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ - "CMT_TOP_SE2A3_7", - "VBRK_SE2A3" + "GTPE2_LOGIC_OUTS_B3_6", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "CMT_TOP_SE4BEG0_7", - "VBRK_SE4BEG0" + "GTPE2_LOGIC_OUTS_B4_6", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "CMT_TOP_SE4C1_7", - "VBRK_SE4C1" + "GTPE2_LOGIC_OUTS_B5_6", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "CMT_TOP_NE4C2_7", - "VBRK_NE4C2" + "GTPE2_LOGIC_OUTS_B6_6", + "VBRK_EXT_LOGIC_OUTS_B6" ], [ - "CMT_TOP_WW4C2_7", - "VBRK_WW4C2" + "GTPE2_LOGIC_OUTS_B7_6", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "CMT_TOP_NW4A3_7", - "VBRK_NW4A3" + "GTPE2_LOGIC_OUTS_B9_6", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "CMT_TOP_SE4C0_7", - "VBRK_SE4C0" + "GTPE2_LOGIC_OUTS_B10_6", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "CMT_TOP_EE4BEG3_7", - "VBRK_EE4BEG3" + "GTPE2_LOGIC_OUTS_B12_6", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "CMT_TOP_WW2A3_7", - "VBRK_WW2A3" + "GTPE2_LOGIC_OUTS_B13_6", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "CMT_TOP_EE4A1_7", - "VBRK_EE4A1" + "GTPE2_LOGIC_OUTS_B14_6", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "CMT_TOP_WL1END1_7", - "VBRK_WL1END1" + "GTPE2_LOGIC_OUTS_B15_6", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "CMT_TOP_WW2END0_7", - "VBRK_WW2END0" + "GTPE2_LOGIC_OUTS_B17_6", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "CMT_TOP_SW2A2_7", - "VBRK_SW2A2" + "GTPE2_LOGIC_OUTS_B19_6", + "VBRK_EXT_LOGIC_OUTS_B19" ], [ - "CMT_TOP_SE4C2_7", - "VBRK_SE4C2" + "GTPE2_LOGIC_OUTS_B21_6", + "VBRK_EXT_LOGIC_OUTS_B21" ], [ - "CMT_TOP_NW4A2_7", - "VBRK_NW4A2" + "GTPE2_LOGIC_OUTS_B22_6", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "CMT_TOP_SE4C3_7", - "VBRK_SE4C3" + "GTPE2_LOGIC_OUTS_B23_6", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }, @@ -312329,7965 +343705,1065 @@ 0 ], "tile_types": [ - "CLBLM_L", - "CLBLM_R" + "GTP_CHANNEL_0", + "VBRK_EXT" ], "wire_pairs": [ [ - "CLBLM_SW2A0", - "CLBLM_SW2A0" + "GTPE2_BYP0_5", + "VBRK_EXT_BYP0" ], [ - "CLBLM_WW4A1", - "CLBLM_WW4A1" + "GTPE2_BYP1_5", + "VBRK_EXT_BYP1" ], [ - "CLBLM_NW4END3", - "CLBLM_NW4END3" + "GTPE2_BYP2_5", + "VBRK_EXT_BYP2" ], [ - "CLBLM_NW4END2", - "CLBLM_NW4END2" + "GTPE2_BYP3_5", + "VBRK_EXT_BYP3" ], [ - "CLBLM_EE4C2", - "CLBLM_EE4C2" + "GTPE2_BYP4_5", + "VBRK_EXT_BYP4" ], [ - "CLBLM_EE4A3", - "CLBLM_EE4A3" + "GTPE2_BYP5_5", + "VBRK_EXT_BYP5" ], [ - "CLBLM_WR1END1", - "CLBLM_WR1END1" + "GTPE2_BYP6_5", + "VBRK_EXT_BYP6" ], [ - "CLBLM_ER1BEG1", - "CLBLM_ER1BEG1" + "GTPE2_BYP7_5", + "VBRK_EXT_BYP7" ], [ - "CLBLM_SE4BEG3", - "CLBLM_SE4BEG3" + "GTPE2_CLK0_5", + "VBRK_EXT_CLK0" ], [ - "CLBLM_WW2END0", - "CLBLM_WW2END0" + "GTPE2_CLK1_5", + "VBRK_EXT_CLK1" ], [ - "CLBLM_EE2A2", - "CLBLM_EE2A2" + "GTPE2_CTRL0_5", + "VBRK_EXT_CTRL0" ], [ - "CLBLM_NE4C0", - "CLBLM_NE4C0" + "GTPE2_CTRL1_5", + "VBRK_EXT_CTRL1" ], [ - "CLBLM_SW2A1", - "CLBLM_SW2A1" + "GTPE2_FAN0_5", + "VBRK_EXT_FAN0" ], [ - "CLBLM_EE2A3", - "CLBLM_EE2A3" + "GTPE2_FAN1_5", + "VBRK_EXT_FAN1" ], [ - "CLBLM_SW2A2", - "CLBLM_SW2A2" + "GTPE2_FAN2_5", + "VBRK_EXT_FAN2" ], [ - "CLBLM_EE4BEG1", - "CLBLM_EE4BEG1" + "GTPE2_FAN3_5", + "VBRK_EXT_FAN3" ], [ - "CLBLM_LH5", - "CLBLM_LH5" + "GTPE2_FAN4_5", + "VBRK_EXT_FAN4" ], [ - "CLBLM_SW4A2", - "CLBLM_SW4A2" + "GTPE2_FAN5_5", + "VBRK_EXT_FAN5" ], [ - "CLBLM_LH7", - "CLBLM_LH7" + "GTPE2_FAN6_5", + "VBRK_EXT_FAN6" ], [ - "CLBLM_EE4B0", - "CLBLM_EE4B0" + "GTPE2_FAN7_5", + "VBRK_EXT_FAN7" ], [ - "CLBLM_EE2A1", - "CLBLM_EE2A1" + "GTPE2_IMUX0_5", + "VBRK_EXT_IMUX0" ], [ - "CLBLM_SE2A3", - "CLBLM_SE2A3" + "GTPE2_IMUX1_5", + "VBRK_EXT_IMUX1" ], [ - "CLBLM_ER1BEG2", - "CLBLM_ER1BEG2" + "GTPE2_IMUX2_5", + "VBRK_EXT_IMUX2" ], [ - "CLBLM_EE4BEG0", - "CLBLM_EE4BEG0" + "GTPE2_IMUX3_5", + "VBRK_EXT_IMUX3" ], [ - "CLBLM_EE2BEG2", - "CLBLM_EE2BEG2" + "GTPE2_IMUX4_5", + "VBRK_EXT_IMUX4" ], [ - "CLBLM_NE4C3", - "CLBLM_NE4C3" + "GTPE2_IMUX5_5", + "VBRK_EXT_IMUX5" ], [ - "CLBLM_NW4A3", - "CLBLM_NW4A3" + "GTPE2_IMUX6_5", + "VBRK_EXT_IMUX6" ], [ - "CLBLM_SW2A3", - "CLBLM_SW2A3" + "GTPE2_IMUX7_5", + "VBRK_EXT_IMUX7" ], [ - "CLBLM_LH12", - "CLBLM_LH12" + "GTPE2_IMUX8_5", + "VBRK_EXT_IMUX8" ], [ - "CLBLM_SE4BEG2", - "CLBLM_SE4BEG2" + "GTPE2_IMUX9_5", + "VBRK_EXT_IMUX9" ], [ - "CLBLM_WW4B1", - "CLBLM_WW4B1" + "GTPE2_IMUX10_5", + "VBRK_EXT_IMUX10" ], [ - "CLBLM_WW4B3", - "CLBLM_WW4B3" + "GTPE2_IMUX11_5", + "VBRK_EXT_IMUX11" ], [ - "CLBLM_WW4END3", - "CLBLM_WW4END3" + "GTPE2_IMUX12_5", + "VBRK_EXT_IMUX12" ], [ - "CLBLM_NW2A3", - "CLBLM_NW2A3" + "GTPE2_IMUX13_5", + "VBRK_EXT_IMUX13" ], [ - "CLBLM_NE4BEG1", - "CLBLM_NE4BEG1" + "GTPE2_IMUX14_5", + "VBRK_EXT_IMUX14" ], [ - "CLBLM_WR1END0", - "CLBLM_WR1END0" + "GTPE2_IMUX15_5", + "VBRK_EXT_IMUX15" ], [ - "CLBLM_LH8", - "CLBLM_LH8" + "GTPE2_IMUX16_5", + "VBRK_EXT_IMUX16" ], [ - "CLBLM_SE2A0", - "CLBLM_SE2A0" + "GTPE2_IMUX17_5", + "VBRK_EXT_IMUX17" ], [ - "CLBLM_EE4BEG2", - "CLBLM_EE4BEG2" + "GTPE2_IMUX18_5", + "VBRK_EXT_IMUX18" ], [ - "CLBLM_NW4END1", - "CLBLM_NW4END1" + "GTPE2_IMUX19_5", + "VBRK_EXT_IMUX19" ], [ - "CLBLM_EE4C3", - "CLBLM_EE4C3" + "GTPE2_IMUX20_5", + "VBRK_EXT_IMUX20" ], [ - "CLBLM_ER1BEG3", - "CLBLM_ER1BEG3" + "GTPE2_IMUX21_5", + "VBRK_EXT_IMUX21" ], [ - "CLBLM_LH4", - "CLBLM_LH4" + "GTPE2_IMUX22_5", + "VBRK_EXT_IMUX22" ], [ - "CLBLM_WW2A2", - "CLBLM_WW2A2" + "GTPE2_IMUX23_5", + "VBRK_EXT_IMUX23" ], [ - "CLBLM_SW4END0", - "CLBLM_SW4END0" + "GTPE2_IMUX24_5", + "VBRK_EXT_IMUX24" ], [ - "CLBLM_SW4END3", - "CLBLM_SW4END3" + "GTPE2_IMUX25_5", + "VBRK_EXT_IMUX25" ], [ - "CLBLM_WW2END2", - "CLBLM_WW2END2" + "GTPE2_IMUX26_5", + "VBRK_EXT_IMUX26" ], [ - "CLBLM_WW2A3", - "CLBLM_WW2A3" + "GTPE2_IMUX27_5", + "VBRK_EXT_IMUX27" ], [ - "CLBLM_NE4BEG2", - "CLBLM_NE4BEG2" + "GTPE2_IMUX28_5", + "VBRK_EXT_IMUX28" ], [ - "CLBLM_WL1END0", - "CLBLM_WL1END0" + "GTPE2_IMUX29_5", + "VBRK_EXT_IMUX29" ], [ - "CLBLM_EL1BEG3", - "CLBLM_EL1BEG3" + "GTPE2_IMUX30_5", + "VBRK_EXT_IMUX30" ], [ - "CLBLM_WW2A1", - "CLBLM_WW2A1" + "GTPE2_IMUX31_5", + "VBRK_EXT_IMUX31" ], [ - "CLBLM_EE4A0", - "CLBLM_EE4A0" + "GTPE2_IMUX32_5", + "VBRK_EXT_IMUX32" ], [ - "CLBLM_EE4B3", - "CLBLM_EE4B3" + "GTPE2_IMUX33_5", + "VBRK_EXT_IMUX33" ], [ - "CLBLM_SE4C0", - "CLBLM_SE4C0" + "GTPE2_IMUX34_5", + "VBRK_EXT_IMUX34" ], [ - "CLBLM_SW4A0", - "CLBLM_SW4A0" + "GTPE2_IMUX35_5", + "VBRK_EXT_IMUX35" ], [ - "CLBLM_NE4C1", - "CLBLM_NE4C1" + "GTPE2_IMUX36_5", + "VBRK_EXT_IMUX36" ], [ - "CLBLM_WW4C2", - "CLBLM_WW4C2" + "GTPE2_IMUX37_5", + "VBRK_EXT_IMUX37" ], [ - "CLBLM_EL1BEG2", - "CLBLM_EL1BEG2" + "GTPE2_IMUX38_5", + "VBRK_EXT_IMUX38" ], [ - "CLBLM_NW4A2", - "CLBLM_NW4A2" + "GTPE2_IMUX39_5", + "VBRK_EXT_IMUX39" ], [ - "CLBLM_EE4A2", - "CLBLM_EE4A2" + "GTPE2_IMUX40_5", + "VBRK_EXT_IMUX40" ], [ - "CLBLM_WW4B0", - "CLBLM_WW4B0" + "GTPE2_IMUX41_5", + "VBRK_EXT_IMUX41" ], [ - "CLBLM_WW4END1", - "CLBLM_WW4END1" + "GTPE2_IMUX42_5", + "VBRK_EXT_IMUX42" ], [ - "CLBLM_EE4B2", - "CLBLM_EE4B2" + "GTPE2_IMUX43_5", + "VBRK_EXT_IMUX43" ], [ - "CLBLM_SE4C3", - "CLBLM_SE4C3" + "GTPE2_IMUX44_5", + "VBRK_EXT_IMUX44" ], [ - "CLBLM_EE4A1", - "CLBLM_EE4A1" + "GTPE2_IMUX45_5", + "VBRK_EXT_IMUX45" ], [ - "CLBLM_WW4END2", - "CLBLM_WW4END2" + "GTPE2_IMUX46_5", + "VBRK_EXT_IMUX46" ], [ - "CLBLM_NE2A1", - "CLBLM_NE2A1" + "GTPE2_IMUX47_5", + "VBRK_EXT_IMUX47" ], [ - "CLBLM_NE4C2", - "CLBLM_NE4C2" + "GTPE2_LOGIC_OUTS_B0_5", + "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "CLBLM_WW2A0", - "CLBLM_WW2A0" + "GTPE2_LOGIC_OUTS_B1_5", + "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "CLBLM_MONITOR_P", - "CLBLM_MONITOR_P" + "GTPE2_LOGIC_OUTS_B2_5", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ - "CLBLM_EE2BEG1", - "CLBLM_EE2BEG1" + "GTPE2_LOGIC_OUTS_B3_5", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "CLBLM_SW4A3", - "CLBLM_SW4A3" + "GTPE2_LOGIC_OUTS_B4_5", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "CLBLM_LH2", - "CLBLM_LH2" + "GTPE2_LOGIC_OUTS_B5_5", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "CLBLM_SE4C1", - "CLBLM_SE4C1" + "GTPE2_LOGIC_OUTS_B6_5", + "VBRK_EXT_LOGIC_OUTS_B6" ], [ - "CLBLM_NE2A0", - "CLBLM_NE2A0" + "GTPE2_LOGIC_OUTS_B7_5", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "CLBLM_SW4A1", - "CLBLM_SW4A1" + "GTPE2_LOGIC_OUTS_B9_5", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "CLBLM_NW4A0", - "CLBLM_NW4A0" + "GTPE2_LOGIC_OUTS_B10_5", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "CLBLM_WR1END3", - "CLBLM_WR1END3" + "GTPE2_LOGIC_OUTS_B12_5", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "CLBLM_ER1BEG0", - "CLBLM_ER1BEG0" + "GTPE2_LOGIC_OUTS_B13_5", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "CLBLM_NW2A2", - "CLBLM_NW2A2" + "GTPE2_LOGIC_OUTS_B14_5", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "CLBLM_EE2A0", - "CLBLM_EE2A0" + "GTPE2_LOGIC_OUTS_B15_5", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "CLBLM_WW2END1", - "CLBLM_WW2END1" + "GTPE2_LOGIC_OUTS_B17_5", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "CLBLM_WL1END3", - "CLBLM_WL1END3" + "GTPE2_LOGIC_OUTS_B21_5", + "VBRK_EXT_LOGIC_OUTS_B21" ], [ - "CLBLM_NW4END0", - "CLBLM_NW4END0" + "GTPE2_LOGIC_OUTS_B22_5", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "CLBLM_WW4A3", - "CLBLM_WW4A3" - ], - [ - "CLBLM_SW4END1", - "CLBLM_SW4END1" - ], - [ - "CLBLM_NE2A2", - "CLBLM_NE2A2" - ], - [ - "CLBLM_WL1END1", - "CLBLM_WL1END1" - ], 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], - [ - "HCLK_NN6D2", - "NN6E2" - ], - [ - "HCLK_SS2A2", - "SS2BEG2" - ], - [ - "HCLK_NW6D0", - "NW6E0" - ], - [ - "HCLK_NN2A2", - "NN2END2" - ], - [ - "HCLK_LVB6", - "LVB6" - ], - [ - "HCLK_NE2BEG2", - "NE2A2" - ], - [ - "HCLK_LEAF_CLK_B_TOP1", - "GCLK_B1" - ], - [ - "HCLK_NL1BEG1", - "NL1END1" - ], - [ - "HCLK_NR1BEG0", - "NR1END0" - ], - [ - "HCLK_SS6END2", - "SS6E2" - ], - [ - "HCLK_NN6A3", - "NN6B3" - ], - [ - "HCLK_LVB2", - "LVB2" - ], - [ - "HCLK_NN6BEG1", - "NN6A1" - ], - [ - "HCLK_SE6E2", - "SE6D2" - ], - [ - "HCLK_SL1END2", - "SL1BEG2" - ], - [ - "HCLK_NN6E3", - "NN6END3" - ], - [ - "HCLK_LV1", - "LV2" - ], - [ - "HCLK_ER1END3", - "ER1END_N3_3" - ], - [ - "HCLK_LV9", - "LV10" - ], - [ - "HCLK_LV12", - "LV13" - ], - [ - "HCLK_NN6BEG0", - "NN6A0" - ], - [ - "HCLK_SS2A3", - "SS2A3" - ], - [ - "HCLK_SW2A3", - "SW2BEG3" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END_N0_3" - ], - [ - "HCLK_NN2END_S2_0", - "NN2END0" - ], - [ - "HCLK_SE6C0", - "SE6B0" - ], - [ - "HCLK_SS6E2", - "SS6D2" - ], - [ - "HCLK_SE6E0", - "SE6D0" - ], - [ - "HCLK_LV4", - "LV5" - ], - [ - "HCLK_NN2BEG1", - "NN2A1" - ], - [ - "HCLK_SW6END3", - "SW6END_N0_3" - ], - [ - "HCLK_SS6C1", - "SS6B1" - ], - [ - "HCLK_SS6A2", - "SS6BEG2" - ], - [ - "HCLK_SR1END_N3_3", - "SR1END_N3_3" - ], - [ - "HCLK_SW6B1", - "SW6A1" - ], - [ - "HCLK_LEAF_CLK_B_TOP4", - "GCLK_B4" - ], - [ - "HCLK_SW6C2", - "SW6B2" - ], - [ - "HCLK_NW6A0", - "NW6B0" - ], - [ - "HCLK_LV7", - "LV8" - ], - [ - "HCLK_NR1BEG2", - "NR1END2" - ], - [ - "HCLK_LVB9", - "LVB9" - ], - [ - "HCLK_SS2BEG3", - "SS2BEG3" - ], - [ - "HCLK_NE6B2", - "NE6C2" - ], - [ - "HCLK_NN6A1", - "NN6B1" - ], - [ - "HCLK_NW6C0", - "NW6D0" - ], - [ - "HCLK_LV10", - "LV11" - ], - [ - "HCLK_LV13", - "LV14" - ], - [ - "HCLK_SE6D3", - "SE6C3" - ], - [ - "HCLK_SS6END1", - "SS6E1" - ], - [ - "HCLK_NE6A1", - "NE6B1" - ], - [ - "HCLK_SE2A3", - "SE2BEG3" - ], - [ - "HCLK_NN2A1", - "NN2END1" - ], - [ - "HCLK_NN6E0", - "NN6END0" - ], - [ - "HCLK_NN6END_S1_0", - "NN6END0" - ], - [ - "HCLK_WL1BEG3", - "WL1BEG_N3" - ], - [ - "HCLK_SE6C3", - "SE6B3" - ], - [ - "HCLK_NN6C3", - "NN6D3" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "HCLK_NE6B1", - "NE6C1" - ], - [ - "HCLK_NN6D0", - "NN6E0" - ], - [ - "HCLK_SS6D2", - "SS6C2" - ], - [ - "HCLK_EL1END_S3_0", - "EL1END0" - ], - [ - "HCLK_LVB5", - "LVB5" - ], - [ - "HCLK_LV5", - "LV6" - ], - [ - "HCLK_SE2A2", - "SE2BEG2" - ], - [ - "HCLK_NE6C1", - "NE6D1" - ], - [ - "HCLK_NW6C2", - "NW6D2" - ], - [ - "HCLK_SW6C0", - "SW6B0" - ], - [ - "HCLK_NW6D1", - "NW6E1" - ], - [ - "HCLK_NW6B1", - "NW6C1" - ], - [ - "HCLK_NW6C3", - "NW6D3" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END0" - ], - [ - "HCLK_SS6C3", - "SS6B3" - ], - [ - "HCLK_NW2A0", - "NW2A0" - ], - [ - "HCLK_FAN_BOUNCE_S3_0", - "FAN_BOUNCE0" - ], - [ - "HCLK_LVB4", - "LVB4" - ], - [ - "HCLK_LV0", - "LV1" - ], - [ - "HCLK_SS6E0", - "SS6D0" - ], - [ - "HCLK_NE6B0", - "NE6C0" - ], - [ - "HCLK_NW6D3", - "NW6E3" - ], - [ - "HCLK_NW6END_S0_0", - "NW6END0" - ], - [ - "HCLK_SS2END2", - "SS2A2" - ], - [ - "HCLK_LV6", - "LV7" - ], - [ - "HCLK_SW6B2", - "SW6A2" - ], - [ - "HCLK_SW6E2", - "SW6D2" - ], - [ - "HCLK_LV3", - "LV4" - ], - [ - "HCLK_WW4END_S0_0", - "WW4END0" - ], - [ - "HCLK_NE2END_S3_0", - "NE2END0" - ], - [ - "HCLK_SE6B3", - "SE6A3" - ], - [ - "HCLK_NN6E2", - "NN6END2" - ], - [ - "HCLK_SS2END1", - "SS2A1" - ], - [ - "HCLK_LVB12", - "LVB12" - ], - [ - "HCLK_SS6A1", - "SS6BEG1" - ], - [ - "HCLK_NR1BEG1", - "NR1END1" - ], - [ - "HCLK_NW6B2", - "NW6C2" - ], - [ - "HCLK_SW6E3", - "SW6D3" - ], - [ - "HCLK_BYP_BOUNCE3", - "BYP_BOUNCE_N3_3" - ], - [ - "HCLK_NR1BEG3", - "NR1END3" - ], - [ - "HCLK_SS6D1", - "SS6C1" - ], - [ - "HCLK_FAN_BOUNCE_S3_2", - "FAN_BOUNCE2" - ], - [ - "HCLK_NN6A0", - "NN6B0" - ], - [ - "HCLK_SS6A3", - "SS6BEG3" - ], - [ - "HCLK_LV11", - "LV12" - ], - [ - "HCLK_NN6B2", - "NN6C2" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "BRKH_INT", - "INT_R" - ], - "wire_pairs": [ - [ - "BRKH_INT_NL1END_S3_0", - "NL1END0" - ], - [ - "BRKH_INT_SS2END0", - "SS2A0" - ], - [ - "BRKH_INT_NE6C2", - "NE6D2" - ], - [ - "BRKH_INT_NE6B0", - "NE6C0" - ], - [ - "BRKH_INT_NN6D1", - "NN6E1" - ], - [ - "BRKH_INT_LV3", - "LV4" - ], - [ - "BRKH_INT_LVB4", - "LVB4" - ], - [ - "BRKH_INT_NE6D0", - "NE6E0" - ], - [ - "BRKH_INT_NN6BEG3", - "NN6A3" - ], - [ - "BRKH_INT_NW6END_S0_0", - "NW6END0" - ], - [ - "BRKH_INT_SW6END3", - "SW6END_N0_3" - ], - [ - "BRKH_INT_SW2END3", - "SW2END_N0_3" - ], - [ - "BRKH_INT_NN6C2", - "NN6D2" - ], - [ - "BRKH_INT_SS2A3", - "SS2BEG3" - ], - [ - "BRKH_INT_NN6END_S1_0", - "NN6END0" - ], - [ - "BRKH_INT_LVB11", - "LVB11" - ], - [ - "BRKH_INT_WL1END3", - "WL1END_N1_3" - ], - [ - "BRKH_INT_SE6D2", - "SE6C2" - ], - [ - "BRKH_INT_SS6B3", - "SS6A3" - ], - [ - "BRKH_INT_SE6C3", - "SE6B3" - ], - [ - "BRKH_INT_NN6A2", - "NN6B2" - ], - [ - "BRKH_INT_LV13", - "LV14" - ], - [ - "BRKH_INT_NE6A3", - "NE6B3" - ], - [ - "BRKH_INT_SW2A1", - "SW2BEG1" - ], - [ - "BRKH_INT_WW4END_S0_0", - "WW4END0" - ], - [ - "BRKH_INT_LVB2", - "LVB2" - ], - [ - "BRKH_INT_BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "BRKH_INT_LVB9", - "LVB9" - ], - [ - "BRKH_INT_NN6A1", - "NN6B1" - ], - [ - "BRKH_INT_NE2BEG3", - "NE2A3" - ], - [ - "BRKH_INT_NE6C3", - "NE6D3" - ], - [ - "BRKH_INT_NW6D3", - "NW6E3" - ], - [ - "BRKH_INT_SE6E3", - "SE6D3" - ], - [ - "BRKH_INT_SS2A1", - "SS2BEG1" - ], - [ - "BRKH_INT_NW6A0", - "NW6B0" - ], - [ - "BRKH_INT_LV7", - "LV8" - ], - [ - "BRKH_INT_NL1BEG0_SLOW", - "NL1END0" - ], - [ - "BRKH_INT_NR1BEG2_SLOW", - "NR1END2" - ], - [ - "BRKH_INT_LVB5", - "LVB5" - ], - [ - "BRKH_INT_SS6C3", - "SS6B3" - ], - [ - "BRKH_INT_SE6B2", - "SE6A2" - ], - [ - "BRKH_INT_SW2A2", - "SW2BEG2" - ], - [ - "BRKH_INT_NE6B1", - "NE6C1" - ], - [ - "BRKH_INT_NE6D3", - "NE6E3" - ], - [ - "BRKH_INT_NW2BEG0", - "NW2A0" - ], - [ - "BRKH_INT_NW6B1", - "NW6C1" - ], - [ - "BRKH_INT_LV2", - "LV3" - ], - [ - "BRKH_INT_BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" - ], - [ - "BRKH_INT_NE6C0", - "NE6D0" - ], - [ - "BRKH_INT_NN6E2", - "NN6END2" - ], - [ - "BRKH_INT_SE6D0", - "SE6C0" - ], - [ - "BRKH_INT_SE2A2", - "SE2BEG2" - ], - [ - "BRKH_INT_EL1END_S3_0", - "EL1END0" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_0", - "FAN_BOUNCE0" - ], - [ - "BRKH_INT_SW6C0", - "SW6B0" - ], - [ - "BRKH_INT_SS6C1", - "SS6B1" - ], - [ - "BRKH_INT_NN2A2", - "NN2END2" - ], - [ - "BRKH_INT_SE2A1", - "SE2BEG1" - ], - [ - "BRKH_INT_SW6C3", - "SW6B3" - ], - [ - "BRKH_INT_SL1END1_SLOW", - "SL1BEG1" - ], - [ - "BRKH_INT_NR1BEG3_SLOW", - "NR1END3" - ], - [ - "BRKH_INT_NE6B2", - "NE6C2" - ], - [ - "BRKH_INT_LVB7", - "LVB7" - ], - [ - "BRKH_INT_SS6E2", - "SS6D2" - ], - [ - "BRKH_INT_SS6A3", - "SS6BEG3" - ], - [ - "BRKH_INT_SR1END3_SLOW", - "SR1BEG3" - ], - [ - "BRKH_INT_NW6D2", - "NW6E2" - ], - [ - "BRKH_INT_NN6A3", - "NN6B3" - ], - [ - "BRKH_INT_SW6E3", - "SW6D3" - ], - [ - "BRKH_INT_SS6END_N0_3", - "SS6END_N0_3" - ], - [ - "BRKH_INT_SW6B1", - "SW6A1" - ], - [ - "BRKH_INT_NW6B0", - "NW6C0" - ], - [ - "BRKH_INT_SS6D2", - "SS6C2" - ], - [ - "BRKH_INT_SS2END_N0_3", - "SS2END_N0_3" - ], - [ - "BRKH_INT_NW6D0", - "NW6E0" - ], - [ - "BRKH_INT_NN6BEG1", - "NN6A1" - ], - [ - "BRKH_INT_NN6D3", - "NN6E3" - ], - [ - "BRKH_INT_NN6C0", - "NN6D0" - ], - [ - "BRKH_INT_LV17", - "LV18" - ], - [ - "BRKH_INT_LV11", - "LV12" - ], - [ - "BRKH_INT_NE6A0", - "NE6B0" - ], - [ - "BRKH_INT_NN6B0", - "NN6C0" - ], - [ - "BRKH_INT_LV14", - "LV15" - ], - [ - "BRKH_INT_SR1END_N3_3", - "SR1END_N3_3" - ], - [ - "BRKH_INT_SE2A3", - "SE2BEG3" - ], - [ - "BRKH_INT_SS6C0", - "SS6B0" - ], - [ - "BRKH_INT_NE6C1", - "NE6D1" - ], - [ - "BRKH_INT_NN2END_S2_0", - "NN2END0" - ], - [ - "BRKH_INT_SS6A0", - "SS6BEG0" - ], - [ - "BRKH_INT_EL1BEG3", - "EL1BEG_N3" - ], - [ - "BRKH_INT_NR1BEG0_SLOW", - "NR1END0" - ], - [ - "BRKH_INT_NW2END_S0_0", - "NW2END0" - ], - [ - "BRKH_INT_LV0", - "LV1" - ], - [ - "BRKH_INT_SL1END0_SLOW", - "SL1BEG0" - ], - [ - "BRKH_INT_NN6C1", - "NN6D1" - ], - [ - "BRKH_INT_SW6D2", - "SW6C2" - ], - [ - "BRKH_INT_SE6E1", - "SE6D1" - ], - [ - "BRKH_INT_SS6END1", - "SS6E1" - ], - [ - "BRKH_INT_ER1END3", - "ER1END_N3_3" - ], - [ - "BRKH_INT_LV10", - "LV11" - ], - [ - "BRKH_INT_WR1END_S1_0", - "WR1END0" - ], - [ - "BRKH_INT_NN2A0", - "NN2END0" - ], - [ - "BRKH_INT_NN6C3", - "NN6D3" - ], - [ - "BRKH_INT_SS6D0", - "SS6C0" - ], - [ - "BRKH_INT_NN6B2", - "NN6C2" - ], - [ - "BRKH_INT_SW6C1", - "SW6B1" - ], - [ - "BRKH_INT_WR1BEG_S0", - "WR1BEG0" - ], - [ - "BRKH_INT_LVB3", - "LVB3" - ], - [ - "BRKH_INT_SW2A3", - "SW2BEG3" - ], - [ - "BRKH_INT_SS6E1", - "SS6D1" - ], - [ - "BRKH_INT_SW6C2", - "SW6B2" - ], - [ - "BRKH_INT_NN2A3", - "NN2END3" - ], - [ - "BRKH_INT_SS2A0", - "SS2BEG0" - ], - [ - "BRKH_INT_SE6D3", - "SE6C3" - ], - [ - "BRKH_INT_NN2BEG0", - "NN2A0" - ], - [ - "BRKH_INT_NN6BEG0", - "NN6A0" - ], - [ - "BRKH_INT_SE6E0", - "SE6D0" - ], - [ - "BRKH_INT_SW6E0", - "SW6D0" - ], - [ - "BRKH_INT_SE6C1", - "SE6B1" - ], - [ - "BRKH_INT_SE6E2", - "SE6D2" - ], - [ - "BRKH_INT_LV16", - "LV17" - ], - [ - "BRKH_INT_LVB12", - "LVB12" - ], - [ - "BRKH_INT_SS6B0", - "SS6A0" - ], - [ - "BRKH_INT_WW2END3", - "WW2END_N0_3" - ], - [ - "BRKH_INT_NW6D1", - "NW6E1" - ], - [ - "BRKH_INT_SS6A1", - "SS6BEG1" - ], - [ - "BRKH_INT_LVB6", - "LVB6" - ], - [ - "BRKH_INT_SE6C0", - "SE6B0" - ], - [ - "BRKH_INT_SW6B3", - "SW6A3" - ], - [ - "BRKH_INT_SW6E1", - "SW6D1" - ], - [ - "BRKH_INT_NW6C3", - "NW6D3" - ], - [ - "BRKH_INT_NN6E1", - "NN6END1" - ], - [ - "BRKH_INT_SS6END2", - "SS6E2" - ], - [ - "BRKH_INT_SE6B1", - "SE6A1" - ], - [ - "BRKH_INT_NE6D2", - "NE6E2" - ], - [ - "BRKH_INT_SS2A2", - "SS2BEG2" - ], - [ - "BRKH_INT_LV15", - "LV16" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_6", - "FAN_BOUNCE6" - ], - [ - "BRKH_INT_SE6B3", - "SE6A3" - ], - [ - "BRKH_INT_NL1BEG2_SLOW", - "NL1END2" - ], - [ - "BRKH_INT_SR1END1_SLOW", - "SR1BEG1" - ], - [ - "BRKH_INT_NN6B1", - "NN6C1" - ], - [ - "BRKH_INT_SS6E3", - "SS6D3" - ], - [ - "BRKH_INT_LVB10", - "LVB10" - ], - [ - "BRKH_INT_SW6B0", - "SW6A0" - ], - [ - "BRKH_INT_SS6D3", - "SS6C3" - ], - [ - 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[ - "CLK_HROW_IMUX36_5", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_SW2A0_5", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_EE2BEG1_5", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_IMUX3_5", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_WW4A0_5", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_IMUX33_5", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_EE4A0_5", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_ER1BEG1_5", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_IMUX23_5", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_FAN2_5", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_WW2A2_5", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_SE2A0_5", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_CTRL0_5", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX41_5", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SW2A1_5", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE4B2_5", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_WW4A2_5", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_SW4END3_5", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_BYP7_5", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WR1END3_5", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_IMUX6_5", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_EE4BEG0_5", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_WW2END3_5", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_LH3_5", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_WW4END3_5", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_SW2A3_5", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_WW2END1_5", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_NE2A1_5", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_SE4C3_5", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_FAN5_5", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_LH9_5", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_IMUX24_5", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX1_5", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_WL1END2_5", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_NE2A3_5", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_WW4B3_5", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_NW4END3_5", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_IMUX15_5", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_BYP5_5", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_BYP2_5", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_SW4A0_5", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_WR1END2_5", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_SE4C1_5", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_EE4BEG2_5", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_IMUX7_5", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WW4B1_5", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_NE4C3_5", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_NW2A0_5", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_IMUX14_5", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_NE4BEG1_5", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_ER1BEG0_5", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SE4C2_5", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_EE4B3_5", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX20_5", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_LH11_5", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EL1BEG2_5", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX9_5", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_IMUX22_5", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_IMUX34_5", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_IMUX35_5", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX5_5", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_SW4A3_5", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_EE2BEG0_5", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_WW4C1_5", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_NW2A2_5", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_WW4B2_5", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_BYP3_5", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_WW4B0_5", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_EE4B1_5", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX13_5", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_FAN1_5", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW4END0_5", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_LH8_5", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_BYP1_5", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_NW4END2_5", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_NW4A0_5", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_LH6_5", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_SE4BEG1_5", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_FAN4_5", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_IMUX21_5", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_NE4C0_5", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_SE4BEG0_5", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_WW2A3_5", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_IMUX30_5", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_WW4END1_5", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_WR1END0_5", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE4A2_5", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_IMUX32_5", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX8_5", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_SW4A2_5", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WR1END1_5", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_IMUX31_5", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_NE4BEG3_5", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EL1BEG1_5", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_BYP4_5", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_WL1END0_5", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_IMUX25_5", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EL1BEG0_5", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SE2A1_5", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX11_5", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_WW4A3_5", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_CLK1_5", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_IMUX12_5", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_FAN7_5", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_IMUX45_5", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_WL1END3_5", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_EE4B0_5", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_IMUX0_5", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_WL1END1_5", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX29_5", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_CTRL1_5", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW4C3_5", - "INT_INTERFACE_WW4C3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_BUFG_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH1_0", - "INT_INTERFACE_LH1" - ], - [ - "CLK_BUFG_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_BUFG_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_BUFG_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_SW4END2_0", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_BUFG_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_0", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_0", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_BUFG_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_BUFG_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_BUFG_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_BUFG_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_BUFG_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_0", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_0", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_BUFG_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_BUFG_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_BUFG_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_BUFG_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_BUFG_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_BUFG_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_BUFG_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_BUFG_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_0", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_BUFG_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_BUFG_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_BUFG_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NW4END2_0", - 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[ - "INT_FEEDTHRU_2_SE4BEG1", - "MONITOR_SE4BEG1_0" - ], - [ - "INT_FEEDTHRU_2_LH9", - "MONITOR_LH9_0" - ], - [ - "INT_FEEDTHRU_2_NE4BEG3", - "MONITOR_NE4BEG3_0" - ], - [ - "INT_FEEDTHRU_2_WR1END1", - "MONITOR_WR1END1_0" - ], - [ - "INT_FEEDTHRU_2_WW4A2", - "MONITOR_WW4A2_0" - ], - [ - "INT_FEEDTHRU_2_SE4BEG3", - "MONITOR_SE4BEG3_0" - ], - [ - "INT_FEEDTHRU_2_WW4C2", - "MONITOR_WW4C2_0" - ], - [ - "INT_FEEDTHRU_2_NE4C3", - "MONITOR_NE4C3_0" - ], - [ - "INT_FEEDTHRU_2_SW2A2", - "MONITOR_SW2A2_0" - ], - [ - "INT_FEEDTHRU_2_LH4", - "MONITOR_LH4_0" - ], - [ - "INT_FEEDTHRU_2_SW4END0", - "MONITOR_SW4END0_0" - ], - [ - "INT_FEEDTHRU_2_EE4BEG1", - "MONITOR_EE4BEG1_0" - ], - [ - "INT_FEEDTHRU_2_EE4A0", - "MONITOR_EE4A0_0" - ], - [ - "INT_FEEDTHRU_2_SW4END1", - "MONITOR_SW4END1_0" - ], - [ - "INT_FEEDTHRU_2_LH1", - "MONITOR_LH1_0" - ], - [ - "INT_FEEDTHRU_2_WW2A3", - "MONITOR_WW2A3_0" - ], - [ - "INT_FEEDTHRU_2_WR1END0", - "MONITOR_WR1END0_0" - ], - [ - "INT_FEEDTHRU_2_SE2A0", - "MONITOR_SE2A0_0" - ], - [ - "INT_FEEDTHRU_2_WW4END3", - "MONITOR_WW4END3_0" - ], - [ - "INT_FEEDTHRU_2_EE2BEG1", - "MONITOR_EE2BEG1_0" - ], - [ - "INT_FEEDTHRU_2_SE2A2", - "MONITOR_SE2A2_0" - ], - [ - "INT_FEEDTHRU_2_WL1END1", - "MONITOR_WL1END1_0" - ], - [ - "INT_FEEDTHRU_2_LH7", - "MONITOR_LH7_0" - ], - [ - "INT_FEEDTHRU_2_EE4C1", - "MONITOR_EE4C1_0" - ], - [ - "INT_FEEDTHRU_2_NE4C1", - "MONITOR_NE4C1_0" - ], - [ - "INT_FEEDTHRU_2_WW4END2", - "MONITOR_WW4END2_0" - ], - [ - "INT_FEEDTHRU_2_NW4A0", - "MONITOR_NW4A0_0" - ], - [ - "INT_FEEDTHRU_2_WW4C3", - "MONITOR_WW4C3_0" - ], - [ - "INT_FEEDTHRU_2_WW2A1", - "MONITOR_WW2A1_0" - ], - [ - "INT_FEEDTHRU_2_WW4A3", - "MONITOR_WW4A3_0" - ], - [ - "INT_FEEDTHRU_2_EE4C2", - "MONITOR_EE4C2_0" - ], - [ - "INT_FEEDTHRU_2_LH11", - "MONITOR_LH11_0" - ], - [ - "INT_FEEDTHRU_2_WW4B1", - "MONITOR_WW4B1_0" - ], - [ - "INT_FEEDTHRU_2_LH12", - "MONITOR_LH12_0" - ], - [ - "INT_FEEDTHRU_2_NE4C0", - "MONITOR_NE4C0_0" - ], - [ - "INT_FEEDTHRU_2_SW2A3", - "MONITOR_SW2A3_0" - ], - [ - "INT_FEEDTHRU_2_MONITOR_N", - "MONITOR_HORIZ_VAUXN2" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLBLM_L", - "HCLK_CLB" - ], - "wire_pairs": [ - [ - "CLBLM_M_CIN", - "HCLK_CLB_COUT0_L" - ], - [ - "CLBLM_L_CIN", - "HCLK_CLB_COUT1_L" + "GTPE2_LOGIC_OUTS_B22_3", + "VBRK_EXT_LOGIC_OUTS_B22" ] ] }, @@ -320297,105 +344773,49 @@ 3 ], "tile_types": [ - "GTP_CHANNEL_3", + "GTP_CHANNEL_0", "VBRK_EXT" ], "wire_pairs": [ [ - "GTPE2_FAN0_2", - "VBRK_EXT_FAN0" + "GTPE2_BYP0_2", + "VBRK_EXT_BYP0" ], [ - "GTPE2_FAN2_2", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX7_2", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX46_2", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_LOGIC_OUTS_B3_2", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_BYP7_2", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_BYP3_2", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX12_2", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX33_2", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_FAN3_2", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX8_2", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_FAN1_2", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX10_2", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX13_2", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX34_2", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX29_2", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B22_2", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX45_2", - "VBRK_EXT_IMUX45" + "GTPE2_BYP1_2", + "VBRK_EXT_BYP1" ], [ "GTPE2_BYP2_2", "VBRK_EXT_BYP2" ], + [ + "GTPE2_BYP3_2", + "VBRK_EXT_BYP3" + ], [ "GTPE2_BYP4_2", "VBRK_EXT_BYP4" ], + [ + "GTPE2_BYP5_2", + "VBRK_EXT_BYP5" + ], [ "GTPE2_BYP6_2", "VBRK_EXT_BYP6" ], [ - "GTPE2_FAN4_2", - "VBRK_EXT_FAN4" + "GTPE2_BYP7_2", + "VBRK_EXT_BYP7" ], [ - "GTPE2_IMUX22_2", - "VBRK_EXT_IMUX22" + "GTPE2_CLK0_2", + "VBRK_EXT_CLK0" ], [ - "GTPE2_LOGIC_OUTS_B18_2", - "VBRK_EXT_LOGIC_OUTS_B18" + "GTPE2_CLK1_2", + "VBRK_EXT_CLK1" ], [ "GTPE2_CTRL0_2", @@ -320406,31748 +344826,492 @@ "VBRK_EXT_CTRL1" ], [ - "GTPE2_BYP1_2", - "VBRK_EXT_BYP1" + "GTPE2_FAN0_2", + "VBRK_EXT_FAN0" ], [ - "GTPE2_IMUX43_2", - "VBRK_EXT_IMUX43" + "GTPE2_FAN1_2", + "VBRK_EXT_FAN1" ], [ - "GTPE2_IMUX40_2", - "VBRK_EXT_IMUX40" + "GTPE2_FAN2_2", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_FAN3_2", + "VBRK_EXT_FAN3" + ], + [ + "GTPE2_FAN4_2", + "VBRK_EXT_FAN4" ], [ "GTPE2_FAN5_2", "VBRK_EXT_FAN5" ], - [ - "GTPE2_LOGIC_OUTS_B20_2", - "VBRK_EXT_LOGIC_OUTS_B20" - ], [ "GTPE2_FAN6_2", "VBRK_EXT_FAN6" ], - [ - "GTPE2_IMUX47_2", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_LOGIC_OUTS_B15_2", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_LOGIC_OUTS_B17_2", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX42_2", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_LOGIC_OUTS_B19_2", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_IMUX41_2", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX5_2", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_LOGIC_OUTS_B13_2", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX11_2", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX37_2", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_CLK0_2", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX32_2", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX30_2", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX14_2", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX28_2", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX26_2", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX16_2", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX15_2", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX27_2", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX39_2", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX35_2", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_LOGIC_OUTS_B6_2", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX23_2", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_LOGIC_OUTS_B7_2", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_LOGIC_OUTS_B14_2", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX0_2", - "VBRK_EXT_IMUX0" - ], [ "GTPE2_FAN7_2", "VBRK_EXT_FAN7" ], [ - "GTPE2_IMUX6_2", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_LOGIC_OUTS_B12_2", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_IMUX2_2", - "VBRK_EXT_IMUX2" + "GTPE2_IMUX0_2", + "VBRK_EXT_IMUX0" ], [ "GTPE2_IMUX1_2", "VBRK_EXT_IMUX1" ], [ - "GTPE2_CLK1_2", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX17_2", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX19_2", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX38_2", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX25_2", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX18_2", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_LOGIC_OUTS_B9_2", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX20_2", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX4_2", - "VBRK_EXT_IMUX4" + "GTPE2_IMUX2_2", + "VBRK_EXT_IMUX2" ], [ "GTPE2_IMUX3_2", "VBRK_EXT_IMUX3" ], [ - "GTPE2_IMUX44_2", - "VBRK_EXT_IMUX44" + "GTPE2_IMUX4_2", + "VBRK_EXT_IMUX4" ], [ - "GTPE2_IMUX36_2", - "VBRK_EXT_IMUX36" + "GTPE2_IMUX5_2", + "VBRK_EXT_IMUX5" ], [ - "GTPE2_IMUX21_2", - "VBRK_EXT_IMUX21" + "GTPE2_IMUX6_2", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_2", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_2", + "VBRK_EXT_IMUX8" ], [ "GTPE2_IMUX9_2", "VBRK_EXT_IMUX9" ], [ - "GTPE2_BYP0_2", - "VBRK_EXT_BYP0" + "GTPE2_IMUX10_2", + "VBRK_EXT_IMUX10" ], [ - "GTPE2_LOGIC_OUTS_B16_2", - "VBRK_EXT_LOGIC_OUTS_B16" + "GTPE2_IMUX11_2", + "VBRK_EXT_IMUX11" ], [ - "GTPE2_BYP5_2", - "VBRK_EXT_BYP5" + "GTPE2_IMUX12_2", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_2", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_2", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_2", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_2", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_2", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_2", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX19_2", + "VBRK_EXT_IMUX19" + ], + [ + "GTPE2_IMUX20_2", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_IMUX21_2", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX22_2", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX23_2", + "VBRK_EXT_IMUX23" ], [ "GTPE2_IMUX24_2", "VBRK_EXT_IMUX24" ], + [ + "GTPE2_IMUX25_2", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX26_2", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX27_2", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX28_2", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_IMUX29_2", + "VBRK_EXT_IMUX29" + ], + [ + "GTPE2_IMUX30_2", + "VBRK_EXT_IMUX30" + ], [ "GTPE2_IMUX31_2", "VBRK_EXT_IMUX31" - ] - ] - }, - { - "grid_deltas": [ - 1, - -1 - ], - "tile_types": [ - "MONITOR_MID", - "VFRAME" - ], - "wire_pairs": [ - [ - "MONITOR_WW2A0_1", - "VFRAME_WW2A0" - ], - [ - "MONITOR_LH2_1", - "VFRAME_LH2" - ], - [ - "MONITOR_WW4END0_1", - "VFRAME_WW4END0" - ], - [ - "MONITOR_SW4END1_1", - "VFRAME_SW4END1" - ], - [ - "MONITOR_IMUX31_1", - "VFRAME_IMUX31" - ], - [ - "MONITOR_SE4C2_1", - "VFRAME_SE4C2" - ], - [ - "MONITOR_IMUX34_1", - "VFRAME_IMUX34" - ], - [ - "MONITOR_WW4B2_1", - "VFRAME_WW4B2" - ], - [ - "MONITOR_SE4BEG0_1", - "VFRAME_SE4BEG0" - ], - [ - "MONITOR_EL1BEG1_1", - "VFRAME_EL1BEG1" - ], - [ - "MONITOR_IMUX7_1", - "VFRAME_IMUX7" - ], - [ - "MONITOR_LH12_1", - "VFRAME_LH12" - ], - [ - "MONITOR_EE4C3_1", - "VFRAME_EE4C3" - ], - [ - "MONITOR_IMUX32_1", - "VFRAME_IMUX32" - ], - [ - "MONITOR_WW2END2_1", - "VFRAME_WW2END2" - ], - [ - "MONITOR_LH6_1", - "VFRAME_LH6" - ], - [ - "MONITOR_CTRL1_1", - "VFRAME_CTRL1" - ], - [ - "MONITOR_EE2BEG2_1", - "VFRAME_EE2BEG2" - ], - [ - "MONITOR_IMUX24_1", - "VFRAME_IMUX24" - ], - [ - "MONITOR_FAN7_1", - "VFRAME_FAN7" - ], - [ - "MONITOR_EE4BEG1_1", - "VFRAME_EE4BEG1" - ], - [ - "MONITOR_EE4C0_1", - "VFRAME_EE4C0" - ], - [ - "MONITOR_ER1BEG2_1", - "VFRAME_ER1BEG2" - ], - [ - "MONITOR_NW4A0_1", - "VFRAME_NW4A0" - ], - [ - "MONITOR_LH5_1", - "VFRAME_LH5" - ], - [ - "MONITOR_FAN5_1", - "VFRAME_FAN5" - ], - [ - "MONITOR_IMUX1_1", - "VFRAME_IMUX1" - ], - [ - "MONITOR_EE2BEG0_1", - "VFRAME_EE2BEG0" - ], - [ - "MONITOR_BYP0_1", - "VFRAME_BYP0" - ], - [ - "MONITOR_EE2BEG1_1", - "VFRAME_EE2BEG1" - ], - [ - "MONITOR_FAN1_1", - "VFRAME_FAN1" - ], - [ - "MONITOR_NW2A0_1", - "VFRAME_NW2A0" - ], - [ - "MONITOR_EE4A0_1", - "VFRAME_EE4A0" - ], - [ - "MONITOR_SE4BEG1_1", - "VFRAME_SE4BEG1" - ], - [ - "MONITOR_IMUX40_1", - "VFRAME_IMUX40" - ], - [ - "MONITOR_FAN2_1", - "VFRAME_FAN2" - ], - [ - "MONITOR_BYP2_1", - "VFRAME_BYP2" - ], - [ - "MONITOR_WW4END1_1", - "VFRAME_WW4END1" - ], - [ - "MONITOR_WW2END1_1", - "VFRAME_WW2END1" - ], - [ - "MONITOR_EE4B0_1", - "VFRAME_EE4B0" - ], - [ - "MONITOR_WL1END1_1", - "VFRAME_WL1END1" - ], - [ - "MONITOR_IMUX29_1", - "VFRAME_IMUX29" - ], - [ - "MONITOR_IMUX37_1", - "VFRAME_IMUX37" - ], - [ - "MONITOR_IMUX22_1", - "VFRAME_IMUX22" - ], - [ - "MONITOR_LH3_1", - "VFRAME_LH3" - ], - [ - "MONITOR_SW4END2_1", - "VFRAME_SW4END2" - ], - [ - "MONITOR_IMUX10_1", - "VFRAME_IMUX10" - ], - [ - "MONITOR_ER1BEG3_1", - "VFRAME_ER1BEG3" - ], - [ - "MONITOR_IMUX21_1", - "VFRAME_IMUX21" - ], - [ - "MONITOR_SW2A3_1", - "VFRAME_SW2A3" - ], - [ - "MONITOR_EE2BEG3_1", - "VFRAME_EE2BEG3" - ], - [ - "MONITOR_BYP3_1", - "VFRAME_BYP3" - ], - [ - "MONITOR_IMUX23_1", - "VFRAME_IMUX23" - ], - [ - "MONITOR_NW4END0_1", - "VFRAME_NW4END0" - ], - [ - "MONITOR_LH4_1", - "VFRAME_LH4" - ], - [ - "MONITOR_NW4END1_1", - "VFRAME_NW4END1" - ], - [ - "MONITOR_WW2END3_1", - "VFRAME_WW2END3" - ], - [ - "MONITOR_NE4BEG3_1", - "VFRAME_NE4BEG3" - ], - [ - "MONITOR_WW2A1_1", - "VFRAME_WW2A1" - ], - [ - "MONITOR_SE4C1_1", - "VFRAME_SE4C1" - ], - [ - "MONITOR_WW4B1_1", - "VFRAME_WW4B1" - ], - [ - "MONITOR_BYP7_1", - "VFRAME_BYP7" - ], - [ - "MONITOR_NE4BEG0_1", - "VFRAME_NE4BEG0" - ], - [ - "MONITOR_WW4B0_1", - "VFRAME_WW4B0" - ], - [ - "MONITOR_CLK1_1", - "VFRAME_CLK1" - ], - [ - "MONITOR_IMUX0_1", - "VFRAME_IMUX0" - ], - [ - "MONITOR_SW4END3_1", - "VFRAME_SW4END3" - ], - [ - "MONITOR_EL1BEG2_1", - "VFRAME_EL1BEG2" - ], - [ - "MONITOR_IMUX13_1", - "VFRAME_IMUX13" - ], - [ - "MONITOR_IMUX47_1", - "VFRAME_IMUX47" - ], - [ - "MONITOR_SW4A0_1", - "VFRAME_SW4A0" - ], - [ - "MONITOR_NE4C2_1", - "VFRAME_NE4C2" - ], - [ - "MONITOR_EE4C1_1", - "VFRAME_EE4C1" - ], - [ - "MONITOR_WW4END3_1", - "VFRAME_WW4END3" - ], - [ - "MONITOR_IMUX17_1", - "VFRAME_IMUX17" - ], - [ - "MONITOR_SW4END0_1", - "VFRAME_SW4END0" - ], - [ - "MONITOR_WW4C3_1", - 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"MONITOR_IMUX39_3", - "VFRAME_IMUX39" - ], - [ - "MONITOR_LH3_3", - "VFRAME_LH3" - ], - [ - "MONITOR_WL1END1_3", - "VFRAME_WL1END1" - ], - [ - "MONITOR_WW4B3_3", - "VFRAME_WW4B3" - ], - [ - "MONITOR_IMUX41_3", - "VFRAME_IMUX41" - ], - [ - "MONITOR_IMUX34_3", - "VFRAME_IMUX34" - ], - [ - "MONITOR_FAN3_3", - "VFRAME_FAN3" - ], - [ - "MONITOR_FAN4_3", - "VFRAME_FAN4" - ], - [ - "MONITOR_IMUX33_3", - "VFRAME_IMUX33" - ], - [ - "MONITOR_NW2A3_3", - "VFRAME_NW2A3" - ], - [ - "MONITOR_WL1END2_3", - "VFRAME_WL1END2" - ], - [ - "MONITOR_SE4C2_3", - "VFRAME_SE4C2" - ] - ] - }, - { - "grid_deltas": [ - -1, - -6 - ], - "tile_types": [ - "GTP_COMMON", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTPE2_BYP3_5", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX16_5", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_FAN6_5", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX20_5", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX7_5", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX33_5", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_LOGIC_OUTS_B20_5", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_BYP1_5", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX5_5", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX38_5", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX26_5", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX21_5", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_LOGIC_OUTS_B19_5", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_CTRL0_5", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_IMUX35_5", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX30_5", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX27_5", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_BYP4_5", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_FAN4_5", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_LOGIC_OUTS_B11_5", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTPE2_FAN5_5", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_LOGIC_OUTS_B10_5", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_IMUX23_5", - "VBRK_EXT_IMUX23" ], [ - "GTPE2_IMUX32_5", + "GTPE2_IMUX32_2", "VBRK_EXT_IMUX32" ], [ - "GTPE2_IMUX24_5", - "VBRK_EXT_IMUX24" + "GTPE2_IMUX33_2", + "VBRK_EXT_IMUX33" ], [ - "GTPE2_LOGIC_OUTS_B23_5", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_LOGIC_OUTS_B13_5", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX19_5", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_LOGIC_OUTS_B8_5", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTPE2_IMUX13_5", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX29_5", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX3_5", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_BYP0_5", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_BYP5_5", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX18_5", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX0_5", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX42_5", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX10_5", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_FAN0_5", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_BYP7_5", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX41_5", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX25_5", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX31_5", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_FAN1_5", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_FAN3_5", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX1_5", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_CLK1_5", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_BYP6_5", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX9_5", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_BYP2_5", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_CLK0_5", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_FAN2_5", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX15_5", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX8_5", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX39_5", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX34_5", + "GTPE2_IMUX34_2", "VBRK_EXT_IMUX34" ], [ - "GTPE2_IMUX28_5", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_LOGIC_OUTS_B14_5", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX2_5", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX36_5", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_LOGIC_OUTS_B9_5", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_LOGIC_OUTS_B18_5", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_LOGIC_OUTS_B17_5", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX4_5", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX14_5", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX6_5", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_CTRL1_5", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX17_5", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX45_5", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX43_5", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX37_5", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX44_5", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX46_5", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_FAN7_5", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX12_5", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX11_5", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX47_5", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX40_5", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_LOGIC_OUTS_B16_5", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_IMUX22_5", - "VBRK_EXT_IMUX22" - ] - ] - }, - { - "grid_deltas": [ - 1, - -4 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_SE4BEG1_7", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_NE4BEG0_7", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SW4A3_7", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WL1END3_7", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE4C3_7", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_LH4_7", - "VBRK_LH4" - ], - [ - "CLK_HROW_EL1BEG2_7", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4END1_7", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SE4C1_7", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW2END1_7", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WW4END0_7", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WR1END1_7", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_SE4BEG3_7", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2A2_7", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_NW4A3_7", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_NE4C2_7", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_LH5_7", - "VBRK_LH5" - ], - [ - "CLK_HROW_EE4BEG3_7", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_LH7_7", - "VBRK_LH7" - ], - [ - "CLK_HROW_LH1_7", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4C1_7", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW4B2_7", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_NW4END3_7", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_LH2_7", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE2A0_7", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE4BEG3_7", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WW2A3_7", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WL1END2_7", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_NW2A0_7", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE4C0_7", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_SW2A2_7", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4B2_7", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_ER1BEG3_7", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_SE2A0_7", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WW4END2_7", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_WL1END0_7", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_EE2A3_7", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_EE4BEG1_7", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4BEG2_7", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EE2BEG3_7", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW2A2_7", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_EE4C2_7", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NW4END0_7", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4A1_7", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NW4A1_7", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_NE4BEG1_7", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_SE4BEG2_7", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_LH6_7", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4C2_7", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_ER1BEG0_7", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW4C3_7", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_LH8_7", - "VBRK_LH8" - ], - [ - "CLK_HROW_SW4A1_7", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_EE4B3_7", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_NE4C1_7", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_SW4END1_7", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_SW4END0_7", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_NW4A2_7", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW2A0_7", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WW4END3_7", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE2BEG0_7", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE2A3_7", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_NW2A1_7", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_WW4A0_7", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW4A2_7", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WW4C1_7", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_NW2A3_7", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WW4A1_7", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_ER1BEG1_7", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_EE4BEG0_7", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WR1END3_7", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_WW4A3_7", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_NE2A0_7", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_SE4C0_7", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW2A3_7", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE2A1_7", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_LH3_7", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE4A2_7", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_NE4C0_7", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_WW4B0_7", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_EE4A3_7", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_SW4A0_7", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_WW4B3_7", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4C0_7", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE2A2_7", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE4BEG2_7", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW2END0_7", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_NE2A1_7", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_SW2A0_7", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_NE2A3_7", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW4B1_7", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW2A1_7", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_NW4A0_7", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NW4END1_7", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EE4A0_7", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW2END3_7", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_ER1BEG2_7", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_EE4B1_7", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_NW4END2_7", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_SW4END3_7", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_EL1BEG0_7", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_SE4C2_7", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_SE4BEG0_7", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SW4END2_7", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_LH11_7", - "VBRK_LH11" - ], - [ - "CLK_HROW_SW2A1_7", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_WL1END1_7", - "VBRK_WL1END1" - ], - [ - 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"SE6E2", - "T_TERM_UTURN_INT_SE6E2" - ], - [ - "LVB7", - "T_TERM_UTURN_INT_LVB4" - ], - [ - "SW2A0", - "T_TERM_UTURN_INT_SW2A0" - ], - [ - "NN6E1", - "T_TERM_UTURN_INT_SS6END2" - ], - [ - "NN2BEG1", - "T_TERM_UTURN_INT_SS2A2" - ], - [ - "SE6B3", - "T_TERM_UTURN_INT_SE6B3" - ], - [ - "NW6A1", - "T_TERM_UTURN_INT_SW6B2" - ], - [ - "SE6D0", - "T_TERM_UTURN_INT_SE6D0" - ], - [ - "NN6BEG1", - "T_TERM_UTURN_INT_SS6A2" - ], - [ - "NN6C1", - "T_TERM_UTURN_INT_SS6D2" - ], - [ - "SS6A2", - "T_TERM_UTURN_INT_SS6A2" - ], - [ - "SS6E3", - "T_TERM_UTURN_INT_SS6E3" - ], - [ - "BYP_BOUNCE6", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4" - ], - [ - "NL1BEG1", - "T_TERM_UTURN_INT_SR1END2" - ], - [ - "SS2A2", - "T_TERM_UTURN_INT_SS2A2" - ], - [ - "SS6E0", - "T_TERM_UTURN_INT_SS6E0" - ], - [ - "LV2", - "T_TERM_INT_UTURN_LV_R2" - ], - [ - "NN6BEG0", - "T_TERM_UTURN_INT_SS6A3" - ], - [ - "SE6C2", - "T_TERM_UTURN_INT_SE6C2" - ], - [ - "SE6C3", - "T_TERM_UTURN_INT_SE6C3" - ], - [ - "SW2A2", - "T_TERM_UTURN_INT_SW2A2" - ], - [ - "NN6B2", - "T_TERM_UTURN_INT_SS6C1" - ], - [ - "NE6D3", - "T_TERM_UTURN_INT_SE6E0" - ], - [ - "SS6D0", - "T_TERM_UTURN_INT_SS6D0" - ], - [ - "SS2A1", - "T_TERM_UTURN_INT_SS2A1" - ], - [ - "SR1END3", - "T_TERM_UTURN_INT_SR1END3" - ], - [ - "NR1BEG1", - "T_TERM_UTURN_INT_SL1END2" - ], - [ - "LVB8", - "T_TERM_UTURN_INT_LVB3" - ], - [ - "NN2A0", - "T_TERM_UTURN_INT_SS2END3" - ], - [ - "LVB1", - "T_TERM_UTURN_INT_LVB1" - ], - [ - "WR1BEG_S0", - "T_TERM_UTURN_INT_WR1BEG_S0" - ], - [ - "NN6D1", - "T_TERM_UTURN_INT_SS6E2" - ], - [ - "NW6C2", - "T_TERM_UTURN_INT_SW6D1" - ], - [ - "LV10", - "T_TERM_INT_UTURN_LV_R7" - ], - [ - "SE6D3", - "T_TERM_UTURN_INT_SE6D3" - ], - [ - "NE2BEG2", - "T_TERM_UTURN_INT_SE2A1" - ], - [ - "SS2END3", - "T_TERM_UTURN_INT_SS2END3" - ], - [ - "LV9", - "T_TERM_INT_UTURN_LV_R9" - ], - [ - "NW6A3", - "T_TERM_UTURN_INT_SW6B0" - ], - [ - "SL1END2", - "T_TERM_UTURN_INT_SL1END2" - ], - [ - "SS6B1", - "T_TERM_UTURN_INT_SS6B1" - ], - [ - "NE2BEG3", - "T_TERM_UTURN_INT_SE2A0" - ], - [ - "SS6END0", - "T_TERM_UTURN_INT_SS6END0" - ], - [ - "ER1END3", - "T_TERM_UTURN_INT_ER1END3" - ], - [ - "NN6BEG3", - "T_TERM_UTURN_INT_SS6A0" - ], - [ - "NR1BEG0", - "T_TERM_UTURN_INT_SL1END3" - ], - [ - "NW6D2", - "T_TERM_UTURN_INT_SW6E1" - ], - [ - "LVB5", - "T_TERM_UTURN_INT_LVB5" - ], - [ - "ER1BEG_S0", - "T_TERM_UTURN_INT_ER1BEG_S0" - ], - [ - "SW6D2", - "T_TERM_UTURN_INT_SW6D2" - ], - [ - "SS6E1", - "T_TERM_UTURN_INT_SS6E1" - ], - [ - "SE6C1", - "T_TERM_UTURN_INT_SE6C1" - ], - [ - "SS6C0", - "T_TERM_UTURN_INT_SS6C0" - ], - [ - "NW6C3", - "T_TERM_UTURN_INT_SW6D0" - ], - [ - "SS2END1", - "T_TERM_UTURN_INT_SS2END1" - ], - [ - "SW6C2", - "T_TERM_UTURN_INT_SW6C2" - ], - [ - "LVB2", - "T_TERM_UTURN_INT_LVB2" - ], - [ - "LVB11", - "T_TERM_UTURN_INT_LVB0" - ], - [ - "NN6E3", - "T_TERM_UTURN_INT_SS6END0" - ], - [ - "SW6B0", - "T_TERM_UTURN_INT_SW6B0" - ], - [ - "SW6B1", - "T_TERM_UTURN_INT_SW6B1" - ], - [ - "SE2A0", - "T_TERM_UTURN_INT_SE2A0" - ], - [ - "NW6B1", - "T_TERM_UTURN_INT_SW6C2" - ], - [ - "NE6C0", - "T_TERM_UTURN_INT_SE6D3" - ], - [ - "SW6D1", - "T_TERM_UTURN_INT_SW6D1" - ], - [ - "LVB9", - "T_TERM_UTURN_INT_LVB2" - ], - [ - "NN6E2", - "T_TERM_UTURN_INT_SS6END1" - ], - [ - "SR1END2", - "T_TERM_UTURN_INT_SR1END2" - ], - [ - "SE6E3", - "T_TERM_UTURN_INT_SE6E3" - ], - [ - "NN2BEG3", - "T_TERM_UTURN_INT_SS2A0" - ], - [ - "NW6B2", - "T_TERM_UTURN_INT_SW6C1" - ], - [ - "SS6C1", - "T_TERM_UTURN_INT_SS6C1" - ], - [ - "SS6E2", - "T_TERM_UTURN_INT_SS6E2" - ], - [ - "NN2BEG0", - "T_TERM_UTURN_INT_SS2A3" - ], - [ - "WL1BEG3", - "T_TERM_UTURN_INT_WR1BEG_S0" - ], - [ - "NE6A2", - "T_TERM_UTURN_INT_SE6B1" - ], - [ - "SW6B3", - "T_TERM_UTURN_INT_SW6B3" - ], - [ - "NN6D2", - "T_TERM_UTURN_INT_SS6E1" - ], - [ - "NW6A0", - "T_TERM_UTURN_INT_SW6B3" - ], - [ - "SW6C3", - "T_TERM_UTURN_INT_SW6C3" - ], - [ - "SE6B2", - "T_TERM_UTURN_INT_SE6B2" - ], - [ - "NW6A2", - "T_TERM_UTURN_INT_SW6B1" - ], - [ - "SE6B1", - "T_TERM_UTURN_INT_SE6B1" - ], - [ - "SE6E1", - "T_TERM_UTURN_INT_SE6E1" - ], - [ - "NE6C2", - "T_TERM_UTURN_INT_SE6D1" - ], - [ - "SE6B0", - "T_TERM_UTURN_INT_SE6B0" - ], - [ - "SW6B2", - "T_TERM_UTURN_INT_SW6B2" - ], - [ - "NE6D2", - "T_TERM_UTURN_INT_SE6E1" - ], - [ - "EL1END_S3_0", - "T_TERM_UTURN_INT_ER1END3" - ], - [ - "LVB4", - "T_TERM_UTURN_INT_LVB4" - ], - [ - "NW6D0", - "T_TERM_UTURN_INT_SW6E3" - ], - [ - "SL1END0", - "T_TERM_UTURN_INT_SL1END0" - ], - [ - "LVB10", - "T_TERM_UTURN_INT_LVB1" - ], - [ - "SS6A3", - "T_TERM_UTURN_INT_SS6A3" - ], - [ - "FAN_BOUNCE_S3_0", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0" - ], - [ - "SS6A1", - "T_TERM_UTURN_INT_SS6A1" - ], - [ - "LV6", - "T_TERM_INT_UTURN_LV_R6" - ], - [ - "LV14", - "T_TERM_INT_UTURN_LV_R3" - ], - [ - "NN2A2", - "T_TERM_UTURN_INT_SS2END1" - ], - [ - "LV17", - "T_TERM_INT_UTURN_LV_R17" - ], - [ - "SW6C1", - "T_TERM_UTURN_INT_SW6C1" - ], - [ - "NW6D3", - "T_TERM_UTURN_INT_SW6E0" - ], - [ - "SE6D2", - "T_TERM_UTURN_INT_SE6D2" - ], - [ - "SE2A1", - "T_TERM_UTURN_INT_SE2A1" - ], - [ - "SW6E0", - "T_TERM_UTURN_INT_SW6E0" - ], - [ - "NR1BEG3", - "T_TERM_UTURN_INT_SL1END0" - ], - [ - "SW6E2", - "T_TERM_UTURN_INT_SW6E2" - ], - [ - "SS6D3", - "T_TERM_UTURN_INT_SS6D3" - ], - [ - "SE6D1", - "T_TERM_UTURN_INT_SE6D1" - ], - [ - "NW2BEG2", - "T_TERM_UTURN_INT_SW2A1" - ], - [ - "NL1BEG0", - "T_TERM_UTURN_INT_SR1END3" - ], - [ - "SL1END3", - "T_TERM_UTURN_INT_SL1END3" - ], - [ - "LV0", - "T_TERM_INT_UTURN_LV_R17" - ], - [ - "SW6E3", - "T_TERM_UTURN_INT_SW6E3" - ], - [ - "NE6A3", - "T_TERM_UTURN_INT_SE6B0" - ], - [ - "NN6D3", - "T_TERM_UTURN_INT_SS6E0" - ], - [ - "NE6C3", - "T_TERM_UTURN_INT_SE6D0" - ], - [ - "NE2BEG1", - "T_TERM_UTURN_INT_SE2A2" - ], - [ - "NW6D1", - "T_TERM_UTURN_INT_SW6E2" - ], - [ - "FAN_BOUNCE_S3_6", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6" - ], - [ - "LV8", - "T_TERM_INT_UTURN_LV_R9" - ], - [ - "NN6A1", - "T_TERM_UTURN_INT_SS6B2" - ], - [ - "NN6C0", - "T_TERM_UTURN_INT_SS6D3" - ], - [ - "NW6C0", - "T_TERM_UTURN_INT_SW6D3" - ], - [ - "NW2BEG0", - "T_TERM_UTURN_INT_SW2A3" - ], - [ - "LV1", - "T_TERM_INT_UTURN_LV_R16" - ], - [ - "NW6B0", - "T_TERM_UTURN_INT_SW6C3" - ], - [ - "LV15", - "T_TERM_INT_UTURN_LV_R2" - ], - [ - "SS2END2", - "T_TERM_UTURN_INT_SS2END2" - ], - [ - "SS6B3", - "T_TERM_UTURN_INT_SS6B3" - ], - [ - "NE6A0", - "T_TERM_UTURN_INT_SE6B3" - ], - [ - "NN6E0", - "T_TERM_UTURN_INT_SS6END3" - ], - [ - "SW6E1", - "T_TERM_UTURN_INT_SW6E1" - ], - [ - "NW2BEG3", - "T_TERM_UTURN_INT_SW2A0" - ], - [ - "NN6D0", - "T_TERM_UTURN_INT_SS6E3" - ], - [ - "SW6D0", - "T_TERM_UTURN_INT_SW6D0" - ], - [ - "LV16", - "T_TERM_INT_UTURN_LV_R16" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH6_0", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_LH7_0", - "VBRK_LH7" - ], - [ - "CLK_HROW_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_LH1_0", - "VBRK_LH1" - ], - [ - "CLK_HROW_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH9_0", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_HROW_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_NE2A1_0", - "VBRK_NE2A1" - ], - [ - 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], - [ - "CFG_CENTER_CTRL1_7", - "VFRAME_CTRL1" - ], - [ - "CFG_CENTER_NW2A2_7", - "VFRAME_NW2A2" - ], - [ - "CFG_CENTER_NE4BEG2_7", - "VFRAME_NE4BEG2" - ], - [ - "CFG_CENTER_SW2A2_7", - "VFRAME_SW2A2" - ], - [ - "CFG_CENTER_SW4END2_7", - "VFRAME_SW4END2" - ], - [ - "CFG_CENTER_IMUX20_7", - "VFRAME_IMUX20" - ], - [ - "CFG_CENTER_IMUX15_7", - "VFRAME_IMUX15" - ], - [ - "CFG_CENTER_NW4END3_7", - "VFRAME_NW4END3" - ], - [ - "CFG_CENTER_IMUX16_7", - "VFRAME_IMUX16" - ], - [ - "CFG_CENTER_CLK0_7", - "VFRAME_CLK0" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B23_7", - "VFRAME_LOGIC_OUTS_B23" - ], - [ - "CFG_CENTER_FAN5_7", - "VFRAME_FAN5" - ], - [ - "CFG_CENTER_IMUX29_7", - "VFRAME_IMUX29" - ], - [ - "CFG_CENTER_LH2_7", - "VFRAME_LH2" - ], - [ - "CFG_CENTER_WW4END0_7", - "VFRAME_WW4END0" - ], - [ - "CFG_CENTER_IMUX46_7", - "VFRAME_IMUX46" - ], - [ - "CFG_CENTER_EE4B0_7", - "VFRAME_EE4B0" - ], - [ - "CFG_CENTER_SW2A1_7", - "VFRAME_SW2A1" - ], - [ - "CFG_CENTER_IMUX37_7", - "VFRAME_IMUX37" - ], - [ - "CFG_CENTER_IMUX41_7", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_CLK1_7", - "VFRAME_CLK1" - ], - [ - "CFG_CENTER_WW2END0_7", - "VFRAME_WW2END0" - ], - [ - "CFG_CENTER_SE4C2_7", - "VFRAME_SE4C2" - ], - [ - "CFG_CENTER_WW4A3_7", - "VFRAME_WW4A3" - ], - [ - "CFG_CENTER_BYP1_7", - "VFRAME_BYP1" - ], - [ - "CFG_CENTER_IMUX26_7", - "VFRAME_IMUX26" - ], - [ - "CFG_CENTER_NW4A1_7", - "VFRAME_NW4A1" - ], - [ - "CFG_CENTER_WW2A0_7", - "VFRAME_WW2A0" - ], - [ - "CFG_CENTER_LH7_7", - "VFRAME_LH7" - ], - [ - "CFG_CENTER_FAN1_7", - "VFRAME_FAN1" - ], - [ - "CFG_CENTER_IMUX47_7", - "VFRAME_IMUX47" - ], - [ - "CFG_CENTER_LH5_7", - "VFRAME_LH5" - ], - [ - "CFG_CENTER_IMUX39_7", - "VFRAME_IMUX39" - ], - [ - "CFG_CENTER_IMUX4_7", - "VFRAME_IMUX4" - ], - [ - "CFG_CENTER_IMUX33_7", - "VFRAME_IMUX33" - ], - [ - "CFG_CENTER_FAN7_7", - "VFRAME_FAN7" - ], - [ - "CFG_CENTER_WL1END3_7", - "VFRAME_WL1END3" - ], - [ - "CFG_CENTER_WW4B3_7", - "VFRAME_WW4B3" - ], - [ - "CFG_CENTER_IMUX24_7", - "VFRAME_IMUX24" - ], - [ - "CFG_CENTER_WW4END3_7", - "VFRAME_WW4END3" - ], - [ - "CFG_CENTER_WW2END2_7", - "VFRAME_WW2END2" - ], - [ - "CFG_CENTER_WW4C3_7", - "VFRAME_WW4C3" - ], - [ - "CFG_CENTER_NE4C1_7", - "VFRAME_NE4C1" - ], - [ - "CFG_CENTER_EE4C2_7", - "VFRAME_EE4C2" - ], - [ - "CFG_CENTER_NE4C2_7", - "VFRAME_NE4C2" - ], - [ - "CFG_CENTER_WL1END1_7", - "VFRAME_WL1END1" - ], - [ - "CFG_CENTER_WW4END1_7", - "VFRAME_WW4END1" - ], - [ - "CFG_CENTER_NE4C0_7", - "VFRAME_NE4C0" - ], - [ - "CFG_CENTER_BYP0_7", - "VFRAME_BYP0" - ], - [ - "CFG_CENTER_IMUX44_7", - "VFRAME_IMUX44" - ], - [ - "CFG_CENTER_ER1BEG3_7", - "VFRAME_ER1BEG3" - ], - [ - "CFG_CENTER_LH9_7", - "VFRAME_LH9" - ], - [ - "CFG_CENTER_SW4A3_7", - "VFRAME_SW4A3" - ], - [ - "CFG_CENTER_SW4A2_7", - "VFRAME_SW4A2" - ], - [ - "CFG_CENTER_EE4BEG3_7", - "VFRAME_EE4BEG3" - ], - [ - "CFG_CENTER_IMUX28_7", - "VFRAME_IMUX28" - ], - [ - "CFG_CENTER_WW4C2_7", - "VFRAME_WW4C2" - ], - [ - "CFG_CENTER_EE2A1_7", - "VFRAME_EE2A1" - ], - [ - "CFG_CENTER_WL1END0_7", - "VFRAME_WL1END0" - ], - [ - "CFG_CENTER_IMUX5_7", - "VFRAME_IMUX5" - ], - [ - "CFG_CENTER_IMUX42_7", - "VFRAME_IMUX42" - ], - [ - "CFG_CENTER_LH11_7", - "VFRAME_LH11" - ], - [ - "CFG_CENTER_NW4A3_7", - "VFRAME_NW4A3" - ], - [ - "CFG_CENTER_WR1END2_7", - "VFRAME_WR1END2" - ], - [ - "CFG_CENTER_CTRL0_7", - "VFRAME_CTRL0" - ], - [ - "CFG_CENTER_EL1BEG3_7", - "VFRAME_EL1BEG3" - ], - [ - "CFG_CENTER_IMUX25_7", - "VFRAME_IMUX25" - ], - [ - "CFG_CENTER_EL1BEG2_7", - "VFRAME_EL1BEG2" - ], - [ - "CFG_CENTER_IMUX31_7", - "VFRAME_IMUX31" - ], - [ - "CFG_CENTER_WW4A2_7", - "VFRAME_WW4A2" - ], - [ - "CFG_CENTER_EE2BEG1_7", - "VFRAME_EE2BEG1" - ], - [ - "CFG_CENTER_WW2A3_7", - "VFRAME_WW2A3" - ], - [ - "CFG_CENTER_IMUX45_7", - "VFRAME_IMUX45" - ], - [ - "CFG_CENTER_NE2A1_7", - "VFRAME_NE2A1" - ], - [ - "CFG_CENTER_EE4B1_7", - "VFRAME_EE4B1" - ], - [ - "CFG_CENTER_IMUX3_7", - "VFRAME_IMUX3" - ], - [ - "CFG_CENTER_EE2BEG3_7", - "VFRAME_EE2BEG3" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B22_7", - "VFRAME_LOGIC_OUTS_B22" - ], - [ - "CFG_CENTER_NE4C3_7", - "VFRAME_NE4C3" - ], - [ - "CFG_CENTER_LH3_7", - "VFRAME_LH3" - ], - [ - "CFG_CENTER_WL1END2_7", - "VFRAME_WL1END2" - ], - [ - "CFG_CENTER_WW2A2_7", - "VFRAME_WW2A2" - ], - [ - "CFG_CENTER_IMUX22_7", - "VFRAME_IMUX22" - ], - [ - "CFG_CENTER_EE4B3_7", - "VFRAME_EE4B3" - ], - [ - "CFG_CENTER_IMUX6_7", - "VFRAME_IMUX6" - ], - [ - "CFG_CENTER_NE2A2_7", - "VFRAME_NE2A2" - ], - [ - "CFG_CENTER_IMUX38_7", - "VFRAME_IMUX38" - ], - [ - "CFG_CENTER_SE4BEG3_7", - "VFRAME_SE4BEG3" - ], - [ - "CFG_CENTER_SE4BEG0_7", - "VFRAME_SE4BEG0" - ], - [ - "CFG_CENTER_EE4C3_7", - "VFRAME_EE4C3" - ], - [ - "CFG_CENTER_WR1END3_7", - "VFRAME_WR1END3" - ], - [ - "CFG_CENTER_IMUX34_7", - "VFRAME_IMUX34" - ], - [ - "CFG_CENTER_FAN2_7", - "VFRAME_FAN2" - ], - [ - "CFG_CENTER_SE4BEG1_7", - "VFRAME_SE4BEG1" - ], - [ - "CFG_CENTER_IMUX27_7", - "VFRAME_IMUX27" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMVIOB" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_CK_IN_R6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "CLK_HROW_CK_BUFHCLK_R10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "CLK_HROW_CK_IN_R7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "CLK_HROW_CK_BUFRCLK_R1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "CLK_HROW_CK_IN_R9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "CLK_HROW_CK_IN_R2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "CLK_HROW_CK_BUFHCLK_R11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "CLK_HROW_CK_IN_R3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_R7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "CLK_HROW_CK_BUFHCLK_R3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_R9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "CLK_HROW_CK_IN_R12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "CLK_HROW_CK_BUFRCLK_R0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "CLK_HROW_CK_IN_R4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "CLK_HROW_CK_BUFHCLK_R6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "CLK_HROW_CK_IN_R13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "CLK_HROW_CK_BUFHCLK_R4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "CLK_HROW_CK_BUFHCLK_R5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "CLK_HROW_CK_IN_R10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "CLK_HROW_CK_IN_R11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "CLK_HROW_CK_IN_R5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "CLK_HROW_CK_IN_R1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "CLK_HROW_CK_BUFHCLK_R0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "CLK_HROW_CK_IN_R8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "CLK_HROW_CK_BUFHCLK_R2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "CLK_HROW_CK_BUFHCLK_R1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "CLK_HROW_CK_BUFRCLK_R3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_R8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "CLK_HROW_CK_BUFRCLK_R2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "CLK_HROW_CK_IN_R0", - "HCLK_VBRK_MUX_CLK0" - ] - ] - }, - { - "grid_deltas": [ - -1, - -3 - ], - "tile_types": [ - "CFG_CENTER_TOP", - "INT_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "CFG_CENTER_EE4B0_3", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_EE4B2_3", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_EE4C0_3", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_SE4BEG1_3", - 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"CFG_CENTER_NW4A2_3", - "INT_FEEDTHRU_2_NW4A2" - ], - [ - "CFG_CENTER_WL1END0_3", - "INT_FEEDTHRU_2_WL1END0" - ], - [ - "CFG_CENTER_EE2A2_3", - "INT_FEEDTHRU_2_EE2A2" - ], - [ - "CFG_CENTER_SE2A0_3", - "INT_FEEDTHRU_2_SE2A0" - ], - [ - "CFG_CENTER_WW4B1_3", - "INT_FEEDTHRU_2_WW4B1" - ], - [ - "CFG_CENTER_SE4BEG2_3", - "INT_FEEDTHRU_2_SE4BEG2" - ], - [ - "CFG_CENTER_NE4BEG0_3", - "INT_FEEDTHRU_2_NE4BEG0" - ], - [ - "CFG_CENTER_NW4END0_3", - "INT_FEEDTHRU_2_NW4END0" - ], - [ - "CFG_CENTER_SW2A2_3", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_WL1END3_3", - "INT_FEEDTHRU_2_WL1END3" - ], - [ - "CFG_CENTER_EE4BEG2_3", - "INT_FEEDTHRU_2_EE4BEG2" - ], - [ - "CFG_CENTER_SW4A0_3", - "INT_FEEDTHRU_2_SW4A0" - ], - [ - "CFG_CENTER_WW4C3_3", - "INT_FEEDTHRU_2_WW4C3" - ], - [ - "CFG_CENTER_EL1BEG1_3", - "INT_FEEDTHRU_2_EL1BEG1" - ], - [ - "CFG_CENTER_EL1BEG0_3", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_NE4C2_3", - "INT_FEEDTHRU_2_NE4C2" - ], - [ - "CFG_CENTER_NW4A3_3", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_LH4_3", - "INT_FEEDTHRU_2_LH4" - ], - [ - "CFG_CENTER_LH5_3", - "INT_FEEDTHRU_2_LH5" - ], - [ - "CFG_CENTER_WW4B3_3", - "INT_FEEDTHRU_2_WW4B3" - ], - [ - "CFG_CENTER_LH7_3", - "INT_FEEDTHRU_2_LH7" - ], - [ - "CFG_CENTER_SE4C3_3", - "INT_FEEDTHRU_2_SE4C3" - ], - [ - "CFG_CENTER_SE4C0_3", - "INT_FEEDTHRU_2_SE4C0" - ], - [ - "CFG_CENTER_WW4A3_3", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_WW4C1_3", - "INT_FEEDTHRU_2_WW4C1" - ], - [ - "CFG_CENTER_WW2END2_3", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_WR1END1_3", - "INT_FEEDTHRU_2_WR1END1" - ], - [ - "CFG_CENTER_WW2END1_3", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_WW4B2_3", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_WW2A0_3", - "INT_FEEDTHRU_2_WW2A0" - ], - [ - "CFG_CENTER_SW4END3_3", - "INT_FEEDTHRU_2_SW4END3" - ], - [ - "CFG_CENTER_NE2A0_3", - "INT_FEEDTHRU_2_NE2A0" - ], - [ - "CFG_CENTER_NE2A1_3", - "INT_FEEDTHRU_2_NE2A1" - ], - [ - "CFG_CENTER_LH1_3", - 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"INT_FEEDTHRU_2_LH9" - ], - [ - "CFG_CENTER_NW2A1_3", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_LH6_3", - "INT_FEEDTHRU_2_LH6" - ], - [ - "CFG_CENTER_EE4A2_3", - "INT_FEEDTHRU_2_EE4A2" - ], - [ - "CFG_CENTER_SW4A2_3", - "INT_FEEDTHRU_2_SW4A2" - ], - [ - "CFG_CENTER_EE4C1_3", - "INT_FEEDTHRU_2_EE4C1" - ], - [ - "CFG_CENTER_NE2A3_3", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_WW4A1_3", - "INT_FEEDTHRU_2_WW4A1" - ], - [ - "CFG_CENTER_EE2BEG0_3", - "INT_FEEDTHRU_2_EE2BEG0" - ], - [ - "CFG_CENTER_WL1END1_3", - "INT_FEEDTHRU_2_WL1END1" - ], - [ - "CFG_CENTER_NW4END1_3", - "INT_FEEDTHRU_2_NW4END1" - ], - [ - "CFG_CENTER_WW4END0_3", - "INT_FEEDTHRU_2_WW4END0" - ], - [ - "CFG_CENTER_NE4BEG2_3", - "INT_FEEDTHRU_2_NE4BEG2" - ], - [ - "CFG_CENTER_EE4B1_3", - "INT_FEEDTHRU_2_EE4B1" - ], - [ - "CFG_CENTER_LH12_3", - "INT_FEEDTHRU_2_LH12" - ], - [ - "CFG_CENTER_NW2A2_3", - "INT_FEEDTHRU_2_NW2A2" - ], - [ - "CFG_CENTER_EL1BEG2_3", - "INT_FEEDTHRU_2_EL1BEG2" - ], - [ - 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"CMT_TOP_EE2BEG0_8", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_SE4BEG3_8", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW4C2_8", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_SW2A2_8", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_WW4C1_8", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_WL1END2_8", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_WW2END0_8", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_SW4A0_8", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_NW2A0_8", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_WL1END0_8", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_EE4A3_8", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_WR1END0_8", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_EE4BEG3_8", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_ER1BEG1_8", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_NE4C3_8", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_NW4END2_8", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_SW4A1_8", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_EE2A1_8", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_LH4_8", - "VBRK_LH4" - ], - [ - "CMT_TOP_WW4B3_8", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_SE4C0_8", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_SE2A3_8", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_SE4C3_8", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WL1END1_8", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_WW2END2_8", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_LH8_8", - "VBRK_LH8" - ], - [ - "CMT_TOP_EE4A1_8", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_WW2END1_8", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_WW2END3_8", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_WW4C0_8", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_EE4C1_8", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_EE2A3_8", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_LH3_8", - "VBRK_LH3" - ], - [ - "CMT_TOP_LH10_8", - "VBRK_LH10" - ], - [ - "CMT_TOP_WR1END1_8", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_NE4BEG1_8", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_WW2A2_8", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_EE4A2_8", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_NE4C2_8", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_EE2BEG3_8", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_NW4END3_8", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW4A0_8", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_LH12_8", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE4BEG2_8", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_WW4B0_8", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_SW4END0_8", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_WW4END1_8", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_EE4BEG0_8", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_NW2A2_8", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WW4END0_8", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_EE4B1_8", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_EE2A2_8", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_LH5_8", - "VBRK_LH5" - ], - [ - "CMT_TOP_NW2A3_8", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_NE4BEG0_8", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_SW2A0_8", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_WW4B1_8", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WW4B2_8", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_NE2A2_8", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_NE4C0_8", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_EE2BEG2_8", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_WR1END3_8", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW2A3_8", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_SE2A2_8", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_WW4END3_8", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_WW4C3_8", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_SE2A0_8", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_WW4END2_8", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_LH1_8", - "VBRK_LH1" - ], - [ - "CMT_TOP_SW4END2_8", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_SE4BEG0_8", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_MONITOR_N_8", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_WR1END2_8", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_LH9_8", - "VBRK_LH9" - ], - [ - "CMT_TOP_SW2A3_8", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_SE4C2_8", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_LH11_8", - "VBRK_LH11" - ], - [ - "CMT_TOP_SE4BEG1_8", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_EE4A0_8", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_SW4END3_8", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SW4A3_8", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_EL1BEG3_8", - "VBRK_EL1BEG3" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "HCLK_L", - "INT_L" - ], - "wire_pairs": [ - [ - "HCLK_FAN_BOUNCE_S3_6", - "FAN_BOUNCE6" - ], - [ - "HCLK_SE6E1", - "SE6D1" - ], - [ - "HCLK_SW6B0", - "SW6A0" - ], - [ - "HCLK_NW6B3", - "NW6C3" - ], - [ - "HCLK_LVB2", - "LVB_L2" - ], - [ - "HCLK_EL1BEG3", - "EL1BEG_N3" - ], - [ - "HCLK_SE6B0", - "SE6A0" - ], - [ - "HCLK_SS6D3", - "SS6C3" - ], - [ - "HCLK_SW6D3", - "SW6C3" - ], - [ - "HCLK_LV10", - "LV_L11" - ], - [ - "HCLK_SS6B1", - "SS6A1" - ], - [ - "HCLK_SW2END0", - "SW2BEG0" - ], - [ - "HCLK_SE6B1", - "SE6A1" - ], - [ - "HCLK_LVB4", - "LVB_L4" - ], - [ - "HCLK_NL1BEG2", - "NL1END2" - ], - [ - "HCLK_WR1BEG_S0", - "WR1BEG0" - ], - [ - "HCLK_NN6A2", - "NN6B2" - ], - [ - "HCLK_NE6B3", - "NE6C3" - ], - [ - "HCLK_NN2BEG2", - "NN2A2" - ], - [ - "HCLK_ER1BEG_S0", - "ER1BEG0" - ], - [ - "HCLK_NN6BEG3", - "NN6A3" - ], - [ - "HCLK_NW6D2", - "NW6E2" - ], - [ - "HCLK_SW2END2", - "SW2BEG2" - ], - [ - "HCLK_SW6D2", - "SW6C2" - ], - [ - "HCLK_LV4", - "LV_L5" - ], - [ - "HCLK_SS2END0", - "SS2A0" - ], - [ - "HCLK_LEAF_CLK_B_TOPL3", - "GCLK_L_B9" - ], - [ - "HCLK_NW6A3", - "NW6B3" - ], - [ - "HCLK_SW6D0", - "SW6C0" - ], - [ - "HCLK_SS6B2", - "SS6A2" - ], - [ - "HCLK_NE6A2", - "NE6B2" - ], - [ - "HCLK_NE6D1", - "NE6E1" - ], - [ - "HCLK_SW6B3", - "SW6A3" - ], - [ - "HCLK_SS6A0", - "SS6BEG0" - ], - [ - "HCLK_SE2A0", - "SE2BEG0" - ], - [ - "HCLK_NE6D0", - "NE6E0" - ], - [ - "HCLK_NW2A1", - "NW2A1" - ], - [ - "HCLK_FAN_BOUNCE_S3_4", - "FAN_BOUNCE4" - ], - [ - "HCLK_SW6D1", - "SW6C1" - ], - [ - "HCLK_NN2BEG0", - "NN2A0" - ], - [ - "HCLK_LV16", - "LV_L17" - ], - [ - "HCLK_SS6END_N0_3", - "SS6END_N0_3" - ], - [ - "HCLK_SS6END3", - "SS6E3" - ], - [ - "HCLK_NE2BEG3", - "NE2A3" - ], - [ - "HCLK_NN6B3", - "NN6C3" - ], - [ - "HCLK_NN6B1", - "NN6C1" - ], - [ - "HCLK_NN6D3", - "NN6E3" - ], - [ - "HCLK_SS6E1", - "SS6D1" - ], - [ - "HCLK_SE6C1", - "SE6B1" - ], - [ - "HCLK_NN6C2", - "NN6D2" - ], - [ - "HCLK_BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" - ], - [ - "HCLK_NN2A0", - "NN2END0" - ], - [ - "HCLK_SS6END0", - "SS6E0" - ], - [ - "HCLK_LV14", - "LV_L15" - ], - [ - "HCLK_SW6E0", - "SW6D0" - ], - [ - "HCLK_NE6D2", - "NE6E2" - ], - [ - "HCLK_SR1END2", - "SR1BEG2" - ], - [ - "HCLK_SS2A0", - "SS2BEG0" - ], - [ - "HCLK_NN2A3", - "NN2END3" - ], - [ - "HCLK_LVB7", - "LVB_L7" - ], - [ - "HCLK_NW6A1", - "NW6B1" - ], - [ - "HCLK_SE6D2", - "SE6C2" - ], - [ - "HCLK_LVB3", - "LVB_L3" - ], - [ - "HCLK_WL1END3", - "WL1END_N1_3" - ], - [ - "HCLK_NE2BEG1", - "NE2A1" - ], - [ - "HCLK_NE6C3", - "NE6D3" - ], - [ - "HCLK_NE2BEG0", - "NE2A0" - ], - [ - "HCLK_NE6A3", - "NE6B3" - ], - [ - "HCLK_SW2END1", - "SW2BEG1" - ], - [ - "HCLK_SW6C3", - "SW6B3" - ], - [ - "HCLK_SE6E3", - "SE6D3" - ], - [ - "HCLK_SE6C2", - "SE6B2" - ], - [ - "HCLK_LV8", - "LV_L9" - ], - [ - "HCLK_SS2END_N0_3", - "SS2END_N0_3" - ], - [ - "HCLK_NE6A0", - "NE6B0" - ], - [ - "HCLK_LEAF_CLK_B_TOPL1", - "GCLK_L_B7" - ], - [ - "HCLK_NW2A3", - "NW2A3" - ], - [ - "HCLK_SS6E3", - "SS6D3" - ], - [ - "HCLK_NE6C0", - "NE6D0" - ], - [ - "HCLK_SE2A1", - "SE2BEG1" - ], - [ - "HCLK_SL1END0", - "SL1BEG0" - ], - [ - "HCLK_NN6BEG2", - "NN6A2" - ], - [ - "HCLK_NL1END_S3_0", - "NL1END0" - ], - [ - "HCLK_SS6B0", - "SS6A0" - ], - [ - "HCLK_NW6A2", - "NW6B2" - ], - [ - "HCLK_NN6C1", - "NN6D1" - ], - [ - "HCLK_SS6C0", - "SS6B0" - ], - [ - "HCLK_SW6C1", - "SW6B1" - ], - [ - "HCLK_NN6C0", - "NN6D0" - ], - [ - "HCLK_LV5", - "LV_L6" - ], - [ - "HCLK_NE6D3", - "NE6E3" - ], - [ - "HCLK_SR1BEG3", - "SR1BEG3" - ], - [ - "HCLK_SS6B3", - "SS6A3" - ], - [ - "HCLK_NN6B0", - "NN6C0" - ], - [ - "HCLK_NN6E1", - "NN6END1" - ], - [ - "HCLK_LVB6", - "LVB_L6" - ], - [ - "HCLK_NW2END_S0_0", - "NW2END0" - ], - [ - "HCLK_SE6D0", - "SE6C0" - ], - [ - "HCLK_NW6B0", - "NW6C0" - ], - [ - "HCLK_SS2A1", - "SS2BEG1" - ], - [ - "HCLK_SE6D1", - "SE6C1" - ], - [ - "HCLK_WW2END3", - "WW2END_N0_3" - ], - [ - "HCLK_NN6D1", - "NN6E1" - ], - [ - "HCLK_SS6C2", - "SS6B2" - ], - [ - "HCLK_NL1BEG0", - "NL1END0" - ], - [ - "HCLK_SL1END1", - "SL1BEG1" - ], - [ - "HCLK_LVB1", - "LVB_L1" - ], - [ - "HCLK_SL1END3", - "SL1BEG3" - ], - [ - "HCLK_NE6C2", - "NE6D2" - ], - [ - "HCLK_SW6E1", - "SW6D1" - ], - [ - "HCLK_SR1END1", - "SR1BEG1" - ], - [ - "HCLK_BYP_BOUNCE7", - "BYP_BOUNCE_N3_7" - ], - [ - "HCLK_NW2A2", - "NW2A2" - ], - [ - "HCLK_NN2BEG3", - "NN2A3" - ], - [ - "HCLK_LVB5", - "LVB_L5" - ], - [ - "HCLK_SE6B2", - "SE6A2" - ], - [ - "HCLK_NW6C1", - "NW6D1" - ], - [ - "HCLK_SS6D0", - "SS6C0" - ], - [ - "HCLK_LEAF_CLK_B_TOPL4", - "GCLK_L_B10" - ], - [ - "HCLK_LV11", - "LV_L12" - ], - [ - "HCLK_NN6D2", - "NN6E2" - ], - [ - "HCLK_SS2A2", - "SS2BEG2" - ], - [ - "HCLK_NW6D0", - "NW6E0" - ], - [ - "HCLK_NN2A2", - "NN2END2" - ], - [ - "HCLK_LVB10", - "LVB_L10" - ], - [ - "HCLK_NE2BEG2", - "NE2A2" - ], - [ - "HCLK_NL1BEG1", - "NL1END1" - ], - [ - "HCLK_NR1BEG0", - "NR1END0" - ], - [ - "HCLK_NN6A3", - "NN6B3" - ], - [ - "HCLK_SS6END2", - "SS6E2" - ], - [ - "HCLK_LV13", - "LV_L14" - ], - [ - "HCLK_NN6BEG1", - "NN6A1" - ], - [ - "HCLK_SE6E2", - "SE6D2" - ], - [ - "HCLK_SL1END2", - "SL1BEG2" - ], - [ - "HCLK_NN6E3", - "NN6END3" - ], - [ - "HCLK_ER1END3", - "ER1END_N3_3" - ], - [ - "HCLK_LEAF_CLK_B_TOPL5", - "GCLK_L_B11" - ], - [ - "HCLK_SS2A3", - "SS2A3" - ], - [ - "HCLK_NN6BEG0", - "NN6A0" - ], - [ - "HCLK_SW2A3", - "SW2BEG3" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END_N0_3" - ], - [ - "HCLK_NN2END_S2_0", - "NN2END0" - ], - [ - "HCLK_SE6C0", - "SE6B0" - ], - [ - "HCLK_LV3", - "LV_L4" - ], - [ - "HCLK_SS6E2", - "SS6D2" - ], - [ - "HCLK_SE6E0", - "SE6D0" - ], - [ - "HCLK_LVB11", - "LVB_L11" - ], - [ - "HCLK_NN2BEG1", - "NN2A1" - ], - [ - "HCLK_SW6END3", - "SW6END_N0_3" - ], - [ - "HCLK_SS6C1", - "SS6B1" - ], - [ - "HCLK_SR1END_N3_3", - "SR1END_N3_3" - ], - [ - "HCLK_SS6A2", - "SS6BEG2" - ], - [ - "HCLK_SW6B1", - "SW6A1" - ], - [ - "HCLK_NW6A0", - "NW6B0" - ], - [ - "HCLK_SW6C2", - "SW6B2" - ], - [ - "HCLK_NR1BEG2", - "NR1END2" - ], - [ - "HCLK_NN6A1", - "NN6B1" - ], - [ - "HCLK_SS2BEG3", - "SS2BEG3" - ], - [ - "HCLK_NE6B2", - "NE6C2" - ], - [ - "HCLK_LV17", - "LV_L18" - ], - [ - "HCLK_NW6C0", - "NW6D0" - ], - [ - "HCLK_NN2A1", - "NN2END1" - ], - [ - "HCLK_SE6D3", - "SE6C3" - ], - [ - "HCLK_SS6END1", - "SS6E1" - ], - [ - "HCLK_NE6A1", - "NE6B1" - ], - [ - "HCLK_SE2A3", - "SE2BEG3" - ], - [ - "HCLK_NN6E0", - "NN6END0" - ], - [ - "HCLK_NN6END_S1_0", - "NN6END0" - ], - [ - "HCLK_WL1BEG3", - "WL1BEG_N3" - ], - [ - "HCLK_SE6C3", - "SE6B3" - ], - [ - "HCLK_NN6C3", - "NN6D3" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "HCLK_NE6B1", - "NE6C1" - ], - [ - "HCLK_LV15", - "LV_L16" - ], - [ - "HCLK_NN6D0", - "NN6E0" - ], - [ - "HCLK_SS6D2", - "SS6C2" - ], - [ - "HCLK_EL1END_S3_0", - "EL1END0" - ], - [ - "HCLK_LV9", - "LV_L10" - ], - [ - "HCLK_LVB8", - "LVB_L8" - ], - [ - "HCLK_LV7", - "LV_L8" - ], - [ - "HCLK_SE2A2", - "SE2BEG2" - ], - [ - "HCLK_LVB9", - "LVB_L9" - ], - [ - "HCLK_NE6C1", - "NE6D1" - ], - [ - "HCLK_NW6C2", - "NW6D2" - ], - [ - "HCLK_SW6C0", - "SW6B0" - ], - [ - "HCLK_NW6D1", - "NW6E1" - ], - [ - "HCLK_NW6B1", - "NW6C1" - ], - [ - "HCLK_NW6C3", - "NW6D3" - ], - [ - "HCLK_LV2", - "LV_L3" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END0" - ], - [ - "HCLK_SS6C3", - "SS6B3" - ], - [ - "HCLK_LV12", - "LV_L13" - ], - [ - "HCLK_NW2A0", - "NW2A0" - ], - [ - "HCLK_FAN_BOUNCE_S3_0", - "FAN_BOUNCE0" - ], - [ - "HCLK_NE6B0", - "NE6C0" - ], - [ - "HCLK_SS6E0", - "SS6D0" - ], - [ - "HCLK_NW6D3", - "NW6E3" - ], - [ - "HCLK_SS2END2", - "SS2A2" - ], - [ - "HCLK_LV6", - "LV_L7" - ], - [ - "HCLK_SW6B2", - "SW6A2" - ], - [ - "HCLK_NW6END_S0_0", - "NW6END0" - ], - [ - "HCLK_LV0", - "LV_L1" - ], - [ - "HCLK_SW6E2", - "SW6D2" - ], - [ - "HCLK_LEAF_CLK_B_TOPL2", - "GCLK_L_B8" - ], - [ - "HCLK_LVB12", - "LVB_L12" - ], - [ - "HCLK_LEAF_CLK_B_TOPL0", - "GCLK_L_B6" - ], - [ - "HCLK_WW4END_S0_0", - "WW4END0" - ], - [ - "HCLK_NE2END_S3_0", - "NE2END0" - ], - [ - "HCLK_SE6B3", - "SE6A3" - ], - [ - "HCLK_NN6E2", - "NN6END2" - ], - [ - "HCLK_SS2END1", - "SS2A1" - ], - [ - "HCLK_NR1BEG1", - "NR1END1" - ], - [ - "HCLK_SS6A1", - "SS6BEG1" - ], - [ - "HCLK_NW6B2", - "NW6C2" - ], - [ - "HCLK_LV1", - "LV_L2" - ], - [ - "HCLK_SW6E3", - "SW6D3" - ], - [ - "HCLK_BYP_BOUNCE3", - "BYP_BOUNCE_N3_3" - ], - [ - "HCLK_NR1BEG3", - "NR1END3" - ], - [ - "HCLK_SS6D1", - "SS6C1" - ], - [ - "HCLK_FAN_BOUNCE_S3_2", - "FAN_BOUNCE2" - ], - [ - "HCLK_NN6A0", - "NN6B0" - ], - [ - "HCLK_SS6A3", - "SS6BEG3" - ], - [ - "HCLK_NN6B2", - "NN6C2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_CLB", - "HCLK_L_BOT_UTURN" - ], - "wire_pairs": [ - [ - "HCLK_CLB_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CLB_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ] - ] - }, - { - "grid_deltas": [ - 0, - 2 - ], - "tile_types": [ - "LIOI3", - "LIOI3_TBYTESRC" - ], - "wire_pairs": [ - [ - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1" - ], - [ - "IOI_IOCLK3", - "IOI_IOCLK3" - ], - [ - "IOI_TBYTEIN", - "IOI_TBYTEIN" - ], - [ - "IOI_IMUX_RC1", - "IOI_IMUX_RC3" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK4" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK1" - ], - [ - "IOI_IOCLK0", - "IOI_IOCLK0" - ], - [ - "IOI_IOCLK1", - "IOI_IOCLK1" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK3" - ], - [ - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK2" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_RCLK_FORIO3" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO2" - ], - [ - "IOI_IOCLK2", - "IOI_IOCLK2" - ], - [ - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR0" - ], - [ - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK0" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO1" - ], - [ - "IOI_IMUX_RC0", - "IOI_IMUX_RC2" - ], - [ - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR1" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_LEAF_GCLK5" - ], - [ - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO0" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH6_0", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_LH7_0", - "VBRK_LH7" - ], - [ - "CLK_HROW_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_LH1_0", - "VBRK_LH1" - ], - [ - "CLK_HROW_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH9_0", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_HROW_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_LH8_0", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_NW4A1_0", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_LH5_0", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH12_0", - "VBRK_LH12" - ], - [ - "CLK_HROW_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_LH11_0", - "VBRK_LH11" - ], - [ - "CLK_HROW_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE4A2_0", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_LH2_0", - "VBRK_LH2" - ], - [ - "CLK_HROW_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_LH10_0", - "VBRK_LH10" - ], - [ - "CLK_HROW_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_NW4END1_0", - "VBRK_NW4END1" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "BRAM_L", - "BRKH_BRAM" - ], - "wire_pairs": [ - [ - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" - ], - [ - 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"VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX40_10", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_BYP3_10", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX37_10", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_FAN6_10", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX33_10", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX30_10", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B9_10", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_LOGIC_OUTS_B6_10", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX16_10", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX45_10", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_LOGIC_OUTS_B1_10", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX28_10", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX39_10", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX15_10", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_FAN2_10", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX2_10", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX11_10", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX5_10", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_FAN5_10", - "VBRK_EXT_FAN5" - ], - [ - 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"VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_IMUX8_1", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX6_1", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_FAN4_1", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX44_1", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_LOGIC_OUTS_B17_1", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_LOGIC_OUTS_B21_1", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_BYP4_1", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX17_1", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX25_1", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX7_1", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_FAN7_1", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX41_1", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX40_1", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_FAN6_1", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX13_1", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX15_1", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX14_1", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX34_1", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX5_1", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX31_1", - "VBRK_EXT_IMUX31" - ], [ "GTPE2_BYP0_1", "VBRK_EXT_BYP0" ], - [ - "GTPE2_IMUX0_1", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX33_1", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX28_1", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_CTRL1_1", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_BYP6_1", - "VBRK_EXT_BYP6" - ], [ "GTPE2_BYP1_1", "VBRK_EXT_BYP1" ], - [ - "GTPE2_LOGIC_OUTS_B11_1", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTPE2_FAN1_1", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_LOGIC_OUTS_B13_1", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX22_1", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX43_1", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX42_1", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_LOGIC_OUTS_B15_1", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_IMUX24_1", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_IMUX19_1", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX37_1", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX32_1", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B8_1", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTPE2_FAN5_1", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_IMUX45_1", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_LOGIC_OUTS_B14_1", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_BYP5_1", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX23_1", - "VBRK_EXT_IMUX23" - ], [ "GTPE2_BYP2_1", "VBRK_EXT_BYP2" ], - [ - "GTPE2_FAN0_1", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX16_1", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX26_1", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_FAN2_1", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_LOGIC_OUTS_B22_1", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_CLK0_1", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX3_1", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX38_1", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX46_1", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX35_1", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX2_1", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_CLK1_1", - "VBRK_EXT_CLK1" - ], [ "GTPE2_BYP3_1", "VBRK_EXT_BYP3" ], [ - "GTPE2_IMUX10_1", - "VBRK_EXT_IMUX10" + "GTPE2_BYP4_1", + "VBRK_EXT_BYP4" ], [ - "GTPE2_IMUX9_1", - "VBRK_EXT_IMUX9" + "GTPE2_BYP5_1", + "VBRK_EXT_BYP5" ], [ - "GTPE2_LOGIC_OUTS_B5_1", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_LOGIC_OUTS_B12_1", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_LOGIC_OUTS_B16_1", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_LOGIC_OUTS_B20_1", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_LOGIC_OUTS_B10_1", - "VBRK_EXT_LOGIC_OUTS_B10" + "GTPE2_BYP6_1", + "VBRK_EXT_BYP6" ], [ "GTPE2_BYP7_1", "VBRK_EXT_BYP7" ], + [ + "GTPE2_CLK0_1", + "VBRK_EXT_CLK0" + ], + [ + "GTPE2_CLK1_1", + "VBRK_EXT_CLK1" + ], + [ + "GTPE2_CTRL0_1", + "VBRK_EXT_CTRL0" + ], + [ + "GTPE2_CTRL1_1", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_FAN0_1", + "VBRK_EXT_FAN0" + ], + [ + "GTPE2_FAN1_1", + "VBRK_EXT_FAN1" + ], + [ + "GTPE2_FAN2_1", + "VBRK_EXT_FAN2" + ], [ "GTPE2_FAN3_1", "VBRK_EXT_FAN3" ], [ - "GTPE2_IMUX36_1", - "VBRK_EXT_IMUX36" + "GTPE2_FAN4_1", + "VBRK_EXT_FAN4" ], [ - "GTPE2_IMUX21_1", - "VBRK_EXT_IMUX21" + "GTPE2_FAN5_1", + "VBRK_EXT_FAN5" ], [ - "GTPE2_IMUX11_1", - "VBRK_EXT_IMUX11" + "GTPE2_FAN6_1", + "VBRK_EXT_FAN6" + ], + [ + "GTPE2_FAN7_1", + "VBRK_EXT_FAN7" + ], + [ + "GTPE2_IMUX0_1", + "VBRK_EXT_IMUX0" ], [ "GTPE2_IMUX1_1", "VBRK_EXT_IMUX1" ], [ - "GTPE2_IMUX47_1", - "VBRK_EXT_IMUX47" + "GTPE2_IMUX2_1", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_1", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_1", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_1", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_1", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_1", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_1", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_1", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX10_1", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX11_1", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_1", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_1", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_1", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_1", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_1", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_1", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_1", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX19_1", + "VBRK_EXT_IMUX19" + ], + [ + "GTPE2_IMUX20_1", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_IMUX21_1", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX22_1", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX23_1", + "VBRK_EXT_IMUX23" + ], + [ + "GTPE2_IMUX24_1", + "VBRK_EXT_IMUX24" + ], + [ + "GTPE2_IMUX25_1", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX26_1", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX27_1", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX28_1", + "VBRK_EXT_IMUX28" ], [ "GTPE2_IMUX29_1", @@ -352158,39112 +345322,532 @@ "VBRK_EXT_IMUX30" ], [ - "GTPE2_IMUX27_1", - "VBRK_EXT_IMUX27" + "GTPE2_IMUX31_1", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_IMUX32_1", + "VBRK_EXT_IMUX32" + ], + [ + "GTPE2_IMUX33_1", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX34_1", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_IMUX35_1", + "VBRK_EXT_IMUX35" + ], + [ + "GTPE2_IMUX36_1", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX37_1", + 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"INT_INTERFACE_EE4B2", - "PCIE_EE4B2_3" - ], - [ - "INT_INTERFACE_WW2A2", - "PCIE_WW2A2_3" - ], - [ - "INT_INTERFACE_NW2A2", - "PCIE_NW2A2_3" - ], - [ - "INT_INTERFACE_EE2BEG0", - "PCIE_EE2BEG0_3" - ], - [ - "INT_INTERFACE_CTRL1", - "PCIE_CTRL1_L_3" - ], - [ - "INT_INTERFACE_LH12", - "PCIE_LH12_3" - ], - [ - "INT_INTERFACE_EL1BEG0", - "PCIE_EL1BEG0_3" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_NW2A1_5", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_LH12_5", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_NW2A3_5", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SE2A2_5", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_NW4END1_5", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_WW4C2_5", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_IMUX44_5", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_EE2BEG3_5", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_SW4END1_5", - "INT_INTERFACE_SW4END1" - ], - [ - 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], - [ - "CLK_HROW_CLK0_5", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_EL1BEG3_5", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_IMUX17_5", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_NE2A0_5", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_IMUX19_5", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_LH7_5", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NW4A2_5", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_IMUX39_5", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_ER1BEG3_5", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_IMUX46_5", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SW4END2_5", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE2A1_5", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_EE4C0_5", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE4A3_5", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_EE2BEG2_5", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_WW2A0_5", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW2A1_5", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX40_5", - 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[ - "CLK_FEED_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLK_FEED_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLK_FEED_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_LH12", - "VBRK_LH12" - ], - [ - "CLK_FEED_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLK_FEED_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLK_FEED_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLK_FEED_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLK_FEED_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_LH7", - "VBRK_LH7" - ], - [ - "CLK_FEED_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLK_FEED_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLK_FEED_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_LH8", - "VBRK_LH8" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLK_FEED_EE4B1", - "VBRK_EE4B1" - ], - [ - "CLK_FEED_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLK_FEED_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLK_FEED_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLK_FEED_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLK_FEED_ER1BEG2", - "VBRK_ER1BEG2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_CK_IN_R6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "CLK_HROW_CK_BUFHCLK_R10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "CLK_HROW_CK_IN_R7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "CLK_HROW_CK_BUFRCLK_R1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "CLK_HROW_CK_IN_R9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "CLK_HROW_CK_IN_R2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "CLK_HROW_CK_BUFHCLK_R11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "CLK_HROW_CK_IN_R3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_R7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "CLK_HROW_CK_BUFHCLK_R3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_R9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "CLK_HROW_CK_IN_R12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "CLK_HROW_CK_BUFRCLK_R0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "CLK_HROW_CK_IN_R4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "CLK_HROW_CK_BUFHCLK_R6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "CLK_HROW_CK_IN_R13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "CLK_HROW_CK_BUFHCLK_R4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "CLK_HROW_CK_BUFHCLK_R5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "CLK_HROW_CK_IN_R10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "CLK_HROW_CK_IN_R11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "CLK_HROW_CK_IN_R5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "CLK_HROW_CK_IN_R1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "CLK_HROW_CK_BUFHCLK_R0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "CLK_HROW_CK_IN_R8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "CLK_HROW_CK_BUFHCLK_R2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "CLK_HROW_CK_BUFHCLK_R1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "CLK_HROW_CK_BUFRCLK_R3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_R8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "CLK_HROW_CK_BUFRCLK_R2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "CLK_HROW_CK_IN_R0", - "HCLK_VBRK_MUX_CLK0" - ] - ] - }, - { - "grid_deltas": [ - 5, - 1 - ], - "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_L" - ], - "wire_pairs": [ - [ - "PCIE_IMUX42_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT42" - ], - [ - "PCIE_EE4C0_9", - "INT_INTERFACE_EE4C0" - ], - [ - "PCIE_LH5_9", - "INT_INTERFACE_LH5" - ], - [ - "PCIE_LH8_9", - "INT_INTERFACE_LH8" - ], - [ - "PCIE_IMUX44_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT44" - ], - [ - "PCIE_IMUX16_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT16" - ], - [ - "PCIE_FAN4_L_9", - "INT_INTERFACE_FAN4" - ], - [ - "PCIE_WR1END3_9", - "INT_INTERFACE_WR1END3" - ], - [ - "PCIE_LOGIC_OUTS_B5_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B5" - ], - [ - "PCIE_WW4END1_9", - "INT_INTERFACE_WW4END1" - ], - [ - "PCIE_LOGIC_OUTS_B21_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B21" - ], - [ - "PCIE_WW4END3_9", - "INT_INTERFACE_WW4END3" - ], - [ - "PCIE_SE2A3_9", - "INT_INTERFACE_SE2A3" - ], - [ - "PCIE_FAN2_L_9", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_IMUX22_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT22" - ], - [ - "PCIE_FAN0_L_9", - "INT_INTERFACE_FAN0" - ], - [ - "PCIE_EE4BEG2_9", - "INT_INTERFACE_EE4BEG2" - ], - [ - "PCIE_LOGIC_OUTS_B9_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B9" - ], - [ - "PCIE_WW4B0_9", - "INT_INTERFACE_WW4B0" - ], - [ - "PCIE_BYP3_L_9", - "INT_INTERFACE_BYP3" - ], - [ - "PCIE_LOGIC_OUTS_B23_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B23" - ], - [ - "PCIE_NE4C2_9", - "INT_INTERFACE_NE4C2" - ], - [ - "PCIE_EL1BEG1_9", - "INT_INTERFACE_EL1BEG1" - ], - [ - "PCIE_IMUX9_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT9" - ], - [ - "PCIE_IMUX46_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT46" - ], - [ - "PCIE_LOGIC_OUTS_B1_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B1" - ], - [ - "PCIE_EE4A1_9", - "INT_INTERFACE_EE4A1" - ], - [ - "PCIE_LOGIC_OUTS_B4_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B4" - ], - [ - "PCIE_IMUX11_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT11" - ], - [ - "PCIE_IMUX39_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT39" - ], - [ - "PCIE_EL1BEG3_9", - "INT_INTERFACE_EL1BEG3" - ], - [ - "PCIE_EE4BEG0_9", - "INT_INTERFACE_EE4BEG0" - ], - [ - "PCIE_IMUX31_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT31" - ], - [ - "PCIE_CTRL0_L_9", - "INT_INTERFACE_CTRL0" - ], - [ - "PCIE_WW2END2_9", - "INT_INTERFACE_WW2END2" - ], - [ - "PCIE_SW4END1_9", - "INT_INTERFACE_SW4END1" - ], - [ - "PCIE_NW2A0_9", - "INT_INTERFACE_NW2A0" - ], - [ - "PCIE_EL1BEG2_9", - "INT_INTERFACE_EL1BEG2" - ], - [ - "PCIE_IMUX21_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT21" - ], - [ - "PCIE_NW4A3_9", - "INT_INTERFACE_NW4A3" - ], - [ - "PCIE_NW2A1_9", - "INT_INTERFACE_NW2A1" - ], - [ - "PCIE_BYP6_L_9", - "INT_INTERFACE_BYP6" - ], - [ - "PCIE_EE4B1_9", - "INT_INTERFACE_EE4B1" - ], - [ - "PCIE_WW4B2_9", - "INT_INTERFACE_WW4B2" - ], - [ - "PCIE_IMUX7_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT7" - ], - [ - "PCIE_NE4C3_9", - "INT_INTERFACE_NE4C3" - ], - [ - "PCIE_SW2A2_9", - "INT_INTERFACE_SW2A2" - ], - [ - "PCIE_NE2A1_9", - "INT_INTERFACE_NE2A1" - ], - [ - "PCIE_IMUX41_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT41" - ], - [ - "PCIE_SW4END0_9", - "INT_INTERFACE_SW4END0" - ], - [ - "PCIE_IMUX24_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT24" - ], - [ - "PCIE_LOGIC_OUTS_B12_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B12" - ], - [ - "PCIE_EE2BEG2_9", - "INT_INTERFACE_EE2BEG2" - ], - [ - "PCIE_WW2END1_9", - "INT_INTERFACE_WW2END1" - ], - [ - "PCIE_SE4BEG0_9", - "INT_INTERFACE_SE4BEG0" - ], - [ - "PCIE_BYP7_L_9", - "INT_INTERFACE_BYP7" - ], - [ - "PCIE_NE4C0_9", - "INT_INTERFACE_NE4C0" - ], - [ - "PCIE_IMUX37_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT37" - ], - [ - "PCIE_LOGIC_OUTS_B2_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B2" - ], - [ - "PCIE_SE2A2_9", - "INT_INTERFACE_SE2A2" - ], - [ - "PCIE_WL1END0_9", - "INT_INTERFACE_WL1END0" - ], - [ - "PCIE_LH10_9", - "INT_INTERFACE_LH10" - ], - [ - "PCIE_EE2BEG0_9", - "INT_INTERFACE_EE2BEG0" - ], - [ - "PCIE_SW4END3_9", - "INT_INTERFACE_SW4END3" - ], - [ - "PCIE_EE2A2_9", - "INT_INTERFACE_EE2A2" - ], - [ - "PCIE_SE4BEG3_9", - "INT_INTERFACE_SE4BEG3" - ], - [ - "PCIE_IMUX30_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT30" - ], - [ - "PCIE_IMUX0_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT0" - ], - [ - "PCIE_IMUX43_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT43" - ], - [ - "PCIE_NW2A2_9", - "INT_INTERFACE_NW2A2" - ], - [ - "PCIE_IMUX12_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT12" - ], - [ - "PCIE_LH7_9", - "INT_INTERFACE_LH7" - ], - [ - "PCIE_EE4A3_9", - "INT_INTERFACE_EE4A3" - ], - [ - "PCIE_IMUX2_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT2" - ], - [ - "PCIE_IMUX1_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT1" - ], - [ - "PCIE_BYP1_L_9", - "INT_INTERFACE_BYP1" - ], - [ - "PCIE_IMUX15_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT15" - ], - [ - "PCIE_NW4END0_9", - "INT_INTERFACE_NW4END0" - ], - [ - "PCIE_WW4A0_9", - "INT_INTERFACE_WW4A0" - ], - [ - "PCIE_EE4B3_9", - "INT_INTERFACE_EE4B3" - ], - [ - "PCIE_IMUX32_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT32" - ], - [ - "PCIE_SE4C1_9", - "INT_INTERFACE_SE4C1" - ], - [ - "PCIE_LOGIC_OUTS_B6_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B6" - ], - [ - "PCIE_LOGIC_OUTS_B14_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B14" - ], - [ - "PCIE_EE2BEG1_9", - "INT_INTERFACE_EE2BEG1" - ], - [ - "PCIE_LOGIC_OUTS_B17_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B17" - ], - [ - "PCIE_IMUX35_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT35" - ], - [ - "PCIE_NW4END1_9", - "INT_INTERFACE_NW4END1" - ], - [ - "PCIE_WW2A0_9", - "INT_INTERFACE_WW2A0" - ], - [ - "PCIE_SE2A1_9", - "INT_INTERFACE_SE2A1" - ], - [ - "PCIE_LOGIC_OUTS_B10_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B10" - ], - [ - "PCIE_IMUX34_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT34" - ], - [ - "PCIE_WR1END0_9", - "INT_INTERFACE_WR1END0" - ], - [ - "PCIE_WW4A1_9", - "INT_INTERFACE_WW4A1" - ], - [ - "PCIE_FAN3_L_9", - "INT_INTERFACE_FAN3" - ], - [ - "PCIE_BYP2_L_9", - "INT_INTERFACE_BYP2" - ], - [ - "PCIE_IMUX26_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT26" - ], - [ - "PCIE_LH6_9", - "INT_INTERFACE_LH6" - ], - [ - "PCIE_WW2END3_9", - "INT_INTERFACE_WW2END3" - ], - [ - "PCIE_SW4A2_9", - "INT_INTERFACE_SW4A2" - ], - [ - "PCIE_LOGIC_OUTS_B11_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "PCIE_IMUX8_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT8" - ], - [ - "PCIE_SW4A3_9", - "INT_INTERFACE_SW4A3" - ], - [ - "PCIE_EE4BEG1_9", - "INT_INTERFACE_EE4BEG1" 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"CLK_BUFG_LOGIC_OUTS_B0_3", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_HROW_NE4C2_3", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_BUFG_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_IMUX26_3", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_FAN0_3", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_BUFG_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_MONITOR_N_3", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "CLK_BUFG_IMUX45_3", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "CLK_BUFG_IMUX17_3", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_BUFG_IMUX24_3", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_BUFG_IMUX9_3", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_FEEDTHRU_2", - "HCLK_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "HCLK_FEEDTHRU_2_CK_IN3", - "HCLK_FEEDTHRU_2_CK_IN3" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK7", - "HCLK_FEEDTHRU_2_CK_BUFHCLK7" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN12", - "HCLK_FEEDTHRU_2_CK_IN12" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFRCLK3", - "HCLK_FEEDTHRU_2_CK_BUFRCLK3" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFRCLK0", - "HCLK_FEEDTHRU_2_CK_BUFRCLK0" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN11", - "HCLK_FEEDTHRU_2_CK_IN11" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN7", - "HCLK_FEEDTHRU_2_CK_IN7" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK1", - "HCLK_FEEDTHRU_2_CK_BUFHCLK1" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN10", - "HCLK_FEEDTHRU_2_CK_IN10" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN8", - "HCLK_FEEDTHRU_2_CK_IN8" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFRCLK1", - "HCLK_FEEDTHRU_2_CK_BUFRCLK1" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN9", - "HCLK_FEEDTHRU_2_CK_IN9" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN5", - "HCLK_FEEDTHRU_2_CK_IN5" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK0", - "HCLK_FEEDTHRU_2_CK_BUFHCLK0" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN0", - "HCLK_FEEDTHRU_2_CK_IN0" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK11", - "HCLK_FEEDTHRU_2_CK_BUFHCLK11" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK3", - "HCLK_FEEDTHRU_2_CK_BUFHCLK3" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN2", - "HCLK_FEEDTHRU_2_CK_IN2" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFRCLK2", - "HCLK_FEEDTHRU_2_CK_BUFRCLK2" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK8", - "HCLK_FEEDTHRU_2_CK_BUFHCLK8" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK4", - "HCLK_FEEDTHRU_2_CK_BUFHCLK4" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK2", - "HCLK_FEEDTHRU_2_CK_BUFHCLK2" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN13", - "HCLK_FEEDTHRU_2_CK_IN13" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN6", - "HCLK_FEEDTHRU_2_CK_IN6" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK5", - "HCLK_FEEDTHRU_2_CK_BUFHCLK5" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN1", - "HCLK_FEEDTHRU_2_CK_IN1" - ], - [ - "HCLK_FEEDTHRU_2_CK_IN4", - "HCLK_FEEDTHRU_2_CK_IN4" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK6", - "HCLK_FEEDTHRU_2_CK_BUFHCLK6" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK10", - "HCLK_FEEDTHRU_2_CK_BUFHCLK10" - ], - [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK9", - "HCLK_FEEDTHRU_2_CK_BUFHCLK9" - ] - ] - }, - { - "grid_deltas": [ - -1, - -3 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_SE4BEG1_6", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NW4END1_6", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_LH4_6", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WW4END1_6", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_CLK0_6", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_NE2A3_6", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_IMUX4_6", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX39_6", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_NW4A0_6", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_LH7_6", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_WR1END1_6", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW2A0_6", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_IMUX44_6", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_NE4BEG3_6", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_SW4END3_6", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WR1END3_6", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_SE4C2_6", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_EE2A3_6", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_NE4C0_6", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_NW2A1_6", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_ER1BEG0_6", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_LH11_6", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_IMUX40_6", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_EE2BEG2_6", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_SW2A1_6", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_IMUX21_6", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_NE2A0_6", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_IMUX0_6", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_SE4C1_6", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_WW2A2_6", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_SW4END1_6", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EE4BEG1_6", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_SW4A0_6", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_IMUX19_6", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_NW4END0_6", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_IMUX36_6", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_WW4A3_6", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_NW2A3_6", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WW4B3_6", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_SW4END2_6", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_NW4END2_6", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_IMUX16_6", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_LH8_6", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_SE4BEG2_6", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_WW2END1_6", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_BYP1_6", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_WW4END0_6", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_EL1BEG2_6", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_LH3_6", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_LH2_6", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EE4A3_6", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_IMUX14_6", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_IMUX17_6", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_WR1END0_6", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_LH12_6", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_SE2A2_6", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_EE2BEG1_6", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_NE4BEG0_6", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_LH9_6", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_SW4END0_6", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_NE4C3_6", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX7_6", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WR1END2_6", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW2A1_6", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_WW2END0_6", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_WW4A1_6", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_FAN6_6", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WL1END0_6", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_IMUX31_6", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_IMUX10_6", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_LH5_6", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NE4BEG1_6", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE4C0_6", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_IMUX45_6", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_BYP4_6", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_EE2A2_6", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_IMUX46_6", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_WL1END3_6", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_EE4B3_6", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_BYP0_6", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_IMUX5_6", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX2_6", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_EE2BEG3_6", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_BYP3_6", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX11_6", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_IMUX23_6", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_IMUX22_6", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_EE4C2_6", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_IMUX8_6", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_IMUX27_6", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_IMUX26_6", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_EE2BEG0_6", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_IMUX18_6", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_NW2A2_6", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_WW4END2_6", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_WW4A2_6", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_LH10_6", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_IMUX20_6", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_WL1END1_6", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_FAN5_6", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_EE4A2_6", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2A1_6", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_EE4BEG3_6", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_SW4A1_6", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_WW4C2_6", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_NE4C1_6", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW4END3_6", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_FAN1_6", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NE4C2_6", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX13_6", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_CLK1_6", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_SE2A0_6", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_SW4A3_6", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX34_6", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_IMUX42_6", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_NW4END3_6", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_FAN2_6", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_IMUX38_6", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX6_6", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_LH6_6", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH1_6", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX15_6", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_CTRL1_6", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW4C0_6", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_MONITOR_N_6", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_BYP5_6", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_WW4C1_6", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_IMUX32_6", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_MONITOR_P_6", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_CTRL0_6", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX3_6", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_EL1BEG0_6", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_IMUX37_6", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_SE2A1_6", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE4A0_6", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_WW4A0_6", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_IMUX12_6", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_NE4BEG2_6", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_IMUX35_6", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_EE4C3_6", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE4B1_6", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SW2A0_6", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_WW2A3_6", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SE2A3_6", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_NW4A2_6", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_EE2A0_6", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EL1BEG1_6", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX43_6", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_IMUX28_6", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_BYP2_6", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_FAN7_6", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_NW4A3_6", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_NW2A0_6", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE4B2_6", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_SE4BEG0_6", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_NW4A1_6", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX41_6", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SE4C0_6", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_FAN0_6", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_EE4BEG0_6", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_NE2A1_6", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_IMUX25_6", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_BYP7_6", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_SE4BEG3_6", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NE2A2_6", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EL1BEG3_6", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_BYP6_6", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_EE4C1_6", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX29_6", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX9_6", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_ER1BEG2_6", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_FAN3_6", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX24_6", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WW4B0_6", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW2END3_6", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE4BEG2_6", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_IMUX33_6", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_ER1BEG3_6", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_SW2A2_6", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_ER1BEG1_6", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_FAN4_6", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_IMUX1_6", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_IMUX30_6", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_WW4B1_6", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE4B0_6", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_SW2A3_6", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SW4A2_6", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW4B2_6", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_SE4C3_6", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE4A1_6", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_WW4C3_6", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WL1END2_6", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_IMUX47_6", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_WW2END2_6", - "INT_INTERFACE_WW2END2" - ] - ] - }, - { - "grid_deltas": [ - 1, - -1 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_LH9_4", - "VBRK_LH9" - ], - [ - "CLK_HROW_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE2A1_4", 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"CLK_HROW_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_LH8_4", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH5_4", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SW2A2_4", - "VBRK_SW2A2" - ], - [ - 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], - [ - "CLK_HROW_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_LH2_4", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_LH3_4", - "VBRK_LH3" - ], - [ - "CLK_HROW_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_WW4A1_4", - "VBRK_WW4A1" - ], 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"CLK_HROW_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_NW2A1_4", - "VBRK_NW2A1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 3 - ], - "tile_types": [ - "CMT_TOP_L_UPPER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "CMT_TOP_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_LH10_2", - "VBRK_LH10" - ], - [ - "CMT_TOP_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_WW2END3_2", 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"CLK_HROW_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_HROW_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_LH6_1", - "VBRK_LH6" - ], - [ - "CLK_HROW_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH1_1", - "VBRK_LH1" - ], - [ - "CLK_HROW_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_HROW_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_HROW_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_HROW_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "BRAM_L", - "CLBLM_R" - ], - "wire_pairs": [ - [ - "BRAM_SW4END1_2", - "CLBLM_SW4END1" - ], - [ - "BRAM_EE2BEG2_2", - "CLBLM_EE2BEG2" - ], - [ - "BRAM_LH7_2", - "CLBLM_LH7" - ], - [ - "BRAM_WW4C3_2", - "CLBLM_WW4C3" - ], - [ - "BRAM_WW2END2_2", - "CLBLM_WW2END2" - ], - [ - "BRAM_NE4C2_2", - "CLBLM_NE4C2" - ], - [ - "BRAM_EE4C2_2", - "CLBLM_EE4C2" - ], - [ - "BRAM_SE4BEG0_2", - "CLBLM_SE4BEG0" - ], - [ - "BRAM_NW2A2_2", - "CLBLM_NW2A2" - ], - [ - "BRAM_NE4BEG1_2", - "CLBLM_NE4BEG1" - ], - [ - "BRAM_SE2A0_2", - "CLBLM_SE2A0" - ], - [ - "BRAM_WW2END3_2", - "CLBLM_WW2END3" - ], - [ - "BRAM_SE4C1_2", - "CLBLM_SE4C1" - ], - [ - "BRAM_SE4BEG3_2", - "CLBLM_SE4BEG3" - ], - [ - "BRAM_EE4C0_2", - "CLBLM_EE4C0" - ], - [ - "BRAM_SW2A1_2", - "CLBLM_SW2A1" - ], - [ - "BRAM_WW2END1_2", - "CLBLM_WW2END1" - ], - [ - "BRAM_SW2A2_2", - "CLBLM_SW2A2" - ], - [ - "BRAM_EE4A1_2", - "CLBLM_EE4A1" - ], - [ - "BRAM_WW4A3_2", - "CLBLM_WW4A3" - ], - [ - "BRAM_WR1END3_2", - "CLBLM_WR1END3" - ], - [ - "BRAM_EL1BEG1_2", - "CLBLM_EL1BEG1" - ], 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"CLBLM_ER1BEG0" - ], - [ - "BRAM_NE4C1_2", - "CLBLM_NE4C1" - ], - [ - "BRAM_NE4BEG3_2", - "CLBLM_NE4BEG3" - ], - [ - "BRAM_NE4BEG0_2", - "CLBLM_NE4BEG0" - ], - [ - "BRAM_WL1END1_2", - "CLBLM_WL1END1" - ], - [ - "BRAM_SE4BEG1_2", - "CLBLM_SE4BEG1" - ], - [ - "BRAM_SE4BEG2_2", - "CLBLM_SE4BEG2" - ], - [ - "BRAM_EE4A3_2", - "CLBLM_EE4A3" - ], - [ - "BRAM_SW2A3_2", - "CLBLM_SW2A3" - ], - [ - "BRAM_SW4END3_2", - "CLBLM_SW4END3" - ], - [ - "BRAM_NE2A3_2", - "CLBLM_NE2A3" - ], - [ - "BRAM_WW4A0_2", - "CLBLM_WW4A0" - ], - [ - "BRAM_LH10_2", - "CLBLM_LH10" - ], - [ - "BRAM_NW4A3_2", - "CLBLM_NW4A3" - ], - [ - "BRAM_LH8_2", - "CLBLM_LH8" - ], - [ - "BRAM_LH5_2", - "CLBLM_LH5" - ], - [ - "BRAM_NW4A0_2", - "CLBLM_NW4A0" - ], - [ - "BRAM_NW2A3_2", - "CLBLM_NW2A3" - ], - [ - "BRAM_SW4END2_2", - "CLBLM_SW4END2" - ], - [ - "BRAM_WW4END3_2", - "CLBLM_WW4END3" - ], - [ - "BRAM_WR1END0_2", - "CLBLM_WR1END0" - ], - [ - "BRAM_SE2A3_2", - "CLBLM_SE2A3" - ], - [ - "BRAM_SW4A0_2", - "CLBLM_SW4A0" - ], - [ - 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[ - "DSP_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "DSP_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "DSP_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "DSP_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "DSP_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "DSP_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "DSP_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "DSP_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "DSP_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "DSP_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "DSP_LH10_1", - "VBRK_LH10" - ], - [ - "DSP_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "DSP_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "DSP_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "DSP_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "DSP_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "DSP_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "DSP_LH3_1", - "VBRK_LH3" - ], - [ - "DSP_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "DSP_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "DSP_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "DSP_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "DSP_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "DSP_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "DSP_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "DSP_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "DSP_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "DSP_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "DSP_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "DSP_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "DSP_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "DSP_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "DSP_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "DSP_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "DSP_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "DSP_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "DSP_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "DSP_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "DSP_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "DSP_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "DSP_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "DSP_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "DSP_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "DSP_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "DSP_LH11_1", - "VBRK_LH11" - ], - [ - "DSP_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "DSP_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "DSP_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "DSP_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "DSP_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "DSP_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "DSP_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "DSP_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "DSP_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "DSP_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "DSP_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "DSP_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "DSP_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "DSP_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "DSP_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "DSP_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "DSP_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "DSP_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "DSP_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "DSP_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "DSP_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "DSP_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "DSP_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "DSP_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "DSP_LH9_1", - "VBRK_LH9" - ], - [ - "DSP_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "DSP_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "DSP_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "DSP_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "DSP_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "DSP_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "DSP_LH1_1", - "VBRK_LH1" - ], - [ - "DSP_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "DSP_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "DSP_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "DSP_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "DSP_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "DSP_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "DSP_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "DSP_LH2_1", - "VBRK_LH2" - ], - [ - "DSP_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "DSP_LH12_1", - "VBRK_LH12" - ], - [ - "DSP_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "DSP_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "DSP_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "DSP_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "DSP_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "DSP_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "DSP_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "DSP_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "DSP_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "DSP_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "DSP_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "DSP_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "DSP_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "DSP_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "DSP_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "DSP_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "DSP_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "DSP_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "DSP_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "DSP_LH8_1", - "VBRK_LH8" - ], - [ - "DSP_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "DSP_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "DSP_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "DSP_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "DSP_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "DSP_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "DSP_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "DSP_LH7_1", - "VBRK_LH7" - ], - [ - "DSP_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "DSP_LH6_1", - "VBRK_LH6" - ], - [ - "DSP_EL1BEG2_1", - "VBRK_EL1BEG2" - ] - ] - }, - { - "grid_deltas": [ - -1, - 3 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_ER1BEG0_1", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_EE4C2_1", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_ER1BEG1_1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_IMUX3_1", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_IMUX10_1", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX39_1", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WW2A3_1", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SW2A0_1", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_BYP4_1", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_NW4END3_1", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "BRKH_INT", - "INT_L" - ], - "wire_pairs": [ - [ - "BRKH_INT_NN6B2", - "NN6B2" - ], - [ - "BRKH_INT_SS6END2", - "SS6END2" - ], - [ - "BRKH_INT_NW2END_S0_0", - "NW2END_S0_0" - ], - [ - "BRKH_INT_SS6E1", - "SS6E1" - ], - [ - "BRKH_INT_WR1END_S1_0", - "WR1END_S1_0" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_2" - ], - [ - "BRKH_INT_SS2END0", - "SS2END0" - ], - [ - "BRKH_INT_NN2A1", - "NN2A1" - ], - [ - "BRKH_INT_LVB_L7", - "LVB_L6" - ], - [ - "BRKH_INT_NN6D0", - "NN6D0" - ], - [ - "BRKH_INT_NN6E2", - "NN6E2" - ], - [ - "BRKH_INT_NW6A0", - "NW6A0" - ], - [ - "BRKH_INT_NW2BEG0", - "NW2BEG0" - ], - [ - "BRKH_INT_NE6C1", - "NE6C1" - ], - [ - "BRKH_INT_NE6B3", - "NE6B3" - ], - [ - "BRKH_INT_SE6D3", - "SE6D3" - ], - [ - "BRKH_INT_BYP_BOUNCE7", - "BYP_BOUNCE7" - ], - [ - "BRKH_INT_SE6C2", - "SE6C2" - ], - [ - "BRKH_INT_SE6C3", - "SE6C3" - ], - [ - "BRKH_INT_WW2END3", - "WW2END3" - ], - [ - "BRKH_INT_SE2A0", - "SE2A0" - ], - [ - "BRKH_INT_NN6C0", - "NN6C0" - ], - [ - "BRKH_INT_BYP_BOUNCE3", - "BYP_BOUNCE3" - ], - [ - "BRKH_INT_NN2BEG3", - "NN2BEG3" - ], - [ - "BRKH_INT_L_LV4", - "LV_L4" - ], - [ - "BRKH_INT_LVB_L3", - "LVB_L2" - ], - [ - "BRKH_INT_SE6D1", - "SE6D1" - ], - [ - "BRKH_INT_BYP_BOUNCE6", - "BYP_BOUNCE6" - ], - [ - "BRKH_INT_L_LV9", - "LV_L9" - ], - [ - "BRKH_INT_L_LV7", - "LV_L7" - ], - [ - "BRKH_INT_SS6B3", - "SS6B3" - ], - [ - "BRKH_INT_L_LV13", - "LV_L13" - ], - [ - "BRKH_INT_L_LV0", - "LV_L0" - ], - [ - "BRKH_INT_SS2END3", - "SS2END3" - ], - [ - "BRKH_INT_SW6C3", - "SW6C3" - ], - [ - "BRKH_INT_NN6A3", - "NN6A3" - ], - [ - "BRKH_INT_NN2BEG1", - "NN2BEG1" - ], - [ - "BRKH_INT_SL1END2", - "SL1END2" - ], - [ - "BRKH_INT_NN2BEG2", - "NN2BEG2" - ], - [ - "BRKH_INT_SW6C1", - "SW6C1" - ], - [ - "BRKH_INT_NN6D1", - "NN6D1" - ], - [ - "BRKH_INT_SR1END1", - "SR1END1" - ], - [ - "BRKH_INT_NE6D2", - "NE6D2" - ], - [ - "BRKH_INT_SS6B0", - "SS6B0" - ], - [ - "BRKH_INT_NE2BEG2", - "NE2BEG2" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_4" - ], - [ - "BRKH_INT_NR1BEG3", - "NR1BEG3" - ], - [ - "BRKH_INT_SE6E3", - "SE6E3" - ], - [ - "BRKH_INT_NN6E3", - "NN6E3" - ], - [ - "BRKH_INT_SW6E0", - "SW6E0" - ], - [ - "BRKH_INT_SR1END2", - "SR1END2" - ], - [ - "BRKH_INT_NN2A0", - "NN2A0" - ], - [ - "BRKH_INT_SS6END1", - "SS6END1" - ], - [ - "BRKH_INT_SW2A2", - "SW2A2" - ], - [ - "BRKH_INT_NE6A0", - "NE6A0" - ], - [ - "BRKH_INT_BYP_BOUNCE2", - "BYP_BOUNCE2" - ], - [ - "BRKH_INT_SS6D1", - "SS6D1" - ], - [ - "BRKH_INT_SS6A3", - "SS6A3" - ], - [ - "BRKH_INT_NN6B1", - "NN6B1" - ], - [ - "BRKH_INT_NN6BEG2", - "NN6BEG2" - ], - [ - "BRKH_INT_SW6E3", - "SW6E3" - ], - [ - "BRKH_INT_LVB_L8", - "LVB_L7" - ], - [ - "BRKH_INT_SS6C0", - "SS6C0" - ], - [ - "BRKH_INT_WW4END_S0_0", - "WW4END_S0_0" - ], - [ - "BRKH_INT_SE6D0", - "SE6D0" - ], - [ - "BRKH_INT_EL1END_S3_0", - "EL1END_S3_0" - ], - [ - "BRKH_INT_NW6C1", - "NW6C1" - ], - [ - "BRKH_INT_NN6A2", - "NN6A2" - ], - [ - "BRKH_INT_SE6E2", - "SE6E2" - ], - [ - "BRKH_INT_NN6B0", - "NN6B0" - ], - [ - "BRKH_INT_NE2BEG3", - "NE2BEG3" - ], - [ - "BRKH_INT_NL1BEG0", - "NL1BEG0" - ], - [ - "BRKH_INT_NN6BEG0", - "NN6BEG0" - ], - [ - "BRKH_INT_L_LV6", - "LV_L6" - ], - [ - "BRKH_INT_SE6B0", - "SE6B0" - ], - [ - "BRKH_INT_SS2A3", - "SS2A3" - ], - [ - "BRKH_INT_NW6B2", - "NW6B2" - ], - [ - "BRKH_INT_NE2BEG1", - "NE2BEG1" - ], - [ - "BRKH_INT_WL1END3", - "WL1END3" - ], - [ - "BRKH_INT_SW6D0", - "SW6D0" - ], - [ - "BRKH_INT_NN6C2", - "NN6C2" - ], - [ - "BRKH_INT_SS2END_N0_3", - "SS2END3" - ], - [ - "BRKH_INT_LVB_L1", - "LVB_L0" - ], - [ - "BRKH_INT_NE6B0", - "NE6B0" - ], - [ - "BRKH_INT_WR1BEG_S0", - "WR1BEG_S0" - ], - [ - "BRKH_INT_SW6B0", - "SW6B0" - ], - [ - "BRKH_INT_NE6C3", - "NE6C3" - ], - [ - "BRKH_INT_SE6B2", - "SE6B2" - ], - [ - "BRKH_INT_SE2A2", - "SE2A2" - ], - [ - "BRKH_INT_NW6A1", - "NW6A1" - ], - [ - "BRKH_INT_NN6D3", - "NN6D3" - ], - [ - "BRKH_INT_SW6B1", - "SW6B1" - ], - [ - "BRKH_INT_NR1BEG0", - "NR1BEG0" - ], - [ - "BRKH_INT_NL1END_S3_0", - "NL1END_S3_0" - ], - [ - "BRKH_INT_SR1END3", - "SR1END3" - ], - [ - "BRKH_INT_NW6C0", - "NW6C0" - ], - [ - "BRKH_INT_NW6D1", - "NW6D1" - ], - [ - "BRKH_INT_EL1BEG3", - "EL1BEG3" - ], - [ - "BRKH_INT_NW6B0", - "NW6B0" - ], - [ - "BRKH_INT_SS6B1", - "SS6B1" - ], - [ - "BRKH_INT_SW6D1", - "SW6D1" - ], - [ - "BRKH_INT_NN6C3", - "NN6C3" - ], - [ - "BRKH_INT_SE6B1", - "SE6B1" - ], - [ - "BRKH_INT_SS2END2", - "SS2END2" - ], - [ - "BRKH_INT_NN2A2", - "NN2A2" - ], - [ - "BRKH_INT_NN6E0", - "NN6E0" - ], - [ - "BRKH_INT_SE6C0", - "SE6C0" - ], - [ - "BRKH_INT_NL1BEG2", - "NL1BEG2" - ], - [ - "BRKH_INT_NW6C2", - "NW6C2" - ], - [ - "BRKH_INT_SE2A3", - "SE2A3" - ], - [ - "BRKH_INT_LVB_L6", - "LVB_L5" - ], - [ - "BRKH_INT_SW6E2", - "SW6E2" - ], - [ - "BRKH_INT_NN6END_S1_0", - "NN6END_S1_0" - ], - [ - "BRKH_INT_SS6END3", - "SS6END3" - ], - [ - "BRKH_INT_LVB_L4", - "LVB_L3" - ], - [ - "BRKH_INT_NE6A3", - "NE6A3" - ], - [ - "BRKH_INT_SE6E0", - "SE6E0" - ], - [ - "BRKH_INT_L_LV12", - "LV_L12" - ], - [ - "BRKH_INT_NE2BEG0", - "NE2BEG0" - ], - [ - "BRKH_INT_NE6B1", - "NE6B1" - ], - [ - "BRKH_INT_NN6E1", - "NN6E1" - ], - [ - "BRKH_INT_L_LV16", - "LV_L16" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_0" - ], - [ - "BRKH_INT_L_LV17", - "LV_L17" - ], - [ - "BRKH_INT_NW6B1", - "NW6B1" - ], - [ - "BRKH_INT_NW6C3", - "NW6C3" - ], - [ - "BRKH_INT_SW2A3", - "SW2A3" - ], - [ - "BRKH_INT_SS6E3", - "SS6E3" - ], - [ - "BRKH_INT_SS6A2", - "SS6A2" - ], - [ - "BRKH_INT_NW6A3", - "NW6A3" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_6", - "FAN_BOUNCE_S3_6" - ], - [ - "BRKH_INT_SW6E1", - "SW6E1" - ], - [ - "BRKH_INT_SW6D3", - "SW6D3" - ], - [ - "BRKH_INT_SS2A0", - "SS2A0" - ], - [ - "BRKH_INT_NE6D3", - "NE6D3" - ], - [ - "BRKH_INT_NE6A2", - "NE6A2" - ], - [ - "BRKH_INT_NE6D0", - "NE6D0" - ], - [ - "BRKH_INT_NW6END_S0_0", - "NW6END_S0_0" - ], - [ - "BRKH_INT_SW2END3", - "SW2END3" - ], - [ - "BRKH_INT_NL1BEG1", - "NL1BEG1" - ], - [ - "BRKH_INT_NN2END_S2_0", - "NN2END_S2_0" - ], - [ - "BRKH_INT_LVB_L11", - "LVB_L10" - ], - [ - "BRKH_INT_NN6C1", - "NN6C1" - ], - [ - "BRKH_INT_SS6D2", - "SS6D2" - ], - [ - "BRKH_INT_LVB_L5", - "LVB_L4" - ], - [ - "BRKH_INT_NW2BEG3", - "NW2BEG3" - ], - [ - "BRKH_INT_SW2A0", - "SW2A0" - ], - [ - "BRKH_INT_SE6B3", - "SE6B3" - ], - [ - "BRKH_INT_SS6E2", - "SS6E2" - ], - [ - "BRKH_INT_NE6C0", - "NE6C0" - ], - [ - "BRKH_INT_SS2A1", - "SS2A1" - ], - [ - "BRKH_INT_SW6B3", - "SW6B3" - ], - [ - "BRKH_INT_NE6B2", - "NE6B2" - ], - [ - "BRKH_INT_SS6E0", - "SS6E0" - ], - [ - "BRKH_INT_NN6BEG3", - "NN6BEG3" - ], - [ - "BRKH_INT_NN2A3", - "NN2A3" - ], - [ - "BRKH_INT_NW6A2", - "NW6A2" - ], - [ - "BRKH_INT_SE6E1", - "SE6E1" - ], - [ - "BRKH_INT_NW6D3", - "NW6D3" - ], - [ - "BRKH_INT_NN2BEG0", - "NN2BEG0" - ], - [ - "BRKH_INT_WL1BEG3", - "WL1BEG3" - ], - [ - "BRKH_INT_SW2A1", - "SW2A1" - ], - [ - "BRKH_INT_NW6D2", - "NW6D2" - ], - [ - "BRKH_INT_SL1END3", - "SL1END3" - ], - [ - "BRKH_INT_NN6B3", - "NN6B3" - ], - [ - "BRKH_INT_SR1END_N3_3", - "SR1END3" - ], - [ - "BRKH_INT_ER1END3", - "ER1END3" - ], - [ - "BRKH_INT_SS6C3", - "SS6C3" - ], - [ - "BRKH_INT_SE6D2", - "SE6D2" - ], - [ - "BRKH_INT_SE6C1", - "SE6C1" - ], - [ - "BRKH_INT_ER1BEG_S0", - "ER1BEG_S0" - ], - [ - "BRKH_INT_SW6END3", - "SW6END3" - ], - [ - "BRKH_INT_SW6B2", - "SW6B2" - ], - [ - "BRKH_INT_SS6END0", - "SS6END0" - ], - [ - "BRKH_INT_NW6B3", - "NW6B3" - ], - [ - "BRKH_INT_NR1BEG1", - "NR1BEG1" - ], - [ - "BRKH_INT_NN6BEG1", - "NN6BEG1" - ], - [ - "BRKH_INT_LVB_L10", - "LVB_L9" - ], - [ - "BRKH_INT_SS6D0", - "SS6D0" - ], - [ - "BRKH_INT_SS6B2", - "SS6B2" - ], - [ - "BRKH_INT_NW2BEG1", - "NW2BEG1" - ], - [ - "BRKH_INT_SS6C2", - "SS6C2" - ], - [ - "BRKH_INT_NN6A0", - "NN6A0" - ], - [ - "BRKH_INT_LVB_L9", - "LVB_L8" - ], - [ - "BRKH_INT_SW6D2", - "SW6D2" - ], - [ - "BRKH_INT_NR1BEG2", - "NR1BEG2" - ], - [ - "BRKH_INT_SW6C2", - "SW6C2" - ], - [ - "BRKH_INT_L_LV14", - "LV_L14" - ], - [ - "BRKH_INT_SE2A1", - "SE2A1" - ], - [ - "BRKH_INT_LVB_L12", - "LVB_L11" - ], - [ - "BRKH_INT_NE6D1", - "NE6D1" - ], - [ - "BRKH_INT_L_LV2", - "LV_L2" - ], - [ - "BRKH_INT_L_LV10", - "LV_L10" - ], - [ - "BRKH_INT_SS6C1", - "SS6C1" - ], - [ - "BRKH_INT_SS6D3", - "SS6D3" - ], - [ - "BRKH_INT_SL1END1", - "SL1END1" - ], - [ - "BRKH_INT_L_LV15", - "LV_L15" - ], - [ - "BRKH_INT_L_LV1", - "LV_L1" - ], - [ - "BRKH_INT_SS6END_N0_3", - "SS6END3" - ], - [ - "BRKH_INT_SL1END0", - "SL1END0" - ], - [ - "BRKH_INT_SW6C0", - "SW6C0" - ], - [ - "BRKH_INT_L_LV11", - "LV_L11" - ], - [ - "BRKH_INT_NW2BEG2", - "NW2BEG2" - ], - [ - "BRKH_INT_NE2END_S3_0", - "NE2END_S3_0" - ], - [ - "BRKH_INT_SS2A2", - "SS2A2" - ], - [ - "BRKH_INT_NE6A1", - "NE6A1" - ], - [ - "BRKH_INT_L_LV3", - "LV_L3" - ], - [ - "BRKH_INT_NE6C2", - "NE6C2" - ], - [ - "BRKH_INT_SS2END1", - "SS2END1" - ], - [ - "BRKH_INT_LVB_L2", - "LVB_L1" - ], - [ - "BRKH_INT_L_LV8", - "LV_L8" - ], - [ - "BRKH_INT_NN6D2", - "NN6D2" - ], - [ - "BRKH_INT_SS6A0", - "SS6A0" - ], - [ - "BRKH_INT_NW6D0", - "NW6D0" - ], - [ - "BRKH_INT_L_LV5", - "LV_L5" - ], - [ - "BRKH_INT_SS6A1", - "SS6A1" - ], - [ - "BRKH_INT_NN6A1", - "NN6A1" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "LIOB33_SING", - "LIOI3_SING" - ], - "wire_pairs": [ - [ - "IOB_PD_INT_EN_1", - "LIOI_PD_INT_EN_1" - ], - [ - "IOB_IBUF0", - "LIOI_IBUF0" - ], - [ - "LIOB_IN_TERM0", - "LIOI_DCI_T_TERM0" - ], - [ - "IOB_KEEPER_INT_EN_1", - "LIOI_KEEPER_INT_EN_1" - ], - [ - "IOB_IBUF_DISABLE0", - "LIOI_IBUF_DISABLE0" - ], - [ - "IOB_PU_INT_EN_1", - "LIOI_PU_INT_EN_1" - ], - [ - "IOB_O0", - "LIOI_O0" - ], - [ - "IOB_T0", - "LIOI_T0" - ] - ] - }, - { - "grid_deltas": [ - 1, - -1 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_LH9_4", - "VBRK_LH9" - ], - [ - "CLK_HROW_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_LH4_4", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_LH8_4", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH5_4", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_LH11_4", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_EE4C0_4", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_LH1_4", - "VBRK_LH1" - ], - [ - "CLK_HROW_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_LH7_4", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_LH6_4", - "VBRK_LH6" - ], - [ - "CLK_HROW_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_LH2_4", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_LH3_4", - "VBRK_LH3" - ], - [ - "CLK_HROW_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_LH12_4", - "VBRK_LH12" - ], - [ - "CLK_HROW_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_SE2A1_4", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_LH10_4", - "VBRK_LH10" - ], - [ - "CLK_HROW_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_NW2A1_4", - "VBRK_NW2A1" - ] - ] - }, - { - "grid_deltas": [ - 1, - 3 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_HROW_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_LH6_1", - "VBRK_LH6" - ], - [ - "CLK_HROW_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH1_1", - "VBRK_LH1" - ], - [ - "CLK_HROW_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_HROW_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_HROW_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_HROW_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_CMT_L", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "HCLK_CMT_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_CMT_CK_IN9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_CMT_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_CMT_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_CMT_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_CMT_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_CMT_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_CMT_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK2", - "HCLK_VBRK_PHSR_PERFCLK2" - ], - [ - "HCLK_CMT_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_CMT_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_CMT_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_CMT_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_CMT_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_CMT_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_CMT_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_CMT_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_CMT_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_CMT_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK1", - "HCLK_VBRK_PHSR_PERFCLK1" - ], - [ - "HCLK_CMT_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_CMT_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK0", - "HCLK_VBRK_PHSR_PERFCLK0" - ], - [ - "HCLK_CMT_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_CMT_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_CMT_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_CMT_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_CMT_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_CMT_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_CMT_CK_IN0", - "HCLK_VBRK_MUX_CLK0" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK3", - "HCLK_VBRK_PHSR_PERFCLK3" - ], - [ - "HCLK_CMT_CK_IN3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_CMT_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_CMT_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_MTBF2", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_FEED_EE2BEG1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_FEED_NW4END3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_PMV_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_FEED_WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_LOGIC_OUTS9_0", - "INT_INTERFACE_LOGIC_OUTS_B9" - ], - [ - "CLK_FEED_EE4BEG1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_FEED_NE2A3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_PMV_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_NE2A2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_FEED_WW4B2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_FEED_NW4A2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_PMV_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_LOGIC_OUTS2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_FEED_WR1END0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_FEED_NE4C3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_FEED_EE4A2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_FEED_EL1BEG1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_FEED_NE4C0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_PMV_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_FEED_WL1END2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_FEED_NW2A2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_PMV_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_FEED_NW4END1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_FEED_LH7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_FEED_SW4A3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_PMV_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_PMV_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_FEED_WW4END3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_FEED_WR1END1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_PMV_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_FEED_SE4C0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_FEED_EE4B3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_FEED_MONITOR_P", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_FEED_SW4A1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_FEED_LH9", - "INT_INTERFACE_LH9" - ], - [ - "CLK_PMV_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_FEED_NW2A1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_FEED_EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_FEED_SW4END1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_FEED_NE4C1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_FEED_SW2A1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_FEED_SW4END3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_FEED_SE4C1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_FEED_LH3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_PMV_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_FEED_WR1END2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_FEED_SE4BEG3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_FEED_LH1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_PMV_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_PMV_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_FEED_NW4A1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_FEED_LH6", - "INT_INTERFACE_LH6" - ], - [ - "CLK_PMV_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_FEED_ER1BEG1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_FEED_WW4B3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_LOGIC_OUTS5_0", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_PMV_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_FEED_NE2A0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_FEED_WW4A1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_PMV_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_FEED_LH12", - "INT_INTERFACE_LH12" - ], - [ - "CLK_FEED_WW4A0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_FEED_SW4END0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_LOGIC_OUTS10_0", - "INT_INTERFACE_LOGIC_OUTS_B10" - ], - [ - "CLK_PMV_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_FEED_EE4A1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_PMV_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_PMV_LOGIC_OUTS16_0", - "INT_INTERFACE_LOGIC_OUTS_B16" - ], - [ - "CLK_PMV_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_FEED_EL1BEG0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_FEED_EE4B1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_FEED_SE4BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_PMV_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_FEED_WW4B1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_FEED_EE2BEG0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_FEED_WW4C2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_FEED_ER1BEG2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_FEED_LH2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_FEED_SE4BEG1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_PMV_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_PMV_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_FEED_EE4A3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_FEED_EL1BEG3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_FEED_LH4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_FEED_LH5", - "INT_INTERFACE_LH5" - ], - [ - "CLK_FEED_SE2A3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_PMV_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_FEED_WW4A3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_FEED_LH11", - "INT_INTERFACE_LH11" - ], - [ - "CLK_FEED_SE2A0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_FEED_NW4A3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_FEED_WW4END1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_FEED_MONITOR_N", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_FEED_EL1BEG2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_FEED_WL1END1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_FEED_SW4A0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_FEED_WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_FEED_SW4END2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_PMV_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_FEED_WW2END2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_FEED_WL1END3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_FEED_WR1END3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_FEED_SE4C3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_FEED_LH8", - "INT_INTERFACE_LH8" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_SE2A1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_FEED_EE4B2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_FEED_NW4END0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_FEED_EE4B0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_FEED_EE2BEG3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_FEED_SW2A0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_FEED_WW4C1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_FEED_WW4B0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_PMV_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_FEED_SE4C2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_FEED_SW2A2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_FEED_EE2A1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_FEED_ER1BEG0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_FEED_WW4A2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_FEED_EE4A0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_PMV_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_LOGIC_OUTS19_0", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_FEED_NE4C2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_FEED_NW4END2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_FEED_EE2A0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_FEED_NE4BEG1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_FEED_WW2A3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_FEED_SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_FEED_WW4END0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_FEED_WW2A2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_FEED_EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_FEED_NE4BEG2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_PMV_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_FEED_WW4C0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_FEED_SE4BEG2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_FEED_NW2A3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_FEED_EE2BEG2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_FEED_WW2END1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_FEED_NE4BEG3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_FEED_WW2A1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_FEED_EE4BEG3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_FEED_NE4BEG0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_PMV_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_FEED_EE4BEG0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_FEED_WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_PMV_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_LOGIC_OUTS14_0", - "INT_INTERFACE_LOGIC_OUTS_B14" - ], - [ - "CLK_PMV_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_FEED_SE2A2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_FEED_EE4BEG2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_PMV_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_FEED_SW4A2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_FEED_NW4A0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_FEED_NW2A0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_FEED_LH10", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_PMV_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_FEED_EE4C0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_LOGIC_OUTS6_0", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_FEED_EE2A3", - "INT_INTERFACE_EE2A3" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "BRKH_CLB", - "CLBLM_R" - ], - "wire_pairs": [ - [ - "BRKH_CLB_COUT1_R", - "CLBLM_M_CIN" - ], - [ - "BRKH_CLB_COUT0_R", - "CLBLM_L_CIN" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "GTP_CHANNEL_3", + "GTP_CHANNEL_0", "VBRK_EXT" ], "wire_pairs": [ [ - "GTPE2_LOGIC_OUTS_B12_5", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_CTRL0_5", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_IMUX35_5", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX27_5", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_FAN5_5", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_LOGIC_OUTS_B1_5", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_LOGIC_OUTS_B7_5", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX13_5", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_FAN0_5", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX31_5", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_CLK1_5", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX9_5", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX36_5", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_LOGIC_OUTS_B15_5", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_LOGIC_OUTS_B21_5", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_IMUX45_5", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX46_5", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX22_5", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX5_5", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX38_5", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX30_5", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_BYP4_5", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX24_5", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_LOGIC_OUTS_B0_5", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_IMUX29_5", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX3_5", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX25_5", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX10_5", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_LOGIC_OUTS_B3_5", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_FAN3_5", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_CLK0_5", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_FAN2_5", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX4_5", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_FAN7_5", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX12_5", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX11_5", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_LOGIC_OUTS_B23_5", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_IMUX40_5", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_BYP3_5", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX16_5", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_FAN6_5", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX20_5", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX7_5", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX26_5", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX21_5", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_LOGIC_OUTS_B10_5", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_LOGIC_OUTS_B4_5", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_BYP0_5", + "GTPE2_BYP0_0", "VBRK_EXT_BYP0" ], [ - "GTPE2_BYP5_5", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX18_5", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX41_5", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_FAN1_5", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_BYP2_5", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX8_5", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX39_5", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX28_5", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX2_5", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_LOGIC_OUTS_B17_5", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_LOGIC_OUTS_B22_5", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX14_5", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX17_5", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX43_5", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX37_5", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX44_5", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX32_5", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B13_5", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX33_5", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_BYP1_5", + "GTPE2_BYP1_0", "VBRK_EXT_BYP1" ], [ - "GTPE2_LOGIC_OUTS_B2_5", - "VBRK_EXT_LOGIC_OUTS_B2" + "GTPE2_BYP2_0", + "VBRK_EXT_BYP2" ], [ - "GTPE2_FAN4_5", - "VBRK_EXT_FAN4" + "GTPE2_BYP3_0", + "VBRK_EXT_BYP3" ], [ - "GTPE2_IMUX23_5", - "VBRK_EXT_IMUX23" + "GTPE2_BYP4_0", + "VBRK_EXT_BYP4" ], [ - "GTPE2_IMUX19_5", - "VBRK_EXT_IMUX19" + "GTPE2_BYP5_0", + "VBRK_EXT_BYP5" ], [ - "GTPE2_IMUX42_5", - "VBRK_EXT_IMUX42" + "GTPE2_BYP6_0", + "VBRK_EXT_BYP6" ], [ - "GTPE2_IMUX0_5", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B5_5", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_BYP7_5", + "GTPE2_BYP7_0", "VBRK_EXT_BYP7" ], [ - "GTPE2_IMUX1_5", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_BYP6_5", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX15_5", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX34_5", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_LOGIC_OUTS_B14_5", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_LOGIC_OUTS_B9_5", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_LOGIC_OUTS_B6_5", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX6_5", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_CTRL1_5", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX47_5", - "VBRK_EXT_IMUX47" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "GTP_COMMON", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTPE2_FAN3_3", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX46_3", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX2_3", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_BYP4_3", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX35_3", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX15_3", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_CLK0_3", + "GTPE2_CLK0_0", "VBRK_EXT_CLK0" ], [ - "GTPE2_IMUX30_3", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B23_3", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_IMUX4_3", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_CTRL1_3", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX42_3", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX5_3", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX44_3", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX17_3", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX20_3", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX41_3", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX40_3", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX25_3", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX26_3", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_BYP2_3", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX38_3", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_LOGIC_OUTS_B13_3", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_LOGIC_OUTS_B10_3", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_BYP5_3", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX11_3", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX37_3", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX27_3", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX7_3", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX9_3", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX39_3", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_LOGIC_OUTS_B9_3", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_FAN7_3", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_FAN0_3", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_BYP3_3", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX0_3", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX47_3", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX22_3", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX28_3", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_BYP0_3", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX32_3", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX23_3", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_BYP6_3", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX21_3", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_BYP1_3", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_LOGIC_OUTS_B16_3", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_LOGIC_OUTS_B17_3", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_FAN1_3", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX33_3", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_CLK1_3", + "GTPE2_CLK1_0", "VBRK_EXT_CLK1" ], [ - "GTPE2_IMUX16_3", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX14_3", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX6_3", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX1_3", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_IMUX31_3", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_LOGIC_OUTS_B20_3", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_FAN4_3", - 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"MONITOR_CLK0_8", - "VFRAME_CLK0" - ], - [ - "MONITOR_IMUX42_8", - "VFRAME_IMUX42" - ], - [ - "MONITOR_IMUX45_8", - "VFRAME_IMUX45" - ], - [ - "MONITOR_IMUX47_8", - "VFRAME_IMUX47" - ], - [ - "MONITOR_IMUX14_8", - "VFRAME_IMUX14" - ], - [ - "MONITOR_EE2BEG0_8", - "VFRAME_EE2BEG0" - ], - [ - "MONITOR_IMUX8_8", - "VFRAME_IMUX8" - ], - [ - "MONITOR_WW2A2_8", - "VFRAME_WW2A2" - ], - [ - "MONITOR_EE4A0_8", - "VFRAME_EE4A0" - ], - [ - "MONITOR_LH9_8", - "VFRAME_LH9" - ], - [ - "MONITOR_WR1END2_8", - "VFRAME_WR1END2" - ], - [ - "MONITOR_IMUX5_8", - "VFRAME_IMUX5" - ], - [ - "MONITOR_LH3_8", - "VFRAME_LH3" - ], - [ - "MONITOR_EE4B1_8", - "VFRAME_EE4B1" - ], - [ - "MONITOR_IMUX40_8", - "VFRAME_IMUX40" - ], - [ - "MONITOR_WW2END2_8", - "VFRAME_WW2END2" - ], - [ - "MONITOR_BYP6_8", - "VFRAME_BYP6" - ], - [ - "MONITOR_WW2END3_8", - "VFRAME_WW2END3" - ], - [ - "MONITOR_IMUX0_8", - "VFRAME_IMUX0" - ], - [ - "MONITOR_NE4BEG1_8", - "VFRAME_NE4BEG1" - ], - [ - "MONITOR_BYP7_8", - "VFRAME_BYP7" - ], - [ - "MONITOR_SE4C2_8", - "VFRAME_SE4C2" - ], - [ - "MONITOR_EL1BEG3_8", - "VFRAME_EL1BEG3" - ], - [ - "MONITOR_ER1BEG3_8", - "VFRAME_ER1BEG3" - ], - [ - "MONITOR_FAN3_8", - "VFRAME_FAN3" - ], - [ - "MONITOR_WW4END1_8", - "VFRAME_WW4END1" - ], - [ - "MONITOR_WW4END2_8", - "VFRAME_WW4END2" - ], - [ - "MONITOR_FAN5_8", - "VFRAME_FAN5" - ], - [ - "MONITOR_EE4B2_8", - "VFRAME_EE4B2" - ], - [ - "MONITOR_WL1END1_8", - "VFRAME_WL1END1" - ], - [ - "MONITOR_LH8_8", - "VFRAME_LH8" - ], - [ - "MONITOR_SW4A0_8", - "VFRAME_SW4A0" - ], - [ - "MONITOR_IMUX30_8", - "VFRAME_IMUX30" - ], - [ - "MONITOR_WL1END2_8", - "VFRAME_WL1END2" - ], - [ - "MONITOR_IMUX7_8", - "VFRAME_IMUX7" - ], - [ - "MONITOR_NE4BEG0_8", - "VFRAME_NE4BEG0" - ], - [ - "MONITOR_HORIZ_VAUXP14", - "VFRAME_MONITOR_P" - ], - [ - "MONITOR_IMUX37_8", - "VFRAME_IMUX37" - ], - [ - "MONITOR_IMUX36_8", - "VFRAME_IMUX36" - ], - [ - "MONITOR_IMUX1_8", - "VFRAME_IMUX1" - ], - [ - "MONITOR_IMUX18_8", - "VFRAME_IMUX18" - ], - [ - "MONITOR_IMUX4_8", - "VFRAME_IMUX4" - ], - [ - "MONITOR_ER1BEG1_8", - "VFRAME_ER1BEG1" - ], - [ - "MONITOR_IMUX17_8", - "VFRAME_IMUX17" - ], - [ - "MONITOR_WR1END0_8", - "VFRAME_WR1END0" - ], - [ - "MONITOR_SE2A3_8", - "VFRAME_SE2A3" - ], - [ - "MONITOR_LH2_8", - "VFRAME_LH2" - ], - [ - "MONITOR_IMUX6_8", - "VFRAME_IMUX6" - ], - [ - "MONITOR_WR1END1_8", - "VFRAME_WR1END1" - ], - [ - "MONITOR_IMUX13_8", - "VFRAME_IMUX13" - ], - [ - "MONITOR_NE2A1_8", - "VFRAME_NE2A1" - ], - [ - "MONITOR_NE2A0_8", - "VFRAME_NE2A0" - ], - [ - "MONITOR_IMUX16_8", - "VFRAME_IMUX16" - ], - [ - "MONITOR_EE2A3_8", - "VFRAME_EE2A3" - ], - [ - "MONITOR_SW4END1_8", - "VFRAME_SW4END1" - ], - [ - "MONITOR_IMUX43_8", - "VFRAME_IMUX43" - ], - [ - "MONITOR_WW4B1_8", - "VFRAME_WW4B1" - ], - [ - "MONITOR_WW2END1_8", - "VFRAME_WW2END1" - ], - [ - "MONITOR_IMUX31_8", - "VFRAME_IMUX31" - ], - [ - "MONITOR_FAN1_8", - "VFRAME_FAN1" - ], - [ - "MONITOR_NE4C2_8", - "VFRAME_NE4C2" - ], - [ - "MONITOR_EL1BEG0_8", - "VFRAME_EL1BEG0" - ], - [ - "MONITOR_LH7_8", - "VFRAME_LH7" - ], - [ - "MONITOR_SE4C1_8", - "VFRAME_SE4C1" - ], - [ - "MONITOR_NW2A2_8", - "VFRAME_NW2A2" - ], - [ - "MONITOR_FAN7_8", - "VFRAME_FAN7" - ], - [ - "MONITOR_SW4END2_8", - "VFRAME_SW4END2" - ], - [ - "MONITOR_IMUX2_8", - "VFRAME_IMUX2" - ], - [ - "MONITOR_ER1BEG0_8", - "VFRAME_ER1BEG0" - ], - [ - "MONITOR_IMUX24_8", - "VFRAME_IMUX24" - ], - [ - "MONITOR_IMUX21_8", - "VFRAME_IMUX21" - ], - [ - "MONITOR_NW4END0_8", - "VFRAME_NW4END0" - ], - [ - "MONITOR_NW2A1_8", - "VFRAME_NW2A1" - ], - [ - "MONITOR_SE2A2_8", - "VFRAME_SE2A2" - ], - [ - "MONITOR_SW4A2_8", - "VFRAME_SW4A2" - ], - [ - "MONITOR_WW4B3_8", - "VFRAME_WW4B3" - ], - [ - "MONITOR_WW4B2_8", - "VFRAME_WW4B2" - ], - [ - "MONITOR_SW2A2_8", - "VFRAME_SW2A2" - ], - [ - "MONITOR_IMUX41_8", - "VFRAME_IMUX41" - ], - [ - "MONITOR_LH4_8", - "VFRAME_LH4" - ], - [ - "MONITOR_IMUX22_8", - "VFRAME_IMUX22" - ], - [ - "MONITOR_CTRL0_8", - "VFRAME_CTRL0" - ], - [ - "MONITOR_EE4C1_8", - "VFRAME_EE4C1" - ], - [ - "MONITOR_EE2A1_8", - "VFRAME_EE2A1" - ], - [ - "MONITOR_FAN4_8", - "VFRAME_FAN4" - ], - [ - "MONITOR_EE4BEG1_8", - "VFRAME_EE4BEG1" - ], - [ - "MONITOR_SE2A1_8", - "VFRAME_SE2A1" - ], - [ - "MONITOR_EL1BEG2_8", - "VFRAME_EL1BEG2" - ], - [ - "MONITOR_EE2A0_8", - "VFRAME_EE2A0" - ], - [ - "MONITOR_IMUX25_8", - "VFRAME_IMUX25" - ], - [ - "MONITOR_IMUX35_8", - "VFRAME_IMUX35" - ], - [ - "MONITOR_SW2A0_8", - "VFRAME_SW2A0" - ], - [ - "MONITOR_EE4B0_8", - "VFRAME_EE4B0" - ], - [ - "MONITOR_EE4BEG0_8", - "VFRAME_EE4BEG0" - ], - [ - "MONITOR_SW4END0_8", - "VFRAME_SW4END0" - ], - [ - "MONITOR_SW4END3_8", - "VFRAME_SW4END3" - ], - [ - "MONITOR_EE2BEG3_8", - "VFRAME_EE2BEG3" - ], - [ - "MONITOR_WR1END3_8", - "VFRAME_WR1END3" - ], - [ - "MONITOR_SE4BEG1_8", - "VFRAME_SE4BEG1" - ], - [ - "MONITOR_WW4A3_8", - "VFRAME_WW4A3" - ], - [ - "MONITOR_BYP0_8", - "VFRAME_BYP0" - ], - [ - "MONITOR_LH10_8", - "VFRAME_LH10" - ], - [ - "MONITOR_EE4A3_8", - "VFRAME_EE4A3" - ], - [ - "MONITOR_WW2A1_8", - "VFRAME_WW2A1" - ], - [ - "MONITOR_EE4BEG2_8", - "VFRAME_EE4BEG2" - ], - [ - "MONITOR_NE4C0_8", - "VFRAME_NE4C0" - ], - [ - "MONITOR_IMUX34_8", - "VFRAME_IMUX34" - ], - [ - "MONITOR_IMUX26_8", - "VFRAME_IMUX26" - ], - [ - "MONITOR_NW4A0_8", - "VFRAME_NW4A0" - ], - [ - "MONITOR_EE4C2_8", - "VFRAME_EE4C2" - ], - [ - "MONITOR_IMUX29_8", - "VFRAME_IMUX29" - ], - [ - "MONITOR_WW4END0_8", - "VFRAME_WW4END0" - ], - [ - "MONITOR_EE4B3_8", - "VFRAME_EE4B3" - ], - [ - "MONITOR_NW4A3_8", - "VFRAME_NW4A3" - ], - [ - "MONITOR_CLK1_8", - "VFRAME_CLK1" - ], - [ - "MONITOR_BYP5_8", - "VFRAME_BYP5" - ], - [ - "MONITOR_IMUX27_8", - "VFRAME_IMUX27" - ], - [ - "MONITOR_IMUX19_8", - "VFRAME_IMUX19" - ], - [ - "MONITOR_WW4B0_8", - "VFRAME_WW4B0" - ], - [ - "MONITOR_IMUX23_8", - "VFRAME_IMUX23" - ], - [ - "MONITOR_IMUX15_8", - "VFRAME_IMUX15" - ], - [ - "MONITOR_IMUX11_8", - "VFRAME_IMUX11" - ], - [ - "MONITOR_IMUX46_8", - "VFRAME_IMUX46" - ], - [ - "MONITOR_FAN0_8", - "VFRAME_FAN0" - ], - [ - "MONITOR_NE4BEG2_8", - "VFRAME_NE4BEG2" - ], - [ - "MONITOR_LH1_8", - "VFRAME_LH1" - ], - [ - "MONITOR_EE2BEG1_8", - "VFRAME_EE2BEG1" - ], - [ - "MONITOR_EE4C0_8", - "VFRAME_EE4C0" - ], - [ - "MONITOR_IMUX9_8", - "VFRAME_IMUX9" - ], - [ - "MONITOR_CTRL1_8", - "VFRAME_CTRL1" - ], - [ - "MONITOR_IMUX32_8", - "VFRAME_IMUX32" - ], - [ - "MONITOR_EE4A2_8", - "VFRAME_EE4A2" - ], - [ - "MONITOR_IMUX3_8", - "VFRAME_IMUX3" - ], - [ - "MONITOR_BYP1_8", - "VFRAME_BYP1" - ], - [ - "MONITOR_EE2BEG2_8", - "VFRAME_EE2BEG2" - ], - [ - "MONITOR_SW2A3_8", - "VFRAME_SW2A3" - ], - [ - "MONITOR_SW2A1_8", - "VFRAME_SW2A1" - ], - [ - "MONITOR_ER1BEG2_8", - "VFRAME_ER1BEG2" - ], - [ - "MONITOR_NE4C3_8", - "VFRAME_NE4C3" - ], - [ - "MONITOR_LH12_8", - "VFRAME_LH12" - ], - [ - "MONITOR_SE4C0_8", - "VFRAME_SE4C0" - ], - [ - "MONITOR_SE4BEG0_8", - "VFRAME_SE4BEG0" - ], - [ - "MONITOR_IMUX38_8", - "VFRAME_IMUX38" - ], - [ - "MONITOR_HORIZ_VAUXN14", - "VFRAME_MONITOR_N" - ], - [ - "MONITOR_EL1BEG1_8", - "VFRAME_EL1BEG1" - ], - [ - "MONITOR_IMUX20_8", - "VFRAME_IMUX20" - ], - [ - "MONITOR_BYP3_8", - "VFRAME_BYP3" - ], - [ - "MONITOR_NE2A2_8", - "VFRAME_NE2A2" - ], - [ - "MONITOR_SE4BEG2_8", - "VFRAME_SE4BEG2" - ], - [ - "MONITOR_BYP2_8", - "VFRAME_BYP2" - ], - [ - "MONITOR_IMUX39_8", - "VFRAME_IMUX39" - ], - [ - "MONITOR_IMUX28_8", - "VFRAME_IMUX28" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "HCLK_INT_INTERFACE" - ], - "wire_pairs": [ - [ - "CLK_HROW_CK_IN_L2", - "HCLK_INT_INTERFACE_CK_IN2" - ], - [ - "CLK_HROW_CK_BUFRCLK_L0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "CLK_HROW_CK_BUFRCLK_L3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_L3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "CLK_HROW_CK_IN_L13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "CLK_HROW_CK_BUFHCLK_L9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "CLK_HROW_CK_BUFHCLK_L4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "CLK_HROW_CK_IN_L0", - "HCLK_INT_INTERFACE_CK_IN0" - ], - [ - "CLK_HROW_CK_BUFHCLK_L1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "CLK_HROW_CK_IN_L12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "CLK_HROW_CK_IN_L3", - "HCLK_INT_INTERFACE_CK_IN3" - ], - [ - "CLK_HROW_CK_BUFHCLK_L11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "CLK_HROW_CK_BUFRCLK_L1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "CLK_HROW_CK_BUFHCLK_L0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "CLK_HROW_CK_IN_L5", - "HCLK_INT_INTERFACE_CK_IN5" - ], - [ - "CLK_HROW_CK_IN_L1", - "HCLK_INT_INTERFACE_CK_IN1" - ], - [ - "CLK_HROW_CK_IN_L4", - "HCLK_INT_INTERFACE_CK_IN4" - ], - [ - "CLK_HROW_CK_IN_L10", - "HCLK_INT_INTERFACE_CK_IN10" - ], - [ - "CLK_HROW_CK_BUFRCLK_L2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "CLK_HROW_CK_BUFHCLK_L8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "CLK_HROW_CK_BUFHCLK_L6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ], - [ - "CLK_HROW_CK_BUFHCLK_L10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "CLK_HROW_CK_IN_L6", - "HCLK_INT_INTERFACE_CK_IN6" - ], - [ - "CLK_HROW_CK_IN_L9", - "HCLK_INT_INTERFACE_CK_IN9" - ], - [ - "CLK_HROW_CK_BUFHCLK_L7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], - [ - "CLK_HROW_CK_IN_L8", - "HCLK_INT_INTERFACE_CK_IN8" - ], - [ - "CLK_HROW_CK_BUFHCLK_L5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "CLK_HROW_CK_BUFHCLK_L2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "CLK_HROW_CK_IN_L7", - "HCLK_INT_INTERFACE_CK_IN7" - ], - [ - "CLK_HROW_CK_IN_L11", - "HCLK_INT_INTERFACE_CK_IN11" + "GTPE2_CHANNEL_TXOUTCLK_3", + "GTPE2_COMMON_TXOUTCLK_3" ] ] }, @@ -391273,73 +345857,29 @@ -5 ], "tile_types": [ - "GTP_CHANNEL_2", + "GTP_CHANNEL_1", "VBRK_EXT" ], "wire_pairs": [ [ - "GTPE2_FAN0_10", - "VBRK_EXT_FAN0" + "GTPE2_BYP0_10", + "VBRK_EXT_BYP0" ], [ - "GTPE2_IMUX9_10", - "VBRK_EXT_IMUX9" + "GTPE2_BYP1_10", + "VBRK_EXT_BYP1" ], [ - "GTPE2_BYP7_10", - "VBRK_EXT_BYP7" + "GTPE2_BYP2_10", + "VBRK_EXT_BYP2" ], [ - "GTPE2_IMUX17_10", - "VBRK_EXT_IMUX17" + "GTPE2_BYP3_10", + "VBRK_EXT_BYP3" ], [ - "GTPE2_IMUX18_10", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX34_10", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX20_10", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX8_10", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX21_10", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX0_10", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B16_10", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_CLK0_10", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX10_10", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_FAN3_10", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX23_10", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX42_10", - "VBRK_EXT_IMUX42" + "GTPE2_BYP4_10", + "VBRK_EXT_BYP4" ], [ "GTPE2_BYP5_10", @@ -391350,22064 +345890,672 @@ "VBRK_EXT_BYP6" ], [ - "GTPE2_IMUX27_10", - "VBRK_EXT_IMUX27" + "GTPE2_BYP7_10", + "VBRK_EXT_BYP7" ], [ - "GTPE2_IMUX26_10", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX31_10", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX12_10", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX25_10", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_LOGIC_OUTS_B5_10", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_IMUX4_10", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_BYP2_10", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX19_10", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX7_10", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_LOGIC_OUTS_B23_10", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_FAN4_10", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_CTRL1_10", - "VBRK_EXT_CTRL1" + "GTPE2_CLK0_10", + "VBRK_EXT_CLK0" ], [ "GTPE2_CLK1_10", "VBRK_EXT_CLK1" ], [ - "GTPE2_BYP4_10", - "VBRK_EXT_BYP4" + "GTPE2_CTRL0_10", + "VBRK_EXT_CTRL0" ], [ - "GTPE2_LOGIC_OUTS_B14_10", - "VBRK_EXT_LOGIC_OUTS_B14" + "GTPE2_CTRL1_10", + "VBRK_EXT_CTRL1" ], [ - "GTPE2_LOGIC_OUTS_B3_10", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_IMUX6_10", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX3_10", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX1_10", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_IMUX35_10", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_BYP1_10", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX47_10", - "VBRK_EXT_IMUX47" + "GTPE2_FAN0_10", + "VBRK_EXT_FAN0" ], [ "GTPE2_FAN1_10", "VBRK_EXT_FAN1" ], - [ - "GTPE2_IMUX14_10", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX43_10", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_LOGIC_OUTS_B13_10", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX32_10", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B11_10", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTPE2_IMUX13_10", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX36_10", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_CTRL0_10", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_BYP0_10", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX40_10", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_BYP3_10", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX37_10", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_FAN6_10", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX33_10", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX30_10", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B9_10", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_LOGIC_OUTS_B6_10", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX16_10", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX45_10", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_LOGIC_OUTS_B1_10", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX28_10", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX39_10", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX15_10", - "VBRK_EXT_IMUX15" - ], [ "GTPE2_FAN2_10", "VBRK_EXT_FAN2" ], [ - "GTPE2_IMUX2_10", - "VBRK_EXT_IMUX2" + "GTPE2_FAN3_10", + "VBRK_EXT_FAN3" ], [ - "GTPE2_IMUX11_10", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX5_10", - "VBRK_EXT_IMUX5" + "GTPE2_FAN4_10", + "VBRK_EXT_FAN4" ], [ "GTPE2_FAN5_10", "VBRK_EXT_FAN5" ], [ - "GTPE2_IMUX44_10", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX29_10", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B12_10", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_LOGIC_OUTS_B2_10", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_LOGIC_OUTS_B4_10", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_IMUX22_10", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX46_10", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_LOGIC_OUTS_B22_10", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX24_10", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_LOGIC_OUTS_B19_10", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_LOGIC_OUTS_B17_10", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_LOGIC_OUTS_B0_10", - "VBRK_EXT_LOGIC_OUTS_B0" + "GTPE2_FAN6_10", + "VBRK_EXT_FAN6" ], [ "GTPE2_FAN7_10", "VBRK_EXT_FAN7" ], + [ + "GTPE2_IMUX0_10", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX1_10", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX2_10", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_10", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_10", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_10", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_10", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_10", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_10", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_10", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX10_10", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX11_10", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_10", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_10", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_10", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_10", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_10", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_10", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_10", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX19_10", + "VBRK_EXT_IMUX19" + ], + [ + "GTPE2_IMUX20_10", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_IMUX21_10", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX22_10", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX23_10", + "VBRK_EXT_IMUX23" + ], + [ + "GTPE2_IMUX24_10", + "VBRK_EXT_IMUX24" + ], + [ + "GTPE2_IMUX25_10", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX26_10", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX27_10", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX28_10", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_IMUX29_10", + "VBRK_EXT_IMUX29" + ], + [ + "GTPE2_IMUX30_10", + "VBRK_EXT_IMUX30" + ], + [ + "GTPE2_IMUX31_10", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_IMUX32_10", + "VBRK_EXT_IMUX32" + ], + [ + "GTPE2_IMUX33_10", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX34_10", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_IMUX35_10", + "VBRK_EXT_IMUX35" + ], + [ + "GTPE2_IMUX36_10", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX37_10", + "VBRK_EXT_IMUX37" + ], [ "GTPE2_IMUX38_10", "VBRK_EXT_IMUX38" ], + [ + "GTPE2_IMUX39_10", + "VBRK_EXT_IMUX39" + ], + [ + "GTPE2_IMUX40_10", + "VBRK_EXT_IMUX40" + ], [ "GTPE2_IMUX41_10", "VBRK_EXT_IMUX41" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "BRKH_TERM_INT", - "INT_R" - ], - "wire_pairs": [ - [ - "T_TERM_UTURN_INT_SW6B3", - "NW6A0" - ], - [ - "T_TERM_UTURN_INT_SE6D1", - "NE6C2" - ], - [ - "T_TERM_UTURN_INT_SS6E3", - "SS6E3" - ], - [ - "T_TERM_UTURN_INT_LVB5", - "LVB6" - ], - [ - "T_TERM_UTURN_INT_LVB1", - "LVB10" - ], - [ - "T_TERM_UTURN_INT_SS2A3", - "SS2A3" - ], - [ - "T_TERM_UTURN_INT_SW6D0", - "NW6C3" - ], - [ - "T_TERM_UTURN_INT_SE6B2", - "NE6A1" - ], - [ - "T_TERM_UTURN_INT_SE6C1", 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- ], - [ - "T_TERM_UTURN_INT_SW6E1", - "SW6E1" - ], - [ - "T_TERM_UTURN_INT_SE6B1", - "SE6B1" - ], - [ - "T_TERM_UTURN_INT_SW6B1", - "NW6A2" - ], - [ - "T_TERM_UTURN_INT_LVB2", - "LVB2" - ], - [ - "T_TERM_UTURN_INT_SW6D2", - "SW6D2" - ], - [ - "T_TERM_UTURN_INT_SW2A3", - "SW2A3" - ], - [ - "T_TERM_UTURN_INT_SL1END1_SLOW", - "SL1END1" - ], - [ - "T_TERM_UTURN_INT_SR1END3_SLOW", - "SR1END3" - ], - [ - "T_TERM_UTURN_INT_SL1END2_SLOW", - "SL1END2" - ], - [ - "T_TERM_UTURN_INT_SS2A1", - "SS2A1" - ], - [ - "T_TERM_UTURN_INT_SE2A1", - "SE2A1" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "FAN_BOUNCE_S3_6" - ], - [ - "T_TERM_UTURN_INT_SS6C3", - "SS6C3" - ], - [ - "T_TERM_UTURN_INT_SE6E1", - "NE6D2" - ], - [ - "T_TERM_INT_UTURN_LV_R7", - "LV10" - ], - [ - "T_TERM_INT_UTURN_LV_R9", - "LV8" - ], - [ - "T_TERM_UTURN_INT_SW6C3", - "NW6B0" - ], - [ - "T_TERM_UTURN_INT_SS6B3", - "SS6B3" - ], - [ - "T_TERM_UTURN_INT_WR1BEG_S0", - "WL1BEG3" - ], - [ - "T_TERM_UTURN_INT_SS6A0", - "SS6A0" - ], - [ - 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], - [ - "T_TERM_UTURN_INT_SW6E1", - "NW6D2" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "BYP_BOUNCE2" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", - "BYP_BOUNCE6" - ], - [ - "T_TERM_UTURN_INT_SW2A2", - "SW2A2" - ], - [ - "T_TERM_INT_UTURN_LV_R17", - "LV17" - ], - [ - "T_TERM_UTURN_INT_SL1END2_SLOW", - "NR1BEG1" - ], - [ - "T_TERM_UTURN_INT_SW6C0", - "NW6B3" - ], - [ - "T_TERM_UTURN_INT_SE6C1", - "SE6C1" - ], - [ - "T_TERM_UTURN_INT_SS2END2", - "SS2END2" - ], - [ - "T_TERM_UTURN_INT_SE2A0", - "NE2BEG3" - ], - [ - "T_TERM_UTURN_INT_SS6D3", - "NN6C0" - ], - [ - "T_TERM_UTURN_INT_SW6B0", - "SW6B0" - ], - [ - "T_TERM_UTURN_INT_SE2A3", - "SE2A3" - ], - [ - "T_TERM_UTURN_INT_SW2A3", - "NW2BEG0" - ], - [ - "T_TERM_UTURN_INT_SE6C2", - "NE6B1" - ], - [ - "T_TERM_UTURN_INT_SR1END1_SLOW", - "NL1BEG2" - ], - [ - "T_TERM_UTURN_INT_SW2A0", - "NW2BEG3" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", - "BYP_BOUNCE7" - ], - [ - "T_TERM_UTURN_INT_LVB0", - "LVB0" - ], - [ - "T_TERM_UTURN_INT_SE6D1", - "SE6D1" - ], - [ - "T_TERM_UTURN_INT_SW6D3", - "NW6C0" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_4" - ], - [ - "T_TERM_UTURN_INT_SE2A0", - "SE2A0" - ], - [ - "T_TERM_UTURN_INT_SE6B0", - "SE6B0" - ], - [ - "T_TERM_UTURN_INT_SR1END3_SLOW", - "NL1BEG0" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_2" - ], - [ - "T_TERM_UTURN_INT_SS6A2", - "SS6A2" - ], - [ - "T_TERM_UTURN_INT_SL1END3_SLOW", - "SL1END3" - ], - [ - "T_TERM_UTURN_INT_SE2A2", - "SE2A2" - ], - [ - "T_TERM_UTURN_INT_SE6D3", - "NE6C0" - ], - [ - "T_TERM_UTURN_INT_SS2END0", - "NN2A3" - ], - [ - "T_TERM_UTURN_INT_SW6B1", - "SW6B1" - ], - [ - "T_TERM_UTURN_INT_SE6D0", - "SE6D0" - ], - [ - "T_TERM_UTURN_INT_SW6C1", - "SW6C1" - ], - [ - "T_TERM_UTURN_INT_SW2A0", - "SW2A0" - ], - [ - "T_TERM_UTURN_INT_SE2A2", - "NE2BEG1" - ], - [ - "T_TERM_UTURN_INT_SW2A1", - "NW2BEG2" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", - "BYP_BOUNCE3" - ], - [ - "T_TERM_UTURN_INT_SW6B2", - "SW6B2" - ], - [ - "T_TERM_UTURN_INT_SS6D2", - "SS6D2" - ], - [ - "T_TERM_UTURN_INT_SR1END1_SLOW", - "SR1END1" - ], - [ - "T_TERM_UTURN_INT_SS2A2", - "NN2BEG1" - ], - [ - "T_TERM_UTURN_INT_SS6E0", - "NN6D3" - ], - [ - "T_TERM_UTURN_INT_SS6A0", - "NN6BEG3" - ], - [ - "T_TERM_INT_UTURN_LV_R16", - "LV16" - ], - [ - "T_TERM_UTURN_INT_SS6A3", - "NN6BEG0" - ], - [ - "T_TERM_UTURN_INT_LVB0", - "LVB11" - ], - [ - "T_TERM_UTURN_INT_SE6B1", - "NE6A2" - ], - [ - "T_TERM_UTURN_INT_SE2A1", - "NE2BEG2" - ], - [ - "T_TERM_UTURN_INT_SE6E2", - "SE6E2" - ], - [ - "T_TERM_INT_UTURN_LV_R3", - "LV14" - ], - [ - "T_TERM_UTURN_INT_SS6E2", - "NN6D1" - ], - [ - "T_TERM_UTURN_INT_WR1BEG_S0", - "WR1BEG_S0" - ], - [ - "T_TERM_UTURN_INT_SL1END3_SLOW", - "NR1BEG0" - ], - [ - "T_TERM_UTURN_INT_SS2END3", - "NN2A0" - ], - [ - "T_TERM_UTURN_INT_SS2A0", - "SS2A0" - ], - [ - "T_TERM_UTURN_INT_SE6E2", - "NE6D1" - ], - [ - "T_TERM_INT_UTURN_LV_R2", - "LV2" - ], - [ - "T_TERM_UTURN_INT_SW6D0", - "SW6D0" - ], - [ - "T_TERM_UTURN_INT_SW6E2", - "SW6E2" - ], - [ - "T_TERM_UTURN_INT_SS2END0", - "SS2END0" - ], - [ - "T_TERM_UTURN_INT_SS6E3", - "NN6D0" - ], - [ - "T_TERM_UTURN_INT_ER1END3", - "ER1END3" - ], - [ - "T_TERM_UTURN_INT_SW6C2", - "NW6B1" - ], - [ - "T_TERM_UTURN_INT_SE6B3", - "SE6B3" - ], - [ - "T_TERM_UTURN_INT_SW6E0", - "NW6D3" - ], - [ - "T_TERM_UTURN_INT_SS6E2", - "SS6E2" - ], - [ - "T_TERM_UTURN_INT_SE6C0", - "NE6B3" - ], - [ - "T_TERM_INT_UTURN_LV_R7", - "LV7" - ], - [ - "T_TERM_UTURN_INT_SL1END1_SLOW", - "NR1BEG2" - ], - [ - "T_TERM_UTURN_INT_SW6E2", - "NW6D1" - ], - [ - "T_TERM_UTURN_INT_LVB5", - "LVB5" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "DSP_L", - "HCLK_DSP_L" - ], - "wire_pairs": [ - [ - "DSP_0_PCIN25", - "HCLK_DSP_PCIN25" - ], - [ - "DSP_0_BCIN17", - "HCLK_DSP_BCIN17" - ], - [ - "DSP_0_PCIN43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_0_PCIN13", - "HCLK_DSP_PCIN13" - ], - [ - "DSP_0_PCIN2", - "HCLK_DSP_PCIN2" - ], - [ - "DSP_0_ACIN8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_0_ACIN13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_0_ACIN3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_0_ACIN25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_0_BCIN12", - "HCLK_DSP_BCIN12" - ], - [ - "DSP_0_ACIN2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_0_BCIN13", - "HCLK_DSP_BCIN13" - ], - [ - "DSP_0_ACIN28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_0_ACIN16", - "HCLK_DSP_ACIN16" - ], - [ - "DSP_0_PCIN45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_0_PCIN11", - "HCLK_DSP_PCIN11" - ], - [ - "DSP_0_BCIN1", - "HCLK_DSP_BCIN1" - ], - [ - "DSP_0_PCIN37", - "HCLK_DSP_PCIN37" - ], - [ - "DSP_0_PCIN28", - "HCLK_DSP_PCIN28" - ], - [ - "DSP_0_PCIN29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_0_PCIN30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_0_PCIN15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_0_BCIN10", - "HCLK_DSP_BCIN10" - ], - [ - "DSP_0_BCIN16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_0_PCIN6", - "HCLK_DSP_PCIN6" - ], - [ - "DSP_0_BCIN2", - "HCLK_DSP_BCIN2" - ], - [ - "DSP_0_ACIN10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_0_PCIN47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_0_ACIN27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_0_ACIN9", - "HCLK_DSP_ACIN9" - ], - [ - "DSP_0_ACIN18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_0_PCIN5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_0_PCIN9", - "HCLK_DSP_PCIN9" - ], - [ - "DSP_0_PCIN42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_0_PCIN31", - "HCLK_DSP_PCIN31" - ], - [ - "DSP_0_PCIN10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_0_PCIN0", - "HCLK_DSP_PCIN0" - ], - [ - "DSP_0_PCIN40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_0_PCIN33", - "HCLK_DSP_PCIN33" - ], - [ - "DSP_0_CARRYCASCIN", - "HCLK_DSP_CARRYCASCIN" - ], - [ - "DSP_0_ACIN20", - "HCLK_DSP_ACIN20" - ], - [ - "DSP_0_ACIN14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_0_ACIN6", - "HCLK_DSP_ACIN6" - ], - [ - "DSP_0_PCIN20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_0_PCIN22", - "HCLK_DSP_PCIN22" - ], - [ - "DSP_0_PCIN18", - "HCLK_DSP_PCIN18" - ], - [ - "DSP_0_PCIN36", - "HCLK_DSP_PCIN36" - ], - [ - "DSP_0_PCIN38", - "HCLK_DSP_PCIN38" - ], - [ - "DSP_0_BCIN14", - "HCLK_DSP_BCIN14" - ], - [ - "DSP_0_PCIN1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_0_ACIN1", - "HCLK_DSP_ACIN1" - ], - [ - "DSP_0_ACIN24", - "HCLK_DSP_ACIN24" - ], - [ - "DSP_0_ACIN11", - "HCLK_DSP_ACIN11" - ], - [ - "DSP_0_PCIN41", - "HCLK_DSP_PCIN41" - ], - [ - "DSP_0_ACIN19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_0_PCIN14", - "HCLK_DSP_PCIN14" - ], - [ - "DSP_0_ACIN0", - "HCLK_DSP_ACIN0" - ], - [ - "DSP_0_PCIN24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_0_BCIN3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_0_PCIN8", - "HCLK_DSP_PCIN8" - ], - [ - "DSP_0_PCIN21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_0_PCIN4", - "HCLK_DSP_PCIN4" - ], - [ - "DSP_0_PCIN26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_0_ACIN15", - "HCLK_DSP_ACIN15" - ], - [ - "DSP_0_ACIN23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_0_BCIN6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_0_ACIN5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_0_PCIN17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_0_PCIN7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_0_BCIN0", - "HCLK_DSP_BCIN0" - ], - [ - "DSP_0_BCIN9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_0_ACIN26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_0_ACIN29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_0_ACIN12", - "HCLK_DSP_ACIN12" - ], - [ - "DSP_0_BCIN4", - "HCLK_DSP_BCIN4" - ], - [ - "DSP_0_PCIN32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_0_ACIN7", - "HCLK_DSP_ACIN7" - ], - [ - "DSP_0_PCIN19", - "HCLK_DSP_PCIN19" - ], - [ - "DSP_0_BCIN8", - "HCLK_DSP_BCIN8" - ], - [ - "DSP_0_ACIN17", - "HCLK_DSP_ACIN17" - ], - [ - "DSP_0_PCIN39", - "HCLK_DSP_PCIN39" - ], - [ - "DSP_0_ACIN22", - "HCLK_DSP_ACIN22" - ], - [ - "DSP_0_ACIN4", - "HCLK_DSP_ACIN4" - ], - [ - "DSP_0_BCIN7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_0_BCIN15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_0_ACIN21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_0_PCIN27", - "HCLK_DSP_PCIN27" - ], - [ - "DSP_0_PCIN35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_0_BCIN5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_0_PCIN16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_0_PCIN34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_0_MULTSIGNIN", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_0_BCIN11", - "HCLK_DSP_BCIN11" - ], - [ - "DSP_0_PCIN46", - "HCLK_DSP_PCIN46" - ], - [ - "DSP_0_PCIN3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_0_PCIN23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_0_PCIN44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_0_PCIN12", - "HCLK_DSP_PCIN12" - ] - ] - }, - { - "grid_deltas": [ - -1, - -5 - ], - "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_IMUX16_5", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_SW2A1_5", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_PMV_IMUX14_5", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_PMV_SW4A0_5", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_PMV_IMUX40_5", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_PMV_WW4A3_5", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_PMV_NW4END2_5", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_IMUX9_5", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_SW4END0_5", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_EE2BEG1_5", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_EE4C3_5", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_PMV_EL1BEG0_5", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_PMV_EE4B0_5", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_PMV_SE4BEG3_5", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_BYP2_5", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_PMV_LH12_5", - "INT_INTERFACE_LH12" - ], - [ - "CLK_PMV_NE4C3_5", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_PMV_SW2A3_5", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_IMUX28_5", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_PMV_IMUX25_5", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_PMV_WR1END1_5", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_PMV_SE4C0_5", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_PMV_BYP4_5", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_PMV_NE4C1_5", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_PMV_IMUX35_5", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_PMV_SE4BEG0_5", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_PMV_WW4END2_5", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_PMV_NW2A0_5", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_PMV_IMUX17_5", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_FAN1_5", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_BYP3_5", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_WW4B1_5", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_PMV_BYP0_5", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_PMV_WL1END3_5", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_PMV_EE2A0_5", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_WL1END0_5", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_PMV_NW4A2_5", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_PMV_IMUX8_5", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_PMV_ER1BEG1_5", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_PMV_WW4A0_5", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_PMV_NE4BEG3_5", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_WL1END2_5", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_PMV_IMUX20_5", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_IMUX5_5", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_IMUX24_5", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_PMV_NW4END3_5", - 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- "DSP_LH12_2", - "VBRK_LH12" - ], - [ - "DSP_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "DSP_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "DSP_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "DSP_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "DSP_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "DSP_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "DSP_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "DSP_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "DSP_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "DSP_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "DSP_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "DSP_LH9_2", - "VBRK_LH9" - ], - [ - "DSP_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "DSP_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "DSP_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "DSP_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "DSP_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "DSP_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "DSP_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "DSP_LH10_2", - "VBRK_LH10" - ], - [ - "DSP_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "DSP_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "DSP_LH2_2", - "VBRK_LH2" - ], - [ - "DSP_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "DSP_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "DSP_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "DSP_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "DSP_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "DSP_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "DSP_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "DSP_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "DSP_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "DSP_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "DSP_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "DSP_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "DSP_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "DSP_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "DSP_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "DSP_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "DSP_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "DSP_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "DSP_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "DSP_LH3_2", - "VBRK_LH3" - ], - [ - "DSP_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "DSP_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "DSP_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "DSP_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "DSP_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "DSP_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "DSP_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "DSP_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "DSP_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "DSP_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "DSP_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "DSP_LH4_2", - "VBRK_LH4" - ], - [ - "DSP_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "DSP_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "DSP_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "DSP_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "DSP_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "DSP_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "DSP_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "DSP_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "DSP_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "DSP_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "DSP_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "DSP_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "DSP_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "DSP_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "DSP_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "DSP_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "DSP_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "DSP_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "DSP_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "DSP_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "DSP_LH1_2", - "VBRK_LH1" - ], - [ - "DSP_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "DSP_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "DSP_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "DSP_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "DSP_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "DSP_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "DSP_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "DSP_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "DSP_LH8_2", - "VBRK_LH8" - ], - [ - "DSP_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "DSP_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "DSP_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "DSP_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "DSP_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "DSP_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "DSP_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "DSP_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "DSP_LH6_2", - "VBRK_LH6" - ], - [ - "DSP_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "DSP_LH5_2", - "VBRK_LH5" - ], - [ - "DSP_LH11_2", - "VBRK_LH11" - ], - [ - "DSP_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "DSP_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "DSP_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "DSP_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "DSP_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "DSP_LH7_2", - "VBRK_LH7" - ], - [ - "DSP_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "DSP_EE4BEG2_2", - "VBRK_EE4BEG2" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_PMVIOB", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_FEED_EE2BEG1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_FEED_NW4END3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_PMV_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_FEED_WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_FEED_EE4BEG1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_FEED_NE2A3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_PMV_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_NE2A2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_FEED_WW4B2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_FEED_NW4A2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_PMV_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_LOGIC_OUTS2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_FEED_WR1END0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_FEED_NE4C3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_FEED_EE4A2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_FEED_EL1BEG1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_FEED_NE4C0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_PMV_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_FEED_WL1END2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_FEED_NW2A2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_PMV_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_FEED_NW4END1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_FEED_LH7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_FEED_SW4A3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_PMV_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_PMV_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_FEED_WW4END3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_FEED_WR1END1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_PMV_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_FEED_SE4C0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_FEED_EE4B3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_FEED_MONITOR_P", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_FEED_SW4A1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_FEED_LH9", - "INT_INTERFACE_LH9" - ], - [ - "CLK_PMV_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_FEED_NW2A1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_FEED_EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_FEED_SW4END1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_FEED_NE4C1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_FEED_SW2A1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_FEED_SW4END3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_FEED_SE4C1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_FEED_LH3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_PMV_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_FEED_WR1END2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_FEED_SE4BEG3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_FEED_LH1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_PMV_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_PMV_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_FEED_NW4A1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_FEED_LH6", - "INT_INTERFACE_LH6" - ], - [ - "CLK_PMV_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_FEED_ER1BEG1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_FEED_WW4B3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_FEED_NE2A0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_FEED_WW4A1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_PMV_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_FEED_LH12", - "INT_INTERFACE_LH12" - ], - [ - "CLK_FEED_WW4A0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_FEED_SW4END0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_FEED_EE4A1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_PMV_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_PMV_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_FEED_EL1BEG0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_FEED_EE4B1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_LOGIC_OUTS1_0", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_PMV_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_FEED_SE4BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_PMV_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_FEED_WW4B1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_FEED_EE2BEG0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_FEED_WW4C2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_FEED_ER1BEG2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_FEED_LH2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_FEED_SE4BEG1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_PMV_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_PMV_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_FEED_EE4A3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_FEED_EL1BEG3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_FEED_LH4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_FEED_LH5", - "INT_INTERFACE_LH5" - ], - [ - "CLK_FEED_SE2A3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_PMV_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_FEED_WW4A3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_FEED_LH11", - "INT_INTERFACE_LH11" - ], - [ - "CLK_FEED_SE2A0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_FEED_NW4A3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_FEED_WW4END1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_FEED_MONITOR_N", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_FEED_EL1BEG2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_FEED_WL1END1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_FEED_SW4A0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_FEED_WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_FEED_SW4END2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_PMV_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_FEED_WW2END2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_FEED_WL1END3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_FEED_WR1END3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_FEED_SE4C3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_FEED_LH8", - "INT_INTERFACE_LH8" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_SE2A1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_FEED_EE4B2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_FEED_NW4END0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_FEED_EE4B0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_FEED_EE2BEG3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_FEED_SW2A0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_FEED_WW4C1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_FEED_WW4B0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_PMV_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_FEED_SE4C2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_FEED_SW2A2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_FEED_EE2A1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_FEED_ER1BEG0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_FEED_WW4A2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_FEED_EE4A0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_PMV_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_FEED_NE4C2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_FEED_NW4END2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_FEED_EE2A0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_FEED_NE4BEG1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_FEED_WW2A3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_FEED_SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_FEED_WW4END0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_FEED_WW2A2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_FEED_EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_FEED_NE4BEG2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_PMV_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_FEED_WW4C0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_FEED_SE4BEG2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_FEED_NW2A3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_FEED_EE2BEG2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_FEED_WW2END1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_FEED_NE4BEG3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_LOGIC_OUTS0_0", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_PMV_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_FEED_WW2A1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_FEED_EE4BEG3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_FEED_NE4BEG0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_PMV_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_FEED_EE4BEG0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_FEED_WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_PMV_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_FEED_SE2A2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_FEED_EE4BEG2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_PMV_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_FEED_SW4A2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_FEED_NW4A0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_FEED_NW2A0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_FEED_LH10", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_PMV_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_FEED_EE4C0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_FEED_EE2A3", - "INT_INTERFACE_EE2A3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "GTP_COMMON", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTPE2_IMUX43_0", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX12_0", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_CLK1_0", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX23_0", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX46_0", + "GTPE2_IMUX46_10", "VBRK_EXT_IMUX46" ], [ - "GTPE2_FAN3_0", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX3_0", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX18_0", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_BYP1_0", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_BYP6_0", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX19_0", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX31_0", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX22_0", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX4_0", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX0_0", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX13_0", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX17_0", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX34_0", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX27_0", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX45_0", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX29_0", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX44_0", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX16_0", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX42_0", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX36_0", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_CLK0_0", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX30_0", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX9_0", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_BYP0_0", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX24_0", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_CTRL1_0", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX8_0", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX2_0", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX40_0", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX33_0", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_BYP7_0", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX5_0", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX21_0", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX7_0", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX28_0", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX1_0", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_IMUX37_0", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_BYP3_0", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX6_0", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX39_0", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX14_0", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX20_0", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX10_0", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX11_0", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX26_0", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_BYP2_0", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_FAN6_0", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_FAN0_0", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX38_0", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX32_0", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_BYP4_0", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX15_0", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_CTRL0_0", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_FAN2_0", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_FAN4_0", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX47_0", + "GTPE2_IMUX47_10", "VBRK_EXT_IMUX47" ], [ - "GTPE2_IMUX41_0", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_FAN5_0", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_FAN1_0", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX25_0", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX35_0", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_BYP5_0", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_FAN7_0", - "VBRK_EXT_FAN7" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_SW4END0_7", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EE4B1_7", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX7_7", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_NW4END3_7", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_LH5_7", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_IMUX9_7", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4BEG3_7", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_ER1BEG2_7", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_EE4C3_7", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_NW2A3_7", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_CTRL1_7", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP4_7", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_BYP7_7", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_CTRL0_7", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_NE4C2_7", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX16_7", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX19_7", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_EE4A2_7", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE4A1_7", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_EE2A0_7", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_SW4A2_7", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_LH6_7", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_IMUX22_7", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_SW4END1_7", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_NW2A2_7", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_SE4C0_7", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_IMUX4_7", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WL1END3_7", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_SW4A1_7", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_EE4C0_7", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_SW2A3_7", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_IMUX38_7", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX34_7", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_NE4C3_7", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX30_7", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_NE2A1_7", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_WW2END1_7", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_NE2A2_7", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_IMUX24_7", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_SE2A1_7", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX11_7", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_WR1END1_7", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_LH2_7", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_IMUX21_7", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX15_7", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_EE4A0_7", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_EE2BEG1_7", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_WW4C3_7", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_FAN1_7", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_WW2A3_7", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_NW4A2_7", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_LH11_7", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_SW2A2_7", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_EE4BEG0_7", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SE4BEG3_7", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_IMUX26_7", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_BYP0_7", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_WR1END3_7", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_EE4BEG1_7", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_IMUX17_7", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_LH1_7", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_WW4C1_7", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_IMUX13_7", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_SE4BEG2_7", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_SE4C3_7", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_NE4BEG2_7", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW2A1_7", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE4A3_7", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_WW2A1_7", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX36_7", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4B3_7", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX39_7", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SE4BEG1_7", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NW4END1_7", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_IMUX41_7", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SE4BEG0_7", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_WL1END1_7", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_NW4END2_7", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EL1BEG0_7", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_EE2BEG0_7", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_NE4BEG3_7", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_IMUX28_7", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_EE2A2_7", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_FAN3_7", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX12_7", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_WW4END3_7", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_SW4END2_7", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_BYP1_7", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SE2A2_7", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2END0_7", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_FAN6_7", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WR1END0_7", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_IMUX14_7", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_WW2A0_7", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SE2A3_7", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_WW2END3_7", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_IMUX33_7", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX45_7", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_CLK1_7", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_ER1BEG3_7", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_NW4A1_7", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_WW4A2_7", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_EE2A1_7", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_SW4END3_7", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EL1BEG2_7", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW4B3_7", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_LH9_7", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_EL1BEG3_7", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_EE2BEG3_7", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW4A3_7", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_NW4A0_7", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX32_7", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX3_7", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_CLK0_7", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW4A1_7", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW4C2_7", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW2A0_7", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_IMUX44_7", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH8_7", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_LH10_7", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_LH7_7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_FAN7_7", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW4C0_7", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_IMUX18_7", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_NE4C0_7", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW2A2_7", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_LH4_7", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_FAN4_7", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_IMUX43_7", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_BYP5_7", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_WW4A0_7", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WL1END0_7", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_SE4C1_7", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_FAN5_7", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_NW2A1_7", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_FAN0_7", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX37_7", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_EE4BEG2_7", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_EE4C2_7", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_IMUX1_7", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_NE4BEG0_7", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_SE2A0_7", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_WW4END0_7", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_WR1END2_7", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_IMUX46_7", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_NE4BEG1_7", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_IMUX35_7", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX47_7", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_NW2A0_7", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_IMUX40_7", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_WW4B2_7", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_NE2A0_7", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_IMUX6_7", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_WW4END1_7", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_IMUX27_7", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_SE4C2_7", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_IMUX42_7", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_NE2A3_7", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_ER1BEG1_7", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_BYP2_7", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_EE2BEG2_7", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX29_7", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_SW4A0_7", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_SW4A3_7", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NW4A3_7", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_IMUX5_7", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX2_7", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_IMUX23_7", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_EE4C1_7", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_LH12_7", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_EE4B2_7", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_WW4B1_7", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_ER1BEG0_7", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_BYP6_7", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_FAN2_7", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_WW4END2_7", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_IMUX31_7", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_WW2END2_7", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_WL1END2_7", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_NW4END0_7", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_NE4C1_7", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW4B0_7", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_IMUX25_7", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EE4B0_7", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_IMUX0_7", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX10_7", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_IMUX20_7", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_EE2A3_7", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_BYP3_7", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_LH3_7", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_EL1BEG1_7", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX8_7", - "INT_INTERFACE_IMUX8" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "BRAM_R", - "BRKH_BRAM" - ], - "wire_pairs": [ - [ - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" - ], - [ - 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"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" - ], - [ - "BRAM_FIFO36_CASCADEOUTB_1", - "BRKH_BRAM_CASCADEB_R" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU13", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU0", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU13", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 2 - ], - "tile_types": [ - "GTP_CHANNEL_1", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTPE2_FAN3_3", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX46_3", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX2_3", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_BYP4_3", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX35_3", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX15_3", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_CLK0_3", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX30_3", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B22_3", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_LOGIC_OUTS_B15_3", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_IMUX4_3", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_CTRL1_3", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX42_3", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX5_3", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX44_3", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_LOGIC_OUTS_B3_3", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_IMUX17_3", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX20_3", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX41_3", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX40_3", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_LOGIC_OUTS_B7_3", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX26_3", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B13_3", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_BYP2_3", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX38_3", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_LOGIC_OUTS_B10_3", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_BYP5_3", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX11_3", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX37_3", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX25_3", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_LOGIC_OUTS_B0_3", + "GTPE2_LOGIC_OUTS_B0_10", "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "GTPE2_IMUX27_3", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX7_3", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_LOGIC_OUTS_B1_3", + "GTPE2_LOGIC_OUTS_B1_10", "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "GTPE2_LOGIC_OUTS_B12_3", - "VBRK_EXT_LOGIC_OUTS_B12" + "GTPE2_LOGIC_OUTS_B2_10", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ - "GTPE2_IMUX9_3", - "VBRK_EXT_IMUX9" + "GTPE2_LOGIC_OUTS_B3_10", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "GTPE2_LOGIC_OUTS_B9_3", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX39_3", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_FAN0_3", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_FAN7_3", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_BYP3_3", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX0_3", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX47_3", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX22_3", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX28_3", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_BYP0_3", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX32_3", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX23_3", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_BYP6_3", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX21_3", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_BYP1_3", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_LOGIC_OUTS_B16_3", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_LOGIC_OUTS_B17_3", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_LOGIC_OUTS_B5_3", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_FAN1_3", - "VBRK_EXT_FAN1" - ], - [ - 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], - [ - "MONITOR_IMUX45_6", - "VFRAME_IMUX45" - ], - [ - "MONITOR_EE4BEG1_6", - "VFRAME_EE4BEG1" - ], - [ - "MONITOR_IMUX6_6", - "VFRAME_IMUX6" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "BRKH_CLK", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "BRKH_CLK_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "BRKH_CLK_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "BRKH_CLK_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "BRKH_CLK_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "BRKH_CLK_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "BRKH_CLK_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "BRKH_CLK_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "BRKH_CLK_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "BRKH_CLK_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "BRKH_CLK_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "BRKH_CLK_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "BRKH_CLK_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "BRKH_CLK_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "BRKH_CLK_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "BRKH_CLK_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "BRKH_CLK_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "BRKH_CLK_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "BRKH_CLK_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "BRKH_CLK_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "BRKH_CLK_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "BRKH_CLK_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "BRKH_CLK_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "BRKH_CLK_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "BRKH_CLK_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "BRKH_CLK_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "BRKH_CLK_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "BRKH_CLK_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "BRKH_CLK_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "BRKH_CLK_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "BRKH_CLK_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "BRKH_CLK_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "BRKH_CLK_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_WW2A3_4", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_PMV_LH12_4", - "INT_INTERFACE_LH12" - ], - [ - "CLK_PMV_IMUX38_4", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_PMV_WL1END1_4", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_PMV_EE4B1_4", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_NE4BEG0_4", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_PMV_NW4A0_4", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_LH8_4", - "INT_INTERFACE_LH8" - ], - [ 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"CLK_PMV_BYP6_4", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_PMV_IMUX24_4", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_PMV_SW4A2_4", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_IMUX22_4", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_PMV_WW2A2_4", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_PMV_SW4END1_4", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_PMV_IMUX6_4", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_PMV_IMUX26_4", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_PMV_NE4C3_4", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_PMV_WR1END2_4", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_SE2A2_4", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_BYP1_4", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_IMUX16_4", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_SE4BEG3_4", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_IMUX10_4", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_PMV_WW4END1_4", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_IMUX47_4", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_NE4C1_4", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_PMV_SW4A1_4", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_PMV_EE4A2_4", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_LH2_4", - "INT_INTERFACE_LH2" - ], - [ - "CLK_PMV_NE4BEG2_4", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_PMV_WW4C1_4", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_PMV_NE2A0_4", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_EL1BEG3_4", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_PMV_EE2A2_4", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_PMV_IMUX31_4", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_PMV_IMUX2_4", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_IMUX41_4", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_PMV_IMUX7_4", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_IMUX40_4", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_PMV_IMUX25_4", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_PMV_IMUX9_4", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_SW4A0_4", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_PMV_WW4B0_4", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_PMV_BYP5_4", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_MONITOR_N_4", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_PMV_NW2A3_4", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_PMV_BYP2_4", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_PMV_IMUX18_4", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_PMV_IMUX43_4", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_PMV_IMUX44_4", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_PMV_EE2A3_4", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_PMV_SE2A1_4", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_SW4END0_4", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_IMUX46_4", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_PMV_SW2A0_4", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_PMV_IMUX32_4", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_PMV_IMUX33_4", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_IMUX21_4", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_IMUX36_4", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_PMV_IMUX20_4", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_EE2A1_4", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_SW2A2_4", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_PMV_LH10_4", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_SE4C1_4", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_PMV_NW2A2_4", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_PMV_EE4A3_4", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_LH1_4", - "INT_INTERFACE_LH1" - ], - [ - "CLK_PMV_LH11_4", - "INT_INTERFACE_LH11" - ], - [ - "CLK_PMV_EE2BEG3_4", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_LH5_4", - "INT_INTERFACE_LH5" - ], - [ - "CLK_PMV_IMUX14_4", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_PMV_WL1END3_4", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_PMV_IMUX19_4", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_PMV_ER1BEG1_4", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_PMV_EE4C2_4", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_PMV_CLK0_4", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_PMV_WL1END2_4", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_PMV_WW2END1_4", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_PMV_IMUX23_4", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_PMV_EE2A0_4", - "INT_INTERFACE_EE2A0" - ], - [ - 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-4 - ], - "tile_types": [ - "CLK_PMV", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_PMV_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "CLK_PMV_LH4_4", - "VBRK_LH4" - ], - [ - "CLK_PMV_LH10_4", - "VBRK_LH10" - ], - [ - "CLK_PMV_LH6_4", - "VBRK_LH6" - ], - [ - "CLK_PMV_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "CLK_PMV_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CLK_PMV_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "CLK_PMV_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "CLK_PMV_LH5_4", - "VBRK_LH5" - ], - [ - "CLK_PMV_SE2A1_4", - "VBRK_SE2A1" - ], - [ - "CLK_PMV_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "CLK_PMV_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "CLK_PMV_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "CLK_PMV_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "CLK_PMV_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "CLK_PMV_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "CLK_PMV_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "CLK_PMV_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "CLK_PMV_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "CLK_PMV_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "CLK_PMV_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "CLK_PMV_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "CLK_PMV_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "CLK_PMV_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "CLK_PMV_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "CLK_PMV_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "CLK_PMV_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CLK_PMV_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CLK_PMV_LH8_4", - "VBRK_LH8" - ], - [ - "CLK_PMV_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CLK_PMV_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "CLK_PMV_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "CLK_PMV_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CLK_PMV_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "CLK_PMV_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "CLK_PMV_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CLK_PMV_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "CLK_PMV_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "CLK_PMV_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "CLK_PMV_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CLK_PMV_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "CLK_PMV_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "CLK_PMV_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "CLK_PMV_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "CLK_PMV_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "CLK_PMV_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "CLK_PMV_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "CLK_PMV_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "CLK_PMV_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "CLK_PMV_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "CLK_PMV_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "CLK_PMV_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CLK_PMV_LH3_4", - "VBRK_LH3" - ], - [ - "CLK_PMV_LH2_4", - "VBRK_LH2" - ], - [ - "CLK_PMV_LH11_4", - "VBRK_LH11" - ], - [ - "CLK_PMV_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CLK_PMV_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CLK_PMV_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "CLK_PMV_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "CLK_PMV_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "CLK_PMV_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "CLK_PMV_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "CLK_PMV_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "CLK_PMV_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CLK_PMV_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "CLK_PMV_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "CLK_PMV_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "CLK_PMV_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "CLK_PMV_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "CLK_PMV_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CLK_PMV_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "CLK_PMV_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CLK_PMV_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CLK_PMV_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CLK_PMV_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "CLK_PMV_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CLK_PMV_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CLK_PMV_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CLK_PMV_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CLK_PMV_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CLK_PMV_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "CLK_PMV_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "CLK_PMV_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "CLK_PMV_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "CLK_PMV_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "CLK_PMV_LH1_4", - "VBRK_LH1" - ], - [ - "CLK_PMV_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CLK_PMV_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "CLK_PMV_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "CLK_PMV_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "CLK_PMV_LH7_4", - "VBRK_LH7" + "GTPE2_IMUX30_9", + "VBRK_EXT_IMUX30" ], [ - "CLK_PMV_SW4END2_4", - "VBRK_SW4END2" + "GTPE2_IMUX31_9", + "VBRK_EXT_IMUX31" ], [ - "CLK_PMV_WW4END2_4", - "VBRK_WW4END2" + "GTPE2_IMUX32_9", + "VBRK_EXT_IMUX32" ], [ - "CLK_PMV_EE4BEG1_4", - "VBRK_EE4BEG1" + "GTPE2_IMUX33_9", + "VBRK_EXT_IMUX33" ], [ - "CLK_PMV_NE4BEG3_4", - "VBRK_NE4BEG3" + "GTPE2_IMUX34_9", + "VBRK_EXT_IMUX34" ], [ - "CLK_PMV_WW2A0_4", - "VBRK_WW2A0" + "GTPE2_IMUX35_9", + "VBRK_EXT_IMUX35" ], [ - "CLK_PMV_EE2BEG1_4", - "VBRK_EE2BEG1" + "GTPE2_IMUX36_9", + "VBRK_EXT_IMUX36" ], [ - "CLK_PMV_EE4BEG2_4", - "VBRK_EE4BEG2" + "GTPE2_IMUX37_9", + "VBRK_EXT_IMUX37" ], [ - "CLK_PMV_WW4B1_4", - "VBRK_WW4B1" + "GTPE2_IMUX38_9", + "VBRK_EXT_IMUX38" ], [ - "CLK_PMV_WL1END3_4", - "VBRK_WL1END3" + "GTPE2_IMUX39_9", + "VBRK_EXT_IMUX39" ], [ - "CLK_PMV_WW4A3_4", - "VBRK_WW4A3" + "GTPE2_IMUX40_9", + "VBRK_EXT_IMUX40" ], [ - "CLK_PMV_WW4END0_4", - "VBRK_WW4END0" + "GTPE2_IMUX41_9", + "VBRK_EXT_IMUX41" ], [ - "CLK_PMV_WW2END2_4", - "VBRK_WW2END2" + "GTPE2_IMUX42_9", + "VBRK_EXT_IMUX42" ], [ - "CLK_PMV_SW4A2_4", - "VBRK_SW4A2" + "GTPE2_IMUX43_9", + "VBRK_EXT_IMUX43" ], [ - "CLK_PMV_WW2END0_4", - "VBRK_WW2END0" + "GTPE2_IMUX44_9", + "VBRK_EXT_IMUX44" ], [ - "CLK_PMV_SE2A0_4", - "VBRK_SE2A0" + "GTPE2_IMUX45_9", + "VBRK_EXT_IMUX45" ], [ - "CLK_PMV_SE4BEG2_4", - "VBRK_SE4BEG2" + "GTPE2_IMUX46_9", + "VBRK_EXT_IMUX46" ], [ - "CLK_PMV_NW2A0_4", - "VBRK_NW2A0" + "GTPE2_IMUX47_9", + "VBRK_EXT_IMUX47" ], [ - "CLK_PMV_EE2BEG3_4", - "VBRK_EE2BEG3" + "GTPE2_LOGIC_OUTS_B0_9", + "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "CLK_PMV_LH12_4", - "VBRK_LH12" + "GTPE2_LOGIC_OUTS_B1_9", + "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "CLK_PMV_SW4A0_4", - "VBRK_SW4A0" + "GTPE2_LOGIC_OUTS_B2_9", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ - "CLK_PMV_WR1END1_4", - "VBRK_WR1END1" + "GTPE2_LOGIC_OUTS_B3_9", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "CLK_PMV_NW4A2_4", - "VBRK_NW4A2" + "GTPE2_LOGIC_OUTS_B4_9", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "CLK_PMV_NW2A1_4", - "VBRK_NW2A1" + "GTPE2_LOGIC_OUTS_B5_9", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "CLK_PMV_SW2A1_4", - "VBRK_SW2A1" + "GTPE2_LOGIC_OUTS_B7_9", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "CLK_PMV_EE4C2_4", - "VBRK_EE4C2" + "GTPE2_LOGIC_OUTS_B9_9", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "CLK_PMV_EE4C0_4", - "VBRK_EE4C0" + "GTPE2_LOGIC_OUTS_B10_9", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "CLK_PMV_SE4C2_4", - "VBRK_SE4C2" + "GTPE2_LOGIC_OUTS_B12_9", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "CLK_PMV_WW4C3_4", - "VBRK_WW4C3" + "GTPE2_LOGIC_OUTS_B13_9", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "CLK_PMV_EE4A2_4", - "VBRK_EE4A2" + "GTPE2_LOGIC_OUTS_B14_9", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "CLK_PMV_LH9_4", - "VBRK_LH9" + "GTPE2_LOGIC_OUTS_B15_9", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "CLK_PMV_WW4END1_4", - "VBRK_WW4END1" + "GTPE2_LOGIC_OUTS_B16_9", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "CLK_PMV_WW4A2_4", - "VBRK_WW4A2" + "GTPE2_LOGIC_OUTS_B18_9", + "VBRK_EXT_LOGIC_OUTS_B18" ], [ - "CLK_PMV_SW4A1_4", - "VBRK_SW4A1" + "GTPE2_LOGIC_OUTS_B20_9", + "VBRK_EXT_LOGIC_OUTS_B20" ], [ - "CLK_PMV_EL1BEG1_4", - "VBRK_EL1BEG1" + "GTPE2_LOGIC_OUTS_B22_9", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "CLK_PMV_SW2A0_4", - "VBRK_SW2A0" + "GTPE2_LOGIC_OUTS_B23_9", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }, @@ -413422,60 +346570,288 @@ ], "wire_pairs": [ [ - "GTPE2_FAN0_8", - "VBRK_EXT_FAN0" + "GTPE2_BYP0_8", + "VBRK_EXT_BYP0" ], [ - "GTPE2_IMUX31_8", - "VBRK_EXT_IMUX31" + "GTPE2_BYP1_8", + "VBRK_EXT_BYP1" ], [ - "GTPE2_FAN5_8", - "VBRK_EXT_FAN5" + "GTPE2_BYP2_8", + "VBRK_EXT_BYP2" + ], + [ + "GTPE2_BYP3_8", + "VBRK_EXT_BYP3" + ], + [ + "GTPE2_BYP4_8", + "VBRK_EXT_BYP4" + ], + [ + "GTPE2_BYP5_8", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_BYP6_8", + "VBRK_EXT_BYP6" + ], + [ + "GTPE2_BYP7_8", + "VBRK_EXT_BYP7" ], [ "GTPE2_CLK0_8", "VBRK_EXT_CLK0" ], [ - "GTPE2_IMUX39_8", - "VBRK_EXT_IMUX39" + "GTPE2_CLK1_8", + "VBRK_EXT_CLK1" ], [ - "GTPE2_IMUX18_8", - "VBRK_EXT_IMUX18" + "GTPE2_CTRL0_8", + "VBRK_EXT_CTRL0" + ], + [ + "GTPE2_CTRL1_8", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_FAN0_8", + "VBRK_EXT_FAN0" + ], + [ + "GTPE2_FAN1_8", + "VBRK_EXT_FAN1" + ], + [ + "GTPE2_FAN2_8", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_FAN3_8", + "VBRK_EXT_FAN3" ], [ "GTPE2_FAN4_8", "VBRK_EXT_FAN4" ], + [ + "GTPE2_FAN5_8", + "VBRK_EXT_FAN5" + ], + [ + "GTPE2_FAN6_8", + "VBRK_EXT_FAN6" + ], + [ + "GTPE2_FAN7_8", + "VBRK_EXT_FAN7" + ], + [ + "GTPE2_IMUX0_8", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX1_8", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX2_8", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_8", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_8", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_8", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_8", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_8", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_8", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_8", + "VBRK_EXT_IMUX9" + ], [ "GTPE2_IMUX10_8", "VBRK_EXT_IMUX10" ], [ - "GTPE2_IMUX27_8", - "VBRK_EXT_IMUX27" + "GTPE2_IMUX11_8", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_8", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_8", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_8", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_8", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_8", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_8", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_8", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX19_8", + "VBRK_EXT_IMUX19" ], [ "GTPE2_IMUX20_8", "VBRK_EXT_IMUX20" ], [ - "GTPE2_LOGIC_OUTS_B15_8", - "VBRK_EXT_LOGIC_OUTS_B15" + "GTPE2_IMUX21_8", + "VBRK_EXT_IMUX21" ], [ - "GTPE2_LOGIC_OUTS_B16_8", - "VBRK_EXT_LOGIC_OUTS_B16" + "GTPE2_IMUX22_8", + "VBRK_EXT_IMUX22" ], [ - "GTPE2_LOGIC_OUTS_B9_8", - "VBRK_EXT_LOGIC_OUTS_B9" + "GTPE2_IMUX23_8", + "VBRK_EXT_IMUX23" ], [ - "GTPE2_LOGIC_OUTS_B13_8", - "VBRK_EXT_LOGIC_OUTS_B13" + "GTPE2_IMUX24_8", + "VBRK_EXT_IMUX24" + ], + [ + "GTPE2_IMUX25_8", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX26_8", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX27_8", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX28_8", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_IMUX29_8", + "VBRK_EXT_IMUX29" + ], + [ + "GTPE2_IMUX30_8", + "VBRK_EXT_IMUX30" + ], + [ + "GTPE2_IMUX31_8", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_IMUX32_8", + "VBRK_EXT_IMUX32" + ], + [ + "GTPE2_IMUX33_8", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX34_8", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_IMUX35_8", + "VBRK_EXT_IMUX35" + ], + [ + "GTPE2_IMUX36_8", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX37_8", + "VBRK_EXT_IMUX37" + ], + [ + "GTPE2_IMUX38_8", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX39_8", + "VBRK_EXT_IMUX39" + ], + [ + "GTPE2_IMUX40_8", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_IMUX41_8", + "VBRK_EXT_IMUX41" + ], + [ + "GTPE2_IMUX42_8", + "VBRK_EXT_IMUX42" + ], + [ + "GTPE2_IMUX43_8", + "VBRK_EXT_IMUX43" + ], + [ + "GTPE2_IMUX44_8", + "VBRK_EXT_IMUX44" + ], + [ + "GTPE2_IMUX45_8", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_IMUX46_8", + "VBRK_EXT_IMUX46" + ], + [ + "GTPE2_IMUX47_8", + "VBRK_EXT_IMUX47" + ], + [ + "GTPE2_LOGIC_OUTS_B0_8", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTPE2_LOGIC_OUTS_B1_8", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTPE2_LOGIC_OUTS_B2_8", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ "GTPE2_LOGIC_OUTS_B4_8", @@ -413485,289 +346861,1489 @@ "GTPE2_LOGIC_OUTS_B5_8", "VBRK_EXT_LOGIC_OUTS_B5" ], - [ - "GTPE2_IMUX28_8", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_LOGIC_OUTS_B19_8", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_IMUX8_8", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX13_8", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_LOGIC_OUTS_B21_8", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_LOGIC_OUTS_B2_8", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_LOGIC_OUTS_B14_8", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_LOGIC_OUTS_B18_8", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_IMUX42_8", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_BYP5_8", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_BYP3_8", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX11_8", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX4_8", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_BYP1_8", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX12_8", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX9_8", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_CLK1_8", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX21_8", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX29_8", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX41_8", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_LOGIC_OUTS_B17_8", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_LOGIC_OUTS_B0_8", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_IMUX19_8", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX33_8", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX3_8", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_FAN6_8", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX14_8", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX40_8", - "VBRK_EXT_IMUX40" - ], [ "GTPE2_LOGIC_OUTS_B6_8", "VBRK_EXT_LOGIC_OUTS_B6" ], - [ - "GTPE2_LOGIC_OUTS_B22_8", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_LOGIC_OUTS_B1_8", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX22_8", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX43_8", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_BYP6_8", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_FAN3_8", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX45_8", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_FAN2_8", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX26_8", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX23_8", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX6_8", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX15_8", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_FAN1_8", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX7_8", - "VBRK_EXT_IMUX7" - ], [ "GTPE2_LOGIC_OUTS_B7_8", "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "GTPE2_BYP2_8", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX32_8", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_BYP0_8", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX47_8", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX38_8", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX35_8", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX0_8", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX25_8", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_BYP4_8", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_CTRL0_8", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_IMUX37_8", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX24_8", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_IMUX30_8", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX1_8", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_LOGIC_OUTS_B23_8", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_IMUX16_8", - "VBRK_EXT_IMUX16" + "GTPE2_LOGIC_OUTS_B9_8", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ "GTPE2_LOGIC_OUTS_B12_8", "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "GTPE2_IMUX34_8", - "VBRK_EXT_IMUX34" + "GTPE2_LOGIC_OUTS_B13_8", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "GTPE2_IMUX46_8", - "VBRK_EXT_IMUX46" + "GTPE2_LOGIC_OUTS_B14_8", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "GTPE2_IMUX2_8", - "VBRK_EXT_IMUX2" + "GTPE2_LOGIC_OUTS_B15_8", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "GTPE2_CTRL1_8", - "VBRK_EXT_CTRL1" + "GTPE2_LOGIC_OUTS_B16_8", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "GTPE2_IMUX44_8", - "VBRK_EXT_IMUX44" + "GTPE2_LOGIC_OUTS_B17_8", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "GTPE2_IMUX36_8", - "VBRK_EXT_IMUX36" + "GTPE2_LOGIC_OUTS_B18_8", + "VBRK_EXT_LOGIC_OUTS_B18" ], [ - "GTPE2_IMUX5_8", - "VBRK_EXT_IMUX5" + "GTPE2_LOGIC_OUTS_B19_8", + "VBRK_EXT_LOGIC_OUTS_B19" ], [ - "GTPE2_BYP7_8", + "GTPE2_LOGIC_OUTS_B21_8", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTPE2_LOGIC_OUTS_B22_8", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTPE2_LOGIC_OUTS_B23_8", + "VBRK_EXT_LOGIC_OUTS_B23" + ] + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "tile_types": [ + "GTP_CHANNEL_1", + "VBRK_EXT" + ], + "wire_pairs": [ + [ + "GTPE2_BYP0_7", + "VBRK_EXT_BYP0" + ], + [ + "GTPE2_BYP1_7", + "VBRK_EXT_BYP1" + ], + [ + "GTPE2_BYP2_7", + "VBRK_EXT_BYP2" + ], + [ + "GTPE2_BYP3_7", + "VBRK_EXT_BYP3" + ], + [ + "GTPE2_BYP4_7", + "VBRK_EXT_BYP4" + ], + [ + "GTPE2_BYP5_7", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_BYP6_7", + "VBRK_EXT_BYP6" + ], + [ + "GTPE2_BYP7_7", "VBRK_EXT_BYP7" ], [ - "GTPE2_FAN7_8", + "GTPE2_CLK0_7", + "VBRK_EXT_CLK0" + ], + [ + "GTPE2_CLK1_7", + "VBRK_EXT_CLK1" + ], + [ + "GTPE2_CTRL0_7", + "VBRK_EXT_CTRL0" + ], + [ + "GTPE2_CTRL1_7", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_FAN0_7", + "VBRK_EXT_FAN0" + ], + [ + "GTPE2_FAN1_7", + "VBRK_EXT_FAN1" + ], + [ + "GTPE2_FAN2_7", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_FAN3_7", + "VBRK_EXT_FAN3" + ], + [ + "GTPE2_FAN4_7", + "VBRK_EXT_FAN4" + ], + [ + "GTPE2_FAN5_7", + "VBRK_EXT_FAN5" + ], + [ + "GTPE2_FAN6_7", + "VBRK_EXT_FAN6" + ], + [ + "GTPE2_FAN7_7", "VBRK_EXT_FAN7" ], [ - "GTPE2_IMUX17_8", + "GTPE2_IMUX0_7", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX1_7", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX2_7", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_7", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_7", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_7", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_7", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_7", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_7", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_7", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX10_7", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX11_7", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_7", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_7", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_7", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_7", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_7", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_7", "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_7", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX19_7", + "VBRK_EXT_IMUX19" + ], + [ + "GTPE2_IMUX20_7", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_IMUX21_7", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX22_7", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX23_7", + "VBRK_EXT_IMUX23" + ], + [ + "GTPE2_IMUX24_7", + "VBRK_EXT_IMUX24" + ], + [ + "GTPE2_IMUX25_7", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX26_7", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX27_7", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX28_7", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_IMUX29_7", + "VBRK_EXT_IMUX29" + ], + [ + "GTPE2_IMUX30_7", + "VBRK_EXT_IMUX30" + ], + [ + "GTPE2_IMUX31_7", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_IMUX32_7", + "VBRK_EXT_IMUX32" + ], + [ + "GTPE2_IMUX33_7", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX34_7", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_IMUX35_7", + "VBRK_EXT_IMUX35" + ], + [ + "GTPE2_IMUX36_7", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX37_7", + "VBRK_EXT_IMUX37" + ], + [ + "GTPE2_IMUX38_7", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX39_7", + "VBRK_EXT_IMUX39" + ], + [ + "GTPE2_IMUX40_7", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_IMUX41_7", + "VBRK_EXT_IMUX41" + ], + [ + "GTPE2_IMUX42_7", + "VBRK_EXT_IMUX42" + ], + [ + "GTPE2_IMUX43_7", + "VBRK_EXT_IMUX43" + ], + [ + "GTPE2_IMUX44_7", + "VBRK_EXT_IMUX44" + ], + [ + "GTPE2_IMUX45_7", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_IMUX46_7", + "VBRK_EXT_IMUX46" + ], + [ + "GTPE2_IMUX47_7", + "VBRK_EXT_IMUX47" + ], + [ + "GTPE2_LOGIC_OUTS_B0_7", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTPE2_LOGIC_OUTS_B1_7", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTPE2_LOGIC_OUTS_B2_7", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTPE2_LOGIC_OUTS_B3_7", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTPE2_LOGIC_OUTS_B4_7", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTPE2_LOGIC_OUTS_B5_7", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTPE2_LOGIC_OUTS_B6_7", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTPE2_LOGIC_OUTS_B7_7", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTPE2_LOGIC_OUTS_B9_7", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTPE2_LOGIC_OUTS_B12_7", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTPE2_LOGIC_OUTS_B13_7", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTPE2_LOGIC_OUTS_B14_7", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTPE2_LOGIC_OUTS_B15_7", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTPE2_LOGIC_OUTS_B16_7", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTPE2_LOGIC_OUTS_B18_7", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTPE2_LOGIC_OUTS_B19_7", + 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], + [ + "GTPE2_IMUX36_4", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX37_4", + "VBRK_EXT_IMUX37" + ], + [ + "GTPE2_IMUX38_4", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX39_4", + "VBRK_EXT_IMUX39" + ], + [ + "GTPE2_IMUX40_4", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_IMUX41_4", + "VBRK_EXT_IMUX41" + ], + [ + "GTPE2_IMUX42_4", + "VBRK_EXT_IMUX42" + ], + [ + "GTPE2_IMUX43_4", + "VBRK_EXT_IMUX43" + ], + [ + "GTPE2_IMUX44_4", + "VBRK_EXT_IMUX44" + ], + [ + "GTPE2_IMUX45_4", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_IMUX46_4", + "VBRK_EXT_IMUX46" + ], + [ + "GTPE2_IMUX47_4", + "VBRK_EXT_IMUX47" + ], + [ + "GTPE2_LOGIC_OUTS_B0_4", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTPE2_LOGIC_OUTS_B1_4", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTPE2_LOGIC_OUTS_B2_4", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTPE2_LOGIC_OUTS_B4_4", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTPE2_LOGIC_OUTS_B6_4", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTPE2_LOGIC_OUTS_B7_4", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTPE2_LOGIC_OUTS_B9_4", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTPE2_LOGIC_OUTS_B12_4", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTPE2_LOGIC_OUTS_B13_4", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTPE2_LOGIC_OUTS_B14_4", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTPE2_LOGIC_OUTS_B15_4", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTPE2_LOGIC_OUTS_B16_4", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTPE2_LOGIC_OUTS_B17_4", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTPE2_LOGIC_OUTS_B18_4", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTPE2_LOGIC_OUTS_B19_4", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTPE2_LOGIC_OUTS_B20_4", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTPE2_LOGIC_OUTS_B21_4", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTPE2_LOGIC_OUTS_B22_4", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTPE2_LOGIC_OUTS_B23_4", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }, @@ -413777,2105 +348353,1373 @@ 2 ], "tile_types": [ - "BRAM_INT_INTERFACE_L", - "BRAM_L" + "GTP_CHANNEL_1", + "VBRK_EXT" ], "wire_pairs": [ [ - "INT_INTERFACE_BRAM_UTURN_IMUX6", - "BRAM_IMUX6_UTURN_2" + "GTPE2_BYP0_3", + "VBRK_EXT_BYP0" ], [ - "INT_INTERFACE_SW2A3", - "BRAM_SW2A3_2" + "GTPE2_BYP1_3", + "VBRK_EXT_BYP1" ], [ - "INT_INTERFACE_BRAM_IMUX43", - "BRAM_IMUX43_2" + "GTPE2_BYP2_3", + "VBRK_EXT_BYP2" ], [ - "INT_INTERFACE_SE4C1", - "BRAM_SE4C1_2" + "GTPE2_BYP3_3", + "VBRK_EXT_BYP3" ], [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_2" + "GTPE2_BYP4_3", + "VBRK_EXT_BYP4" ], [ - "INT_INTERFACE_BRAM_IMUX42", - "BRAM_IMUX42_2" + "GTPE2_BYP5_3", + "VBRK_EXT_BYP5" ], [ - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "BRAM_LOGIC_OUTS_B3_2" + "GTPE2_BYP6_3", + "VBRK_EXT_BYP6" ], [ - "INT_INTERFACE_EE2A2", - "BRAM_EE2A2_2" + "GTPE2_BYP7_3", + "VBRK_EXT_BYP7" ], [ - "INT_INTERFACE_BYP0", - "BRAM_BYP0_2" + "GTPE2_CLK0_3", + "VBRK_EXT_CLK0" ], [ - "INT_INTERFACE_EE2A1", - "BRAM_EE2A1_2" + "GTPE2_CLK1_3", + "VBRK_EXT_CLK1" ], [ - "INT_INTERFACE_FAN3", - "BRAM_FAN3_2" + "GTPE2_CTRL0_3", + "VBRK_EXT_CTRL0" ], [ - "INT_INTERFACE_LH5", - "BRAM_LH5_2" + "GTPE2_CTRL1_3", + "VBRK_EXT_CTRL1" ], [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_2" + "GTPE2_FAN0_3", + "VBRK_EXT_FAN0" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX13", - "BRAM_IMUX13_UTURN_2" + "GTPE2_FAN1_3", + "VBRK_EXT_FAN1" ], [ - "INT_INTERFACE_EL1BEG2", - "BRAM_EL1BEG2_2" + "GTPE2_FAN2_3", + "VBRK_EXT_FAN2" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX16", - "BRAM_IMUX16_UTURN_2" + "GTPE2_FAN3_3", + "VBRK_EXT_FAN3" ], [ - "INT_INTERFACE_SW4END0", - "BRAM_SW4END0_2" + "GTPE2_FAN4_3", + "VBRK_EXT_FAN4" ], [ - "INT_INTERFACE_ER1BEG2", - "BRAM_ER1BEG2_2" + "GTPE2_FAN5_3", + "VBRK_EXT_FAN5" ], [ - "INT_INTERFACE_BRAM_IMUX47", - "BRAM_IMUX47_2" + "GTPE2_FAN6_3", + "VBRK_EXT_FAN6" ], [ - "INT_INTERFACE_BRAM_IMUX16", - "BRAM_IMUX16_2" + "GTPE2_FAN7_3", + "VBRK_EXT_FAN7" ], [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_2" + "GTPE2_IMUX0_3", + "VBRK_EXT_IMUX0" ], [ - "INT_INTERFACE_BRAM_IMUX20", - "BRAM_IMUX20_2" + "GTPE2_IMUX1_3", + "VBRK_EXT_IMUX1" ], [ - "INT_INTERFACE_WW4A1", - "BRAM_WW4A1_2" + "GTPE2_IMUX2_3", + "VBRK_EXT_IMUX2" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX9", - "BRAM_IMUX9_UTURN_2" + "GTPE2_IMUX3_3", + "VBRK_EXT_IMUX3" ], [ - "INT_INTERFACE_NW2A3", - "BRAM_NW2A3_2" + "GTPE2_IMUX4_3", + "VBRK_EXT_IMUX4" ], [ - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "BRAM_LOGIC_OUTS_B10_2" + "GTPE2_IMUX5_3", + "VBRK_EXT_IMUX5" ], [ - "INT_INTERFACE_LH9", - "BRAM_LH9_2" + "GTPE2_IMUX6_3", + "VBRK_EXT_IMUX6" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX47", - "BRAM_IMUX47_UTURN_2" + "GTPE2_IMUX7_3", + "VBRK_EXT_IMUX7" ], [ - "INT_INTERFACE_NW4END2", - "BRAM_NW4END2_2" + "GTPE2_IMUX8_3", + "VBRK_EXT_IMUX8" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX21", - "BRAM_IMUX21_UTURN_2" + "GTPE2_IMUX9_3", + "VBRK_EXT_IMUX9" ], [ - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "BRAM_LOGIC_OUTS_B21_2" + "GTPE2_IMUX10_3", + "VBRK_EXT_IMUX10" ], [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_2" + "GTPE2_IMUX11_3", + "VBRK_EXT_IMUX11" ], [ - "INT_INTERFACE_WR1END3", - "BRAM_WR1END3_2" + "GTPE2_IMUX12_3", + "VBRK_EXT_IMUX12" ], [ - "INT_INTERFACE_EE4A3", - "BRAM_EE4A3_2" + "GTPE2_IMUX13_3", + "VBRK_EXT_IMUX13" ], [ - "INT_INTERFACE_FAN4", - "BRAM_FAN4_2" + "GTPE2_IMUX14_3", + "VBRK_EXT_IMUX14" ], [ - "INT_INTERFACE_LH12", - "BRAM_LH12_2" + "GTPE2_IMUX15_3", + "VBRK_EXT_IMUX15" ], [ - "INT_INTERFACE_BRAM_IMUX13", - "BRAM_IMUX13_2" + "GTPE2_IMUX16_3", + "VBRK_EXT_IMUX16" ], [ - "INT_INTERFACE_BRAM_IMUX37", - "BRAM_IMUX37_2" + "GTPE2_IMUX17_3", + "VBRK_EXT_IMUX17" ], [ - "INT_INTERFACE_NE4BEG1", - "BRAM_NE4BEG1_2" + "GTPE2_IMUX18_3", + "VBRK_EXT_IMUX18" ], [ - "INT_INTERFACE_CTRL0", - "BRAM_CTRL0_2" + "GTPE2_IMUX19_3", + "VBRK_EXT_IMUX19" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX26", - "BRAM_IMUX26_UTURN_2" + "GTPE2_IMUX20_3", + "VBRK_EXT_IMUX20" ], [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_2" + "GTPE2_IMUX21_3", + "VBRK_EXT_IMUX21" ], [ - "INT_INTERFACE_EE4B1", - "BRAM_EE4B1_2" + "GTPE2_IMUX22_3", + "VBRK_EXT_IMUX22" ], [ - "INT_INTERFACE_EE4B2", - "BRAM_EE4B2_2" + "GTPE2_IMUX23_3", + "VBRK_EXT_IMUX23" ], [ - "INT_INTERFACE_NW4A0", - "BRAM_NW4A0_2" + "GTPE2_IMUX24_3", + "VBRK_EXT_IMUX24" ], [ - "INT_INTERFACE_BYP4", - "BRAM_BYP4_2" + "GTPE2_IMUX25_3", + "VBRK_EXT_IMUX25" ], [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_2" + "GTPE2_IMUX26_3", + "VBRK_EXT_IMUX26" ], [ - "INT_INTERFACE_MONITOR_N", - "BRAM_MONITOR_N_2" + "GTPE2_IMUX27_3", + "VBRK_EXT_IMUX27" ], [ - "INT_INTERFACE_WW4END1", - "BRAM_WW4END1_2" + "GTPE2_IMUX28_3", + "VBRK_EXT_IMUX28" ], [ - "INT_INTERFACE_LH3", - "BRAM_LH3_2" + "GTPE2_IMUX29_3", + "VBRK_EXT_IMUX29" ], [ - "INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_2" + "GTPE2_IMUX30_3", + "VBRK_EXT_IMUX30" ], [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_2" + "GTPE2_IMUX31_3", + "VBRK_EXT_IMUX31" ], [ - "INT_INTERFACE_BRAM_IMUX36", - "BRAM_IMUX36_2" + "GTPE2_IMUX32_3", + "VBRK_EXT_IMUX32" ], [ - "INT_INTERFACE_SW4A3", - "BRAM_SW4A3_2" + "GTPE2_IMUX33_3", + "VBRK_EXT_IMUX33" ], [ - "INT_INTERFACE_BRAM_IMUX33", - "BRAM_IMUX33_2" + "GTPE2_IMUX34_3", + "VBRK_EXT_IMUX34" ], [ - "INT_INTERFACE_SE2A1", - "BRAM_SE2A1_2" + "GTPE2_IMUX35_3", + "VBRK_EXT_IMUX35" ], [ - "INT_INTERFACE_WW2A1", - "BRAM_WW2A1_2" + "GTPE2_IMUX36_3", + "VBRK_EXT_IMUX36" ], [ - "INT_INTERFACE_NE2A3", - "BRAM_NE2A3_2" + "GTPE2_IMUX37_3", + "VBRK_EXT_IMUX37" ], [ - "INT_INTERFACE_BRAM_IMUX34", - "BRAM_IMUX34_2" + "GTPE2_IMUX38_3", + "VBRK_EXT_IMUX38" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX25", - "BRAM_IMUX25_UTURN_2" + "GTPE2_IMUX39_3", + "VBRK_EXT_IMUX39" ], [ - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "BRAM_LOGIC_OUTS_B9_2" + "GTPE2_IMUX40_3", + "VBRK_EXT_IMUX40" ], [ - "INT_INTERFACE_WW4C0", - "BRAM_WW4C0_2" + "GTPE2_IMUX41_3", + "VBRK_EXT_IMUX41" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX3", - "BRAM_IMUX3_UTURN_2" + "GTPE2_IMUX42_3", + "VBRK_EXT_IMUX42" ], [ - "INT_INTERFACE_WW2A0", - "BRAM_WW2A0_2" + "GTPE2_IMUX43_3", + "VBRK_EXT_IMUX43" ], [ - "INT_INTERFACE_WW2A2", - "BRAM_WW2A2_2" + "GTPE2_IMUX44_3", + "VBRK_EXT_IMUX44" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX24", - "BRAM_IMUX24_UTURN_2" + "GTPE2_IMUX45_3", + "VBRK_EXT_IMUX45" ], [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_2" + "GTPE2_IMUX46_3", + "VBRK_EXT_IMUX46" ], [ - "INT_INTERFACE_EE4BEG3", - "BRAM_EE4BEG3_2" + "GTPE2_IMUX47_3", + "VBRK_EXT_IMUX47" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX18", - "BRAM_IMUX18_UTURN_2" + "GTPE2_LOGIC_OUTS_B0_3", + "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX17", - "BRAM_IMUX17_UTURN_2" + "GTPE2_LOGIC_OUTS_B1_3", + "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX36", - "BRAM_IMUX36_UTURN_2" + "GTPE2_LOGIC_OUTS_B3_3", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "INT_INTERFACE_WW4B1", - "BRAM_WW4B1_2" + "GTPE2_LOGIC_OUTS_B4_3", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX38", - "BRAM_IMUX38_UTURN_2" + "GTPE2_LOGIC_OUTS_B5_3", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "INT_INTERFACE_LH4", - "BRAM_LH4_2" + "GTPE2_LOGIC_OUTS_B7_3", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "INT_INTERFACE_BRAM_IMUX32", - "BRAM_IMUX32_2" + "GTPE2_LOGIC_OUTS_B9_3", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX33", - "BRAM_IMUX33_UTURN_2" + "GTPE2_LOGIC_OUTS_B10_3", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "INT_INTERFACE_WW2END3", - "BRAM_WW2END3_2" + "GTPE2_LOGIC_OUTS_B12_3", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "INT_INTERFACE_NE2A1", - "BRAM_NE2A1_2" + "GTPE2_LOGIC_OUTS_B13_3", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "INT_INTERFACE_BRAM_IMUX0", - "BRAM_IMUX0_2" + "GTPE2_LOGIC_OUTS_B14_3", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "INT_INTERFACE_BRAM_IMUX18", - "BRAM_IMUX18_2" + "GTPE2_LOGIC_OUTS_B15_3", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "INT_INTERFACE_EE4BEG2", - "BRAM_EE4BEG2_2" + "GTPE2_LOGIC_OUTS_B16_3", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "INT_INTERFACE_BRAM_UTURN_IMUX19", - "BRAM_IMUX19_UTURN_2" + "GTPE2_LOGIC_OUTS_B17_3", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "INT_INTERFACE_BRAM_IMUX31", - "BRAM_IMUX31_2" + "GTPE2_LOGIC_OUTS_B18_3", + "VBRK_EXT_LOGIC_OUTS_B18" ], [ - "INT_INTERFACE_FAN5", - "BRAM_FAN5_2" + "GTPE2_LOGIC_OUTS_B19_3", + "VBRK_EXT_LOGIC_OUTS_B19" ], [ - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "BRAM_LOGIC_OUTS_B11_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "BRAM_LOGIC_OUTS_B12_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX5", - "BRAM_IMUX5_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "BRAM_IMUX4_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX23", - "BRAM_IMUX23_2" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "BRAM_IMUX10_UTURN_2" - ], - [ - "INT_INTERFACE_SW4A1", - "BRAM_SW4A1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX32", - "BRAM_IMUX32_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX39", - "BRAM_IMUX39_2" - ], - [ - "INT_INTERFACE_EE4C2", - "BRAM_EE4C2_2" - ], - [ - "INT_INTERFACE_SW4A0", - "BRAM_SW4A0_2" - ], - [ - "INT_INTERFACE_SE4C2", - "BRAM_SE4C2_2" - ], - [ - "INT_INTERFACE_NW2A0", - "BRAM_NW2A0_2" - ], - [ - "INT_INTERFACE_SE4C0", - "BRAM_SE4C0_2" - ], - [ - "INT_INTERFACE_NW2A1", - "BRAM_NW2A1_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "BRAM_LOGIC_OUTS_B18_2" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "BRAM_IMUX5_2" - ], - [ - "INT_INTERFACE_EE2BEG1", - "BRAM_EE2BEG1_2" - ], - [ - "INT_INTERFACE_LH11", - "BRAM_LH11_2" - ], - [ - "INT_INTERFACE_EE4A2", - "BRAM_EE4A2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX27", - "BRAM_IMUX27_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "BRAM_IMUX38_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "BRAM_LOGIC_OUTS_B6_2" - ], - [ - "INT_INTERFACE_NE4C0", - "BRAM_NE4C0_2" - ], - [ - "INT_INTERFACE_SE4BEG0", - "BRAM_SE4BEG0_2" - ], - [ - "INT_INTERFACE_EE4A1", - "BRAM_EE4A1_2" - ], - [ - "INT_INTERFACE_SE2A0", - "BRAM_SE2A0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_2" - ], - [ - "INT_INTERFACE_WW4C1", - "BRAM_WW4C1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX11", - "BRAM_IMUX11_2" - ], - [ - "INT_INTERFACE_EE2BEG0", - "BRAM_EE2BEG0_2" - ], - [ - "INT_INTERFACE_WW4C2", - "BRAM_WW4C2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX35", - "BRAM_IMUX35_UTURN_2" - ], - [ - "INT_INTERFACE_LH6", - "BRAM_LH6_2" - ], - [ - "INT_INTERFACE_NE4BEG0", - "BRAM_NE4BEG0_2" - ], - [ - "INT_INTERFACE_WL1END0", - "BRAM_WL1END0_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX20", - "BRAM_IMUX20_UTURN_2" - ], - [ - "INT_INTERFACE_BYP6", - "BRAM_BYP6_2" - ], - [ - "INT_INTERFACE_EE2BEG2", - "BRAM_EE2BEG2_2" - ], - [ - "INT_INTERFACE_WR1END1", - "BRAM_WR1END1_2" - ], - [ - "INT_INTERFACE_NE2A0", - "BRAM_NE2A0_2" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_2" - ], - [ - "INT_INTERFACE_LH1", - "BRAM_LH1_2" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_2" - ], - [ - "INT_INTERFACE_FAN0", - "BRAM_FAN0_2" - ], - [ - "INT_INTERFACE_WW4C3", - "BRAM_WW4C3_2" - ], - [ - "INT_INTERFACE_WW4A3", - "BRAM_WW4A3_2" - ], - [ - "INT_INTERFACE_SW4A2", - "BRAM_SW4A2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "BRAM_LOGIC_OUTS_B8_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "BRAM_LOGIC_OUTS_B17_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX30", - "BRAM_IMUX30_UTURN_2" - ], - [ - "INT_INTERFACE_NE4C3", - "BRAM_NE4C3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX40", - "BRAM_IMUX40_UTURN_2" - ], - [ - "INT_INTERFACE_NE4BEG3", - "BRAM_NE4BEG3_2" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_2" - ], - [ - "INT_INTERFACE_EE4C3", - "BRAM_EE4C3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_2" - ], - [ - "INT_INTERFACE_LH7", - "BRAM_LH7_2" - ], - [ - "INT_INTERFACE_ER1BEG1", - "BRAM_ER1BEG1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX44", - "BRAM_IMUX44_UTURN_2" - ], - [ - "INT_INTERFACE_NE2A2", - "BRAM_NE2A2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX37", - "BRAM_IMUX37_UTURN_2" - ], - [ - "INT_INTERFACE_BYP3", - "BRAM_BYP3_2" - ], - [ - "INT_INTERFACE_EL1BEG0", - "BRAM_EL1BEG0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "BRAM_LOGIC_OUTS_B13_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX1", - "BRAM_IMUX1_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX34", - "BRAM_IMUX34_UTURN_2" - ], - [ - "INT_INTERFACE_WL1END1", - "BRAM_WL1END1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX39", - "BRAM_IMUX39_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX0", - "BRAM_IMUX0_UTURN_2" - ], - [ - "INT_INTERFACE_WW2END2", - "BRAM_WW2END2_2" - ], - [ - "INT_INTERFACE_NE4C1", - "BRAM_NE4C1_2" - ], - [ - "INT_INTERFACE_EE2A0", - "BRAM_EE2A0_2" - ], - [ - "INT_INTERFACE_SW4END1", - "BRAM_SW4END1_2" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_2" - ], - [ - "INT_INTERFACE_SE4BEG1", - "BRAM_SE4BEG1_2" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX41", - "BRAM_IMUX41_UTURN_2" - ], - [ - "INT_INTERFACE_EE4B3", - "BRAM_EE4B3_2" - ], - [ - "INT_INTERFACE_EE4C1", - "BRAM_EE4C1_2" - ], - [ - "INT_INTERFACE_NW4END3", - "BRAM_NW4END3_2" - ], - [ - "INT_INTERFACE_NW4A1", - "BRAM_NW4A1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_2" - ], - [ - "INT_INTERFACE_WW4END2", - "BRAM_WW4END2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "BRAM_LOGIC_OUTS_B16_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX11", - "BRAM_IMUX11_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX22", - "BRAM_IMUX22_2" - ], - [ - "INT_INTERFACE_FAN7", - "BRAM_FAN7_2" - ], - [ - "INT_INTERFACE_CTRL1", - "BRAM_CTRL1_2" - ], - [ - "INT_INTERFACE_SE4BEG3", - "BRAM_SE4BEG3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX29", - "BRAM_IMUX29_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "BRAM_IMUX25_2" - ], - [ - "INT_INTERFACE_EE4C0", - "BRAM_EE4C0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX10", - "BRAM_IMUX10_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX42", - "BRAM_IMUX42_UTURN_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "BRAM_LOGIC_OUTS_B20_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "BRAM_IMUX6_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX29", - "BRAM_IMUX29_2" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX31", - "BRAM_IMUX31_UTURN_2" - ], - [ - "INT_INTERFACE_WW2END1", - "BRAM_WW2END1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX23", - "BRAM_IMUX23_UTURN_2" - ], - [ - "INT_INTERFACE_NW4END0", - "BRAM_NW4END0_2" - ], - [ - "INT_INTERFACE_FAN6", - "BRAM_FAN6_2" - ], - [ - "INT_INTERFACE_WL1END2", - "BRAM_WL1END2_2" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "BRAM_LOGIC_OUTS_B2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "BRAM_LOGIC_OUTS_B19_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX27", - "BRAM_IMUX27_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "BRAM_LOGIC_OUTS_B15_2" - ], - [ - "INT_INTERFACE_WW4B0", - "BRAM_WW4B0_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX14", - "BRAM_IMUX14_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX46", - "BRAM_IMUX46_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "BRAM_IMUX3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX12", - "BRAM_IMUX12_UTURN_2" - ], - [ - "INT_INTERFACE_WL1END3", - "BRAM_WL1END3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX35", - "BRAM_IMUX35_2" - ], - [ - "INT_INTERFACE_SE2A3", - "BRAM_SE2A3_2" - ], - [ - "INT_INTERFACE_NW2A2", - "BRAM_NW2A2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "BRAM_LOGIC_OUTS_B23_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_2" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_2" - ], - [ - "INT_INTERFACE_NE4BEG2", - "BRAM_NE4BEG2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX45", - "BRAM_IMUX45_2" - ], - [ - "INT_INTERFACE_ER1BEG3", - "BRAM_ER1BEG3_2" - ], - [ - "INT_INTERFACE_EE4BEG1", - "BRAM_EE4BEG1_2" - ], - [ - "INT_INTERFACE_FAN2", - "BRAM_FAN2_2" - ], - [ - "INT_INTERFACE_WW4B2", - "BRAM_WW4B2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX2", - "BRAM_IMUX2_UTURN_2" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_2" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX43", - "BRAM_IMUX43_UTURN_2" - ], - [ - "INT_INTERFACE_MONITOR_P", - "BRAM_MONITOR_P_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX45", - "BRAM_IMUX45_UTURN_2" - ], - [ - "INT_INTERFACE_NE4C2", - "BRAM_NE4C2_2" - ], - [ - "INT_INTERFACE_BYP2", - "BRAM_BYP2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "BRAM_IMUX1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "BRAM_IMUX17_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX15", - "BRAM_IMUX15_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX22", - "BRAM_IMUX22_UTURN_2" - ], - [ - "INT_INTERFACE_SW2A2", - "BRAM_SW2A2_2" - ], - [ - "INT_INTERFACE_EE4BEG0", - "BRAM_EE4BEG0_2" - ], - [ - "INT_INTERFACE_EE2A3", - "BRAM_EE2A3_2" - ], - [ - "INT_INTERFACE_EL1BEG1", - "BRAM_EL1BEG1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B14", - "BRAM_LOGIC_OUTS_B14_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX28", - "BRAM_IMUX28_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX8", - "BRAM_IMUX8_UTURN_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "BRAM_LOGIC_OUTS_B4_2" - ], - [ - "INT_INTERFACE_SE4C3", - "BRAM_SE4C3_2" - ], - [ - "INT_INTERFACE_LH2", - "BRAM_LH2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_2" - ], - [ - "INT_INTERFACE_CLK0", - "BRAM_CLK0_2" - ], - [ - "INT_INTERFACE_NW4A2", - "BRAM_NW4A2_2" - ], - [ - "INT_INTERFACE_SE2A2", - "BRAM_SE2A2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX4", - "BRAM_IMUX4_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX7", - "BRAM_IMUX7_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "BRAM_IMUX8_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX26", - "BRAM_IMUX26_2" - ], - [ - "INT_INTERFACE_WW2A3", - "BRAM_WW2A3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX9", - "BRAM_IMUX9_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "BRAM_LOGIC_OUTS_B5_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX24", - "BRAM_IMUX24_2" - ], - [ - "INT_INTERFACE_WW4END3", - "BRAM_WW4END3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX19", - "BRAM_IMUX19_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX7", - "BRAM_IMUX7_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "BRAM_LOGIC_OUTS_B22_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "BRAM_LOGIC_OUTS_B0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX30", - "BRAM_IMUX30_2" - ], - [ - "INT_INTERFACE_BYP1", - "BRAM_BYP1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX40", - "BRAM_IMUX40_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "BRAM_LOGIC_OUTS_B7_2" - ], - [ - "INT_INTERFACE_EE2BEG3", - "BRAM_EE2BEG3_2" - ], - [ - "INT_INTERFACE_SW4END2", - "BRAM_SW4END2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "BRAM_IMUX44_2" - ], - [ - "INT_INTERFACE_BYP5", - "BRAM_BYP5_2" - ], - [ - "INT_INTERFACE_ER1BEG0", - "BRAM_ER1BEG0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "BRAM_LOGIC_OUTS_B1_2" - ], - [ - "INT_INTERFACE_EE4A0", - "BRAM_EE4A0_2" + "GTPE2_LOGIC_OUTS_B22_3", + "VBRK_EXT_LOGIC_OUTS_B22" ] ] }, { "grid_deltas": [ -1, - 0 + 3 ], "tile_types": [ - "CLBLL_L", - "CLBLM_R" + "GTP_CHANNEL_1", + "VBRK_EXT" ], "wire_pairs": [ [ - "CLBLL_EE2BEG0", - "CLBLM_EE2BEG0" + "GTPE2_BYP0_2", + "VBRK_EXT_BYP0" ], [ - "CLBLL_EE2BEG2", - "CLBLM_EE2BEG2" + "GTPE2_BYP1_2", + "VBRK_EXT_BYP1" ], [ - "CLBLL_SE4BEG1", - "CLBLM_SE4BEG1" + "GTPE2_BYP2_2", + "VBRK_EXT_BYP2" ], [ - "CLBLL_SW4END2", - "CLBLM_SW4END2" + "GTPE2_BYP3_2", + "VBRK_EXT_BYP3" ], [ - "CLBLL_NE4C1", - "CLBLM_NE4C1" + "GTPE2_BYP4_2", + "VBRK_EXT_BYP4" ], [ - "CLBLL_SE2A0", - "CLBLM_SE2A0" + "GTPE2_BYP5_2", + "VBRK_EXT_BYP5" ], [ - "CLBLL_SE2A3", - "CLBLM_SE2A3" + "GTPE2_BYP6_2", + "VBRK_EXT_BYP6" ], [ - "CLBLL_EE4BEG0", - "CLBLM_EE4BEG0" + "GTPE2_BYP7_2", + "VBRK_EXT_BYP7" ], [ - "CLBLL_WW2A1", - "CLBLM_WW2A1" + "GTPE2_CLK0_2", + "VBRK_EXT_CLK0" ], [ - "CLBLL_MONITOR_P", - "CLBLM_MONITOR_P" + "GTPE2_CLK1_2", + "VBRK_EXT_CLK1" ], [ - "CLBLL_WW4B2", - "CLBLM_WW4B2" + "GTPE2_CTRL0_2", + "VBRK_EXT_CTRL0" ], [ - "CLBLL_NW4END1", - "CLBLM_NW4END1" + "GTPE2_CTRL1_2", + "VBRK_EXT_CTRL1" ], [ - "CLBLL_SW4A1", - "CLBLM_SW4A1" + "GTPE2_FAN0_2", + "VBRK_EXT_FAN0" ], [ - "CLBLL_WL1END1", - "CLBLM_WL1END1" + "GTPE2_FAN1_2", + "VBRK_EXT_FAN1" ], [ - "CLBLL_EE4B3", - "CLBLM_EE4B3" + "GTPE2_FAN2_2", + "VBRK_EXT_FAN2" ], [ - "CLBLL_EE2A3", - "CLBLM_EE2A3" + "GTPE2_FAN3_2", + "VBRK_EXT_FAN3" ], [ - "CLBLL_WW4C3", - "CLBLM_WW4C3" + "GTPE2_FAN4_2", + "VBRK_EXT_FAN4" ], [ - "CLBLL_WR1END1", - "CLBLM_WR1END1" + "GTPE2_FAN5_2", + "VBRK_EXT_FAN5" ], [ - "CLBLL_WR1END0", - "CLBLM_WR1END0" + "GTPE2_FAN6_2", + "VBRK_EXT_FAN6" ], [ - "CLBLL_WR1END3", - "CLBLM_WR1END3" + "GTPE2_FAN7_2", + "VBRK_EXT_FAN7" ], [ - "CLBLL_NW2A0", - "CLBLM_NW2A0" + "GTPE2_IMUX0_2", + "VBRK_EXT_IMUX0" ], [ - "CLBLL_WW2A3", - "CLBLM_WW2A3" + "GTPE2_IMUX1_2", + "VBRK_EXT_IMUX1" ], [ - "CLBLL_NE4C2", - "CLBLM_NE4C2" + "GTPE2_IMUX2_2", + "VBRK_EXT_IMUX2" ], [ - "CLBLL_EE2A2", - "CLBLM_EE2A2" + "GTPE2_IMUX3_2", + "VBRK_EXT_IMUX3" ], [ - "CLBLL_SW4A3", - "CLBLM_SW4A3" + "GTPE2_IMUX4_2", + "VBRK_EXT_IMUX4" ], [ - "CLBLL_SE4BEG0", - "CLBLM_SE4BEG0" + "GTPE2_IMUX5_2", + "VBRK_EXT_IMUX5" ], [ - "CLBLL_WW4C1", - "CLBLM_WW4C1" + "GTPE2_IMUX6_2", + "VBRK_EXT_IMUX6" ], [ - "CLBLL_SE4C0", - "CLBLM_SE4C0" + "GTPE2_IMUX7_2", + "VBRK_EXT_IMUX7" ], [ - "CLBLL_NW4A1", - "CLBLM_NW4A1" + "GTPE2_IMUX8_2", + "VBRK_EXT_IMUX8" ], [ - "CLBLL_EE2BEG1", - "CLBLM_EE2BEG1" + "GTPE2_IMUX9_2", + "VBRK_EXT_IMUX9" ], [ - "CLBLL_WW2A0", - "CLBLM_WW2A0" + "GTPE2_IMUX10_2", + "VBRK_EXT_IMUX10" ], [ - "CLBLL_LH12", - "CLBLM_LH12" + "GTPE2_IMUX11_2", + "VBRK_EXT_IMUX11" ], [ - "CLBLL_EE4B2", - "CLBLM_EE4B2" + "GTPE2_IMUX12_2", + "VBRK_EXT_IMUX12" ], [ - "CLBLL_WW4B1", - "CLBLM_WW4B1" + "GTPE2_IMUX13_2", + "VBRK_EXT_IMUX13" ], [ - "CLBLL_NW4A0", - "CLBLM_NW4A0" + "GTPE2_IMUX14_2", + "VBRK_EXT_IMUX14" ], [ - "CLBLL_SW4END1", - "CLBLM_SW4END1" + "GTPE2_IMUX15_2", + "VBRK_EXT_IMUX15" ], [ - "CLBLL_NE2A0", - "CLBLM_NE2A0" + "GTPE2_IMUX16_2", + "VBRK_EXT_IMUX16" ], [ - "CLBLL_MONITOR_N", - "CLBLM_MONITOR_N" + "GTPE2_IMUX17_2", + "VBRK_EXT_IMUX17" ], [ - "CLBLL_NE4BEG0", - "CLBLM_NE4BEG0" + "GTPE2_IMUX18_2", + "VBRK_EXT_IMUX18" ], [ - "CLBLL_NW2A1", - "CLBLM_NW2A1" + "GTPE2_IMUX19_2", + "VBRK_EXT_IMUX19" ], [ - "CLBLL_LH11", - "CLBLM_LH11" + "GTPE2_IMUX20_2", + "VBRK_EXT_IMUX20" ], [ - "CLBLL_EE4B0", - "CLBLM_EE4B0" + "GTPE2_IMUX21_2", + "VBRK_EXT_IMUX21" ], [ - "CLBLL_SW2A0", - "CLBLM_SW2A0" + "GTPE2_IMUX22_2", + "VBRK_EXT_IMUX22" ], [ - "CLBLL_WW2END2", - "CLBLM_WW2END2" + "GTPE2_IMUX23_2", + "VBRK_EXT_IMUX23" ], [ - "CLBLL_SE2A1", - "CLBLM_SE2A1" + "GTPE2_IMUX24_2", + "VBRK_EXT_IMUX24" ], [ - "CLBLL_NW2A3", - "CLBLM_NW2A3" + "GTPE2_IMUX25_2", + "VBRK_EXT_IMUX25" ], [ - "CLBLL_NE4BEG3", - "CLBLM_NE4BEG3" + "GTPE2_IMUX26_2", + "VBRK_EXT_IMUX26" ], [ - "CLBLL_WW4END3", - "CLBLM_WW4END3" + "GTPE2_IMUX27_2", + "VBRK_EXT_IMUX27" ], [ - "CLBLL_SW2A3", - "CLBLM_SW2A3" + "GTPE2_IMUX28_2", + "VBRK_EXT_IMUX28" ], [ - "CLBLL_EE4C3", - "CLBLM_EE4C3" + "GTPE2_IMUX29_2", + "VBRK_EXT_IMUX29" ], [ - "CLBLL_WW4END1", - "CLBLM_WW4END1" + "GTPE2_IMUX30_2", + "VBRK_EXT_IMUX30" ], [ - "CLBLL_EL1BEG2", - "CLBLM_EL1BEG2" + "GTPE2_IMUX31_2", + "VBRK_EXT_IMUX31" ], [ - "CLBLL_EE4C2", - "CLBLM_EE4C2" + "GTPE2_IMUX32_2", + "VBRK_EXT_IMUX32" ], [ - "CLBLL_SW4END0", - "CLBLM_SW4END0" + "GTPE2_IMUX33_2", + "VBRK_EXT_IMUX33" ], [ - "CLBLL_EE4BEG3", - "CLBLM_EE4BEG3" + "GTPE2_IMUX34_2", + "VBRK_EXT_IMUX34" ], [ - "CLBLL_ER1BEG0", - "CLBLM_ER1BEG0" + "GTPE2_IMUX35_2", + "VBRK_EXT_IMUX35" ], [ - "CLBLL_NE4BEG2", - "CLBLM_NE4BEG2" + "GTPE2_IMUX36_2", + "VBRK_EXT_IMUX36" ], [ - "CLBLL_EE4A3", - "CLBLM_EE4A3" + "GTPE2_IMUX37_2", + "VBRK_EXT_IMUX37" ], [ - "CLBLL_ER1BEG3", - "CLBLM_ER1BEG3" + "GTPE2_IMUX38_2", + "VBRK_EXT_IMUX38" ], [ - "CLBLL_EE4A2", - "CLBLM_EE4A2" + "GTPE2_IMUX39_2", + "VBRK_EXT_IMUX39" ], [ - "CLBLL_WW2END1", - "CLBLM_WW2END1" + "GTPE2_IMUX40_2", + "VBRK_EXT_IMUX40" ], [ - "CLBLL_NE2A2", - "CLBLM_NE2A2" + "GTPE2_IMUX41_2", + "VBRK_EXT_IMUX41" ], [ - "CLBLL_EE4C0", - "CLBLM_EE4C0" + "GTPE2_IMUX42_2", + "VBRK_EXT_IMUX42" ], [ - "CLBLL_WW4C2", - "CLBLM_WW4C2" + "GTPE2_IMUX43_2", + "VBRK_EXT_IMUX43" ], [ - "CLBLL_WW2END3", - "CLBLM_WW2END3" + "GTPE2_IMUX44_2", + "VBRK_EXT_IMUX44" ], [ - "CLBLL_LH10", - "CLBLM_LH10" + "GTPE2_IMUX45_2", + "VBRK_EXT_IMUX45" ], [ - "CLBLL_LH6", - "CLBLM_LH6" + "GTPE2_IMUX46_2", + "VBRK_EXT_IMUX46" ], [ - "CLBLL_WW4C0", - "CLBLM_WW4C0" + "GTPE2_IMUX47_2", + "VBRK_EXT_IMUX47" ], [ - "CLBLL_SW4A0", - "CLBLM_SW4A0" + "GTPE2_LOGIC_OUTS_B3_2", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "CLBLL_NW4END3", - "CLBLM_NW4END3" + "GTPE2_LOGIC_OUTS_B6_2", + "VBRK_EXT_LOGIC_OUTS_B6" ], [ - "CLBLL_SE4C1", - "CLBLM_SE4C1" + "GTPE2_LOGIC_OUTS_B7_2", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "CLBLL_LH2", - "CLBLM_LH2" + "GTPE2_LOGIC_OUTS_B9_2", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "CLBLL_NE2A1", - "CLBLM_NE2A1" + "GTPE2_LOGIC_OUTS_B12_2", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "CLBLL_NE4C0", - "CLBLM_NE4C0" + "GTPE2_LOGIC_OUTS_B13_2", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "CLBLL_SW4A2", - "CLBLM_SW4A2" + "GTPE2_LOGIC_OUTS_B14_2", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "CLBLL_WW4A1", - "CLBLM_WW4A1" + "GTPE2_LOGIC_OUTS_B15_2", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "CLBLL_ER1BEG1", - "CLBLM_ER1BEG1" + "GTPE2_LOGIC_OUTS_B16_2", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "CLBLL_SE4BEG3", - "CLBLM_SE4BEG3" + "GTPE2_LOGIC_OUTS_B17_2", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "CLBLL_WL1END2", - "CLBLM_WL1END2" + "GTPE2_LOGIC_OUTS_B18_2", + "VBRK_EXT_LOGIC_OUTS_B18" ], [ - "CLBLL_WW4B0", - "CLBLM_WW4B0" + "GTPE2_LOGIC_OUTS_B19_2", + "VBRK_EXT_LOGIC_OUTS_B19" ], [ - "CLBLL_NW4A2", - "CLBLM_NW4A2" + "GTPE2_LOGIC_OUTS_B20_2", + "VBRK_EXT_LOGIC_OUTS_B20" ], [ - "CLBLL_ER1BEG2", - "CLBLM_ER1BEG2" - ], - [ - "CLBLL_EE4A1", - "CLBLM_EE4A1" - ], - [ - "CLBLL_LH8", - "CLBLM_LH8" - ], - [ - "CLBLL_NW4A3", - "CLBLM_NW4A3" - ], - [ - "CLBLL_EE4A0", - "CLBLM_EE4A0" - ], - [ - "CLBLL_EE4C1", - "CLBLM_EE4C1" - ], - [ - "CLBLL_EL1BEG3", - "CLBLM_EL1BEG3" - ], - [ - "CLBLL_EL1BEG1", - "CLBLM_EL1BEG1" - ], - [ - "CLBLL_SE4C3", - "CLBLM_SE4C3" - ], - [ - "CLBLL_SW2A2", - "CLBLM_SW2A2" - ], - [ - "CLBLL_WW4A2", - "CLBLM_WW4A2" - ], - [ - "CLBLL_EE4BEG1", - "CLBLM_EE4BEG1" - ], - [ - "CLBLL_EE2BEG3", - "CLBLM_EE2BEG3" - ], - [ - "CLBLL_LH5", - "CLBLM_LH5" - ], - [ - "CLBLL_NE4C3", - "CLBLM_NE4C3" - ], - [ - "CLBLL_WW4A3", - "CLBLM_WW4A3" - ], - [ - "CLBLL_EE4BEG2", - "CLBLM_EE4BEG2" - ], - [ - "CLBLL_WL1END3", - "CLBLM_WL1END3" - ], - [ - "CLBLL_SE2A2", - "CLBLM_SE2A2" - ], - [ - "CLBLL_EL1BEG0", - "CLBLM_EL1BEG0" - ], - [ - "CLBLL_NE2A3", - "CLBLM_NE2A3" - ], - [ - "CLBLL_LH7", - "CLBLM_LH7" - ], - [ - "CLBLL_LH1", - "CLBLM_LH1" - ], - [ - "CLBLL_EE4B1", - "CLBLM_EE4B1" - ], - [ - "CLBLL_SE4C2", - "CLBLM_SE4C2" - ], - [ - "CLBLL_WW2END0", - "CLBLM_WW2END0" - ], - [ - "CLBLL_LH9", - "CLBLM_LH9" - ], - [ - "CLBLL_WW4END2", - "CLBLM_WW4END2" - ], - [ - "CLBLL_LH4", - "CLBLM_LH4" - ], - [ - "CLBLL_WR1END2", - "CLBLM_WR1END2" - ], - [ - "CLBLL_EE2A1", - "CLBLM_EE2A1" - ], - [ - "CLBLL_WW4A0", - "CLBLM_WW4A0" - ], - [ - "CLBLL_EE2A0", - "CLBLM_EE2A0" - ], - [ - "CLBLL_SW4END3", - "CLBLM_SW4END3" - ], - [ - "CLBLL_NW4END2", - "CLBLM_NW4END2" - ], - [ - "CLBLL_NE4BEG1", - "CLBLM_NE4BEG1" - ], - [ - "CLBLL_WW2A2", - "CLBLM_WW2A2" - ], - [ - "CLBLL_SW2A1", - "CLBLM_SW2A1" - ], - [ - "CLBLL_NW4END0", - "CLBLM_NW4END0" - ], - [ - "CLBLL_NW2A2", - "CLBLM_NW2A2" - ], - [ - "CLBLL_LH3", - "CLBLM_LH3" - ], - [ - "CLBLL_SE4BEG2", - "CLBLM_SE4BEG2" - ], - [ - "CLBLL_WW4B3", - "CLBLM_WW4B3" - ], - [ - "CLBLL_WW4END0", - "CLBLM_WW4END0" - ], - [ - "CLBLL_WL1END0", - "CLBLM_WL1END0" + "GTPE2_LOGIC_OUTS_B22_2", + "VBRK_EXT_LOGIC_OUTS_B22" ] ] }, { "grid_deltas": [ -1, - 0 + 4 ], "tile_types": [ - "CLBLL_L", - "VBRK" + "GTP_CHANNEL_1", + "VBRK_EXT" ], "wire_pairs": [ [ - "CLBLL_WW4B2", - "VBRK_WW4B2" + "GTPE2_BYP0_1", + "VBRK_EXT_BYP0" ], [ - "CLBLL_WL1END0", - "VBRK_WL1END0" + "GTPE2_BYP1_1", + "VBRK_EXT_BYP1" ], [ - "CLBLL_WW2END2", - "VBRK_WW2END2" + "GTPE2_BYP2_1", + "VBRK_EXT_BYP2" ], [ - "CLBLL_SW4END2", - "VBRK_SW4END2" + "GTPE2_BYP3_1", + "VBRK_EXT_BYP3" ], [ - "CLBLL_SE4BEG1", - "VBRK_SE4BEG1" + "GTPE2_BYP4_1", + "VBRK_EXT_BYP4" ], [ - "CLBLL_EE2BEG1", - "VBRK_EE2BEG1" + "GTPE2_BYP5_1", + "VBRK_EXT_BYP5" ], [ - "CLBLL_NE2A3", - "VBRK_NE2A3" + "GTPE2_BYP6_1", + "VBRK_EXT_BYP6" ], [ - "CLBLL_EE4A1", - "VBRK_EE4A1" + "GTPE2_BYP7_1", + "VBRK_EXT_BYP7" ], [ - "CLBLL_MONITOR_P", - "VBRK_MONITOR_P" + "GTPE2_CLK0_1", + "VBRK_EXT_CLK0" ], [ - "CLBLL_WW4END1", - "VBRK_WW4END1" + "GTPE2_CLK1_1", + "VBRK_EXT_CLK1" ], [ - "CLBLL_EE4C1", - "VBRK_EE4C1" + "GTPE2_CTRL0_1", + "VBRK_EXT_CTRL0" ], [ - "CLBLL_WL1END2", - "VBRK_WL1END2" + "GTPE2_CTRL1_1", + "VBRK_EXT_CTRL1" ], [ - "CLBLL_NE4C0", - "VBRK_NE4C0" + "GTPE2_FAN0_1", + "VBRK_EXT_FAN0" ], [ - "CLBLL_NW4END3", - "VBRK_NW4END3" + "GTPE2_FAN1_1", + "VBRK_EXT_FAN1" ], [ - "CLBLL_WW4C3", - "VBRK_WW4C3" + "GTPE2_FAN2_1", + "VBRK_EXT_FAN2" ], [ - "CLBLL_WR1END1", - "VBRK_WR1END1" + "GTPE2_FAN3_1", + "VBRK_EXT_FAN3" ], [ - "CLBLL_ER1BEG1", - "VBRK_ER1BEG1" + "GTPE2_FAN4_1", + "VBRK_EXT_FAN4" ], [ - "CLBLL_NW4A1", - "VBRK_NW4A1" + "GTPE2_FAN5_1", + "VBRK_EXT_FAN5" ], [ - "CLBLL_SE4BEG3", - "VBRK_SE4BEG3" + "GTPE2_FAN6_1", + "VBRK_EXT_FAN6" ], [ - "CLBLL_NE4BEG3", - "VBRK_NE4BEG3" + "GTPE2_FAN7_1", + "VBRK_EXT_FAN7" ], [ - "CLBLL_NW4A0", - "VBRK_NW4A0" + "GTPE2_IMUX0_1", + "VBRK_EXT_IMUX0" ], [ - "CLBLL_SW4A3", - "VBRK_SW4A3" + "GTPE2_IMUX1_1", + "VBRK_EXT_IMUX1" ], [ - "CLBLL_SE4C0", - "VBRK_SE4C0" + "GTPE2_IMUX2_1", + "VBRK_EXT_IMUX2" ], [ - "CLBLL_WW2END3", - "VBRK_WW2END3" + "GTPE2_IMUX3_1", + "VBRK_EXT_IMUX3" ], [ - "CLBLL_WW4END0", - "VBRK_WW4END0" + "GTPE2_IMUX4_1", + "VBRK_EXT_IMUX4" ], [ - "CLBLL_EE4B3", - "VBRK_EE4B3" + "GTPE2_IMUX5_1", + "VBRK_EXT_IMUX5" ], [ - "CLBLL_EE4A2", - "VBRK_EE4A2" + "GTPE2_IMUX6_1", + "VBRK_EXT_IMUX6" ], [ - "CLBLL_WW4A2", - "VBRK_WW4A2" + "GTPE2_IMUX7_1", + "VBRK_EXT_IMUX7" ], [ - "CLBLL_WW4END2", - "VBRK_WW4END2" + "GTPE2_IMUX8_1", + "VBRK_EXT_IMUX8" ], [ - "CLBLL_ER1BEG0", - "VBRK_ER1BEG0" + "GTPE2_IMUX9_1", + "VBRK_EXT_IMUX9" ], [ - "CLBLL_WR1END3", - "VBRK_WR1END3" + "GTPE2_IMUX10_1", + "VBRK_EXT_IMUX10" ], [ - "CLBLL_EE2BEG0", - "VBRK_EE2BEG0" + "GTPE2_IMUX11_1", + "VBRK_EXT_IMUX11" ], [ - "CLBLL_NW2A1", - "VBRK_NW2A1" + "GTPE2_IMUX12_1", + "VBRK_EXT_IMUX12" ], [ - "CLBLL_NW2A0", - "VBRK_NW2A0" + "GTPE2_IMUX13_1", + "VBRK_EXT_IMUX13" ], [ - "CLBLL_LH2", - "VBRK_LH2" + "GTPE2_IMUX14_1", + "VBRK_EXT_IMUX14" ], [ - "CLBLL_WW2END1", - "VBRK_WW2END1" + "GTPE2_IMUX15_1", + "VBRK_EXT_IMUX15" ], [ - "CLBLL_WW4C1", - "VBRK_WW4C1" + "GTPE2_IMUX16_1", + "VBRK_EXT_IMUX16" ], [ - "CLBLL_EE2A3", - "VBRK_EE2A3" + "GTPE2_IMUX17_1", + "VBRK_EXT_IMUX17" ], [ - "CLBLL_WW4A1", - "VBRK_WW4A1" + "GTPE2_IMUX18_1", + "VBRK_EXT_IMUX18" ], [ - "CLBLL_NW2A3", - "VBRK_NW2A3" + "GTPE2_IMUX19_1", + "VBRK_EXT_IMUX19" ], [ - "CLBLL_SE2A1", - "VBRK_SE2A1" + "GTPE2_IMUX20_1", + "VBRK_EXT_IMUX20" ], [ - "CLBLL_SW4END1", - "VBRK_SW4END1" + "GTPE2_IMUX21_1", + "VBRK_EXT_IMUX21" ], [ - "CLBLL_EL1BEG1", - "VBRK_EL1BEG1" + "GTPE2_IMUX22_1", + "VBRK_EXT_IMUX22" ], [ - "CLBLL_WW2A0", - "VBRK_WW2A0" + "GTPE2_IMUX23_1", + "VBRK_EXT_IMUX23" ], [ - "CLBLL_LH7", - "VBRK_LH7" + "GTPE2_IMUX24_1", + "VBRK_EXT_IMUX24" ], [ - "CLBLL_WW4B3", - "VBRK_WW4B3" + "GTPE2_IMUX25_1", + "VBRK_EXT_IMUX25" ], [ - "CLBLL_SE4C2", - "VBRK_SE4C2" + "GTPE2_IMUX26_1", + "VBRK_EXT_IMUX26" ], [ - "CLBLL_LH11", - "VBRK_LH11" + "GTPE2_IMUX27_1", + "VBRK_EXT_IMUX27" ], [ - "CLBLL_EE2A0", - "VBRK_EE2A0" + "GTPE2_IMUX28_1", + "VBRK_EXT_IMUX28" ], [ - "CLBLL_SW4END0", - "VBRK_SW4END0" + "GTPE2_IMUX29_1", + "VBRK_EXT_IMUX29" ], [ - "CLBLL_LH5", - "VBRK_LH5" + "GTPE2_IMUX30_1", + "VBRK_EXT_IMUX30" ], [ - "CLBLL_EE4C0", - "VBRK_EE4C0" + "GTPE2_IMUX31_1", + "VBRK_EXT_IMUX31" ], [ - "CLBLL_LH8", - "VBRK_LH8" + "GTPE2_IMUX32_1", + "VBRK_EXT_IMUX32" ], [ - "CLBLL_EE4B1", - "VBRK_EE4B1" + "GTPE2_IMUX33_1", + "VBRK_EXT_IMUX33" ], [ - "CLBLL_EL1BEG2", - "VBRK_EL1BEG2" + "GTPE2_IMUX34_1", + "VBRK_EXT_IMUX34" ], [ - "CLBLL_NE4BEG0", - "VBRK_NE4BEG0" + "GTPE2_IMUX35_1", + "VBRK_EXT_IMUX35" ], [ - "CLBLL_NW4A2", - "VBRK_NW4A2" + "GTPE2_IMUX36_1", + "VBRK_EXT_IMUX36" ], [ - "CLBLL_EL1BEG0", - "VBRK_EL1BEG0" + "GTPE2_IMUX37_1", + "VBRK_EXT_IMUX37" ], [ - "CLBLL_EE4C2", - "VBRK_EE4C2" + "GTPE2_IMUX38_1", + "VBRK_EXT_IMUX38" ], [ - "CLBLL_ER1BEG3", - "VBRK_ER1BEG3" + "GTPE2_IMUX39_1", + "VBRK_EXT_IMUX39" ], [ - "CLBLL_WR1END0", - "VBRK_WR1END0" + "GTPE2_IMUX40_1", + "VBRK_EXT_IMUX40" ], [ - "CLBLL_EE2A1", - "VBRK_EE2A1" + "GTPE2_IMUX41_1", + "VBRK_EXT_IMUX41" ], [ - "CLBLL_EE4B2", - "VBRK_EE4B2" + "GTPE2_IMUX42_1", + "VBRK_EXT_IMUX42" ], [ - "CLBLL_WW4A0", - "VBRK_WW4A0" + "GTPE2_IMUX43_1", + "VBRK_EXT_IMUX43" ], [ - "CLBLL_WR1END2", - "VBRK_WR1END2" + "GTPE2_IMUX44_1", + "VBRK_EXT_IMUX44" ], [ - "CLBLL_NW4END2", - "VBRK_NW4END2" + "GTPE2_IMUX45_1", + "VBRK_EXT_IMUX45" ], [ - "CLBLL_SE2A2", - "VBRK_SE2A2" + "GTPE2_IMUX46_1", + "VBRK_EXT_IMUX46" ], [ - "CLBLL_WL1END1", - "VBRK_WL1END1" + "GTPE2_IMUX47_1", + "VBRK_EXT_IMUX47" ], [ - "CLBLL_NW2A2", - "VBRK_NW2A2" + "GTPE2_LOGIC_OUTS_B5_1", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "CLBLL_WW2END0", - "VBRK_WW2END0" + "GTPE2_LOGIC_OUTS_B8_1", + "VBRK_EXT_LOGIC_OUTS_B8" ], [ - "CLBLL_SE4BEG0", - "VBRK_SE4BEG0" + "GTPE2_LOGIC_OUTS_B10_1", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "CLBLL_SW2A2", - "VBRK_SW2A2" + "GTPE2_LOGIC_OUTS_B11_1", + "VBRK_EXT_LOGIC_OUTS_B11" ], [ - "CLBLL_SW4END3", - "VBRK_SW4END3" + "GTPE2_LOGIC_OUTS_B12_1", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "CLBLL_LH3", - "VBRK_LH3" + "GTPE2_LOGIC_OUTS_B13_1", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "CLBLL_NE2A2", - "VBRK_NE2A2" + "GTPE2_LOGIC_OUTS_B14_1", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "CLBLL_NW4END1", - "VBRK_NW4END1" + "GTPE2_LOGIC_OUTS_B15_1", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "CLBLL_MONITOR_N", - "VBRK_MONITOR_N" + "GTPE2_LOGIC_OUTS_B16_1", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "CLBLL_EE4A0", - "VBRK_EE4A0" + "GTPE2_LOGIC_OUTS_B17_1", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "CLBLL_EE2BEG3", - "VBRK_EE2BEG3" + "GTPE2_LOGIC_OUTS_B18_1", + "VBRK_EXT_LOGIC_OUTS_B18" ], [ - "CLBLL_LH10", - "VBRK_LH10" + "GTPE2_LOGIC_OUTS_B20_1", + "VBRK_EXT_LOGIC_OUTS_B20" ], [ - "CLBLL_LH1", - "VBRK_LH1" + "GTPE2_LOGIC_OUTS_B21_1", + "VBRK_EXT_LOGIC_OUTS_B21" ], [ - "CLBLL_NE4C1", - "VBRK_NE4C1" + "GTPE2_LOGIC_OUTS_B22_1", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "CLBLL_SW2A3", - "VBRK_SW2A3" + "GTPE2_LOGIC_OUTS_B23_1", + "VBRK_EXT_LOGIC_OUTS_B23" + ] + ] + }, + { + "grid_deltas": [ + -1, + 5 + ], + "tile_types": [ + "GTP_CHANNEL_1", + "VBRK_EXT" + ], + "wire_pairs": [ + [ + "GTPE2_BYP0_0", + "VBRK_EXT_BYP0" + ], + [ + "GTPE2_BYP1_0", + "VBRK_EXT_BYP1" + ], + [ + "GTPE2_BYP2_0", + "VBRK_EXT_BYP2" + ], + [ + "GTPE2_BYP3_0", + "VBRK_EXT_BYP3" + ], + [ + "GTPE2_BYP4_0", + "VBRK_EXT_BYP4" + ], + [ + "GTPE2_BYP5_0", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_BYP6_0", + "VBRK_EXT_BYP6" + ], + [ + "GTPE2_BYP7_0", + "VBRK_EXT_BYP7" + ], + [ + "GTPE2_CLK0_0", + "VBRK_EXT_CLK0" + ], + [ + "GTPE2_CLK1_0", + "VBRK_EXT_CLK1" + ], + [ + "GTPE2_CTRL0_0", + "VBRK_EXT_CTRL0" + ], + [ + "GTPE2_CTRL1_0", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_FAN0_0", + "VBRK_EXT_FAN0" + ], + [ + "GTPE2_FAN1_0", + "VBRK_EXT_FAN1" + ], + [ + "GTPE2_FAN2_0", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_FAN3_0", + "VBRK_EXT_FAN3" + ], + [ + "GTPE2_FAN4_0", + "VBRK_EXT_FAN4" + ], + [ + "GTPE2_FAN5_0", + "VBRK_EXT_FAN5" + ], + [ + "GTPE2_FAN6_0", + "VBRK_EXT_FAN6" + ], + [ + "GTPE2_FAN7_0", + "VBRK_EXT_FAN7" + ], + [ + "GTPE2_IMUX0_0", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX1_0", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX2_0", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_0", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_0", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_0", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_0", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_0", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_0", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_0", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX10_0", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX11_0", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_0", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_0", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_0", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_0", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_0", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_0", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_0", + "VBRK_EXT_IMUX18" ], [ - "CLBLL_SW2A0", - "VBRK_SW2A0" + "GTPE2_IMUX19_0", + "VBRK_EXT_IMUX19" ], [ - "CLBLL_WW4END3", - "VBRK_WW4END3" + "GTPE2_IMUX20_0", + "VBRK_EXT_IMUX20" ], [ - "CLBLL_NW4END0", - "VBRK_NW4END0" + "GTPE2_IMUX21_0", + "VBRK_EXT_IMUX21" ], [ - "CLBLL_EE4B0", - "VBRK_EE4B0" + "GTPE2_IMUX22_0", + "VBRK_EXT_IMUX22" ], [ - "CLBLL_WW4B0", - "VBRK_WW4B0" + "GTPE2_IMUX23_0", + "VBRK_EXT_IMUX23" ], [ - "CLBLL_LH9", - "VBRK_LH9" + "GTPE2_IMUX24_0", + "VBRK_EXT_IMUX24" ], [ - "CLBLL_LH6", - "VBRK_LH6" + "GTPE2_IMUX25_0", + "VBRK_EXT_IMUX25" ], [ - "CLBLL_NE2A0", - "VBRK_NE2A0" + "GTPE2_IMUX26_0", + "VBRK_EXT_IMUX26" ], [ - "CLBLL_SE2A0", - "VBRK_SE2A0" + "GTPE2_IMUX27_0", + "VBRK_EXT_IMUX27" ], [ - "CLBLL_SE4C3", - "VBRK_SE4C3" + "GTPE2_IMUX28_0", + "VBRK_EXT_IMUX28" ], [ - "CLBLL_EL1BEG3", - "VBRK_EL1BEG3" + "GTPE2_IMUX29_0", + "VBRK_EXT_IMUX29" ], [ - "CLBLL_WW2A3", - "VBRK_WW2A3" + "GTPE2_IMUX30_0", + "VBRK_EXT_IMUX30" ], [ - "CLBLL_LH4", - "VBRK_LH4" + "GTPE2_IMUX31_0", + "VBRK_EXT_IMUX31" ], [ - "CLBLL_EE4BEG2", - "VBRK_EE4BEG2" + "GTPE2_IMUX32_0", + "VBRK_EXT_IMUX32" ], [ - "CLBLL_EE4C3", - "VBRK_EE4C3" + "GTPE2_IMUX33_0", + "VBRK_EXT_IMUX33" ], [ - "CLBLL_NE2A1", - "VBRK_NE2A1" + "GTPE2_IMUX34_0", + "VBRK_EXT_IMUX34" ], [ - "CLBLL_EE4BEG3", - "VBRK_EE4BEG3" + "GTPE2_IMUX35_0", + "VBRK_EXT_IMUX35" ], [ - "CLBLL_EE4A3", - "VBRK_EE4A3" + "GTPE2_IMUX36_0", + "VBRK_EXT_IMUX36" ], [ - "CLBLL_EE2A2", - "VBRK_EE2A2" + "GTPE2_IMUX37_0", + "VBRK_EXT_IMUX37" ], [ - "CLBLL_NE4BEG1", - "VBRK_NE4BEG1" + "GTPE2_IMUX38_0", + "VBRK_EXT_IMUX38" ], [ - "CLBLL_SW4A2", - "VBRK_SW4A2" + "GTPE2_IMUX39_0", + "VBRK_EXT_IMUX39" ], [ - "CLBLL_NE4BEG2", - "VBRK_NE4BEG2" + "GTPE2_IMUX40_0", + "VBRK_EXT_IMUX40" ], [ - "CLBLL_WW2A1", - "VBRK_WW2A1" + "GTPE2_IMUX41_0", + "VBRK_EXT_IMUX41" ], [ - "CLBLL_SW4A1", - "VBRK_SW4A1" + "GTPE2_IMUX42_0", + "VBRK_EXT_IMUX42" ], [ - "CLBLL_WW2A2", - "VBRK_WW2A2" + "GTPE2_IMUX43_0", + "VBRK_EXT_IMUX43" ], [ - "CLBLL_SE4BEG2", - "VBRK_SE4BEG2" + "GTPE2_IMUX44_0", + "VBRK_EXT_IMUX44" ], [ - "CLBLL_NW4A3", - "VBRK_NW4A3" + "GTPE2_IMUX45_0", + "VBRK_EXT_IMUX45" ], [ - "CLBLL_WW4A3", - "VBRK_WW4A3" + "GTPE2_IMUX46_0", + "VBRK_EXT_IMUX46" ], [ - "CLBLL_SW2A1", - "VBRK_SW2A1" + "GTPE2_IMUX47_0", + "VBRK_EXT_IMUX47" ], [ - "CLBLL_ER1BEG2", - "VBRK_ER1BEG2" + "GTPE2_LOGIC_OUTS_B8_0", + "VBRK_EXT_LOGIC_OUTS_B8" ], [ - "CLBLL_EE4BEG0", - "VBRK_EE4BEG0" + "GTPE2_LOGIC_OUTS_B9_0", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "CLBLL_SE4C1", - "VBRK_SE4C1" + "GTPE2_LOGIC_OUTS_B10_0", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "CLBLL_LH12", - "VBRK_LH12" + "GTPE2_LOGIC_OUTS_B11_0", + "VBRK_EXT_LOGIC_OUTS_B11" ], [ - "CLBLL_NE4C2", - "VBRK_NE4C2" + "GTPE2_LOGIC_OUTS_B12_0", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "CLBLL_NE4C3", - "VBRK_NE4C3" + "GTPE2_LOGIC_OUTS_B13_0", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "CLBLL_WW4C2", - "VBRK_WW4C2" + "GTPE2_LOGIC_OUTS_B14_0", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "CLBLL_WL1END3", - "VBRK_WL1END3" + "GTPE2_LOGIC_OUTS_B15_0", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "CLBLL_EE2BEG2", - "VBRK_EE2BEG2" + "GTPE2_LOGIC_OUTS_B16_0", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "CLBLL_EE4BEG1", - "VBRK_EE4BEG1" + "GTPE2_LOGIC_OUTS_B18_0", + "VBRK_EXT_LOGIC_OUTS_B18" ], [ - "CLBLL_SW4A0", - "VBRK_SW4A0" + "GTPE2_LOGIC_OUTS_B19_0", + "VBRK_EXT_LOGIC_OUTS_B19" ], [ - "CLBLL_WW4B1", - "VBRK_WW4B1" + "GTPE2_LOGIC_OUTS_B20_0", + "VBRK_EXT_LOGIC_OUTS_B20" ], [ - "CLBLL_SE2A3", - "VBRK_SE2A3" + "GTPE2_LOGIC_OUTS_B22_0", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "CLBLL_WW4C0", - "VBRK_WW4C0" + "GTPE2_LOGIC_OUTS_B23_0", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }, @@ -415894,404 +349738,460 @@ "GTPE2_CHANNEL_PLLCLK0" ], [ - "GTPE2_CHANNEL_TXOUTCLK_3", - "GTPE2_CHANNEL_TXOUTCLK_3" - ], - [ - "GTPE2_CHANNEL_RXOUTCLK_2", - "GTPE2_CHANNEL_RXOUTCLK_2" - ], - [ - "GTPE2_CHANNEL_TXOUTCLK_2", - "GTPE2_CHANNEL_TXOUTCLK_2" - ], - [ - "GTPE2_CHANNEL_PLLREFCLK1", - "GTPE2_CHANNEL_PLLREFCLK1" + "GTPE2_CHANNEL_PLLCLK1", + "GTPE2_CHANNEL_PLLCLK1" ], [ "GTPE2_CHANNEL_PLLREFCLK0", "GTPE2_CHANNEL_PLLREFCLK0" ], [ - "GTPE2_CHANNEL_RXOUTCLK_1", - "GTPE2_CHANNEL_RXOUTCLK_1" - ], - [ - "GTPE2_CHANNEL_TXOUTCLK_1", - "GTPE2_CHANNEL_TXOUTCLK_1" - ], - [ - "GTPE2_CHANNEL_TXOUTCLK_0", - "GTPE2_CHANNEL_TXOUTCLK_0" + "GTPE2_CHANNEL_PLLREFCLK1", + "GTPE2_CHANNEL_PLLREFCLK1" ], [ "GTPE2_CHANNEL_RXOUTCLK_0", "GTPE2_CHANNEL_RXOUTCLK_0" ], + [ + "GTPE2_CHANNEL_RXOUTCLK_1", + "GTPE2_CHANNEL_RXOUTCLK_1" + ], + [ + "GTPE2_CHANNEL_RXOUTCLK_2", + "GTPE2_CHANNEL_RXOUTCLK_2" + ], [ "GTPE2_CHANNEL_RXOUTCLK_3", "GTPE2_CHANNEL_RXOUTCLK_3" ], + [ + "GTPE2_CHANNEL_TXOUTCLK_0", + "GTPE2_CHANNEL_TXOUTCLK_0" + ], + [ + "GTPE2_CHANNEL_TXOUTCLK_1", + "GTPE2_CHANNEL_TXOUTCLK_1" + ], + [ + "GTPE2_CHANNEL_TXOUTCLK_2", + "GTPE2_CHANNEL_TXOUTCLK_2" + ], + [ + "GTPE2_CHANNEL_TXOUTCLK_3", + "GTPE2_CHANNEL_TXOUTCLK_3" + ] + ] + }, + { + "grid_deltas": [ + 0, + 12 + ], + "tile_types": [ + "GTP_CHANNEL_2", + "GTP_COMMON" + ], + "wire_pairs": [ + [ + "GTPE2_CHANNEL_PLLCLK0", + "GTPE2_COMMON_PLLOUTCLK0" + ], [ "GTPE2_CHANNEL_PLLCLK1", - "GTPE2_CHANNEL_PLLCLK1" + "GTPE2_COMMON_PLLOUTCLK1" + ], + [ + "GTPE2_CHANNEL_PLLREFCLK0", + "GTPE2_COMMON_PLLREFCLK0" + ], + [ + "GTPE2_CHANNEL_PLLREFCLK1", + "GTPE2_COMMON_PLLREFCLK1" + ], + [ + "GTPE2_CHANNEL_RXOUTCLK_0", + "GTPE2_COMMON_RXOUTCLK_0" + ], + [ + "GTPE2_CHANNEL_RXOUTCLK_1", + "GTPE2_COMMON_RXOUTCLK_1" + ], + [ + "GTPE2_CHANNEL_RXOUTCLK_2", + "GTPE2_COMMON_RXOUTCLK_2" + ], + [ + "GTPE2_CHANNEL_RXOUTCLK_3", + "GTPE2_COMMON_RXOUTCLK_3" + ], + [ + "GTPE2_CHANNEL_TXOUTCLK_0", + "GTPE2_COMMON_TXOUTCLK_0" + ], + [ + "GTPE2_CHANNEL_TXOUTCLK_1", + "GTPE2_COMMON_TXOUTCLK_1" + ], + [ + "GTPE2_CHANNEL_TXOUTCLK_2", + "GTPE2_COMMON_TXOUTCLK_2" + ], + [ + "GTPE2_CHANNEL_TXOUTCLK_3", + "GTPE2_COMMON_TXOUTCLK_3" ] ] }, { "grid_deltas": [ -1, - -4 + -5 ], "tile_types": [ - "GTP_CHANNEL_0", + "GTP_CHANNEL_2", "VBRK_EXT" ], "wire_pairs": [ [ - "GTPE2_LOGIC_OUTS_B15_9", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_LOGIC_OUTS_B16_9", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_FAN3_9", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_BYP6_9", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_LOGIC_OUTS_B18_9", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_FAN2_9", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_CLK1_9", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX21_9", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_CTRL1_9", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX30_9", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B1_9", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX41_9", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_LOGIC_OUTS_B13_9", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_FAN5_9", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_LOGIC_OUTS_B0_9", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_IMUX7_9", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX33_9", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_LOGIC_OUTS_B20_9", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_IMUX12_9", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX11_9", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX8_9", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_BYP7_9", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX0_9", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B3_9", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_FAN0_9", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX9_9", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX20_9", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_FAN7_9", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_LOGIC_OUTS_B4_9", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_IMUX45_9", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX14_9", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_FAN1_9", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_LOGIC_OUTS_B5_9", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_IMUX6_9", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX2_9", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_BYP4_9", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX17_9", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX38_9", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX43_9", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX37_9", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX44_9", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX25_9", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_LOGIC_OUTS_B14_9", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX39_9", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_CLK0_9", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX18_9", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_BYP1_9", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX28_9", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX46_9", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX13_9", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_FAN4_9", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_BYP2_9", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX47_9", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX3_9", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_LOGIC_OUTS_B10_9", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_IMUX5_9", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_BYP5_9", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX4_9", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX40_9", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX32_9", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX26_9", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B23_9", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_BYP3_9", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_LOGIC_OUTS_B2_9", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_CTRL0_9", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_IMUX31_9", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX34_9", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX19_9", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_LOGIC_OUTS_B9_9", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_BYP0_9", + "GTPE2_BYP0_10", "VBRK_EXT_BYP0" ], [ - "GTPE2_IMUX23_9", - "VBRK_EXT_IMUX23" + "GTPE2_BYP1_10", + "VBRK_EXT_BYP1" ], [ - "GTPE2_IMUX10_9", - "VBRK_EXT_IMUX10" + "GTPE2_BYP2_10", + "VBRK_EXT_BYP2" ], [ - "GTPE2_IMUX35_9", - "VBRK_EXT_IMUX35" + "GTPE2_BYP3_10", + "VBRK_EXT_BYP3" ], [ - "GTPE2_LOGIC_OUTS_B12_9", - "VBRK_EXT_LOGIC_OUTS_B12" + "GTPE2_BYP4_10", + "VBRK_EXT_BYP4" ], [ - "GTPE2_FAN6_9", + "GTPE2_BYP5_10", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_BYP6_10", + "VBRK_EXT_BYP6" + ], + [ + "GTPE2_BYP7_10", + "VBRK_EXT_BYP7" + ], + [ + "GTPE2_CLK0_10", + "VBRK_EXT_CLK0" + ], + [ + "GTPE2_CLK1_10", + "VBRK_EXT_CLK1" + ], + [ + "GTPE2_CTRL0_10", + "VBRK_EXT_CTRL0" + ], + [ + "GTPE2_CTRL1_10", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_FAN0_10", + "VBRK_EXT_FAN0" + ], + [ + "GTPE2_FAN1_10", + "VBRK_EXT_FAN1" + ], + [ + "GTPE2_FAN2_10", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_FAN3_10", + "VBRK_EXT_FAN3" + ], + [ + "GTPE2_FAN4_10", + "VBRK_EXT_FAN4" + ], + [ + "GTPE2_FAN5_10", + "VBRK_EXT_FAN5" + ], + [ + "GTPE2_FAN6_10", "VBRK_EXT_FAN6" ], [ - "GTPE2_IMUX15_9", + "GTPE2_FAN7_10", + "VBRK_EXT_FAN7" + ], + [ + "GTPE2_IMUX0_10", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX1_10", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX2_10", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_10", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_10", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_10", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_10", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_10", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_10", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_10", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX10_10", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX11_10", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_10", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_10", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_10", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_10", "VBRK_EXT_IMUX15" ], [ - "GTPE2_IMUX36_9", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_LOGIC_OUTS_B22_9", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_LOGIC_OUTS_B7_9", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX16_9", + "GTPE2_IMUX16_10", "VBRK_EXT_IMUX16" ], [ - "GTPE2_IMUX24_9", - "VBRK_EXT_IMUX24" + "GTPE2_IMUX17_10", + "VBRK_EXT_IMUX17" ], [ - "GTPE2_IMUX27_9", - "VBRK_EXT_IMUX27" + "GTPE2_IMUX18_10", + "VBRK_EXT_IMUX18" ], [ - "GTPE2_IMUX29_9", - "VBRK_EXT_IMUX29" + "GTPE2_IMUX19_10", + "VBRK_EXT_IMUX19" ], [ - "GTPE2_IMUX42_9", - "VBRK_EXT_IMUX42" + "GTPE2_IMUX20_10", + "VBRK_EXT_IMUX20" ], [ - "GTPE2_IMUX22_9", + "GTPE2_IMUX21_10", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX22_10", "VBRK_EXT_IMUX22" ], [ - "GTPE2_IMUX1_9", - "VBRK_EXT_IMUX1" + "GTPE2_IMUX23_10", + "VBRK_EXT_IMUX23" + ], + [ + "GTPE2_IMUX24_10", + "VBRK_EXT_IMUX24" + ], + [ + "GTPE2_IMUX25_10", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX26_10", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX27_10", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX28_10", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_IMUX29_10", + "VBRK_EXT_IMUX29" + ], + [ + "GTPE2_IMUX30_10", + "VBRK_EXT_IMUX30" + ], + [ + "GTPE2_IMUX31_10", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_IMUX32_10", + "VBRK_EXT_IMUX32" + ], + [ + "GTPE2_IMUX33_10", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX34_10", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_IMUX35_10", + "VBRK_EXT_IMUX35" + ], + [ + "GTPE2_IMUX36_10", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX37_10", + "VBRK_EXT_IMUX37" + ], + [ + "GTPE2_IMUX38_10", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX39_10", + "VBRK_EXT_IMUX39" + ], + [ + "GTPE2_IMUX40_10", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_IMUX41_10", + "VBRK_EXT_IMUX41" + ], + [ + "GTPE2_IMUX42_10", + "VBRK_EXT_IMUX42" + ], + [ + "GTPE2_IMUX43_10", + "VBRK_EXT_IMUX43" + ], + [ + "GTPE2_IMUX44_10", + "VBRK_EXT_IMUX44" + ], + [ + "GTPE2_IMUX45_10", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_IMUX46_10", + "VBRK_EXT_IMUX46" + ], + [ + "GTPE2_IMUX47_10", + "VBRK_EXT_IMUX47" + ], + [ + "GTPE2_LOGIC_OUTS_B0_10", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTPE2_LOGIC_OUTS_B1_10", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTPE2_LOGIC_OUTS_B2_10", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTPE2_LOGIC_OUTS_B3_10", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTPE2_LOGIC_OUTS_B4_10", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTPE2_LOGIC_OUTS_B5_10", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTPE2_LOGIC_OUTS_B6_10", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTPE2_LOGIC_OUTS_B9_10", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTPE2_LOGIC_OUTS_B11_10", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTPE2_LOGIC_OUTS_B12_10", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTPE2_LOGIC_OUTS_B13_10", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTPE2_LOGIC_OUTS_B14_10", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTPE2_LOGIC_OUTS_B16_10", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTPE2_LOGIC_OUTS_B17_10", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTPE2_LOGIC_OUTS_B19_10", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTPE2_LOGIC_OUTS_B22_10", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTPE2_LOGIC_OUTS_B23_10", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }, @@ -416305,6 +350205,326 @@ "VBRK_EXT" ], "wire_pairs": [ + [ + "GTPE2_BYP0_9", + "VBRK_EXT_BYP0" + ], + [ + "GTPE2_BYP1_9", + "VBRK_EXT_BYP1" + ], + [ + "GTPE2_BYP2_9", + "VBRK_EXT_BYP2" + ], + [ + "GTPE2_BYP3_9", + "VBRK_EXT_BYP3" + ], + [ + "GTPE2_BYP4_9", + "VBRK_EXT_BYP4" + ], + [ + "GTPE2_BYP5_9", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_BYP6_9", + "VBRK_EXT_BYP6" + ], + [ + "GTPE2_BYP7_9", + "VBRK_EXT_BYP7" + ], + [ + "GTPE2_CLK0_9", + "VBRK_EXT_CLK0" + ], + [ + "GTPE2_CLK1_9", + "VBRK_EXT_CLK1" + ], + [ + "GTPE2_CTRL0_9", + "VBRK_EXT_CTRL0" + ], + [ + "GTPE2_CTRL1_9", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_FAN0_9", + "VBRK_EXT_FAN0" + ], + [ + "GTPE2_FAN1_9", + "VBRK_EXT_FAN1" + ], + [ + "GTPE2_FAN2_9", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_FAN3_9", + "VBRK_EXT_FAN3" + ], + [ + "GTPE2_FAN4_9", + "VBRK_EXT_FAN4" + ], + [ + "GTPE2_FAN5_9", + "VBRK_EXT_FAN5" + ], + [ + "GTPE2_FAN6_9", + "VBRK_EXT_FAN6" + ], + [ + "GTPE2_FAN7_9", + "VBRK_EXT_FAN7" + ], + [ + "GTPE2_IMUX0_9", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX1_9", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX2_9", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_9", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_9", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_9", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_9", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_9", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_9", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_9", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX10_9", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX11_9", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_9", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_9", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_9", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_9", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_9", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_9", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_9", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX19_9", + "VBRK_EXT_IMUX19" + ], + [ + "GTPE2_IMUX20_9", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_IMUX21_9", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX22_9", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX23_9", + "VBRK_EXT_IMUX23" + ], + [ + "GTPE2_IMUX24_9", + "VBRK_EXT_IMUX24" + ], + [ + "GTPE2_IMUX25_9", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX26_9", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX27_9", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX28_9", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_IMUX29_9", + "VBRK_EXT_IMUX29" + ], + [ + "GTPE2_IMUX30_9", + "VBRK_EXT_IMUX30" + ], + [ + "GTPE2_IMUX31_9", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_IMUX32_9", + "VBRK_EXT_IMUX32" + ], + [ + "GTPE2_IMUX33_9", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX34_9", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_IMUX35_9", + "VBRK_EXT_IMUX35" + ], + [ + "GTPE2_IMUX36_9", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX37_9", + "VBRK_EXT_IMUX37" + ], + [ + "GTPE2_IMUX38_9", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX39_9", + "VBRK_EXT_IMUX39" + ], + [ + "GTPE2_IMUX40_9", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_IMUX41_9", + "VBRK_EXT_IMUX41" + ], + [ + "GTPE2_IMUX42_9", + "VBRK_EXT_IMUX42" + ], + [ + "GTPE2_IMUX43_9", + "VBRK_EXT_IMUX43" + ], + [ + "GTPE2_IMUX44_9", + "VBRK_EXT_IMUX44" + ], + [ + "GTPE2_IMUX45_9", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_IMUX46_9", + "VBRK_EXT_IMUX46" + ], + [ + "GTPE2_IMUX47_9", + "VBRK_EXT_IMUX47" + ], + [ + "GTPE2_LOGIC_OUTS_B0_9", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTPE2_LOGIC_OUTS_B1_9", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTPE2_LOGIC_OUTS_B2_9", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTPE2_LOGIC_OUTS_B3_9", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTPE2_LOGIC_OUTS_B4_9", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTPE2_LOGIC_OUTS_B5_9", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTPE2_LOGIC_OUTS_B7_9", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTPE2_LOGIC_OUTS_B9_9", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTPE2_LOGIC_OUTS_B10_9", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTPE2_LOGIC_OUTS_B12_9", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTPE2_LOGIC_OUTS_B13_9", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTPE2_LOGIC_OUTS_B14_9", + "VBRK_EXT_LOGIC_OUTS_B14" + ], [ "GTPE2_LOGIC_OUTS_B15_9", "VBRK_EXT_LOGIC_OUTS_B15" @@ -416313,17065 +350533,733 @@ "GTPE2_LOGIC_OUTS_B16_9", "VBRK_EXT_LOGIC_OUTS_B16" ], - [ - "GTPE2_FAN3_9", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_BYP6_9", - "VBRK_EXT_BYP6" - ], [ "GTPE2_LOGIC_OUTS_B18_9", "VBRK_EXT_LOGIC_OUTS_B18" ], - [ - "GTPE2_FAN2_9", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_CLK1_9", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX21_9", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_CTRL1_9", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX30_9", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B1_9", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX41_9", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_LOGIC_OUTS_B13_9", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_FAN5_9", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_LOGIC_OUTS_B0_9", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_IMUX7_9", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX33_9", - "VBRK_EXT_IMUX33" - ], [ "GTPE2_LOGIC_OUTS_B20_9", "VBRK_EXT_LOGIC_OUTS_B20" ], - [ - "GTPE2_IMUX12_9", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX11_9", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX8_9", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_BYP7_9", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX0_9", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B3_9", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_FAN0_9", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX9_9", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX20_9", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_FAN7_9", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_LOGIC_OUTS_B4_9", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_IMUX45_9", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX14_9", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_FAN1_9", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_LOGIC_OUTS_B5_9", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_IMUX6_9", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX2_9", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_BYP4_9", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX17_9", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX38_9", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX43_9", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX37_9", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX44_9", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX25_9", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_LOGIC_OUTS_B14_9", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX39_9", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_CLK0_9", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX18_9", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_BYP1_9", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX28_9", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX46_9", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX13_9", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_FAN4_9", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_BYP2_9", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX47_9", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX3_9", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_LOGIC_OUTS_B10_9", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_IMUX5_9", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_BYP5_9", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX4_9", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX40_9", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX32_9", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX26_9", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B23_9", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_BYP3_9", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_LOGIC_OUTS_B2_9", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_CTRL0_9", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_IMUX31_9", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX34_9", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX19_9", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_LOGIC_OUTS_B9_9", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_BYP0_9", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX23_9", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX10_9", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX35_9", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_LOGIC_OUTS_B12_9", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_FAN6_9", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX15_9", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX36_9", - "VBRK_EXT_IMUX36" - ], [ "GTPE2_LOGIC_OUTS_B22_9", "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "GTPE2_LOGIC_OUTS_B7_9", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX16_9", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX24_9", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_IMUX27_9", - "VBRK_EXT_IMUX27" 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"VFRAME_BYP4" - ], - [ - "CFG_CENTER_BYP2_0", - "VFRAME_BYP2" - ], - [ - "CFG_CENTER_WW2A3_0", - "VFRAME_WW2A3" - ], - [ - "CFG_CENTER_NW4A1_0", - "VFRAME_NW4A1" - ], - [ - "CFG_CENTER_WR1END3_0", - "VFRAME_WR1END3" - ], - [ - "CFG_CENTER_WW2A2_0", - "VFRAME_WW2A2" - ], - [ - "CFG_CENTER_FAN0_0", - "VFRAME_FAN0" - ], - [ - "CFG_CENTER_SW4A3_0", - "VFRAME_SW4A3" - ], - [ - "CFG_CENTER_FAN4_0", - "VFRAME_FAN4" - ], - [ - "CFG_CENTER_EE4C0_0", - "VFRAME_EE4C0" - ], - [ - "CFG_CENTER_LH4_0", - "VFRAME_LH4" - ], - [ - "CFG_CENTER_WW4B3_0", - "VFRAME_WW4B3" - ], - [ - "CFG_CENTER_EE2BEG3_0", - "VFRAME_EE2BEG3" - ], - [ - "CFG_CENTER_IMUX15_0", - "VFRAME_IMUX15" - ], - [ - "CFG_CENTER_WR1END1_0", - "VFRAME_WR1END1" - ], - [ - "CFG_CENTER_ER1BEG3_0", - "VFRAME_ER1BEG3" - ], - [ - "CFG_CENTER_IMUX0_0", - "VFRAME_IMUX0" - ], - [ - "CFG_CENTER_IMUX12_0", - "VFRAME_IMUX12" - ], - [ - "CFG_CENTER_EE2A3_0", - "VFRAME_EE2A3" - ], - [ - "CFG_CENTER_NE4BEG3_0", - "VFRAME_NE4BEG3" - ], - [ - "CFG_CENTER_IMUX24_0", - "VFRAME_IMUX24" - ], - [ - "CFG_CENTER_IMUX29_0", - "VFRAME_IMUX29" - ], - [ - "CFG_CENTER_IMUX16_0", - "VFRAME_IMUX16" - ], - [ - "CFG_CENTER_CLK1_0", - "VFRAME_CLK1" - ], - [ - "CFG_CENTER_IMUX21_0", - "VFRAME_IMUX21" - ], - [ - "CFG_CENTER_IMUX32_0", - "VFRAME_IMUX32" - ], - [ - "CFG_CENTER_FAN6_0", - "VFRAME_FAN6" - ], - [ - "CFG_CENTER_SE2A3_0", - "VFRAME_SE2A3" - ], - [ - "CFG_CENTER_SE4BEG3_0", - "VFRAME_SE4BEG3" - ], - [ - "CFG_CENTER_WW4B0_0", - "VFRAME_WW4B0" - ], - [ - "CFG_CENTER_NE4BEG1_0", - "VFRAME_NE4BEG1" - ], - [ - "CFG_CENTER_IMUX44_0", - "VFRAME_IMUX44" - ], - [ - "CFG_CENTER_NW4END2_0", - "VFRAME_NW4END2" - ], - [ - "CFG_CENTER_SW2A1_0", - "VFRAME_SW2A1" - ], - [ - "CFG_CENTER_NE2A0_0", - "VFRAME_NE2A0" - ], - [ - "CFG_CENTER_IMUX20_0", - "VFRAME_IMUX20" - ], - [ - "CFG_CENTER_IMUX26_0", - "VFRAME_IMUX26" - ], - [ - "CFG_CENTER_IMUX19_0", - "VFRAME_IMUX19" - ], - [ - "CFG_CENTER_EE4A2_0", - "VFRAME_EE4A2" - ], - [ - "CFG_CENTER_SE4BEG1_0", - "VFRAME_SE4BEG1" - ], - [ - "CFG_CENTER_NW4A0_0", - "VFRAME_NW4A0" - ], - [ - "CFG_CENTER_IMUX41_0", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_SE4C1_0", - "VFRAME_SE4C1" - ], - [ - "CFG_CENTER_EE4A3_0", - "VFRAME_EE4A3" - ], - [ - "CFG_CENTER_BYP5_0", - "VFRAME_BYP5" - ], - [ - "CFG_CENTER_FAN7_0", - "VFRAME_FAN7" - ], - [ - "CFG_CENTER_WW2END0_0", - "VFRAME_WW2END0" - ], - [ - "CFG_CENTER_SE4BEG0_0", - "VFRAME_SE4BEG0" - ], - [ - "CFG_CENTER_CLK0_0", - "VFRAME_CLK0" - ], - [ - "CFG_CENTER_NW2A0_0", - "VFRAME_NW2A0" - ], - [ - "CFG_CENTER_WW2A1_0", - "VFRAME_WW2A1" - ], - [ - "CFG_CENTER_WW4END3_0", - "VFRAME_WW4END3" - ], - [ - "CFG_CENTER_IMUX34_0", - "VFRAME_IMUX34" - ], - [ - "CFG_CENTER_EE4B2_0", - "VFRAME_EE4B2" - ], - [ - "CFG_CENTER_CTRL1_0", - "VFRAME_CTRL1" - ], - [ - "CFG_CENTER_FAN2_0", - "VFRAME_FAN2" - ], - [ - "CFG_CENTER_LH2_0", - "VFRAME_LH2" - ], - [ - "CFG_CENTER_WW4C3_0", - "VFRAME_WW4C3" - ], - [ - "CFG_CENTER_EL1BEG2_0", - "VFRAME_EL1BEG2" - ], - [ - "CFG_CENTER_NE4C2_0", - "VFRAME_NE4C2" - ], - [ - "CFG_CENTER_NE2A1_0", - "VFRAME_NE2A1" - ], - [ - "CFG_CENTER_SE4BEG2_0", - "VFRAME_SE4BEG2" - ], - [ - "CFG_CENTER_LH5_0", - "VFRAME_LH5" - ], - [ - "CFG_CENTER_EE4BEG1_0", - "VFRAME_EE4BEG1" - ], - [ - "CFG_CENTER_NE2A2_0", - "VFRAME_NE2A2" - ], - [ - "CFG_CENTER_NW4END3_0", - "VFRAME_NW4END3" - ], - [ - "CFG_CENTER_WW4C2_0", - "VFRAME_WW4C2" - ], - [ - "CFG_CENTER_LH1_0", - "VFRAME_LH1" - ], - [ - "CFG_CENTER_IMUX1_0", - "VFRAME_IMUX1" - ], - [ - "CFG_CENTER_SE4C3_0", - "VFRAME_SE4C3" - ], - [ - "CFG_CENTER_IMUX11_0", - "VFRAME_IMUX11" - ], - [ - "CFG_CENTER_EL1BEG1_0", - "VFRAME_EL1BEG1" - ], - [ - "CFG_CENTER_IMUX42_0", - "VFRAME_IMUX42" - ], - [ - "CFG_CENTER_WW4C1_0", - "VFRAME_WW4C1" - ], - [ - "CFG_CENTER_NE4C3_0", - "VFRAME_NE4C3" - ] - ] - }, - { - "grid_deltas": [ - 0, - -2 - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_CLB", - "HCLK_CLB" - ], - "wire_pairs": [ - [ - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_CLB_CK_BUFHCLK2" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_CLB_CK_IN11" - ], - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CLB_CK_BUFHCLK9" - ], - [ - "HCLK_CLB_CK_IN3", - "HCLK_CLB_CK_IN3" - ], - [ - "HCLK_CLB_CK_IN2", - "HCLK_CLB_CK_IN2" - ], - [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_CLB_CK_BUFHCLK0" - ], - [ - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_CLB_CK_BUFRCLK1" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_CLB_CK_IN4" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_CLB_CK_IN6" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_CLB_CK_IN12" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_CLB_CK_IN13" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CLB_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_IN7", - "HCLK_CLB_CK_IN7" - ], - [ - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_CLB_CK_BUFRCLK3" - ], - [ - "HCLK_CLB_CK_IN9", - "HCLK_CLB_CK_IN9" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_CLB_CK_BUFHCLK10" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_CLB_CK_IN10" - ], - [ - "HCLK_CLB_CK_BUFRCLK0", - "HCLK_CLB_CK_BUFRCLK0" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_CLB_CK_IN5" - ], - [ - "HCLK_CLB_PERFCLK1", - "HCLK_CLB_PERFCLK1" - ], - [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_CLB_CK_BUFHCLK1" - ], - [ - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_CLB_CK_BUFRCLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_CLB_CK_BUFHCLK8" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CLB_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_IN0", - "HCLK_CLB_CK_IN0" - ], - [ - "HCLK_CLB_PERFCLK3", - "HCLK_CLB_PERFCLK3" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_CLB_CK_IN8" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_CLB_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_PERFCLK0", - "HCLK_CLB_PERFCLK0" - ], - [ - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CLB_CK_BUFHCLK4" - ], - [ - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_CLB_CK_BUFHCLK7" - ], - [ - "HCLK_CLB_CK_IN1", - "HCLK_CLB_CK_IN1" - ], - [ - "HCLK_CLB_PERFCLK2", - "HCLK_CLB_PERFCLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_CLB_CK_BUFHCLK3" - ] - ] - }, - { - "grid_deltas": [ - 1, - 1 - ], - "tile_types": [ - "CMT_TOP_R_UPPER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_LH5_3", - "VBRK_LH5" - ], - [ - "CMT_TOP_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_LH1_3", - "VBRK_LH1" - ], - [ - "CMT_TOP_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_LH9_3", - "VBRK_LH9" - ], - [ - "CMT_TOP_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_WW4C1_3", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_LH7_3", - "VBRK_LH7" - ], - [ - "CMT_TOP_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_LH11_3", - "VBRK_LH11" - ], - [ - "CMT_TOP_LH2_3", - "VBRK_LH2" - ], - [ - "CMT_TOP_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_LH10_3", - "VBRK_LH10" - ], - [ - "CMT_TOP_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_LH4_3", - "VBRK_LH4" - ], - [ - "CMT_TOP_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_LH12_3", - "VBRK_LH12" - ], - [ - "CMT_TOP_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_WL1END2_3", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_LH8_3", - "VBRK_LH8" - ], - [ - "CMT_TOP_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_SE2A2_3", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_SW2A0_3", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_LH6_3", - "VBRK_LH6" - ], - [ - "CMT_TOP_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_LH3_3", - "VBRK_LH3" - ], - [ - "CMT_TOP_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_WW4C2_3", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_NE4BEG0_3", - "VBRK_NE4BEG0" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_INT_INTERFACE", - "HCLK_R" - ], - "wire_pairs": [ - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_CK_BUFRCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_IN2", - "HCLK_CK_IN2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN1", - "HCLK_CK_IN1" - ], - [ - "HCLK_INT_INTERFACE_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_CK_IN0", - "HCLK_CK_IN0" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_INT_PERFCLK3" - ], - [ - "HCLK_INT_INTERFACE_CCIO0", - "HCLK_CCIO0" - ], - [ - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_CCIO2" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_INT_PERFCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_CCIO1" - ], - [ - "HCLK_INT_INTERFACE_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_INT_INTERFACE_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_INT_INTERFACE_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_INT_INTERFACE_CK_IN3", - "HCLK_CK_IN3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_INT_PERFCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK0" - ], - [ - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_CCIO3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_INT_INTERFACE_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_INT_INTERFACE_CK_IN5", - "HCLK_CK_IN5" - ] - ] - }, - { - "grid_deltas": [ - -1, - -1 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_BUFG_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_BUFG_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_BUFG_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_1", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_BUFG_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_BUFG_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_BUFG_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_BUFG_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_BUFG_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_BUFG_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "CLK_BUFG_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_BUFG_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_BUFG_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_MONITOR_N_1", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_1", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_HROW_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_BUFG_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_BUFG_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_BUFG_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_1", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_HROW_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_1", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_BUFG_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_1", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_1", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_BUFG_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_BUFG_IMUX3_1", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_BUFG_IMUX39_1", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_BUFG_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_1", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_BUFG_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_BUFG_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_ER1BEG0_1", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_BUFG_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_BUFG_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_EE4C2_1", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_BUFG_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_BUFG_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_BUFG_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_ER1BEG1_1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_BUFG_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_BUFG_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_BUFG_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_BUFG_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WW2A3_1", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_BUFG_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_BUFG_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SW2A0_1", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_BUFG_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_BUFG_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WW4END3_1", - "INT_INTERFACE_WW4END3" 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"INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_BUFG_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_BUFG_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_MONITOR_P_1", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_1", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_HROW_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_EL1BEG1_8", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_NE2A0_8", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_EE4B2_8", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_NE4BEG3_8", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_NW4A1_8", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4A1_8", - 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"INT_INTERFACE_ER1BEG0" - ], - [ - "PCIE_LH11_16", - "INT_INTERFACE_LH11" - ], - [ - "PCIE_SW2A1_16", - "INT_INTERFACE_SW2A1" - ], - [ - "PCIE_LOGIC_OUTS_B11_L_16", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "PCIE_IMUX13_L_16", - "PCIE_INT_INTERFACE_IMUX_L_OUT13" - ], - [ - "PCIE_BYP7_L_16", - "INT_INTERFACE_BYP7" - ], - [ - "PCIE_WW2A0_16", - "INT_INTERFACE_WW2A0" - ], - [ - "PCIE_EE4A0_16", - "INT_INTERFACE_EE4A0" - ], - [ - "PCIE_IMUX21_L_16", - "PCIE_INT_INTERFACE_IMUX_L_OUT21" - ], - [ - "PCIE_NW4END0_16", - "INT_INTERFACE_NW4END0" - ], - [ - "PCIE_SE4C3_16", - "INT_INTERFACE_SE4C3" - ], - [ - "PCIE_LOGIC_OUTS_B1_L_16", - "INT_INTERFACE_LOGIC_OUTS_L_B1" - ], - [ - "PCIE_SW2A2_16", - "INT_INTERFACE_SW2A2" - ], - [ - "PCIE_EE2BEG2_16", - "INT_INTERFACE_EE2BEG2" - ], - [ - "PCIE_EE4C3_16", - "INT_INTERFACE_EE4C3" - ], - [ - "PCIE_IMUX35_L_16", - "PCIE_INT_INTERFACE_IMUX_L_OUT35" - ], - [ - "PCIE_IMUX34_L_16", - "PCIE_INT_INTERFACE_IMUX_L_OUT34" - ], - [ - "PCIE_IMUX26_L_16", - "PCIE_INT_INTERFACE_IMUX_L_OUT26" - ], - [ - "PCIE_WW4A3_16", - "INT_INTERFACE_WW4A3" - ], - [ - "PCIE_IMUX20_L_16", - "PCIE_INT_INTERFACE_IMUX_L_OUT20" - ], - [ - "PCIE_FAN4_L_16", - "INT_INTERFACE_FAN4" - ], - [ - "PCIE_IMUX12_L_16", - "PCIE_INT_INTERFACE_IMUX_L_OUT12" - ], - [ - "PCIE_CTRL0_L_16", - "INT_INTERFACE_CTRL0" - ], - [ - "PCIE_FAN2_L_16", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_SE2A1_16", - "INT_INTERFACE_SE2A1" - ], - [ - "PCIE_WW2A2_16", - "INT_INTERFACE_WW2A2" - ], - [ - "PCIE_IMUX31_L_16", - "PCIE_INT_INTERFACE_IMUX_L_OUT31" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "HCLK_L", - "INT_L" - ], - "wire_pairs": [ - [ - "HCLK_NE6B1", - "NE6B1" - ], - [ - "HCLK_SW6D2", - "SW6D2" - ], - [ - "HCLK_BYP_BOUNCE3", - "BYP_BOUNCE3" - ], - [ - "HCLK_NW2END_S0_0", - "NW2END_S0_0" - ], - [ - "HCLK_SS2END1", - "SS2END1" - ], - [ - "HCLK_SS6C1", - "SS6C1" - ], - [ - "HCLK_NN2BEG3", - "NN2BEG3" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END3" - ], - [ - "HCLK_NN6C3", - "NN6C3" - ], - [ - "HCLK_SE6D0", - "SE6D0" - ], - [ - "HCLK_SL1END0", - "SL1END0" - ], - [ - "HCLK_NE6A3", - "NE6A3" - ], - [ - "HCLK_SR1END_N3_3", - "SR1END3" - ], - [ - "HCLK_SS6D2", - "SS6D2" - ], - [ - "HCLK_SS6A0", - "SS6A0" - ], - [ - "HCLK_NE6B2", - "NE6B2" - ], - [ - "HCLK_LVB4", - "LVB_L3" - ], - [ - "HCLK_NN6BEG1", - "NN6BEG1" - ], - [ - "HCLK_SS2A0", - "SS2A0" - ], - [ - "HCLK_NN6B2", - "NN6B2" - ], - [ - "HCLK_LVB10", - "LVB_L9" - ], - [ - "HCLK_LVB6", - "LVB_L5" - ], - [ - "HCLK_SW6B0", - "SW6B0" - ], - [ - "HCLK_SS6END_N0_3", - "SS6END3" - ], - [ - "HCLK_NW2A3", - "NW2BEG3" - ], - [ - "HCLK_SW6C1", - "SW6C1" - ], - [ - "HCLK_LVB9", - "LVB_L8" - ], - [ - "HCLK_SW6D1", - "SW6D1" - ], - [ - "HCLK_SE6E2", - "SE6E2" - ], - [ - "HCLK_SS6B2", - "SS6B2" - ], - [ - "HCLK_NN6A0", - "NN6A0" - ], - [ - "HCLK_LVB7", - "LVB_L6" - ], - [ - "HCLK_NE6C1", - "NE6C1" - ], - [ - "HCLK_NE6B0", - "NE6B0" - ], - [ - "HCLK_FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_0" - ], - [ - "HCLK_SE6B0", - "SE6B0" - ], - [ - "HCLK_NW6A0", - "NW6A0" - ], - [ - "HCLK_NE6A0", - "NE6A0" - ], - [ - "HCLK_SS6D1", - "SS6D1" - ], - [ - "HCLK_LV5", - "LV_L5" - ], - [ - "HCLK_SS6END2", - "SS6END2" - ], - [ - "HCLK_SE6D1", - "SE6D1" - ], - [ - "HCLK_SW6E2", - "SW6E2" - ], - [ - "HCLK_NW2A1", - "NW2BEG1" - ], - [ - "HCLK_NW6B2", - "NW6B2" - ], - [ - "HCLK_NL1BEG2", - "NL1BEG2" - ], - [ - "HCLK_SW6C3", - "SW6C3" - ], - [ - "HCLK_NN2A0", - "NN2A0" - ], - [ - "HCLK_SS2END2", - "SS2END2" - ], - [ - "HCLK_SE6E0", - "SE6E0" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE2" - ], - [ - "HCLK_SS6B0", - "SS6B0" - ], - [ - "HCLK_SE6B2", - "SE6B2" - ], - [ - "HCLK_LV10", - "LV_L10" - ], - [ - "HCLK_LV7", - "LV_L7" - ], - [ - "HCLK_NW2A0", - "NW2BEG0" - ], - [ - "HCLK_NN2A1", - "NN2A1" - ], - [ - "HCLK_WW4END_S0_0", - "WW4END_S0_0" - ], - [ - "HCLK_LV2", - "LV_L2" - ], - [ - "HCLK_LV13", - "LV_L13" - ], - [ - "HCLK_LV14", - "LV_L14" - ], - [ - "HCLK_SS2END_N0_3", - "SS2END3" - ], - [ - "HCLK_SR1END1", - "SR1END1" - ], - [ - "HCLK_NE6D2", - "NE6D2" - ], - [ - "HCLK_NW6C1", - "NW6C1" - ], - [ - "HCLK_NW6D2", - "NW6D2" - ], - [ - "HCLK_SL1END2", - "SL1END2" - ], - [ - "HCLK_SS6C3", - "SS6C3" - ], - [ - "HCLK_NN6C2", - "NN6C2" - ], - [ - "HCLK_LEAF_CLK_B_BOTL0", - "GCLK_L_B6" - ], - [ - "HCLK_SS6C2", - "SS6C2" - ], - [ - "HCLK_SW2END0", - "SW2A0" - ], - [ - "HCLK_NN6B0", - "NN6B0" - ], - [ - "HCLK_SW6D0", - "SW6D0" - ], - [ - "HCLK_SS6B3", - "SS6B3" - ], - [ - "HCLK_NW6C3", - "NW6C3" - ], - [ - "HCLK_NR1BEG1", - "NR1BEG1" - ], - [ - "HCLK_NN6A2", - "NN6A2" - ], - [ - "HCLK_NE6C3", - "NE6C3" - ], - [ - "HCLK_SS6D3", - "SS6D3" - ], - [ - "HCLK_NW6B1", - "NW6B1" - ], - [ - "HCLK_NW6A2", - "NW6A2" - ], - [ - "HCLK_NW6D0", - "NW6D0" - ], - [ - "HCLK_NE6D3", - "NE6D3" - ], - [ - "HCLK_SS6END3", - "SS6END3" - ], - [ - "HCLK_NN6B3", - "NN6B3" - ], - [ - "HCLK_WL1BEG3", - "WL1BEG3" - ], - [ - "HCLK_SS2END0", - "SS2END0" - ], - [ - "HCLK_NE6A2", - "NE6A2" - ], - [ - "HCLK_SE6B3", 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], - [ - "HCLK_NN6E2", - "NN6E2" - ] - ] - }, - { - "grid_deltas": [ - -1, - -5 - ], - "tile_types": [ - "CMT_TOP_L_UPPER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_NE4BEG3_9", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_WW4C3_9", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_LH10_9", - "VBRK_LH10" - ], - [ - "CMT_TOP_WW4C0_9", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_NE4C2_9", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_SW4A2_9", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_NW4A0_9", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_EE2A1_9", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_WW2END0_9", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_LH3_9", - "VBRK_LH3" - ], - [ - "CMT_TOP_LH1_9", - "VBRK_LH1" - ], - [ - "CMT_TOP_SE4BEG3_9", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_NW4A1_9", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW2END2_9", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_SE4C3_9", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_SE4C1_9", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_SE4BEG0_9", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_EE2A0_9", - "VBRK_EE2A0" - ], - [ - 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"GTPE2_LOGIC_OUTS_B5_8", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTPE2_LOGIC_OUTS_B6_8", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTPE2_LOGIC_OUTS_B7_8", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTPE2_LOGIC_OUTS_B9_8", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTPE2_LOGIC_OUTS_B12_8", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTPE2_LOGIC_OUTS_B13_8", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTPE2_LOGIC_OUTS_B14_8", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTPE2_LOGIC_OUTS_B15_8", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTPE2_LOGIC_OUTS_B16_8", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTPE2_LOGIC_OUTS_B17_8", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTPE2_LOGIC_OUTS_B18_8", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTPE2_LOGIC_OUTS_B19_8", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTPE2_LOGIC_OUTS_B21_8", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "GTPE2_LOGIC_OUTS_B22_8", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTPE2_LOGIC_OUTS_B23_8", + "VBRK_EXT_LOGIC_OUTS_B23" + ] + ] + }, + { + "grid_deltas": [ + -1, + -2 + ], + "tile_types": [ + "GTP_CHANNEL_2", + "VBRK_EXT" + ], + "wire_pairs": [ + [ + "GTPE2_BYP0_7", + "VBRK_EXT_BYP0" + ], [ "GTPE2_BYP1_7", "VBRK_EXT_BYP1" ], - [ - "GTPE2_BYP4_7", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_LOGIC_OUTS_B12_7", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_BYP6_7", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX45_7", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX37_7", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_LOGIC_OUTS_B5_7", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_LOGIC_OUTS_B1_7", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX14_7", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_FAN2_7", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX17_7", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX22_7", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX1_7", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_LOGIC_OUTS_B2_7", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_IMUX20_7", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX40_7", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX3_7", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX42_7", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_CLK0_7", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_LOGIC_OUTS_B7_7", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX31_7", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX21_7", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX30_7", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX6_7", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX46_7", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_BYP0_7", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX34_7", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX29_7", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B18_7", - "VBRK_EXT_LOGIC_OUTS_B18" - ], [ "GTPE2_BYP2_7", "VBRK_EXT_BYP2" ], - [ - "GTPE2_IMUX18_7", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_LOGIC_OUTS_B3_7", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_LOGIC_OUTS_B9_7", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_BYP5_7", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_FAN6_7", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX24_7", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_CTRL1_7", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX13_7", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_LOGIC_OUTS_B19_7", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_FAN7_7", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX10_7", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX8_7", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_FAN4_7", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX47_7", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX33_7", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_LOGIC_OUTS_B14_7", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX19_7", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX12_7", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX44_7", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_LOGIC_OUTS_B16_7", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_LOGIC_OUTS_B13_7", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX43_7", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX35_7", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_LOGIC_OUTS_B21_7", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_IMUX26_7", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B15_7", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_IMUX25_7", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_FAN1_7", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_FAN5_7", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_FAN0_7", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX11_7", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX38_7", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_FAN3_7", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX5_7", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX2_7", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX28_7", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX23_7", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX16_7", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX15_7", - "VBRK_EXT_IMUX15" - ], [ "GTPE2_BYP3_7", "VBRK_EXT_BYP3" ], + [ + "GTPE2_BYP4_7", + "VBRK_EXT_BYP4" + ], + [ + "GTPE2_BYP5_7", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_BYP6_7", + "VBRK_EXT_BYP6" + ], [ "GTPE2_BYP7_7", "VBRK_EXT_BYP7" ], [ - "GTPE2_IMUX36_7", - "VBRK_EXT_IMUX36" + "GTPE2_CLK0_7", + "VBRK_EXT_CLK0" ], [ - "GTPE2_IMUX0_7", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX9_7", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX41_7", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX32_7", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B0_7", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_IMUX4_7", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX27_7", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_LOGIC_OUTS_B6_7", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX7_7", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_LOGIC_OUTS_B4_7", - "VBRK_EXT_LOGIC_OUTS_B4" + "GTPE2_CLK1_7", + "VBRK_EXT_CLK1" ], [ "GTPE2_CTRL0_7", "VBRK_EXT_CTRL0" ], [ - "GTPE2_CLK1_7", - "VBRK_EXT_CLK1" + "GTPE2_CTRL1_7", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_FAN0_7", + "VBRK_EXT_FAN0" + ], + [ + "GTPE2_FAN1_7", + "VBRK_EXT_FAN1" + ], + [ + "GTPE2_FAN2_7", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_FAN3_7", + "VBRK_EXT_FAN3" + ], + [ + "GTPE2_FAN4_7", + "VBRK_EXT_FAN4" + ], + [ + "GTPE2_FAN5_7", + "VBRK_EXT_FAN5" + ], + [ + "GTPE2_FAN6_7", + "VBRK_EXT_FAN6" + ], + [ + "GTPE2_FAN7_7", + "VBRK_EXT_FAN7" + ], + [ + "GTPE2_IMUX0_7", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX1_7", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX2_7", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX3_7", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_IMUX4_7", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX5_7", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_IMUX6_7", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX7_7", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX8_7", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX9_7", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX10_7", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX11_7", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX12_7", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX13_7", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_IMUX14_7", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_IMUX15_7", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX16_7", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_IMUX17_7", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX18_7", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX19_7", + "VBRK_EXT_IMUX19" + ], + [ + "GTPE2_IMUX20_7", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_IMUX21_7", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX22_7", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX23_7", + "VBRK_EXT_IMUX23" + ], + [ + "GTPE2_IMUX24_7", + "VBRK_EXT_IMUX24" + ], + [ + "GTPE2_IMUX25_7", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX26_7", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX27_7", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX28_7", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_IMUX29_7", + "VBRK_EXT_IMUX29" + ], + [ + "GTPE2_IMUX30_7", + "VBRK_EXT_IMUX30" + ], + [ + "GTPE2_IMUX31_7", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_IMUX32_7", + "VBRK_EXT_IMUX32" + ], + [ + "GTPE2_IMUX33_7", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX34_7", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_IMUX35_7", + "VBRK_EXT_IMUX35" + ], + [ + "GTPE2_IMUX36_7", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX37_7", + "VBRK_EXT_IMUX37" + ], + [ + "GTPE2_IMUX38_7", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX39_7", + "VBRK_EXT_IMUX39" + ], + [ + "GTPE2_IMUX40_7", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_IMUX41_7", + "VBRK_EXT_IMUX41" + ], + [ + "GTPE2_IMUX42_7", + "VBRK_EXT_IMUX42" + ], + [ + "GTPE2_IMUX43_7", + "VBRK_EXT_IMUX43" + ], + [ + "GTPE2_IMUX44_7", + "VBRK_EXT_IMUX44" + ], + [ + "GTPE2_IMUX45_7", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_IMUX46_7", + "VBRK_EXT_IMUX46" + ], + [ + "GTPE2_IMUX47_7", + "VBRK_EXT_IMUX47" + ], + [ + "GTPE2_LOGIC_OUTS_B0_7", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTPE2_LOGIC_OUTS_B1_7", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTPE2_LOGIC_OUTS_B2_7", + "VBRK_EXT_LOGIC_OUTS_B2" + ], + [ + "GTPE2_LOGIC_OUTS_B3_7", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTPE2_LOGIC_OUTS_B4_7", + "VBRK_EXT_LOGIC_OUTS_B4" + ], + [ + "GTPE2_LOGIC_OUTS_B5_7", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTPE2_LOGIC_OUTS_B6_7", + "VBRK_EXT_LOGIC_OUTS_B6" + ], + [ + "GTPE2_LOGIC_OUTS_B7_7", + "VBRK_EXT_LOGIC_OUTS_B7" + ], + [ + "GTPE2_LOGIC_OUTS_B9_7", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTPE2_LOGIC_OUTS_B12_7", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTPE2_LOGIC_OUTS_B13_7", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTPE2_LOGIC_OUTS_B14_7", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTPE2_LOGIC_OUTS_B15_7", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTPE2_LOGIC_OUTS_B16_7", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTPE2_LOGIC_OUTS_B18_7", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTPE2_LOGIC_OUTS_B19_7", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTPE2_LOGIC_OUTS_B21_7", + "VBRK_EXT_LOGIC_OUTS_B21" ] ] }, @@ -433381,7769 +351269,10185 @@ -1 ], "tile_types": [ - "GTP_CHANNEL_0", + "GTP_CHANNEL_2", "VBRK_EXT" ], "wire_pairs": [ - [ - "GTPE2_BYP5_6", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX17_6", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX40_6", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX16_6", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX0_6", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B7_6", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX26_6", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX36_6", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_LOGIC_OUTS_B6_6", - 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"VBRK_WW2END0" - ], - [ - "CLK_HROW_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_LH4_2", - "VBRK_LH4" - ], - [ - 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"CLK_HROW_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_LH9_2", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_LH12_2", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_LH5_2", - "VBRK_LH5" - ], - [ - "CLK_HROW_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WL1END2_2", - "VBRK_WL1END2" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "BRAM_L", - "HCLK_BRAM" - ], - "wire_pairs": [ - [ - "BRAM_CASCOUT_ADDRARDADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" - ], - [ - "BRAM_FIFO36_CASCADEOUTB_1", - "HCLK_BRAM_CASCADEB_L" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" + "GTPE2_IMUX23_6", + "VBRK_EXT_IMUX23" ], [ - "BRAM_CASCOUT_ADDRARDADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" + "GTPE2_IMUX24_6", + "VBRK_EXT_IMUX24" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" + "GTPE2_IMUX25_6", + "VBRK_EXT_IMUX25" ], [ - "BRAM_FIFO36_CASCADEOUTA_1", - "HCLK_BRAM_CASCADEA_L" + "GTPE2_IMUX26_6", + "VBRK_EXT_IMUX26" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" + "GTPE2_IMUX27_6", + "VBRK_EXT_IMUX27" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" + "GTPE2_IMUX28_6", + "VBRK_EXT_IMUX28" ], [ - "BRAM_CASCOUT_ADDRARDADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" + "GTPE2_IMUX29_6", + "VBRK_EXT_IMUX29" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" + "GTPE2_IMUX30_6", + "VBRK_EXT_IMUX30" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" + "GTPE2_IMUX31_6", + "VBRK_EXT_IMUX31" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" + "GTPE2_IMUX32_6", + "VBRK_EXT_IMUX32" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" + "GTPE2_IMUX33_6", + "VBRK_EXT_IMUX33" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + "GTPE2_IMUX34_6", + "VBRK_EXT_IMUX34" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + "GTPE2_IMUX35_6", + "VBRK_EXT_IMUX35" ], [ - "BRAM_CASCOUT_ADDRARDADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" + "GTPE2_IMUX36_6", + "VBRK_EXT_IMUX36" ], [ - "BRAM_CASCOUT_ADDRARDADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" + "GTPE2_IMUX37_6", + "VBRK_EXT_IMUX37" ], [ - "BRAM_CASCOUT_ADDRARDADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" + "GTPE2_IMUX38_6", + "VBRK_EXT_IMUX38" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" + "GTPE2_IMUX39_6", + "VBRK_EXT_IMUX39" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" + "GTPE2_IMUX40_6", + "VBRK_EXT_IMUX40" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" + "GTPE2_IMUX41_6", + "VBRK_EXT_IMUX41" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" + "GTPE2_IMUX42_6", + "VBRK_EXT_IMUX42" ], [ - "BRAM_CASCOUT_ADDRARDADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" + "GTPE2_IMUX43_6", + "VBRK_EXT_IMUX43" ], [ - "BRAM_CASCOUT_ADDRARDADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" + "GTPE2_IMUX44_6", + "VBRK_EXT_IMUX44" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" + "GTPE2_IMUX45_6", + "VBRK_EXT_IMUX45" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" + "GTPE2_IMUX46_6", + "VBRK_EXT_IMUX46" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" + "GTPE2_IMUX47_6", + "VBRK_EXT_IMUX47" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" + "GTPE2_LOGIC_OUTS_B0_6", + "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" + "GTPE2_LOGIC_OUTS_B1_6", + "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" + "GTPE2_LOGIC_OUTS_B2_6", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" + "GTPE2_LOGIC_OUTS_B3_6", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + "GTPE2_LOGIC_OUTS_B4_6", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "BRAM_CASCOUT_ADDRARDADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" + "GTPE2_LOGIC_OUTS_B5_6", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" + "GTPE2_LOGIC_OUTS_B6_6", + "VBRK_EXT_LOGIC_OUTS_B6" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" + "GTPE2_LOGIC_OUTS_B7_6", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + "GTPE2_LOGIC_OUTS_B9_6", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "BRAM_CASCOUT_ADDRARDADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" + "GTPE2_LOGIC_OUTS_B10_6", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" + "GTPE2_LOGIC_OUTS_B12_6", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" + "GTPE2_LOGIC_OUTS_B13_6", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "BRAM_CASCOUT_ADDRARDADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" + "GTPE2_LOGIC_OUTS_B14_6", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" + "GTPE2_LOGIC_OUTS_B15_6", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "BRAM_CASCOUT_ADDRBWRADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" + "GTPE2_LOGIC_OUTS_B17_6", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" + "GTPE2_LOGIC_OUTS_B19_6", + "VBRK_EXT_LOGIC_OUTS_B19" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" + "GTPE2_LOGIC_OUTS_B21_6", + "VBRK_EXT_LOGIC_OUTS_B21" ], [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" + "GTPE2_LOGIC_OUTS_B22_6", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" + "GTPE2_LOGIC_OUTS_B23_6", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }, { "grid_deltas": [ -1, - -1 - ], - "tile_types": [ - "RIOI3_TBYTESRC", - "R_TERM_INT" - ], - "wire_pairs": [ - [ - "IOI_IMUX24_1", - "TERM_INT_IMUX24" - ], - [ - "IOI_BYP3_1", - "TERM_INT_BYP3" - ], - [ - "IOI_LOGIC_OUTS8_1", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_IMUX46_1", - "TERM_INT_IMUX46" - ], - [ - "IOI_BLOCK_OUTS0_1", - "TERM_INT_BLOCK_OUTS_L_B0" - ], - [ - "IOI_CLK0_1", - "TERM_INT_CLK0" - ], - [ - "IOI_LOGIC_OUTS19_1", - "TERM_INT_LOGIC_OUTS_L_B19" - ], - [ - "IOI_IMUX39_1", - "TERM_INT_IMUX39" - ], - [ - "IOI_IMUX42_1", - "TERM_INT_IMUX42" - ], - [ - "IOI_IMUX27_1", - "TERM_INT_IMUX27" - ], - [ - "IOI_IMUX12_1", - "TERM_INT_IMUX12" - ], - [ - "IOI_IMUX8_1", - "TERM_INT_IMUX8" - ], - [ - "IOI_IMUX14_1", - "TERM_INT_IMUX14" - ], - [ - "IOI_IMUX19_1", - "TERM_INT_IMUX19" - ], - [ - "IOI_BYP7_1", - "TERM_INT_BYP7" - ], - [ - "IOI_BYP2_1", - "TERM_INT_BYP2" - ], - [ - "IOI_LOGIC_OUTS3_1", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_LOGIC_OUTS0_1", - "TERM_INT_LOGIC_OUTS_L_B0" - ], - [ - "IOI_IMUX29_1", - "TERM_INT_IMUX29" - ], - [ - "IOI_IMUX10_1", - "TERM_INT_IMUX10" - ], - [ - "IOI_LOGIC_OUTS23_1", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "IOI_IMUX2_1", - "TERM_INT_IMUX2" - ], - [ - "IOI_BYP5_1", - "TERM_INT_BYP5" - ], - [ - "IOI_CTRL1_1", - "TERM_INT_CTRL1" - ], - [ - "IOI_FAN2_1", - "TERM_INT_FAN2" - ], - [ - "IOI_IMUX20_1", - "TERM_INT_IMUX20" - ], - [ - "IOI_BYP1_1", - "TERM_INT_BYP1" - ], - [ - "IOI_IMUX21_1", - "TERM_INT_IMUX21" - ], - [ - "IOI_IMUX26_1", - "TERM_INT_IMUX26" - ], - [ - "IOI_IMUX32_1", - "TERM_INT_IMUX32" - ], - [ - "IOI_IMUX35_1", - "TERM_INT_IMUX35" - ], - [ - "IOI_FAN6_1", - "TERM_INT_FAN6" - ], - [ - "IOI_IMUX36_1", - "TERM_INT_IMUX36" - ], - [ - "IOI_CTRL0_1", - "TERM_INT_CTRL0" - ], - [ - "IOI_IMUX18_1", - "TERM_INT_IMUX18" - ], - [ - "IOI_LOGIC_OUTS11_1", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "IOI_FAN5_1", - "TERM_INT_FAN5" - ], - [ - "IOI_PHASER_TO_IO_ICLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" - ], - [ - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" - ], - [ - "IOI_IMUX9_1", - "TERM_INT_IMUX9" - ], - [ - "IOI_IMUX40_1", - "TERM_INT_IMUX40" - ], - [ - "IOI_IMUX3_1", - "TERM_INT_IMUX3" - ], - [ - "IOI_IMUX7_1", - "TERM_INT_IMUX7" - ], - [ - "IOI_IMUX0_1", - "TERM_INT_IMUX0" - ], - [ - "IOI_FAN0_1", - "TERM_INT_FAN0" - ], - [ - "IOI_IMUX37_1", - "TERM_INT_IMUX37" - ], - [ - "IOI_PHASER_TO_IO_OCLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "IOI_LOGIC_OUTS14_1", - "TERM_INT_LOGIC_OUTS_L_B14" - ], - [ - "IOI_FAN1_1", - "TERM_INT_FAN1" - ], - [ - "IOI_FAN4_1", - "TERM_INT_FAN4" - ], - [ - "IOI_IMUX1_1", - "TERM_INT_IMUX1" - ], - [ - "IOI_LOGIC_OUTS10_1", - "TERM_INT_LOGIC_OUTS_L_B10" - ], - [ - "IOI_IMUX33_1", - "TERM_INT_IMUX33" - ], - [ - "IOI_IMUX34_1", - "TERM_INT_IMUX34" - ], - [ - "IOI_IMUX4_1", - "TERM_INT_IMUX4" - ], - [ - "IOI_IMUX38_1", - "TERM_INT_IMUX38" - ], - [ - "IOI_IMUX15_1", - "TERM_INT_IMUX15" - ], - [ - "IOI_IMUX30_1", - "TERM_INT_IMUX30" - ], - [ - "IOI_IMUX11_1", - "TERM_INT_IMUX11" - ], - [ - "IOI_IMUX5_1", - "TERM_INT_IMUX5" - ], - [ - "IOI_IMUX28_1", - "TERM_INT_IMUX28" - ], - [ - "IOI_CLK1_1", - "TERM_INT_CLK1" - ], - [ - "IOI_IMUX16_1", - "TERM_INT_IMUX16" - ], - [ - "IOI_IMUX43_1", - "TERM_INT_IMUX43" - ], - [ - "IOI_IMUX31_1", - "TERM_INT_IMUX31" - ], - [ - "IOI_IMUX13_1", - "TERM_INT_IMUX13" - ], - [ - "IOI_IMUX44_1", - "TERM_INT_IMUX44" - ], - [ - "IOI_LOGIC_OUTS18_1", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "IOI_IMUX22_1", - "TERM_INT_IMUX22" - ], - [ - "IOI_LOGIC_OUTS7_1", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_FAN3_1", - "TERM_INT_FAN3" - ], - [ - "IOI_LOGIC_OUTS5_1", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_PHASER_TO_IO_OCLK_0", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_LOGIC_OUTS20_1", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_IMUX47_1", - "TERM_INT_IMUX47" - ], - [ - "IOI_IMUX17_1", - "TERM_INT_IMUX17" - ], - [ - "IOI_LOGIC_OUTS15_1", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_BLOCK_OUTS2_1", - "TERM_INT_BLOCK_OUTS_L_B2" - ], - [ - "IOI_PHASER_TO_IO_ICLK_0", - "L_TERM_INT_PHASER_TO_IO_ICLK" - ], - [ - "IOI_BYP4_1", - "TERM_INT_BYP4" - ], - [ - "IOI_IMUX45_1", - "TERM_INT_IMUX45" - ], - [ - "IOI_FAN7_1", - "TERM_INT_FAN7" - ], - [ - "IOI_BYP0_1", - "TERM_INT_BYP0" - ], - [ - "IOI_IMUX23_1", - "TERM_INT_IMUX23" - ], - [ - "IOI_LOGIC_OUTS1_1", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_IMUX25_1", - "TERM_INT_IMUX25" - ], - [ - "IOI_LOGIC_OUTS9_1", - "TERM_INT_LOGIC_OUTS_L_B9" - ], - [ - "IOI_LOGIC_OUTS2_1", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "IOI_IMUX6_1", - "TERM_INT_IMUX6" - ], - [ - "IOI_BYP6_1", - "TERM_INT_BYP6" - ], - [ - "IOI_IMUX41_1", - "TERM_INT_IMUX41" - ] - ] - }, - { - "grid_deltas": [ - 1, - -9 - ], - "tile_types": [ - "MONITOR_MID", - "VFRAME" - ], - "wire_pairs": [ - [ - "MONITOR_IMUX19_9", - "VFRAME_IMUX19" - ], - [ - "MONITOR_SW2A2_9", - "VFRAME_SW2A2" - ], - [ - "MONITOR_IMUX5_9", - "VFRAME_IMUX5" - ], - [ - "MONITOR_IMUX13_9", - "VFRAME_IMUX13" - ], - [ - "MONITOR_NE4C3_9", - "VFRAME_NE4C3" - ], - [ - "MONITOR_NE4BEG2_9", - "VFRAME_NE4BEG2" - ], - [ - "MONITOR_IMUX39_9", - "VFRAME_IMUX39" - ], - [ - "MONITOR_SW4A1_9", - "VFRAME_SW4A1" - ], - [ - "MONITOR_BYP5_9", - "VFRAME_BYP5" - ], - [ - "MONITOR_WW4B0_9", - "VFRAME_WW4B0" - ], - [ - "MONITOR_WL1END0_9", - "VFRAME_WL1END0" - ], - [ - "MONITOR_WW2A3_9", - "VFRAME_WW2A3" - ], - [ - "MONITOR_SE4BEG1_9", - "VFRAME_SE4BEG1" - ], - [ - "MONITOR_EE4BEG3_9", - "VFRAME_EE4BEG3" - ], - [ - "MONITOR_IMUX0_9", - "VFRAME_IMUX0" - ], - [ - "MONITOR_EE4C0_9", - "VFRAME_EE4C0" - ], - [ - "MONITOR_EE2BEG1_9", - "VFRAME_EE2BEG1" - ], - [ - "MONITOR_EE2BEG0_9", - "VFRAME_EE2BEG0" - ], - [ - "MONITOR_IMUX6_9", - "VFRAME_IMUX6" - ], - [ - "MONITOR_NW4A3_9", - "VFRAME_NW4A3" - ], - [ - "MONITOR_FAN6_9", - "VFRAME_FAN6" - ], - [ - "MONITOR_WW4C0_9", - "VFRAME_WW4C0" - ], - [ - "MONITOR_SE4C1_9", - "VFRAME_SE4C1" - ], - [ - "MONITOR_EE2BEG2_9", - "VFRAME_EE2BEG2" - ], - [ - "MONITOR_EE4A1_9", - "VFRAME_EE4A1" - ], - [ - "MONITOR_EE4C3_9", - "VFRAME_EE4C3" - ], - [ - "MONITOR_NE2A1_9", - "VFRAME_NE2A1" - ], - [ - "MONITOR_WW4C3_9", - "VFRAME_WW4C3" - ], - [ - "MONITOR_SE4C0_9", - "VFRAME_SE4C0" - ], - [ - "MONITOR_CLK1_9", - "VFRAME_CLK1" - ], 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"wire_pairs": [ [ - "DSP_EE2BEG1_0", - "VBRK_EE2BEG1" + "GTPE2_BYP0_5", + "VBRK_EXT_BYP0" ], [ - "DSP_WW4B0_0", - "VBRK_WW4B0" + "GTPE2_BYP1_5", + "VBRK_EXT_BYP1" ], [ - "DSP_SE4BEG3_0", - "VBRK_SE4BEG3" + "GTPE2_BYP2_5", + "VBRK_EXT_BYP2" ], [ - "DSP_ER1BEG2_0", - "VBRK_ER1BEG2" + "GTPE2_BYP3_5", + "VBRK_EXT_BYP3" ], [ - "DSP_MONITOR_N_0", - "VBRK_MONITOR_N" + "GTPE2_BYP4_5", + "VBRK_EXT_BYP4" ], [ - "DSP_SW4A0_0", - "VBRK_SW4A0" + "GTPE2_BYP5_5", + "VBRK_EXT_BYP5" ], [ - "DSP_WW4B2_0", - "VBRK_WW4B2" + "GTPE2_BYP6_5", + "VBRK_EXT_BYP6" ], [ - "DSP_NW4END0_0", - "VBRK_NW4END0" + "GTPE2_BYP7_5", + "VBRK_EXT_BYP7" ], [ - "DSP_NE4BEG3_0", - "VBRK_NE4BEG3" + "GTPE2_CLK0_5", + "VBRK_EXT_CLK0" ], [ - "DSP_EE4A2_0", - "VBRK_EE4A2" + "GTPE2_CLK1_5", + "VBRK_EXT_CLK1" ], [ - "DSP_EE4C2_0", - "VBRK_EE4C2" + "GTPE2_CTRL0_5", + "VBRK_EXT_CTRL0" ], [ - "DSP_EE4BEG3_0", - "VBRK_EE4BEG3" + "GTPE2_CTRL1_5", + "VBRK_EXT_CTRL1" ], [ - "DSP_WR1END2_0", - "VBRK_WR1END2" + "GTPE2_FAN0_5", + "VBRK_EXT_FAN0" ], [ - "DSP_SE4C0_0", - "VBRK_SE4C0" + "GTPE2_FAN1_5", + "VBRK_EXT_FAN1" ], [ - "DSP_SW4END3_0", - "VBRK_SW4END3" + "GTPE2_FAN2_5", + "VBRK_EXT_FAN2" ], [ - "DSP_EE4A0_0", - "VBRK_EE4A0" + "GTPE2_FAN3_5", + "VBRK_EXT_FAN3" ], [ - "DSP_SE4C2_0", - "VBRK_SE4C2" + "GTPE2_FAN4_5", + "VBRK_EXT_FAN4" ], [ - "DSP_NE2A1_0", - "VBRK_NE2A1" + "GTPE2_FAN5_5", + "VBRK_EXT_FAN5" ], [ - "DSP_LH11_0", - "VBRK_LH11" + "GTPE2_FAN6_5", + "VBRK_EXT_FAN6" ], [ - "DSP_WW4B1_0", - "VBRK_WW4B1" + "GTPE2_FAN7_5", + "VBRK_EXT_FAN7" ], [ - "DSP_EE4C3_0", - "VBRK_EE4C3" + "GTPE2_IMUX0_5", + "VBRK_EXT_IMUX0" ], [ - "DSP_LH7_0", - "VBRK_LH7" + "GTPE2_IMUX1_5", + "VBRK_EXT_IMUX1" ], [ - "DSP_NE2A2_0", - "VBRK_NE2A2" + "GTPE2_IMUX2_5", + "VBRK_EXT_IMUX2" ], [ - "DSP_NE4C0_0", - "VBRK_NE4C0" + "GTPE2_IMUX3_5", + "VBRK_EXT_IMUX3" ], [ - "DSP_NW4A1_0", - "VBRK_NW4A1" + "GTPE2_IMUX4_5", + "VBRK_EXT_IMUX4" ], [ - "DSP_WW2A1_0", - "VBRK_WW2A1" + "GTPE2_IMUX5_5", + "VBRK_EXT_IMUX5" ], [ - "DSP_WL1END1_0", - "VBRK_WL1END1" + "GTPE2_IMUX6_5", + "VBRK_EXT_IMUX6" ], [ - "DSP_NE4BEG1_0", - "VBRK_NE4BEG1" + "GTPE2_IMUX7_5", + "VBRK_EXT_IMUX7" ], [ - "DSP_EE4B1_0", - "VBRK_EE4B1" + "GTPE2_IMUX8_5", + "VBRK_EXT_IMUX8" ], [ - "DSP_EE2A1_0", - "VBRK_EE2A1" + "GTPE2_IMUX9_5", + "VBRK_EXT_IMUX9" ], [ - "DSP_NE4C3_0", - "VBRK_NE4C3" + "GTPE2_IMUX10_5", + "VBRK_EXT_IMUX10" ], [ - "DSP_NW4END3_0", - "VBRK_NW4END3" + "GTPE2_IMUX11_5", + "VBRK_EXT_IMUX11" ], [ - "DSP_SW2A1_0", - "VBRK_SW2A1" + "GTPE2_IMUX12_5", + "VBRK_EXT_IMUX12" ], [ - "DSP_SW2A2_0", - "VBRK_SW2A2" + "GTPE2_IMUX13_5", + "VBRK_EXT_IMUX13" ], [ - "DSP_EL1BEG3_0", - "VBRK_EL1BEG3" + "GTPE2_IMUX14_5", + "VBRK_EXT_IMUX14" ], [ - "DSP_LH10_0", - "VBRK_LH10" + "GTPE2_IMUX15_5", + "VBRK_EXT_IMUX15" ], [ - "DSP_SW4A1_0", - "VBRK_SW4A1" + "GTPE2_IMUX16_5", + "VBRK_EXT_IMUX16" ], [ - "DSP_WW4C0_0", - "VBRK_WW4C0" + "GTPE2_IMUX17_5", + "VBRK_EXT_IMUX17" ], [ - "DSP_LH12_0", - "VBRK_LH12" + "GTPE2_IMUX18_5", + "VBRK_EXT_IMUX18" ], [ - "DSP_WW4A1_0", - "VBRK_WW4A1" + "GTPE2_IMUX19_5", + "VBRK_EXT_IMUX19" ], [ - "DSP_SE4BEG1_0", - "VBRK_SE4BEG1" + "GTPE2_IMUX20_5", + "VBRK_EXT_IMUX20" ], [ - "DSP_ER1BEG3_0", - "VBRK_ER1BEG3" + "GTPE2_IMUX21_5", + "VBRK_EXT_IMUX21" ], [ - "DSP_EE4A1_0", - "VBRK_EE4A1" + "GTPE2_IMUX22_5", + "VBRK_EXT_IMUX22" ], [ - "DSP_WW4END2_0", - "VBRK_WW4END2" + "GTPE2_IMUX23_5", + "VBRK_EXT_IMUX23" ], [ - "DSP_NW2A3_0", - "VBRK_NW2A3" + "GTPE2_IMUX24_5", + "VBRK_EXT_IMUX24" ], [ - "DSP_SW2A0_0", - "VBRK_SW2A0" + "GTPE2_IMUX25_5", + "VBRK_EXT_IMUX25" ], [ - "DSP_EE4B0_0", - "VBRK_EE4B0" + "GTPE2_IMUX26_5", + "VBRK_EXT_IMUX26" ], [ - "DSP_MONITOR_P_0", - "VBRK_MONITOR_P" + "GTPE2_IMUX27_5", + "VBRK_EXT_IMUX27" ], [ - "DSP_SE2A3_0", - "VBRK_SE2A3" + "GTPE2_IMUX28_5", + "VBRK_EXT_IMUX28" ], [ - "DSP_WR1END0_0", - "VBRK_WR1END0" + "GTPE2_IMUX29_5", + "VBRK_EXT_IMUX29" ], [ - "DSP_SE4C3_0", - "VBRK_SE4C3" + "GTPE2_IMUX30_5", + "VBRK_EXT_IMUX30" ], [ - "DSP_SW4END0_0", - "VBRK_SW4END0" + "GTPE2_IMUX31_5", + "VBRK_EXT_IMUX31" ], [ - "DSP_SW2A3_0", - "VBRK_SW2A3" + "GTPE2_IMUX32_5", + "VBRK_EXT_IMUX32" ], [ - "DSP_SW4A2_0", - "VBRK_SW4A2" + "GTPE2_IMUX33_5", + "VBRK_EXT_IMUX33" ], [ - "DSP_NW2A1_0", - "VBRK_NW2A1" + "GTPE2_IMUX34_5", + "VBRK_EXT_IMUX34" ], [ - "DSP_WW4A0_0", - "VBRK_WW4A0" + "GTPE2_IMUX35_5", + "VBRK_EXT_IMUX35" ], [ - "DSP_WW4END1_0", - "VBRK_WW4END1" + "GTPE2_IMUX36_5", + "VBRK_EXT_IMUX36" ], [ - "DSP_NW4A0_0", - "VBRK_NW4A0" + "GTPE2_IMUX37_5", + "VBRK_EXT_IMUX37" ], [ - "DSP_WR1END1_0", - "VBRK_WR1END1" + "GTPE2_IMUX38_5", + "VBRK_EXT_IMUX38" ], [ - "DSP_WW4B3_0", - "VBRK_WW4B3" + "GTPE2_IMUX39_5", + "VBRK_EXT_IMUX39" ], [ - "DSP_WW2END1_0", - "VBRK_WW2END1" + "GTPE2_IMUX40_5", + "VBRK_EXT_IMUX40" ], [ - "DSP_EE2BEG3_0", - "VBRK_EE2BEG3" + "GTPE2_IMUX41_5", + "VBRK_EXT_IMUX41" ], [ - "DSP_WW4C3_0", - "VBRK_WW4C3" + "GTPE2_IMUX42_5", + "VBRK_EXT_IMUX42" ], [ - "DSP_WL1END0_0", - "VBRK_WL1END0" + "GTPE2_IMUX43_5", + "VBRK_EXT_IMUX43" ], [ - "DSP_WW2END3_0", - "VBRK_WW2END3" + "GTPE2_IMUX44_5", + "VBRK_EXT_IMUX44" ], [ - "DSP_EE4BEG1_0", - "VBRK_EE4BEG1" + "GTPE2_IMUX45_5", + "VBRK_EXT_IMUX45" ], [ - "DSP_WW2END2_0", - "VBRK_WW2END2" + "GTPE2_IMUX46_5", + "VBRK_EXT_IMUX46" ], [ - "DSP_SW4END2_0", - "VBRK_SW4END2" + "GTPE2_IMUX47_5", + "VBRK_EXT_IMUX47" ], [ - "DSP_NE4BEG0_0", - "VBRK_NE4BEG0" + "GTPE2_LOGIC_OUTS_B0_5", + "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "DSP_WR1END3_0", - "VBRK_WR1END3" + "GTPE2_LOGIC_OUTS_B1_5", + "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "DSP_EE4B3_0", - "VBRK_EE4B3" + "GTPE2_LOGIC_OUTS_B2_5", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ - "DSP_WW2A0_0", - "VBRK_WW2A0" + "GTPE2_LOGIC_OUTS_B3_5", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "DSP_NE2A3_0", - "VBRK_NE2A3" + "GTPE2_LOGIC_OUTS_B4_5", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "DSP_NE4C1_0", - "VBRK_NE4C1" + "GTPE2_LOGIC_OUTS_B5_5", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "DSP_EL1BEG0_0", - "VBRK_EL1BEG0" + "GTPE2_LOGIC_OUTS_B6_5", + "VBRK_EXT_LOGIC_OUTS_B6" ], [ - "DSP_NE4BEG2_0", - "VBRK_NE4BEG2" + "GTPE2_LOGIC_OUTS_B7_5", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "DSP_NW4A3_0", - "VBRK_NW4A3" + "GTPE2_LOGIC_OUTS_B9_5", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "DSP_LH1_0", - "VBRK_LH1" + "GTPE2_LOGIC_OUTS_B10_5", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "DSP_LH9_0", - "VBRK_LH9" + "GTPE2_LOGIC_OUTS_B12_5", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "DSP_NW2A2_0", - "VBRK_NW2A2" + "GTPE2_LOGIC_OUTS_B13_5", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "DSP_WW4A2_0", - "VBRK_WW4A2" + "GTPE2_LOGIC_OUTS_B14_5", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "DSP_EE4B2_0", - "VBRK_EE4B2" + "GTPE2_LOGIC_OUTS_B15_5", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "DSP_EE4C0_0", - "VBRK_EE4C0" + "GTPE2_LOGIC_OUTS_B17_5", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "DSP_ER1BEG1_0", - "VBRK_ER1BEG1" + "GTPE2_LOGIC_OUTS_B21_5", + "VBRK_EXT_LOGIC_OUTS_B21" ], [ - "DSP_LH2_0", - "VBRK_LH2" + "GTPE2_LOGIC_OUTS_B22_5", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "DSP_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "DSP_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "DSP_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "DSP_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "DSP_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "DSP_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "DSP_LH5_0", - "VBRK_LH5" - ], - [ - "DSP_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "DSP_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "DSP_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "DSP_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "DSP_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "DSP_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "DSP_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "DSP_LH6_0", - "VBRK_LH6" - ], - [ - "DSP_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "DSP_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "DSP_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "DSP_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "DSP_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "DSP_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "DSP_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "DSP_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "DSP_LH8_0", - "VBRK_LH8" - ], - [ - "DSP_LH3_0", - "VBRK_LH3" - ], - [ - "DSP_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "DSP_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "DSP_LH4_0", - "VBRK_LH4" - ], - [ - "DSP_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "DSP_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "DSP_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "DSP_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "DSP_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "DSP_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "DSP_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "DSP_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "DSP_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "DSP_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "DSP_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "DSP_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "DSP_EE4C1_0", - "VBRK_EE4C1" + "GTPE2_LOGIC_OUTS_B23_5", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }, { "grid_deltas": [ -1, - 4 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH1_0", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_SW4END2_0", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_MONITOR_N_0", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NW4END2_0", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_WL1END2_0", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_WR1END3_0", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_MONITOR_P_0", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_SE2A0_0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_LH9_0", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_SW4END0_0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_SE4C0_0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "BRKH_CLB", - "CLBLM_L" - ], - "wire_pairs": [ - [ - "BRKH_CLB_COUT1_L", - "CLBLM_L_CIN" - ], - [ - "BRKH_CLB_COUT0_L", - "CLBLM_M_CIN" - ] - ] - }, - { - "grid_deltas": [ - 1, - -3 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_LH5_4", - "VBRK_LH5" - ], - [ - "CMT_TOP_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_LH11_4", - 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"INT_FEEDTHRU_2_NW2A3" + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_CLB_CK_BUFHCLK6" ], [ - "CFG_CENTER_SW4END1_7", - "INT_FEEDTHRU_2_SW4END1" - ], - [ - "CFG_CENTER_NW2A0_7", - "INT_FEEDTHRU_2_NW2A0" - ], - [ - "CFG_CENTER_SW4A2_7", - "INT_FEEDTHRU_2_SW4A2" - ], - [ - "CFG_CENTER_WW4END2_7", - "INT_FEEDTHRU_2_WW4END2" - ], - [ - "CFG_CENTER_SW2A2_7", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_SE4C0_7", - "INT_FEEDTHRU_2_SE4C0" - ], - [ - "CFG_CENTER_WW2A2_7", - "INT_FEEDTHRU_2_WW2A2" - ], - [ - "CFG_CENTER_NE4C3_7", - "INT_FEEDTHRU_2_NE4C3" - ], - [ - "CFG_CENTER_EL1BEG1_7", - "INT_FEEDTHRU_2_EL1BEG1" - ], - [ - "CFG_CENTER_EE4B0_7", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_SW2A1_7", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_SE4BEG1_7", - "INT_FEEDTHRU_2_SE4BEG1" - ], - [ - "CFG_CENTER_WR1END1_7", - "INT_FEEDTHRU_2_WR1END1" - ], - [ - "CFG_CENTER_SW2A0_7", - "INT_FEEDTHRU_2_SW2A0" - ], - [ - "CFG_CENTER_NE4BEG2_7", - "INT_FEEDTHRU_2_NE4BEG2" - ], - [ - "CFG_CENTER_WW2END0_7", - "INT_FEEDTHRU_2_WW2END0" - ], - [ - "CFG_CENTER_EE4B3_7", - "INT_FEEDTHRU_2_EE4B3" - ], - [ - "CFG_CENTER_SE4BEG0_7", - "INT_FEEDTHRU_2_SE4BEG0" - ], - [ - "CFG_CENTER_SW4END3_7", - "INT_FEEDTHRU_2_SW4END3" - ], - [ - "CFG_CENTER_WW4C0_7", - "INT_FEEDTHRU_2_WW4C0" - ], - [ - "CFG_CENTER_EE2A0_7", - "INT_FEEDTHRU_2_EE2A0" - ], - [ - "CFG_CENTER_NE4C0_7", - "INT_FEEDTHRU_2_NE4C0" - ], - [ - "CFG_CENTER_NW4A1_7", - "INT_FEEDTHRU_2_NW4A1" - ], - [ - "CFG_CENTER_NE2A1_7", - "INT_FEEDTHRU_2_NE2A1" - ], - [ - "CFG_CENTER_WW4A0_7", - "INT_FEEDTHRU_2_WW4A0" - ], - [ - "CFG_CENTER_SE4BEG2_7", - "INT_FEEDTHRU_2_SE4BEG2" - ], - [ - "CFG_CENTER_ER1BEG0_7", - "INT_FEEDTHRU_2_ER1BEG0" - ], - [ - "CFG_CENTER_WW4C1_7", - "INT_FEEDTHRU_2_WW4C1" - ], - [ - "CFG_CENTER_WW2A3_7", - "INT_FEEDTHRU_2_WW2A3" - ], - [ - "CFG_CENTER_SW4A1_7", - "INT_FEEDTHRU_2_SW4A1" - ] - ] - }, - { - "grid_deltas": [ - 1, - 7 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_NE4C1_1", - "VBRK_NE4C1" + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_CLB_CK_BUFHCLK7" ], [ - "CMT_TOP_SE4BEG2_1", - "VBRK_SE4BEG2" + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_CLB_CK_BUFHCLK8" ], [ - "CMT_TOP_SW4A3_1", - "VBRK_SW4A3" + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_CLB_CK_BUFHCLK9" ], [ - "CMT_TOP_WW4B0_1", - "VBRK_WW4B0" + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_CLB_CK_BUFHCLK10" ], [ - "CMT_TOP_SW4END3_1", - "VBRK_SW4END3" + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_CLB_CK_BUFHCLK11" ], [ - "CMT_TOP_EE4BEG1_1", - "VBRK_EE4BEG1" + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_CLB_CK_BUFRCLK0" ], [ - "CMT_TOP_WR1END2_1", - "VBRK_WR1END2" + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_CLB_CK_BUFRCLK1" ], [ - "CMT_TOP_SW2A3_1", - "VBRK_SW2A3" + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_CLB_CK_BUFRCLK2" ], [ - "CMT_TOP_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_LH3_1", - "VBRK_LH3" - ], - [ - "CMT_TOP_LH4_1", - "VBRK_LH4" - ], - [ - "CMT_TOP_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_LH6_1", - "VBRK_LH6" - ], - [ - "CMT_TOP_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_LH7_1", - "VBRK_LH7" - ], - [ - "CMT_TOP_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_LH8_1", - "VBRK_LH8" - ], - [ - "CMT_TOP_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CMT_TOP_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_LH12_1", - "VBRK_LH12" - ], - [ - "CMT_TOP_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_LH10_1", - "VBRK_LH10" - ], - [ - "CMT_TOP_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_LH2_1", - "VBRK_LH2" - ], - [ - "CMT_TOP_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_LH1_1", - "VBRK_LH1" - ], - [ - "CMT_TOP_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_LH11_1", - "VBRK_LH11" - ], - [ - "CMT_TOP_LH5_1", - "VBRK_LH5" - ], - [ - "CMT_TOP_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_LH9_1", - "VBRK_LH9" - ], - [ - "CMT_TOP_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_WW2END2_1", - "VBRK_WW2END2" - ] - ] - }, - { - "grid_deltas": [ - 0, - -2 - ], - "tile_types": [ - "LIOI3", - "LIOI3_SING" - ], - "wire_pairs": [ - [ - "IOI_IOCLK1", - "IOI_SING_IOCLK1" + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_CLB_CK_BUFRCLK3" ], [ - "IOI_IOCLK0", - "IOI_SING_IOCLK0" + "HCLK_BRAM_CK_IN0", + "HCLK_CLB_CK_IN0" ], [ - "IOI_LEAF_GCLK5", - "IOI_SING_LEAF_GCLK5" + "HCLK_BRAM_CK_IN1", + "HCLK_CLB_CK_IN1" ], [ - "IOI_RCLK_FORIO1", - "IOI_SING_RCLK_FORIO1" + "HCLK_BRAM_CK_IN2", + "HCLK_CLB_CK_IN2" ], [ - "IOI_LEAF_GCLK4", - "IOI_SING_LEAF_GCLK4" + "HCLK_BRAM_CK_IN3", + "HCLK_CLB_CK_IN3" ], [ - "IOI_LEAF_GCLK2", - "IOI_SING_LEAF_GCLK2" + "HCLK_BRAM_CK_IN4", + "HCLK_CLB_CK_IN4" ], [ - "IOI_RCLK_FORIO0", - "IOI_SING_RCLK_FORIO0" + "HCLK_BRAM_CK_IN5", + "HCLK_CLB_CK_IN5" ], [ - "IOI_IOCLK3", - "IOI_SING_IOCLK3" + "HCLK_BRAM_CK_IN6", + "HCLK_CLB_CK_IN6" ], [ - "IOI_RCLK_FORIO3", - "IOI_SING_RCLK_FORIO3" + "HCLK_BRAM_CK_IN7", + "HCLK_CLB_CK_IN7" ], [ - "IOI_LEAF_GCLK0", - "IOI_SING_LEAF_GCLK0" + "HCLK_BRAM_CK_IN8", + "HCLK_CLB_CK_IN8" ], [ - "IOI_LEAF_GCLK3", - "IOI_SING_LEAF_GCLK3" + "HCLK_BRAM_CK_IN9", + "HCLK_CLB_CK_IN9" ], [ - "IOI_TBYTEIN", - "IOI_SING_TBYTEIN" + "HCLK_BRAM_CK_IN10", + "HCLK_CLB_CK_IN10" ], [ - "IOI_LEAF_GCLK1", - "IOI_SING_LEAF_GCLK1" + "HCLK_BRAM_CK_IN11", + "HCLK_CLB_CK_IN11" ], [ - "IOI_RCLK_FORIO2", - "IOI_SING_RCLK_FORIO2" + "HCLK_BRAM_CK_IN12", + "HCLK_CLB_CK_IN12" ], [ - "IOI_IOCLK2", - "IOI_SING_IOCLK2" + "HCLK_BRAM_CK_IN13", + "HCLK_CLB_CK_IN13" ] ] }, @@ -441153,11013 +361457,129 @@ 0 ], "tile_types": [ - "HCLK_CLB", - "HCLK_R" - ], - "wire_pairs": [ - [ - "HCLK_CLB_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_CK_IN2", - "HCLK_CK_IN2" - ], - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CLB_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK2" - ], - [ - "HCLK_CLB_CK_IN1", - "HCLK_CK_IN1" - ], - [ - "HCLK_CLB_PERFCLK2", - "HCLK_INT_PERFCLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ], - [ - "HCLK_CLB_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - "HCLK_CLB_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK0" - ], - [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_CK_BUFRCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_CLB_PERFCLK1", - "HCLK_INT_PERFCLK1" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_CLB_CK_IN3", - "HCLK_CK_IN3" - ], - [ - "HCLK_CLB_CK_IN0", - "HCLK_CK_IN0" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_CLB_PERFCLK3", - "HCLK_INT_PERFCLK3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CFG_CENTER_MID", - "INT_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "CFG_CENTER_ER1BEG2_10", - "INT_FEEDTHRU_2_ER1BEG2" - ], - [ - "CFG_CENTER_SW2A1_10", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_SE4BEG2_10", - "INT_FEEDTHRU_2_SE4BEG2" - ], - [ - "CFG_CENTER_SW4A2_10", - "INT_FEEDTHRU_2_SW4A2" - ], - [ - "CFG_CENTER_NE4BEG2_10", - "INT_FEEDTHRU_2_NE4BEG2" - ], - [ - "CFG_CENTER_SE4BEG1_10", - "INT_FEEDTHRU_2_SE4BEG1" - ], - [ - "CFG_CENTER_WL1END1_10", - "INT_FEEDTHRU_2_WL1END1" - ], - [ - "CFG_CENTER_WW4A3_10", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_LH10_10", - "INT_FEEDTHRU_2_LH10" - ], - [ - "CFG_CENTER_NE4C1_10", - "INT_FEEDTHRU_2_NE4C1" - ], - [ - "CFG_CENTER_EE2BEG2_10", - "INT_FEEDTHRU_2_EE2BEG2" - ], - [ - "CFG_CENTER_NW4A0_10", - "INT_FEEDTHRU_2_NW4A0" - ], - [ - "CFG_CENTER_NE4BEG3_10", - "INT_FEEDTHRU_2_NE4BEG3" - ], - [ - "CFG_CENTER_SE4C0_10", - "INT_FEEDTHRU_2_SE4C0" - ], - [ - "CFG_CENTER_NW4END2_10", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_EE4B0_10", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_EE2BEG1_10", - "INT_FEEDTHRU_2_EE2BEG1" - ], - [ - "CFG_CENTER_WW4END2_10", - "INT_FEEDTHRU_2_WW4END2" - ], - [ - "CFG_CENTER_NE2A0_10", - "INT_FEEDTHRU_2_NE2A0" - ], - [ - "CFG_CENTER_EL1BEG2_10", - "INT_FEEDTHRU_2_EL1BEG2" - ], - [ - "CFG_CENTER_LH7_10", - "INT_FEEDTHRU_2_LH7" - ], - [ - "CFG_CENTER_EE4A1_10", - "INT_FEEDTHRU_2_EE4A1" - ], - [ - "CFG_CENTER_SW4END0_10", - "INT_FEEDTHRU_2_SW4END0" - ], - [ - "CFG_CENTER_EE4A2_10", - "INT_FEEDTHRU_2_EE4A2" - ], - [ - "CFG_CENTER_SE4C3_10", - "INT_FEEDTHRU_2_SE4C3" - ], - [ - "CFG_CENTER_WW4A2_10", - "INT_FEEDTHRU_2_WW4A2" - ], - [ - "CFG_CENTER_WW4A0_10", - "INT_FEEDTHRU_2_WW4A0" - ], - [ - "CFG_CENTER_SE4C2_10", - "INT_FEEDTHRU_2_SE4C2" - ], - [ - "CFG_CENTER_SE2A2_10", - "INT_FEEDTHRU_2_SE2A2" - ], - [ - "CFG_CENTER_LH3_10", - "INT_FEEDTHRU_2_LH3" - ], - [ - "CFG_CENTER_SW4END3_10", - "INT_FEEDTHRU_2_SW4END3" - ], - [ - "CFG_CENTER_WW2END0_10", - "INT_FEEDTHRU_2_WW2END0" - ], - [ - "CFG_CENTER_WL1END0_10", - "INT_FEEDTHRU_2_WL1END0" - ], - [ - "CFG_CENTER_EE4BEG2_10", - "INT_FEEDTHRU_2_EE4BEG2" - ], - [ - "CFG_CENTER_EL1BEG0_10", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_NE4BEG0_10", - "INT_FEEDTHRU_2_NE4BEG0" - ], - [ - "CFG_CENTER_EL1BEG3_10", - "INT_FEEDTHRU_2_EL1BEG3" - ], - [ - "CFG_CENTER_SW4A0_10", - "INT_FEEDTHRU_2_SW4A0" - ], - [ - "CFG_CENTER_NW4END1_10", - "INT_FEEDTHRU_2_NW4END1" - ], - [ - "CFG_CENTER_WL1END2_10", - "INT_FEEDTHRU_2_WL1END2" - ], - [ - "CFG_CENTER_SE4BEG3_10", - "INT_FEEDTHRU_2_SE4BEG3" - ], - [ - "CFG_CENTER_EE4A3_10", - "INT_FEEDTHRU_2_EE4A3" - ], - [ - "CFG_CENTER_WR1END0_10", - "INT_FEEDTHRU_2_WR1END0" - ], - [ - "CFG_CENTER_NW2A1_10", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_WW2A1_10", - "INT_FEEDTHRU_2_WW2A1" - ], - [ - "CFG_CENTER_LH5_10", - "INT_FEEDTHRU_2_LH5" - ], - [ - "CFG_CENTER_NE4C3_10", - "INT_FEEDTHRU_2_NE4C3" - ], - [ - "CFG_CENTER_EE4C3_10", - "INT_FEEDTHRU_2_EE4C3" - ], - [ - "CFG_CENTER_WW4C1_10", - "INT_FEEDTHRU_2_WW4C1" - ], - [ - "CFG_CENTER_NW4END0_10", - "INT_FEEDTHRU_2_NW4END0" - ], - [ - "CFG_CENTER_SW4END2_10", - "INT_FEEDTHRU_2_SW4END2" - ], - [ - "CFG_CENTER_NE2A3_10", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_SE2A1_10", - "INT_FEEDTHRU_2_SE2A1" - ], - [ - "CFG_CENTER_ER1BEG1_10", - "INT_FEEDTHRU_2_ER1BEG1" - ], - [ - "CFG_CENTER_SE4BEG0_10", - "INT_FEEDTHRU_2_SE4BEG0" - ], - [ - "CFG_CENTER_WR1END3_10", - "INT_FEEDTHRU_2_WR1END3" - ], - [ - "CFG_CENTER_NW4END3_10", - "INT_FEEDTHRU_2_NW4END3" - ], - [ - "CFG_CENTER_SW2A3_10", - "INT_FEEDTHRU_2_SW2A3" - ], - [ - "CFG_CENTER_WW4B1_10", - "INT_FEEDTHRU_2_WW4B1" - ], - [ - "CFG_CENTER_LH2_10", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_NE4C2_10", - "INT_FEEDTHRU_2_NE4C2" - ], - [ - "CFG_CENTER_WW2A2_10", - "INT_FEEDTHRU_2_WW2A2" - ], - [ - "CFG_CENTER_WW4B0_10", - "INT_FEEDTHRU_2_WW4B0" - ], - [ - "CFG_CENTER_SW4A1_10", - "INT_FEEDTHRU_2_SW4A1" - ], - [ - "CFG_CENTER_EE4BEG1_10", - "INT_FEEDTHRU_2_EE4BEG1" - ], - [ - "CFG_CENTER_NE2A2_10", - "INT_FEEDTHRU_2_NE2A2" - ], - [ - "CFG_CENTER_NW4A1_10", - "INT_FEEDTHRU_2_NW4A1" - ], - [ - "CFG_CENTER_WW2END3_10", - "INT_FEEDTHRU_2_WW2END3" - ], - [ - "CFG_CENTER_EE4C0_10", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_EE4BEG0_10", - "INT_FEEDTHRU_2_EE4BEG0" - ], - [ - "CFG_CENTER_ER1BEG0_10", - "INT_FEEDTHRU_2_ER1BEG0" - ], - [ - "CFG_CENTER_EE2BEG0_10", - "INT_FEEDTHRU_2_EE2BEG0" - ], - [ - "CFG_CENTER_SW2A0_10", - "INT_FEEDTHRU_2_SW2A0" - ], - [ - "CFG_CENTER_NE4BEG1_10", - "INT_FEEDTHRU_2_NE4BEG1" - ], - [ - "CFG_CENTER_WW4C2_10", - "INT_FEEDTHRU_2_WW4C2" - ], - [ - "CFG_CENTER_WW2A3_10", - "INT_FEEDTHRU_2_WW2A3" - ], - [ - "CFG_CENTER_LH4_10", - "INT_FEEDTHRU_2_LH4" - ], - [ - "CFG_CENTER_WW4C3_10", - "INT_FEEDTHRU_2_WW4C3" - ], - [ - "CFG_CENTER_NW4A3_10", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_WW4B3_10", - "INT_FEEDTHRU_2_WW4B3" - ], - [ - "CFG_CENTER_WW4B2_10", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_WW2A0_10", - "INT_FEEDTHRU_2_WW2A0" - ], - [ - "CFG_CENTER_NE2A1_10", - "INT_FEEDTHRU_2_NE2A1" - ], - [ - "CFG_CENTER_EE2A3_10", - "INT_FEEDTHRU_2_EE2A3" - ], - [ - "CFG_CENTER_WL1END3_10", - "INT_FEEDTHRU_2_WL1END3" - ], - [ - "CFG_CENTER_SW4A3_10", - "INT_FEEDTHRU_2_SW4A3" - ], - [ - "CFG_CENTER_LH1_10", - "INT_FEEDTHRU_2_LH1" - ], - [ - "CFG_CENTER_EE2A1_10", - "INT_FEEDTHRU_2_EE2A1" - ], - [ - "CFG_CENTER_LH9_10", - "INT_FEEDTHRU_2_LH9" - ], - [ - "CFG_CENTER_EE2A2_10", - "INT_FEEDTHRU_2_EE2A2" - ], - [ - "CFG_CENTER_WW2END1_10", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_SE2A3_10", - "INT_FEEDTHRU_2_SE2A3" - ], - [ - "CFG_CENTER_WW4END0_10", - "INT_FEEDTHRU_2_WW4END0" - ], - [ - "CFG_CENTER_LH11_10", - "INT_FEEDTHRU_2_LH11" - ], - [ - "CFG_CENTER_EE4C2_10", - "INT_FEEDTHRU_2_EE4C2" - ], - [ - "CFG_CENTER_NE4C0_10", - "INT_FEEDTHRU_2_NE4C0" - ], - [ - "CFG_CENTER_LH6_10", - "INT_FEEDTHRU_2_LH6" - ], - [ - "CFG_CENTER_SW4END1_10", - "INT_FEEDTHRU_2_SW4END1" - ], - [ - "CFG_CENTER_ER1BEG3_10", - "INT_FEEDTHRU_2_ER1BEG3" - ], - [ - "CFG_CENTER_NW2A3_10", - "INT_FEEDTHRU_2_NW2A3" - ], - [ - "CFG_CENTER_SE2A0_10", - "INT_FEEDTHRU_2_SE2A0" - ], - [ - "CFG_CENTER_WW4END1_10", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_WW2END2_10", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_EE4C1_10", - "INT_FEEDTHRU_2_EE4C1" - ], - [ - "CFG_CENTER_SE4C1_10", - "INT_FEEDTHRU_2_SE4C1" - ], - [ - "CFG_CENTER_EE4B2_10", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_NW4A2_10", - "INT_FEEDTHRU_2_NW4A2" - ], - [ - "CFG_CENTER_EE2A0_10", - "INT_FEEDTHRU_2_EE2A0" - ], - [ - "CFG_CENTER_WW4END3_10", - "INT_FEEDTHRU_2_WW4END3" - ], - [ - "CFG_CENTER_NW2A0_10", - "INT_FEEDTHRU_2_NW2A0" - ], - [ - "CFG_CENTER_EE2BEG3_10", - "INT_FEEDTHRU_2_EE2BEG3" - ], - [ - "CFG_CENTER_EE4BEG3_10", - "INT_FEEDTHRU_2_EE4BEG3" - ], - [ - "CFG_CENTER_WW4C0_10", - "INT_FEEDTHRU_2_WW4C0" - ], - [ - "CFG_CENTER_EE4A0_10", - "INT_FEEDTHRU_2_EE4A0" - ], - [ - "CFG_CENTER_WR1END2_10", - "INT_FEEDTHRU_2_WR1END2" - ], - [ - "CFG_CENTER_EL1BEG1_10", - "INT_FEEDTHRU_2_EL1BEG1" - ], - [ - "CFG_CENTER_EE4B3_10", - "INT_FEEDTHRU_2_EE4B3" - ], - [ - "CFG_CENTER_WR1END1_10", - "INT_FEEDTHRU_2_WR1END1" - ], - [ - "CFG_CENTER_EE4B1_10", - "INT_FEEDTHRU_2_EE4B1" - ], - [ - "CFG_CENTER_LH12_10", - "INT_FEEDTHRU_2_LH12" - ], - [ - "CFG_CENTER_NW2A2_10", - "INT_FEEDTHRU_2_NW2A2" - ], - [ - "CFG_CENTER_LH8_10", - "INT_FEEDTHRU_2_LH8" - ], - [ - "CFG_CENTER_SW2A2_10", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_WW4A1_10", - "INT_FEEDTHRU_2_WW4A1" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_MTBF2" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_GCLK21", - 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- ], - [ - "LOGIC_OUTS_L18", - "INT_INTERFACE_LOGIC_OUTS_L18" - ], - [ - "EE4A3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "FAN_L7", - "INT_INTERFACE_FAN7" - ], - [ - "LH8", - "INT_INTERFACE_LH9" - ], - [ - "NE6END2", - "INT_INTERFACE_NE4C2" - ], - [ - "SE2END1", - "INT_INTERFACE_SE2A1" - ], - [ - "SW6E0", - "INT_INTERFACE_SW4END0" - ], - [ - "WW2A3", - "INT_INTERFACE_WW2END3" - ], - [ - "EE2END1", - "INT_INTERFACE_EE2A1" - ], - [ - "SE6END2", - "INT_INTERFACE_SE4C2" - ], - [ - "NW6BEG2", - "INT_INTERFACE_NW4A2" - ], - [ - "WL1BEG1", - "INT_INTERFACE_WL1END1" - ], - [ - "ER1END3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "LOGIC_OUTS_L20", - "INT_INTERFACE_LOGIC_OUTS_L20" - ], - [ - "SE6END1", - "INT_INTERFACE_SE4C1" - ], - [ - "IMUX_L4", - "INT_INTERFACE_IMUX4" - ], - [ - "EL1END0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "LH1", - "INT_INTERFACE_LH2" - ], - [ - "EE4B1", - "INT_INTERFACE_EE4A1" - ], - [ - "WW2BEG1", - "INT_INTERFACE_WW2A1" - ], - [ - "EE4A2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_L1", - "INT_INTERFACE_CLK1" - ], - [ - "EE4C2", - "INT_INTERFACE_EE4B2" - ], - [ - "SW6BEG3", - "INT_INTERFACE_SW4A3" - ], - [ - "INT_PHASER_TO_IO_ICLK", - "INT_INTERFACE_PHASER_TO_IO_ICLK" - ], - [ - "IMUX_L19", - "INT_INTERFACE_IMUX19" - ], - [ - "IMUX_L9", - "INT_INTERFACE_IMUX9" - ], - [ - "IMUX_L6", - "INT_INTERFACE_IMUX6" - ], - [ - "IMUX_L40", - "INT_INTERFACE_IMUX40" - ], - [ - "BYP_L7", - "INT_INTERFACE_BYP7" - ], - [ - "IMUX_L26", - "INT_INTERFACE_IMUX26" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMV2" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", 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"CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ] - ] - }, - { - "grid_deltas": [ - 0, - -13 - ], - "tile_types": [ - "CMT_TOP_L_UPPER_B", - "CMT_TOP_L_UPPER_T" - ], - "wire_pairs": [ - [ - "CMT_PHASER_UP_PHASERREF0", - "CMT_PLL_PHASERREF0" - ], - [ - "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "PLLOUT_CLK_FREQ_BB_0" - ], - [ - "CMT_PHASER_UP_PHASERREF1", - "CMT_PLL_PHASERREF1" - ], - [ - "CMT_PHASER_UP_PHASERREF_ABOVE0", - "CMT_PLL_PHASERREF_ABOVE0" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL3", - "CMT_TOP_L_UPPER_T_CLKPLL3" - ], - [ - "CMT_PHASER_IN_D_ICLK", - "CMT_PLL_PHASER_IN_D_ICLK" - ], - [ - "CMT_PHASER_OUT_D_OCLK", - "CMT_PLL_PHASER_OUT_D_OCLK" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL7", - "CMT_TOP_L_UPPER_T_CLKPLL7" - ], - [ - "CMT_PHASER_TOP_SYNC_BB", - "CMT_PLL_PHYCTRL_SYNC_BB_DN" - ], - [ - "PLL_CLK_FREQBB_REBUFOUT2", - "PLL_CLK_FREQ_BB2_NS" - ], - [ - "CMT_PHASER_IN_D_ICLKDIV", - "CMT_PLL_PHASER_IN_D_ICLKDIV" - ], - [ - "CMT_PHASER_OUT_D_OCLK1X_90", - "CMT_PLL_PHASER_OUT_D_OCLK1X_90" - ], - [ - "CMT_PHASERD_CTSBUS1", - "CMT_PLL_PHASERD_CTSBUS1" - ], - [ - "CMT_PHASERD_DQSBUS0", - "CMT_PLL_PHASERD_DQSBUS0" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL0", - "CMT_TOP_L_UPPER_T_CLKPLL0" - ], - [ - "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", - "CMT_PLL_PHASER_RDCLK_TOFIFO" - ], - [ - "CMT_PHASER_IN_D_WRENABLE_FIFO", - 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- "BRAM_IMUX21_UTURN_1" - ], - [ - "INT_INTERFACE_EE2A1", - "BRAM_EE2A1_1" - ], - [ - "INT_INTERFACE_WW2END3", - "BRAM_WW2END3_1" - ], - [ - "INT_INTERFACE_WW4B0", - "BRAM_WW4B0_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX26", - "BRAM_IMUX26_UTURN_1" - ], - [ - "INT_INTERFACE_WW4B1", - "BRAM_WW4B1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX27", - "BRAM_IMUX27_UTURN_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "BRAM_LOGIC_OUTS_B22_1" - ], - [ - "INT_INTERFACE_WR1END1", - "BRAM_WR1END1_1" - ], - [ - "INT_INTERFACE_LH4", - "BRAM_LH4_1" - ], - [ - "INT_INTERFACE_SE4C2", - "BRAM_SE4C2_1" - ], - [ - "INT_INTERFACE_NE2A2", - "BRAM_NE2A2_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX7", - "BRAM_IMUX7_1" - ], - [ - "INT_INTERFACE_BYP6", - "BRAM_BYP6_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX0", - "BRAM_IMUX0_UTURN_1" - ], - [ - "INT_INTERFACE_NW4A2", - "BRAM_NW4A2_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX34", - "BRAM_IMUX34_UTURN_1" - ], - [ - "INT_INTERFACE_NW4A0", - "BRAM_NW4A0_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "BRAM_IMUX31_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX24", - "BRAM_IMUX24_1" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "BRAM_LOGIC_OUTS_B21_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX19", - "BRAM_IMUX19_UTURN_1" - ], - [ - "INT_INTERFACE_WL1END1", - "BRAM_WL1END1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX17", - "BRAM_IMUX17_UTURN_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "BRAM_LOGIC_OUTS_B1_1" - ], - [ - "INT_INTERFACE_FAN5", - "BRAM_FAN5_1" - ], - [ - "INT_INTERFACE_SE4C3", - "BRAM_SE4C3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "BRAM_IMUX37_1" - ], - [ - "INT_INTERFACE_SE2A0", - "BRAM_SE2A0_1" - ], - [ - "INT_INTERFACE_WW4A1", - "BRAM_WW4A1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX3", - "BRAM_IMUX3_UTURN_1" - ], - [ - "INT_INTERFACE_SW2A2", - "BRAM_SW2A2_1" - ], - [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_1" - ], - [ - "INT_INTERFACE_ER1BEG1", - "BRAM_ER1BEG1_1" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX16", - "BRAM_IMUX16_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "BRAM_LOGIC_OUTS_B19_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX36", - "BRAM_IMUX36_1" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "BRAM_LOGIC_OUTS_B8_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX22", - "BRAM_IMUX22_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "BRAM_IMUX3_1" - ], - [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "BRAM_LOGIC_OUTS_B4_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX20", - "BRAM_IMUX20_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX24", - "BRAM_IMUX24_UTURN_1" - ], - [ - "INT_INTERFACE_EE4C3", - "BRAM_EE4C3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX2", - "BRAM_IMUX2_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX28", - "BRAM_IMUX28_UTURN_1" - ], - [ - "INT_INTERFACE_SW4A1", - "BRAM_SW4A1_1" - ], - [ - "INT_INTERFACE_NW2A0", - "BRAM_NW2A0_1" - ], - [ - "INT_INTERFACE_NW4END3", - "BRAM_NW4END3_1" - ], - [ - "INT_INTERFACE_NE2A3", - "BRAM_NE2A3_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "BRAM_LOGIC_OUTS_B20_1" - ], - [ - "INT_INTERFACE_MONITOR_N", - "BRAM_MONITOR_N_1" - ], - [ - "INT_INTERFACE_LH2", - "BRAM_LH2_1" - ], - [ - "INT_INTERFACE_EE2A0", - "BRAM_EE2A0_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "BRAM_LOGIC_OUTS_B11_1" - ], - [ - "INT_INTERFACE_WL1END2", - "BRAM_WL1END2_1" - ], - [ - "INT_INTERFACE_CLK0", - "BRAM_CLK0_1" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX30", - "BRAM_IMUX30_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX16", - "BRAM_IMUX16_UTURN_1" - ], - [ - "INT_INTERFACE_EE4BEG1", - "BRAM_EE4BEG1_1" - ], - [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_1" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_1" - ], - [ - "INT_INTERFACE_SE4BEG3", - "BRAM_SE4BEG3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX13", - "BRAM_IMUX13_1" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_1" - ], - [ - "INT_INTERFACE_WW4END3", - "BRAM_WW4END3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX25", - "BRAM_IMUX25_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX42", - "BRAM_IMUX42_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX9", - "BRAM_IMUX9_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "BRAM_IMUX4_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX38", - "BRAM_IMUX38_UTURN_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "BRAM_LOGIC_OUTS_B18_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX10", - "BRAM_IMUX10_1" - ], - [ - "INT_INTERFACE_LH7", - "BRAM_LH7_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX47", - "BRAM_IMUX47_UTURN_1" - ], - [ - "INT_INTERFACE_WW2A3", - "BRAM_WW2A3_1" - ], - [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX33", - "BRAM_IMUX33_UTURN_1" - ], - [ - "INT_INTERFACE_SE4C1", - "BRAM_SE4C1_1" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_1" - ], - [ - "INT_INTERFACE_CTRL1", - "BRAM_CTRL1_1" - ], - [ - "INT_INTERFACE_FAN2", - "BRAM_FAN2_1" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_1" - ], - [ - "INT_INTERFACE_WW4A3", - "BRAM_WW4A3_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "BRAM_LOGIC_OUTS_B2_1" - ], - [ - "INT_INTERFACE_SE2A3", - "BRAM_SE2A3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX45", - "BRAM_IMUX45_UTURN_1" - ], - [ - "INT_INTERFACE_WW2A1", - "BRAM_WW2A1_1" - ], - [ - "INT_INTERFACE_SW2A3", - "BRAM_SW2A3_1" - ], - [ - "INT_INTERFACE_CTRL0", - "BRAM_CTRL0_1" - ], - [ - "INT_INTERFACE_NE4C2", - "BRAM_NE4C2_1" - ], - [ - "INT_INTERFACE_LH9", - "BRAM_LH9_1" - ], - [ - "INT_INTERFACE_ER1BEG0", - "BRAM_ER1BEG0_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_1" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_1" - ], - [ - "INT_INTERFACE_NE4C0", - "BRAM_NE4C0_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX26", - "BRAM_IMUX26_1" - ], - [ - "INT_INTERFACE_WR1END3", - "BRAM_WR1END3_1" - ], - [ - "INT_INTERFACE_WW2A0", - "BRAM_WW2A0_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX35", - "BRAM_IMUX35_UTURN_1" - ], - [ - "INT_INTERFACE_WW4C1", - "BRAM_WW4C1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX22", - "BRAM_IMUX22_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX11", - "BRAM_IMUX11_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_1" - ], - [ - "INT_INTERFACE_NE2A1", - "BRAM_NE2A1_1" - ], - [ - "INT_INTERFACE_EL1BEG0", - "BRAM_EL1BEG0_1" - ], - [ - "INT_INTERFACE_NW4A1", - "BRAM_NW4A1_1" - ], - [ - "INT_INTERFACE_EE4B2", - "BRAM_EE4B2_1" - ], - [ - "INT_INTERFACE_NE2A0", - "BRAM_NE2A0_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX31", - "BRAM_IMUX31_UTURN_1" - ], - [ - "INT_INTERFACE_NE4BEG0", - "BRAM_NE4BEG0_1" - ], - [ - "INT_INTERFACE_WL1END3", - "BRAM_WL1END3_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "BRAM_LOGIC_OUTS_B15_1" - ], - [ - "INT_INTERFACE_EE2BEG3", - "BRAM_EE2BEG3_1" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_1" - ], - [ - "INT_INTERFACE_LH5", - "BRAM_LH5_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "BRAM_IMUX17_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "BRAM_LOGIC_OUTS_B0_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX32", - "BRAM_IMUX32_UTURN_1" - ], - [ - "INT_INTERFACE_NE4C3", - "BRAM_NE4C3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "BRAM_IMUX25_1" - ], - [ - "INT_INTERFACE_EE4C0", - "BRAM_EE4C0_1" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_1" - ], - [ - "INT_INTERFACE_EE4BEG3", - "BRAM_EE4BEG3_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B14", - "BRAM_LOGIC_OUTS_B14_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "BRAM_LOGIC_OUTS_B17_1" - ], - [ - "INT_INTERFACE_WW4C3", - "BRAM_WW4C3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX46", - "BRAM_IMUX46_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "BRAM_IMUX32_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "BRAM_LOGIC_OUTS_B10_1" - ], - [ - "INT_INTERFACE_BYP3", - "BRAM_BYP3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "BRAM_IMUX10_UTURN_1" - ], - [ - "INT_INTERFACE_EE4B3", - "BRAM_EE4B3_1" - ], - [ - "INT_INTERFACE_ER1BEG3", - "BRAM_ER1BEG3_1" - ], - [ - "INT_INTERFACE_BYP5", - "BRAM_BYP5_1" - ], - [ - "INT_INTERFACE_BYP2", - "BRAM_BYP2_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX37", - "BRAM_IMUX37_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX27", - "BRAM_IMUX27_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX29", - "BRAM_IMUX29_UTURN_1" - ], - [ - "INT_INTERFACE_EE4B1", - "BRAM_EE4B1_1" - ], - [ - "INT_INTERFACE_SE2A1", - "BRAM_SE2A1_1" - ], - [ - "INT_INTERFACE_FAN4", - "BRAM_FAN4_1" - ], - [ - "INT_INTERFACE_WW2END2", - "BRAM_WW2END2_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX29", - "BRAM_IMUX29_1" - ], - [ - "INT_INTERFACE_EE2BEG0", - "BRAM_EE2BEG0_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX41", - "BRAM_IMUX41_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "BRAM_IMUX6_1" - ], - [ - "INT_INTERFACE_FAN6", - "BRAM_FAN6_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX36", - "BRAM_IMUX36_UTURN_1" - ], - [ - "INT_INTERFACE_LH3", - "BRAM_LH3_1" - ], - [ - "INT_INTERFACE_EL1BEG1", - "BRAM_EL1BEG1_1" - ], - [ - "INT_INTERFACE_NE4BEG2", - "BRAM_NE4BEG2_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "BRAM_LOGIC_OUTS_B12_1" - ], - [ - "INT_INTERFACE_EE4A3", - "BRAM_EE4A3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX34", - "BRAM_IMUX34_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX0", - "BRAM_IMUX0_1" - ], - [ - "INT_INTERFACE_NE4C1", - "BRAM_NE4C1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX20", - "BRAM_IMUX20_UTURN_1" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX5", - "BRAM_IMUX5_UTURN_1" - ], - [ - "INT_INTERFACE_WW2END1", - "BRAM_WW2END1_1" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_1" - ], - [ - "INT_INTERFACE_WW4END1", - "BRAM_WW4END1_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX23", - "BRAM_IMUX23_1" - ], - [ - "INT_INTERFACE_EE2A3", - "BRAM_EE2A3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX33", - "BRAM_IMUX33_1" - ], - [ - "INT_INTERFACE_FAN3", - "BRAM_FAN3_1" - ], - [ - "INT_INTERFACE_SE4BEG0", - "BRAM_SE4BEG0_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "BRAM_LOGIC_OUTS_B23_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX18", - "BRAM_IMUX18_UTURN_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "BRAM_LOGIC_OUTS_B9_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX43", - "BRAM_IMUX43_UTURN_1" - ], - [ - "INT_INTERFACE_EE2BEG1", - "BRAM_EE2BEG1_1" - ], - [ - "INT_INTERFACE_EE2BEG2", - "BRAM_EE2BEG2_1" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX19", - "BRAM_IMUX19_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX12", - "BRAM_IMUX12_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "BRAM_IMUX5_1" - ], - [ - "INT_INTERFACE_NW2A1", - "BRAM_NW2A1_1" - ], - [ - "INT_INTERFACE_NW4END2", - "BRAM_NW4END2_1" - ], - [ - "INT_INTERFACE_WW4C0", - "BRAM_WW4C0_1" - ], - [ - "INT_INTERFACE_NE4BEG3", - "BRAM_NE4BEG3_1" - ], - [ - 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"HCLK_FIFO_L", + "HCLK_BRAM", "HCLK_INT_INTERFACE" ], "wire_pairs": [ [ - "HCLK_FIFO_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" ], [ - "HCLK_FIFO_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_FIFO_CK_BUFHCLK1", + "HCLK_BRAM_CK_BUFHCLK1", "HCLK_INT_INTERFACE_CK_BUFHCLK1" ], [ - "HCLK_FIFO_CK_BUFHCLK9", + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", "HCLK_INT_INTERFACE_CK_BUFHCLK9" ], [ - "HCLK_FIFO_CK_BUFRCLK3", + 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- ], - [ - "CFG_CENTER_FAN2_12", - "VFRAME_FAN2" - ], - [ - "CFG_CENTER_CLK0_12", - "VFRAME_CLK0" - ], - [ - "CFG_CENTER_FAN1_12", - "VFRAME_FAN1" - ], - [ - "CFG_CENTER_LH9_12", - "VFRAME_LH9" - ], - [ - "CFG_CENTER_NW2A2_12", - "VFRAME_NW2A2" - ], - [ - "CFG_CENTER_IMUX18_12", - "VFRAME_IMUX18" - ], - [ - "CFG_CENTER_NW4A3_12", - "VFRAME_NW4A3" - ], - [ - "CFG_CENTER_IMUX7_12", - "VFRAME_IMUX7" - ], - [ - "CFG_CENTER_NE2A2_12", - "VFRAME_NE2A2" - ], - [ - "CFG_CENTER_CLK1_12", - "VFRAME_CLK1" - ], - [ - "CFG_CENTER_IMUX13_12", - "VFRAME_IMUX13" - ], - [ - "CFG_CENTER_IMUX40_12", - "VFRAME_IMUX40" - ], - [ - "CFG_CENTER_SW4END3_12", - "VFRAME_SW4END3" - ], - [ - "CFG_CENTER_EE2A3_12", - "VFRAME_EE2A3" - ], - [ - "CFG_CENTER_SE4BEG2_12", - "VFRAME_SE4BEG2" - ], - [ - "CFG_CENTER_IMUX36_12", - "VFRAME_IMUX36" - ], - [ - "CFG_CENTER_LH4_12", - "VFRAME_LH4" - ], - [ - "CFG_CENTER_WW2A2_12", - "VFRAME_WW2A2" - ], - [ - "CFG_CENTER_SW2A2_12", - "VFRAME_SW2A2" - ], - [ - "CFG_CENTER_EL1BEG0_12", - "VFRAME_EL1BEG0" - ], - [ - "CFG_CENTER_WW2A3_12", - "VFRAME_WW2A3" - ], - [ - "CFG_CENTER_EE4B3_12", - "VFRAME_EE4B3" - ], - [ - "CFG_CENTER_SE2A1_12", - "VFRAME_SE2A1" - ], - [ - "CFG_CENTER_IMUX2_12", - "VFRAME_IMUX2" - ], - [ - "CFG_CENTER_NE4C2_12", - "VFRAME_NE4C2" - ], - [ - "CFG_CENTER_LH6_12", - "VFRAME_LH6" - ], - [ - "CFG_CENTER_ER1BEG3_12", - "VFRAME_ER1BEG3" - ], - [ - "CFG_CENTER_IMUX26_12", - "VFRAME_IMUX26" - ], - [ - "CFG_CENTER_IMUX1_12", - "VFRAME_IMUX1" - ], - [ - "CFG_CENTER_EE2BEG0_12", - "VFRAME_EE2BEG0" - ], - [ - "CFG_CENTER_IMUX16_12", - "VFRAME_IMUX16" - ], - [ - "CFG_CENTER_NE4BEG2_12", - "VFRAME_NE4BEG2" - ], - [ - "CFG_CENTER_WW4B1_12", - "VFRAME_WW4B1" - ], - [ - "CFG_CENTER_ER1BEG1_12", - "VFRAME_ER1BEG1" - ], - [ - "CFG_CENTER_IMUX24_12", - "VFRAME_IMUX24" - ], - [ - "CFG_CENTER_NW4END1_12", - "VFRAME_NW4END1" - ], - [ - "CFG_CENTER_SE4C0_12", - "VFRAME_SE4C0" - ], - [ - "CFG_CENTER_IMUX19_12", - "VFRAME_IMUX19" - ], - [ - "CFG_CENTER_LH10_12", - "VFRAME_LH10" - ], - [ - "CFG_CENTER_IMUX0_12", - "VFRAME_IMUX0" - ], - [ - "CFG_CENTER_EE4B0_12", - "VFRAME_EE4B0" - ], - [ - "CFG_CENTER_IMUX43_12", - "VFRAME_IMUX43" - ], - [ - "CFG_CENTER_EE4BEG2_12", - "VFRAME_EE4BEG2" - ], - [ - "CFG_CENTER_WW4C3_12", - "VFRAME_WW4C3" - ], - [ - "CFG_CENTER_NW2A3_12", - "VFRAME_NW2A3" - ], - [ - "CFG_CENTER_SE4BEG0_12", - "VFRAME_SE4BEG0" - ], - [ - "CFG_CENTER_IMUX22_12", - "VFRAME_IMUX22" - ], - [ - "CFG_CENTER_EE4C0_12", - "VFRAME_EE4C0" - ], - [ - "CFG_CENTER_LH12_12", - "VFRAME_LH12" - ], - [ - "CFG_CENTER_IMUX30_12", - "VFRAME_IMUX30" - ], - [ - "CFG_CENTER_LH1_12", - "VFRAME_LH1" - ], - [ - "CFG_CENTER_WL1END1_12", - "VFRAME_WL1END1" - ], - [ - "CFG_CENTER_EE4C2_12", - "VFRAME_EE4C2" - ], - [ - "CFG_CENTER_IMUX41_12", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_ER1BEG0_12", - "VFRAME_ER1BEG0" - ], - [ - "CFG_CENTER_EL1BEG2_12", - "VFRAME_EL1BEG2" - ], - [ - "CFG_CENTER_LH3_12", - "VFRAME_LH3" - ], - [ - "CFG_CENTER_NE4C1_12", - "VFRAME_NE4C1" - ], - [ - "CFG_CENTER_WR1END2_12", - "VFRAME_WR1END2" - ], - [ - "CFG_CENTER_WW4B3_12", - "VFRAME_WW4B3" - ], - [ - "CFG_CENTER_EE4BEG3_12", - "VFRAME_EE4BEG3" - ], - [ - "CFG_CENTER_SW4END0_12", - "VFRAME_SW4END0" - ], - [ - "CFG_CENTER_EE4C3_12", - "VFRAME_EE4C3" - ], - [ - "CFG_CENTER_WL1END3_12", - "VFRAME_WL1END3" - ], - [ - "CFG_CENTER_LH2_12", - "VFRAME_LH2" - ], - [ - "CFG_CENTER_WR1END0_12", - "VFRAME_WR1END0" - ], - [ - "CFG_CENTER_SW2A0_12", - "VFRAME_SW2A0" - ], - [ - "CFG_CENTER_LH7_12", - "VFRAME_LH7" - ], - [ - "CFG_CENTER_NE2A0_12", - "VFRAME_NE2A0" - ], - [ - "CFG_CENTER_WW4END1_12", - "VFRAME_WW4END1" - ], - [ - "CFG_CENTER_NE4BEG3_12", - "VFRAME_NE4BEG3" - ], - [ - "CFG_CENTER_WW4C2_12", - "VFRAME_WW4C2" - ], - [ - "CFG_CENTER_BYP0_12", - "VFRAME_BYP0" - ], - [ - "CFG_CENTER_IMUX46_12", - "VFRAME_IMUX46" - ], - [ - "CFG_CENTER_BYP4_12", - "VFRAME_BYP4" - ], - [ - "CFG_CENTER_FAN6_12", - "VFRAME_FAN6" - ], - [ - "CFG_CENTER_IMUX11_12", - "VFRAME_IMUX11" - ], - [ - "CFG_CENTER_BYP6_12", - "VFRAME_BYP6" - ], - [ - "CFG_CENTER_CTRL1_12", - "VFRAME_CTRL1" - ], - [ - "CFG_CENTER_SW4A3_12", - "VFRAME_SW4A3" - ], - [ - "CFG_CENTER_IMUX10_12", - "VFRAME_IMUX10" - ], - [ - "CFG_CENTER_IMUX17_12", - "VFRAME_IMUX17" - ], - [ - "CFG_CENTER_IMUX37_12", - "VFRAME_IMUX37" - ], - [ - "CFG_CENTER_IMUX8_12", - "VFRAME_IMUX8" - ], - [ - "CFG_CENTER_IMUX38_12", - "VFRAME_IMUX38" - ], - [ - "CFG_CENTER_IMUX39_12", - "VFRAME_IMUX39" - ], - [ - "CFG_CENTER_ER1BEG2_12", - "VFRAME_ER1BEG2" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "INT_L", - "INT_L" - ], - "wire_pairs": [ - [ - "NN2A2", - "NN2BEG2" - ], - [ - "SS6C2", - "SS6D2" - ], - [ - "SS2A0", - "SS2END0" - ], - [ - "NE2END0", - "NE2END_S3_0" - ], - [ - "SW6B1", - "SW6C1" - ], - [ - "SE6C3", - "SE6D3" - ], - [ - "SS6E1", - "SS6END1" - ], - [ - "SW6A0", - "SW6B0" - ], - [ - "GCLK_L_B7", - "GCLK_L_B7" - ], - [ - "SE6B2", - "SE6C2" - ], - [ - "LV_L10", - "LV_L9" - ], - [ - "SS6A2", - "SS6B2" - ], - [ - "FAN_BOUNCE0", - "FAN_BOUNCE_S3_0" - ], - [ - "SS6D2", - "SS6E2" - ], - [ - "SW6C0", - "SW6D0" - ], - [ - "SS6C1", - "SS6D1" - ], - [ - "SW6D0", - "SW6E0" - ], - [ - "SW6C3", - "SW6D3" - ], - [ - "SE6C1", - "SE6D1" - ], - [ - "SW6B2", - "SW6C2" - ], - [ - "SS6E2", - "SS6END2" - ], - [ - "SS2A1", - "SS2END1" - ], - [ - "SS6B3", - "SS6C3" - ], - [ - "SL1BEG0", - "SL1END0" - ], - [ - "FAN_BOUNCE2", - "FAN_BOUNCE_S3_2" - ], - [ - "WR1END0", - "WR1END_S1_0" - ], - [ - "FAN_BOUNCE4", - "FAN_BOUNCE_S3_4" - ], - [ - "SS6A1", - "SS6B1" - ], - [ - "SS6E0", - "SS6END0" - ], - [ - "SS6E3", - "SS6END3" - ], - [ - "SE6A2", - "SE6B2" - ], - [ - "SE6C0", - "SE6D0" - ], - [ - "SE6B0", - "SE6C0" - ], - [ - "SR1BEG2", - "SR1END2" - ], - [ - "SW6A3", - "SW6B3" - ], - [ - "SW6A2", - "SW6B2" - ], - [ - "NE2A2", - "NE2BEG2" - ], - [ - "ER1BEG0", - "ER1BEG_S0" - ], - [ - "SE6A0", - "SE6B0" - ], - [ - "SS6A0", - "SS6B0" - ], - [ - "LVB_L10", - "LVB_L9" - ], - [ - "SL1BEG2", - "SL1END2" - ], - [ - "NW2A0", - "NW2BEG0" - ], - [ - "NN2END0", - "NN2END_S2_0" - ], - [ - "GCLK_L_B9", - "GCLK_L_B9" - ], - [ - "SW6B3", - "SW6C3" - ], - [ - "SS6D0", - "SS6E0" - ], - [ - "NW2END0", - "NW2END_S0_0" - ], - [ - "NL1END0", - "NL1END_S3_0" - ], - [ - "SE6A3", - "SE6B3" - ], - [ - "SW6D2", - "SW6E2" - ], - [ - "SE6D1", - "SE6E1" - ], - [ - "SW6D3", - "SW6E3" - ], - [ - "NE2A1", - "NE2BEG1" - ], - [ - "SS6D3", - "SS6E3" - ], - [ - "NN6A3", - "NN6BEG3" - ], - [ - "SW6B0", - "SW6C0" - ], - [ - "SW6C1", - "SW6D1" - ], - [ - "NE2A0", - "NE2BEG0" - ], - [ - "NN2A0", - "NN2BEG0" - ], - [ - "NN2A1", - "NN2BEG1" - ], - [ - "SE6D2", - "SE6E2" - ], - [ - "NN2A3", - "NN2BEG3" - ], - [ - "SS6B0", - "SS6C0" - ], - [ - "FAN_BOUNCE6", - "FAN_BOUNCE_S3_6" - ], - [ - "GCLK_L_B6", - "GCLK_L_B6" - ], - [ - "SE6B1", - "SE6C1" - ], - [ - "GCLK_L_B8", - "GCLK_L_B8" - ], - [ - "SE6A1", - "SE6B1" - ], - [ - "GCLK_L_B10", - "GCLK_L_B10" - ], - [ - "SS2A2", - "SS2END2" - ], - [ - "SR1BEG1", - "SR1END1" - ], - [ - "SS6B2", - "SS6C2" - ], - [ - "NN6END0", - "NN6END_S1_0" - ], - [ - "SS6A3", - "SS6B3" - ], - [ - "NW6END0", - "NW6END_S0_0" - ], - [ - "NN6A0", - "NN6BEG0" - ], - [ - "SS6D1", - "SS6E1" - ], - [ - "GCLK_L_B11", - "GCLK_L_B11" - ], - [ - "SE6B3", - "SE6C3" - ], - [ - "SW6A1", - "SW6B1" - ], - [ - "NE2A3", - "NE2BEG3" - ], - [ - "SE6C2", - "SE6D2" - ], - [ - "SE6D3", - "SE6E3" - ], - [ - "EL1END0", - "EL1END_S3_0" - ], - [ - "SS6B1", - "SS6C1" - ], - [ - "SS6C3", - "SS6D3" - ], - [ - "NW2A3", - "NW2BEG3" - ], - [ - "NN6A2", - "NN6BEG2" - ], - [ - "WW4END0", - "WW4END_S0_0" - ], - [ - "NW2A2", - "NW2BEG2" - ], - [ - "SE6D0", - "SE6E0" + "HCLK_BRAM_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" ], [ - "SR1BEG3", - "SR1END3" + "HCLK_BRAM_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" ], [ - "SL1BEG1", - "SL1END1" + "HCLK_BRAM_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" ], [ - "SL1BEG3", - "SL1END3" + "HCLK_BRAM_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" ], [ - "NN6A1", - "NN6BEG1" + "HCLK_BRAM_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" ], [ - "SW6C2", - "SW6D2" + "HCLK_BRAM_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" ], [ - "NW2A1", - "NW2BEG1" + "HCLK_BRAM_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" ], [ - "SW6D1", - "SW6E1" + "HCLK_BRAM_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" ], [ - "WR1BEG0", - "WR1BEG_S0" + "HCLK_BRAM_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" ], [ - "SS2A3", - "SS2END3" + "HCLK_BRAM_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" ], [ - "SS6C0", - "SS6D0" + "HCLK_BRAM_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" ] ] }, @@ -452173,45 +361593,53 @@ "HCLK_INT_INTERFACE" ], "wire_pairs": [ - [ - "HCLK_BRAM_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], [ "HCLK_BRAM_CK_BUFHCLK0", "HCLK_INT_INTERFACE_CK_BUFHCLK0" ], [ - "HCLK_BRAM_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN9" + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" ], [ "HCLK_BRAM_CK_BUFHCLK3", "HCLK_INT_INTERFACE_CK_BUFHCLK3" ], [ - "HCLK_BRAM_CK_IN2", - "HCLK_INT_INTERFACE_CK_IN2" - ], - [ - "HCLK_BRAM_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" ], [ "HCLK_BRAM_CK_BUFHCLK5", "HCLK_INT_INTERFACE_CK_BUFHCLK5" ], [ - "HCLK_BRAM_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" ], [ - "HCLK_BRAM_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN5" + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" ], [ - "HCLK_BRAM_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN0" + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" ], [ "HCLK_BRAM_CK_BUFRCLK0", @@ -452221,37 +361649,41 @@ "HCLK_BRAM_CK_BUFRCLK1", "HCLK_INT_INTERFACE_CK_BUFRCLK1" ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], [ "HCLK_BRAM_CK_IN1", "HCLK_INT_INTERFACE_CK_IN1" ], [ - "HCLK_BRAM_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" + "HCLK_BRAM_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" ], [ "HCLK_BRAM_CK_IN3", "HCLK_INT_INTERFACE_CK_IN3" ], - [ - "HCLK_BRAM_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_BRAM_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "HCLK_BRAM_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], [ "HCLK_BRAM_CK_IN4", "HCLK_INT_INTERFACE_CK_IN4" ], [ - "HCLK_BRAM_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" + "HCLK_BRAM_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" ], [ "HCLK_BRAM_CK_IN7", @@ -452262,32 +361694,20 @@ "HCLK_INT_INTERFACE_CK_IN8" ], [ - "HCLK_BRAM_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN6" - ], - [ - "HCLK_BRAM_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "HCLK_BRAM_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "HCLK_BRAM_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "HCLK_BRAM_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN11" + "HCLK_BRAM_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" ], [ "HCLK_BRAM_CK_IN10", "HCLK_INT_INTERFACE_CK_IN10" ], [ - "HCLK_BRAM_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" + "HCLK_BRAM_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" ], [ "HCLK_BRAM_CK_IN13", @@ -452298,1464 +361718,20472 @@ { "grid_deltas": [ -1, - -3 + 0 ], "tile_types": [ - "CLK_BUFG_BOT_R", - "INT_INTERFACE_R" + "HCLK_BRAM", + "HCLK_VBRK" ], "wire_pairs": [ [ - "CLK_HROW_WR1END2_3", - "INT_INTERFACE_WR1END2" + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" ], [ - "CLK_HROW_SE4BEG1_3", - "INT_INTERFACE_SE4BEG1" + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" ], [ - "CLK_HROW_WW4C1_3", - "INT_INTERFACE_WW4C1" + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" ], [ - "CLK_HROW_EE2A1_3", - "INT_INTERFACE_EE2A1" + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" ], [ - "CLK_BUFG_IMUX39_3", - "INT_INTERFACE_IMUX39" + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" ], [ - "CLK_HROW_WW2END2_3", - "INT_INTERFACE_WW2END2" + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" ], [ - "CLK_HROW_EE4B2_3", - "INT_INTERFACE_EE4B2" + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" ], [ - "CLK_HROW_NE2A2_3", - "INT_INTERFACE_NE2A2" + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" ], [ - "CLK_HROW_SW2A1_3", - "INT_INTERFACE_SW2A1" + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" ], [ - "CLK_HROW_SW4A3_3", - "INT_INTERFACE_SW4A3" + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" ], [ - "CLK_HROW_WW2A0_3", - "INT_INTERFACE_WW2A0" + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" ], [ - "CLK_BUFG_LOGIC_OUTS_B7_3", - "INT_INTERFACE_LOGIC_OUTS_B7" + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" ], [ - "CLK_HROW_SW4END2_3", - "INT_INTERFACE_SW4END2" + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" ], [ - "CLK_HROW_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" ], [ - "CLK_HROW_SE2A3_3", - "INT_INTERFACE_SE2A3" + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" ], [ - "CLK_HROW_WW4B3_3", - "INT_INTERFACE_WW4B3" + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" ], [ - "CLK_BUFG_IMUX29_3", - "INT_INTERFACE_IMUX29" + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" ], [ - "CLK_HROW_SE2A2_3", - "INT_INTERFACE_SE2A2" + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" ], [ - "CLK_BUFG_IMUX5_3", - "INT_INTERFACE_IMUX5" + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" ], [ - "CLK_HROW_EE2A0_3", - "INT_INTERFACE_EE2A0" + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" ], [ - "CLK_HROW_EE4C0_3", - "INT_INTERFACE_EE4C0" + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" ], [ - "CLK_HROW_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" ], [ - "CLK_HROW_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" ], [ - "CLK_HROW_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" ], [ - "CLK_BUFG_IMUX1_3", - "INT_INTERFACE_IMUX1" + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" ], [ - "CLK_HROW_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" ], [ - "CLK_HROW_SE4C2_3", - "INT_INTERFACE_SE4C2" + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" ], [ - "CLK_HROW_SW4A0_3", - "INT_INTERFACE_SW4A0" + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" ], [ - "CLK_HROW_NE2A3_3", - "INT_INTERFACE_NE2A3" + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" ], [ - "CLK_BUFG_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_BYP1_3", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_FAN7_3", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_SW2A2_3", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_EE4A1_3", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_BUFG_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_NE2A1_3", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_IMUX41_3", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SE4BEG2_3", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_LH1_3", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_NE4C0_3", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_BUFG_IMUX40_3", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_WW2END1_3", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_BUFG_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NW4A2_3", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_FAN6_3", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_3", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_CLK1_3", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WW4C3_3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW4B0_3", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_NW2A0_3", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_3", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_BUFG_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_BUFG_IMUX11_3", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_BUFG_IMUX38_3", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_BUFG_IMUX35_3", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_NW2A3_3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_EE4C3_3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_WL1END0_3", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_WW2A3_3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_BUFG_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_BUFG_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_CLK0_3", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW4C2_3", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_3", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_VBRK" + ], + "wire_pairs": [ [ - "CLK_HROW_BYP7_3", - "INT_INTERFACE_BYP7" + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" ], [ - "CLK_HROW_BYP0_3", - "INT_INTERFACE_BYP0" + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" ], [ - "CLK_HROW_WW4A2_3", - "INT_INTERFACE_WW4A2" + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" ], [ - "CLK_HROW_NE2A0_3", - "INT_INTERFACE_NE2A0" + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" ], [ - "CLK_HROW_BYP4_3", - "INT_INTERFACE_BYP4" + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" ], [ - "CLK_BUFG_IMUX14_3", - "INT_INTERFACE_IMUX14" + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" ], [ - "CLK_BUFG_IMUX2_3", - "INT_INTERFACE_IMUX2" + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" ], [ - "CLK_BUFG_LOGIC_OUTS_B5_3", - "INT_INTERFACE_LOGIC_OUTS_B5" + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" ], [ - "CLK_HROW_SW4END0_3", - "INT_INTERFACE_SW4END0" + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" ], [ - "CLK_HROW_WL1END3_3", - "INT_INTERFACE_WL1END3" + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" ], [ - "CLK_BUFG_IMUX47_3", - "INT_INTERFACE_IMUX47" + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" ], [ - "CLK_HROW_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" ], [ - "CLK_BUFG_IMUX19_3", - "INT_INTERFACE_IMUX19" + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" ], [ - "CLK_HROW_SE2A1_3", - "INT_INTERFACE_SE2A1" + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" ], [ - "CLK_HROW_SE4C3_3", - "INT_INTERFACE_SE4C3" + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" ], [ - "CLK_HROW_WW2END0_3", - "INT_INTERFACE_WW2END0" + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" ], [ - "CLK_BUFG_LOGIC_OUTS_B2_3", - "INT_INTERFACE_LOGIC_OUTS_B2" + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" ], [ - "CLK_HROW_WW4END2_3", - "INT_INTERFACE_WW4END2" + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" ], [ - "CLK_HROW_NE4BEG3_3", - "INT_INTERFACE_NE4BEG3" + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" ], [ - "CLK_HROW_WW4A1_3", - "INT_INTERFACE_WW4A1" + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" ], [ - "CLK_BUFG_IMUX25_3", - "INT_INTERFACE_IMUX25" + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" ], [ - "CLK_BUFG_IMUX8_3", - "INT_INTERFACE_IMUX8" + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" ], [ - "CLK_HROW_NW4A1_3", - "INT_INTERFACE_NW4A1" + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" ], [ - "CLK_BUFG_IMUX33_3", - "INT_INTERFACE_IMUX33" + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" ], [ - "CLK_HROW_NW2A2_3", - "INT_INTERFACE_NW2A2" + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" ], [ - "CLK_HROW_LH11_3", - "INT_INTERFACE_LH11" + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" ], [ - "CLK_HROW_NW2A1_3", - "INT_INTERFACE_NW2A1" + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" ], [ - "CLK_HROW_EE4B1_3", - "INT_INTERFACE_EE4B1" + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" ], [ - "CLK_BUFG_LOGIC_OUTS_B4_3", - "INT_INTERFACE_LOGIC_OUTS_B4" + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" ], [ - "CLK_HROW_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EE4C1_3", - "INT_INTERFACE_EE4C1" - ], + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_CLB" + ], + "wire_pairs": [ [ - "CLK_BUFG_IMUX43_3", - "INT_INTERFACE_IMUX43" + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CLB_CK_BUFHCLK0" ], [ - "CLK_HROW_EE4BEG0_3", - "INT_INTERFACE_EE4BEG0" + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CLB_CK_BUFHCLK1" ], [ - "CLK_HROW_FAN5_3", - "INT_INTERFACE_FAN5" + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CLB_CK_BUFHCLK2" ], [ - "CLK_HROW_LH8_3", - "INT_INTERFACE_LH8" + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CLB_CK_BUFHCLK3" ], [ - "CLK_BUFG_IMUX20_3", - "INT_INTERFACE_IMUX20" + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CLB_CK_BUFHCLK4" ], [ - "CLK_HROW_NE4C1_3", - "INT_INTERFACE_NE4C1" + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CLB_CK_BUFHCLK5" ], [ - "CLK_HROW_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CLB_CK_BUFHCLK6" ], [ - "CLK_HROW_FAN3_3", - "INT_INTERFACE_FAN3" + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CLB_CK_BUFHCLK7" ], [ - "CLK_HROW_SE4C1_3", - "INT_INTERFACE_SE4C1" + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CLB_CK_BUFHCLK8" ], [ - "CLK_HROW_WW4C0_3", - "INT_INTERFACE_WW4C0" + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CLB_CK_BUFHCLK9" ], [ - "CLK_HROW_WL1END1_3", - "INT_INTERFACE_WL1END1" + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CLB_CK_BUFHCLK10" ], [ - "CLK_BUFG_IMUX0_3", - "INT_INTERFACE_IMUX0" + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CLB_CK_BUFHCLK11" ], [ - "CLK_HROW_NW4END3_3", - "INT_INTERFACE_NW4END3" + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CLB_CK_BUFRCLK0" ], [ - "CLK_HROW_FAN1_3", - "INT_INTERFACE_FAN1" + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CLB_CK_BUFRCLK1" ], [ - "CLK_BUFG_IMUX6_3", - "INT_INTERFACE_IMUX6" + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CLB_CK_BUFRCLK2" ], [ - "CLK_HROW_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CLB_CK_BUFRCLK3" ], [ - "CLK_BUFG_IMUX22_3", - "INT_INTERFACE_IMUX22" + "HCLK_CLB_CK_IN0", + "HCLK_CLB_CK_IN0" ], [ - "CLK_HROW_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" + "HCLK_CLB_CK_IN1", + "HCLK_CLB_CK_IN1" ], [ - "CLK_HROW_WW4END0_3", - "INT_INTERFACE_WW4END0" + "HCLK_CLB_CK_IN2", + "HCLK_CLB_CK_IN2" ], [ - "CLK_HROW_WW2A2_3", - "INT_INTERFACE_WW2A2" + "HCLK_CLB_CK_IN3", + "HCLK_CLB_CK_IN3" ], [ - "CLK_HROW_BYP3_3", - "INT_INTERFACE_BYP3" + "HCLK_CLB_CK_IN4", + "HCLK_CLB_CK_IN4" ], [ - "CLK_HROW_BYP2_3", - "INT_INTERFACE_BYP2" + "HCLK_CLB_CK_IN5", + "HCLK_CLB_CK_IN5" ], [ - "CLK_BUFG_IMUX21_3", - "INT_INTERFACE_IMUX21" + "HCLK_CLB_CK_IN6", + "HCLK_CLB_CK_IN6" ], [ - "CLK_HROW_WW2A1_3", - "INT_INTERFACE_WW2A1" + "HCLK_CLB_CK_IN7", + "HCLK_CLB_CK_IN7" ], [ - "CLK_HROW_NE4C3_3", - "INT_INTERFACE_NE4C3" + "HCLK_CLB_CK_IN8", + "HCLK_CLB_CK_IN8" ], [ - "CLK_BUFG_IMUX44_3", - "INT_INTERFACE_IMUX44" + "HCLK_CLB_CK_IN9", + "HCLK_CLB_CK_IN9" ], [ - "CLK_HROW_EE4A2_3", - "INT_INTERFACE_EE4A2" + "HCLK_CLB_CK_IN10", + "HCLK_CLB_CK_IN10" ], [ - "CLK_HROW_EE4C2_3", - "INT_INTERFACE_EE4C2" + "HCLK_CLB_CK_IN11", + "HCLK_CLB_CK_IN11" ], [ - "CLK_BUFG_IMUX4_3", - "INT_INTERFACE_IMUX4" + "HCLK_CLB_CK_IN12", + "HCLK_CLB_CK_IN12" ], [ - "CLK_BUFG_IMUX7_3", - "INT_INTERFACE_IMUX7" + "HCLK_CLB_CK_IN13", + "HCLK_CLB_CK_IN13" ], [ - "CLK_HROW_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" + "HCLK_CLB_PERFCLK0", + "HCLK_CLB_PERFCLK0" ], [ - "CLK_HROW_LH4_3", - "INT_INTERFACE_LH4" + "HCLK_CLB_PERFCLK1", + "HCLK_CLB_PERFCLK1" ], [ - "CLK_HROW_NW4END0_3", - "INT_INTERFACE_NW4END0" + "HCLK_CLB_PERFCLK2", + "HCLK_CLB_PERFCLK2" ], [ - "CLK_HROW_WW4B2_3", - "INT_INTERFACE_WW4B2" - ], + "HCLK_CLB_PERFCLK3", + "HCLK_CLB_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L" + ], + "wire_pairs": [ [ - "CLK_HROW_EE4A3_3", - "INT_INTERFACE_EE4A3" + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" ], [ - "CLK_BUFG_IMUX27_3", - "INT_INTERFACE_IMUX27" + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" ], [ - "CLK_HROW_WR1END0_3", - "INT_INTERFACE_WR1END0" + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" ], [ - "CLK_HROW_EE4B0_3", - "INT_INTERFACE_EE4B0" + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" ], [ - "CLK_HROW_EE2A3_3", - "INT_INTERFACE_EE2A3" + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" ], [ - "CLK_BUFG_IMUX37_3", - "INT_INTERFACE_IMUX37" + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" ], [ - "CLK_HROW_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" ], [ - "CLK_HROW_WW2END3_3", - "INT_INTERFACE_WW2END3" + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" ], [ - "CLK_BUFG_IMUX36_3", - "INT_INTERFACE_IMUX36" + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" ], [ - "CLK_HROW_WW4A0_3", - "INT_INTERFACE_WW4A0" + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" ], [ - "CLK_HROW_EE4A0_3", - "INT_INTERFACE_EE4A0" + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" ], [ - "CLK_BUFG_IMUX3_3", - "INT_INTERFACE_IMUX3" + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" ], [ - "CLK_HROW_WL1END2_3", - "INT_INTERFACE_WL1END2" + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" ], [ - "CLK_HROW_SE4C0_3", - "INT_INTERFACE_SE4C0" + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" ], [ - "CLK_HROW_WW4END1_3", - "INT_INTERFACE_WW4END1" + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" ], [ - "CLK_HROW_LH7_3", - "INT_INTERFACE_LH7" + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" ], [ - "CLK_BUFG_IMUX18_3", - "INT_INTERFACE_IMUX18" + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" ], [ - "CLK_HROW_SW4END1_3", - "INT_INTERFACE_SW4END1" + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" ], [ - "CLK_HROW_EE4B3_3", - "INT_INTERFACE_EE4B3" + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" ], [ - "CLK_HROW_BYP5_3", - "INT_INTERFACE_BYP5" + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" ], [ - "CLK_BUFG_IMUX10_3", - "INT_INTERFACE_IMUX10" + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" ], [ - "CLK_HROW_WR1END1_3", - "INT_INTERFACE_WR1END1" + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" ], [ - "CLK_HROW_WW4B1_3", - "INT_INTERFACE_WW4B1" + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" ], [ - "CLK_HROW_SW4A2_3", - "INT_INTERFACE_SW4A2" + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" ], [ - "CLK_BUFG_IMUX23_3", - "INT_INTERFACE_IMUX23" + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" ], [ - "CLK_BUFG_IMUX42_3", - "INT_INTERFACE_IMUX42" + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" ], [ - "CLK_BUFG_IMUX30_3", - "INT_INTERFACE_IMUX30" + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" ], [ - "CLK_BUFG_LOGIC_OUTS_B0_3", - "INT_INTERFACE_LOGIC_OUTS_B0" + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" ], [ - "CLK_HROW_NE4C2_3", - "INT_INTERFACE_NE4C2" + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" ], [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" ], [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" ], [ - "CLK_BUFG_IMUX15_3", - "INT_INTERFACE_IMUX15" + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" ], [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" ], [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L_BOT_UTURN" + ], + "wire_pairs": [ [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" ], [ - "CLK_BUFG_IMUX26_3", - "INT_INTERFACE_IMUX26" + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" ], [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" ], [ - "CLK_HROW_FAN0_3", - "INT_INTERFACE_FAN0" + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" ], [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" ], [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" ], [ - "CLK_BUFG_IMUX28_3", - "INT_INTERFACE_IMUX28" + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" ], [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" ], [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" ], [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" ], [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" ], [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" ], [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" ], [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" ], [ - "CLK_BUFG_IMUX45_3", - "INT_INTERFACE_IMUX45" + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" ], [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" ], [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" ], [ - "CLK_BUFG_IMUX17_3", - "INT_INTERFACE_IMUX17" + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" ], [ - "CLK_BUFG_IMUX24_3", - "INT_INTERFACE_IMUX24" + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" ], [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" ], [ - "CLK_BUFG_IMUX9_3", - "INT_INTERFACE_IMUX9" + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" ], [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" ] ] }, { "grid_deltas": [ -1, - -2 + 0 ], "tile_types": [ - "CFG_CENTER_MID", - "INT_FEEDTHRU_2" + "HCLK_CLB", + "HCLK_R" ], "wire_pairs": [ [ - "CFG_CENTER_WW4C2_12", - "INT_FEEDTHRU_2_WW4C2" + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" ], [ - "CFG_CENTER_WW4C3_12", - "INT_FEEDTHRU_2_WW4C3" + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" ], [ - "CFG_CENTER_WL1END3_12", - "INT_FEEDTHRU_2_WL1END3" + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" ], [ - "CFG_CENTER_WW4B1_12", - "INT_FEEDTHRU_2_WW4B1" + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" ], [ - "CFG_CENTER_NE4BEG0_12", - "INT_FEEDTHRU_2_NE4BEG0" + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" ], [ - "CFG_CENTER_EE4BEG1_12", - "INT_FEEDTHRU_2_EE4BEG1" + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" ], [ - "CFG_CENTER_NW4A2_12", - "INT_FEEDTHRU_2_NW4A2" + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" ], [ - "CFG_CENTER_WW2END1_12", - "INT_FEEDTHRU_2_WW2END1" + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" ], [ - "CFG_CENTER_LH2_12", - "INT_FEEDTHRU_2_LH2" + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" ], [ - "CFG_CENTER_EE4B2_12", - "INT_FEEDTHRU_2_EE4B2" + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" ], [ - "CFG_CENTER_EE2A0_12", - "INT_FEEDTHRU_2_EE2A0" + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" ], [ - "CFG_CENTER_NE4BEG3_12", - "INT_FEEDTHRU_2_NE4BEG3" + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" ], [ - "CFG_CENTER_EE4A1_12", - "INT_FEEDTHRU_2_EE4A1" + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" ], [ - "CFG_CENTER_SW4A1_12", - "INT_FEEDTHRU_2_SW4A1" + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" ], [ - "CFG_CENTER_WL1END2_12", - "INT_FEEDTHRU_2_WL1END2" + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" ], [ - "CFG_CENTER_SW4A0_12", - "INT_FEEDTHRU_2_SW4A0" + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" ], [ - "CFG_CENTER_WL1END1_12", - "INT_FEEDTHRU_2_WL1END1" + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" ], [ - "CFG_CENTER_ER1BEG0_12", - "INT_FEEDTHRU_2_ER1BEG0" + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" ], [ - "CFG_CENTER_WW2END2_12", - "INT_FEEDTHRU_2_WW2END2" + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" ], [ - "CFG_CENTER_SE4BEG3_12", - "INT_FEEDTHRU_2_SE4BEG3" + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" ], [ - "CFG_CENTER_EE4C0_12", - "INT_FEEDTHRU_2_EE4C0" + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" ], [ - "CFG_CENTER_EE2A3_12", - "INT_FEEDTHRU_2_EE2A3" + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" ], [ - "CFG_CENTER_EL1BEG1_12", - "INT_FEEDTHRU_2_EL1BEG1" + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" ], [ - "CFG_CENTER_NE4BEG1_12", - "INT_FEEDTHRU_2_NE4BEG1" + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" ], [ - "CFG_CENTER_EE4A0_12", - "INT_FEEDTHRU_2_EE4A0" + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" ], [ - "CFG_CENTER_EE4A3_12", - "INT_FEEDTHRU_2_EE4A3" + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" ], [ - "CFG_CENTER_EE4C2_12", - "INT_FEEDTHRU_2_EE4C2" + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" ], [ - "CFG_CENTER_WW4C0_12", - "INT_FEEDTHRU_2_WW4C0" + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" ], [ - "CFG_CENTER_NE4C0_12", - "INT_FEEDTHRU_2_NE4C0" + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" ], [ - "CFG_CENTER_ER1BEG1_12", - "INT_FEEDTHRU_2_ER1BEG1" + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" ], [ - "CFG_CENTER_EE2BEG3_12", - "INT_FEEDTHRU_2_EE2BEG3" + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" ], [ - "CFG_CENTER_WW4A3_12", - "INT_FEEDTHRU_2_WW4A3" + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" ], [ - "CFG_CENTER_SW4END2_12", - "INT_FEEDTHRU_2_SW4END2" + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" ], [ - "CFG_CENTER_EE4B0_12", - "INT_FEEDTHRU_2_EE4B0" + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_R_BOT_UTURN" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VFRAME" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VFRAME_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VFRAME_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_FIFO_L" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_CLK_0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_MUX_CLK_1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_MUX_CLK_2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_MUX_CLK_3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_MUX_CLK_4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_MUX_CLK_5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_MUX_CLK_6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_MUX_CLK_7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_MUX_CLK_8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_MUX_CLK_9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_MUX_CLK_10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_MUX_CLK_11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_MUX_CLK_12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_MUX_CLK_13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_FIFO_L" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_FEEDTHRU_1" + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_1_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_1_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_1_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_1_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_1_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + 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"HCLK_FIFO_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_FIFO_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_FIFO_PERFCLK0", + "HCLK_INT_INTERFACE_PERFCLK0" + ], + [ + "HCLK_FIFO_PERFCLK1", + "HCLK_INT_INTERFACE_PERFCLK1" + ], + [ + "HCLK_FIFO_PERFCLK2", + "HCLK_INT_INTERFACE_PERFCLK2" + ], + [ + "HCLK_FIFO_PERFCLK3", + "HCLK_INT_INTERFACE_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_FIFO_L", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_FIFO_CCIO0", + "HCLK_INT_INTERFACE_CCIO0" + ], + [ + "HCLK_FIFO_CCIO1", + "HCLK_INT_INTERFACE_CCIO1" + ], + [ + "HCLK_FIFO_CCIO2", + "HCLK_INT_INTERFACE_CCIO2" + ], + [ + "HCLK_FIFO_CCIO3", + "HCLK_INT_INTERFACE_CCIO3" + ], + [ + "HCLK_FIFO_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_FIFO_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_FIFO_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_FIFO_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_FIFO_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_FIFO_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_FIFO_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_FIFO_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_FIFO_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_FIFO_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_FIFO_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_FIFO_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_FIFO_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_FIFO_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_FIFO_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_FIFO_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_FIFO_PERFCLK0", + "HCLK_INT_INTERFACE_PERFCLK0" + ], + [ + "HCLK_FIFO_PERFCLK1", + "HCLK_INT_INTERFACE_PERFCLK1" + ], + [ + "HCLK_FIFO_PERFCLK2", + "HCLK_INT_INTERFACE_PERFCLK2" + ], + [ + "HCLK_FIFO_PERFCLK3", + "HCLK_INT_INTERFACE_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_GTX", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_GTX_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_GTX_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_GTX_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_GTX_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_GTX_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_GTX_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_GTX_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_GTX_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_GTX_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_GTX_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_GTX", + "HCLK_TERM_GTX" + ], + "wire_pairs": [ + [ + "HCLK_GTX_CK_IN4", + "HCLK_TERM_GTX_CK_IN4" + ], + [ + "HCLK_GTX_CK_IN5", + "HCLK_TERM_GTX_CK_IN5" + ], + [ + "HCLK_GTX_CK_IN6", + "HCLK_TERM_GTX_CK_IN6" + ], + [ + "HCLK_GTX_CK_IN7", + "HCLK_TERM_GTX_CK_IN7" + ], + [ + "HCLK_GTX_CK_IN8", + "HCLK_TERM_GTX_CK_IN8" + ], + [ + "HCLK_GTX_CK_IN9", + "HCLK_TERM_GTX_CK_IN9" + ], + [ + "HCLK_GTX_CK_IN10", + "HCLK_TERM_GTX_CK_IN10" + ], + [ + "HCLK_GTX_CK_IN11", + "HCLK_TERM_GTX_CK_IN11" + ], + [ + "HCLK_GTX_CK_IN12", + "HCLK_TERM_GTX_CK_IN12" + ], + [ + "HCLK_GTX_CK_IN13", + "HCLK_TERM_GTX_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_L" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" ], [ - "CFG_CENTER_NW2A0_12", - "INT_FEEDTHRU_2_NW2A0" + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_CK_IN0" ], [ - "CFG_CENTER_SW4END0_12", - "INT_FEEDTHRU_2_SW4END0" + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_CK_IN1" ], [ - "CFG_CENTER_EE2A1_12", - "INT_FEEDTHRU_2_EE2A1" + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_CK_IN2" ], [ - "CFG_CENTER_LH4_12", - "INT_FEEDTHRU_2_LH4" + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_CK_IN3" ], [ - "CFG_CENTER_EE4C3_12", - "INT_FEEDTHRU_2_EE4C3" + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_CK_IN4" ], [ - "CFG_CENTER_WW2END3_12", - "INT_FEEDTHRU_2_WW2END3" + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_CK_IN5" ], [ - "CFG_CENTER_SE4BEG1_12", - "INT_FEEDTHRU_2_SE4BEG1" + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_CK_IN6" ], [ - "CFG_CENTER_LH5_12", - "INT_FEEDTHRU_2_LH5" + "HCLK_INT_INTERFACE_CK_IN7", + "HCLK_CK_IN7" ], [ - "CFG_CENTER_WW4END3_12", - "INT_FEEDTHRU_2_WW4END3" + "HCLK_INT_INTERFACE_CK_IN8", + "HCLK_CK_IN8" ], [ - "CFG_CENTER_WW4END1_12", - "INT_FEEDTHRU_2_WW4END1" + "HCLK_INT_INTERFACE_CK_IN9", + "HCLK_CK_IN9" ], [ - "CFG_CENTER_EE2BEG2_12", - "INT_FEEDTHRU_2_EE2BEG2" + "HCLK_INT_INTERFACE_CK_IN10", + "HCLK_CK_IN10" ], [ - "CFG_CENTER_EE4BEG3_12", - "INT_FEEDTHRU_2_EE4BEG3" + "HCLK_INT_INTERFACE_CK_IN11", + "HCLK_CK_IN11" ], [ - "CFG_CENTER_SW4END1_12", - "INT_FEEDTHRU_2_SW4END1" + "HCLK_INT_INTERFACE_CK_IN12", + "HCLK_CK_IN12" ], [ - "CFG_CENTER_WW4A1_12", - "INT_FEEDTHRU_2_WW4A1" + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_CK_IN13" ], [ - "CFG_CENTER_NW4END2_12", - "INT_FEEDTHRU_2_NW4END2" + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_INT_PERFCLK0" ], [ - "CFG_CENTER_SW2A2_12", - "INT_FEEDTHRU_2_SW2A2" + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_INT_PERFCLK1" ], [ - "CFG_CENTER_LH12_12", - "INT_FEEDTHRU_2_LH12" + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_INT_PERFCLK2" ], [ - "CFG_CENTER_NW4A0_12", - "INT_FEEDTHRU_2_NW4A0" + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_R" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], 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"HCLK_CK_IN11" + ], + [ + "HCLK_INT_INTERFACE_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_VFRAME" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" ], [ - "CFG_CENTER_WW2A2_12", - "INT_FEEDTHRU_2_WW2A2" + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" ], [ - "CFG_CENTER_LH7_12", - "INT_FEEDTHRU_2_LH7" + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" ], [ - "CFG_CENTER_NE2A2_12", - "INT_FEEDTHRU_2_NE2A2" + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" ], [ - "CFG_CENTER_EL1BEG2_12", - "INT_FEEDTHRU_2_EL1BEG2" + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" ], [ - "CFG_CENTER_WW2A1_12", - "INT_FEEDTHRU_2_WW2A1" + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_VFRAME_CK_IN0" ], [ - "CFG_CENTER_SE2A1_12", - "INT_FEEDTHRU_2_SE2A1" + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_VFRAME_CK_IN1" ], [ - "CFG_CENTER_WW4C1_12", - "INT_FEEDTHRU_2_WW4C1" + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_VFRAME_CK_IN2" ], [ - "CFG_CENTER_NW4A1_12", - "INT_FEEDTHRU_2_NW4A1" + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_VFRAME_CK_IN3" ], [ - "CFG_CENTER_LH6_12", - "INT_FEEDTHRU_2_LH6" + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_VFRAME_CK_IN4" ], [ - "CFG_CENTER_SE2A3_12", - "INT_FEEDTHRU_2_SE2A3" + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_VFRAME_CK_IN5" ], [ - "CFG_CENTER_LH3_12", - "INT_FEEDTHRU_2_LH3" + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_VFRAME_CK_IN6" ], [ - "CFG_CENTER_NE2A3_12", - "INT_FEEDTHRU_2_NE2A3" + "HCLK_INT_INTERFACE_CK_IN7", + "HCLK_VFRAME_CK_IN7" ], [ - "CFG_CENTER_WR1END3_12", - "INT_FEEDTHRU_2_WR1END3" + "HCLK_INT_INTERFACE_CK_IN8", + "HCLK_VFRAME_CK_IN8" ], [ - "CFG_CENTER_LH10_12", - "INT_FEEDTHRU_2_LH10" + "HCLK_INT_INTERFACE_CK_IN9", + "HCLK_VFRAME_CK_IN9" ], [ - "CFG_CENTER_WW4END0_12", - "INT_FEEDTHRU_2_WW4END0" + "HCLK_INT_INTERFACE_CK_IN10", + "HCLK_VFRAME_CK_IN10" ], [ - "CFG_CENTER_WL1END0_12", - "INT_FEEDTHRU_2_WL1END0" + "HCLK_INT_INTERFACE_CK_IN11", + "HCLK_VFRAME_CK_IN11" ], [ - "CFG_CENTER_LH11_12", - "INT_FEEDTHRU_2_LH11" + "HCLK_INT_INTERFACE_CK_IN12", + "HCLK_VFRAME_CK_IN12" ], [ - "CFG_CENTER_SW2A1_12", - "INT_FEEDTHRU_2_SW2A1" + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_IOB", + "HCLK_IOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOI_CK_BUFHCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOI_CK_BUFHCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK2", + "HCLK_IOI_CK_BUFHCLK2" + ], + [ + "HCLK_IOB_CK_BUFHCLK3", + "HCLK_IOI_CK_BUFHCLK3" + ], + [ + "HCLK_IOB_CK_BUFHCLK4", + "HCLK_IOI_CK_BUFHCLK4" + ], + [ + "HCLK_IOB_CK_BUFHCLK5", + "HCLK_IOI_CK_BUFHCLK5" + ], + [ + "HCLK_IOB_CK_BUFHCLK6", + "HCLK_IOI_CK_BUFHCLK6" + ], + [ + "HCLK_IOB_CK_BUFHCLK7", + "HCLK_IOI_CK_BUFHCLK7" + ], + [ + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOI_CK_BUFHCLK8" + ], + [ + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOI_CK_BUFHCLK9" + ], + [ + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOI_CK_BUFHCLK10" + ], + [ + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOI_CK_BUFHCLK11" + ], + [ + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOI_CK_BUFRCLK0" + ], + [ + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFRCLK1" + ], + [ + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOI_CK_BUFRCLK2" + ], + [ + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOI_CK_BUFRCLK3" + ], + [ + "HCLK_IOB_PERFCLK0", + "HCLK_IOI_IOCLK_PLL0" + ], + [ + "HCLK_IOB_PERFCLK1", + "HCLK_IOI_IOCLK_PLL1" + ], + [ + "HCLK_IOB_PERFCLK2", + "HCLK_IOI_IOCLK_PLL2" + ], + [ + "HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_IOB", + "HCLK_IOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOI_CK_BUFHCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOI_CK_BUFHCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK2", + "HCLK_IOI_CK_BUFHCLK2" + ], + [ + "HCLK_IOB_CK_BUFHCLK3", + "HCLK_IOI_CK_BUFHCLK3" + ], + [ + "HCLK_IOB_CK_BUFHCLK4", + "HCLK_IOI_CK_BUFHCLK4" ], [ - "CFG_CENTER_EE2A2_12", - "INT_FEEDTHRU_2_EE2A2" + "HCLK_IOB_CK_BUFHCLK5", + "HCLK_IOI_CK_BUFHCLK5" ], [ - "CFG_CENTER_EE4C1_12", - "INT_FEEDTHRU_2_EE4C1" + "HCLK_IOB_CK_BUFHCLK6", + "HCLK_IOI_CK_BUFHCLK6" ], [ - "CFG_CENTER_NE4BEG2_12", - "INT_FEEDTHRU_2_NE4BEG2" + "HCLK_IOB_CK_BUFHCLK7", + "HCLK_IOI_CK_BUFHCLK7" ], [ - "CFG_CENTER_WR1END2_12", - "INT_FEEDTHRU_2_WR1END2" + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOI_CK_BUFHCLK8" ], [ - "CFG_CENTER_NE4C3_12", - "INT_FEEDTHRU_2_NE4C3" + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOI_CK_BUFHCLK9" ], [ - "CFG_CENTER_WW4END2_12", - "INT_FEEDTHRU_2_WW4END2" + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOI_CK_BUFHCLK10" ], [ - "CFG_CENTER_EE2BEG0_12", - "INT_FEEDTHRU_2_EE2BEG0" + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOI_CK_BUFHCLK11" ], [ - "CFG_CENTER_WW4B2_12", - "INT_FEEDTHRU_2_WW4B2" + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOI_CK_BUFRCLK0" ], [ - "CFG_CENTER_NW2A3_12", - "INT_FEEDTHRU_2_NW2A3" + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFRCLK1" ], [ - "CFG_CENTER_NE2A1_12", - "INT_FEEDTHRU_2_NE2A1" + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOI_CK_BUFRCLK2" ], [ - "CFG_CENTER_SE4BEG0_12", - "INT_FEEDTHRU_2_SE4BEG0" + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOI_CK_BUFRCLK3" ], [ - "CFG_CENTER_WW4B0_12", - "INT_FEEDTHRU_2_WW4B0" + "HCLK_IOB_PERFCLK0", + "HCLK_IOI_IOCLK_PLL0" ], [ - "CFG_CENTER_SW4END3_12", - "INT_FEEDTHRU_2_SW4END3" + "HCLK_IOB_PERFCLK1", + "HCLK_IOI_IOCLK_PLL1" ], [ - "CFG_CENTER_NW2A2_12", - "INT_FEEDTHRU_2_NW2A2" + "HCLK_IOB_PERFCLK2", + "HCLK_IOI_IOCLK_PLL2" ], [ - "CFG_CENTER_EE4BEG0_12", - "INT_FEEDTHRU_2_EE4BEG0" + "HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_IOI3", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" ], [ - "CFG_CENTER_WW2A0_12", - "INT_FEEDTHRU_2_WW2A0" + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" ], [ - "CFG_CENTER_NW4END1_12", - "INT_FEEDTHRU_2_NW4END1" + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" ], [ - "CFG_CENTER_NE2A0_12", - "INT_FEEDTHRU_2_NE2A0" + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" ], [ - "CFG_CENTER_NW4END3_12", - "INT_FEEDTHRU_2_NW4END3" + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" ], [ - "CFG_CENTER_EE4A2_12", - "INT_FEEDTHRU_2_EE4A2" + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" ], [ - "CFG_CENTER_WW4A2_12", - "INT_FEEDTHRU_2_WW4A2" + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" ], [ - "CFG_CENTER_WR1END0_12", - "INT_FEEDTHRU_2_WR1END0" + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" ], [ - "CFG_CENTER_NE4C1_12", - "INT_FEEDTHRU_2_NE4C1" + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" ], [ - "CFG_CENTER_SW4A2_12", - "INT_FEEDTHRU_2_SW4A2" + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" ], [ - "CFG_CENTER_SW2A3_12", - "INT_FEEDTHRU_2_SW2A3" + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" ], [ - "CFG_CENTER_SE2A0_12", - "INT_FEEDTHRU_2_SE2A0" + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" ], [ - "CFG_CENTER_EE4B3_12", - "INT_FEEDTHRU_2_EE4B3" + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" ], [ - "CFG_CENTER_EL1BEG0_12", - "INT_FEEDTHRU_2_EL1BEG0" + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" ], [ - "CFG_CENTER_SE4C0_12", - "INT_FEEDTHRU_2_SE4C0" + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" ], [ - "CFG_CENTER_SW4A3_12", - "INT_FEEDTHRU_2_SW4A3" + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" ], [ - "CFG_CENTER_EE2BEG1_12", - "INT_FEEDTHRU_2_EE2BEG1" + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_IOI3", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" ], [ - "CFG_CENTER_WR1END1_12", - "INT_FEEDTHRU_2_WR1END1" + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" ], [ - "CFG_CENTER_LH9_12", - "INT_FEEDTHRU_2_LH9" + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" ], [ - "CFG_CENTER_SE4C1_12", - "INT_FEEDTHRU_2_SE4C1" + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" ], [ - "CFG_CENTER_ER1BEG2_12", - "INT_FEEDTHRU_2_ER1BEG2" + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" ], [ - "CFG_CENTER_WW4A0_12", - "INT_FEEDTHRU_2_WW4A0" + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" ], [ - "CFG_CENTER_NW2A1_12", - "INT_FEEDTHRU_2_NW2A1" + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" ], [ - "CFG_CENTER_SE4BEG2_12", - "INT_FEEDTHRU_2_SE4BEG2" + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" ], [ - "CFG_CENTER_WW2END0_12", - "INT_FEEDTHRU_2_WW2END0" + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" ], [ - "CFG_CENTER_ER1BEG3_12", - "INT_FEEDTHRU_2_ER1BEG3" + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" ], [ - "CFG_CENTER_NW4A3_12", - "INT_FEEDTHRU_2_NW4A3" + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" ], [ - "CFG_CENTER_LH1_12", - "INT_FEEDTHRU_2_LH1" + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" ], [ - "CFG_CENTER_SE4C2_12", - "INT_FEEDTHRU_2_SE4C2" + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" ], [ - "CFG_CENTER_WW2A3_12", - "INT_FEEDTHRU_2_WW2A3" + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" ], [ - "CFG_CENTER_SE2A2_12", - "INT_FEEDTHRU_2_SE2A2" + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" ], [ - "CFG_CENTER_SE4C3_12", - "INT_FEEDTHRU_2_SE4C3" + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" ], [ - "CFG_CENTER_WW4B3_12", - "INT_FEEDTHRU_2_WW4B3" + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" ], [ - "CFG_CENTER_SW2A0_12", - "INT_FEEDTHRU_2_SW2A0" + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" ], [ - "CFG_CENTER_EE4B1_12", - "INT_FEEDTHRU_2_EE4B1" + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" ], [ - "CFG_CENTER_EE4BEG2_12", - "INT_FEEDTHRU_2_EE4BEG2" + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" ], [ - "CFG_CENTER_NW4END0_12", - "INT_FEEDTHRU_2_NW4END0" + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" ], [ - "CFG_CENTER_LH8_12", - "INT_FEEDTHRU_2_LH8" + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" ], [ - "CFG_CENTER_NE4C2_12", - "INT_FEEDTHRU_2_NE4C2" + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" ], [ - "CFG_CENTER_EL1BEG3_12", - "INT_FEEDTHRU_2_EL1BEG3" + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" ] ] }, { "grid_deltas": [ 0, - -5 + -1 ], "tile_types": [ - "BRAM_L", - "BRAM_L" + "HCLK_IOI3", + "LIOI3" ], "wire_pairs": [ [ - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRAM_CASCOUT_ADDRBWRADDRU3" + "HCLK_IOI_I2IOCLK_TOP0", + "LIOI_I2GCLK_TOP0" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRAM_CASCOUT_ADDRARDADDRU4" + "HCLK_IOI_I2IOCLK_TOP1", + "LIOI_I2GCLK_TOP1" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRAM_CASCOUT_ADDRBWRADDRU14" + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU9" + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU0" + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRAM_CASCOUT_ADDRARDADDRU1" + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRAM_CASCOUT_ADDRBWRADDRU5" + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" ], [ - "BRAM_PMVBRAM_O", - "BRAM_PMVBRAM_O_1" + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRAM_CASCOUT_ADDRBWRADDRU11" + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU7" + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRAM_CASCOUT_ADDRARDADDRU5" + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRAM_CASCOUT_ADDRBWRADDRU1" + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRAM_CASCOUT_ADDRBWRADDRU8" + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRAM_CASCOUT_ADDRARDADDRU14" + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRAM_CASCOUT_ADDRARDADDRU2" + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRARDADDRU9" + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRAM_CASCOUT_ADDRARDADDRU10" + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRAM_CASCOUT_ADDRBWRADDRU2" + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRAM_CASCOUT_ADDRBWRADDRU10" + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRAM_CASCOUT_ADDRBWRADDRU13" + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRAM_CASCOUT_ADDRBWRADDRU4" + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRAM_CASCOUT_ADDRARDADDRU0" + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRARDADDRU7" + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRAM_CASCOUT_ADDRBWRADDRU6" + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRAM_CASCOUT_ADDRARDADDRU8" + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ] + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "tile_types": [ + "HCLK_IOI3", + "LIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_BOT0", + "LIOI_I2GCLK_BOT1" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU11" + "HCLK_IOI_I2IOCLK_BOT1", + "LIOI_I2GCLK_TOP0" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRAM_CASCOUT_ADDRARDADDRU12" + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" ], [ - "BRAM_PMVBRAM_ODIV2", - "BRAM_PMVBRAM_ODIV2_1" + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRAM_CASCOUT_ADDRARDADDRU3" + "HCLK_IOI_IDELAYCTRL_RDY", + "IOI_IDELAYCTRL_RDY" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRAM_CASCOUT_ADDRBWRADDRU12" + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" ], [ - "BRAM_PMVBRAM_O_1", - "BRAM_PMVBRAM_O_2" + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRAM_CASCOUT_ADDRARDADDRU13" + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRAM_CASCOUT_ADDRARDADDRU6" + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX2", + "IOI_IMUX_RC2" + ], + [ + "HCLK_IOI_RCLK_IMUX3", + "IOI_IMUX_RC3" + ], + [ + "HCLK_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2" + ], + [ + "HCLK_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3" + ], + [ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "HCLK_IOI3", + "RIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_TOP0", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "RIOI_I2GCLK_TOP1" + ], + [ + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" + ], + [ + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" + ], + [ + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" + ], + [ + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" + ], + [ + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" + ], + [ + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" + ], + [ + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" + ], + [ + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ] + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "tile_types": [ + "HCLK_IOI3", + "RIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_BOT0", + "RIOI_I2GCLK_BOT1" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ], + [ + "HCLK_IOI_IDELAYCTRL_RDY", + "IOI_IDELAYCTRL_RDY" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX2", + "IOI_IMUX_RC2" + ], + [ + "HCLK_IOI_RCLK_IMUX3", + "IOI_IMUX_RC3" + ], + [ + "HCLK_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2" + ], + [ + "HCLK_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3" + ], + [ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_L", + "HCLK_R" + ], + "wire_pairs": [ + [ + "HCLK_CCIO0", + "HCLK_CCIO0" + ], + [ + "HCLK_CCIO1", + "HCLK_CCIO1" + ], + [ + "HCLK_CCIO2", + "HCLK_CCIO2" + ], + [ + "HCLK_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CK_INOUT_L0", + "HCLK_CK_OUTIN_R4" + ], + [ + "HCLK_CK_INOUT_L1", + "HCLK_CK_OUTIN_R5" + ], + [ + "HCLK_CK_INOUT_L2", + "HCLK_CK_OUTIN_R6" + ], + [ + "HCLK_CK_INOUT_L3", + "HCLK_CK_OUTIN_R7" + ], + [ + "HCLK_CK_INOUT_L4", + "HCLK_CK_OUTIN_R0" + ], + [ + "HCLK_CK_INOUT_L5", + "HCLK_CK_OUTIN_R1" + ], + [ + "HCLK_CK_INOUT_L6", + "HCLK_CK_OUTIN_R2" + ], + [ + "HCLK_CK_INOUT_L7", + "HCLK_CK_OUTIN_R3" + ], + [ + "HCLK_CK_OUTIN_L0", + "HCLK_CK_INOUT_R0" + ], + [ + "HCLK_CK_OUTIN_L1", + "HCLK_CK_INOUT_R1" + ], + [ + "HCLK_CK_OUTIN_L2", + "HCLK_CK_INOUT_R2" + ], + [ + "HCLK_CK_OUTIN_L3", + "HCLK_CK_INOUT_R3" + ], + [ + "HCLK_CK_OUTIN_L4", + "HCLK_CK_INOUT_R4" + ], + [ + "HCLK_CK_OUTIN_L5", + "HCLK_CK_INOUT_R5" + ], + [ + "HCLK_CK_OUTIN_L6", + "HCLK_CK_INOUT_R6" + ], + [ + "HCLK_CK_OUTIN_L7", + "HCLK_CK_INOUT_R7" + ], + [ + "HCLK_INT_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_INT_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_INT_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_INT_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "HCLK_L", + "INT_L" + ], + "wire_pairs": [ + [ + "HCLK_BYP_BOUNCE2", + "BYP_BOUNCE_N3_2" + ], + [ + "HCLK_BYP_BOUNCE3", + "BYP_BOUNCE_N3_3" + ], + [ + "HCLK_BYP_BOUNCE6", + "BYP_BOUNCE_N3_6" + ], + [ + "HCLK_BYP_BOUNCE7", + "BYP_BOUNCE_N3_7" + ], + [ + "HCLK_EL1BEG3", + "EL1BEG_N3" + ], + [ + "HCLK_EL1END_S3_0", + "EL1END0" + ], + [ + "HCLK_ER1BEG_S0", + "ER1BEG0" + ], + [ + "HCLK_ER1END3", + "ER1END_N3_3" + ], + [ + "HCLK_FAN_BOUNCE_S3_0", + "FAN_BOUNCE0" + ], + [ + "HCLK_FAN_BOUNCE_S3_2", + "FAN_BOUNCE2" + ], + [ + "HCLK_FAN_BOUNCE_S3_4", + "FAN_BOUNCE4" + ], + [ + "HCLK_FAN_BOUNCE_S3_6", + "FAN_BOUNCE6" + ], + [ + "HCLK_LEAF_CLK_B_TOPL0", + "GCLK_L_B6" + ], + [ + "HCLK_LEAF_CLK_B_TOPL1", + "GCLK_L_B7" + ], + [ + "HCLK_LEAF_CLK_B_TOPL2", + "GCLK_L_B8" + ], + [ + "HCLK_LEAF_CLK_B_TOPL3", + "GCLK_L_B9" + ], + [ + "HCLK_LEAF_CLK_B_TOPL4", + "GCLK_L_B10" + ], + [ + "HCLK_LEAF_CLK_B_TOPL5", + "GCLK_L_B11" + ], + [ + "HCLK_LV0", + "LV_L1" + ], + [ + "HCLK_LV1", + "LV_L2" + ], + [ + "HCLK_LV2", + "LV_L3" + ], + [ + "HCLK_LV3", + "LV_L4" + ], + [ + "HCLK_LV4", + "LV_L5" + ], + [ + "HCLK_LV5", + "LV_L6" + ], + [ + "HCLK_LV6", + "LV_L7" + ], + [ + "HCLK_LV7", + "LV_L8" + ], + [ + "HCLK_LV8", + "LV_L9" + ], + [ + "HCLK_LV9", + "LV_L10" + ], + [ + "HCLK_LV10", + "LV_L11" + ], + [ + "HCLK_LV11", + "LV_L12" + ], + [ + "HCLK_LV12", + "LV_L13" + ], + [ + "HCLK_LV13", + "LV_L14" + ], + [ + "HCLK_LV14", + "LV_L15" + ], + [ + "HCLK_LV15", + "LV_L16" + ], + [ + "HCLK_LV16", + "LV_L17" + ], + [ + "HCLK_LV17", + "LV_L18" + ], + [ + "HCLK_LVB1", + "LVB_L1" + ], + [ + "HCLK_LVB2", + "LVB_L2" + ], + [ + "HCLK_LVB3", + "LVB_L3" + ], + [ + "HCLK_LVB4", + "LVB_L4" + ], + [ + "HCLK_LVB5", + "LVB_L5" + ], + [ + "HCLK_LVB6", + "LVB_L6" + ], + [ + "HCLK_LVB7", + "LVB_L7" + ], + [ + "HCLK_LVB8", + "LVB_L8" + ], + [ + "HCLK_LVB9", + "LVB_L9" + ], + [ + "HCLK_LVB10", + "LVB_L10" + ], + [ + "HCLK_LVB11", + "LVB_L11" + ], + [ + "HCLK_LVB12", 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"IMUX_L30" + ], + [ + "INT_INTERFACE_IMUX31", + "IMUX_L31" + ], + [ + "INT_INTERFACE_IMUX32", + "IMUX_L32" + ], + [ + "INT_INTERFACE_IMUX33", + "IMUX_L33" + ], + [ + "INT_INTERFACE_IMUX34", + "IMUX_L34" + ], + [ + "INT_INTERFACE_IMUX35", + "IMUX_L35" + ], + [ + "INT_INTERFACE_IMUX36", + "IMUX_L36" + ], + [ + "INT_INTERFACE_IMUX37", + "IMUX_L37" + ], + [ + "INT_INTERFACE_IMUX38", + "IMUX_L38" + ], + [ + "INT_INTERFACE_IMUX39", + "IMUX_L39" + ], + [ + "INT_INTERFACE_IMUX40", + "IMUX_L40" + ], + [ + "INT_INTERFACE_IMUX41", + "IMUX_L41" + ], + [ + "INT_INTERFACE_IMUX42", + "IMUX_L42" + ], + [ + "INT_INTERFACE_IMUX43", + "IMUX_L43" + ], + [ + "INT_INTERFACE_IMUX44", + "IMUX_L44" + ], + [ + "INT_INTERFACE_IMUX45", + "IMUX_L45" + ], + [ + "INT_INTERFACE_IMUX46", + "IMUX_L46" + ], + [ + "INT_INTERFACE_IMUX47", + "IMUX_L47" + ], + [ + "INT_INTERFACE_LH1", + "LH0" + ], + [ + "INT_INTERFACE_LH2", + "LH1" + ], + [ + "INT_INTERFACE_LH3", + "LH2" + ], + [ + "INT_INTERFACE_LH4", + "LH3" + ], + [ + "INT_INTERFACE_LH5", + "LH4" + ], + [ + "INT_INTERFACE_LH6", + "LH5" + ], + [ + "INT_INTERFACE_LH7", + "LH6" + ], + [ + "INT_INTERFACE_LH8", + "LH7" + ], + [ + "INT_INTERFACE_LH9", + "LH8" + ], + [ + "INT_INTERFACE_LH10", + "LH9" + ], + [ + "INT_INTERFACE_LH11", + "LH10" + ], + [ + "INT_INTERFACE_LH12", + "LH11" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L0", + "LOGIC_OUTS_L0" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L1", + "LOGIC_OUTS_L1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L2", + "LOGIC_OUTS_L2" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L3", + "LOGIC_OUTS_L3" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L4", + "LOGIC_OUTS_L4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L5", + "LOGIC_OUTS_L5" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L6", + "LOGIC_OUTS_L6" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L7", + "LOGIC_OUTS_L7" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L8", + "LOGIC_OUTS_L8" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L9", + "LOGIC_OUTS_L9" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L10", + "LOGIC_OUTS_L10" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L11", + "LOGIC_OUTS_L11" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L12", + "LOGIC_OUTS_L12" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L13", + "LOGIC_OUTS_L13" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L14", + "LOGIC_OUTS_L14" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L15", + "LOGIC_OUTS_L15" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L16", + "LOGIC_OUTS_L16" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L17", + "LOGIC_OUTS_L17" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L18", + "LOGIC_OUTS_L18" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L19", + "LOGIC_OUTS_L19" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L20", + "LOGIC_OUTS_L20" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L21", + "LOGIC_OUTS_L21" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L22", + "LOGIC_OUTS_L22" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L23", + "LOGIC_OUTS_L23" + ], + [ + "INT_INTERFACE_MONITOR_N", + "MONITOR_N" + ], + [ + "INT_INTERFACE_MONITOR_P", + "MONITOR_P" + ], + [ + "INT_INTERFACE_NE2A0", + "NE2END0" + ], + [ + "INT_INTERFACE_NE2A1", + "NE2END1" + ], + [ + "INT_INTERFACE_NE2A2", + "NE2END2" + ], + [ + "INT_INTERFACE_NE2A3", + "NE2END3" + ], + [ + "INT_INTERFACE_NE4BEG0", + "NE6A0" + ], + [ + "INT_INTERFACE_NE4BEG1", + "NE6A1" + ], + [ + "INT_INTERFACE_NE4BEG2", + "NE6A2" + ], + [ + "INT_INTERFACE_NE4BEG3", + "NE6A3" + ], + [ + "INT_INTERFACE_NE4C0", + "NE6END0" + ], + [ + "INT_INTERFACE_NE4C1", + "NE6END1" + ], + [ + "INT_INTERFACE_NE4C2", + "NE6END2" + ], + [ + "INT_INTERFACE_NE4C3", + "NE6END3" + ], + [ + "INT_INTERFACE_NW2A0", + "NW2A0" + ], + [ + "INT_INTERFACE_NW2A1", + "NW2A1" + ], + [ + "INT_INTERFACE_NW2A2", + "NW2A2" + ], + [ + "INT_INTERFACE_NW2A3", + "NW2A3" + ], + [ + "INT_INTERFACE_NW4A0", + "NW6BEG0" + ], + [ + "INT_INTERFACE_NW4A1", + "NW6BEG1" + ], + [ + "INT_INTERFACE_NW4A2", + "NW6BEG2" + ], + [ + "INT_INTERFACE_NW4A3", + "NW6BEG3" + ], + [ + "INT_INTERFACE_NW4END0", + "NW6E0" + ], + [ + "INT_INTERFACE_NW4END1", + "NW6E1" + ], + [ + "INT_INTERFACE_NW4END2", + "NW6E2" + ], + [ + "INT_INTERFACE_NW4END3", + "NW6E3" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_PHASER_TO_IO_ICLK" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_PHASER_TO_IO_ICLKDIV" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_PHASER_TO_IO_OCLK" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_PHASER_TO_IO_OCLK1X_90" + ], + [ + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_PHASER_TO_IO_OCLKDIV" + ], + [ + "INT_INTERFACE_SE2A0", + "SE2END0" + ], + [ + "INT_INTERFACE_SE2A1", + "SE2END1" + ], + [ + "INT_INTERFACE_SE2A2", + "SE2END2" + ], + [ + "INT_INTERFACE_SE2A3", + "SE2END3" + ], + [ + "INT_INTERFACE_SE4BEG0", + "SE6A0" + ], + [ + "INT_INTERFACE_SE4BEG1", + "SE6A1" + ], + [ + "INT_INTERFACE_SE4BEG2", + "SE6A2" + ], + [ + "INT_INTERFACE_SE4BEG3", + "SE6A3" + ], + [ + "INT_INTERFACE_SE4C0", + "SE6END0" + ], + [ + "INT_INTERFACE_SE4C1", + "SE6END1" + ], + [ + "INT_INTERFACE_SE4C2", + "SE6END2" + ], + [ + "INT_INTERFACE_SE4C3", + "SE6END3" + ], + [ + "INT_INTERFACE_SW2A0", + "SW2A0" + ], + [ + "INT_INTERFACE_SW2A1", + "SW2A1" + ], + [ + "INT_INTERFACE_SW2A2", + "SW2A2" + ], + [ + "INT_INTERFACE_SW2A3", + "SW2A3" + ], + [ + "INT_INTERFACE_SW4A0", + "SW6BEG0" + ], + [ + "INT_INTERFACE_SW4A1", + "SW6BEG1" + ], + [ + "INT_INTERFACE_SW4A2", + "SW6BEG2" + ], + [ + "INT_INTERFACE_SW4A3", + "SW6BEG3" + ], + [ + "INT_INTERFACE_SW4END0", + "SW6E0" + ], + [ + "INT_INTERFACE_SW4END1", + "SW6E1" + ], + [ + "INT_INTERFACE_SW4END2", + "SW6E2" + ], + [ + "INT_INTERFACE_SW4END3", + "SW6E3" + ], + [ + "INT_INTERFACE_WL1END0", + "WL1BEG0" + ], + [ + "INT_INTERFACE_WL1END1", + "WL1BEG1" + ], + [ + "INT_INTERFACE_WL1END2", + "WL1BEG2" + ], + [ + "INT_INTERFACE_WL1END3", + "WL1BEG3" + ], + [ + "INT_INTERFACE_WR1END0", + "WR1BEG0" + ], + [ + "INT_INTERFACE_WR1END1", + "WR1BEG1" + ], + [ + "INT_INTERFACE_WR1END2", + "WR1BEG2" + ], + [ + "INT_INTERFACE_WR1END3", + "WR1BEG3" + ], + [ + "INT_INTERFACE_WW2A0", + "WW2BEG0" + ], + [ + "INT_INTERFACE_WW2A1", + "WW2BEG1" + ], + [ + "INT_INTERFACE_WW2A2", + "WW2BEG2" + ], + [ + "INT_INTERFACE_WW2A3", + "WW2BEG3" + ], + [ + "INT_INTERFACE_WW2END0", + "WW2A0" + ], + [ + "INT_INTERFACE_WW2END1", + "WW2A1" + ], + [ + "INT_INTERFACE_WW2END2", + "WW2A2" + ], + [ + "INT_INTERFACE_WW2END3", + "WW2A3" + ], + [ + "INT_INTERFACE_WW4A0", + "WW4BEG0" + ], + [ + "INT_INTERFACE_WW4A1", + "WW4BEG1" + ], + [ + "INT_INTERFACE_WW4A2", + "WW4BEG2" + ], + [ + "INT_INTERFACE_WW4A3", + "WW4BEG3" + ], + [ + "INT_INTERFACE_WW4B0", + "WW4A0" + ], + [ + "INT_INTERFACE_WW4B1", + "WW4A1" + ], + [ + "INT_INTERFACE_WW4B2", + "WW4A2" + ], + [ + "INT_INTERFACE_WW4B3", + "WW4A3" + ], + [ + "INT_INTERFACE_WW4C0", + "WW4B0" + ], + [ + "INT_INTERFACE_WW4C1", + "WW4B1" + ], + [ + "INT_INTERFACE_WW4C2", + "WW4B2" + ], + [ + "INT_INTERFACE_WW4C3", + "WW4B3" + ], + [ + "INT_INTERFACE_WW4END0", + "WW4C0" + ], + [ + "INT_INTERFACE_WW4END1", + "WW4C1" + ], + [ + "INT_INTERFACE_WW4END2", + "WW4C2" + ], + [ + "INT_INTERFACE_WW4END3", + "WW4C3" + ], + [ + "L_INT_INTER_DQS_IOTOPHASER", + "INT_DQS_IOTOPHASER" ] ] }, @@ -454613,1913 +389229,5053 @@ 0 ], "tile_types": [ - "BRAM_L", - "VBRK" + "INT_INTERFACE_L", + "VFRAME" ], "wire_pairs": [ [ - "BRAM_NW4END0_0", - "VBRK_NW4END0" + "INT_INTERFACE_BYP0", + "VFRAME_BYP0" ], [ - "BRAM_EE4BEG3_0", - "VBRK_EE4BEG3" + "INT_INTERFACE_BYP1", + "VFRAME_BYP1" ], [ - "BRAM_NE4C3_0", - "VBRK_NE4C3" + "INT_INTERFACE_BYP2", + "VFRAME_BYP2" ], [ - "BRAM_EE4A1_0", - "VBRK_EE4A1" + "INT_INTERFACE_BYP3", + "VFRAME_BYP3" ], [ - "BRAM_NW4A0_0", - "VBRK_NW4A0" + "INT_INTERFACE_BYP4", + "VFRAME_BYP4" ], [ - "BRAM_EE4C1_0", - "VBRK_EE4C1" + "INT_INTERFACE_BYP5", + "VFRAME_BYP5" ], [ - "BRAM_ER1BEG3_0", - "VBRK_ER1BEG3" + "INT_INTERFACE_BYP6", + "VFRAME_BYP6" ], [ - "BRAM_LH3_0", - "VBRK_LH3" + "INT_INTERFACE_BYP7", + "VFRAME_BYP7" ], [ - "BRAM_SE2A1_0", - "VBRK_SE2A1" + "INT_INTERFACE_CLK0", + "VFRAME_CLK0" ], [ - "BRAM_EE4BEG0_0", - "VBRK_EE4BEG0" + "INT_INTERFACE_CLK1", + "VFRAME_CLK1" ], [ - "BRAM_NW4END2_0", - "VBRK_NW4END2" + "INT_INTERFACE_CTRL0", + "VFRAME_CTRL0" ], [ - "BRAM_WW4B1_0", - "VBRK_WW4B1" + "INT_INTERFACE_CTRL1", + "VFRAME_CTRL1" ], [ - "BRAM_EE4B0_0", - "VBRK_EE4B0" + "INT_INTERFACE_EE2A0", + "VFRAME_EE2A0" ], [ - "BRAM_NW2A3_0", - "VBRK_NW2A3" + "INT_INTERFACE_EE2A1", + "VFRAME_EE2A1" ], [ - "BRAM_WW4A3_0", - "VBRK_WW4A3" + "INT_INTERFACE_EE2A2", + "VFRAME_EE2A2" ], [ - "BRAM_LH6_0", - "VBRK_LH6" + "INT_INTERFACE_EE2A3", + "VFRAME_EE2A3" ], [ - "BRAM_WL1END0_0", - "VBRK_WL1END0" + "INT_INTERFACE_EE2BEG0", + "VFRAME_EE2BEG0" ], [ - "BRAM_WR1END1_0", - "VBRK_WR1END1" + "INT_INTERFACE_EE2BEG1", + "VFRAME_EE2BEG1" ], [ - "BRAM_WW4END0_0", - "VBRK_WW4END0" + "INT_INTERFACE_EE2BEG2", + "VFRAME_EE2BEG2" ], [ - "BRAM_NE4C0_0", - "VBRK_NE4C0" + "INT_INTERFACE_EE2BEG3", + "VFRAME_EE2BEG3" ], [ - "BRAM_EE4B3_0", - "VBRK_EE4B3" + "INT_INTERFACE_EE4A0", + "VFRAME_EE4A0" ], [ - "BRAM_MONITOR_P_0", - "VBRK_MONITOR_P" + "INT_INTERFACE_EE4A1", + "VFRAME_EE4A1" ], [ - "BRAM_NE4C2_0", - "VBRK_NE4C2" + "INT_INTERFACE_EE4A2", + "VFRAME_EE4A2" ], [ - "BRAM_WW4END2_0", - "VBRK_WW4END2" + "INT_INTERFACE_EE4A3", + "VFRAME_EE4A3" ], [ - "BRAM_SW4A1_0", - "VBRK_SW4A1" + "INT_INTERFACE_EE4B0", + "VFRAME_EE4B0" ], [ - "BRAM_WW4A0_0", - "VBRK_WW4A0" + "INT_INTERFACE_EE4B1", + "VFRAME_EE4B1" ], [ - "BRAM_EE4B1_0", - "VBRK_EE4B1" + "INT_INTERFACE_EE4B2", + "VFRAME_EE4B2" ], [ - "BRAM_SE2A2_0", - "VBRK_SE2A2" + "INT_INTERFACE_EE4B3", + "VFRAME_EE4B3" ], [ - "BRAM_NE4C1_0", - "VBRK_NE4C1" + "INT_INTERFACE_EE4BEG0", + "VFRAME_EE4BEG0" ], [ - "BRAM_SE4BEG1_0", - "VBRK_SE4BEG1" + "INT_INTERFACE_EE4BEG1", + "VFRAME_EE4BEG1" ], [ - "BRAM_EE2A2_0", - "VBRK_EE2A2" + "INT_INTERFACE_EE4BEG2", + "VFRAME_EE4BEG2" ], [ - "BRAM_SW4END1_0", - "VBRK_SW4END1" + "INT_INTERFACE_EE4BEG3", + "VFRAME_EE4BEG3" ], [ - "BRAM_SW2A3_0", - "VBRK_SW2A3" + "INT_INTERFACE_EE4C0", + "VFRAME_EE4C0" ], [ - "BRAM_WR1END3_0", - "VBRK_WR1END3" + "INT_INTERFACE_EE4C1", + "VFRAME_EE4C1" ], [ - "BRAM_SE2A3_0", - "VBRK_SE2A3" + "INT_INTERFACE_EE4C2", + "VFRAME_EE4C2" ], [ - "BRAM_WW4C0_0", - "VBRK_WW4C0" + "INT_INTERFACE_EE4C3", + "VFRAME_EE4C3" ], [ - "BRAM_WW2END2_0", - "VBRK_WW2END2" + "INT_INTERFACE_EL1BEG0", + "VFRAME_EL1BEG0" ], [ - "BRAM_SE4C2_0", - "VBRK_SE4C2" + "INT_INTERFACE_EL1BEG1", + "VFRAME_EL1BEG1" ], [ - "BRAM_ER1BEG0_0", - "VBRK_ER1BEG0" + "INT_INTERFACE_EL1BEG2", + "VFRAME_EL1BEG2" ], [ - "BRAM_WW4END1_0", - "VBRK_WW4END1" + "INT_INTERFACE_EL1BEG3", + "VFRAME_EL1BEG3" ], [ - "BRAM_EE4C2_0", - "VBRK_EE4C2" + "INT_INTERFACE_ER1BEG0", + "VFRAME_ER1BEG0" ], [ - "BRAM_EL1BEG1_0", - "VBRK_EL1BEG1" + "INT_INTERFACE_ER1BEG1", + "VFRAME_ER1BEG1" ], [ - "BRAM_EE4BEG1_0", - "VBRK_EE4BEG1" + "INT_INTERFACE_ER1BEG2", + "VFRAME_ER1BEG2" ], [ - "BRAM_SE4C3_0", - "VBRK_SE4C3" + "INT_INTERFACE_ER1BEG3", + "VFRAME_ER1BEG3" ], [ - "BRAM_SW2A1_0", - "VBRK_SW2A1" + "INT_INTERFACE_FAN0", + "VFRAME_FAN0" ], [ - "BRAM_EE2A0_0", - "VBRK_EE2A0" + "INT_INTERFACE_FAN1", + "VFRAME_FAN1" ], [ - "BRAM_LH1_0", - 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"VBRK_WW4END3" + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "VFRAME_LOGIC_OUTS_B14" ], [ - "BRAM_NW4END3_0", - "VBRK_NW4END3" + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "VFRAME_LOGIC_OUTS_B15" ], [ - "BRAM_SE2A0_0", - "VBRK_SE2A0" + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "VFRAME_LOGIC_OUTS_B16" ], [ - "BRAM_WW4C3_0", - "VBRK_WW4C3" + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "VFRAME_LOGIC_OUTS_B17" ], [ - "BRAM_WW2A2_0", - "VBRK_WW2A2" + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "VFRAME_LOGIC_OUTS_B18" ], [ - "BRAM_NW2A0_0", - "VBRK_NW2A0" + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "VFRAME_LOGIC_OUTS_B19" ], [ - "BRAM_NW4A2_0", - "VBRK_NW4A2" + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "VFRAME_LOGIC_OUTS_B20" ], [ - "BRAM_SW4END0_0", - "VBRK_SW4END0" - ] - ] - }, - { - "grid_deltas": [ - 1, - -3 - ], - "tile_types": [ - "DSP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "DSP_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "DSP_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "DSP_LH2_3", - "VBRK_LH2" - ], - [ - "DSP_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "DSP_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "DSP_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "DSP_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "DSP_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "DSP_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "DSP_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "DSP_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "DSP_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "DSP_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "DSP_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "DSP_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "DSP_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "DSP_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "DSP_LH8_3", - "VBRK_LH8" - ], - [ - "DSP_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "DSP_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "DSP_MONITOR_P_3", - "VBRK_MONITOR_P" - ], - [ - "DSP_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "DSP_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "DSP_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "DSP_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "DSP_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "DSP_NW2A1_3", - "VBRK_NW2A1" - ], - [ - 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+ "INT_INTERFACE_NE4C3", + "VFRAME_NE4C3" ], [ - "DSP_WW4B2_3", - "VBRK_WW4B2" + "INT_INTERFACE_NW2A0", + "VFRAME_NW2A0" ], [ - "DSP_NW2A0_3", - "VBRK_NW2A0" + "INT_INTERFACE_NW2A1", + "VFRAME_NW2A1" ], [ - "DSP_SW4END2_3", - "VBRK_SW4END2" + "INT_INTERFACE_NW2A2", + "VFRAME_NW2A2" ], [ - "DSP_LH5_3", - "VBRK_LH5" + "INT_INTERFACE_NW2A3", + "VFRAME_NW2A3" ], [ - "DSP_NW2A3_3", - "VBRK_NW2A3" + "INT_INTERFACE_NW4A0", + "VFRAME_NW4A0" ], [ - "DSP_WW4C2_3", - "VBRK_WW4C2" + "INT_INTERFACE_NW4A1", + "VFRAME_NW4A1" ], [ - "DSP_SW4A2_3", - "VBRK_SW4A2" + "INT_INTERFACE_NW4A2", + "VFRAME_NW4A2" ], [ - "DSP_SW4END1_3", - "VBRK_SW4END1" + "INT_INTERFACE_NW4A3", + "VFRAME_NW4A3" ], [ - "DSP_EE4B0_3", - "VBRK_EE4B0" + "INT_INTERFACE_NW4END0", + "VFRAME_NW4END0" ], [ - "DSP_WW4C0_3", - "VBRK_WW4C0" + "INT_INTERFACE_NW4END1", + "VFRAME_NW4END1" ], [ - "DSP_WW4B0_3", - "VBRK_WW4B0" + "INT_INTERFACE_NW4END2", + "VFRAME_NW4END2" ], [ - "DSP_EE2A0_3", - "VBRK_EE2A0" + "INT_INTERFACE_NW4END3", + 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"PCIE_INT_INTERFACE_IMUX_L44" + ], + [ + "IMUX_L45", + "PCIE_INT_INTERFACE_IMUX_L45" + ], + [ + "IMUX_L46", + "PCIE_INT_INTERFACE_IMUX_L46" + ], + [ + "IMUX_L47", + "PCIE_INT_INTERFACE_IMUX_L47" + ], + [ + "LH0", + "INT_INTERFACE_LH1" + ], + [ + "LH1", + "INT_INTERFACE_LH2" + ], + [ + "LH2", + "INT_INTERFACE_LH3" + ], + [ + "LH3", + "INT_INTERFACE_LH4" + ], + [ + "LH4", + "INT_INTERFACE_LH5" + ], + [ + "LH5", + "INT_INTERFACE_LH6" + ], + [ + "LH6", + "INT_INTERFACE_LH7" + ], + [ + "LH7", + "INT_INTERFACE_LH8" + ], + [ + "LH8", + "INT_INTERFACE_LH9" + ], + [ + "LH9", + "INT_INTERFACE_LH10" + ], + [ + "LH10", + "INT_INTERFACE_LH11" + ], + [ + "LH11", + "INT_INTERFACE_LH12" + ], + [ + "LOGIC_OUTS_L0", + "INT_INTERFACE_LOGIC_OUTS_L0" + ], + [ + "LOGIC_OUTS_L1", + "INT_INTERFACE_LOGIC_OUTS_L1" + ], + [ + "LOGIC_OUTS_L2", + "INT_INTERFACE_LOGIC_OUTS_L2" + ], + [ + "LOGIC_OUTS_L3", + "INT_INTERFACE_LOGIC_OUTS_L3" + ], + [ + "LOGIC_OUTS_L4", + "INT_INTERFACE_LOGIC_OUTS_L4" + ], + [ + "LOGIC_OUTS_L5", + "INT_INTERFACE_LOGIC_OUTS_L5" + ], + [ + "LOGIC_OUTS_L6", + "INT_INTERFACE_LOGIC_OUTS_L6" + ], + [ + "LOGIC_OUTS_L7", + "INT_INTERFACE_LOGIC_OUTS_L7" + ], + [ + "LOGIC_OUTS_L8", + "INT_INTERFACE_LOGIC_OUTS_L8" + ], + [ + "LOGIC_OUTS_L9", + "INT_INTERFACE_LOGIC_OUTS_L9" + ], + [ + "LOGIC_OUTS_L10", + "INT_INTERFACE_LOGIC_OUTS_L10" + ], + [ + "LOGIC_OUTS_L11", + "INT_INTERFACE_LOGIC_OUTS_L11" + ], + [ + "LOGIC_OUTS_L12", + "INT_INTERFACE_LOGIC_OUTS_L12" + ], + [ + "LOGIC_OUTS_L13", + "INT_INTERFACE_LOGIC_OUTS_L13" + ], + [ + "LOGIC_OUTS_L14", + "INT_INTERFACE_LOGIC_OUTS_L14" + ], + [ + "LOGIC_OUTS_L15", + "INT_INTERFACE_LOGIC_OUTS_L15" + ], + [ + "LOGIC_OUTS_L16", + "INT_INTERFACE_LOGIC_OUTS_L16" + ], + [ + "LOGIC_OUTS_L17", + "INT_INTERFACE_LOGIC_OUTS_L17" + ], + [ + "LOGIC_OUTS_L18", + "INT_INTERFACE_LOGIC_OUTS_L18" + ], + [ + "LOGIC_OUTS_L19", + "INT_INTERFACE_LOGIC_OUTS_L19" + ], + [ + "LOGIC_OUTS_L20", + "INT_INTERFACE_LOGIC_OUTS_L20" + ], + [ + "LOGIC_OUTS_L21", + "INT_INTERFACE_LOGIC_OUTS_L21" + ], + [ + "LOGIC_OUTS_L22", + "INT_INTERFACE_LOGIC_OUTS_L22" + ], + [ + "LOGIC_OUTS_L23", + "INT_INTERFACE_LOGIC_OUTS_L23" + ], + [ + "MONITOR_N", + "INT_INTERFACE_MONITOR_N" + ], + [ + "MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "NE2END0", + "INT_INTERFACE_NE2A0" + ], + [ + "NE2END1", + "INT_INTERFACE_NE2A1" + ], + [ + "NE2END2", + "INT_INTERFACE_NE2A2" + ], + [ + "NE2END3", + "INT_INTERFACE_NE2A3" + ], + [ + "NE6A0", + "INT_INTERFACE_NE4BEG0" + ], + [ + "NE6A1", + "INT_INTERFACE_NE4BEG1" + ], + [ + "NE6A2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "NE6A3", + "INT_INTERFACE_NE4BEG3" + ], + [ + "NE6END0", + "INT_INTERFACE_NE4C0" + ], + [ + "NE6END1", + "INT_INTERFACE_NE4C1" + ], + [ + "NE6END2", + "INT_INTERFACE_NE4C2" + ], + [ + "NE6END3", + "INT_INTERFACE_NE4C3" + ], + [ + "NW2A0", + "INT_INTERFACE_NW2A0" + ], + [ + "NW2A1", + "INT_INTERFACE_NW2A1" + ], + [ + "NW2A2", + "INT_INTERFACE_NW2A2" + ], + [ + "NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "NW6BEG0", + "INT_INTERFACE_NW4A0" + ], + [ + "NW6BEG1", + "INT_INTERFACE_NW4A1" + ], + [ + "NW6BEG2", + "INT_INTERFACE_NW4A2" + ], + [ + "NW6BEG3", + "INT_INTERFACE_NW4A3" + ], + [ + "NW6E0", + "INT_INTERFACE_NW4END0" + ], + [ + "NW6E1", + "INT_INTERFACE_NW4END1" + ], + [ + "NW6E2", + "INT_INTERFACE_NW4END2" + ], + [ + "NW6E3", + "INT_INTERFACE_NW4END3" + ], + [ + "SE2END0", + "INT_INTERFACE_SE2A0" + ], + [ + "SE2END1", + "INT_INTERFACE_SE2A1" + ], + [ + "SE2END2", + "INT_INTERFACE_SE2A2" + ], + [ + "SE2END3", + "INT_INTERFACE_SE2A3" + ], + [ + "SE6A0", + "INT_INTERFACE_SE4BEG0" + ], + [ + "SE6A1", + "INT_INTERFACE_SE4BEG1" + ], + [ + "SE6A2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "SE6A3", + "INT_INTERFACE_SE4BEG3" + ], + [ + "SE6END0", + "INT_INTERFACE_SE4C0" + ], + [ + "SE6END1", + "INT_INTERFACE_SE4C1" + ], + [ + "SE6END2", + "INT_INTERFACE_SE4C2" + ], + [ + "SE6END3", + "INT_INTERFACE_SE4C3" + ], + [ + "SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "SW2A1", + "INT_INTERFACE_SW2A1" + ], + [ + "SW2A2", + "INT_INTERFACE_SW2A2" + ], + [ + "SW2A3", + "INT_INTERFACE_SW2A3" + ], + [ + "SW6BEG0", + "INT_INTERFACE_SW4A0" + ], + [ + "SW6BEG1", + "INT_INTERFACE_SW4A1" + ], + [ + "SW6BEG2", + "INT_INTERFACE_SW4A2" + ], + [ + "SW6BEG3", + "INT_INTERFACE_SW4A3" + ], + [ + "SW6E0", + "INT_INTERFACE_SW4END0" + ], + [ + "SW6E1", + "INT_INTERFACE_SW4END1" + ], + [ + "SW6E2", + "INT_INTERFACE_SW4END2" + ], + [ + "SW6E3", + "INT_INTERFACE_SW4END3" + ], + [ + "WL1BEG0", + "INT_INTERFACE_WL1END0" + ], + [ + "WL1BEG1", + "INT_INTERFACE_WL1END1" + ], + [ + "WL1BEG2", + "INT_INTERFACE_WL1END2" + ], + [ + "WL1BEG3", + "INT_INTERFACE_WL1END3" + ], + [ + "WR1BEG0", + "INT_INTERFACE_WR1END0" + ], + [ + "WR1BEG1", + "INT_INTERFACE_WR1END1" + ], + [ + "WR1BEG2", + "INT_INTERFACE_WR1END2" + ], + [ + "WR1BEG3", + "INT_INTERFACE_WR1END3" + ], + [ + "WW2A0", + "INT_INTERFACE_WW2END0" + ], + [ + "WW2A1", + "INT_INTERFACE_WW2END1" + ], + [ + "WW2A2", + "INT_INTERFACE_WW2END2" + ], + [ + "WW2A3", + "INT_INTERFACE_WW2END3" + ], + [ + "WW2BEG0", + "INT_INTERFACE_WW2A0" + ], + [ + "WW2BEG1", + "INT_INTERFACE_WW2A1" + ], + [ + "WW2BEG2", + "INT_INTERFACE_WW2A2" + ], + [ + "WW2BEG3", + "INT_INTERFACE_WW2A3" + ], + [ + "WW4A0", + "INT_INTERFACE_WW4B0" + ], + [ + "WW4A1", + "INT_INTERFACE_WW4B1" + ], + [ + "WW4A2", + "INT_INTERFACE_WW4B2" + ], + [ + "WW4A3", + "INT_INTERFACE_WW4B3" + ], + [ + "WW4B0", + "INT_INTERFACE_WW4C0" + ], + [ + "WW4B1", + "INT_INTERFACE_WW4C1" + ], + [ + "WW4B2", + "INT_INTERFACE_WW4C2" + ], + [ + "WW4B3", + "INT_INTERFACE_WW4C3" + ], + [ + "WW4BEG0", + "INT_INTERFACE_WW4A0" + ], + [ + "WW4BEG1", + "INT_INTERFACE_WW4A1" + ], + [ + "WW4BEG2", + "INT_INTERFACE_WW4A2" + ], + [ + "WW4BEG3", + "INT_INTERFACE_WW4A3" + ], + [ + "WW4C0", + "INT_INTERFACE_WW4END0" + ], + [ + "WW4C1", + "INT_INTERFACE_WW4END1" + ], + [ + "WW4C2", + "INT_INTERFACE_WW4END2" + ], + [ + "WW4C3", + "INT_INTERFACE_WW4END3" ] ] }, @@ -456537,358 +394293,526 @@ "BYP_BOUNCE2", "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6" ], - [ - "SW2A3", - "T_TERM_UTURN_INT_SW2A3" - ], - [ - "SS6B2", - "T_TERM_UTURN_INT_SS6B2" - ], - [ - "SS6A0", - "T_TERM_UTURN_INT_SS6A0" - ], - [ - "LVB_L10", - "T_TERM_UTURN_INT_LVB_L1" - ], - [ - "SS6C2", - "T_TERM_UTURN_INT_SS6C2" - ], - [ - "SE2A3", - "T_TERM_UTURN_INT_SE2A3" - ], - [ - "FAN_BOUNCE_S3_2", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2" - ], - [ - "NE6B2", - "T_TERM_UTURN_INT_SE6C1" - ], - [ - "SE6C0", - "T_TERM_UTURN_INT_SE6C0" - ], - [ - "SS2A0", - "T_TERM_UTURN_INT_SS2A0" - ], - [ - "LVB_L3", - "T_TERM_UTURN_INT_LVB_L3" - ], - [ - "NE6D1", - "T_TERM_UTURN_INT_SE6E2" - ], - [ - "NE6B3", - "T_TERM_UTURN_INT_SE6C0" - ], - [ - "LV_L13", - "T_TERM_UTURN_INT_LV_L4" - ], - [ - "SW6C0", - "T_TERM_UTURN_INT_SW6C0" - ], - [ - "LV_L11", - "T_TERM_UTURN_INT_LV_L6" - ], - [ - "SS6END3", - "T_TERM_UTURN_INT_SS6END3" - ], [ "BYP_BOUNCE3", "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2" ], - [ - "SS6END1", - "T_TERM_UTURN_INT_SS6END1" - ], - [ - "SS6B0", - "T_TERM_UTURN_INT_SS6B0" - ], - [ - "EL1BEG3", - "T_TERM_UTURN_INT_ER1BEG_S0" - ], - [ - "SR1END1", - "T_TERM_UTURN_INT_SR1END1" - ], - [ - "NN6C3", - "T_TERM_UTURN_INT_SS6D0" - ], - [ - "LV_L8", - "T_TERM_UTURN_INT_LV_L9" - ], - [ - "NE6A1", - "T_TERM_UTURN_INT_SE6B2" - ], - [ - "NN6BEG2", - "T_TERM_UTURN_INT_SS6A1" - ], - [ - "NE6B1", - "T_TERM_UTURN_INT_SE6C2" - ], - [ - "NL1BEG2", - "T_TERM_UTURN_INT_SR1END1" - ], - [ - "LVB_L6", - "T_TERM_UTURN_INT_LVB_L5" - ], - [ - "NN2A1", - "T_TERM_UTURN_INT_SS2END2" - ], - [ - "NE6B0", - "T_TERM_UTURN_INT_SE6C3" - ], - [ - "NN6A3", - "T_TERM_UTURN_INT_SS6B0" - ], - [ - "FAN_BOUNCE_S3_4", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4" - ], - [ - "WL1END3", - "T_TERM_UTURN_INT_WR1END_S1_0" - ], - [ - "LVB_L9", - "T_TERM_UTURN_INT_LVB_L2" - ], - [ - "LVB_L2", - "T_TERM_UTURN_INT_LVB_L2" - ], - [ - "LV_L4", - "T_TERM_UTURN_INT_LV_L4" - ], - [ - "SE2A2", - "T_TERM_UTURN_INT_SE2A2" - ], - [ - "NW6C1", - "T_TERM_UTURN_INT_SW6D2" - ], - [ - "SS6D1", - "T_TERM_UTURN_INT_SS6D1" - ], - [ - "NN6B0", - "T_TERM_UTURN_INT_SS6C3" - ], - [ - "SW2A1", - "T_TERM_UTURN_INT_SW2A1" - ], - [ - "NE6C1", - "T_TERM_UTURN_INT_SE6D2" - ], - [ - "WR1END_S1_0", - "T_TERM_UTURN_INT_WR1END_S1_0" - ], - [ - "NN2BEG2", - "T_TERM_UTURN_INT_SS2A1" - ], - [ - "SE6E0", - "T_TERM_UTURN_INT_SE6E0" - ], - [ - "BYP_BOUNCE7", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0" - ], - [ - "NN2A3", - "T_TERM_UTURN_INT_SS2END0" - ], - [ - "NN6B3", - "T_TERM_UTURN_INT_SS6C0" - ], - [ - "NR1BEG2", - "T_TERM_UTURN_INT_SL1END1" - ], - [ - "NN6C2", - "T_TERM_UTURN_INT_SS6D1" - ], - [ - "LV_L16", - "T_TERM_UTURN_INT_LV_L16" - ], - [ - "LVB_L8", - "T_TERM_UTURN_INT_LVB_L3" - ], - [ - "LV_L12", - "T_TERM_UTURN_INT_LV_L5" - ], - [ - "NW2BEG1", - "T_TERM_UTURN_INT_SW2A2" - ], - [ - "SS2A3", - "T_TERM_UTURN_INT_SS2A3" - ], - [ - "SS2END0", - "T_TERM_UTURN_INT_SS2END0" - ], - [ - "LV_L5", - "T_TERM_UTURN_INT_LV_L5" - ], - [ - "NE2BEG0", - "T_TERM_UTURN_INT_SE2A3" - ], - [ - "SS6C3", - "T_TERM_UTURN_INT_SS6C3" - ], - [ - "LV_L3", - "T_TERM_UTURN_INT_LV_L3" - ], - [ - "SS6D2", - "T_TERM_UTURN_INT_SS6D2" - ], - [ - "SW6D3", - "T_TERM_UTURN_INT_SW6D3" - ], - [ - "NE6D0", - "T_TERM_UTURN_INT_SE6E3" - ], - [ - "NN6A2", - "T_TERM_UTURN_INT_SS6B1" - ], - [ - "LV_L10", - "T_TERM_UTURN_INT_LV_L7" - ], - [ - "SL1END1", - "T_TERM_UTURN_INT_SL1END1" - ], - [ - "NN6B1", - "T_TERM_UTURN_INT_SS6C2" - ], - [ - "NW6B3", - "T_TERM_UTURN_INT_SW6C0" - ], - [ - "NN6A0", - "T_TERM_UTURN_INT_SS6B3" - ], - [ - "SE6E2", - "T_TERM_UTURN_INT_SE6E2" - ], - [ - "SW2A0", - "T_TERM_UTURN_INT_SW2A0" - ], - [ - "NN6E1", - "T_TERM_UTURN_INT_SS6END2" - ], - [ - "LV_L14", - "T_TERM_UTURN_INT_LV_L3" - ], - [ - "NN2BEG1", - "T_TERM_UTURN_INT_SS2A2" - ], - [ - "SE6B3", - "T_TERM_UTURN_INT_SE6B3" - ], - [ - "NW6A1", - "T_TERM_UTURN_INT_SW6B2" - ], - [ - "SE6D0", - "T_TERM_UTURN_INT_SE6D0" - ], - [ - "LV_L6", - "T_TERM_UTURN_INT_LV_L6" - ], - [ - "NN6BEG1", - "T_TERM_UTURN_INT_SS6A2" - ], - [ - "NN6C1", - "T_TERM_UTURN_INT_SS6D2" - ], - [ - "SS6A2", - "T_TERM_UTURN_INT_SS6A2" - ], - [ - "SS6E3", - "T_TERM_UTURN_INT_SS6E3" - ], [ "BYP_BOUNCE6", "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4" ], + [ + "BYP_BOUNCE7", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0" + ], + [ + "EL1BEG3", + "T_TERM_UTURN_INT_ER1BEG_S0" + ], + [ + "EL1END_S3_0", + "T_TERM_UTURN_INT_ER1END3" + ], + [ + "ER1BEG_S0", + "T_TERM_UTURN_INT_ER1BEG_S0" + ], + [ + "ER1END3", + "T_TERM_UTURN_INT_ER1END3" + ], + [ + "FAN_BOUNCE_S3_0", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0" + ], + [ + "FAN_BOUNCE_S3_2", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2" + ], + [ + "FAN_BOUNCE_S3_4", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4" + ], + [ + "FAN_BOUNCE_S3_6", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6" + ], + [ + "LVB_L0", + "T_TERM_UTURN_INT_LVB_L0" + ], + [ + "LVB_L1", + "T_TERM_UTURN_INT_LVB_L1" + ], + [ + "LVB_L2", + "T_TERM_UTURN_INT_LVB_L2" + ], + [ + "LVB_L3", + "T_TERM_UTURN_INT_LVB_L3" + ], + [ + "LVB_L4", + "T_TERM_UTURN_INT_LVB_L4" + ], + [ + "LVB_L5", + "T_TERM_UTURN_INT_LVB_L5" + ], + [ + "LVB_L6", + "T_TERM_UTURN_INT_LVB_L5" + ], + [ + "LVB_L7", + "T_TERM_UTURN_INT_LVB_L4" + ], + [ + "LVB_L8", + "T_TERM_UTURN_INT_LVB_L3" + ], + [ + "LVB_L9", + "T_TERM_UTURN_INT_LVB_L2" + ], + [ + "LVB_L10", + "T_TERM_UTURN_INT_LVB_L1" + ], + [ + "LVB_L11", + "T_TERM_UTURN_INT_LVB_L0" + ], + [ + "LV_L0", + "T_TERM_UTURN_INT_LV_L17" + ], + [ + "LV_L1", + "T_TERM_UTURN_INT_LV_L16" + ], + [ + "LV_L2", + "T_TERM_UTURN_INT_LV_L2" + ], + [ + "LV_L3", + "T_TERM_UTURN_INT_LV_L3" + ], + [ + "LV_L4", + "T_TERM_UTURN_INT_LV_L4" + ], + [ + "LV_L5", + "T_TERM_UTURN_INT_LV_L5" + ], + [ + "LV_L6", + "T_TERM_UTURN_INT_LV_L6" + ], + [ + "LV_L7", + "T_TERM_UTURN_INT_LV_L7" + ], + [ + "LV_L8", + "T_TERM_UTURN_INT_LV_L9" + ], + [ + "LV_L9", + "T_TERM_UTURN_INT_LV_L9" + ], + [ + "LV_L10", + "T_TERM_UTURN_INT_LV_L7" + ], + [ + "LV_L11", + "T_TERM_UTURN_INT_LV_L6" + ], + [ + "LV_L12", + "T_TERM_UTURN_INT_LV_L5" + ], + [ + "LV_L13", + "T_TERM_UTURN_INT_LV_L4" + ], + [ + "LV_L14", + "T_TERM_UTURN_INT_LV_L3" + ], + [ + "LV_L15", + "T_TERM_UTURN_INT_LV_L2" + ], + [ + "LV_L16", + "T_TERM_UTURN_INT_LV_L16" + ], + [ + "LV_L17", + "T_TERM_UTURN_INT_LV_L17" + ], + [ + "NE2BEG0", + "T_TERM_UTURN_INT_SE2A3" + ], + [ + "NE2BEG1", + "T_TERM_UTURN_INT_SE2A2" + ], + [ + "NE2BEG2", + "T_TERM_UTURN_INT_SE2A1" + ], + [ + "NE2BEG3", + "T_TERM_UTURN_INT_SE2A0" + ], + [ + "NE6A0", + "T_TERM_UTURN_INT_SE6B3" + ], + [ + "NE6A1", + "T_TERM_UTURN_INT_SE6B2" + ], + [ + "NE6A2", + "T_TERM_UTURN_INT_SE6B1" + ], + [ + "NE6A3", + "T_TERM_UTURN_INT_SE6B0" + ], + [ + "NE6B0", + "T_TERM_UTURN_INT_SE6C3" + ], + [ + "NE6B1", + "T_TERM_UTURN_INT_SE6C2" + ], + [ + "NE6B2", + "T_TERM_UTURN_INT_SE6C1" + ], + [ + "NE6B3", + "T_TERM_UTURN_INT_SE6C0" + ], + [ + "NE6C0", + "T_TERM_UTURN_INT_SE6D3" + ], + [ + "NE6C1", + "T_TERM_UTURN_INT_SE6D2" + ], + [ + "NE6C2", + "T_TERM_UTURN_INT_SE6D1" + ], + [ + "NE6C3", + "T_TERM_UTURN_INT_SE6D0" + ], + [ + "NE6D0", + "T_TERM_UTURN_INT_SE6E3" + ], + [ + "NE6D1", + "T_TERM_UTURN_INT_SE6E2" + ], + [ + "NE6D2", + "T_TERM_UTURN_INT_SE6E1" + ], + [ + "NE6D3", + "T_TERM_UTURN_INT_SE6E0" + ], + [ + "NL1BEG0", + "T_TERM_UTURN_INT_SR1END3" + ], [ "NL1BEG1", "T_TERM_UTURN_INT_SR1END2" ], [ - "SS2A2", + "NL1BEG2", + "T_TERM_UTURN_INT_SR1END1" + ], + [ + "NN2A0", + "T_TERM_UTURN_INT_SS2END3" + ], + [ + "NN2A1", + "T_TERM_UTURN_INT_SS2END2" + ], + [ + "NN2A2", + "T_TERM_UTURN_INT_SS2END1" + ], + [ + "NN2A3", + "T_TERM_UTURN_INT_SS2END0" + ], + [ + "NN2BEG0", + "T_TERM_UTURN_INT_SS2A3" + ], + [ + "NN2BEG1", "T_TERM_UTURN_INT_SS2A2" ], [ - "SS6E0", - "T_TERM_UTURN_INT_SS6E0" + "NN2BEG2", + "T_TERM_UTURN_INT_SS2A1" + ], + [ + "NN2BEG3", + "T_TERM_UTURN_INT_SS2A0" + ], + [ + "NN6A0", + "T_TERM_UTURN_INT_SS6B3" + ], + [ + "NN6A1", + "T_TERM_UTURN_INT_SS6B2" + ], + [ + "NN6A2", + "T_TERM_UTURN_INT_SS6B1" + ], + [ + "NN6A3", + "T_TERM_UTURN_INT_SS6B0" + ], + [ + "NN6B0", + "T_TERM_UTURN_INT_SS6C3" + ], + [ + "NN6B1", + "T_TERM_UTURN_INT_SS6C2" + ], + [ + "NN6B2", + "T_TERM_UTURN_INT_SS6C1" + ], + [ + "NN6B3", + "T_TERM_UTURN_INT_SS6C0" ], [ "NN6BEG0", "T_TERM_UTURN_INT_SS6A3" ], + [ + "NN6BEG1", + "T_TERM_UTURN_INT_SS6A2" + ], + [ + "NN6BEG2", + "T_TERM_UTURN_INT_SS6A1" + ], + [ + "NN6BEG3", + "T_TERM_UTURN_INT_SS6A0" + ], + [ + "NN6C0", + "T_TERM_UTURN_INT_SS6D3" + ], + [ + "NN6C1", + "T_TERM_UTURN_INT_SS6D2" + ], + [ + "NN6C2", + "T_TERM_UTURN_INT_SS6D1" + ], + [ + "NN6C3", + "T_TERM_UTURN_INT_SS6D0" + ], + [ + "NN6D0", + "T_TERM_UTURN_INT_SS6E3" + ], + [ + "NN6D1", + "T_TERM_UTURN_INT_SS6E2" + ], + [ + "NN6D2", + "T_TERM_UTURN_INT_SS6E1" + ], + [ + "NN6D3", + "T_TERM_UTURN_INT_SS6E0" + ], + [ + "NN6E0", + "T_TERM_UTURN_INT_SS6END3" + ], + [ + "NN6E1", + "T_TERM_UTURN_INT_SS6END2" + ], + [ + "NN6E2", + "T_TERM_UTURN_INT_SS6END1" + ], + [ + "NN6E3", + "T_TERM_UTURN_INT_SS6END0" + ], + [ + "NR1BEG0", + "T_TERM_UTURN_INT_SL1END3" + ], + [ + "NR1BEG1", + "T_TERM_UTURN_INT_SL1END2" + ], + [ + "NR1BEG2", + "T_TERM_UTURN_INT_SL1END1" + ], + [ + "NR1BEG3", + "T_TERM_UTURN_INT_SL1END0" + ], + [ + "NW2BEG0", + "T_TERM_UTURN_INT_SW2A3" + ], + [ + "NW2BEG1", + "T_TERM_UTURN_INT_SW2A2" + ], + [ + "NW2BEG2", + "T_TERM_UTURN_INT_SW2A1" + ], + [ + "NW2BEG3", + "T_TERM_UTURN_INT_SW2A0" + ], + [ + "NW6A0", + "T_TERM_UTURN_INT_SW6B3" + ], + [ + "NW6A1", + "T_TERM_UTURN_INT_SW6B2" + ], + [ + "NW6A2", + "T_TERM_UTURN_INT_SW6B1" + ], + [ + "NW6A3", + "T_TERM_UTURN_INT_SW6B0" + ], + [ + "NW6B0", + "T_TERM_UTURN_INT_SW6C3" + ], + [ + "NW6B1", + "T_TERM_UTURN_INT_SW6C2" + ], + [ + "NW6B2", + "T_TERM_UTURN_INT_SW6C1" + ], + [ + "NW6B3", + "T_TERM_UTURN_INT_SW6C0" + ], + [ + "NW6C0", + "T_TERM_UTURN_INT_SW6D3" + ], + [ + "NW6C1", + "T_TERM_UTURN_INT_SW6D2" + ], + [ + "NW6C2", + "T_TERM_UTURN_INT_SW6D1" + ], + [ + "NW6C3", + "T_TERM_UTURN_INT_SW6D0" + ], + [ + "NW6D0", + "T_TERM_UTURN_INT_SW6E3" + ], + [ + "NW6D1", + "T_TERM_UTURN_INT_SW6E2" + ], + [ + "NW6D2", + "T_TERM_UTURN_INT_SW6E1" + ], + [ + "NW6D3", + "T_TERM_UTURN_INT_SW6E0" + ], + [ + "SE2A0", + "T_TERM_UTURN_INT_SE2A0" + ], + [ + "SE2A1", + "T_TERM_UTURN_INT_SE2A1" + ], + [ + "SE2A2", + "T_TERM_UTURN_INT_SE2A2" + ], + [ + "SE2A3", + "T_TERM_UTURN_INT_SE2A3" + ], + [ + "SE6B0", + "T_TERM_UTURN_INT_SE6B0" + ], + [ + "SE6B1", + "T_TERM_UTURN_INT_SE6B1" + ], + [ + "SE6B2", + "T_TERM_UTURN_INT_SE6B2" + ], + [ + "SE6B3", + "T_TERM_UTURN_INT_SE6B3" + ], + [ + "SE6C0", + "T_TERM_UTURN_INT_SE6C0" + ], + [ + "SE6C1", + "T_TERM_UTURN_INT_SE6C1" + ], [ "SE6C2", "T_TERM_UTURN_INT_SE6C2" @@ -456898,165 +394822,209 @@ "T_TERM_UTURN_INT_SE6C3" ], [ - "LVB_L5", - "T_TERM_UTURN_INT_LVB_L5" + "SE6D0", + "T_TERM_UTURN_INT_SE6D0" ], [ - "SW2A2", - "T_TERM_UTURN_INT_SW2A2" + "SE6D1", + "T_TERM_UTURN_INT_SE6D1" ], [ - "LV_L0", - "T_TERM_UTURN_INT_LV_L17" - ], - [ - "NN6B2", - "T_TERM_UTURN_INT_SS6C1" - ], - [ - "NE6D3", - "T_TERM_UTURN_INT_SE6E0" - ], - [ - "SS6D0", - "T_TERM_UTURN_INT_SS6D0" - ], - [ - "LVB_L0", - "T_TERM_UTURN_INT_LVB_L0" - ], - [ - "SS2A1", - "T_TERM_UTURN_INT_SS2A1" - ], - [ - "LV_L2", - "T_TERM_UTURN_INT_LV_L2" - ], - [ - "SR1END3", - "T_TERM_UTURN_INT_SR1END3" - ], - [ - "NR1BEG1", - "T_TERM_UTURN_INT_SL1END2" - ], - [ - "LVB_L11", - "T_TERM_UTURN_INT_LVB_L0" - ], - [ - "NN2A0", - "T_TERM_UTURN_INT_SS2END3" - ], - [ - "WR1BEG_S0", - "T_TERM_UTURN_INT_WR1BEG_S0" - ], - [ - "NN6D1", - "T_TERM_UTURN_INT_SS6E2" - ], - [ - "NW6C2", - "T_TERM_UTURN_INT_SW6D1" + "SE6D2", + "T_TERM_UTURN_INT_SE6D2" ], [ "SE6D3", "T_TERM_UTURN_INT_SE6D3" ], [ - "LV_L1", - "T_TERM_UTURN_INT_LV_L16" + "SE6E0", + "T_TERM_UTURN_INT_SE6E0" ], [ - "NE2BEG2", - "T_TERM_UTURN_INT_SE2A1" + "SE6E1", + "T_TERM_UTURN_INT_SE6E1" ], [ - "SS2END3", - "T_TERM_UTURN_INT_SS2END3" + "SE6E2", + "T_TERM_UTURN_INT_SE6E2" ], [ - "NW6A3", - "T_TERM_UTURN_INT_SW6B0" + "SE6E3", + "T_TERM_UTURN_INT_SE6E3" + ], + [ + "SL1END0", + "T_TERM_UTURN_INT_SL1END0" + ], + [ + "SL1END1", + "T_TERM_UTURN_INT_SL1END1" ], [ "SL1END2", "T_TERM_UTURN_INT_SL1END2" ], [ - "SS6B1", - "T_TERM_UTURN_INT_SS6B1" - ], - [ - "NE2BEG3", - "T_TERM_UTURN_INT_SE2A0" - ], - [ - "SS6END0", - "T_TERM_UTURN_INT_SS6END0" - ], - [ - "ER1END3", - "T_TERM_UTURN_INT_ER1END3" - ], - [ - "NN6BEG3", - "T_TERM_UTURN_INT_SS6A0" - ], - [ - "NR1BEG0", + "SL1END3", "T_TERM_UTURN_INT_SL1END3" ], [ - "NW6D2", - "T_TERM_UTURN_INT_SW6E1" + "SR1END1", + "T_TERM_UTURN_INT_SR1END1" ], [ - "LV_L17", - "T_TERM_UTURN_INT_LV_L17" + "SR1END2", + "T_TERM_UTURN_INT_SR1END2" ], [ - "ER1BEG_S0", - "T_TERM_UTURN_INT_ER1BEG_S0" + "SR1END3", + "T_TERM_UTURN_INT_SR1END3" ], [ - "SW6D2", - "T_TERM_UTURN_INT_SW6D2" + "SS2A0", + "T_TERM_UTURN_INT_SS2A0" ], [ - "SS6E1", - "T_TERM_UTURN_INT_SS6E1" + "SS2A1", + "T_TERM_UTURN_INT_SS2A1" ], [ - "SE6C1", - "T_TERM_UTURN_INT_SE6C1" + "SS2A2", + "T_TERM_UTURN_INT_SS2A2" ], [ - "LV_L7", - "T_TERM_UTURN_INT_LV_L7" + "SS2A3", + "T_TERM_UTURN_INT_SS2A3" ], [ - "SS6C0", - "T_TERM_UTURN_INT_SS6C0" - ], - [ - "NW6C3", - "T_TERM_UTURN_INT_SW6D0" + "SS2END0", + "T_TERM_UTURN_INT_SS2END0" ], [ "SS2END1", "T_TERM_UTURN_INT_SS2END1" ], [ - "SW6C2", - "T_TERM_UTURN_INT_SW6C2" + "SS2END2", + "T_TERM_UTURN_INT_SS2END2" ], [ - "NN6E3", + "SS2END3", + "T_TERM_UTURN_INT_SS2END3" + ], + [ + "SS6A0", + "T_TERM_UTURN_INT_SS6A0" + ], + [ + "SS6A1", + "T_TERM_UTURN_INT_SS6A1" + ], + [ + "SS6A2", + "T_TERM_UTURN_INT_SS6A2" + ], + [ + "SS6A3", + "T_TERM_UTURN_INT_SS6A3" + ], + [ + "SS6B0", + "T_TERM_UTURN_INT_SS6B0" + ], + [ + "SS6B1", + "T_TERM_UTURN_INT_SS6B1" + ], + [ + "SS6B2", + "T_TERM_UTURN_INT_SS6B2" + ], + [ + "SS6B3", + "T_TERM_UTURN_INT_SS6B3" + ], + [ + "SS6C0", + "T_TERM_UTURN_INT_SS6C0" + ], + [ + "SS6C1", + "T_TERM_UTURN_INT_SS6C1" + ], + [ + "SS6C2", + "T_TERM_UTURN_INT_SS6C2" + ], + [ + "SS6C3", + "T_TERM_UTURN_INT_SS6C3" + ], + [ + "SS6D0", + "T_TERM_UTURN_INT_SS6D0" + ], + [ + "SS6D1", + "T_TERM_UTURN_INT_SS6D1" + ], + [ + "SS6D2", + "T_TERM_UTURN_INT_SS6D2" + ], + [ + "SS6D3", + "T_TERM_UTURN_INT_SS6D3" + ], + [ + "SS6E0", + "T_TERM_UTURN_INT_SS6E0" + ], + [ + "SS6E1", + "T_TERM_UTURN_INT_SS6E1" + ], + [ + "SS6E2", + "T_TERM_UTURN_INT_SS6E2" + ], + [ + "SS6E3", + "T_TERM_UTURN_INT_SS6E3" + ], + [ + "SS6END0", "T_TERM_UTURN_INT_SS6END0" ], + [ + "SS6END1", + "T_TERM_UTURN_INT_SS6END1" + ], + [ + "SS6END2", + "T_TERM_UTURN_INT_SS6END2" + ], + [ + "SS6END3", + "T_TERM_UTURN_INT_SS6END3" + ], + [ + "SW2A0", + "T_TERM_UTURN_INT_SW2A0" + ], + [ + "SW2A1", + "T_TERM_UTURN_INT_SW2A1" + ], + [ + "SW2A2", + "T_TERM_UTURN_INT_SW2A2" + ], + [ + "SW2A3", + "T_TERM_UTURN_INT_SW2A3" + ], [ "SW6B0", "T_TERM_UTURN_INT_SW6B0" @@ -457066,288 +395034,76 @@ "T_TERM_UTURN_INT_SW6B1" ], [ - "SE2A0", - "T_TERM_UTURN_INT_SE2A0" - ], - [ - "NW6B1", - "T_TERM_UTURN_INT_SW6C2" - ], - [ - "NE6C0", - "T_TERM_UTURN_INT_SE6D3" - ], - [ - "SW6D1", - "T_TERM_UTURN_INT_SW6D1" - ], - [ - "NN6E2", - "T_TERM_UTURN_INT_SS6END1" - ], - [ - "SR1END2", - "T_TERM_UTURN_INT_SR1END2" - ], - [ - "SE6E3", - "T_TERM_UTURN_INT_SE6E3" - ], - [ - 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+ "IMUX7", + "INT_INTERFACE_IMUX7" ], [ - "MONITOR_IMUX24_7", - "VFRAME_IMUX24" + "IMUX8", + "INT_INTERFACE_IMUX8" ], [ - "MONITOR_BYP2_7", - "VFRAME_BYP2" + "IMUX9", + "INT_INTERFACE_IMUX9" ], [ - "MONITOR_IMUX23_7", - "VFRAME_IMUX23" + "IMUX10", + "INT_INTERFACE_IMUX10" ], [ - "MONITOR_NW4END1_7", - "VFRAME_NW4END1" + "IMUX11", + "INT_INTERFACE_IMUX11" ], [ - "MONITOR_IMUX29_7", - "VFRAME_IMUX29" + "IMUX12", + "INT_INTERFACE_IMUX12" ], [ - "MONITOR_FAN1_7", - "VFRAME_FAN1" + "IMUX13", + "INT_INTERFACE_IMUX13" ], [ - "MONITOR_EE4BEG1_7", - "VFRAME_EE4BEG1" + "IMUX14", + "INT_INTERFACE_IMUX14" ], [ - "MONITOR_IMUX34_7", - "VFRAME_IMUX34" + "IMUX15", + "INT_INTERFACE_IMUX15" ], [ - "MONITOR_FAN0_7", - "VFRAME_FAN0" + "IMUX16", + "INT_INTERFACE_IMUX16" ], [ - "MONITOR_CLK1_7", - "VFRAME_CLK1" + "IMUX17", + "INT_INTERFACE_IMUX17" ], [ - "MONITOR_SW4A3_7", - "VFRAME_SW4A3" + "IMUX18", + "INT_INTERFACE_IMUX18" ], [ - "MONITOR_IMUX22_7", - "VFRAME_IMUX22" + "IMUX19", + "INT_INTERFACE_IMUX19" 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"IMUX44", + "INT_INTERFACE_IMUX44" ], [ - "MONITOR_NE4BEG3_7", - "VFRAME_NE4BEG3" + "IMUX45", + "INT_INTERFACE_IMUX45" ], [ - "MONITOR_EL1BEG2_7", - "VFRAME_EL1BEG2" + "IMUX46", + "INT_INTERFACE_IMUX46" ], [ - "MONITOR_WR1END0_7", - "VFRAME_WR1END0" + "IMUX47", + "INT_INTERFACE_IMUX47" ], [ - "MONITOR_IMUX45_7", - "VFRAME_IMUX45" + "INT_DQS_IOTOPHASER", + "L_INT_INTER_DQS_IOTOPHASER" ], [ - "MONITOR_FAN5_7", - "VFRAME_FAN5" + "INT_PHASER_TO_IO_ICLK", + "INT_INTERFACE_PHASER_TO_IO_ICLK" ], [ - "MONITOR_IMUX38_7", - "VFRAME_IMUX38" + "INT_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" ], [ - "MONITOR_WW4END3_7", - "VFRAME_WW4END3" + "INT_PHASER_TO_IO_OCLK", + "INT_INTERFACE_PHASER_TO_IO_OCLK" ], [ - "MONITOR_IMUX18_7", - "VFRAME_IMUX18" + "INT_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90" ], [ - "MONITOR_NE2A0_7", - "VFRAME_NE2A0" + "INT_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" ], [ - "MONITOR_LH10_7", - "VFRAME_LH10" + "LH1", + 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"VFRAME_EE2A1" + "LOGIC_OUTS23", + "INT_INTERFACE_LOGIC_OUTS23" ], [ - "MONITOR_SW4END0_7", - "VFRAME_SW4END0" + "MONITOR_N", + "INT_INTERFACE_MONITOR_N" ], [ - "MONITOR_EE2A0_7", - "VFRAME_EE2A0" + "MONITOR_P", + "INT_INTERFACE_MONITOR_P" ], [ - "MONITOR_WW4C2_7", - "VFRAME_WW4C2" + "NE2A0", + "INT_INTERFACE_NE2A0" ], [ - "MONITOR_EE4C3_7", - "VFRAME_EE4C3" + "NE2A1", + "INT_INTERFACE_NE2A1" ], [ - "MONITOR_WW4B3_7", - "VFRAME_WW4B3" + "NE2A2", + "INT_INTERFACE_NE2A2" ], [ - "MONITOR_IMUX10_7", - "VFRAME_IMUX10" + "NE2A3", + "INT_INTERFACE_NE2A3" ], [ - "MONITOR_EE4B0_7", - "VFRAME_EE4B0" + "NE6BEG0", + "INT_INTERFACE_NE4BEG0" ], [ - "MONITOR_NW4A1_7", - "VFRAME_NW4A1" + "NE6BEG1", + "INT_INTERFACE_NE4BEG1" ], [ - "MONITOR_NW4A2_7", - "VFRAME_NW4A2" + "NE6BEG2", + "INT_INTERFACE_NE4BEG2" ], [ - "MONITOR_IMUX12_7", - "VFRAME_IMUX12" + "NE6BEG3", + "INT_INTERFACE_NE4BEG3" ], [ - "MONITOR_EE4C2_7", - "VFRAME_EE4C2" + "NE6E0", + "INT_INTERFACE_NE4C0" ], [ - "MONITOR_IMUX6_7", - "VFRAME_IMUX6" + "NE6E1", + "INT_INTERFACE_NE4C1" ], [ - "MONITOR_NE4C0_7", - "VFRAME_NE4C0" + "NE6E2", + "INT_INTERFACE_NE4C2" ], [ - "MONITOR_NW4A3_7", - "VFRAME_NW4A3" + "NE6E3", + "INT_INTERFACE_NE4C3" ], [ - "MONITOR_WW4END1_7", - "VFRAME_WW4END1" + "NW2END0", + "INT_INTERFACE_NW2A0" ], [ - "MONITOR_IMUX26_7", - "VFRAME_IMUX26" + "NW2END1", + "INT_INTERFACE_NW2A1" ], [ - "MONITOR_IMUX41_7", - "VFRAME_IMUX41" + "NW2END2", + "INT_INTERFACE_NW2A2" ], [ - "MONITOR_WW4C0_7", - "VFRAME_WW4C0" + "NW2END3", + "INT_INTERFACE_NW2A3" ], [ - "MONITOR_EE2BEG3_7", - "VFRAME_EE2BEG3" + "NW6A0", + "INT_INTERFACE_NW4A0" ], [ - "MONITOR_NE4C2_7", - "VFRAME_NE4C2" + "NW6A1", + "INT_INTERFACE_NW4A1" ], [ - "MONITOR_IMUX19_7", - "VFRAME_IMUX19" + "NW6A2", + "INT_INTERFACE_NW4A2" ], [ - "MONITOR_SE2A2_7", - "VFRAME_SE2A2" + "NW6A3", + "INT_INTERFACE_NW4A3" ], [ - "MONITOR_WR1END1_7", - "VFRAME_WR1END1" + "NW6END0", + "INT_INTERFACE_NW4END0" ], [ - "MONITOR_WW2END2_7", - "VFRAME_WW2END2" + "NW6END1", + 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"INT_FEEDTHRU_2_SE2A2" - ], - [ - "CFG_CENTER_WW4A2_19", - "INT_FEEDTHRU_2_WW4A2" - ], - [ - "CFG_CENTER_NE2A2_19", - "INT_FEEDTHRU_2_NE2A2" - ], - [ - "CFG_CENTER_NW4A2_19", - "INT_FEEDTHRU_2_NW4A2" - ], - [ - "CFG_CENTER_WW4END2_19", - "INT_FEEDTHRU_2_WW4END2" - ], - [ - "CFG_CENTER_WW4C3_19", - "INT_FEEDTHRU_2_WW4C3" - ], - [ - "CFG_CENTER_NE4C2_19", - "INT_FEEDTHRU_2_NE4C2" - ], - [ - "CFG_CENTER_SE2A3_19", - "INT_FEEDTHRU_2_SE2A3" - ], - [ - "CFG_CENTER_NE4C3_19", - "INT_FEEDTHRU_2_NE4C3" - ], - [ - "CFG_CENTER_WL1END1_19", - "INT_FEEDTHRU_2_WL1END1" - ], - [ - "CFG_CENTER_WW4B1_19", - "INT_FEEDTHRU_2_WW4B1" - ], - [ - "CFG_CENTER_LH3_19", - "INT_FEEDTHRU_2_LH3" - ], - [ - "CFG_CENTER_NE2A3_19", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_WW4A3_19", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_SW2A2_19", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_EE2A1_19", - "INT_FEEDTHRU_2_EE2A1" - ], - [ - "CFG_CENTER_EE4B2_19", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_SW4END3_19", - "INT_FEEDTHRU_2_SW4END3" - ], - [ - "CFG_CENTER_WL1END3_19", - "INT_FEEDTHRU_2_WL1END3" - ], - [ - "CFG_CENTER_WW2A0_19", - "INT_FEEDTHRU_2_WW2A0" - ], - [ - "CFG_CENTER_EE2BEG3_19", - "INT_FEEDTHRU_2_EE2BEG3" - ], - [ - "CFG_CENTER_SE4BEG2_19", - "INT_FEEDTHRU_2_SE4BEG2" - ], - [ - "CFG_CENTER_WL1END2_19", - "INT_FEEDTHRU_2_WL1END2" - ], - [ - "CFG_CENTER_EE4B0_19", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_WW2END2_19", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_SW2A1_19", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_NW4END2_19", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_LH5_19", - "INT_FEEDTHRU_2_LH5" - ], - [ - "CFG_CENTER_NW4A1_19", - "INT_FEEDTHRU_2_NW4A1" - ], - [ - "CFG_CENTER_NW2A2_19", - "INT_FEEDTHRU_2_NW2A2" - ], - [ - "CFG_CENTER_NW2A3_19", - "INT_FEEDTHRU_2_NW2A3" - ], - [ - "CFG_CENTER_WW4B2_19", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_EL1BEG2_19", - "INT_FEEDTHRU_2_EL1BEG2" - ], - [ - "CFG_CENTER_EE4A2_19", - "INT_FEEDTHRU_2_EE4A2" - ], - [ - "CFG_CENTER_EE4A0_19", - "INT_FEEDTHRU_2_EE4A0" - ], - [ - "CFG_CENTER_WW4A1_19", - "INT_FEEDTHRU_2_WW4A1" - ], - [ - "CFG_CENTER_NW2A1_19", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_SW2A3_19", - "INT_FEEDTHRU_2_SW2A3" - ], - [ - "CFG_CENTER_LH6_19", - "INT_FEEDTHRU_2_LH6" - ], - [ - "CFG_CENTER_LH11_19", - "INT_FEEDTHRU_2_LH11" - ], - [ - "CFG_CENTER_SW4END1_19", - "INT_FEEDTHRU_2_SW4END1" - ], - [ - "CFG_CENTER_WW4C2_19", - "INT_FEEDTHRU_2_WW4C2" - ], - [ - "CFG_CENTER_LH12_19", - "INT_FEEDTHRU_2_LH12" - ], - [ - "CFG_CENTER_LH2_19", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_WW2A3_19", - "INT_FEEDTHRU_2_WW2A3" - ], - [ - "CFG_CENTER_LH8_19", - "INT_FEEDTHRU_2_LH8" - ], - [ - "CFG_CENTER_WW4END1_19", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_NE4BEG0_19", - "INT_FEEDTHRU_2_NE4BEG0" - ], - [ - "CFG_CENTER_NE4C0_19", - "INT_FEEDTHRU_2_NE4C0" - ], - [ - "CFG_CENTER_SE4C2_19", - "INT_FEEDTHRU_2_SE4C2" - ], - [ - "CFG_CENTER_EE4C3_19", - "INT_FEEDTHRU_2_EE4C3" - ], - [ - "CFG_CENTER_EE4A1_19", - "INT_FEEDTHRU_2_EE4A1" - ], - [ - "CFG_CENTER_EE2BEG1_19", - "INT_FEEDTHRU_2_EE2BEG1" - ], - [ - "CFG_CENTER_WW4C1_19", - "INT_FEEDTHRU_2_WW4C1" - ], - [ - "CFG_CENTER_SE4C3_19", - "INT_FEEDTHRU_2_SE4C3" - ], - [ - "CFG_CENTER_EE4BEG0_19", - "INT_FEEDTHRU_2_EE4BEG0" - ], - [ - "CFG_CENTER_NW4END3_19", - "INT_FEEDTHRU_2_NW4END3" - ], - [ - "CFG_CENTER_NE4BEG2_19", - "INT_FEEDTHRU_2_NE4BEG2" - ], - [ - "CFG_CENTER_WW4END3_19", - "INT_FEEDTHRU_2_WW4END3" - ], - [ - "CFG_CENTER_SW4A3_19", - "INT_FEEDTHRU_2_SW4A3" - ], - [ - "CFG_CENTER_WR1END0_19", - "INT_FEEDTHRU_2_WR1END0" - ], - [ - "CFG_CENTER_NW4A3_19", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_NE4BEG3_19", - "INT_FEEDTHRU_2_NE4BEG3" - ], - [ - "CFG_CENTER_EL1BEG3_19", - "INT_FEEDTHRU_2_EL1BEG3" - ], - [ - "CFG_CENTER_NE4C1_19", - "INT_FEEDTHRU_2_NE4C1" - ], - [ - "CFG_CENTER_EE4BEG2_19", - "INT_FEEDTHRU_2_EE4BEG2" - ], - [ - "CFG_CENTER_LH4_19", - "INT_FEEDTHRU_2_LH4" - ], - [ - "CFG_CENTER_EL1BEG0_19", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_NE2A0_19", - "INT_FEEDTHRU_2_NE2A0" - ], - [ - "CFG_CENTER_SE4C1_19", - "INT_FEEDTHRU_2_SE4C1" - ], - [ - "CFG_CENTER_SE4BEG3_19", - "INT_FEEDTHRU_2_SE4BEG3" - ], - [ - "CFG_CENTER_SW4END2_19", - "INT_FEEDTHRU_2_SW4END2" - ], - [ - "CFG_CENTER_NW4END1_19", - "INT_FEEDTHRU_2_NW4END1" + "IOI_PHASER_TO_IO_OCLKDIV", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" ] ] }, @@ -463685,9937 +402537,373 @@ -1 ], "tile_types": [ - "CLK_BUFG_REBUF", - "VBRK" + "LIOI3_TBYTESRC", + "L_TERM_INT" ], "wire_pairs": [ [ - "CLK_BUFG_REBUF_SW2A3_1", - "VBRK_SW2A3" + "IOI_BLOCK_OUTS0_1", + "TERM_INT_BLOCK_OUTS_L_B0" ], [ - "CLK_BUFG_REBUF_EE4BEG1_1", - "VBRK_EE4BEG1" + "IOI_BLOCK_OUTS2_1", + "TERM_INT_BLOCK_OUTS_L_B2" ], [ - "CLK_BUFG_REBUF_SE2A2_1", - "VBRK_SE2A2" + "IOI_BYP0_1", + "TERM_INT_BYP0" ], [ - "CLK_BUFG_REBUF_LH11_1", - "VBRK_LH11" + "IOI_BYP1_1", + "TERM_INT_BYP1" ], [ - "CLK_BUFG_REBUF_WW4B3_1", - "VBRK_WW4B3" + "IOI_BYP2_1", + "TERM_INT_BYP2" ], [ - "CLK_BUFG_REBUF_NE4BEG0_1", - "VBRK_NE4BEG0" + "IOI_BYP3_1", + "TERM_INT_BYP3" ], [ - "CLK_BUFG_REBUF_NE2A2_1", - "VBRK_NE2A2" + "IOI_BYP4_1", + "TERM_INT_BYP4" ], [ - "CLK_BUFG_REBUF_LH1_1", - "VBRK_LH1" + "IOI_BYP5_1", + "TERM_INT_BYP5" ], [ - "CLK_BUFG_REBUF_WW4END0_1", - "VBRK_WW4END0" + "IOI_BYP6_1", + "TERM_INT_BYP6" ], [ - "CLK_BUFG_REBUF_SE4C2_1", - "VBRK_SE4C2" + "IOI_BYP7_1", + "TERM_INT_BYP7" ], [ - "CLK_BUFG_REBUF_NE4C0_1", - "VBRK_NE4C0" + "IOI_CLK0_1", + "TERM_INT_CLK0" ], [ - "CLK_BUFG_REBUF_EE4B0_1", - "VBRK_EE4B0" + "IOI_CLK1_1", + "TERM_INT_CLK1" ], [ - "CLK_BUFG_REBUF_LH6_1", - "VBRK_LH6" + "IOI_CTRL0_1", + "TERM_INT_CTRL0" ], [ - "CLK_BUFG_REBUF_NW2A0_1", - "VBRK_NW2A0" + "IOI_CTRL1_1", + "TERM_INT_CTRL1" ], [ - "CLK_BUFG_REBUF_NE4C3_1", - "VBRK_NE4C3" + "IOI_FAN0_1", + "TERM_INT_FAN0" ], [ - "CLK_BUFG_REBUF_LH4_1", - "VBRK_LH4" + "IOI_FAN1_1", + "TERM_INT_FAN1" ], [ - "CLK_BUFG_REBUF_NE4C2_1", - "VBRK_NE4C2" + "IOI_FAN2_1", + "TERM_INT_FAN2" ], [ - "CLK_BUFG_REBUF_WW4A1_1", - "VBRK_WW4A1" + "IOI_FAN3_1", + "TERM_INT_FAN3" ], [ - "CLK_BUFG_REBUF_WW2END1_1", - "VBRK_WW2END1" + "IOI_FAN4_1", + "TERM_INT_FAN4" ], [ - "CLK_BUFG_REBUF_WL1END3_1", - "VBRK_WL1END3" + "IOI_FAN5_1", + "TERM_INT_FAN5" ], [ - "CLK_BUFG_REBUF_EE4B1_1", - "VBRK_EE4B1" + "IOI_FAN6_1", + "TERM_INT_FAN6" ], [ - "CLK_BUFG_REBUF_WW4C3_1", - "VBRK_WW4C3" + "IOI_FAN7_1", + "TERM_INT_FAN7" ], [ - "CLK_BUFG_REBUF_EE4A1_1", - "VBRK_EE4A1" + "IOI_IMUX0_1", + "TERM_INT_IMUX0" ], [ - "CLK_BUFG_REBUF_SE4BEG0_1", - "VBRK_SE4BEG0" + "IOI_IMUX1_1", + "TERM_INT_IMUX1" ], [ - "CLK_BUFG_REBUF_WR1END3_1", - "VBRK_WR1END3" + "IOI_IMUX2_1", + "TERM_INT_IMUX2" ], [ - "CLK_BUFG_REBUF_NW4A0_1", - "VBRK_NW4A0" + "IOI_IMUX3_1", + "TERM_INT_IMUX3" ], [ - "CLK_BUFG_REBUF_ER1BEG3_1", - "VBRK_ER1BEG3" + "IOI_IMUX4_1", + "TERM_INT_IMUX4" ], [ - "CLK_BUFG_REBUF_WW4B2_1", - "VBRK_WW4B2" + "IOI_IMUX5_1", + "TERM_INT_IMUX5" ], [ - "CLK_BUFG_REBUF_EE4A2_1", - "VBRK_EE4A2" + "IOI_IMUX6_1", + "TERM_INT_IMUX6" ], [ - "CLK_BUFG_REBUF_WW4B0_1", - "VBRK_WW4B0" + "IOI_IMUX7_1", + "TERM_INT_IMUX7" ], [ - "CLK_BUFG_REBUF_LH7_1", - "VBRK_LH7" + "IOI_IMUX8_1", + "TERM_INT_IMUX8" ], [ - "CLK_BUFG_REBUF_WW4C0_1", - "VBRK_WW4C0" + "IOI_IMUX9_1", + "TERM_INT_IMUX9" ], [ - "CLK_BUFG_REBUF_LH5_1", - "VBRK_LH5" + "IOI_IMUX10_1", + "TERM_INT_IMUX10" ], [ - "CLK_BUFG_REBUF_WW2A1_1", - "VBRK_WW2A1" + "IOI_IMUX11_1", + "TERM_INT_IMUX11" ], [ - "CLK_BUFG_REBUF_WR1END0_1", - "VBRK_WR1END0" + "IOI_IMUX12_1", + "TERM_INT_IMUX12" ], [ - "CLK_BUFG_REBUF_NE4BEG1_1", - "VBRK_NE4BEG1" + "IOI_IMUX13_1", + "TERM_INT_IMUX13" ], [ - "CLK_BUFG_REBUF_WW2END0_1", - "VBRK_WW2END0" + "IOI_IMUX14_1", + "TERM_INT_IMUX14" ], [ - "CLK_BUFG_REBUF_LH8_1", - "VBRK_LH8" + "IOI_IMUX15_1", + "TERM_INT_IMUX15" ], [ - "CLK_BUFG_REBUF_WW4END1_1", - "VBRK_WW4END1" + "IOI_IMUX16_1", + "TERM_INT_IMUX16" ], [ - "CLK_BUFG_REBUF_EE2BEG2_1", - "VBRK_EE2BEG2" + "IOI_IMUX17_1", + "TERM_INT_IMUX17" ], [ - "CLK_BUFG_REBUF_NE4BEG2_1", - "VBRK_NE4BEG2" + "IOI_IMUX18_1", + "TERM_INT_IMUX18" ], [ - "CLK_BUFG_REBUF_EL1BEG1_1", - "VBRK_EL1BEG1" + "IOI_IMUX19_1", + "TERM_INT_IMUX19" ], [ - "CLK_BUFG_REBUF_WR1END1_1", - "VBRK_WR1END1" + "IOI_IMUX20_1", + "TERM_INT_IMUX20" ], [ - "CLK_BUFG_REBUF_LH12_1", - "VBRK_LH12" + "IOI_IMUX21_1", + "TERM_INT_IMUX21" ], [ - "CLK_BUFG_REBUF_ER1BEG0_1", - "VBRK_ER1BEG0" + "IOI_IMUX22_1", + "TERM_INT_IMUX22" ], [ - "CLK_BUFG_REBUF_NW2A1_1", - "VBRK_NW2A1" + "IOI_IMUX23_1", + "TERM_INT_IMUX23" ], [ - "CLK_BUFG_REBUF_NW4END0_1", - "VBRK_NW4END0" + "IOI_IMUX24_1", + "TERM_INT_IMUX24" ], [ - "CLK_BUFG_REBUF_EE2BEG0_1", - "VBRK_EE2BEG0" + "IOI_IMUX25_1", + "TERM_INT_IMUX25" ], [ - "CLK_BUFG_REBUF_LH2_1", - "VBRK_LH2" + "IOI_IMUX26_1", + "TERM_INT_IMUX26" ], [ - "CLK_BUFG_REBUF_NW4END3_1", - "VBRK_NW4END3" + "IOI_IMUX27_1", + "TERM_INT_IMUX27" ], [ - "CLK_BUFG_REBUF_SE2A3_1", - "VBRK_SE2A3" + "IOI_IMUX28_1", + "TERM_INT_IMUX28" ], [ - "CLK_BUFG_REBUF_EE4C3_1", - "VBRK_EE4C3" + "IOI_IMUX29_1", + "TERM_INT_IMUX29" ], [ - "CLK_BUFG_REBUF_WW4A0_1", - "VBRK_WW4A0" + "IOI_IMUX30_1", + "TERM_INT_IMUX30" ], [ - "CLK_BUFG_REBUF_SE2A1_1", - "VBRK_SE2A1" + "IOI_IMUX31_1", + "TERM_INT_IMUX31" ], [ - "CLK_BUFG_REBUF_WW2A3_1", - "VBRK_WW2A3" + "IOI_IMUX32_1", + "TERM_INT_IMUX32" ], [ - "CLK_BUFG_REBUF_SW4A1_1", - "VBRK_SW4A1" + "IOI_IMUX33_1", + "TERM_INT_IMUX33" ], [ - "CLK_BUFG_REBUF_EE4C0_1", - "VBRK_EE4C0" + "IOI_IMUX34_1", + "TERM_INT_IMUX34" ], [ - "CLK_BUFG_REBUF_SE2A0_1", - "VBRK_SE2A0" + "IOI_IMUX35_1", + "TERM_INT_IMUX35" ], [ - "CLK_BUFG_REBUF_MONITOR_N_1", - "VBRK_MONITOR_N" + "IOI_IMUX36_1", + "TERM_INT_IMUX36" ], [ - "CLK_BUFG_REBUF_SE4C1_1", - "VBRK_SE4C1" + "IOI_IMUX37_1", + "TERM_INT_IMUX37" ], [ - "CLK_BUFG_REBUF_EL1BEG2_1", - "VBRK_EL1BEG2" + "IOI_IMUX38_1", + "TERM_INT_IMUX38" ], [ - "CLK_BUFG_REBUF_SW4A3_1", - "VBRK_SW4A3" + "IOI_IMUX39_1", + "TERM_INT_IMUX39" ], [ - "CLK_BUFG_REBUF_SW4A2_1", - "VBRK_SW4A2" + "IOI_IMUX40_1", + "TERM_INT_IMUX40" ], [ - "CLK_BUFG_REBUF_WW4B1_1", - "VBRK_WW4B1" + "IOI_IMUX41_1", + "TERM_INT_IMUX41" ], [ - "CLK_BUFG_REBUF_EE4C1_1", - "VBRK_EE4C1" + "IOI_IMUX42_1", + "TERM_INT_IMUX42" ], [ - "CLK_BUFG_REBUF_EE4A3_1", - "VBRK_EE4A3" + "IOI_IMUX43_1", + "TERM_INT_IMUX43" ], [ - "CLK_BUFG_REBUF_LH10_1", - "VBRK_LH10" + "IOI_IMUX44_1", + "TERM_INT_IMUX44" ], [ - "CLK_BUFG_REBUF_WL1END2_1", - "VBRK_WL1END2" + "IOI_IMUX45_1", + "TERM_INT_IMUX45" ], [ - "CLK_BUFG_REBUF_WW4END3_1", - "VBRK_WW4END3" + "IOI_IMUX46_1", + "TERM_INT_IMUX46" ], [ - "CLK_BUFG_REBUF_EL1BEG3_1", - "VBRK_EL1BEG3" + "IOI_IMUX47_1", + "TERM_INT_IMUX47" ], [ - "CLK_BUFG_REBUF_SW4END2_1", - "VBRK_SW4END2" + "IOI_LOGIC_OUTS0_1", + "TERM_INT_LOGIC_OUTS_L_B0" ], [ - "CLK_BUFG_REBUF_NW2A2_1", - "VBRK_NW2A2" + "IOI_LOGIC_OUTS1_1", + "TERM_INT_LOGIC_OUTS_L_B1" ], [ - "CLK_BUFG_REBUF_EE2A2_1", - "VBRK_EE2A2" + "IOI_LOGIC_OUTS2_1", + "TERM_INT_LOGIC_OUTS_L_B2" ], [ - "CLK_BUFG_REBUF_WW4END2_1", - "VBRK_WW4END2" + "IOI_LOGIC_OUTS3_1", + "TERM_INT_LOGIC_OUTS_L_B3" ], [ - "CLK_BUFG_REBUF_SW2A1_1", - "VBRK_SW2A1" + "IOI_LOGIC_OUTS5_1", + "TERM_INT_LOGIC_OUTS_L_B5" ], [ - "CLK_BUFG_REBUF_MONITOR_P_1", - "VBRK_MONITOR_P" + "IOI_LOGIC_OUTS7_1", + "TERM_INT_LOGIC_OUTS_L_B7" ], [ - "CLK_BUFG_REBUF_NW4A2_1", - "VBRK_NW4A2" + "IOI_LOGIC_OUTS8_1", + "TERM_INT_LOGIC_OUTS_L_B8" ], [ - "CLK_BUFG_REBUF_NW4END1_1", - "VBRK_NW4END1" + "IOI_LOGIC_OUTS9_1", + "TERM_INT_LOGIC_OUTS_L_B9" ], [ - "CLK_BUFG_REBUF_WR1END2_1", - "VBRK_WR1END2" + "IOI_LOGIC_OUTS10_1", + "TERM_INT_LOGIC_OUTS_L_B10" ], [ - "CLK_BUFG_REBUF_SW2A0_1", - "VBRK_SW2A0" + "IOI_LOGIC_OUTS11_1", + "TERM_INT_LOGIC_OUTS_L_B11" ], [ - "CLK_BUFG_REBUF_EE4A0_1", - "VBRK_EE4A0" + "IOI_LOGIC_OUTS14_1", + "TERM_INT_LOGIC_OUTS_L_B14" ], [ - "CLK_BUFG_REBUF_WL1END1_1", - "VBRK_WL1END1" + "IOI_LOGIC_OUTS15_1", + "TERM_INT_LOGIC_OUTS_L_B15" ], [ - "CLK_BUFG_REBUF_NW4A3_1", - "VBRK_NW4A3" + "IOI_LOGIC_OUTS18_1", + "TERM_INT_LOGIC_OUTS_L_B18" ], [ - "CLK_BUFG_REBUF_WW2END3_1", - "VBRK_WW2END3" + "IOI_LOGIC_OUTS19_1", + "TERM_INT_LOGIC_OUTS_L_B19" ], [ - "CLK_BUFG_REBUF_EE4BEG3_1", - "VBRK_EE4BEG3" + "IOI_LOGIC_OUTS20_1", + "TERM_INT_LOGIC_OUTS_L_B20" ], [ - "CLK_BUFG_REBUF_EE4BEG2_1", - "VBRK_EE4BEG2" + "IOI_LOGIC_OUTS23_1", + "TERM_INT_LOGIC_OUTS_L_B23" ], [ - "CLK_BUFG_REBUF_WW4A2_1", - "VBRK_WW4A2" + "IOI_PHASER_TO_IO_ICLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" ], [ - "CLK_BUFG_REBUF_NE2A1_1", - "VBRK_NE2A1" + "IOI_PHASER_TO_IO_ICLK_0", + "L_TERM_INT_PHASER_TO_IO_ICLK" ], [ - "CLK_BUFG_REBUF_EE2A0_1", - "VBRK_EE2A0" + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" ], [ - "CLK_BUFG_REBUF_WL1END0_1", - "VBRK_WL1END0" + "IOI_PHASER_TO_IO_OCLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" ], [ - "CLK_BUFG_REBUF_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_BUFG_REBUF_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_BUFG_REBUF_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_BUFG_REBUF_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_BUFG_REBUF_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_BUFG_REBUF_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_BUFG_REBUF_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_BUFG_REBUF_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_BUFG_REBUF_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CLK_BUFG_REBUF_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_BUFG_REBUF_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_BUFG_REBUF_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_BUFG_REBUF_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_BUFG_REBUF_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_BUFG_REBUF_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CLK_BUFG_REBUF_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CLK_BUFG_REBUF_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_BUFG_REBUF_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_BUFG_REBUF_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_BUFG_REBUF_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_BUFG_REBUF_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_BUFG_REBUF_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_BUFG_REBUF_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_BUFG_REBUF_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_BUFG_REBUF_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CLK_BUFG_REBUF_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_BUFG_REBUF_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_BUFG_REBUF_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_BUFG_REBUF_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CLK_BUFG_REBUF_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_BUFG_REBUF_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_BUFG_REBUF_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_BUFG_REBUF_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_BUFG_REBUF_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_BUFG_REBUF_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_BUFG_REBUF_SE4C3_1", - "VBRK_SE4C3" - ] - ] - }, - { - "grid_deltas": [ - -1, - -1 - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_BUFG_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_BUFG_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_BUFG_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_1", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_BUFG_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_BUFG_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_BUFG_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_BUFG_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_BUFG_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_BUFG_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "CLK_BUFG_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_BUFG_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_MONITOR_N_1", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_BUFG_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_1", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_HROW_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_BUFG_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_BUFG_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_BUFG_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_1", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_HROW_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_1", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_BUFG_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_1", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_1", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_BUFG_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_BUFG_IMUX3_1", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_BUFG_IMUX39_1", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_BUFG_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_1", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_BUFG_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_BUFG_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_ER1BEG0_1", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_BUFG_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_BUFG_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_EE4C2_1", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_BUFG_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_BUFG_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_BUFG_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_ER1BEG1_1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_BUFG_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_BUFG_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_BUFG_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_BUFG_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WW2A3_1", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_BUFG_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_BUFG_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SW2A0_1", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_BUFG_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_BUFG_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_BYP4_1", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_BUFG_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_BUFG_IMUX10_1", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_BUFG_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_NW4END3_1", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_BUFG_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_BUFG_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_MONITOR_P_1", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_1", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_HROW_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_L_BOT_UTURN", - "HCLK_R_BOT_UTURN" - ], - "wire_pairs": [ - [ - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CK_INOUT_L5", - "HCLK_CK_OUTIN_R1" - ], - [ - "HCLK_CK_INOUT_L0", - "HCLK_CK_OUTIN_R4" - ], - [ - "HCLK_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_CK_OUTIN_L2", - "HCLK_CK_INOUT_R2" - ], - [ - "HCLK_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CK_OUTIN_L4", - "HCLK_CK_INOUT_R4" - ], - [ - "HCLK_CK_OUTIN_L7", - "HCLK_CK_INOUT_R7" - ], - [ - "HCLK_CK_OUTIN_L6", - "HCLK_CK_INOUT_R6" - ], - [ - "HCLK_CK_OUTIN_L5", - "HCLK_CK_INOUT_R5" - ], - [ - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_CK_OUTIN_L0", - "HCLK_CK_INOUT_R0" - ], - [ - "HCLK_CK_INOUT_L2", - "HCLK_CK_OUTIN_R6" - ], - [ - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CK_INOUT_L6", - "HCLK_CK_OUTIN_R2" - ], - [ - "HCLK_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CK_OUTIN_L3", - "HCLK_CK_INOUT_R3" - ], - [ - "HCLK_CK_INOUT_L1", - "HCLK_CK_OUTIN_R5" - ], - [ - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CK_INOUT_L4", - "HCLK_CK_OUTIN_R0" - ], - [ - "HCLK_CK_OUTIN_L1", - "HCLK_CK_INOUT_R1" - ], - [ - "HCLK_CK_INOUT_L3", - "HCLK_CK_OUTIN_R7" - ], - [ - "HCLK_CK_INOUT_L7", - "HCLK_CK_OUTIN_R3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 2 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_IMUX17_2", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_IMUX42_2", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_WW4C0_2", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_WW4C2_2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_NW4A3_2", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_SW4A1_2", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_FAN6_2", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_SE2A3_2", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_IMUX31_2", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_FAN7_2", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_BYP5_2", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_EE2BEG0_2", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_IMUX14_2", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_IMUX19_2", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_LH3_2", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_IMUX39_2", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_IMUX22_2", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_IMUX3_2", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_IMUX20_2", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_LH12_2", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WR1END1_2", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_NW2A0_2", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_IMUX0_2", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_NW4END1_2", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_EE4B0_2", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_LH4_2", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_BYP3_2", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE4BEG3_2", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE4B3_2", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_EE4C0_2", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_BYP6_2", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX27_2", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_LH11_2", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW4B3_2", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_NE4BEG0_2", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_WW2A3_2", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_WW2A0_2", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_IMUX40_2", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_IMUX37_2", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_IMUX29_2", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_FAN5_2", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_ER1BEG2_2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_IMUX5_2", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_NW4END2_2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_NE4C1_2", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_IMUX9_2", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_SE4C0_2", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_IMUX23_2", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_WW2A2_2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_IMUX33_2", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX11_2", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SE2A0_2", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_CTRL0_2", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_EL1BEG3_2", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_NW4A0_2", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_SE4BEG2_2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_NE2A0_2", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_SW4A3_2", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NW2A3_2", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_NE4C3_2", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_NW2A2_2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_IMUX16_2", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_EE2BEG1_2", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_WW4A3_2", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_WW2END1_2", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_LH10_2", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_SW4END0_2", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_IMUX46_2", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_EE4A3_2", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_MONITOR_P_2", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_IMUX18_2", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX15_2", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_IMUX30_2", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_WW2A1_2", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_SE4C1_2", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_FAN1_2", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_LH1_2", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_EE4BEG0_2", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4END3_2", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EE4BEG3_2", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_SW2A1_2", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_WL1END2_2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_NE2A3_2", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_LH2_2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_LH9_2", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_EE4A0_2", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4C3_2", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_LH6_2", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_IMUX35_2", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SE4BEG3_2", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE4BEG2_2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX8_2", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_BYP0_2", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_IMUX13_2", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_MONITOR_N_2", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_BYP1_2", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_IMUX47_2", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_NE2A1_2", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_IMUX12_2", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX21_2", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX44_2", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_SE4BEG0_2", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_SE4C2_2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_WR1END3_2", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_FAN3_2", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_EE2A2_2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE2A0_2", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_IMUX26_2", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_EE2A1_2", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_WW4B2_2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_NE2A2_2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_SW2A3_2", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_WW2END0_2", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_FAN0_2", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_EE4B2_2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_WW4A2_2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_WW4END1_2", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_WW4END2_2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_SE4BEG1_2", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_WW4B0_2", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_ER1BEG0_2", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_IMUX43_2", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_EE2BEG3_2", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_IMUX7_2", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WL1END0_2", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_EE4C2_2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_IMUX45_2", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_IMUX6_2", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_EE4A2_2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_FAN2_2", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_EL1BEG2_2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW4A0_2", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NW4END3_2", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_NW4A1_2", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_EE4B1_2", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SW4A2_2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_CTRL1_2", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP7_2", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_BYP4_2", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_IMUX24_2", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WW4END3_2", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_NE4BEG2_2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_WR1END2_2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_SE2A1_2", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_WW2END3_2", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_CLK0_2", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW2END2_2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_SW2A0_2", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_IMUX36_2", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_SE2A2_2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_LH5_2", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_WR1END0_2", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE4BEG1_2", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_FAN4_2", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_IMUX32_2", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NW4END0_2", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_WW4C1_2", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_IMUX2_2", - "INT_INTERFACE_IMUX2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 4 - ], - "tile_types": [ - "BRAM_INT_INTERFACE_R", - "BRAM_R" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX38", - "BRAM_IMUX38_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_4" - ], - [ - "INT_INTERFACE_SE4C0", - "BRAM_SE4C0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX20", - "BRAM_IMUX20_UTURN_4" - ], - [ - "INT_INTERFACE_NE2A1", - "BRAM_NE2A1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX11", - "BRAM_IMUX11_UTURN_4" - ], - [ - "INT_INTERFACE_NE4C0", - "BRAM_NE4C0_4" - ], - [ - "INT_INTERFACE_FAN3", - "BRAM_FAN3_4" - ], - [ - "INT_INTERFACE_SE4BEG0", - "BRAM_SE4BEG0_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "BRAM_IMUX25_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX11", - "BRAM_IMUX11_4" - ], - [ - "INT_INTERFACE_NW4END2", - "BRAM_NW4END2_4" - ], - [ - "INT_INTERFACE_SW4END2", - "BRAM_SW4END2_4" - ], - [ - "INT_INTERFACE_BYP2", - "BRAM_BYP2_4" - ], - [ - "INT_INTERFACE_EE4C2", - "BRAM_EE4C2_4" - ], - [ - "INT_INTERFACE_FAN5", - "BRAM_FAN5_4" - ], - [ - "INT_INTERFACE_WW4C1", - "BRAM_WW4C1_4" - ], - [ - "INT_INTERFACE_FAN2", - "BRAM_FAN2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX37", - "BRAM_IMUX37_UTURN_4" - ], - [ - "INT_INTERFACE_LH9", - "BRAM_LH9_4" - ], - [ - "INT_INTERFACE_LH5", - "BRAM_LH5_4" - ], - [ - "INT_INTERFACE_EE2A2", - "BRAM_EE2A2_4" - ], - [ - "INT_INTERFACE_SE4BEG1", - "BRAM_SE4BEG1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX44", - "BRAM_IMUX44_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "BRAM_IMUX1_4" - ], - [ - "INT_INTERFACE_LH1", - "BRAM_LH1_4" - ], - [ - "INT_INTERFACE_SW4A3", - "BRAM_SW4A3_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B22", - "BRAM_LOGIC_OUTS_B22_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX7", - "BRAM_IMUX7_4" - ], - [ - "INT_INTERFACE_BYP1", - "BRAM_BYP1_4" - ], - [ - "INT_INTERFACE_SW4END1", - "BRAM_SW4END1_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B6", - "BRAM_LOGIC_OUTS_B6_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B13", - "BRAM_LOGIC_OUTS_B13_4" - ], - [ - "INT_INTERFACE_BYP4", - "BRAM_BYP4_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX22", - "BRAM_IMUX22_UTURN_4" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_4" - ], - [ - "INT_INTERFACE_WW4END3", - "BRAM_WW4END3_4" - ], - [ - "INT_INTERFACE_NE4C2", - "BRAM_NE4C2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_4" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX13", - "BRAM_IMUX13_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX19", - "BRAM_IMUX19_UTURN_4" - ], - [ - "INT_INTERFACE_LH3", - "BRAM_LH3_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B23", - "BRAM_LOGIC_OUTS_B23_4" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX29", - "BRAM_IMUX29_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "BRAM_IMUX32_4" - ], - [ - "INT_INTERFACE_MONITOR_N", - "BRAM_MONITOR_N_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX9", - "BRAM_IMUX9_4" - ], - [ - "INT_INTERFACE_WW4C0", - "BRAM_WW4C0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX41", - "BRAM_IMUX41_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX43", - "BRAM_IMUX43_UTURN_4" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_4" - ], - [ - "INT_INTERFACE_NE4BEG3", - "BRAM_NE4BEG3_4" - ], - [ - "INT_INTERFACE_SW4A2", - "BRAM_SW4A2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX16", - "BRAM_IMUX16_UTURN_4" - ], - [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_4" - ], - [ - "INT_INTERFACE_WW2A3", - "BRAM_WW2A3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "BRAM_IMUX8_4" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX22", - "BRAM_IMUX22_4" - ], - [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_4" - ], - [ - "INT_INTERFACE_WW2A0", - "BRAM_WW2A0_4" - ], - [ - "INT_INTERFACE_WW2END1", - "BRAM_WW2END1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX28", - "BRAM_IMUX28_UTURN_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B8", - "BRAM_LOGIC_OUTS_B8_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B9", - "BRAM_LOGIC_OUTS_B9_4" - ], - [ - "INT_INTERFACE_WL1END1", - "BRAM_WL1END1_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "BRAM_IMUX6_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX3", - "BRAM_IMUX3_UTURN_4" - ], - [ - "INT_INTERFACE_SE2A2", - "BRAM_SE2A2_4" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_4" - ], - [ - "INT_INTERFACE_SE4C2", - "BRAM_SE4C2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX26", - "BRAM_IMUX26_4" - ], - [ - "INT_INTERFACE_NE4BEG0", - "BRAM_NE4BEG0_4" - ], - [ - "INT_INTERFACE_NW2A1", - "BRAM_NW2A1_4" - ], - [ - "INT_INTERFACE_WW4B0", - "BRAM_WW4B0_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B21", - "BRAM_LOGIC_OUTS_B21_4" - ], - [ - "INT_INTERFACE_EL1BEG1", - "BRAM_EL1BEG1_4" - ], - [ - "INT_INTERFACE_WW2END3", - "BRAM_WW2END3_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX4", - "BRAM_IMUX4_UTURN_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B17", - "BRAM_LOGIC_OUTS_B17_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX32", - "BRAM_IMUX32_UTURN_4" - ], - [ - "INT_INTERFACE_WW2A2", - "BRAM_WW2A2_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B3", - "BRAM_LOGIC_OUTS_B3_4" - ], - [ - "INT_INTERFACE_SE2A0", - "BRAM_SE2A0_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_4" - ], - [ - "INT_INTERFACE_FAN7", - "BRAM_FAN7_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX30", - "BRAM_IMUX30_4" - ], - [ - "INT_INTERFACE_SE4BEG3", - "BRAM_SE4BEG3_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX25", - "BRAM_IMUX25_UTURN_4" - ], - [ - "INT_INTERFACE_ER1BEG0", - "BRAM_ER1BEG0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX18", - "BRAM_IMUX18_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX27", - "BRAM_IMUX27_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B14", - "BRAM_LOGIC_OUTS_B14_4" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_4" - ], - [ - "INT_INTERFACE_EE4BEG2", - "BRAM_EE4BEG2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX16", - "BRAM_IMUX16_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_4" - ], - [ - "INT_INTERFACE_FAN4", - "BRAM_FAN4_4" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "BRAM_IMUX37_4" - ], - [ - "INT_INTERFACE_EE4A0", - "BRAM_EE4A0_4" - ], - [ - "INT_INTERFACE_EE4B1", - "BRAM_EE4B1_4" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX40", - "BRAM_IMUX40_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX34", - "BRAM_IMUX34_4" - ], - [ - "INT_INTERFACE_SW4A0", - "BRAM_SW4A0_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_4" - ], - [ - "INT_INTERFACE_WW4A3", - "BRAM_WW4A3_4" - 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"INT_INTERFACE_EE4B1" - ], - [ - "CMT_FIFO_EE4C0_4", - "INT_INTERFACE_EE4C0" - ], - [ - "CMT_FIFO_L_IMUX13_4", - "INT_INTERFACE_IMUX13" - ], - [ - "CMT_FIFO_WW2END0_4", - "INT_INTERFACE_WW2END0" - ], - [ - "CMT_FIFO_WW4END3_4", - "INT_INTERFACE_WW4END3" - ], - [ - "CMT_FIFO_LH7_4", - "INT_INTERFACE_LH7" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS16_4", - "INT_INTERFACE_LOGIC_OUTS_B16" - ], - [ - "CMT_FIFO_LH3_4", - "INT_INTERFACE_LH3" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS9_4", - "INT_INTERFACE_LOGIC_OUTS_B9" - ], - [ - "CMT_FIFO_ER1BEG2_4", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CMT_FIFO_ER1BEG0_4", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CMT_FIFO_L_IMUX1_4", - "INT_INTERFACE_IMUX1" - ], - [ - "CMT_FIFO_L_IMUX8_4", - "INT_INTERFACE_IMUX8" - ], - [ - "CMT_FIFO_EE2BEG1_4", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CMT_FIFO_L_BYP0_4", - "INT_INTERFACE_BYP0" - ], - [ - "CMT_FIFO_SE4C3_4", - "INT_INTERFACE_SE4C3" - ], - [ - "CMT_FIFO_NW4END1_4", - "INT_INTERFACE_NW4END1" - ], - [ - "CMT_FIFO_EE4A0_4", - "INT_INTERFACE_EE4A0" - ], - [ - "CMT_FIFO_L_IMUX32_4", - "INT_INTERFACE_IMUX32" - ], - [ - "CMT_FIFO_L_IMUX9_4", - "INT_INTERFACE_IMUX9" - ], - [ - "CMT_FIFO_L_IMUX15_4", - "INT_INTERFACE_IMUX15" - ], - [ - "CMT_FIFO_L_FAN5_4", - "INT_INTERFACE_FAN5" - ], - [ - "CMT_FIFO_EE4A3_4", - "INT_INTERFACE_EE4A3" - ], - [ - "CMT_FIFO_NW2A1_4", - "INT_INTERFACE_NW2A1" - ], - [ - "CMT_FIFO_WW2A0_4", - "INT_INTERFACE_WW2A0" - ], - [ - "CMT_FIFO_L_CLK1_4", - "INT_INTERFACE_CLK1" - ], - [ - "CMT_FIFO_L_BYP3_4", - "INT_INTERFACE_BYP3" - ], - [ - "CMT_FIFO_L_IMUX12_4", - "INT_INTERFACE_IMUX12" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS4_4", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CMT_FIFO_L_IMUX43_4", - "INT_INTERFACE_IMUX43" - ], - [ - "CMT_FIFO_WR1END3_4", - "INT_INTERFACE_WR1END3" - ], - [ - "CMT_FIFO_L_FAN2_4", - "INT_INTERFACE_FAN2" - ], - [ - "CMT_FIFO_SW2A1_4", - "INT_INTERFACE_SW2A1" - ], - [ - "CMT_FIFO_SW4END3_4", - "INT_INTERFACE_SW4END3" - ], - [ - "CMT_FIFO_WW4C0_4", - "INT_INTERFACE_WW4C0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS23_4", - "INT_INTERFACE_LOGIC_OUTS_B23" - ], - [ - "CMT_FIFO_MONITOR_P_4", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CMT_FIFO_L_CLK0_4", - "INT_INTERFACE_CLK0" - ], - [ - "CMT_FIFO_WW2A3_4", - "INT_INTERFACE_WW2A3" - ], - [ - "CMT_FIFO_L_IMUX21_4", - "INT_INTERFACE_IMUX21" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS15_4", - "INT_INTERFACE_LOGIC_OUTS_B15" - ], - [ - "CMT_FIFO_EE4BEG2_4", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CMT_FIFO_NW2A0_4", - "INT_INTERFACE_NW2A0" - ], - [ - "CMT_FIFO_L_BYP6_4", - "INT_INTERFACE_BYP6" - ], - [ - "CMT_FIFO_EL1BEG3_4", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CMT_FIFO_LH11_4", - "INT_INTERFACE_LH11" - ], - [ - "CMT_FIFO_SE4BEG2_4", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CMT_FIFO_WR1END2_4", - "INT_INTERFACE_WR1END2" - ], - [ - "CMT_FIFO_WW4B3_4", - "INT_INTERFACE_WW4B3" - ], - [ - "CMT_FIFO_EE4B2_4", - "INT_INTERFACE_EE4B2" - ], - [ - "CMT_FIFO_WW4B2_4", - "INT_INTERFACE_WW4B2" - ], - [ - "CMT_FIFO_L_IMUX16_4", - "INT_INTERFACE_IMUX16" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS19_4", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "CMT_FIFO_L_IMUX19_4", - "INT_INTERFACE_IMUX19" - ], - [ - "CMT_FIFO_NE4BEG3_4", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CMT_FIFO_NW4A3_4", - "INT_INTERFACE_NW4A3" - ], - [ - "CMT_FIFO_EE2BEG3_4", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CMT_FIFO_L_FAN1_4", - "INT_INTERFACE_FAN1" - ], - [ - "CMT_FIFO_WW4END0_4", - "INT_INTERFACE_WW4END0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS8_4", - "INT_INTERFACE_LOGIC_OUTS_B8" - ], - [ - "CMT_FIFO_WW4B1_4", - "INT_INTERFACE_WW4B1" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS14_4", - "INT_INTERFACE_LOGIC_OUTS_B14" - ], - [ - "CMT_FIFO_L_IMUX2_4", - "INT_INTERFACE_IMUX2" - ], - [ - "CMT_FIFO_EE2A2_4", - "INT_INTERFACE_EE2A2" - ], - [ - "CMT_FIFO_LH1_4", - "INT_INTERFACE_LH1" - ], - [ - "CMT_FIFO_NE4C0_4", - "INT_INTERFACE_NE4C0" - ], - [ - "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", - "INT_INTERFACE_PHASER_TO_IO_OCLK" - ], - [ - "CMT_FIFO_L_IMUX11_4", - "INT_INTERFACE_IMUX11" - ], - [ - "CMT_FIFO_SW2A2_4", - "INT_INTERFACE_SW2A2" - ], - [ - "CMT_FIFO_SW2A0_4", - "INT_INTERFACE_SW2A0" - ], - [ - "CMT_FIFO_NE4C2_4", - "INT_INTERFACE_NE4C2" - ], - [ - "CMT_FIFO_EL1BEG2_4", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CMT_FIFO_EE4A2_4", - "INT_INTERFACE_EE4A2" - ], - [ - "CMT_FIFO_L_IMUX39_4", - "INT_INTERFACE_IMUX39" - ], - [ - "CMT_FIFO_WW2END1_4", - "INT_INTERFACE_WW2END1" + "IOI_PHASER_TO_IO_OCLK_0", + "L_TERM_INT_PHASER_TO_IO_OCLK" ] ] }, @@ -473630,376 +402918,71088 @@ ], "wire_pairs": [ [ - "IOI_IMUX43_0", - "TERM_INT_IMUX43" - ], - [ - "IOI_IMUX11_0", - "TERM_INT_IMUX11" - ], - [ - "IOI_FAN7_0", - "TERM_INT_FAN7" - ], - [ - "IOI_LOGIC_OUTS14_0", - "TERM_INT_LOGIC_OUTS_L_B14" - ], - [ - "IOI_CLK1_0", - "TERM_INT_CLK1" - ], - [ - "IOI_IMUX42_0", - "TERM_INT_IMUX42" - ], - [ - "IOI_IMUX13_0", - "TERM_INT_IMUX13" - ], - [ - "IOI_IMUX37_0", - "TERM_INT_IMUX37" - ], - [ - "IOI_IMUX39_0", - "TERM_INT_IMUX39" - ], - [ - "IOI_IMUX5_0", - "TERM_INT_IMUX5" - ], - [ - "IOI_LOGIC_OUTS11_0", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "IOI_IMUX27_0", - "TERM_INT_IMUX27" - ], - [ - "IOI_IMUX41_0", - "TERM_INT_IMUX41" - ], - [ - "IOI_LOGIC_OUTS23_0", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "IOI_LOGIC_OUTS8_0", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_IMUX1_0", - "TERM_INT_IMUX1" - ], - [ - "IOI_LOGIC_OUTS19_0", - "TERM_INT_LOGIC_OUTS_L_B19" - ], - [ - "IOI_IMUX38_0", - "TERM_INT_IMUX38" - ], - [ - "IOI_IMUX46_0", - "TERM_INT_IMUX46" - ], - [ - "IOI_BYP5_0", - "TERM_INT_BYP5" - ], - [ - "IOI_IMUX7_0", - "TERM_INT_IMUX7" + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" ], [ "IOI_BLOCK_OUTS2_0", "TERM_INT_BLOCK_OUTS_L_B2" ], - [ - "IOI_IMUX3_0", - "TERM_INT_IMUX3" - ], - [ - "IOI_IMUX15_0", - "TERM_INT_IMUX15" - ], - [ - "IOI_FAN1_0", - "TERM_INT_FAN1" - ], - [ - "IOI_IMUX40_0", - "TERM_INT_IMUX40" - ], - [ - "IOI_PHASER_TO_IO_OCLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "IOI_IMUX14_0", - "TERM_INT_IMUX14" - ], - [ - "IOI_IMUX28_0", - "TERM_INT_IMUX28" - ], - [ - "IOI_MONITOR_N", - "TERM_INT_MONITOR_N" - ], - [ - "IOI_IMUX17_0", - "TERM_INT_IMUX17" - ], - [ - "IOI_BYP6_0", - "TERM_INT_BYP6" - ], - [ - "IOI_LOGIC_OUTS18_0", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "IOI_IMUX32_0", - "TERM_INT_IMUX32" - ], - [ - "IOI_CTRL0_0", - "TERM_INT_CTRL0" - ], - [ - "IOI_LOGIC_OUTS0_0", - "TERM_INT_LOGIC_OUTS_L_B0" - ], - [ - "IOI_IMUX12_0", - "TERM_INT_IMUX12" - ], - [ - "IOI_IMUX44_0", - "TERM_INT_IMUX44" - ], - [ - "IOI_FAN5_0", - "TERM_INT_FAN5" - ], - [ - "IOI_IMUX20_0", - "TERM_INT_IMUX20" - ], - [ - "IOI_IMUX35_0", - "TERM_INT_IMUX35" - ], - [ - "IOI_BYP4_0", - "TERM_INT_BYP4" - ], - [ - "IOI_LOGIC_OUTS1_0", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_IMUX25_0", - "TERM_INT_IMUX25" - ], - [ - "IOI_IMUX31_0", - "TERM_INT_IMUX31" - ], - [ - "IOI_IMUX34_0", - "TERM_INT_IMUX34" - ], [ "IOI_BYP0_0", "TERM_INT_BYP0" ], - [ - "IOI_MONITOR_P", - "TERM_INT_MONITOR_P" - ], - [ - "IOI_FAN0_0", - "TERM_INT_FAN0" - ], - [ - "IOI_LOGIC_OUTS20_0", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_IMUX26_0", - "TERM_INT_IMUX26" - ], - [ - "IOI_IMUX6_0", - "TERM_INT_IMUX6" - ], - [ - "IOI_LOGIC_OUTS2_0", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "IOI_IMUX10_0", - "TERM_INT_IMUX10" - ], - [ - "IOI_LOGIC_OUTS7_0", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_BYP7_0", - "TERM_INT_BYP7" - ], - [ - "IOI_IMUX29_0", - "TERM_INT_IMUX29" - ], - [ - "IOI_IMUX4_0", - "TERM_INT_IMUX4" - ], - [ - "IOI_IMUX47_0", - "TERM_INT_IMUX47" - ], - [ - "IOI_IMUX45_0", - "TERM_INT_IMUX45" - ], - [ - "IOI_IMUX33_0", - "TERM_INT_IMUX33" - ], - [ - "IOI_FAN3_0", - "TERM_INT_FAN3" - ], - [ - "IOI_IMUX23_0", - "TERM_INT_IMUX23" - ], - [ - "IOI_LOGIC_OUTS5_0", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_BYP2_0", - "TERM_INT_BYP2" - ], - [ - "IOI_IMUX24_0", - "TERM_INT_IMUX24" - ], - [ - "IOI_LOGIC_OUTS10_0", - "TERM_INT_LOGIC_OUTS_L_B10" - ], - [ - "IOI_CLK0_0", - "TERM_INT_CLK0" - ], - [ - "IOI_IMUX16_0", - "TERM_INT_IMUX16" - ], - [ - "IOI_FAN2_0", - "TERM_INT_FAN2" - ], - [ - "IOI_IMUX0_0", - "TERM_INT_IMUX0" - ], - [ - "IOI_LOGIC_OUTS3_0", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_IMUX21_0", - "TERM_INT_IMUX21" - ], - [ - "IOI_LOGIC_OUTS15_0", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_FAN6_0", - "TERM_INT_FAN6" - ], - [ - "IOI_IMUX30_0", - "TERM_INT_IMUX30" - ], [ "IOI_BYP1_0", "TERM_INT_BYP1" ], [ - "IOI_CTRL1_0", - "TERM_INT_CTRL1" - ], - [ - "LIOI_I2GCLK_TOP0", - "L_TERM_INT_DQS_IOTOPHASER" - ], - [ - "IOI_IMUX9_0", - "TERM_INT_IMUX9" - ], - [ - "IOI_IMUX22_0", - "TERM_INT_IMUX22" - ], - [ - "IOI_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" - ], - [ - "IOI_BLOCK_OUTS0_0", - "TERM_INT_BLOCK_OUTS_L_B0" - ], - [ - "IOI_IMUX2_0", - "TERM_INT_IMUX2" - ], - [ - "IOI_LOGIC_OUTS9_0", - "TERM_INT_LOGIC_OUTS_L_B9" + "IOI_BYP2_0", + "TERM_INT_BYP2" ], [ "IOI_BYP3_0", "TERM_INT_BYP3" ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], + [ + "IOI_CTRL0_0", + "TERM_INT_CTRL0" + ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], [ "IOI_FAN4_0", "TERM_INT_FAN4" ], [ - "IOI_IMUX18_0", - "TERM_INT_IMUX18" + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], + [ + "IOI_FAN6_0", + "TERM_INT_FAN6" + ], + [ + "IOI_FAN7_0", + "TERM_INT_FAN7" + ], + [ + "IOI_IMUX0_0", + "TERM_INT_IMUX0" + ], + [ + "IOI_IMUX1_0", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX2_0", + "TERM_INT_IMUX2" + ], + [ + "IOI_IMUX3_0", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX4_0", + "TERM_INT_IMUX4" + ], + [ + "IOI_IMUX5_0", + "TERM_INT_IMUX5" + ], + [ + "IOI_IMUX6_0", + "TERM_INT_IMUX6" + ], + [ + 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"R_TERM_INT_GTX_LOGIC_OUTS_B16", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B17", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B18", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B19", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B20", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B21", + "VBRK_EXT_LOGIC_OUTS_B21" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B22", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "R_TERM_INT_GTX_LOGIC_OUTS_B23", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] } diff --git a/kintex7/tileconn.json b/kintex7/tileconn.json index 7d1f0da..79f0674 100644 --- a/kintex7/tileconn.json +++ b/kintex7/tileconn.json @@ -1,2017 +1,2153 @@ [ - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "HCLK_L_BOT_UTURN", - "INT_L" - ], - "wire_pairs": [ - [ - "B_TERM_UTURN_INT_LVB_L4", - "LVB_L8" - ], - [ - "B_TERM_UTURN_INT_LVB_L1", - "LVB_L2" - ], - [ - "B_TERM_UTURN_INT_SW6D1", - "SW6D1" - ], - [ - "B_TERM_UTURN_INT_SW6END_N0_3", - "NW6END0" - ], - [ - "B_TERM_UTURN_INT_SE6A1", - "SE6A1" - ], - [ - "B_TERM_UTURN_INT_SS2BEG2", - "NN2A1" - ], - [ - "B_TERM_UTURN_INT_SS6E3", - "NN6END0" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "BYP_BOUNCE_N3_2" - ], - [ - "B_TERM_UTURN_INT_WR1BEG0", - "WR1BEG0" - ], - [ - "B_TERM_UTURN_INT_SS6D3", - "NN6E0" - ], - [ - "B_TERM_UTURN_INT_SL1BEG0", - "SL1BEG0" - ], - [ - "B_TERM_UTURN_INT_SS6C3", - "NN6D0" - ], - [ - "B_TERM_UTURN_INT_SE2BEG3", - "NE2A0" - ], - [ - "B_TERM_UTURN_INT_SS6D2", - "NN6E1" - ], - [ - "B_TERM_UTURN_INT_SW6B2", - "SW6B2" - ], - [ - "B_TERM_UTURN_INT_SW6B2", - "NW6C1" - ], - [ - "B_TERM_UTURN_INT_SS2BEG1", - "SS2BEG1" - ], - [ - "B_TERM_UTURN_INT_SW6B0", - "SW6B0" - ], - [ - "B_TERM_UTURN_INT_SR1BEG2", - "SR1BEG2" - ], - [ - "B_TERM_UTURN_INT_LVB_L1", - "LVB_L11" - ], - [ - "B_TERM_UTURN_INT_SS6D1", - "SS6D1" - ], - [ - "B_TERM_UTURN_INT_SS2BEG1", - "NN2A2" - ], - [ - "B_TERM_UTURN_INT_SE6C1", - "NE6D2" - ], - [ - "B_TERM_UTURN_INT_ER1BEG0", - "ER1BEG0" - ], - [ - "B_TERM_UTURN_INT_SW6C2", - "SW6C2" - ], - [ - "B_TERM_UTURN_INT_SW6C2", - "NW6D1" - ], - [ - "B_TERM_UTURN_INT_SS6B1", - "SS6B1" - ], - [ - "B_TERM_UTURN_INT_SR1BEG3", - "NL1END0" - ], - [ - "B_TERM_UTURN_INT_LVB_L2", - "LVB_L10" - ], - [ - "B_TERM_UTURN_INT_SS6C3", - "SS6C3" - ], - [ - "B_TERM_UTURN_INT_SW6B0", - "NW6C3" - ], - [ - "B_TERM_UTURN_INT_LV_L3", - "LV_L16" - ], - [ - "B_TERM_UTURN_INT_SS6E2", - "SS6E2" - ], - [ - "B_TERM_UTURN_INT_LVB_L5", - "LVB_L6" - ], - [ - "B_TERM_UTURN_INT_LVB_L5", - "LVB_L7" - ], - [ - "B_TERM_UTURN_INT_SS6D0", - "SS6D0" - ], - [ - "B_TERM_UTURN_INT_SS6B3", - "SS6B3" - ], - [ - "B_TERM_UTURN_INT_LVB_L0", - "LVB_L1" - ], - [ - "B_TERM_UTURN_INT_SW6END_N0_3", - "SW6END_N0_3" - ], - [ - "B_TERM_UTURN_INT_SE6C3", - "NE6D0" - ], - [ - "B_TERM_UTURN_INT_SS6A2", - "NN6B1" - ], - [ - "B_TERM_UTURN_INT_LVB_L3", - "LVB_L9" - ], - [ - "B_TERM_UTURN_INT_SE6D0", - "NE6E3" - ], - [ - "B_TERM_UTURN_INT_SW6A2", - "NW6B1" - ], - [ - "B_TERM_UTURN_INT_SE6B3", - "SE6B3" - ], - [ - "B_TERM_UTURN_INT_SS6B2", - "NN6C1" - ], - [ - "B_TERM_UTURN_INT_SE6D1", - "SE6D1" - ], - [ - "B_TERM_UTURN_INT_SE6C2", - "SE6C2" - ], - [ - "B_TERM_UTURN_INT_SE6D3", - "NE6E0" - ], - [ - "B_TERM_UTURN_INT_SE2BEG2", - "SE2BEG2" - ], - [ - "B_TERM_UTURN_INT_SS2A1", - "NN2END2" - ], - [ - "B_TERM_UTURN_INT_SW2BEG3", - "NW2A0" - ], - [ - "B_TERM_UTURN_INT_SS6E3", - "SS6E3" - ], - [ - "HCLK_LEAF_CLK_B_TOPL3", - "GCLK_L_B9" - ], - [ - "B_TERM_UTURN_INT_SE6D2", - "NE6E1" - ], - [ - "B_TERM_UTURN_INT_SS2BEG0", - "SS2BEG0" - ], - [ - "B_TERM_UTURN_INT_SS6BEG1", - "SS6BEG1" - ], - [ - "B_TERM_UTURN_INT_SS2A3", - "NN2END0" - ], - [ - "B_TERM_UTURN_INT_SE6D0", - "SE6D0" - ], - [ - "B_TERM_UTURN_INT_SL1BEG2", - "SL1BEG2" - ], - [ - "B_TERM_UTURN_INT_SS6A3", - "NN6B0" - ], - [ - "B_TERM_UTURN_INT_SS6B0", - "NN6C3" - ], - [ - "B_TERM_UTURN_INT_LV_L6", - "LV_L6" - ], - [ - "B_TERM_UTURN_INT_SL1BEG2", - "NR1END1" - ], - [ - "B_TERM_UTURN_INT_SS6A2", - "SS6A2" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE0", - "FAN_BOUNCE0" - ], - [ - "B_TERM_UTURN_INT_LV_L2", - "LV_L2" - ], - [ - "B_TERM_UTURN_INT_SS6E1", - "SS6E1" - ], - [ - "B_TERM_UTURN_INT_SE2BEG0", - "SE2BEG0" - ], - [ - "B_TERM_UTURN_INT_SE6D2", - "SE6D2" - ], - [ - "B_TERM_UTURN_INT_SS6B1", - "NN6C2" - ], - [ - "B_TERM_UTURN_INT_SE6C2", - "NE6D1" - ], - [ - "HCLK_LEAF_CLK_B_TOPL2", - "GCLK_L_B8" - ], - [ - "B_TERM_UTURN_INT_LV_L4", - "LV_L15" - ], - [ - "B_TERM_UTURN_INT_ER1END_N3_3", - "EL1END0" - ], - [ - "B_TERM_UTURN_INT_SS6C1", - "NN6D2" - ], - [ - "B_TERM_UTURN_INT_SL1BEG3", - "SL1BEG3" - ], - [ - "B_TERM_UTURN_INT_SS6B3", - "NN6C0" - ], - [ - "B_TERM_UTURN_INT_LV_L7", - "LV_L7" - ], - [ - "B_TERM_UTURN_INT_LV_L5", - "LV_L5" - ], - [ - "B_TERM_UTURN_INT_LV_L8", - "LV_L8" - ], - [ - "B_TERM_UTURN_INT_SS6D1", - "NN6E2" - ], - [ - "B_TERM_UTURN_INT_LVB_L2", - "LVB_L3" - ], - [ - "B_TERM_UTURN_INT_SW2BEG1", - "SW2BEG1" - ], - [ - "B_TERM_UTURN_INT_SS6C0", - "SS6C0" - ], - [ - "B_TERM_UTURN_INT_SS6D2", - "SS6D2" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "FAN_BOUNCE4" - ], - [ - "B_TERM_UTURN_INT_SS6A3", - "SS6A3" - ], - [ - "B_TERM_UTURN_INT_SW6A3", - "SW6A3" - ], - [ - "B_TERM_UTURN_INT_LV_L18", - "LV_L18" - ], - [ - "B_TERM_UTURN_INT_SS6C0", - "NN6D3" - ], - [ - "B_TERM_UTURN_INT_SS6A0", - "NN6B3" - ], - [ - "B_TERM_UTURN_INT_SS6C2", - "NN6D1" - ], - [ - "B_TERM_UTURN_INT_SE6D1", - "NE6E2" - ], - [ - "B_TERM_UTURN_INT_WR1END0", - "WR1END0" - ], - [ - "B_TERM_UTURN_INT_SL1BEG0", - "NR1END3" - ], - [ - "B_TERM_UTURN_INT_SS6BEG0", - "SS6BEG0" - ], - [ - "B_TERM_UTURN_INT_SE6A3", - "NE6B0" - ], - [ - "B_TERM_UTURN_INT_SE6C1", - "SE6C1" - ], - [ - "B_TERM_UTURN_INT_SS2A0", - "SS2A0" - ], - [ - "B_TERM_UTURN_INT_SW2BEG0", - "SW2BEG0" - ], - [ - "B_TERM_UTURN_INT_LV_L4", - "LV_L4" - ], - [ - "B_TERM_UTURN_INT_SW6D1", - "NW6E2" - ], - [ - "B_TERM_UTURN_INT_SW6D3", - "SW6D3" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE0", - "BYP_BOUNCE_N3_7" - ], - [ - "B_TERM_UTURN_INT_SL1BEG1", - "NR1END2" - ], - [ - "B_TERM_UTURN_INT_SW6B1", - "NW6C2" - ], - [ - "B_TERM_UTURN_INT_SW6D2", - "SW6D2" - ], - [ - "B_TERM_UTURN_INT_LV_L2", - "LV_L17" - ], - [ - "B_TERM_UTURN_INT_SS2BEG3", - "SS2BEG3" - ], - [ - "B_TERM_UTURN_INT_SS6A1", - "SS6A1" - ], - [ - "B_TERM_UTURN_INT_SE2BEG0", - "NE2A3" - ], - [ - "B_TERM_UTURN_INT_SW2BEG1", - "NW2A2" - ], - [ - "B_TERM_UTURN_INT_SE6B2", - "NE6C1" - ], - [ - "B_TERM_UTURN_INT_SL1BEG1", - "SL1BEG1" - ], - [ - "B_TERM_UTURN_INT_SW6D2", - "NW6E1" - ], - [ - "B_TERM_UTURN_INT_LV_L6", - "LV_L13" - ], - [ - "B_TERM_UTURN_INT_SW6B3", - "SW6B3" - ], - [ - "B_TERM_UTURN_INT_SS2BEG3", - "NN2A0" - ], - [ - "B_TERM_UTURN_INT_LV_L18", - "LV_L1" - ], - [ - "B_TERM_UTURN_INT_SE6C3", - "SE6C3" - ], - [ - "B_TERM_UTURN_INT_SE6B1", - "NE6C2" - ], - [ - "B_TERM_UTURN_INT_SW6A0", - "NW6B3" - ], - [ - "B_TERM_UTURN_INT_SS2A3", - "SS2A3" - ], - [ - "B_TERM_UTURN_INT_SE6A2", - "SE6A2" - ], - [ - "B_TERM_UTURN_INT_SS6BEG2", - "SS6BEG2" - ], - [ - "B_TERM_UTURN_INT_SW6C3", - "SW6C3" - ], - [ - "B_TERM_UTURN_INT_LV_L3", - "LV_L3" - ], - [ - "B_TERM_UTURN_INT_SW2BEG2", - "NW2A1" - ], - [ - "B_TERM_UTURN_INT_SS6BEG3", - "SS6BEG3" - ], - [ - "B_TERM_UTURN_INT_SS6B0", - "SS6B0" - ], - [ - "B_TERM_UTURN_INT_SW6A2", - "SW6A2" - ], - [ - "B_TERM_UTURN_INT_SE6A0", - "NE6B3" - ], - [ - "B_TERM_UTURN_INT_SW6A1", - "SW6A1" - ], - [ - "B_TERM_UTURN_INT_SW6A3", - "NW6B0" - ], - [ - "B_TERM_UTURN_INT_SE2BEG1", - "SE2BEG1" - ], - [ - "B_TERM_UTURN_INT_SE6A0", - "SE6A0" - ], - [ - "B_TERM_UTURN_INT_SW6C3", - "NW6D0" - ], - [ - "B_TERM_UTURN_INT_LVB_L4", - "LVB_L5" - ], - [ - "B_TERM_UTURN_INT_SW2BEG3", - "SW2BEG3" - ], - [ - "B_TERM_UTURN_INT_SW2BEG0", - "NW2A3" - ], - [ - "HCLK_LEAF_CLK_B_TOPL4", - "GCLK_L_B10" - ], - [ - "B_TERM_UTURN_INT_SE6C0", - "NE6D3" - ], - [ - "B_TERM_UTURN_INT_SW6C1", - "SW6C1" - ], - [ - "B_TERM_UTURN_INT_SS6C2", - "SS6C2" - ], - [ - "B_TERM_UTURN_INT_SW6B3", - "NW6C0" - ], - [ - "B_TERM_UTURN_INT_SW6C0", - "NW6D3" - ], - [ - "B_TERM_UTURN_INT_SS2BEG2", - "SS2BEG2" - ], - [ - "B_TERM_UTURN_INT_SS2BEG0", - "NN2A3" - ], - [ - "B_TERM_UTURN_INT_SW6A1", - "NW6B2" - ], - [ - "B_TERM_UTURN_INT_SS6E0", - "SS6E0" - ], - [ - "B_TERM_UTURN_INT_LV_L5", - "LV_L14" - ], - [ - "B_TERM_UTURN_INT_LV_L9", - "LV_L9" - ], - [ - "B_TERM_UTURN_INT_SW2BEG2", - "SW2BEG2" - ], - [ - "B_TERM_UTURN_INT_SS2A0", - "NN2END3" - ], - [ - "B_TERM_UTURN_INT_SS2A2", - "SS2A2" - ], - [ - "B_TERM_UTURN_INT_SS6D0", - "NN6E3" - ], - [ - "B_TERM_UTURN_INT_SE6C0", - "SE6C0" - ], - [ - "B_TERM_UTURN_INT_SS6A0", - "SS6A0" - ], - [ - "B_TERM_UTURN_INT_SE6B3", - "NE6C0" - ], - [ - "B_TERM_UTURN_INT_SS2A2", - "NN2END1" - ], - [ - "B_TERM_UTURN_INT_WR1END0", - "WL1END_N1_3" - ], - [ - "B_TERM_UTURN_INT_SS6E0", - "NN6END3" - ], - [ - "B_TERM_UTURN_INT_SW6D3", - "NW6E0" - ], - [ - "B_TERM_UTURN_INT_SS6BEG3", - "NN6A0" - ], - [ - "B_TERM_UTURN_INT_LV_L7", - "LV_L12" - ], - [ - "B_TERM_UTURN_INT_ER1BEG0", - "EL1BEG_N3" - ], - [ - "B_TERM_UTURN_INT_WR1BEG0", - "WL1BEG_N3" - ], - [ - "B_TERM_UTURN_INT_SE6A1", - "NE6B2" - ], - [ - "B_TERM_UTURN_INT_SE6B1", - "SE6B1" - ], - [ - "B_TERM_UTURN_INT_SW6D0", - "NW6E3" - ], - [ - "B_TERM_UTURN_INT_SE6B0", - "SE6B0" - ], - [ - "B_TERM_UTURN_INT_SE6A2", - "NE6B1" - ], - [ - "B_TERM_UTURN_INT_SR1BEG2", - "NL1END1" - ], - [ - "B_TERM_UTURN_INT_LVB_L3", - "LVB_L4" - ], - [ - "HCLK_LEAF_CLK_B_TOPL0", - "GCLK_L_B6" - ], - [ - "B_TERM_UTURN_INT_SW6C0", - "SW6C0" - ], - [ - "B_TERM_UTURN_INT_SW6B1", - "SW6B1" - ], - [ - "B_TERM_UTURN_INT_SS6BEG1", - "NN6A2" - ], - [ - "B_TERM_UTURN_INT_SR1BEG3", - "SR1BEG3" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "FAN_BOUNCE6" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "FAN_BOUNCE2" - ], - [ - "B_TERM_UTURN_INT_SR1BEG1", - "SR1BEG1" - ], - [ - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "BYP_BOUNCE_N3_6" - ], - [ - "B_TERM_UTURN_INT_SE6B2", - "SE6B2" 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"CMT_TOP_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_LH3_2", - "VBRK_LH3" - ], - [ - "CMT_TOP_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_EE4A1_2", - "VBRK_EE4A1" - ] - ] - }, - { - "grid_deltas": [ - 1, 0 ], "tile_types": [ - "HCLK_BRAM", - "HCLK_INT_INTERFACE" + "BRAM_INT_INTERFACE_L", + "BRAM_L" ], "wire_pairs": [ [ - "HCLK_BRAM_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_0" ], [ - "HCLK_BRAM_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN6" + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_0" ], [ - "HCLK_BRAM_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_0" ], [ - "HCLK_BRAM_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN11" + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_0" ], [ - "HCLK_BRAM_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN5" + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_0" ], [ - "HCLK_BRAM_CK_IN2", - "HCLK_INT_INTERFACE_CK_IN2" + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_0" ], [ - "HCLK_BRAM_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_0" ], [ - "HCLK_BRAM_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN12" + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_0" ], [ - "HCLK_BRAM_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_0" ], [ - "HCLK_BRAM_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN0" + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_0" ], [ - "HCLK_BRAM_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_0" ], [ - "HCLK_BRAM_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN4" + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_0" ], [ - "HCLK_BRAM_CK_IN1", - "HCLK_INT_INTERFACE_CK_IN1" + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_0" ], [ - "HCLK_BRAM_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_0" ], [ - "HCLK_BRAM_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_0" ], [ - "HCLK_BRAM_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN10" + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_0" ], [ - "HCLK_BRAM_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN9" + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_0" ], [ - "HCLK_BRAM_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_0" ], [ - "HCLK_BRAM_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN13" + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_0" ], [ - "HCLK_BRAM_CK_IN3", - "HCLK_INT_INTERFACE_CK_IN3" + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_0" ], [ - "HCLK_BRAM_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_0" ], [ - "HCLK_BRAM_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_0" ], [ - "HCLK_BRAM_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_0" ], [ - "HCLK_BRAM_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN8" + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_0" ], [ - "HCLK_BRAM_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_0" ], [ - "HCLK_BRAM_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_0" ], [ - "HCLK_BRAM_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_0" ], [ - "HCLK_BRAM_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_0" ], [ - "HCLK_BRAM_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN7" + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_0" ], [ - "HCLK_BRAM_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_0" + ], + [ + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX0", + "BRAM_IMUX0_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX1", + "BRAM_IMUX1_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX2", + "BRAM_IMUX2_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX3", + "BRAM_IMUX3_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX4", + "BRAM_IMUX4_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX5", + "BRAM_IMUX5_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX6", + "BRAM_IMUX6_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX7", + "BRAM_IMUX7_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX8", + "BRAM_IMUX8_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX9", + "BRAM_IMUX9_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX10", + "BRAM_IMUX10_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX11", + "BRAM_IMUX11_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX12", + "BRAM_IMUX12_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX13", + "BRAM_IMUX13_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX14", + "BRAM_IMUX14_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX15", + "BRAM_IMUX15_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX16", + "BRAM_IMUX16_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX17", + "BRAM_IMUX17_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX18", + "BRAM_IMUX18_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX19", + "BRAM_IMUX19_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX20", + "BRAM_IMUX20_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX21", + "BRAM_IMUX21_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX22", + "BRAM_IMUX22_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX23", + "BRAM_IMUX23_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX24", + "BRAM_IMUX24_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX25", + "BRAM_IMUX25_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX26", + "BRAM_IMUX26_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX27", + "BRAM_IMUX27_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX28", + "BRAM_IMUX28_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX29", + "BRAM_IMUX29_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX30", + "BRAM_IMUX30_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX31", + "BRAM_IMUX31_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX32", + "BRAM_IMUX32_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX33", + "BRAM_IMUX33_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX34", + "BRAM_IMUX34_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX35", + "BRAM_IMUX35_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX36", + "BRAM_IMUX36_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX37", + "BRAM_IMUX37_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX38", + "BRAM_IMUX38_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX39", + "BRAM_IMUX39_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX40", + "BRAM_IMUX40_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX41", + "BRAM_IMUX41_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX42", + "BRAM_IMUX42_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX43", + "BRAM_IMUX43_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX44", + "BRAM_IMUX44_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX45", + "BRAM_IMUX45_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX46", + "BRAM_IMUX46_UTURN_0" + ], + [ + "INT_INTERFACE_BRAM_UTURN_IMUX47", + "BRAM_IMUX47_UTURN_0" + ], + [ + "INT_INTERFACE_BYP0", + "BRAM_BYP0_0" + ], + [ + "INT_INTERFACE_BYP1", + "BRAM_BYP1_0" + ], + [ + "INT_INTERFACE_BYP2", + "BRAM_BYP2_0" + ], + [ + "INT_INTERFACE_BYP3", + "BRAM_BYP3_0" + ], + [ + "INT_INTERFACE_BYP4", + "BRAM_BYP4_0" + ], + [ + "INT_INTERFACE_BYP5", + "BRAM_BYP5_0" + ], + [ + "INT_INTERFACE_BYP6", + "BRAM_BYP6_0" + ], + [ + "INT_INTERFACE_BYP7", + "BRAM_BYP7_0" + ], + [ + "INT_INTERFACE_CLK0", + "BRAM_CLK0_0" + ], + [ + "INT_INTERFACE_CLK1", + "BRAM_CLK1_0" + ], + [ + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_0" + ], + [ + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_0" + ], + [ + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_0" + ], + [ + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_0" + ], 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"BRAM_EL1BEG2_1" + ], + [ + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_1" + ], + [ + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_1" + ], + [ + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_1" + ], + [ + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_1" + ], + [ + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_1" + ], + [ + "INT_INTERFACE_FAN0", + "BRAM_FAN0_1" + ], + [ + "INT_INTERFACE_FAN1", + "BRAM_FAN1_1" + ], + [ + "INT_INTERFACE_FAN2", + "BRAM_FAN2_1" + ], + [ + "INT_INTERFACE_FAN3", + "BRAM_FAN3_1" + ], + [ + "INT_INTERFACE_FAN4", + "BRAM_FAN4_1" + ], + [ + "INT_INTERFACE_FAN5", + "BRAM_FAN5_1" + ], + [ + "INT_INTERFACE_FAN6", + "BRAM_FAN6_1" + ], + [ + "INT_INTERFACE_FAN7", + "BRAM_FAN7_1" + ], + [ + "INT_INTERFACE_LH1", + "BRAM_LH1_1" + ], + [ + "INT_INTERFACE_LH2", + "BRAM_LH2_1" + ], + [ + "INT_INTERFACE_LH3", + "BRAM_LH3_1" + ], + [ + "INT_INTERFACE_LH4", + "BRAM_LH4_1" + ], + [ + "INT_INTERFACE_LH5", + "BRAM_LH5_1" + ], + [ + "INT_INTERFACE_LH6", + "BRAM_LH6_1" + ], + [ + "INT_INTERFACE_LH7", + "BRAM_LH7_1" + ], + [ + "INT_INTERFACE_LH8", + "BRAM_LH8_1" + ], + [ + "INT_INTERFACE_LH9", + "BRAM_LH9_1" + ], + [ + "INT_INTERFACE_LH10", + "BRAM_LH10_1" + ], + [ + "INT_INTERFACE_LH11", + "BRAM_LH11_1" + ], + [ + "INT_INTERFACE_LH12", + "BRAM_LH12_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "BRAM_LOGIC_OUTS_B0_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "BRAM_LOGIC_OUTS_B1_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "BRAM_LOGIC_OUTS_B2_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "BRAM_LOGIC_OUTS_B3_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "BRAM_LOGIC_OUTS_B4_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "BRAM_LOGIC_OUTS_B5_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "BRAM_LOGIC_OUTS_B6_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "BRAM_LOGIC_OUTS_B7_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "BRAM_LOGIC_OUTS_B8_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "BRAM_LOGIC_OUTS_B9_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "BRAM_LOGIC_OUTS_B10_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "BRAM_LOGIC_OUTS_B11_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "BRAM_LOGIC_OUTS_B12_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "BRAM_LOGIC_OUTS_B13_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "BRAM_LOGIC_OUTS_B14_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "BRAM_LOGIC_OUTS_B15_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "BRAM_LOGIC_OUTS_B16_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "BRAM_LOGIC_OUTS_B17_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "BRAM_LOGIC_OUTS_B18_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "BRAM_LOGIC_OUTS_B19_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "BRAM_LOGIC_OUTS_B20_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "BRAM_LOGIC_OUTS_B21_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "BRAM_LOGIC_OUTS_B22_1" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "BRAM_LOGIC_OUTS_B23_1" + ], + [ + "INT_INTERFACE_MONITOR_N", + "BRAM_MONITOR_N_1" + ], + [ + "INT_INTERFACE_MONITOR_P", + "BRAM_MONITOR_P_1" + ], + [ + "INT_INTERFACE_NE2A0", + "BRAM_NE2A0_1" + ], + [ + "INT_INTERFACE_NE2A1", + "BRAM_NE2A1_1" + ], + [ + "INT_INTERFACE_NE2A2", + "BRAM_NE2A2_1" + ], + [ + "INT_INTERFACE_NE2A3", + "BRAM_NE2A3_1" + ], + [ + "INT_INTERFACE_NE4BEG0", + "BRAM_NE4BEG0_1" + ], + [ + "INT_INTERFACE_NE4BEG1", + "BRAM_NE4BEG1_1" + ], + [ + "INT_INTERFACE_NE4BEG2", + "BRAM_NE4BEG2_1" + ], + [ + "INT_INTERFACE_NE4BEG3", + "BRAM_NE4BEG3_1" + ], + [ + "INT_INTERFACE_NE4C0", + "BRAM_NE4C0_1" + ], + [ + "INT_INTERFACE_NE4C1", + "BRAM_NE4C1_1" + ], + [ + "INT_INTERFACE_NE4C2", + "BRAM_NE4C2_1" + ], + [ + "INT_INTERFACE_NE4C3", + "BRAM_NE4C3_1" + ], + [ + "INT_INTERFACE_NW2A0", + "BRAM_NW2A0_1" + ], + [ + "INT_INTERFACE_NW2A1", + "BRAM_NW2A1_1" + ], + [ + "INT_INTERFACE_NW2A2", + "BRAM_NW2A2_1" + ], + [ + "INT_INTERFACE_NW2A3", + "BRAM_NW2A3_1" + ], + [ + "INT_INTERFACE_NW4A0", + "BRAM_NW4A0_1" + ], + [ + "INT_INTERFACE_NW4A1", + "BRAM_NW4A1_1" + ], + [ + "INT_INTERFACE_NW4A2", + "BRAM_NW4A2_1" + ], + [ + "INT_INTERFACE_NW4A3", + "BRAM_NW4A3_1" + ], + [ + "INT_INTERFACE_NW4END0", + "BRAM_NW4END0_1" + ], + [ + "INT_INTERFACE_NW4END1", + "BRAM_NW4END1_1" + ], + [ + "INT_INTERFACE_NW4END2", + "BRAM_NW4END2_1" + ], + [ + "INT_INTERFACE_NW4END3", + "BRAM_NW4END3_1" + ], + [ + "INT_INTERFACE_SE2A0", + "BRAM_SE2A0_1" + ], + [ + "INT_INTERFACE_SE2A1", + "BRAM_SE2A1_1" + ], + [ + "INT_INTERFACE_SE2A2", + "BRAM_SE2A2_1" + ], + [ + "INT_INTERFACE_SE2A3", + "BRAM_SE2A3_1" + ], + [ + "INT_INTERFACE_SE4BEG0", + "BRAM_SE4BEG0_1" + ], + [ + "INT_INTERFACE_SE4BEG1", + "BRAM_SE4BEG1_1" + ], + [ + "INT_INTERFACE_SE4BEG2", + "BRAM_SE4BEG2_1" + ], + [ + "INT_INTERFACE_SE4BEG3", + "BRAM_SE4BEG3_1" + ], + [ + "INT_INTERFACE_SE4C0", + "BRAM_SE4C0_1" + ], + [ + "INT_INTERFACE_SE4C1", + "BRAM_SE4C1_1" + ], + [ + "INT_INTERFACE_SE4C2", + "BRAM_SE4C2_1" + ], + [ + "INT_INTERFACE_SE4C3", + "BRAM_SE4C3_1" + ], + [ + "INT_INTERFACE_SW2A0", + "BRAM_SW2A0_1" + ], + [ + "INT_INTERFACE_SW2A1", + "BRAM_SW2A1_1" + ], + [ + "INT_INTERFACE_SW2A2", + "BRAM_SW2A2_1" + ], + [ + "INT_INTERFACE_SW2A3", + "BRAM_SW2A3_1" + ], + [ + "INT_INTERFACE_SW4A0", + "BRAM_SW4A0_1" + ], + [ + "INT_INTERFACE_SW4A1", + "BRAM_SW4A1_1" + ], + [ + "INT_INTERFACE_SW4A2", + "BRAM_SW4A2_1" + ], + [ + "INT_INTERFACE_SW4A3", + "BRAM_SW4A3_1" + ], + [ + "INT_INTERFACE_SW4END0", + "BRAM_SW4END0_1" + ], + [ + "INT_INTERFACE_SW4END1", + "BRAM_SW4END1_1" + ], + [ + "INT_INTERFACE_SW4END2", + "BRAM_SW4END2_1" + ], + [ + "INT_INTERFACE_SW4END3", + "BRAM_SW4END3_1" + ], + [ + "INT_INTERFACE_WL1END0", + "BRAM_WL1END0_1" + ], + [ + "INT_INTERFACE_WL1END1", + "BRAM_WL1END1_1" + ], + [ + "INT_INTERFACE_WL1END2", + "BRAM_WL1END2_1" + ], + [ + "INT_INTERFACE_WL1END3", + "BRAM_WL1END3_1" + ], + [ + "INT_INTERFACE_WR1END0", + "BRAM_WR1END0_1" + ], + [ + "INT_INTERFACE_WR1END1", + "BRAM_WR1END1_1" + ], + [ + "INT_INTERFACE_WR1END2", + "BRAM_WR1END2_1" + ], + [ + "INT_INTERFACE_WR1END3", + "BRAM_WR1END3_1" + ], + [ + "INT_INTERFACE_WW2A0", + "BRAM_WW2A0_1" + ], + [ + "INT_INTERFACE_WW2A1", + "BRAM_WW2A1_1" + ], + [ + "INT_INTERFACE_WW2A2", + "BRAM_WW2A2_1" + ], + [ + "INT_INTERFACE_WW2A3", + "BRAM_WW2A3_1" + ], + [ + "INT_INTERFACE_WW2END0", + "BRAM_WW2END0_1" + ], + [ + "INT_INTERFACE_WW2END1", + "BRAM_WW2END1_1" + ], + [ + "INT_INTERFACE_WW2END2", + "BRAM_WW2END2_1" + ], + [ + "INT_INTERFACE_WW2END3", + "BRAM_WW2END3_1" + ], + [ + "INT_INTERFACE_WW4A0", + "BRAM_WW4A0_1" + ], + [ + "INT_INTERFACE_WW4A1", + "BRAM_WW4A1_1" + ], + [ + "INT_INTERFACE_WW4A2", + "BRAM_WW4A2_1" + ], + [ + "INT_INTERFACE_WW4A3", + "BRAM_WW4A3_1" + ], + [ + "INT_INTERFACE_WW4B0", + "BRAM_WW4B0_1" + ], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_1" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_1" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_1" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_1" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_1" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_1" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_1" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_1" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_1" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_1" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_1" ] ] }, @@ -2021,901 +2157,9489 @@ 2 ], "tile_types": [ - "CMT_FIFO_R", - "INT_INTERFACE_R" + "BRAM_INT_INTERFACE_L", + "BRAM_L" ], "wire_pairs": [ [ - "CMT_FIFO_L_IMUX6_4", - "INT_INTERFACE_IMUX6" + "INT_INTERFACE_BRAM_IMUX0", + "BRAM_IMUX0_2" ], [ - "CMT_FIFO_L_IMUX35_4", - "INT_INTERFACE_IMUX35" + "INT_INTERFACE_BRAM_IMUX1", + "BRAM_IMUX1_2" ], [ - "FIFO_DQS_IOTOPHASER_22", - "L_INT_INTER_DQS_IOTOPHASER" + "INT_INTERFACE_BRAM_IMUX2", + "BRAM_IMUX2_2" ], [ - "CMT_FIFO_WW2END3_4", - "INT_INTERFACE_WW2END3" + "INT_INTERFACE_BRAM_IMUX3", + "BRAM_IMUX3_2" ], [ - "CMT_FIFO_NW4A2_4", - "INT_INTERFACE_NW4A2" + "INT_INTERFACE_BRAM_IMUX4", + "BRAM_IMUX4_2" ], [ - "CMT_FIFO_NE4BEG0_4", - "INT_INTERFACE_NE4BEG0" + "INT_INTERFACE_BRAM_IMUX5", + "BRAM_IMUX5_2" ], [ - "CMT_FIFO_WW4A0_4", - "INT_INTERFACE_WW4A0" + "INT_INTERFACE_BRAM_IMUX6", + "BRAM_IMUX6_2" ], [ - "CMT_FIFO_WL1END3_4", - "INT_INTERFACE_WL1END3" + "INT_INTERFACE_BRAM_IMUX7", + "BRAM_IMUX7_2" ], [ - "CMT_FIFO_EE2A0_4", - "INT_INTERFACE_EE2A0" + "INT_INTERFACE_BRAM_IMUX8", + "BRAM_IMUX8_2" ], [ - "CMT_FIFO_L_IMUX45_4", - "INT_INTERFACE_IMUX45" + "INT_INTERFACE_BRAM_IMUX9", + "BRAM_IMUX9_2" ], [ - "CMT_FIFO_WW4C2_4", - "INT_INTERFACE_WW4C2" + "INT_INTERFACE_BRAM_IMUX10", + "BRAM_IMUX10_2" ], [ - "CMT_FIFO_L_BYP3_4", - "INT_INTERFACE_BYP3" + "INT_INTERFACE_BRAM_IMUX11", + "BRAM_IMUX11_2" ], [ - "CMT_FIFO_WW2A2_4", - "INT_INTERFACE_WW2A2" + "INT_INTERFACE_BRAM_IMUX12", + "BRAM_IMUX12_2" ], [ - "CMT_FIFO_L_IMUX44_4", - "INT_INTERFACE_IMUX44" + "INT_INTERFACE_BRAM_IMUX13", + "BRAM_IMUX13_2" ], [ - "CMT_FIFO_L_CTRL0_4", - "INT_INTERFACE_CTRL0" + "INT_INTERFACE_BRAM_IMUX14", + "BRAM_IMUX14_2" ], [ - "CMT_FIFO_L_IMUX18_4", - "INT_INTERFACE_IMUX18" + "INT_INTERFACE_BRAM_IMUX15", + "BRAM_IMUX15_2" ], [ - "CMT_FIFO_SW2A0_4", - "INT_INTERFACE_SW2A0" + "INT_INTERFACE_BRAM_IMUX16", + "BRAM_IMUX16_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS12_4", - "INT_INTERFACE_LOGIC_OUTS_B12" + "INT_INTERFACE_BRAM_IMUX17", + "BRAM_IMUX17_2" ], [ - "CMT_FIFO_WR1END1_4", - "INT_INTERFACE_WR1END1" + "INT_INTERFACE_BRAM_IMUX18", + "BRAM_IMUX18_2" ], [ - "CMT_FIFO_WR1END0_4", - "INT_INTERFACE_WR1END0" + "INT_INTERFACE_BRAM_IMUX19", + "BRAM_IMUX19_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS22_4", - "INT_INTERFACE_LOGIC_OUTS_B22" + "INT_INTERFACE_BRAM_IMUX20", + "BRAM_IMUX20_2" ], [ - "CMT_FIFO_SW4END1_4", - "INT_INTERFACE_SW4END1" + "INT_INTERFACE_BRAM_IMUX21", + "BRAM_IMUX21_2" ], [ - "CMT_FIFO_SE4BEG2_4", - "INT_INTERFACE_SE4BEG2" + "INT_INTERFACE_BRAM_IMUX22", + "BRAM_IMUX22_2" ], [ - "CMT_FIFO_L_IMUX28_4", - "INT_INTERFACE_IMUX28" + "INT_INTERFACE_BRAM_IMUX23", + "BRAM_IMUX23_2" ], [ - "CMT_FIFO_PHASER_TO_IO_ICLK_4", - "INT_INTERFACE_PHASER_TO_IO_ICLK" + "INT_INTERFACE_BRAM_IMUX24", + "BRAM_IMUX24_2" ], [ - "CMT_FIFO_WW2END1_4", - "INT_INTERFACE_WW2END1" + "INT_INTERFACE_BRAM_IMUX25", + "BRAM_IMUX25_2" ], [ - "CMT_FIFO_L_IMUX3_4", - "INT_INTERFACE_IMUX3" + "INT_INTERFACE_BRAM_IMUX26", + "BRAM_IMUX26_2" ], [ - "CMT_FIFO_L_FAN4_4", - "INT_INTERFACE_FAN4" + "INT_INTERFACE_BRAM_IMUX27", + "BRAM_IMUX27_2" ], [ - "CMT_FIFO_EE2A2_4", - "INT_INTERFACE_EE2A2" + "INT_INTERFACE_BRAM_IMUX28", + "BRAM_IMUX28_2" ], [ - "CMT_FIFO_L_IMUX42_4", - "INT_INTERFACE_IMUX42" + "INT_INTERFACE_BRAM_IMUX29", + "BRAM_IMUX29_2" ], [ - "CMT_FIFO_L_FAN6_4", - "INT_INTERFACE_FAN6" + "INT_INTERFACE_BRAM_IMUX30", + "BRAM_IMUX30_2" ], [ - "CMT_FIFO_SW4A0_4", - "INT_INTERFACE_SW4A0" + "INT_INTERFACE_BRAM_IMUX31", + "BRAM_IMUX31_2" ], [ - "CMT_FIFO_L_BYP7_4", - "INT_INTERFACE_BYP7" + "INT_INTERFACE_BRAM_IMUX32", + "BRAM_IMUX32_2" ], [ - "CMT_FIFO_NW2A3_4", - "INT_INTERFACE_NW2A3" + "INT_INTERFACE_BRAM_IMUX33", + "BRAM_IMUX33_2" ], [ - "CMT_FIFO_L_IMUX40_4", - "INT_INTERFACE_IMUX40" + "INT_INTERFACE_BRAM_IMUX34", + "BRAM_IMUX34_2" ], [ - "CMT_FIFO_ER1BEG0_4", - "INT_INTERFACE_ER1BEG0" + "INT_INTERFACE_BRAM_IMUX35", + "BRAM_IMUX35_2" ], [ - "CMT_FIFO_EE4A0_4", - "INT_INTERFACE_EE4A0" + "INT_INTERFACE_BRAM_IMUX36", + "BRAM_IMUX36_2" ], [ - "CMT_FIFO_MONITOR_P_4", - "INT_INTERFACE_MONITOR_P" + "INT_INTERFACE_BRAM_IMUX37", + "BRAM_IMUX37_2" ], [ - "CMT_FIFO_L_IMUX4_4", - "INT_INTERFACE_IMUX4" + "INT_INTERFACE_BRAM_IMUX38", + "BRAM_IMUX38_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS20_4", - "INT_INTERFACE_LOGIC_OUTS_B20" + "INT_INTERFACE_BRAM_IMUX39", + "BRAM_IMUX39_2" ], [ - "CMT_FIFO_ER1BEG2_4", - "INT_INTERFACE_ER1BEG2" + "INT_INTERFACE_BRAM_IMUX40", + "BRAM_IMUX40_2" ], [ - "CMT_FIFO_WL1END1_4", - "INT_INTERFACE_WL1END1" + "INT_INTERFACE_BRAM_IMUX41", + "BRAM_IMUX41_2" ], [ - "CMT_FIFO_LH2_4", - "INT_INTERFACE_LH2" + "INT_INTERFACE_BRAM_IMUX42", + "BRAM_IMUX42_2" ], [ - "CMT_FIFO_WW2END0_4", - "INT_INTERFACE_WW2END0" + "INT_INTERFACE_BRAM_IMUX43", + "BRAM_IMUX43_2" ], [ - "CMT_FIFO_SW4END2_4", - "INT_INTERFACE_SW4END2" + "INT_INTERFACE_BRAM_IMUX44", + "BRAM_IMUX44_2" ], [ - "CMT_FIFO_L_IMUX8_4", - "INT_INTERFACE_IMUX8" + "INT_INTERFACE_BRAM_IMUX45", + "BRAM_IMUX45_2" ], [ - "CMT_FIFO_NE4BEG1_4", - "INT_INTERFACE_NE4BEG1" + "INT_INTERFACE_BRAM_IMUX46", + "BRAM_IMUX46_2" ], [ - "CMT_FIFO_L_IMUX10_4", - "INT_INTERFACE_IMUX10" + "INT_INTERFACE_BRAM_IMUX47", + "BRAM_IMUX47_2" ], [ - "CMT_FIFO_WW4A3_4", - "INT_INTERFACE_WW4A3" + "INT_INTERFACE_BRAM_UTURN_IMUX0", + "BRAM_IMUX0_UTURN_2" ], [ - "CMT_FIFO_L_IMUX21_4", - "INT_INTERFACE_IMUX21" + "INT_INTERFACE_BRAM_UTURN_IMUX1", + "BRAM_IMUX1_UTURN_2" ], [ - "CMT_FIFO_SW4A1_4", - "INT_INTERFACE_SW4A1" + "INT_INTERFACE_BRAM_UTURN_IMUX2", + "BRAM_IMUX2_UTURN_2" ], [ - "CMT_FIFO_NE4C1_4", - "INT_INTERFACE_NE4C1" + "INT_INTERFACE_BRAM_UTURN_IMUX3", + "BRAM_IMUX3_UTURN_2" ], [ - "CMT_FIFO_WW4B1_4", - "INT_INTERFACE_WW4B1" + "INT_INTERFACE_BRAM_UTURN_IMUX4", + "BRAM_IMUX4_UTURN_2" ], [ - "CMT_FIFO_SE4C1_4", - "INT_INTERFACE_SE4C1" + "INT_INTERFACE_BRAM_UTURN_IMUX5", + "BRAM_IMUX5_UTURN_2" ], [ - "CMT_FIFO_EE2BEG1_4", - "INT_INTERFACE_EE2BEG1" + "INT_INTERFACE_BRAM_UTURN_IMUX6", + "BRAM_IMUX6_UTURN_2" ], [ - "CMT_FIFO_NE4BEG2_4", - "INT_INTERFACE_NE4BEG2" + "INT_INTERFACE_BRAM_UTURN_IMUX7", + "BRAM_IMUX7_UTURN_2" ], [ - "CMT_FIFO_L_IMUX31_4", - "INT_INTERFACE_IMUX31" + "INT_INTERFACE_BRAM_UTURN_IMUX8", + "BRAM_IMUX8_UTURN_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS13_4", - "INT_INTERFACE_LOGIC_OUTS_B13" + "INT_INTERFACE_BRAM_UTURN_IMUX9", + "BRAM_IMUX9_UTURN_2" ], [ - "CMT_FIFO_L_CLK1_4", - "INT_INTERFACE_CLK1" + "INT_INTERFACE_BRAM_UTURN_IMUX10", + "BRAM_IMUX10_UTURN_2" ], [ - "CMT_FIFO_NE2A0_4", - "INT_INTERFACE_NE2A0" + "INT_INTERFACE_BRAM_UTURN_IMUX11", + "BRAM_IMUX11_UTURN_2" ], [ - "CMT_FIFO_SE4BEG3_4", - "INT_INTERFACE_SE4BEG3" + "INT_INTERFACE_BRAM_UTURN_IMUX12", + "BRAM_IMUX12_UTURN_2" ], [ - "CMT_FIFO_L_BYP4_4", - "INT_INTERFACE_BYP4" + "INT_INTERFACE_BRAM_UTURN_IMUX13", + "BRAM_IMUX13_UTURN_2" ], [ - "CMT_FIFO_L_CLK0_4", - "INT_INTERFACE_CLK0" + "INT_INTERFACE_BRAM_UTURN_IMUX14", + "BRAM_IMUX14_UTURN_2" ], [ - "CMT_FIFO_EL1BEG0_4", - "INT_INTERFACE_EL1BEG0" + "INT_INTERFACE_BRAM_UTURN_IMUX15", + "BRAM_IMUX15_UTURN_2" ], [ - "CMT_FIFO_L_IMUX41_4", - "INT_INTERFACE_IMUX41" + "INT_INTERFACE_BRAM_UTURN_IMUX16", + "BRAM_IMUX16_UTURN_2" ], [ - "CMT_FIFO_L_IMUX13_4", - "INT_INTERFACE_IMUX13" + "INT_INTERFACE_BRAM_UTURN_IMUX17", + "BRAM_IMUX17_UTURN_2" ], [ - "CMT_FIFO_L_IMUX14_4", - "INT_INTERFACE_IMUX14" + "INT_INTERFACE_BRAM_UTURN_IMUX18", + "BRAM_IMUX18_UTURN_2" ], [ - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + "INT_INTERFACE_BRAM_UTURN_IMUX19", + "BRAM_IMUX19_UTURN_2" ], [ - "CMT_FIFO_SW4END0_4", - "INT_INTERFACE_SW4END0" + "INT_INTERFACE_BRAM_UTURN_IMUX20", + "BRAM_IMUX20_UTURN_2" ], [ - "CMT_FIFO_L_IMUX17_4", - "INT_INTERFACE_IMUX17" + "INT_INTERFACE_BRAM_UTURN_IMUX21", + "BRAM_IMUX21_UTURN_2" ], [ - "CMT_FIFO_EE2BEG2_4", - "INT_INTERFACE_EE2BEG2" + "INT_INTERFACE_BRAM_UTURN_IMUX22", + "BRAM_IMUX22_UTURN_2" ], [ - "CMT_FIFO_L_FAN2_4", - "INT_INTERFACE_FAN2" + "INT_INTERFACE_BRAM_UTURN_IMUX23", + "BRAM_IMUX23_UTURN_2" ], [ - "CMT_FIFO_SW4A2_4", - "INT_INTERFACE_SW4A2" + "INT_INTERFACE_BRAM_UTURN_IMUX24", + "BRAM_IMUX24_UTURN_2" ], [ - "CMT_FIFO_NE4C2_4", - "INT_INTERFACE_NE4C2" + "INT_INTERFACE_BRAM_UTURN_IMUX25", + "BRAM_IMUX25_UTURN_2" ], [ - "CMT_FIFO_EE4B1_4", - "INT_INTERFACE_EE4B1" + "INT_INTERFACE_BRAM_UTURN_IMUX26", + "BRAM_IMUX26_UTURN_2" ], [ - "CMT_FIFO_L_FAN7_4", - "INT_INTERFACE_FAN7" + "INT_INTERFACE_BRAM_UTURN_IMUX27", + "BRAM_IMUX27_UTURN_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS17_4", - "INT_INTERFACE_LOGIC_OUTS_B17" + "INT_INTERFACE_BRAM_UTURN_IMUX28", + "BRAM_IMUX28_UTURN_2" ], [ - "CMT_FIFO_NE4C0_4", - "INT_INTERFACE_NE4C0" + "INT_INTERFACE_BRAM_UTURN_IMUX29", + "BRAM_IMUX29_UTURN_2" ], [ - "CMT_FIFO_SE4BEG1_4", - "INT_INTERFACE_SE4BEG1" + "INT_INTERFACE_BRAM_UTURN_IMUX30", + "BRAM_IMUX30_UTURN_2" ], [ - "CMT_FIFO_L_IMUX0_4", - "INT_INTERFACE_IMUX0" + "INT_INTERFACE_BRAM_UTURN_IMUX31", + "BRAM_IMUX31_UTURN_2" ], [ - "CMT_FIFO_L_CTRL1_4", - "INT_INTERFACE_CTRL1" + "INT_INTERFACE_BRAM_UTURN_IMUX32", + "BRAM_IMUX32_UTURN_2" ], [ - "CMT_FIFO_EE2A1_4", - "INT_INTERFACE_EE2A1" + "INT_INTERFACE_BRAM_UTURN_IMUX33", + "BRAM_IMUX33_UTURN_2" ], [ - "CMT_FIFO_SE2A2_4", - "INT_INTERFACE_SE2A2" + "INT_INTERFACE_BRAM_UTURN_IMUX34", + "BRAM_IMUX34_UTURN_2" ], [ - "CMT_FIFO_LH10_4", - "INT_INTERFACE_LH10" + "INT_INTERFACE_BRAM_UTURN_IMUX35", + "BRAM_IMUX35_UTURN_2" ], [ - "CMT_FIFO_EL1BEG3_4", - "INT_INTERFACE_EL1BEG3" + "INT_INTERFACE_BRAM_UTURN_IMUX36", + "BRAM_IMUX36_UTURN_2" ], [ - "CMT_FIFO_WW2END2_4", - "INT_INTERFACE_WW2END2" + "INT_INTERFACE_BRAM_UTURN_IMUX37", + "BRAM_IMUX37_UTURN_2" ], [ - "CMT_FIFO_NW4A1_4", - "INT_INTERFACE_NW4A1" + "INT_INTERFACE_BRAM_UTURN_IMUX38", + "BRAM_IMUX38_UTURN_2" ], [ - "CMT_FIFO_WL1END0_4", - "INT_INTERFACE_WL1END0" + "INT_INTERFACE_BRAM_UTURN_IMUX39", + "BRAM_IMUX39_UTURN_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS15_4", - "INT_INTERFACE_LOGIC_OUTS_B15" + "INT_INTERFACE_BRAM_UTURN_IMUX40", + "BRAM_IMUX40_UTURN_2" ], [ - "CMT_FIFO_L_BYP0_4", - "INT_INTERFACE_BYP0" + "INT_INTERFACE_BRAM_UTURN_IMUX41", + "BRAM_IMUX41_UTURN_2" ], [ - "CMT_FIFO_WW4A1_4", - "INT_INTERFACE_WW4A1" + "INT_INTERFACE_BRAM_UTURN_IMUX42", + "BRAM_IMUX42_UTURN_2" ], [ - "CMT_FIFO_SE2A0_4", - "INT_INTERFACE_SE2A0" + "INT_INTERFACE_BRAM_UTURN_IMUX43", + "BRAM_IMUX43_UTURN_2" ], [ - "CMT_FIFO_LH12_4", - "INT_INTERFACE_LH12" + "INT_INTERFACE_BRAM_UTURN_IMUX44", + "BRAM_IMUX44_UTURN_2" ], [ - "CMT_FIFO_L_FAN3_4", - "INT_INTERFACE_FAN3" + "INT_INTERFACE_BRAM_UTURN_IMUX45", + "BRAM_IMUX45_UTURN_2" ], [ - "CMT_FIFO_L_IMUX7_4", - "INT_INTERFACE_IMUX7" + "INT_INTERFACE_BRAM_UTURN_IMUX46", + "BRAM_IMUX46_UTURN_2" ], [ - "CMT_FIFO_EE4A1_4", - "INT_INTERFACE_EE4A1" + "INT_INTERFACE_BRAM_UTURN_IMUX47", + "BRAM_IMUX47_UTURN_2" ], [ - "CMT_FIFO_L_IMUX32_4", - "INT_INTERFACE_IMUX32" + "INT_INTERFACE_BYP0", + "BRAM_BYP0_2" ], [ - "CMT_FIFO_LH5_4", - "INT_INTERFACE_LH5" + "INT_INTERFACE_BYP1", + "BRAM_BYP1_2" ], [ - "CMT_FIFO_NW2A0_4", - "INT_INTERFACE_NW2A0" + "INT_INTERFACE_BYP2", + "BRAM_BYP2_2" ], [ - "CMT_FIFO_WW2A1_4", - "INT_INTERFACE_WW2A1" + "INT_INTERFACE_BYP3", + "BRAM_BYP3_2" ], [ - "CMT_FIFO_EE4C3_4", - "INT_INTERFACE_EE4C3" + "INT_INTERFACE_BYP4", + "BRAM_BYP4_2" ], [ - "CMT_FIFO_LH4_4", - "INT_INTERFACE_LH4" + "INT_INTERFACE_BYP5", + "BRAM_BYP5_2" ], [ - "CMT_FIFO_SE4C3_4", - "INT_INTERFACE_SE4C3" + "INT_INTERFACE_BYP6", + "BRAM_BYP6_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS18_4", - "INT_INTERFACE_LOGIC_OUTS_B18" + "INT_INTERFACE_BYP7", + "BRAM_BYP7_2" ], [ - "CMT_FIFO_NW4END0_4", - "INT_INTERFACE_NW4END0" + "INT_INTERFACE_CLK0", + "BRAM_CLK0_2" ], [ - "CMT_FIFO_WW2A3_4", - "INT_INTERFACE_WW2A3" + "INT_INTERFACE_CLK1", + "BRAM_CLK1_2" ], [ - "CMT_FIFO_L_IMUX33_4", - "INT_INTERFACE_IMUX33" + "INT_INTERFACE_CTRL0", + "BRAM_CTRL0_2" ], [ - "CMT_FIFO_EL1BEG2_4", - "INT_INTERFACE_EL1BEG2" + "INT_INTERFACE_CTRL1", + "BRAM_CTRL1_2" ], [ - "CMT_FIFO_NE2A3_4", - "INT_INTERFACE_NE2A3" + "INT_INTERFACE_EE2A0", + "BRAM_EE2A0_2" ], [ - "CMT_FIFO_L_IMUX43_4", - "INT_INTERFACE_IMUX43" + "INT_INTERFACE_EE2A1", + "BRAM_EE2A1_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS6_4", - "INT_INTERFACE_LOGIC_OUTS_B6" + "INT_INTERFACE_EE2A2", + "BRAM_EE2A2_2" ], [ - "CMT_FIFO_EE4BEG1_4", - "INT_INTERFACE_EE4BEG1" + "INT_INTERFACE_EE2A3", + "BRAM_EE2A3_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS10_4", - "INT_INTERFACE_LOGIC_OUTS_B10" + "INT_INTERFACE_EE2BEG0", + "BRAM_EE2BEG0_2" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", - "INT_INTERFACE_PHASER_TO_IO_OCLK" + "INT_INTERFACE_EE2BEG1", + "BRAM_EE2BEG1_2" ], [ - "CMT_FIFO_L_FAN1_4", - "INT_INTERFACE_FAN1" + "INT_INTERFACE_EE2BEG2", + "BRAM_EE2BEG2_2" ], [ - "CMT_FIFO_L_IMUX37_4", - "INT_INTERFACE_IMUX37" + "INT_INTERFACE_EE2BEG3", + "BRAM_EE2BEG3_2" ], [ - "CMT_FIFO_EE4A3_4", - "INT_INTERFACE_EE4A3" + "INT_INTERFACE_EE4A0", + "BRAM_EE4A0_2" ], [ - "CMT_FIFO_NW2A2_4", - "INT_INTERFACE_NW2A2" + "INT_INTERFACE_EE4A1", + "BRAM_EE4A1_2" ], [ - "CMT_FIFO_SW4A3_4", - "INT_INTERFACE_SW4A3" + "INT_INTERFACE_EE4A2", + "BRAM_EE4A2_2" ], [ - "CMT_FIFO_SE2A1_4", - "INT_INTERFACE_SE2A1" + "INT_INTERFACE_EE4A3", + "BRAM_EE4A3_2" ], [ - "CMT_FIFO_WW4C3_4", - "INT_INTERFACE_WW4C3" + "INT_INTERFACE_EE4B0", + "BRAM_EE4B0_2" ], [ - "CMT_FIFO_NW4A3_4", - "INT_INTERFACE_NW4A3" + "INT_INTERFACE_EE4B1", + "BRAM_EE4B1_2" ], [ - "CMT_FIFO_LH6_4", - "INT_INTERFACE_LH6" + "INT_INTERFACE_EE4B2", + "BRAM_EE4B2_2" ], [ - "CMT_FIFO_NW2A1_4", - "INT_INTERFACE_NW2A1" + "INT_INTERFACE_EE4B3", + "BRAM_EE4B3_2" ], [ - "CMT_FIFO_SE4C0_4", - "INT_INTERFACE_SE4C0" + "INT_INTERFACE_EE4BEG0", + "BRAM_EE4BEG0_2" ], [ - "CMT_FIFO_L_FAN5_4", - "INT_INTERFACE_FAN5" + "INT_INTERFACE_EE4BEG1", + "BRAM_EE4BEG1_2" ], [ - "CMT_FIFO_L_IMUX2_4", - "INT_INTERFACE_IMUX2" + "INT_INTERFACE_EE4BEG2", + "BRAM_EE4BEG2_2" ], [ - "CMT_FIFO_L_IMUX36_4", - "INT_INTERFACE_IMUX36" + "INT_INTERFACE_EE4BEG3", + "BRAM_EE4BEG3_2" ], [ - "CMT_FIFO_WW4B3_4", - "INT_INTERFACE_WW4B3" + "INT_INTERFACE_EE4C0", + "BRAM_EE4C0_2" ], [ - "CMT_FIFO_SE4C2_4", - "INT_INTERFACE_SE4C2" + "INT_INTERFACE_EE4C1", + "BRAM_EE4C1_2" ], [ - "CMT_FIFO_L_IMUX11_4", - "INT_INTERFACE_IMUX11" + "INT_INTERFACE_EE4C2", + "BRAM_EE4C2_2" ], [ - "CMT_FIFO_L_IMUX23_4", - "INT_INTERFACE_IMUX23" + "INT_INTERFACE_EE4C3", + "BRAM_EE4C3_2" ], [ - "CMT_FIFO_L_IMUX26_4", - "INT_INTERFACE_IMUX26" + "INT_INTERFACE_EL1BEG0", + "BRAM_EL1BEG0_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS1_4", - "INT_INTERFACE_LOGIC_OUTS_B1" + "INT_INTERFACE_EL1BEG1", + "BRAM_EL1BEG1_2" ], [ - "CMT_FIFO_EE4B0_4", - "INT_INTERFACE_EE4B0" + "INT_INTERFACE_EL1BEG2", + "BRAM_EL1BEG2_2" ], [ - "CMT_FIFO_L_IMUX27_4", - "INT_INTERFACE_IMUX27" + "INT_INTERFACE_EL1BEG3", + "BRAM_EL1BEG3_2" ], [ - "CMT_FIFO_EE4C2_4", - "INT_INTERFACE_EE4C2" + "INT_INTERFACE_ER1BEG0", + "BRAM_ER1BEG0_2" ], [ - "CMT_FIFO_L_BYP6_4", - "INT_INTERFACE_BYP6" + "INT_INTERFACE_ER1BEG1", + "BRAM_ER1BEG1_2" ], [ - "CMT_FIFO_WW4C0_4", - "INT_INTERFACE_WW4C0" + "INT_INTERFACE_ER1BEG2", + "BRAM_ER1BEG2_2" ], [ - "CMT_FIFO_NE2A1_4", - "INT_INTERFACE_NE2A1" + "INT_INTERFACE_ER1BEG3", + "BRAM_ER1BEG3_2" ], [ - "CMT_FIFO_NE4BEG3_4", - "INT_INTERFACE_NE4BEG3" + "INT_INTERFACE_FAN0", + "BRAM_FAN0_2" ], [ - "CMT_FIFO_L_FAN0_4", - "INT_INTERFACE_FAN0" + "INT_INTERFACE_FAN1", + "BRAM_FAN1_2" ], [ - "CMT_FIFO_L_IMUX15_4", - "INT_INTERFACE_IMUX15" + "INT_INTERFACE_FAN2", + "BRAM_FAN2_2" ], [ - "CMT_FIFO_NE4C3_4", - "INT_INTERFACE_NE4C3" + "INT_INTERFACE_FAN3", + "BRAM_FAN3_2" ], [ - "CMT_FIFO_L_IMUX38_4", - "INT_INTERFACE_IMUX38" + "INT_INTERFACE_FAN4", + "BRAM_FAN4_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS21_4", - "INT_INTERFACE_LOGIC_OUTS_B21" + "INT_INTERFACE_FAN5", + "BRAM_FAN5_2" ], [ - "CMT_FIFO_L_BYP2_4", - "INT_INTERFACE_BYP2" + "INT_INTERFACE_FAN6", + "BRAM_FAN6_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS23_4", - "INT_INTERFACE_LOGIC_OUTS_B23" + "INT_INTERFACE_FAN7", + "BRAM_FAN7_2" ], [ - "CMT_FIFO_L_IMUX30_4", - "INT_INTERFACE_IMUX30" + "INT_INTERFACE_LH1", + "BRAM_LH1_2" ], [ - "CMT_FIFO_L_IMUX16_4", - "INT_INTERFACE_IMUX16" + "INT_INTERFACE_LH2", + "BRAM_LH2_2" ], [ - "CMT_FIFO_SW4END3_4", - "INT_INTERFACE_SW4END3" + "INT_INTERFACE_LH3", + "BRAM_LH3_2" ], [ - "CMT_FIFO_LH9_4", - "INT_INTERFACE_LH9" + "INT_INTERFACE_LH4", + "BRAM_LH4_2" ], [ - "CMT_FIFO_NW4END1_4", - "INT_INTERFACE_NW4END1" + "INT_INTERFACE_LH5", + "BRAM_LH5_2" ], [ - "CMT_FIFO_L_IMUX20_4", - "INT_INTERFACE_IMUX20" + "INT_INTERFACE_LH6", + "BRAM_LH6_2" ], [ - "CMT_FIFO_EE4BEG0_4", - "INT_INTERFACE_EE4BEG0" + "INT_INTERFACE_LH7", + "BRAM_LH7_2" ], [ - "CMT_FIFO_MONITOR_N_4", - "INT_INTERFACE_MONITOR_N" + "INT_INTERFACE_LH8", + "BRAM_LH8_2" ], [ - "CMT_FIFO_SW2A1_4", - "INT_INTERFACE_SW2A1" + "INT_INTERFACE_LH9", + "BRAM_LH9_2" ], [ - "CMT_FIFO_SE2A3_4", - "INT_INTERFACE_SE2A3" + "INT_INTERFACE_LH10", + "BRAM_LH10_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS16_4", - "INT_INTERFACE_LOGIC_OUTS_B16" + "INT_INTERFACE_LH11", + "BRAM_LH11_2" ], [ - "CMT_FIFO_L_IMUX34_4", - "INT_INTERFACE_IMUX34" + "INT_INTERFACE_LH12", + "BRAM_LH12_2" ], [ - "CMT_FIFO_NE2A2_4", - "INT_INTERFACE_NE2A2" + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "BRAM_LOGIC_OUTS_B0_2" ], [ - "CMT_FIFO_EE2A3_4", - "INT_INTERFACE_EE2A3" + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "BRAM_LOGIC_OUTS_B1_2" ], [ - "CMT_FIFO_EE2BEG3_4", - "INT_INTERFACE_EE2BEG3" + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "BRAM_LOGIC_OUTS_B2_2" ], [ - "CMT_FIFO_L_IMUX47_4", - "INT_INTERFACE_IMUX47" + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "BRAM_LOGIC_OUTS_B3_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS5_4", - "INT_INTERFACE_LOGIC_OUTS_B5" + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "BRAM_LOGIC_OUTS_B4_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS7_4", - "INT_INTERFACE_LOGIC_OUTS_B7" + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "BRAM_LOGIC_OUTS_B5_2" ], [ - "CMT_FIFO_SW2A2_4", - "INT_INTERFACE_SW2A2" + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "BRAM_LOGIC_OUTS_B6_2" ], [ - "CMT_FIFO_L_IMUX19_4", - "INT_INTERFACE_IMUX19" + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "BRAM_LOGIC_OUTS_B7_2" ], [ - "CMT_FIFO_EE2BEG0_4", - "INT_INTERFACE_EE2BEG0" + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "BRAM_LOGIC_OUTS_B8_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS19_4", - "INT_INTERFACE_LOGIC_OUTS_B19" + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "BRAM_LOGIC_OUTS_B9_2" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "BRAM_LOGIC_OUTS_B10_2" ], [ - "CMT_FIFO_WW4END1_4", - "INT_INTERFACE_WW4END1" + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "BRAM_LOGIC_OUTS_B11_2" ], [ - "CMT_FIFO_EE4BEG3_4", - "INT_INTERFACE_EE4BEG3" + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "BRAM_LOGIC_OUTS_B12_2" ], [ - "CMT_FIFO_WW4END0_4", - "INT_INTERFACE_WW4END0" + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "BRAM_LOGIC_OUTS_B13_2" ], [ - "CMT_FIFO_L_IMUX22_4", - "INT_INTERFACE_IMUX22" + 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], + [ + "INT_INTERFACE_WW4B1", + "BRAM_WW4B1_4" + ], + [ + "INT_INTERFACE_WW4B2", + "BRAM_WW4B2_4" + ], + [ + "INT_INTERFACE_WW4B3", + "BRAM_WW4B3_4" + ], + [ + "INT_INTERFACE_WW4C0", + "BRAM_WW4C0_4" + ], + [ + "INT_INTERFACE_WW4C1", + "BRAM_WW4C1_4" + ], + [ + "INT_INTERFACE_WW4C2", + "BRAM_WW4C2_4" + ], + [ + "INT_INTERFACE_WW4C3", + "BRAM_WW4C3_4" + ], + [ + "INT_INTERFACE_WW4END0", + "BRAM_WW4END0_4" + ], + [ + "INT_INTERFACE_WW4END1", + "BRAM_WW4END1_4" + ], + [ + "INT_INTERFACE_WW4END2", + "BRAM_WW4END2_4" + ], + [ + "INT_INTERFACE_WW4END3", + "BRAM_WW4END3_4" ] ] }, @@ -2925,3545 +11649,881 @@ 0 ], "tile_types": [ - "CLBLM_L", - "VBRK" - ], - "wire_pairs": [ - [ - "CLBLM_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLBLM_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLBLM_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLBLM_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLBLM_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLBLM_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLBLM_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLBLM_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLBLM_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLBLM_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLBLM_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLBLM_LH4", - "VBRK_LH4" - ], - [ - "CLBLM_WW4C2", - "VBRK_WW4C2" - ], - [ - "CLBLM_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLBLM_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLBLM_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLBLM_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLBLM_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLBLM_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLBLM_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLBLM_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLBLM_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLBLM_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLBLM_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLBLM_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLBLM_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLBLM_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLBLM_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLBLM_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLBLM_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLBLM_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLBLM_LH10", - "VBRK_LH10" - ], - [ - "CLBLM_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLBLM_NE2A2", - "VBRK_NE2A2" - ], - [ - "CLBLM_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLBLM_LH2", - "VBRK_LH2" - ], - [ - "CLBLM_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLBLM_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLBLM_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLBLM_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLBLM_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLBLM_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLBLM_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLBLM_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLBLM_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLBLM_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLBLM_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLBLM_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLBLM_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLBLM_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLBLM_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLBLM_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLBLM_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLBLM_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLBLM_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLBLM_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLBLM_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLBLM_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLBLM_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLBLM_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLBLM_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLBLM_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLBLM_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLBLM_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLBLM_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLBLM_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLBLM_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLBLM_EE4B1", - "VBRK_EE4B1" - ], - [ - "CLBLM_LH5", - "VBRK_LH5" - ], - [ - "CLBLM_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLBLM_EE4BEG2", - "VBRK_EE4BEG2" - ], - [ - "CLBLM_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLBLM_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLBLM_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLBLM_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLBLM_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLBLM_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLBLM_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLBLM_LH6", - "VBRK_LH6" - ], - [ - "CLBLM_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLBLM_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLBLM_LH11", - "VBRK_LH11" - ], - [ - "CLBLM_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLBLM_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLBLM_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLBLM_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLBLM_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLBLM_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLBLM_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLBLM_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLBLM_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLBLM_LH7", - "VBRK_LH7" - ], - [ - "CLBLM_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLBLM_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLBLM_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLBLM_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLBLM_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLBLM_LH1", - "VBRK_LH1" - ], - [ - "CLBLM_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLBLM_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLBLM_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLBLM_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLBLM_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLBLM_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLBLM_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLBLM_LH3", - "VBRK_LH3" - ], - [ - "CLBLM_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLBLM_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLBLM_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLBLM_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLBLM_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLBLM_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLBLM_LH9", - "VBRK_LH9" - ], - [ - "CLBLM_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLBLM_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLBLM_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLBLM_LH8", - "VBRK_LH8" - ], - [ - "CLBLM_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLBLM_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLBLM_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLBLM_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLBLM_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLBLM_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLBLM_LH12", - "VBRK_LH12" - ], - [ - "CLBLM_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLBLM_SE4BEG3", - "VBRK_SE4BEG3" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "HCLK_R", + "BRAM_INT_INTERFACE_R", "INT_R" ], "wire_pairs": [ [ - "HCLK_BYP_BOUNCE7", - "BYP_BOUNCE_N3_7" + "INT_INTERFACE_BRAM_IMUX0", + "IMUX0" ], [ - "HCLK_NN2A1", - "NN2END1" + "INT_INTERFACE_BRAM_IMUX1", + "IMUX1" ], [ - "HCLK_SE2A3", - "SE2BEG3" + "INT_INTERFACE_BRAM_IMUX2", + "IMUX2" ], [ - "HCLK_NN6A1", - "NN6B1" + "INT_INTERFACE_BRAM_IMUX3", + "IMUX3" ], [ - "HCLK_NE6C0", - "NE6D0" + "INT_INTERFACE_BRAM_IMUX4", + "IMUX4" ], [ - "HCLK_LV13", - "LV14" + "INT_INTERFACE_BRAM_IMUX5", + "IMUX5" ], [ - "HCLK_LVB10", - "LVB10" + "INT_INTERFACE_BRAM_IMUX6", + "IMUX6" ], [ - "HCLK_NW6D1", - "NW6E1" + "INT_INTERFACE_BRAM_IMUX7", + "IMUX7" ], [ - "HCLK_LV5", - "LV6" + "INT_INTERFACE_BRAM_IMUX8", + "IMUX8" ], [ - "HCLK_SS6A1", - "SS6BEG1" + "INT_INTERFACE_BRAM_IMUX9", + "IMUX9" ], [ - "HCLK_WW2END3", - "WW2END_N0_3" + "INT_INTERFACE_BRAM_IMUX10", + "IMUX10" ], [ - "HCLK_SE6E1", - "SE6D1" + "INT_INTERFACE_BRAM_IMUX11", + "IMUX11" ], [ - "HCLK_SW6C1", - "SW6B1" + "INT_INTERFACE_BRAM_IMUX12", + "IMUX12" ], [ - "HCLK_NN6BEG0", - "NN6A0" + "INT_INTERFACE_BRAM_IMUX13", + "IMUX13" ], [ - "HCLK_EL1BEG3", - "EL1BEG_N3" + "INT_INTERFACE_BRAM_IMUX14", + "IMUX14" ], [ - "HCLK_NE6B0", - "NE6C0" + "INT_INTERFACE_BRAM_IMUX15", + "IMUX15" ], [ - "HCLK_NN6B0", - "NN6C0" + "INT_INTERFACE_BRAM_IMUX16", + "IMUX16" ], [ - "HCLK_WL1END3", - "WL1END_N1_3" + "INT_INTERFACE_BRAM_IMUX17", + "IMUX17" ], [ - "HCLK_NL1BEG2", - "NL1END2" + "INT_INTERFACE_BRAM_IMUX18", + "IMUX18" ], [ - "HCLK_LV16", - "LV17" + "INT_INTERFACE_BRAM_IMUX19", + "IMUX19" ], [ - "HCLK_SS6END3", - "SS6E3" + "INT_INTERFACE_BRAM_IMUX20", + "IMUX20" ], [ - "HCLK_LV17", - "LV18" + "INT_INTERFACE_BRAM_IMUX21", + "IMUX21" ], [ - "HCLK_LV10", - "LV11" + "INT_INTERFACE_BRAM_IMUX22", + "IMUX22" ], [ - "HCLK_LEAF_CLK_B_TOP2", - "GCLK_B2" + "INT_INTERFACE_BRAM_IMUX23", + "IMUX23" ], [ - "HCLK_SE6D0", - "SE6C0" + "INT_INTERFACE_BRAM_IMUX24", + "IMUX24" ], [ - "HCLK_LVB11", - "LVB11" + "INT_INTERFACE_BRAM_IMUX25", + "IMUX25" ], [ - "HCLK_FAN_BOUNCE_S3_0", - "FAN_BOUNCE0" + "INT_INTERFACE_BRAM_IMUX26", + "IMUX26" ], [ - "HCLK_NW6A3", - "NW6B3" + "INT_INTERFACE_BRAM_IMUX27", + "IMUX27" ], [ - "HCLK_LVB7", - "LVB7" + "INT_INTERFACE_BRAM_IMUX28", + "IMUX28" ], [ - "HCLK_LV2", - "LV3" + "INT_INTERFACE_BRAM_IMUX29", + "IMUX29" ], [ - "HCLK_NE6A1", - "NE6B1" + "INT_INTERFACE_BRAM_IMUX30", + "IMUX30" ], [ - "HCLK_SE6D3", - "SE6C3" + "INT_INTERFACE_BRAM_IMUX31", + "IMUX31" ], [ - "HCLK_SW6B0", - "SW6A0" + "INT_INTERFACE_BRAM_IMUX32", + "IMUX32" ], [ - "HCLK_NE6C1", - "NE6D1" + "INT_INTERFACE_BRAM_IMUX33", + "IMUX33" ], [ - "HCLK_NN2A0", - "NN2END0" + "INT_INTERFACE_BRAM_IMUX34", + "IMUX34" ], [ - "HCLK_SW6B1", - "SW6A1" + "INT_INTERFACE_BRAM_IMUX35", + "IMUX35" ], [ - "HCLK_BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" + "INT_INTERFACE_BRAM_IMUX36", + "IMUX36" ], [ - "HCLK_NN6END_S1_0", - "NN6END0" + "INT_INTERFACE_BRAM_IMUX37", + "IMUX37" ], [ - "HCLK_NW6A2", - "NW6B2" + "INT_INTERFACE_BRAM_IMUX38", + "IMUX38" ], [ - "HCLK_SW2A3", - "SW2BEG3" + "INT_INTERFACE_BRAM_IMUX39", + "IMUX39" ], [ - "HCLK_NE6A0", - "NE6B0" + "INT_INTERFACE_BRAM_IMUX40", + "IMUX40" ], [ - "HCLK_SW6D0", - "SW6C0" + "INT_INTERFACE_BRAM_IMUX41", + "IMUX41" ], [ - "HCLK_LV1", - "LV2" + "INT_INTERFACE_BRAM_IMUX42", + "IMUX42" ], [ - "HCLK_SS6B2", - "SS6A2" + "INT_INTERFACE_BRAM_IMUX43", + "IMUX43" ], [ - "HCLK_SR1END1", - "SR1BEG1" + "INT_INTERFACE_BRAM_IMUX44", + "IMUX44" ], [ - "HCLK_SE6B0", - "SE6A0" + "INT_INTERFACE_BRAM_IMUX45", + "IMUX45" ], [ - "HCLK_LVB12", - "LVB12" + "INT_INTERFACE_BRAM_IMUX46", + "IMUX46" ], [ - "HCLK_NW2A1", - "NW2A1" + "INT_INTERFACE_BRAM_IMUX47", + "IMUX47" ], [ - "HCLK_NR1BEG2", - "NR1END2" + "INT_INTERFACE_BYP0", + "BYP0" ], [ - "HCLK_NE6B1", - "NE6C1" + "INT_INTERFACE_BYP1", + "BYP1" ], [ - "HCLK_SS6B1", - "SS6A1" + "INT_INTERFACE_BYP2", + "BYP2" ], [ - "HCLK_LVB5", - "LVB5" + "INT_INTERFACE_BYP3", + "BYP3" ], [ - "HCLK_FAN_BOUNCE_S3_2", - "FAN_BOUNCE2" + "INT_INTERFACE_BYP4", + "BYP4" ], [ - "HCLK_NE6D3", - "NE6E3" + "INT_INTERFACE_BYP5", + "BYP5" ], [ - "HCLK_SS6C0", - "SS6B0" + "INT_INTERFACE_BYP6", + "BYP6" ], [ - "HCLK_NE6D2", - "NE6E2" + "INT_INTERFACE_BYP7", + "BYP7" ], [ - "HCLK_NW6B2", - "NW6C2" + "INT_INTERFACE_CLK0", + "CLK0" ], [ - "HCLK_SS6B0", - "SS6A0" + "INT_INTERFACE_CLK1", + "CLK1" ], [ - "HCLK_SE6B1", - "SE6A1" + "INT_INTERFACE_CTRL0", + "CTRL0" ], [ - "HCLK_SS6B3", - "SS6A3" + "INT_INTERFACE_CTRL1", + "CTRL1" ], [ - "HCLK_NN6C3", - "NN6D3" + "INT_INTERFACE_EE2A0", + "EE2A0" ], [ - "HCLK_NW6C1", - "NW6D1" + "INT_INTERFACE_EE2A1", + "EE2A1" ], [ - "HCLK_SS6END0", - "SS6E0" + "INT_INTERFACE_EE2A2", + "EE2A2" ], [ - "HCLK_NW6D0", - "NW6E0" + "INT_INTERFACE_EE2A3", + "EE2A3" ], [ - "HCLK_SS6END_N0_3", - "SS6END_N0_3" + "INT_INTERFACE_EE2BEG0", + "EE2BEG0" ], [ - "HCLK_SS2A2", - "SS2BEG2" + "INT_INTERFACE_EE2BEG1", + "EE2BEG1" ], [ - "HCLK_NW6A0", - "NW6B0" + "INT_INTERFACE_EE2BEG2", + "EE2BEG2" ], [ - "HCLK_LEAF_CLK_B_TOP1", - "GCLK_B1" + "INT_INTERFACE_EE2BEG3", + "EE2BEG3" ], [ - "HCLK_LV7", - "LV8" + "INT_INTERFACE_EE4A0", + "EE4A0" ], [ - "HCLK_WL1BEG3", - "WL1BEG_N3" + "INT_INTERFACE_EE4A1", + "EE4A1" ], [ - "HCLK_ER1BEG_S0", + "INT_INTERFACE_EE4A2", + "EE4A2" + ], + [ + "INT_INTERFACE_EE4A3", + "EE4A3" + ], + [ + "INT_INTERFACE_EE4B0", + "EE4B0" + ], + [ + "INT_INTERFACE_EE4B1", + "EE4B1" + ], + [ + "INT_INTERFACE_EE4B2", + "EE4B2" + ], + [ + "INT_INTERFACE_EE4B3", + "EE4B3" + ], + [ + "INT_INTERFACE_EE4BEG0", + "EE4BEG0" + ], + [ + "INT_INTERFACE_EE4BEG1", + "EE4BEG1" + ], + [ + "INT_INTERFACE_EE4BEG2", + "EE4BEG2" + ], + [ + "INT_INTERFACE_EE4BEG3", + "EE4BEG3" + ], + [ + "INT_INTERFACE_EE4C0", + "EE4C0" + ], + [ + "INT_INTERFACE_EE4C1", + "EE4C1" + ], + [ + "INT_INTERFACE_EE4C2", + "EE4C2" + ], + [ + "INT_INTERFACE_EE4C3", + "EE4C3" + ], + [ + "INT_INTERFACE_EL1BEG0", + "EL1BEG0" + ], + [ + "INT_INTERFACE_EL1BEG1", + "EL1BEG1" + ], + [ + "INT_INTERFACE_EL1BEG2", + "EL1BEG2" + ], + [ + "INT_INTERFACE_EL1BEG3", + "EL1BEG3" + ], + [ + "INT_INTERFACE_ER1BEG0", "ER1BEG0" ], [ - "HCLK_NW6B1", - "NW6C1" + "INT_INTERFACE_ER1BEG1", + "ER1BEG1" ], [ - "HCLK_LVB8", - "LVB8" + "INT_INTERFACE_ER1BEG2", + "ER1BEG2" ], [ - "HCLK_SE2A1", - "SE2BEG1" + "INT_INTERFACE_ER1BEG3", + "ER1BEG3" ], [ - "HCLK_SW2END2", - "SW2BEG2" + "INT_INTERFACE_FAN0", + "FAN0" ], [ - "HCLK_SS2END_N0_3", - "SS2END_N0_3" + "INT_INTERFACE_FAN1", + "FAN1" ], [ - "HCLK_NN2BEG1", - "NN2A1" + "INT_INTERFACE_FAN2", + "FAN2" ], [ - "HCLK_SS6E0", - "SS6D0" + "INT_INTERFACE_FAN3", + "FAN3" ], [ - "HCLK_SW6END3", - "SW6END_N0_3" + "INT_INTERFACE_FAN4", + "FAN4" ], [ - "HCLK_NW2END_S0_0", - "NW2END0" + "INT_INTERFACE_FAN5", + "FAN5" ], [ - "HCLK_SE6E0", - "SE6D0" + "INT_INTERFACE_FAN6", + "FAN6" ], [ - "HCLK_SE6C0", - "SE6B0" + "INT_INTERFACE_FAN7", + "FAN7" ], [ - "HCLK_SE6E2", - "SE6D2" + "INT_INTERFACE_LH1", + "LH1" ], [ - "HCLK_SS6D0", - "SS6C0" + "INT_INTERFACE_LH2", + "LH2" ], [ - "HCLK_NN6E0", - "NN6END0" + "INT_INTERFACE_LH3", + "LH3" ], [ - "HCLK_LV12", - "LV13" + "INT_INTERFACE_LH4", + "LH4" ], [ - "HCLK_NE6B3", - "NE6C3" + "INT_INTERFACE_LH5", + "LH5" ], [ - "HCLK_NN2A3", - "NN2END3" + "INT_INTERFACE_LH6", + "LH6" ], [ - "HCLK_NE6C2", - "NE6D2" + "INT_INTERFACE_LH7", + "LH7" ], [ - "HCLK_SS2A1", - "SS2BEG1" + "INT_INTERFACE_LH8", + "LH8" ], [ - "HCLK_SS6D1", - "SS6C1" + "INT_INTERFACE_LH9", + "LH9" ], [ - "HCLK_SE6B2", - "SE6A2" + "INT_INTERFACE_LH10", + "LH10" ], [ - "HCLK_NW2A2", - "NW2A2" + "INT_INTERFACE_LH11", + "LH11" ], [ - "HCLK_SS6E3", - "SS6D3" + "INT_INTERFACE_LH12", + "LH12" ], [ - "HCLK_SS2BEG3", - "SS2BEG3" + "INT_INTERFACE_LOGIC_OUTS0", + "LOGIC_OUTS0" ], [ - "HCLK_NE6A3", - "NE6B3" + "INT_INTERFACE_LOGIC_OUTS1", + "LOGIC_OUTS1" ], [ - "HCLK_SS2END2", - "SS2A2" + "INT_INTERFACE_LOGIC_OUTS2", + "LOGIC_OUTS2" ], [ - "HCLK_NN6E1", - "NN6END1" + "INT_INTERFACE_LOGIC_OUTS3", + "LOGIC_OUTS3" ], [ - "HCLK_SE6B3", - "SE6A3" + "INT_INTERFACE_LOGIC_OUTS4", + "LOGIC_OUTS4" ], [ - "HCLK_SS6A2", - "SS6BEG2" + "INT_INTERFACE_LOGIC_OUTS5", + "LOGIC_OUTS5" ], [ - "HCLK_LV8", - "LV9" + "INT_INTERFACE_LOGIC_OUTS6", + "LOGIC_OUTS6" ], [ - "HCLK_SS6A3", - "SS6BEG3" + "INT_INTERFACE_LOGIC_OUTS7", + "LOGIC_OUTS7" ], [ - "HCLK_SR1END_N3_3", - "SR1END_N3_3" + "INT_INTERFACE_LOGIC_OUTS8", + "LOGIC_OUTS8" ], [ - "HCLK_NN6C0", - "NN6D0" + "INT_INTERFACE_LOGIC_OUTS9", + "LOGIC_OUTS9" ], [ - "HCLK_NN6D1", - "NN6E1" + "INT_INTERFACE_LOGIC_OUTS10", + "LOGIC_OUTS10" ], [ - "HCLK_NN6BEG1", - "NN6A1" + "INT_INTERFACE_LOGIC_OUTS11", + "LOGIC_OUTS11" ], [ - "HCLK_NN6A2", - "NN6B2" + "INT_INTERFACE_LOGIC_OUTS12", + "LOGIC_OUTS12" ], [ - "HCLK_LV9", - "LV10" + "INT_INTERFACE_LOGIC_OUTS13", + "LOGIC_OUTS13" ], [ - "HCLK_NW6D3", - "NW6E3" + "INT_INTERFACE_LOGIC_OUTS14", + "LOGIC_OUTS14" ], [ - "HCLK_NE6A2", - "NE6B2" + "INT_INTERFACE_LOGIC_OUTS15", + "LOGIC_OUTS15" ], [ - "HCLK_SW6D2", - "SW6C2" + "INT_INTERFACE_LOGIC_OUTS16", + "LOGIC_OUTS16" ], [ - "HCLK_SS6END2", - "SS6E2" + "INT_INTERFACE_LOGIC_OUTS17", + "LOGIC_OUTS17" ], [ - "HCLK_SS6C1", - "SS6B1" + "INT_INTERFACE_LOGIC_OUTS18", + "LOGIC_OUTS18" ], [ - "HCLK_NN6C2", - "NN6D2" + "INT_INTERFACE_LOGIC_OUTS19", + "LOGIC_OUTS19" ], [ - "HCLK_SE6E3", - "SE6D3" + "INT_INTERFACE_LOGIC_OUTS20", + "LOGIC_OUTS20" ], [ - "HCLK_SS6E1", - "SS6D1" + "INT_INTERFACE_LOGIC_OUTS21", + "LOGIC_OUTS21" ], [ - "HCLK_NR1BEG0", - "NR1END0" + "INT_INTERFACE_LOGIC_OUTS22", + "LOGIC_OUTS22" ], [ - "HCLK_SE2A0", - "SE2BEG0" + "INT_INTERFACE_LOGIC_OUTS23", + "LOGIC_OUTS23" ], [ - "HCLK_WW4END_S0_0", - "WW4END0" + "INT_INTERFACE_MONITOR_N", + "MONITOR_N" ], [ - "HCLK_NW6END_S0_0", - "NW6END0" + "INT_INTERFACE_MONITOR_P", + "MONITOR_P" ], [ - "HCLK_NN2BEG3", - "NN2A3" - ], - [ - "HCLK_LV11", - "LV12" - ], - [ - "HCLK_NE2BEG2", - "NE2A2" - ], - [ - "HCLK_LVB1", - "LVB1" - ], - [ - "HCLK_EL1END_S3_0", - "EL1END0" - ], - [ - "HCLK_NE6B2", - "NE6C2" - ], - [ - "HCLK_NW6B3", - "NW6C3" - ], - [ - "HCLK_NW6C3", - "NW6D3" - ], - [ - "HCLK_SE2A2", - "SE2BEG2" - ], - [ - "HCLK_LEAF_CLK_B_TOP0", - "GCLK_B0" - ], - [ - "HCLK_NW6C2", - "NW6D2" - ], - [ - "HCLK_LVB9", - "LVB9" - ], - [ - "HCLK_LV0", - "LV1" - ], - [ - "HCLK_SL1END0", - "SL1BEG0" - ], - [ - "HCLK_SL1END1", - "SL1BEG1" - ], - [ - "HCLK_SS6E2", - "SS6D2" - ], - [ - "HCLK_NR1BEG3", - "NR1END3" - ], - [ - "HCLK_SW6E1", - "SW6D1" - ], - [ - "HCLK_NN6A0", - "NN6B0" - ], - [ - "HCLK_NN2A2", - "NN2END2" - ], - [ - "HCLK_NN6D0", - "NN6E0" - ], - [ - "HCLK_WR1BEG_S0", - "WR1BEG0" - ], - [ - "HCLK_NN6BEG3", - "NN6A3" - ], - [ - "HCLK_NE2BEG0", + "INT_INTERFACE_NE2A0", "NE2A0" ], [ - "HCLK_NN6D3", - "NN6E3" - ], - [ - "HCLK_NN2END_S2_0", - "NN2END0" - ], - [ - "HCLK_LV14", - "LV15" - ], - [ - "HCLK_LEAF_CLK_B_TOP5", - "GCLK_B5" - ], - [ - "HCLK_BYP_BOUNCE3", - "BYP_BOUNCE_N3_3" - ], - [ - "HCLK_NN6E3", - "NN6END3" - ], - [ - "HCLK_LVB2", - "LVB2" - ], - [ - "HCLK_SS6END1", - "SS6E1" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END_N0_3" - ], - [ - "HCLK_SR1BEG3", - "SR1BEG3" - ], - [ - "HCLK_SE6C1", - "SE6B1" - ], - [ - "HCLK_NE2BEG3", - "NE2A3" - ], - [ - "HCLK_SS2END1", - "SS2A1" - ], - [ - "HCLK_NN6BEG2", - "NN6A2" - ], - [ - "HCLK_LVB6", - "LVB6" - ], - [ - "HCLK_LEAF_CLK_B_TOP3", - "GCLK_B3" - ], - [ - "HCLK_LEAF_CLK_B_TOP4", - "GCLK_B4" - ], - [ - "HCLK_NW2A0", - "NW2A0" - ], - [ - "HCLK_NN6B3", - "NN6C3" - ], - [ - "HCLK_SS6D2", - "SS6C2" - ], - [ - "HCLK_LVB3", - "LVB3" - ], - [ - "HCLK_SE6C2", - "SE6B2" - ], - [ - "HCLK_SW6D1", - "SW6C1" - ], - [ - "HCLK_LV15", - "LV16" - ], - [ - "HCLK_NW6B0", - "NW6C0" - ], - [ - "HCLK_NN2BEG0", - "NN2A0" - ], - [ - "HCLK_NL1END_S3_0", - "NL1END0" - ], - [ - "HCLK_NN6D2", - "NN6E2" - ], - [ - "HCLK_SE6D1", - "SE6C1" - ], - [ - "HCLK_NN6E2", - "NN6END2" - ], - [ - "HCLK_SS6C2", - "SS6B2" - ], - [ - "HCLK_NE6D0", - "NE6E0" - ], - [ - "HCLK_NN6B1", - "NN6C1" - ], - [ - "HCLK_FAN_BOUNCE_S3_6", - "FAN_BOUNCE6" - ], - [ - "HCLK_NW6D2", - "NW6E2" - ], - [ - "HCLK_SW6C2", - "SW6B2" - ], - [ - "HCLK_SW6E3", - "SW6D3" - ], - [ - "HCLK_LVB4", - "LVB4" - ], - [ - "HCLK_NE6C3", - "NE6D3" - ], - [ - "HCLK_SS6D3", - "SS6C3" - ], - [ - "HCLK_NL1BEG1", - "NL1END1" - ], - [ - "HCLK_SW6C0", - "SW6B0" - ], - [ - "HCLK_SE6C3", - "SE6B3" - ], - [ - "HCLK_NE6D1", - "NE6E1" - ], - [ - "HCLK_NN6C1", - "NN6D1" - ], - [ - "HCLK_SW6D3", - "SW6C3" - ], - [ - "HCLK_SE6D2", - "SE6C2" - ], - [ - "HCLK_NN6A3", - "NN6B3" - ], - [ - "HCLK_SW6E0", - "SW6D0" - ], - [ - "HCLK_LV3", - "LV4" - ], - [ - "HCLK_NN2BEG2", - "NN2A2" - ], - [ - "HCLK_NW6C0", - "NW6D0" - ], - [ - "HCLK_NL1BEG0", - "NL1END0" - ], - [ - "HCLK_SR1END2", - "SR1BEG2" - ], - [ - "HCLK_ER1END3", - "ER1END_N3_3" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END0" - ], - [ - "HCLK_NN6B2", - "NN6C2" - ], - [ - "HCLK_SS6A0", - "SS6BEG0" - ], - [ - "HCLK_SW2END1", - "SW2BEG1" - ], - [ - "HCLK_SW6B3", - "SW6A3" - ], - [ - "HCLK_FAN_BOUNCE_S3_4", - "FAN_BOUNCE4" - ], - [ - "HCLK_SS6C3", - "SS6B3" - ], - [ - "HCLK_LV4", - "LV5" - ], - [ - "HCLK_SS2A0", - "SS2BEG0" - ], - [ - "HCLK_NE2END_S3_0", - "NE2END0" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "HCLK_LV6", - "LV7" - ], - [ - "HCLK_NR1BEG1", - "NR1END1" - ], - [ - "HCLK_NW2A3", - "NW2A3" - ], - [ - "HCLK_SS2A3", - "SS2A3" - ], - [ - "HCLK_SW6B2", - "SW6A2" - ], - [ - "HCLK_SS2END0", - "SS2A0" - ], - [ - "HCLK_SL1END3", - "SL1BEG3" - ], - [ - "HCLK_NE2BEG1", + "INT_INTERFACE_NE2A1", "NE2A1" ], [ - "HCLK_SW2END0", - "SW2BEG0" + "INT_INTERFACE_NE2A2", + "NE2A2" ], [ - "HCLK_SW6E2", - "SW6D2" + "INT_INTERFACE_NE2A3", + "NE2A3" ], [ - "HCLK_SW6C3", - "SW6B3" + "INT_INTERFACE_NE4BEG0", + "NE6BEG0" ], [ - "HCLK_NW6A1", - "NW6B1" + "INT_INTERFACE_NE4BEG1", + "NE6BEG1" ], [ - "HCLK_SL1END2", - "SL1BEG2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_L", - "HCLK_R" - ], - "wire_pairs": [ - [ - "HCLK_INT_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - "HCLK_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK0" - ], - [ - "HCLK_CCIO0", - "HCLK_CCIO0" - ], - [ - "HCLK_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ], - [ - "HCLK_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CK_OUTIN_L2", - "HCLK_CK_INOUT_R2" - ], - [ - "HCLK_CK_IN2", - "HCLK_CK_IN2" - ], - [ - "HCLK_CK_OUTIN_L5", - "HCLK_CK_INOUT_R5" - ], - [ - "HCLK_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK2" - ], - [ - "HCLK_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_CK_IN3", - "HCLK_CK_IN3" - ], - [ - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_CK_INOUT_L3", - "HCLK_CK_OUTIN_R7" - ], - [ - "HCLK_CK_OUTIN_L6", - "HCLK_CK_INOUT_R6" - ], - [ - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_CCIO1", - "HCLK_CCIO1" - ], - [ - "HCLK_CK_OUTIN_L7", - "HCLK_CK_INOUT_R7" - ], - [ - "HCLK_CK_INOUT_L1", - "HCLK_CK_OUTIN_R5" - ], - [ - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CK_OUTIN_L1", - "HCLK_CK_INOUT_R1" - ], - [ - "HCLK_CK_INOUT_L5", - "HCLK_CK_OUTIN_R1" - ], - [ - "HCLK_CK_INOUT_L2", - "HCLK_CK_OUTIN_R6" - ], - [ - "HCLK_CK_OUTIN_L4", - "HCLK_CK_INOUT_R4" - ], - [ - "HCLK_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_CK_OUTIN_L3", - "HCLK_CK_INOUT_R3" - ], - [ - "HCLK_CCIO3", - "HCLK_CCIO3" - ], - [ - "HCLK_CK_INOUT_L6", - "HCLK_CK_OUTIN_R2" - ], - [ - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CK_IN0", - "HCLK_CK_IN0" - ], - [ - "HCLK_CK_INOUT_L7", - "HCLK_CK_OUTIN_R3" - ], - [ - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CK_INOUT_L0", - "HCLK_CK_OUTIN_R4" - ], - [ - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CCIO2", - "HCLK_CCIO2" - ], - [ - "HCLK_CK_BUFRCLK3", - "HCLK_CK_BUFRCLK3" - ], - [ - "HCLK_INT_PERFCLK1", - "HCLK_INT_PERFCLK1" - ], - [ - "HCLK_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CK_OUTIN_L0", - "HCLK_CK_INOUT_R0" - ], - [ - "HCLK_INT_PERFCLK2", - "HCLK_INT_PERFCLK2" - ], - [ - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_CK_INOUT_L4", - "HCLK_CK_OUTIN_R0" - ], - [ - "HCLK_CK_IN1", - "HCLK_CK_IN1" - ], - [ - "HCLK_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_INT_PERFCLK3", - "HCLK_INT_PERFCLK3" - ] - ] - }, - { - "grid_deltas": [ - 1, - -3 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH7_6", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE4BEG2_6", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_SE2A2_6", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_WW2END1_6", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EL1BEG3_6", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE4C3_6", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_SW2A3_6", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_SE4BEG3_6", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NE2A0_6", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_ER1BEG0_6", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WL1END0_6", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4A3_6", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_NE4C3_6", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_SW2A2_6", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_NE4BEG3_6", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE4A1_6", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW4A2_6", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE2BEG0_6", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_ER1BEG3_6", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE2BEG2_6", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_NE2A2_6", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_LH8_6", - "VBRK_LH8" - ], - [ - "CLK_HROW_LH12_6", - "VBRK_LH12" - ], - [ - "CLK_HROW_EL1BEG0_6", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE2A2_6", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW2A0_6", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE2BEG3_6", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW4C3_6", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_SW4A0_6", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_SE4C1_6", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW2END0_6", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WR1END0_6", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_WW4B0_6", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_NW4A0_6", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EL1BEG2_6", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_SE4C0_6", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EL1BEG1_6", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE4A0_6", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_LH5_6", - "VBRK_LH5" - ], - [ - "CLK_HROW_LH2_6", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW2A1_6", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SE4C2_6", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_NE2A3_6", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW4C2_6", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_NW4A3_6", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_EE4B2_6", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_WW2END2_6", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_NW4END3_6", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_NE4C0_6", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_WR1END1_6", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW4END1_6", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW4END0_6", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_SW4END3_6", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_EE4A2_6", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_NE4BEG1_6", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_NW4END0_6", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_LH1_6", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW4END2_6", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WL1END3_6", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_ER1BEG1_6", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SE4C3_6", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WW4END3_6", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE2A1_6", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_SW2A1_6", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_EE4BEG3_6", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW4A1_6", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_EE4B0_6", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_LH9_6", - "VBRK_LH9" - ], - [ - "CLK_HROW_EE4BEG0_6", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4BEG1_6", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_WR1END2_6", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_NE4C1_6", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_SW4A1_6", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_MONITOR_N_6", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_LH4_6", - "VBRK_LH4" - ], - [ - "CLK_HROW_WW2A2_6", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WW4END0_6", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NW2A0_6", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_NE4C2_6", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW2END3_6", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_WW4C1_6", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SW4A2_6", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_EE4B1_6", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_NW2A2_6", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WW2A1_6", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_SE2A3_6", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_EE2A3_6", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_WW4C0_6", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_LH11_6", - "VBRK_LH11" - ], - [ - "CLK_HROW_SE2A0_6", - "VBRK_SE2A0" - ], - [ - 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"PCIE_IMUX1_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT1" - ], - [ - "PCIE_NE4C0_16", - "INT_INTERFACE_NE4C0" - ], - [ - "PCIE_LOGIC_OUTS_B6_R_16", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "PCIE_LOGIC_OUTS_B8_R_16", - "INT_INTERFACE_LOGIC_OUTS_B8" - ], - [ - "PCIE_LH6_16", - "INT_INTERFACE_LH6" - ], - [ - "PCIE_FAN7_R_16", - "INT_INTERFACE_FAN7" - ], - [ - "PCIE_NW4A3_16", - "INT_INTERFACE_NW4A3" - ], - [ - "PCIE_WW4B3_16", - "INT_INTERFACE_WW4B3" - ], - [ - "PCIE_WW4C2_16", - "INT_INTERFACE_WW4C2" - ], - [ - "PCIE_BYP2_R_16", - "INT_INTERFACE_BYP2" - ], - [ - "PCIE_BYP5_R_16", - "INT_INTERFACE_BYP5" - ], - [ - "PCIE_ER1BEG2_16", - "INT_INTERFACE_ER1BEG2" - ], - [ - "PCIE_FAN5_R_16", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_SW4A3_16", - "INT_INTERFACE_SW4A3" - ], - [ - "PCIE_IMUX33_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT33" - ], - [ - "PCIE_WL1END2_16", - "INT_INTERFACE_WL1END2" - ], - [ - "PCIE_FAN3_R_16", - "INT_INTERFACE_FAN3" - ], - [ - "PCIE_SW4END1_16", - "INT_INTERFACE_SW4END1" - ], - [ - "PCIE_IMUX14_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT14" - ], - [ - "PCIE_LH3_16", - "INT_INTERFACE_LH3" - ], - [ - "PCIE_SW2A2_16", - "INT_INTERFACE_SW2A2" - ], - [ - "PCIE_EE4A1_16", - "INT_INTERFACE_EE4A1" - ], - [ - "PCIE_NW2A1_16", - "INT_INTERFACE_NW2A1" - ], - [ - "PCIE_IMUX44_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT44" - ], - [ - "PCIE_BYP6_R_16", - "INT_INTERFACE_BYP6" - ], - [ - "PCIE_LOGIC_OUTS_B19_R_16", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "PCIE_SW2A0_16", - "INT_INTERFACE_SW2A0" - ], - [ - "PCIE_SE2A2_16", - "INT_INTERFACE_SE2A2" - ], - [ - "PCIE_WW2END1_16", - "INT_INTERFACE_WW2END1" - ], - [ - "PCIE_IMUX8_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT8" - ], - [ - "PCIE_IMUX5_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT5" - ], - [ - "PCIE_LH1_16", - "INT_INTERFACE_LH1" - ], - [ - "PCIE_WW4B0_16", - "INT_INTERFACE_WW4B0" - ], - [ - "PCIE_SE2A3_16", - "INT_INTERFACE_SE2A3" - ], - [ - "PCIE_IMUX29_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT29" - ], - [ - "PCIE_LOGIC_OUTS_B7_R_16", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "PCIE_WW2A2_16", - "INT_INTERFACE_WW2A2" - ], - [ - "PCIE_WW4B1_16", - "INT_INTERFACE_WW4B1" - ], - [ - "PCIE_BYP0_R_16", - "INT_INTERFACE_BYP0" - ], - [ - "PCIE_IMUX26_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT26" - ], - [ - "PCIE_FAN2_R_16", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_CTRL1_R_16", - "INT_INTERFACE_CTRL1" - ], - [ - "PCIE_IMUX11_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT11" - ], - [ - "PCIE_EE4B3_16", - "INT_INTERFACE_EE4B3" - ], - [ - "PCIE_IMUX20_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT20" - ], - [ - "PCIE_SE4BEG1_16", - "INT_INTERFACE_SE4BEG1" - ], - [ - "PCIE_LOGIC_OUTS_B20_R_16", - "INT_INTERFACE_LOGIC_OUTS_B20" - ], - [ - "PCIE_EE4B2_16", - "INT_INTERFACE_EE4B2" - ], - [ - "PCIE_IMUX40_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT40" - ], - [ - "PCIE_IMUX35_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT35" - ], - [ - "PCIE_WW4C0_16", - "INT_INTERFACE_WW4C0" - ], - [ - "PCIE_BYP7_R_16", - "INT_INTERFACE_BYP7" - ], - [ - "PCIE_EE4A3_16", - "INT_INTERFACE_EE4A3" - ], - [ - "PCIE_WW2A1_16", - "INT_INTERFACE_WW2A1" - ], - [ - "PCIE_NW4A0_16", - "INT_INTERFACE_NW4A0" - ], - [ - "PCIE_ER1BEG1_16", - "INT_INTERFACE_ER1BEG1" - ], - [ - "PCIE_EE4BEG0_16", - "INT_INTERFACE_EE4BEG0" - ], - [ - "PCIE_IMUX46_R_16", - "PCIE_INT_INTERFACE_IMUX_OUT46" - ], - [ - "PCIE_ER1BEG0_16", - "INT_INTERFACE_ER1BEG0" - ] - ] - }, - { - "grid_deltas": [ - -1, - -5 - ], - "tile_types": [ - "CFG_CENTER_TOP", - "INT_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "CFG_CENTER_NE2A2_5", - "INT_FEEDTHRU_2_NE2A2" - ], - [ - "CFG_CENTER_WL1END1_5", - "INT_FEEDTHRU_2_WL1END1" - ], - [ - "CFG_CENTER_NW4A0_5", - "INT_FEEDTHRU_2_NW4A0" - ], - [ - "CFG_CENTER_WW4B2_5", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_NW4A3_5", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_SE4BEG2_5", - "INT_FEEDTHRU_2_SE4BEG2" - ], - [ - "CFG_CENTER_EE2A1_5", - "INT_FEEDTHRU_2_EE2A1" - ], - [ - "CFG_CENTER_EL1BEG0_5", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_SW2A3_5", - "INT_FEEDTHRU_2_SW2A3" - ], - [ - "CFG_CENTER_NE4C0_5", - "INT_FEEDTHRU_2_NE4C0" - ], - [ - "CFG_CENTER_WW4A3_5", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_EE4B0_5", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_WW2END2_5", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_SE4C0_5", - "INT_FEEDTHRU_2_SE4C0" - ], - [ - "CFG_CENTER_ER1BEG2_5", - "INT_FEEDTHRU_2_ER1BEG2" - ], - [ - "CFG_CENTER_SW4A2_5", - "INT_FEEDTHRU_2_SW4A2" - ], - [ - "CFG_CENTER_SW4A0_5", - "INT_FEEDTHRU_2_SW4A0" - ], - [ - "CFG_CENTER_EE2BEG1_5", - "INT_FEEDTHRU_2_EE2BEG1" - ], - [ - "CFG_CENTER_WW2END0_5", - "INT_FEEDTHRU_2_WW2END0" - ], - [ - "CFG_CENTER_WW4END1_5", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_WR1END1_5", - "INT_FEEDTHRU_2_WR1END1" - ], - [ - "CFG_CENTER_EE2BEG2_5", - "INT_FEEDTHRU_2_EE2BEG2" - ], - [ - "CFG_CENTER_SE4BEG1_5", - "INT_FEEDTHRU_2_SE4BEG1" - ], - [ - "CFG_CENTER_NE2A3_5", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_EE4B3_5", - "INT_FEEDTHRU_2_EE4B3" - ], - [ - "CFG_CENTER_SW4A1_5", - "INT_FEEDTHRU_2_SW4A1" - ], - [ - "CFG_CENTER_EE4B1_5", - "INT_FEEDTHRU_2_EE4B1" - ], - [ - "CFG_CENTER_LH11_5", - "INT_FEEDTHRU_2_LH11" - ], - [ - "CFG_CENTER_NW2A0_5", - "INT_FEEDTHRU_2_NW2A0" - ], - [ - "CFG_CENTER_WW4C3_5", - "INT_FEEDTHRU_2_WW4C3" - ], - [ - "CFG_CENTER_SE4C1_5", - "INT_FEEDTHRU_2_SE4C1" - ], - [ - "CFG_CENTER_EL1BEG2_5", - "INT_FEEDTHRU_2_EL1BEG2" - ], - [ - "CFG_CENTER_LH5_5", - "INT_FEEDTHRU_2_LH5" - ], - [ - "CFG_CENTER_EE4C0_5", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_EE4BEG3_5", - "INT_FEEDTHRU_2_EE4BEG3" - ], - [ - "CFG_CENTER_EE4BEG2_5", - "INT_FEEDTHRU_2_EE4BEG2" - ], - [ - "CFG_CENTER_NW4A1_5", - "INT_FEEDTHRU_2_NW4A1" - ], - [ - "CFG_CENTER_EE4A0_5", - "INT_FEEDTHRU_2_EE4A0" - ], - [ - "CFG_CENTER_NW4END2_5", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_EE4A3_5", - "INT_FEEDTHRU_2_EE4A3" - ], - [ - "CFG_CENTER_WW2END1_5", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_EE2A3_5", - "INT_FEEDTHRU_2_EE2A3" - ], - [ - "CFG_CENTER_SE4C3_5", - "INT_FEEDTHRU_2_SE4C3" - ], - [ - "CFG_CENTER_NE4BEG1_5", - "INT_FEEDTHRU_2_NE4BEG1" - ], - [ - "CFG_CENTER_SW2A2_5", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_LH1_5", - "INT_FEEDTHRU_2_LH1" - ], - [ - "CFG_CENTER_EE4BEG0_5", - "INT_FEEDTHRU_2_EE4BEG0" - ], - [ - "CFG_CENTER_SW4END2_5", - "INT_FEEDTHRU_2_SW4END2" - ], - [ - "CFG_CENTER_WW4C2_5", - "INT_FEEDTHRU_2_WW4C2" - ], - [ - "CFG_CENTER_SW2A0_5", - "INT_FEEDTHRU_2_SW2A0" - ], - [ - "CFG_CENTER_WW4A0_5", - "INT_FEEDTHRU_2_WW4A0" + "INT_INTERFACE_NE4BEG2", + "NE6BEG2" ], [ - "CFG_CENTER_LH7_5", - "INT_FEEDTHRU_2_LH7" + "INT_INTERFACE_NE4BEG3", + "NE6BEG3" ], [ - "CFG_CENTER_NW2A2_5", - "INT_FEEDTHRU_2_NW2A2" + "INT_INTERFACE_NE4C0", + "NE6E0" ], [ - "CFG_CENTER_WW4B3_5", - "INT_FEEDTHRU_2_WW4B3" + "INT_INTERFACE_NE4C1", + "NE6E1" ], [ - "CFG_CENTER_WW4B0_5", - "INT_FEEDTHRU_2_WW4B0" + "INT_INTERFACE_NE4C2", + "NE6E2" ], [ - "CFG_CENTER_LH6_5", - "INT_FEEDTHRU_2_LH6" + "INT_INTERFACE_NE4C3", + "NE6E3" ], [ - "CFG_CENTER_WL1END0_5", - "INT_FEEDTHRU_2_WL1END0" + "INT_INTERFACE_NW2A0", + "NW2END0" ], [ - "CFG_CENTER_EE4BEG1_5", - "INT_FEEDTHRU_2_EE4BEG1" + "INT_INTERFACE_NW2A1", + "NW2END1" ], [ - "CFG_CENTER_ER1BEG3_5", - "INT_FEEDTHRU_2_ER1BEG3" + "INT_INTERFACE_NW2A2", + "NW2END2" ], [ - "CFG_CENTER_NW4END1_5", - "INT_FEEDTHRU_2_NW4END1" + "INT_INTERFACE_NW2A3", + "NW2END3" ], [ - "CFG_CENTER_LH10_5", - "INT_FEEDTHRU_2_LH10" + "INT_INTERFACE_NW4A0", + "NW6A0" ], [ - "CFG_CENTER_SW2A1_5", - "INT_FEEDTHRU_2_SW2A1" + "INT_INTERFACE_NW4A1", + "NW6A1" ], [ - "CFG_CENTER_WW4B1_5", - "INT_FEEDTHRU_2_WW4B1" + "INT_INTERFACE_NW4A2", + "NW6A2" ], [ - "CFG_CENTER_EE4B2_5", - "INT_FEEDTHRU_2_EE4B2" + "INT_INTERFACE_NW4A3", + "NW6A3" ], [ - "CFG_CENTER_WW2A3_5", - "INT_FEEDTHRU_2_WW2A3" + "INT_INTERFACE_NW4END0", + "NW6END0" ], [ - "CFG_CENTER_WW4END2_5", - "INT_FEEDTHRU_2_WW4END2" + "INT_INTERFACE_NW4END1", + "NW6END1" ], [ - "CFG_CENTER_LH3_5", - "INT_FEEDTHRU_2_LH3" + "INT_INTERFACE_NW4END2", + "NW6END2" ], [ - "CFG_CENTER_WW4END3_5", - "INT_FEEDTHRU_2_WW4END3" + "INT_INTERFACE_NW4END3", + "NW6END3" ], [ - "CFG_CENTER_LH2_5", - "INT_FEEDTHRU_2_LH2" + "INT_INTERFACE_SE2A0", + "SE2A0" ], [ - "CFG_CENTER_LH8_5", - "INT_FEEDTHRU_2_LH8" + "INT_INTERFACE_SE2A1", + "SE2A1" ], [ - "CFG_CENTER_LH12_5", - "INT_FEEDTHRU_2_LH12" + "INT_INTERFACE_SE2A2", + "SE2A2" ], [ - "CFG_CENTER_NE4BEG2_5", - "INT_FEEDTHRU_2_NE4BEG2" + "INT_INTERFACE_SE2A3", + "SE2A3" ], [ - "CFG_CENTER_EE2A0_5", - "INT_FEEDTHRU_2_EE2A0" + "INT_INTERFACE_SE4BEG0", + "SE6BEG0" ], [ - "CFG_CENTER_EE4C2_5", - "INT_FEEDTHRU_2_EE4C2" + "INT_INTERFACE_SE4BEG1", + "SE6BEG1" ], [ - "CFG_CENTER_ER1BEG1_5", - "INT_FEEDTHRU_2_ER1BEG1" + "INT_INTERFACE_SE4BEG2", + "SE6BEG2" ], [ - "CFG_CENTER_NW4A2_5", - "INT_FEEDTHRU_2_NW4A2" + "INT_INTERFACE_SE4BEG3", + "SE6BEG3" ], [ - "CFG_CENTER_NW4END3_5", - "INT_FEEDTHRU_2_NW4END3" + "INT_INTERFACE_SE4C0", + "SE6E0" ], [ - "CFG_CENTER_NE2A0_5", - "INT_FEEDTHRU_2_NE2A0" + "INT_INTERFACE_SE4C1", + "SE6E1" ], [ - "CFG_CENTER_NE4BEG3_5", - "INT_FEEDTHRU_2_NE4BEG3" + "INT_INTERFACE_SE4C2", + "SE6E2" ], [ - "CFG_CENTER_SE2A3_5", - "INT_FEEDTHRU_2_SE2A3" + "INT_INTERFACE_SE4C3", + "SE6E3" ], [ - "CFG_CENTER_EE4C1_5", - "INT_FEEDTHRU_2_EE4C1" + "INT_INTERFACE_SW2A0", + "SW2END0" ], [ - "CFG_CENTER_SE4BEG0_5", - "INT_FEEDTHRU_2_SE4BEG0" + "INT_INTERFACE_SW2A1", + "SW2END1" ], [ - "CFG_CENTER_WR1END2_5", - "INT_FEEDTHRU_2_WR1END2" + "INT_INTERFACE_SW2A2", + "SW2END2" ], [ - "CFG_CENTER_SW4END0_5", - "INT_FEEDTHRU_2_SW4END0" + "INT_INTERFACE_SW2A3", + "SW2END3" ], [ - "CFG_CENTER_WW4A2_5", - "INT_FEEDTHRU_2_WW4A2" + "INT_INTERFACE_SW4A0", + "SW6A0" ], [ - "CFG_CENTER_SE2A0_5", - "INT_FEEDTHRU_2_SE2A0" + "INT_INTERFACE_SW4A1", + "SW6A1" ], [ - "CFG_CENTER_NE4C2_5", - "INT_FEEDTHRU_2_NE4C2" + "INT_INTERFACE_SW4A2", + "SW6A2" ], [ - "CFG_CENTER_SW4END3_5", - "INT_FEEDTHRU_2_SW4END3" + "INT_INTERFACE_SW4A3", + "SW6A3" ], [ - "CFG_CENTER_SW4END1_5", - "INT_FEEDTHRU_2_SW4END1" + "INT_INTERFACE_SW4END0", + "SW6END0" ], [ - "CFG_CENTER_WL1END3_5", - "INT_FEEDTHRU_2_WL1END3" + "INT_INTERFACE_SW4END1", + "SW6END1" ], [ - "CFG_CENTER_LH4_5", - "INT_FEEDTHRU_2_LH4" + "INT_INTERFACE_SW4END2", + "SW6END2" ], [ - "CFG_CENTER_NW2A3_5", - "INT_FEEDTHRU_2_NW2A3" + "INT_INTERFACE_SW4END3", + "SW6END3" ], [ - "CFG_CENTER_SE4C2_5", - "INT_FEEDTHRU_2_SE4C2" + "INT_INTERFACE_WL1END0", + "WL1END0" ], [ - "CFG_CENTER_WW4END0_5", - "INT_FEEDTHRU_2_WW4END0" + "INT_INTERFACE_WL1END1", + "WL1END1" ], [ - "CFG_CENTER_LH9_5", - "INT_FEEDTHRU_2_LH9" + "INT_INTERFACE_WL1END2", + "WL1END2" ], [ - "CFG_CENTER_SE2A2_5", - "INT_FEEDTHRU_2_SE2A2" + "INT_INTERFACE_WL1END3", + "WL1END3" ], [ - "CFG_CENTER_SE4BEG3_5", - "INT_FEEDTHRU_2_SE4BEG3" + "INT_INTERFACE_WR1END0", + "WR1END0" ], [ - "CFG_CENTER_EE2A2_5", - "INT_FEEDTHRU_2_EE2A2" + "INT_INTERFACE_WR1END1", + "WR1END1" ], [ - "CFG_CENTER_WR1END3_5", - "INT_FEEDTHRU_2_WR1END3" + "INT_INTERFACE_WR1END2", + "WR1END2" ], [ - "CFG_CENTER_EE4A1_5", - "INT_FEEDTHRU_2_EE4A1" + "INT_INTERFACE_WR1END3", + "WR1END3" ], [ - "CFG_CENTER_WW4A1_5", - "INT_FEEDTHRU_2_WW4A1" + "INT_INTERFACE_WW2A0", + "WW2A0" ], [ - "CFG_CENTER_WL1END2_5", - "INT_FEEDTHRU_2_WL1END2" + "INT_INTERFACE_WW2A1", + "WW2A1" ], [ - "CFG_CENTER_NE2A1_5", - "INT_FEEDTHRU_2_NE2A1" + "INT_INTERFACE_WW2A2", + "WW2A2" ], [ - "CFG_CENTER_EL1BEG3_5", - "INT_FEEDTHRU_2_EL1BEG3" + "INT_INTERFACE_WW2A3", + "WW2A3" ], [ - "CFG_CENTER_WW2A2_5", - "INT_FEEDTHRU_2_WW2A2" + "INT_INTERFACE_WW2END0", + "WW2END0" ], [ - "CFG_CENTER_EE2BEG3_5", - "INT_FEEDTHRU_2_EE2BEG3" + "INT_INTERFACE_WW2END1", + "WW2END1" ], [ - "CFG_CENTER_WW2END3_5", - "INT_FEEDTHRU_2_WW2END3" + "INT_INTERFACE_WW2END2", + "WW2END2" ], [ - "CFG_CENTER_SE2A1_5", - "INT_FEEDTHRU_2_SE2A1" + "INT_INTERFACE_WW2END3", + "WW2END3" ], [ - "CFG_CENTER_NW2A1_5", - "INT_FEEDTHRU_2_NW2A1" + "INT_INTERFACE_WW4A0", + "WW4A0" ], [ - "CFG_CENTER_WR1END0_5", - "INT_FEEDTHRU_2_WR1END0" + "INT_INTERFACE_WW4A1", + "WW4A1" ], [ - "CFG_CENTER_NW4END0_5", - "INT_FEEDTHRU_2_NW4END0" + "INT_INTERFACE_WW4A2", + "WW4A2" ], [ - "CFG_CENTER_EE4C3_5", - "INT_FEEDTHRU_2_EE4C3" + "INT_INTERFACE_WW4A3", + "WW4A3" ], [ - "CFG_CENTER_NE4C1_5", - "INT_FEEDTHRU_2_NE4C1" + "INT_INTERFACE_WW4B0", + "WW4B0" ], [ - "CFG_CENTER_EE4A2_5", - "INT_FEEDTHRU_2_EE4A2" + "INT_INTERFACE_WW4B1", + "WW4B1" ], [ - "CFG_CENTER_WW2A1_5", - "INT_FEEDTHRU_2_WW2A1" + "INT_INTERFACE_WW4B2", + "WW4B2" ], [ - "CFG_CENTER_WW4C1_5", - "INT_FEEDTHRU_2_WW4C1" + "INT_INTERFACE_WW4B3", + "WW4B3" ], [ - "CFG_CENTER_SW4A3_5", - "INT_FEEDTHRU_2_SW4A3" + "INT_INTERFACE_WW4C0", + "WW4C0" ], [ - "CFG_CENTER_EE2BEG0_5", - "INT_FEEDTHRU_2_EE2BEG0" + "INT_INTERFACE_WW4C1", + "WW4C1" ], [ - "CFG_CENTER_ER1BEG0_5", - "INT_FEEDTHRU_2_ER1BEG0" + "INT_INTERFACE_WW4C2", + "WW4C2" ], [ - "CFG_CENTER_WW2A0_5", - "INT_FEEDTHRU_2_WW2A0" + "INT_INTERFACE_WW4C3", + "WW4C3" ], [ - "CFG_CENTER_NE4BEG0_5", - "INT_FEEDTHRU_2_NE4BEG0" + "INT_INTERFACE_WW4END0", + "WW4END0" ], [ - "CFG_CENTER_WW4C0_5", - "INT_FEEDTHRU_2_WW4C0" + "INT_INTERFACE_WW4END1", + "WW4END1" ], [ - "CFG_CENTER_NE4C3_5", - "INT_FEEDTHRU_2_NE4C3" + "INT_INTERFACE_WW4END2", + "WW4END2" ], [ - "CFG_CENTER_EL1BEG1_5", - "INT_FEEDTHRU_2_EL1BEG1" + "INT_INTERFACE_WW4END3", + "WW4END3" ] ] }, @@ -6477,65 +12537,129 @@ "BRAM_L" ], "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRAM_CASCOUT_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRAM_CASCOUT_ADDRARDADDRU2" + ], [ "BRAM_CASCINTOP_ADDRARDADDRU3", "BRAM_CASCOUT_ADDRARDADDRU3" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRAM_CASCOUT_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRAM_CASCOUT_ADDRBWRADDRU13" + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_CASCOUT_ADDRARDADDRU4" ], [ "BRAM_CASCINTOP_ADDRARDADDRU5", "BRAM_CASCOUT_ADDRARDADDRU5" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRAM_CASCOUT_ADDRBWRADDRU6" + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRAM_CASCOUT_ADDRARDADDRU6" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRAM_CASCOUT_ADDRBWRADDRU2" + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRAM_CASCOUT_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRARDADDRU9" ], [ "BRAM_CASCINTOP_ADDRARDADDRU10", "BRAM_CASCOUT_ADDRARDADDRU10" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU7" + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU11" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRAM_CASCOUT_ADDRARDADDRU6" + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU12" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU9" + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU13" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRAM_CASCOUT_ADDRARDADDRU0" + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_CASCOUT_ADDRARDADDRU14" ], [ - "BRAM_PMVBRAM_O", - "BRAM_PMVBRAM_O_1" + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRAM_CASCOUT_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRAM_CASCOUT_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRAM_CASCOUT_ADDRBWRADDRU4" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU5", "BRAM_CASCOUT_ADDRBWRADDRU5" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRAM_CASCOUT_ADDRARDADDRU2" + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRAM_CASCOUT_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRAM_CASCOUT_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRAM_CASCOUT_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRAM_CASCOUT_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRAM_CASCOUT_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRAM_CASCOUT_ADDRBWRADDRU14" + ], + [ + "BRAM_PMVBRAM_O", + "BRAM_PMVBRAM_O_1" ], [ "BRAM_PMVBRAM_ODIV2", @@ -6544,6218 +12668,406 @@ [ "BRAM_PMVBRAM_O_1", "BRAM_PMVBRAM_O_2" + ] + ] + }, + { + "grid_deltas": [ + 0, + 5 + ], + "tile_types": [ + "BRAM_L", + "BRAM_L" + ], + "wire_pairs": [ + [ + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRAM_CASCOUT_ADDRARDADDRU0" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRAM_CASCOUT_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRAM_CASCOUT_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRAM_CASCOUT_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRAM_CASCOUT_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRAM_CASCOUT_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRAM_CASCOUT_ADDRARDADDRU12" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRAM_CASCOUT_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRAM_CASCOUT_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_CASCINBOT_ADDRARDADDRU1", "BRAM_CASCOUT_ADDRARDADDRU1" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU11" + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRAM_CASCOUT_ADDRARDADDRU2" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU0" + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRAM_CASCOUT_ADDRARDADDRU3" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_CASCINBOT_ADDRARDADDRU4", "BRAM_CASCOUT_ADDRARDADDRU4" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRAM_CASCOUT_ADDRARDADDRU8" + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRAM_CASCOUT_ADDRARDADDRU5" ], [ - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRAM_CASCOUT_ADDRBWRADDRU1" + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRAM_CASCOUT_ADDRARDADDRU6" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_CASCINBOT_ADDRARDADDRU7", "BRAM_CASCOUT_ADDRARDADDRU7" ], [ - "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRAM_CASCOUT_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRAM_CASCOUT_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", "BRAM_CASCOUT_ADDRARDADDRU14" - ] - ] - }, - { - "grid_deltas": [ - -1, - 5 - ], - "tile_types": [ - "CMT_FIFO_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CMT_FIFO_L_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CMT_FIFO_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CMT_FIFO_L_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CMT_FIFO_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CMT_FIFO_L_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CMT_FIFO_L_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CMT_FIFO_L_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CMT_FIFO_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CMT_FIFO_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS0_1", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CMT_FIFO_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CMT_FIFO_L_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CMT_FIFO_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CMT_FIFO_L_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS22_1", - "INT_INTERFACE_LOGIC_OUTS_B22" - ], - [ - "CMT_FIFO_L_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CMT_FIFO_L_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CMT_FIFO_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CMT_FIFO_L_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CMT_FIFO_L_BYP4_1", - "INT_INTERFACE_BYP4" - ], - [ - "CMT_FIFO_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CMT_FIFO_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CMT_FIFO_L_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "CMT_FIFO_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CMT_FIFO_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "CMT_FIFO_L_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CMT_FIFO_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS19_1", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "CMT_FIFO_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "CMT_FIFO_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CMT_FIFO_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CMT_FIFO_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CMT_FIFO_L_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CMT_FIFO_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CMT_FIFO_L_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CMT_FIFO_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "CMT_FIFO_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CMT_FIFO_L_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CMT_FIFO_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS7_1", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CMT_FIFO_L_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "CMT_FIFO_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CMT_FIFO_L_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CMT_FIFO_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS21_1", - "INT_INTERFACE_LOGIC_OUTS_B21" - ], - [ - "CMT_FIFO_L_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CMT_FIFO_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CMT_FIFO_L_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CMT_FIFO_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CMT_FIFO_L_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CMT_FIFO_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CMT_FIFO_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CMT_FIFO_L_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS4_1", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CMT_FIFO_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CMT_FIFO_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CMT_FIFO_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CMT_FIFO_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS20_1", - "INT_INTERFACE_LOGIC_OUTS_B20" - ], - [ - "CMT_FIFO_L_IMUX10_1", - "INT_INTERFACE_IMUX10" - ], - [ - "CMT_FIFO_L_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CMT_FIFO_L_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CMT_FIFO_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CMT_FIFO_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CMT_FIFO_NW4END3_1", - "INT_INTERFACE_NW4END3" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS8_1", - "INT_INTERFACE_LOGIC_OUTS_B8" - ], - [ - "CMT_FIFO_L_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CMT_FIFO_L_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CMT_FIFO_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "CMT_FIFO_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CMT_FIFO_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CMT_FIFO_L_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CMT_FIFO_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CMT_FIFO_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "CMT_FIFO_L_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CMT_FIFO_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CMT_FIFO_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CMT_FIFO_SW2A0_1", - "INT_INTERFACE_SW2A0" - ], - [ - "CMT_FIFO_L_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CMT_FIFO_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CMT_FIFO_L_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CMT_FIFO_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CMT_FIFO_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CMT_FIFO_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CMT_FIFO_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CMT_FIFO_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CMT_FIFO_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CMT_FIFO_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CMT_FIFO_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CMT_FIFO_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CMT_FIFO_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CMT_FIFO_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CMT_FIFO_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CMT_FIFO_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CMT_FIFO_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CMT_FIFO_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CMT_FIFO_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CMT_FIFO_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CMT_FIFO_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CMT_FIFO_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CMT_FIFO_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CMT_FIFO_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CMT_FIFO_L_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CMT_FIFO_L_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CMT_FIFO_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CMT_FIFO_L_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "CMT_FIFO_L_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS16_1", - "INT_INTERFACE_LOGIC_OUTS_B16" - ], - [ - "CMT_FIFO_L_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS5_1", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CMT_FIFO_L_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CMT_FIFO_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CMT_FIFO_PHASER_TO_IO_ICLK_1", - "INT_INTERFACE_PHASER_TO_IO_ICLK" - ], - [ - "CMT_FIFO_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CMT_FIFO_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CMT_FIFO_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS15_1", - "INT_INTERFACE_LOGIC_OUTS_B15" - ], - [ - "CMT_FIFO_L_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS6_1", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CMT_FIFO_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" - ], - [ - "CMT_FIFO_L_IMUX5_1", - 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"DSP_LH3_3", - "VBRK_LH3" - ], - [ - "DSP_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "DSP_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "DSP_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "DSP_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "DSP_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "DSP_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "DSP_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "DSP_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - "DSP_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "DSP_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "DSP_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "DSP_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "DSP_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "DSP_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "DSP_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "DSP_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "DSP_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "DSP_LH10_3", - "VBRK_LH10" - ], - [ - "DSP_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "DSP_MONITOR_N_3", - "VBRK_MONITOR_N" - ], - [ - "DSP_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "DSP_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "DSP_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "DSP_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "DSP_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "DSP_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "DSP_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "DSP_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "DSP_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "DSP_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "DSP_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "DSP_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "DSP_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "DSP_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "DSP_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "DSP_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "DSP_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "DSP_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "DSP_LH7_3", - "VBRK_LH7" - ], - [ - "DSP_LH2_3", - "VBRK_LH2" - ], - [ - "DSP_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "DSP_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "DSP_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "DSP_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "DSP_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "DSP_LH5_3", - "VBRK_LH5" - ], - [ - "DSP_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "DSP_LH4_3", - "VBRK_LH4" - ], - [ - "DSP_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "DSP_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "DSP_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "DSP_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "DSP_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "DSP_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "DSP_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "DSP_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "DSP_LH8_3", - "VBRK_LH8" - ], - [ - "DSP_LH11_3", - "VBRK_LH11" - ], - [ - "DSP_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "DSP_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "DSP_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "DSP_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "DSP_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "DSP_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "DSP_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "DSP_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "DSP_MONITOR_P_3", - "VBRK_MONITOR_P" - ], - [ - "DSP_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "DSP_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "DSP_LH12_3", - "VBRK_LH12" - ], - [ - "DSP_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "DSP_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "DSP_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "DSP_LH1_3", - "VBRK_LH1" - ], - [ - "DSP_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "DSP_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "DSP_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "DSP_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "DSP_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "DSP_NE4C3_3", - "VBRK_NE4C3" ], [ - "DSP_NE4C1_3", - "VBRK_NE4C1" + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRAM_CASCOUT_ADDRBWRADDRU0" ], [ - "DSP_SW2A3_3", - "VBRK_SW2A3" + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU1" ], [ - "DSP_WW4C2_3", - "VBRK_WW4C2" + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRAM_CASCOUT_ADDRBWRADDRU2" ], [ - "DSP_EE4B2_3", - "VBRK_EE4B2" + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3" ], [ - "DSP_SW4A2_3", - "VBRK_SW4A2" + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRAM_CASCOUT_ADDRBWRADDRU4" ], [ - "DSP_NE2A3_3", - "VBRK_NE2A3" + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU5" ], [ - "DSP_EE4C3_3", - "VBRK_EE4C3" + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRAM_CASCOUT_ADDRBWRADDRU6" ], [ - "DSP_NW4A0_3", - "VBRK_NW4A0" + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRAM_CASCOUT_ADDRBWRADDRU7" ], [ - "DSP_SE2A3_3", - "VBRK_SE2A3" + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU8" ], [ - "DSP_WW4B3_3", - "VBRK_WW4B3" + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU9" ], [ - "DSP_NW4END2_3", - "VBRK_NW4END2" + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRAM_CASCOUT_ADDRBWRADDRU10" ], [ - "DSP_LH9_3", - "VBRK_LH9" + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRAM_CASCOUT_ADDRBWRADDRU11" ], [ - "DSP_EE2BEG2_3", - "VBRK_EE2BEG2" + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRAM_CASCOUT_ADDRBWRADDRU12" ], [ - "DSP_WW4C1_3", - "VBRK_WW4C1" + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU13" ], [ - "DSP_EE4BEG0_3", - "VBRK_EE4BEG0" + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRAM_CASCOUT_ADDRBWRADDRU14" ], [ - "DSP_NW4END1_3", - "VBRK_NW4END1" + "BRAM_FIFO36_CASCADEINA", + "BRAM_FIFO36_CASCADEOUTA_1" ], [ - "DSP_WW4C3_3", - "VBRK_WW4C3" + "BRAM_FIFO36_CASCADEINB", + "BRAM_FIFO36_CASCADEOUTB_1" ] ] }, { "grid_deltas": [ 0, - 5 - ], - "tile_types": [ - "CLK_FEED", - "CLK_HROW_TOP_R" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN24" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN31" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN21" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN30" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_HROW_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN25" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN1" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN15" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN0" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN19" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN20" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN6" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN26" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN3" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN18" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN11" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN5" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN23" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN29" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN8" - 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"CLK_HROW_WW4END1_7", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EE4C2_7", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_SW2A2_7", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4B3_7", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_EL1BEG0_7", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW2END1_7", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_NW4END0_7", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_NE2A0_7", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WW4B2_7", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_LH7_7", - "VBRK_LH7" - ], - [ - "CLK_HROW_WW4B3_7", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_LH2_7", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW2A3_7", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WW4A0_7", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_LH12_7", - "VBRK_LH12" - ], - [ - "CLK_HROW_NE4C3_7", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_LH11_7", - "VBRK_LH11" - ], - [ - "CLK_HROW_WW2A1_7", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_NE4BEG0_7", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WW4END3_7", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SE2A0_7", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_NE2A2_7", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE4BEG3_7", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NW4END3_7", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_NW4A0_7", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_LH4_7", - "VBRK_LH4" - ] - ] - }, - { - "grid_deltas": [ - -1, - 6 - ], - "tile_types": [ - "CFG_CENTER_BOT", - "INT_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "CFG_CENTER_EE4BEG3_4", - "INT_FEEDTHRU_2_EE4BEG3" - ], - [ - "CFG_CENTER_EE4C2_4", - "INT_FEEDTHRU_2_EE4C2" - ], - [ - "CFG_CENTER_LH3_4", - "INT_FEEDTHRU_2_LH3" - ], - [ - "CFG_CENTER_WW4END2_4", - "INT_FEEDTHRU_2_WW4END2" - ], - [ - "CFG_CENTER_NE2A3_4", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_WW4A1_4", - "INT_FEEDTHRU_2_WW4A1" - ], - [ - "CFG_CENTER_EE4B3_4", - "INT_FEEDTHRU_2_EE4B3" - ], - [ - "CFG_CENTER_WR1END1_4", - "INT_FEEDTHRU_2_WR1END1" - ], - [ - "CFG_CENTER_SW4END3_4", - "INT_FEEDTHRU_2_SW4END3" - ], - [ - "CFG_CENTER_NE2A0_4", - "INT_FEEDTHRU_2_NE2A0" - ], - [ - "CFG_CENTER_SE2A3_4", - "INT_FEEDTHRU_2_SE2A3" - ], - [ - "CFG_CENTER_EE2A3_4", - "INT_FEEDTHRU_2_EE2A3" - ], - [ - "CFG_CENTER_WW4B1_4", - "INT_FEEDTHRU_2_WW4B1" - ], - [ - "CFG_CENTER_SW4END2_4", - "INT_FEEDTHRU_2_SW4END2" - ], - [ - "CFG_CENTER_EE2A1_4", - "INT_FEEDTHRU_2_EE2A1" - ], - [ - "CFG_CENTER_LH12_4", - "INT_FEEDTHRU_2_LH12" - ], - [ - "CFG_CENTER_EE4C3_4", - "INT_FEEDTHRU_2_EE4C3" - ], - [ - "CFG_CENTER_EE4C1_4", - "INT_FEEDTHRU_2_EE4C1" - ], - [ - "CFG_CENTER_NW4A2_4", - "INT_FEEDTHRU_2_NW4A2" - ], - [ - "CFG_CENTER_EE4A0_4", - "INT_FEEDTHRU_2_EE4A0" - ], - [ - "CFG_CENTER_NE4C1_4", - "INT_FEEDTHRU_2_NE4C1" - ], - [ - "CFG_CENTER_NW4A3_4", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_NW2A0_4", - "INT_FEEDTHRU_2_NW2A0" - ], - [ - "CFG_CENTER_SW2A1_4", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_NE2A1_4", - "INT_FEEDTHRU_2_NE2A1" - ], - [ - "CFG_CENTER_EL1BEG1_4", - "INT_FEEDTHRU_2_EL1BEG1" - ], - [ - "CFG_CENTER_WW4C0_4", - "INT_FEEDTHRU_2_WW4C0" - ], - [ - "CFG_CENTER_EE2A0_4", - "INT_FEEDTHRU_2_EE2A0" - ], - [ - "CFG_CENTER_WR1END0_4", - "INT_FEEDTHRU_2_WR1END0" - ], - [ - "CFG_CENTER_EE4BEG2_4", - "INT_FEEDTHRU_2_EE4BEG2" - ], - [ - "CFG_CENTER_SW4END1_4", - "INT_FEEDTHRU_2_SW4END1" - ], - [ - "CFG_CENTER_WW4A2_4", - "INT_FEEDTHRU_2_WW4A2" - ], - [ - "CFG_CENTER_NW4A1_4", - "INT_FEEDTHRU_2_NW4A1" - ], - [ - "CFG_CENTER_ER1BEG0_4", - "INT_FEEDTHRU_2_ER1BEG0" - ], - [ - "CFG_CENTER_WW4C3_4", - "INT_FEEDTHRU_2_WW4C3" - ], - [ - "CFG_CENTER_WL1END0_4", - "INT_FEEDTHRU_2_WL1END0" - ], - [ - "CFG_CENTER_EE4B1_4", - "INT_FEEDTHRU_2_EE4B1" - ], - [ - "CFG_CENTER_WR1END2_4", - "INT_FEEDTHRU_2_WR1END2" - ], - [ - "CFG_CENTER_SE4C2_4", - "INT_FEEDTHRU_2_SE4C2" - ], - [ - "CFG_CENTER_WW2A0_4", - "INT_FEEDTHRU_2_WW2A0" - ], - [ - "CFG_CENTER_SW4A2_4", - "INT_FEEDTHRU_2_SW4A2" - ], - [ - "CFG_CENTER_WL1END2_4", - "INT_FEEDTHRU_2_WL1END2" - ], - [ - "CFG_CENTER_NE4BEG2_4", - "INT_FEEDTHRU_2_NE4BEG2" - ], - [ - "CFG_CENTER_WW4END0_4", - "INT_FEEDTHRU_2_WW4END0" - ], - [ - "CFG_CENTER_NE4BEG1_4", - "INT_FEEDTHRU_2_NE4BEG1" - ], - [ - "CFG_CENTER_WW2END1_4", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_EE4BEG1_4", - "INT_FEEDTHRU_2_EE4BEG1" - ], - [ - "CFG_CENTER_EE4BEG0_4", - "INT_FEEDTHRU_2_EE4BEG0" - ], - [ - "CFG_CENTER_SE4C1_4", - "INT_FEEDTHRU_2_SE4C1" - ], - [ - "CFG_CENTER_WW4A0_4", - "INT_FEEDTHRU_2_WW4A0" - ], - [ - "CFG_CENTER_NW4A0_4", - "INT_FEEDTHRU_2_NW4A0" - ], - [ - "CFG_CENTER_EE2BEG1_4", - "INT_FEEDTHRU_2_EE2BEG1" - ], - [ - "CFG_CENTER_ER1BEG2_4", - "INT_FEEDTHRU_2_ER1BEG2" - ], - [ - "CFG_CENTER_EE4A3_4", - "INT_FEEDTHRU_2_EE4A3" - ], - [ - "CFG_CENTER_EE2A2_4", - "INT_FEEDTHRU_2_EE2A2" - ], - [ - "CFG_CENTER_WW4B3_4", - "INT_FEEDTHRU_2_WW4B3" - ], - [ - "CFG_CENTER_WW4C1_4", - "INT_FEEDTHRU_2_WW4C1" - ], - [ - "CFG_CENTER_NE4C3_4", - "INT_FEEDTHRU_2_NE4C3" - ], - [ - "CFG_CENTER_EE4C0_4", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_WW4C2_4", - "INT_FEEDTHRU_2_WW4C2" - ], - [ - "CFG_CENTER_EE2BEG3_4", - "INT_FEEDTHRU_2_EE2BEG3" - ], - [ - "CFG_CENTER_SW2A3_4", - "INT_FEEDTHRU_2_SW2A3" - ], - [ - "CFG_CENTER_SW4A3_4", - "INT_FEEDTHRU_2_SW4A3" - ], - [ - "CFG_CENTER_SE2A1_4", - "INT_FEEDTHRU_2_SE2A1" - ], - [ - "CFG_CENTER_WW4END3_4", - "INT_FEEDTHRU_2_WW4END3" - ], - [ - "CFG_CENTER_WW4END1_4", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_LH2_4", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_SE4BEG1_4", - "INT_FEEDTHRU_2_SE4BEG1" - ], - [ - "CFG_CENTER_NW2A3_4", - "INT_FEEDTHRU_2_NW2A3" - ], - [ - "CFG_CENTER_LH6_4", - "INT_FEEDTHRU_2_LH6" - ], - [ - "CFG_CENTER_SW4A0_4", - "INT_FEEDTHRU_2_SW4A0" - ], - [ - "CFG_CENTER_LH4_4", - "INT_FEEDTHRU_2_LH4" - ], - [ - "CFG_CENTER_SW2A0_4", - "INT_FEEDTHRU_2_SW2A0" - ], - [ - "CFG_CENTER_NE2A2_4", - "INT_FEEDTHRU_2_NE2A2" - ], - [ - "CFG_CENTER_EE4B2_4", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_NW4END3_4", - "INT_FEEDTHRU_2_NW4END3" - ], - [ - "CFG_CENTER_ER1BEG1_4", - "INT_FEEDTHRU_2_ER1BEG1" - ], - [ - "CFG_CENTER_NW2A2_4", - "INT_FEEDTHRU_2_NW2A2" - ], - [ - "CFG_CENTER_EE4A2_4", - "INT_FEEDTHRU_2_EE4A2" - ], - [ - "CFG_CENTER_SE4BEG0_4", - "INT_FEEDTHRU_2_SE4BEG0" - ], - [ - "CFG_CENTER_WW4B0_4", - "INT_FEEDTHRU_2_WW4B0" - ], - [ - "CFG_CENTER_WW2END0_4", - "INT_FEEDTHRU_2_WW2END0" - ], - [ - "CFG_CENTER_EL1BEG0_4", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_NW4END0_4", - "INT_FEEDTHRU_2_NW4END0" - ], - [ - "CFG_CENTER_LH8_4", - "INT_FEEDTHRU_2_LH8" - ], - [ - "CFG_CENTER_ER1BEG3_4", - "INT_FEEDTHRU_2_ER1BEG3" - ], - [ - "CFG_CENTER_NE4BEG3_4", - "INT_FEEDTHRU_2_NE4BEG3" - ], - [ - "CFG_CENTER_SW4END0_4", - "INT_FEEDTHRU_2_SW4END0" - ], - [ - "CFG_CENTER_SW2A2_4", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_NW4END1_4", - "INT_FEEDTHRU_2_NW4END1" - ], - [ - "CFG_CENTER_WW2END2_4", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_SE4BEG3_4", - "INT_FEEDTHRU_2_SE4BEG3" - ], - [ - "CFG_CENTER_LH11_4", - "INT_FEEDTHRU_2_LH11" - ], - [ - "CFG_CENTER_EE2BEG0_4", - "INT_FEEDTHRU_2_EE2BEG0" - ], - [ - "CFG_CENTER_SE4C0_4", - "INT_FEEDTHRU_2_SE4C0" - ], - [ - "CFG_CENTER_WL1END1_4", - "INT_FEEDTHRU_2_WL1END1" - ], - [ - "CFG_CENTER_WW2A2_4", - "INT_FEEDTHRU_2_WW2A2" - ], - [ - "CFG_CENTER_SE2A2_4", - "INT_FEEDTHRU_2_SE2A2" - ], - [ - "CFG_CENTER_LH5_4", - "INT_FEEDTHRU_2_LH5" - ], - [ - "CFG_CENTER_NE4C2_4", - "INT_FEEDTHRU_2_NE4C2" - ], - [ - "CFG_CENTER_NW2A1_4", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_EE4A1_4", - "INT_FEEDTHRU_2_EE4A1" - ], - [ - "CFG_CENTER_SW4A1_4", - "INT_FEEDTHRU_2_SW4A1" - ], - [ - "CFG_CENTER_LH1_4", - "INT_FEEDTHRU_2_LH1" - ], - [ - "CFG_CENTER_EE2BEG2_4", - "INT_FEEDTHRU_2_EE2BEG2" - ], - [ - "CFG_CENTER_NE4C0_4", - "INT_FEEDTHRU_2_NE4C0" - ], - [ - "CFG_CENTER_WR1END3_4", - "INT_FEEDTHRU_2_WR1END3" - ], - [ - "CFG_CENTER_NW4END2_4", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_SE2A0_4", - "INT_FEEDTHRU_2_SE2A0" - ], - [ - "CFG_CENTER_WL1END3_4", - "INT_FEEDTHRU_2_WL1END3" - ], - [ - "CFG_CENTER_LH7_4", - "INT_FEEDTHRU_2_LH7" - ], - [ - "CFG_CENTER_WW2A1_4", - "INT_FEEDTHRU_2_WW2A1" - ], - [ - "CFG_CENTER_WW4B2_4", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_EL1BEG3_4", - "INT_FEEDTHRU_2_EL1BEG3" - ], - [ - "CFG_CENTER_LH10_4", - "INT_FEEDTHRU_2_LH10" - ], - [ - "CFG_CENTER_WW2END3_4", - "INT_FEEDTHRU_2_WW2END3" - ], - [ - "CFG_CENTER_SE4C3_4", - "INT_FEEDTHRU_2_SE4C3" - ], - [ - "CFG_CENTER_EL1BEG2_4", - "INT_FEEDTHRU_2_EL1BEG2" - ], - [ - "CFG_CENTER_WW4A3_4", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_EE4B0_4", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_WW2A3_4", - "INT_FEEDTHRU_2_WW2A3" - ], - [ - "CFG_CENTER_LH9_4", - "INT_FEEDTHRU_2_LH9" - ], - [ - "CFG_CENTER_NE4BEG0_4", - "INT_FEEDTHRU_2_NE4BEG0" - ], - [ - "CFG_CENTER_SE4BEG2_4", - "INT_FEEDTHRU_2_SE4BEG2" - ] - ] - }, - { - "grid_deltas": [ - -1, -5 ], "tile_types": [ - "CFG_CENTER_BOT", - "INT_FEEDTHRU_2" + "BRAM_L", + "BRKH_BRAM" ], "wire_pairs": [ [ - "CFG_CENTER_WW4A2_15", - "INT_FEEDTHRU_2_WW4A2" + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ - "CFG_CENTER_EE4A1_15", - "INT_FEEDTHRU_2_EE4A1" + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ - "CFG_CENTER_EE4BEG3_15", - "INT_FEEDTHRU_2_EE4BEG3" + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ - "CFG_CENTER_NW2A2_15", - "INT_FEEDTHRU_2_NW2A2" + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ - "CFG_CENTER_SW4A3_15", - "INT_FEEDTHRU_2_SW4A3" + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ - "CFG_CENTER_EE2BEG2_15", - "INT_FEEDTHRU_2_EE2BEG2" + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ - "CFG_CENTER_SW4A2_15", - "INT_FEEDTHRU_2_SW4A2" + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ - "CFG_CENTER_EE4C1_15", - "INT_FEEDTHRU_2_EE4C1" + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ - "CFG_CENTER_SE4BEG0_15", - "INT_FEEDTHRU_2_SE4BEG0" + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ - "CFG_CENTER_SE2A3_15", - "INT_FEEDTHRU_2_SE2A3" + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ - "CFG_CENTER_LH10_15", - "INT_FEEDTHRU_2_LH10" + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ - "CFG_CENTER_WW2A3_15", - "INT_FEEDTHRU_2_WW2A3" + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ - "CFG_CENTER_EE4B1_15", - "INT_FEEDTHRU_2_EE4B1" + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ - "CFG_CENTER_EE4BEG1_15", - "INT_FEEDTHRU_2_EE4BEG1" + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ - "CFG_CENTER_EE4A3_15", - "INT_FEEDTHRU_2_EE4A3" + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ - "CFG_CENTER_WL1END0_15", - "INT_FEEDTHRU_2_WL1END0" + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ - "CFG_CENTER_LH12_15", - "INT_FEEDTHRU_2_LH12" + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ - "CFG_CENTER_ER1BEG3_15", - "INT_FEEDTHRU_2_ER1BEG3" + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ - "CFG_CENTER_WW2END0_15", - "INT_FEEDTHRU_2_WW2END0" + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ - "CFG_CENTER_NW4END0_15", - "INT_FEEDTHRU_2_NW4END0" + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ - "CFG_CENTER_SE4C3_15", - "INT_FEEDTHRU_2_SE4C3" + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ - "CFG_CENTER_NW4A2_15", - "INT_FEEDTHRU_2_NW4A2" + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ - "CFG_CENTER_ER1BEG2_15", - "INT_FEEDTHRU_2_ER1BEG2" + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ - "CFG_CENTER_WW4A0_15", - "INT_FEEDTHRU_2_WW4A0" + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ - "CFG_CENTER_WW4C1_15", - "INT_FEEDTHRU_2_WW4C1" + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ - "CFG_CENTER_EE2A3_15", - "INT_FEEDTHRU_2_EE2A3" + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ - "CFG_CENTER_WW4A1_15", - "INT_FEEDTHRU_2_WW4A1" + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ - "CFG_CENTER_WR1END3_15", - "INT_FEEDTHRU_2_WR1END3" + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ - "CFG_CENTER_SW4END2_15", - "INT_FEEDTHRU_2_SW4END2" + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ - "CFG_CENTER_SW2A3_15", - "INT_FEEDTHRU_2_SW2A3" + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ - "CFG_CENTER_LH11_15", - "INT_FEEDTHRU_2_LH11" + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ - "CFG_CENTER_WW2END3_15", - "INT_FEEDTHRU_2_WW2END3" + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ - "CFG_CENTER_EE4A2_15", - "INT_FEEDTHRU_2_EE4A2" + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ - "CFG_CENTER_LH5_15", - "INT_FEEDTHRU_2_LH5" + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ - "CFG_CENTER_NW4A3_15", - "INT_FEEDTHRU_2_NW4A3" + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ - "CFG_CENTER_WR1END0_15", - "INT_FEEDTHRU_2_WR1END0" + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ - "CFG_CENTER_SE4C1_15", - "INT_FEEDTHRU_2_SE4C1" + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ - "CFG_CENTER_NW4A0_15", - "INT_FEEDTHRU_2_NW4A0" + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ - "CFG_CENTER_EL1BEG1_15", - "INT_FEEDTHRU_2_EL1BEG1" + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ - "CFG_CENTER_NW2A0_15", - "INT_FEEDTHRU_2_NW2A0" + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ - "CFG_CENTER_NE4BEG3_15", - "INT_FEEDTHRU_2_NE4BEG3" + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ - "CFG_CENTER_WL1END2_15", - "INT_FEEDTHRU_2_WL1END2" + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ - "CFG_CENTER_NE4BEG0_15", - "INT_FEEDTHRU_2_NE4BEG0" + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ - "CFG_CENTER_WW4END3_15", - "INT_FEEDTHRU_2_WW4END3" + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ - "CFG_CENTER_NW2A3_15", - "INT_FEEDTHRU_2_NW2A3" + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ - "CFG_CENTER_EE4BEG0_15", - "INT_FEEDTHRU_2_EE4BEG0" + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ - "CFG_CENTER_WW4C2_15", - "INT_FEEDTHRU_2_WW4C2" + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ - "CFG_CENTER_NW4END3_15", - "INT_FEEDTHRU_2_NW4END3" + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ - "CFG_CENTER_NE4BEG2_15", - "INT_FEEDTHRU_2_NE4BEG2" + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ - "CFG_CENTER_WW4END0_15", - "INT_FEEDTHRU_2_WW4END0" + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ - "CFG_CENTER_EE4B3_15", - "INT_FEEDTHRU_2_EE4B3" + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ - "CFG_CENTER_WW4END2_15", - "INT_FEEDTHRU_2_WW4END2" + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ - "CFG_CENTER_SE4BEG2_15", - "INT_FEEDTHRU_2_SE4BEG2" + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ - "CFG_CENTER_LH2_15", - "INT_FEEDTHRU_2_LH2" + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ - "CFG_CENTER_EE4A0_15", - "INT_FEEDTHRU_2_EE4A0" + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ - "CFG_CENTER_LH8_15", - "INT_FEEDTHRU_2_LH8" + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ - "CFG_CENTER_NW4A1_15", - "INT_FEEDTHRU_2_NW4A1" + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ - "CFG_CENTER_SE2A0_15", - "INT_FEEDTHRU_2_SE2A0" + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ - "CFG_CENTER_SW2A0_15", - "INT_FEEDTHRU_2_SW2A0" + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ - "CFG_CENTER_WW4C0_15", - "INT_FEEDTHRU_2_WW4C0" + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ - "CFG_CENTER_NE4C0_15", - "INT_FEEDTHRU_2_NE4C0" + "BRAM_FIFO36_CASCADEOUTA_1", + "BRKH_BRAM_CASCADEA_L" ], [ - "CFG_CENTER_EL1BEG0_15", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_EE4BEG2_15", - "INT_FEEDTHRU_2_EE4BEG2" - ], - [ - "CFG_CENTER_SW2A2_15", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_NW4END1_15", - "INT_FEEDTHRU_2_NW4END1" - ], - [ - "CFG_CENTER_SW4A0_15", - "INT_FEEDTHRU_2_SW4A0" - ], - [ - "CFG_CENTER_SE2A2_15", - "INT_FEEDTHRU_2_SE2A2" - ], - [ - "CFG_CENTER_SE4BEG1_15", - "INT_FEEDTHRU_2_SE4BEG1" - ], - [ - "CFG_CENTER_NE2A0_15", - "INT_FEEDTHRU_2_NE2A0" - ], - [ - "CFG_CENTER_NE2A2_15", - "INT_FEEDTHRU_2_NE2A2" - ], - [ - "CFG_CENTER_EE2BEG0_15", - "INT_FEEDTHRU_2_EE2BEG0" - ], - [ - "CFG_CENTER_LH4_15", - "INT_FEEDTHRU_2_LH4" - ], - [ - "CFG_CENTER_EE2A0_15", - "INT_FEEDTHRU_2_EE2A0" - ], - [ - "CFG_CENTER_WW4B3_15", - "INT_FEEDTHRU_2_WW4B3" - ], - [ - "CFG_CENTER_WR1END2_15", - "INT_FEEDTHRU_2_WR1END2" - ], - [ - "CFG_CENTER_NE2A3_15", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_NE4C3_15", - "INT_FEEDTHRU_2_NE4C3" - ], - [ - "CFG_CENTER_SW4END0_15", - "INT_FEEDTHRU_2_SW4END0" - ], - [ - "CFG_CENTER_SW4END3_15", - "INT_FEEDTHRU_2_SW4END3" - ], - [ - "CFG_CENTER_EE2BEG1_15", - "INT_FEEDTHRU_2_EE2BEG1" - ], - [ - "CFG_CENTER_LH1_15", - "INT_FEEDTHRU_2_LH1" - ], - [ - "CFG_CENTER_EE2A1_15", - "INT_FEEDTHRU_2_EE2A1" - ], - [ - "CFG_CENTER_ER1BEG1_15", - "INT_FEEDTHRU_2_ER1BEG1" - ], - [ - "CFG_CENTER_LH7_15", - "INT_FEEDTHRU_2_LH7" - ], - [ - "CFG_CENTER_EE4C3_15", - "INT_FEEDTHRU_2_EE4C3" - ], - [ - "CFG_CENTER_EE2A2_15", - "INT_FEEDTHRU_2_EE2A2" - ], - [ - "CFG_CENTER_SW2A1_15", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_NE2A1_15", - "INT_FEEDTHRU_2_NE2A1" - ], - [ - "CFG_CENTER_WW4B0_15", - "INT_FEEDTHRU_2_WW4B0" - ], - [ - "CFG_CENTER_SE4BEG3_15", - "INT_FEEDTHRU_2_SE4BEG3" - ], - [ - "CFG_CENTER_SW4A1_15", - "INT_FEEDTHRU_2_SW4A1" - ], - [ - "CFG_CENTER_LH3_15", - "INT_FEEDTHRU_2_LH3" - ], - [ - "CFG_CENTER_SE4C0_15", - "INT_FEEDTHRU_2_SE4C0" - ], - [ - "CFG_CENTER_WW2A2_15", - "INT_FEEDTHRU_2_WW2A2" - ], - [ - "CFG_CENTER_WW4END1_15", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_NE4C2_15", - "INT_FEEDTHRU_2_NE4C2" - ], - [ - "CFG_CENTER_WW4C3_15", - "INT_FEEDTHRU_2_WW4C3" - ], - [ - "CFG_CENTER_NW4END2_15", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_WL1END3_15", - "INT_FEEDTHRU_2_WL1END3" - ], - [ - "CFG_CENTER_EE2BEG3_15", - "INT_FEEDTHRU_2_EE2BEG3" - ], - [ - "CFG_CENTER_SE4C2_15", - "INT_FEEDTHRU_2_SE4C2" - ], - [ - "CFG_CENTER_WW4B2_15", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_WL1END1_15", - "INT_FEEDTHRU_2_WL1END1" - ], - [ - "CFG_CENTER_LH6_15", - "INT_FEEDTHRU_2_LH6" - ], - [ - "CFG_CENTER_WW4A3_15", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_EL1BEG3_15", - "INT_FEEDTHRU_2_EL1BEG3" - ], - [ - "CFG_CENTER_NE4BEG1_15", - "INT_FEEDTHRU_2_NE4BEG1" - ], - [ - "CFG_CENTER_WW2END1_15", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_NW2A1_15", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_SE2A1_15", - "INT_FEEDTHRU_2_SE2A1" - ], - [ - "CFG_CENTER_WW4B1_15", - "INT_FEEDTHRU_2_WW4B1" - ], - [ - "CFG_CENTER_SW4END1_15", - "INT_FEEDTHRU_2_SW4END1" - ], - [ - "CFG_CENTER_EE4C0_15", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_WW2A1_15", - "INT_FEEDTHRU_2_WW2A1" - ], - [ - "CFG_CENTER_EE4C2_15", - "INT_FEEDTHRU_2_EE4C2" - ], - [ - "CFG_CENTER_EE4B0_15", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_LH9_15", - "INT_FEEDTHRU_2_LH9" - ], - [ - "CFG_CENTER_EE4B2_15", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_WW2A0_15", - "INT_FEEDTHRU_2_WW2A0" - ], - [ - "CFG_CENTER_NE4C1_15", - "INT_FEEDTHRU_2_NE4C1" - ], - [ - "CFG_CENTER_EL1BEG2_15", - "INT_FEEDTHRU_2_EL1BEG2" - ], - [ - "CFG_CENTER_WW2END2_15", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_ER1BEG0_15", - "INT_FEEDTHRU_2_ER1BEG0" - ], - [ - "CFG_CENTER_WR1END1_15", - "INT_FEEDTHRU_2_WR1END1" - ] - ] - }, - { - "grid_deltas": [ - 1, - -2 - ], - "tile_types": [ - "CMT_TOP_R_UPPER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW2END3_7", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_WW4C1_7", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_LH6_7", - "VBRK_LH6" - ], - [ - "CMT_TOP_SW4END0_7", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_EE4B2_7", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_ER1BEG2_7", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_EE4BEG3_7", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_SE2A2_7", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_NE4C1_7", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_WR1END0_7", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_LH5_7", - "VBRK_LH5" - ], - [ - "CMT_TOP_WW2A0_7", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_WW4A0_7", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WL1END1_7", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_EE2BEG3_7", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_LH9_7", - "VBRK_LH9" - ], - [ - "CMT_TOP_ER1BEG1_7", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_SW4END3_7", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_WW4A1_7", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_SW4END2_7", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WR1END2_7", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_EE2A3_7", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_WW4B2_7", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_SE4BEG2_7", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_WW4B0_7", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_WW4C3_7", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_WW4END1_7", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_NE4C0_7", - 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[ - "PCIE_ER1BEG2_5", - "INT_INTERFACE_ER1BEG2" - ], - [ - "PCIE_EL1BEG2_5", - "INT_INTERFACE_EL1BEG2" - ], - [ - "PCIE_IMUX15_R_5", - "PCIE_INT_INTERFACE_IMUX_OUT15" - ], - [ - "PCIE_LOGIC_OUTS_B21_R_5", - "INT_INTERFACE_LOGIC_OUTS_B21" - ], - [ - "PCIE_LH5_5", - "INT_INTERFACE_LH5" - ], - [ - "PCIE_WW4END1_5", - "INT_INTERFACE_WW4END1" - ], - [ - "PCIE_EL1BEG0_5", - "INT_INTERFACE_EL1BEG0" - ], - [ - "PCIE_LH7_5", - "INT_INTERFACE_LH7" - ], - [ - "PCIE_IMUX0_R_5", - "PCIE_INT_INTERFACE_IMUX_OUT0" - ], - [ - "PCIE_IMUX8_R_5", - "PCIE_INT_INTERFACE_IMUX_OUT8" - ], - [ - "PCIE_WW2A3_5", - "INT_INTERFACE_WW2A3" - ], - [ - "PCIE_BYP7_R_5", - "INT_INTERFACE_BYP7" - ], - [ - "PCIE_BYP6_R_5", - "INT_INTERFACE_BYP6" + "BRAM_FIFO36_CASCADEOUTB_1", + "BRKH_BRAM_CASCADEB_L" ] ] }, @@ -12765,1705 +13077,1289 @@ 1 ], "tile_types": [ - "BRKH_TERM_INT", - "INT_R" + "BRAM_L", + "BRKH_BRAM" ], "wire_pairs": [ [ - "T_TERM_UTURN_INT_SS6B2", - "NN6A1" + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ - "T_TERM_UTURN_INT_SE6E3", - "SE6E3" + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ - "T_TERM_UTURN_INT_WR1END_S1_0", - "WL1END3" + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ - "T_TERM_UTURN_INT_SS6B3", - "NN6A0" + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", - "BYP_BOUNCE7" + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ - "T_TERM_INT_UTURN_LV_R17", - "LV0" + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ - "T_TERM_UTURN_INT_SE6E3", - "NE6D0" + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ - "T_TERM_UTURN_INT_SS6D0", - "SS6D0" + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ - "T_TERM_UTURN_INT_SW2A2", - "SW2A2" + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ - "T_TERM_UTURN_INT_SS6E1", - "NN6D2" + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ - "T_TERM_UTURN_INT_SE6E0", - "NE6D3" + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ - "T_TERM_UTURN_INT_SS6D3", - "NN6C0" + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ - "T_TERM_UTURN_INT_SW6D3", - "SW6D3" + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ - "T_TERM_UTURN_INT_LVB4", - "LVB4" + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ - "T_TERM_UTURN_INT_SL1END0_SLOW", - "NR1BEG3" + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ - "T_TERM_UTURN_INT_SE6C2", - "NE6B1" + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ - "T_TERM_UTURN_INT_SS2END0", - "SS2END0" + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ - "T_TERM_UTURN_INT_SW6E0", - "SW6E0" + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ - "T_TERM_UTURN_INT_SW6D2", - "SW6D2" + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ - "T_TERM_UTURN_INT_WR1END_S1_0", - "WR1END_S1_0" + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ - "T_TERM_UTURN_INT_SS6E3", - "SS6E3" + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ - "T_TERM_UTURN_INT_SR1END3_SLOW", - "SR1END3" + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ - "T_TERM_UTURN_INT_SE2A1", - "SE2A1" + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ - "T_TERM_UTURN_INT_SS6END2", - "SS6END2" + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", - "BYP_BOUNCE3" + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ - "T_TERM_UTURN_INT_LVB4", - "LVB7" + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ - "T_TERM_UTURN_INT_SS2A1", - "SS2A1" + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ - "T_TERM_UTURN_INT_SW6C2", - "SW6C2" + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ - "T_TERM_UTURN_INT_SW6D0", - "NW6C3" + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ - "T_TERM_UTURN_INT_SS6D0", - "NN6C3" + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ - "T_TERM_UTURN_INT_SS2A2", - "NN2BEG1" + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ - "T_TERM_UTURN_INT_SL1END3_SLOW", - "NR1BEG0" + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ - "T_TERM_UTURN_INT_SS6B2", - "SS6B2" + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ - "T_TERM_UTURN_INT_SW6B1", - "NW6A2" + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ - "T_TERM_UTURN_INT_SW2A2", - "NW2BEG1" + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ - "T_TERM_UTURN_INT_SW6D0", - "SW6D0" + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ - "T_TERM_UTURN_INT_SS2A3", - "SS2A3" + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ - "T_TERM_UTURN_INT_SS2END2", - "SS2END2" + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ - "T_TERM_UTURN_INT_SW2A3", - "NW2BEG0" + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ - "T_TERM_UTURN_INT_SE6C3", - "NE6B0" + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ - "T_TERM_INT_UTURN_LV_R3", - "LV14" + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ - "T_TERM_INT_UTURN_LV_R6", - "LV6" + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ - "T_TERM_UTURN_INT_SW6B3", - "NW6A0" + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ - "T_TERM_UTURN_INT_SE6E2", - "NE6D1" + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ - "T_TERM_UTURN_INT_SE2A1", - "NE2BEG2" + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ - "T_TERM_UTURN_INT_SE6B3", - "SE6B3" + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ - "T_TERM_UTURN_INT_SE6C0", - "NE6B3" + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ - "T_TERM_INT_UTURN_LV_R3", - "LV3" + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ - "T_TERM_UTURN_INT_SR1END1_SLOW", - "NL1BEG2" + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ - "T_TERM_UTURN_INT_WR1BEG_S0", - "WL1BEG3" + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ - "T_TERM_UTURN_INT_SS6C3", - "SS6C3" + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ - "T_TERM_UTURN_INT_SR1END1_SLOW", - "SR1END1" + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ - "T_TERM_UTURN_INT_SE2A2", - "SE2A2" + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ - "T_TERM_UTURN_INT_SS2END3", - "SS2END3" + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ - "T_TERM_UTURN_INT_SS6END2", - "NN6E1" + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ - "T_TERM_UTURN_INT_LVB1", - "LVB1" + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ - "T_TERM_UTURN_INT_SE6D1", - "SE6D1" + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ - "T_TERM_INT_UTURN_LV_R4", - "LV13" + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ - "T_TERM_UTURN_INT_SS6END1", - "SS6END1" + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ - "T_TERM_INT_UTURN_LV_R5", - "LV5" + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ - "T_TERM_UTURN_INT_SR1END2_SLOW", - "SR1END2" + "BRAM_FIFO36_CASCADEINA", + "BRKH_BRAM_CASCADEA_L" ], [ - "T_TERM_UTURN_INT_SS2A0", - "SS2A0" - ], - [ - "T_TERM_UTURN_INT_SS2A1", - "NN2BEG2" - ], - [ - "T_TERM_UTURN_INT_SS2END3", - "NN2A0" - ], - [ - "T_TERM_UTURN_INT_SW6C0", - "SW6C0" - ], - [ - "T_TERM_UTURN_INT_LVB2", - "LVB2" - ], - [ - "T_TERM_INT_UTURN_LV_R7", - "LV10" - ], - [ - "T_TERM_UTURN_INT_SS6C1", - "SS6C1" - ], - [ - "T_TERM_UTURN_INT_SS6B0", - "SS6B0" - ], - [ - "T_TERM_INT_UTURN_LV_R6", - "LV11" - ], - [ - "T_TERM_UTURN_INT_SS6END3", - "NN6E0" - ], - [ - "T_TERM_UTURN_INT_SS6B0", - "NN6A3" - ], - [ - "T_TERM_UTURN_INT_SS2END1", - "NN2A2" - ], - [ - "T_TERM_UTURN_INT_SW6E3", - "NW6D0" - ], - [ - "T_TERM_UTURN_INT_SE6B0", - "SE6B0" - ], - [ - "T_TERM_UTURN_INT_SE6C2", - "SE6C2" - ], - [ - "T_TERM_INT_UTURN_LV_R7", - "LV7" - ], - [ - "T_TERM_UTURN_INT_ER1BEG_S0", - "ER1BEG_S0" - ], - [ - "T_TERM_UTURN_INT_LVB5", - "LVB6" - ], - [ - "T_TERM_UTURN_INT_SE6E2", - "SE6E2" - ], - [ - "T_TERM_UTURN_INT_SE6E0", - "SE6E0" - ], - [ - "T_TERM_UTURN_INT_SE6B2", - "NE6A1" - ], - [ - "T_TERM_UTURN_INT_SE2A3", - "NE2BEG0" - ], - [ - "T_TERM_UTURN_INT_SW6C1", - "SW6C1" - ], - [ - "T_TERM_UTURN_INT_LVB2", - "LVB9" - ], - [ - "T_TERM_UTURN_INT_SS6D2", - "NN6C1" - ], - [ - "T_TERM_UTURN_INT_SW6E1", - "NW6D2" - ], - [ - "T_TERM_UTURN_INT_LVB0", - "LVB11" - ], - [ - "T_TERM_UTURN_INT_SE2A0", - "SE2A0" - ], - [ - "T_TERM_UTURN_INT_SS6A0", - "NN6BEG3" - ], - [ - "T_TERM_UTURN_INT_SE6D2", - "SE6D2" - ], - [ - "T_TERM_UTURN_INT_SE2A2", - "NE2BEG1" - ], - [ - "T_TERM_UTURN_INT_SS6C2", - "NN6B1" - ], - [ - "T_TERM_INT_UTURN_LV_R2", - "LV2" - ], - [ - "T_TERM_UTURN_INT_SW6D1", - "NW6C2" - ], - [ - "T_TERM_UTURN_INT_SW6E3", - "SW6E3" - ], - [ - "T_TERM_UTURN_INT_SS6END0", - "NN6E3" - ], - [ - "T_TERM_UTURN_INT_SE6C1", - "SE6C1" - ], - [ - "T_TERM_UTURN_INT_SS6E3", - "NN6D0" - ], - [ - "T_TERM_UTURN_INT_SS6E1", - "SS6E1" - ], - [ - "T_TERM_UTURN_INT_SE6C1", - "NE6B2" - ], - [ - "T_TERM_UTURN_INT_SS6E0", - "SS6E0" - ], - [ - "T_TERM_UTURN_INT_ER1END3", - "EL1END_S3_0" - ], - [ - "T_TERM_UTURN_INT_SS6E2", - "NN6D1" - ], - [ - "T_TERM_UTURN_INT_SE6B1", - "NE6A2" - ], - [ - "T_TERM_INT_UTURN_LV_R16", - "LV16" - ], - [ - "T_TERM_UTURN_INT_SW6B0", - "SW6B0" - ], - [ - "T_TERM_UTURN_INT_SE6D3", - "NE6C0" - ], - [ - "T_TERM_UTURN_INT_SW2A0", - "SW2A0" - ], - [ - "T_TERM_UTURN_INT_SE6D0", - "NE6C3" - ], - [ - "T_TERM_UTURN_INT_SS6C3", - "NN6B0" - ], - [ - "T_TERM_UTURN_INT_SE6D3", - "SE6D3" - ], - [ - "T_TERM_INT_UTURN_LV_R16", - "LV1" - ], - [ - "T_TERM_UTURN_INT_ER1BEG_S0", - "EL1BEG3" - ], - [ - "T_TERM_UTURN_INT_SS6C2", - "SS6C2" - ], - [ - "T_TERM_UTURN_INT_SW6C3", - "SW6C3" - ], - [ - "T_TERM_UTURN_INT_SW6D1", - "SW6D1" - ], - [ - "T_TERM_UTURN_INT_SS2END0", - "NN2A3" - ], - [ - "T_TERM_UTURN_INT_SW6C3", - "NW6B0" - ], - [ - "T_TERM_UTURN_INT_SW2A0", - "NW2BEG3" - ], - [ - "T_TERM_UTURN_INT_SW6B0", - "NW6A3" - ], - [ - "T_TERM_UTURN_INT_SE6D0", - "SE6D0" - ], - [ - "T_TERM_UTURN_INT_SS6END1", - "NN6E2" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "BYP_BOUNCE2" - ], - [ - "T_TERM_UTURN_INT_SE6D2", - "NE6C1" - ], - [ - "T_TERM_INT_UTURN_LV_R2", - "LV15" - ], - [ - "T_TERM_UTURN_INT_SS6END0", - "SS6END0" - ], - [ - "T_TERM_UTURN_INT_SS6A0", - "SS6A0" - ], - [ - "T_TERM_UTURN_INT_SL1END1_SLOW", - "NR1BEG2" - ], - [ - "T_TERM_UTURN_INT_WR1BEG_S0", - "WR1BEG_S0" - ], - [ - "T_TERM_UTURN_INT_SS2END1", - "SS2END1" - ], - [ - "T_TERM_UTURN_INT_SE6D1", - "NE6C2" - ], - [ - "T_TERM_UTURN_INT_LVB3", - "LVB8" - ], - [ - "T_TERM_UTURN_INT_SW2A3", - "SW2A3" - ], - [ - "T_TERM_UTURN_INT_LVB3", - "LVB3" - ], - [ - "T_TERM_UTURN_INT_SS6D3", - "SS6D3" - ], - [ - "T_TERM_UTURN_INT_SL1END3_SLOW", - "SL1END3" - ], - [ - "T_TERM_INT_UTURN_LV_R17", - "LV17" - ], - [ - "T_TERM_UTURN_INT_SE6B0", - "NE6A3" - ], - [ - "T_TERM_UTURN_INT_SW6B2", - "NW6A1" - ], - [ - "T_TERM_UTURN_INT_SR1END3_SLOW", - "NL1BEG0" - ], - [ - "T_TERM_UTURN_INT_SS6A2", - "NN6BEG1" - ], - [ - "T_TERM_UTURN_INT_SS6B3", - "SS6B3" - ], - [ - "T_TERM_UTURN_INT_SW2A1", - "SW2A1" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "FAN_BOUNCE_S3_6" - ], - [ - "T_TERM_UTURN_INT_SS6A3", - "NN6BEG0" - ], - [ - "T_TERM_UTURN_INT_SS6A3", - "SS6A3" - ], - [ - "T_TERM_UTURN_INT_SS2A0", - "NN2BEG3" - ], - [ - "T_TERM_UTURN_INT_SS6END3", - "SS6END3" - ], - [ - "T_TERM_UTURN_INT_LVB0", - "LVB0" - ], - [ - "T_TERM_UTURN_INT_SS6C1", - "NN6B2" - ], - [ - "T_TERM_UTURN_INT_SE6C3", - "SE6C3" - ], - [ - "T_TERM_UTURN_INT_SW6D3", - "NW6C0" - ], - [ - "T_TERM_UTURN_INT_SW6B2", - "SW6B2" - ], - [ - "T_TERM_INT_UTURN_LV_R9", - "LV8" - ], - [ - "T_TERM_UTURN_INT_SW6B3", - "SW6B3" - ], - [ - "T_TERM_UTURN_INT_SS6C0", - "NN6B3" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_2" - ], - [ - "T_TERM_UTURN_INT_SS6A2", - "SS6A2" - ], - [ - "T_TERM_INT_UTURN_LV_R5", - "LV12" - ], - [ - "T_TERM_UTURN_INT_SE6B2", - "SE6B2" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_0" - ], - [ - "T_TERM_UTURN_INT_SS6A1", - "NN6BEG2" - ], - [ - "T_TERM_UTURN_INT_SW6E0", - "NW6D3" - ], - [ - "T_TERM_UTURN_INT_SS6A1", - "SS6A1" - ], - [ - "T_TERM_UTURN_INT_LVB5", - "LVB5" - ], - [ - "T_TERM_UTURN_INT_SS6D2", - "SS6D2" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", - "BYP_BOUNCE6" - ], - [ - "T_TERM_UTURN_INT_SW6E2", - "NW6D1" - ], - [ - "T_TERM_UTURN_INT_SW6E2", - "SW6E2" - ], - [ - "T_TERM_UTURN_INT_SS6E2", - "SS6E2" - ], - [ - "T_TERM_INT_UTURN_LV_R9", - "LV9" - ], - [ - "T_TERM_UTURN_INT_SE6B1", - "SE6B1" - ], - [ - "T_TERM_UTURN_INT_SS2A2", - "SS2A2" - ], - [ - "T_TERM_UTURN_INT_LVB1", - "LVB10" - ], - [ - "T_TERM_UTURN_INT_SW6E1", - "SW6E1" - ], - [ - "T_TERM_UTURN_INT_SW6C0", - "NW6B3" - ], - [ - "T_TERM_UTURN_INT_ER1END3", - "ER1END3" - ], - [ - "T_TERM_UTURN_INT_SL1END2_SLOW", - "NR1BEG1" - ], - [ - "T_TERM_UTURN_INT_SW6C2", - "NW6B1" - ], - [ - "T_TERM_UTURN_INT_SL1END0_SLOW", - "SL1END0" - ], - [ - "T_TERM_UTURN_INT_SS6E0", - "NN6D3" - ], - [ - "T_TERM_UTURN_INT_SE2A0", - "NE2BEG3" - ], - [ - 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"CLBLM_WL1END2" + ], + [ + "BRAM_WL1END3_4", + "CLBLM_WL1END3" + ], + [ + "BRAM_WR1END0_4", + "CLBLM_WR1END0" + ], + [ + "BRAM_WR1END1_4", + "CLBLM_WR1END1" + ], + [ + "BRAM_WR1END2_4", + "CLBLM_WR1END2" + ], + [ + "BRAM_WR1END3_4", + "CLBLM_WR1END3" + ], + [ + "BRAM_WW2A0_4", + "CLBLM_WW2A0" + ], + [ + "BRAM_WW2A1_4", + "CLBLM_WW2A1" + ], + [ + "BRAM_WW2A2_4", + "CLBLM_WW2A2" + ], + [ + "BRAM_WW2A3_4", + "CLBLM_WW2A3" + ], + [ + "BRAM_WW2END0_4", + "CLBLM_WW2END0" + ], + [ + "BRAM_WW2END1_4", + "CLBLM_WW2END1" + ], + [ + "BRAM_WW2END2_4", + "CLBLM_WW2END2" + ], + [ + "BRAM_WW2END3_4", + "CLBLM_WW2END3" + ], + [ + "BRAM_WW4A0_4", + "CLBLM_WW4A0" + ], + [ + "BRAM_WW4A1_4", + "CLBLM_WW4A1" + ], + [ + "BRAM_WW4A2_4", + "CLBLM_WW4A2" + ], + [ + "BRAM_WW4A3_4", + "CLBLM_WW4A3" + ], + [ + "BRAM_WW4B0_4", + "CLBLM_WW4B0" + ], + [ + "BRAM_WW4B1_4", + "CLBLM_WW4B1" + ], + [ + "BRAM_WW4B2_4", + "CLBLM_WW4B2" + ], + [ + "BRAM_WW4B3_4", + "CLBLM_WW4B3" + ], + [ + "BRAM_WW4C0_4", + "CLBLM_WW4C0" + ], + [ + "BRAM_WW4C1_4", + "CLBLM_WW4C1" + ], + [ + "BRAM_WW4C2_4", + "CLBLM_WW4C2" + ], + [ + "BRAM_WW4C3_4", + "CLBLM_WW4C3" + ], + [ + "BRAM_WW4END0_4", + "CLBLM_WW4END0" + ], + [ + "BRAM_WW4END1_4", + "CLBLM_WW4END1" + ], + [ + "BRAM_WW4END2_4", + "CLBLM_WW4END2" + ], + [ + "BRAM_WW4END3_4", + "CLBLM_WW4END3" ] ] }, { "grid_deltas": [ -1, - 8 + -3 ], "tile_types": [ - "CMT_TOP_L_LOWER_B", - "VBRK" + "BRAM_L", + "CLBLM_R" ], "wire_pairs": [ [ - "CMT_TOP_NW2A2_0", - "VBRK_NW2A2" + "BRAM_EE2A0_3", + "CLBLM_EE2A0" ], [ - "CMT_TOP_NW2A1_0", - "VBRK_NW2A1" + "BRAM_EE2A1_3", + "CLBLM_EE2A1" ], [ - "CMT_TOP_EE2A0_0", - "VBRK_EE2A0" + "BRAM_EE2A2_3", + "CLBLM_EE2A2" ], [ - "CMT_TOP_NE2A3_0", - "VBRK_NE2A3" + "BRAM_EE2A3_3", + "CLBLM_EE2A3" ], [ - "CMT_TOP_WW2A1_0", - "VBRK_WW2A1" + "BRAM_EE2BEG0_3", + "CLBLM_EE2BEG0" ], [ - "CMT_TOP_EE2BEG3_0", - "VBRK_EE2BEG3" + "BRAM_EE2BEG1_3", + "CLBLM_EE2BEG1" ], [ - "CMT_TOP_EE4C1_0", - "VBRK_EE4C1" + "BRAM_EE2BEG2_3", + "CLBLM_EE2BEG2" ], [ - "CMT_TOP_WW4A1_0", - "VBRK_WW4A1" + "BRAM_EE2BEG3_3", + "CLBLM_EE2BEG3" ], [ - "CMT_TOP_WW2END3_0", - "VBRK_WW2END3" + "BRAM_EE4A0_3", + "CLBLM_EE4A0" ], [ - "CMT_TOP_WW2A0_0", - "VBRK_WW2A0" + "BRAM_EE4A1_3", + "CLBLM_EE4A1" ], [ - "CMT_TOP_LH2_0", - "VBRK_LH2" + "BRAM_EE4A2_3", + "CLBLM_EE4A2" ], [ - "CMT_TOP_WW4END1_0", - "VBRK_WW4END1" + "BRAM_EE4A3_3", + "CLBLM_EE4A3" ], [ - "CMT_TOP_WW4B0_0", - "VBRK_WW4B0" + "BRAM_EE4B0_3", + "CLBLM_EE4B0" ], [ - "CMT_TOP_WW2END2_0", - "VBRK_WW2END2" + "BRAM_EE4B1_3", + "CLBLM_EE4B1" ], [ - "CMT_TOP_NW4END3_0", - "VBRK_NW4END3" + "BRAM_EE4B2_3", + "CLBLM_EE4B2" ], [ - "CMT_TOP_LH7_0", - "VBRK_LH7" + "BRAM_EE4B3_3", + "CLBLM_EE4B3" ], [ - "CMT_TOP_EE2BEG0_0", - "VBRK_EE2BEG0" + "BRAM_EE4BEG0_3", + "CLBLM_EE4BEG0" ], [ - "CMT_TOP_WW4END0_0", - "VBRK_WW4END0" + "BRAM_EE4BEG1_3", + "CLBLM_EE4BEG1" ], [ - "CMT_TOP_WW4B2_0", - "VBRK_WW4B2" + "BRAM_EE4BEG2_3", + "CLBLM_EE4BEG2" ], [ - "CMT_TOP_EE4BEG0_0", - "VBRK_EE4BEG0" + "BRAM_EE4BEG3_3", + "CLBLM_EE4BEG3" ], [ - "CMT_TOP_EE4B3_0", - "VBRK_EE4B3" + "BRAM_EE4C0_3", + "CLBLM_EE4C0" ], [ - "CMT_TOP_NE4C2_0", - "VBRK_NE4C2" + "BRAM_EE4C1_3", + "CLBLM_EE4C1" ], [ - "CMT_TOP_WW4B3_0", - "VBRK_WW4B3" + "BRAM_EE4C2_3", + "CLBLM_EE4C2" ], [ - "CMT_TOP_NE2A2_0", - "VBRK_NE2A2" + "BRAM_EE4C3_3", + "CLBLM_EE4C3" ], [ - "CMT_TOP_EL1BEG0_0", - "VBRK_EL1BEG0" + "BRAM_EL1BEG0_3", + "CLBLM_EL1BEG0" ], [ - "CMT_TOP_WW4C2_0", - "VBRK_WW4C2" + "BRAM_EL1BEG1_3", + "CLBLM_EL1BEG1" ], [ - "CMT_TOP_SE4C1_0", - "VBRK_SE4C1" + "BRAM_EL1BEG2_3", + "CLBLM_EL1BEG2" ], [ - "CMT_TOP_SE2A3_0", - "VBRK_SE2A3" + "BRAM_EL1BEG3_3", + "CLBLM_EL1BEG3" ], [ - "CMT_TOP_SE2A1_0", - "VBRK_SE2A1" + "BRAM_ER1BEG0_3", + "CLBLM_ER1BEG0" ], [ - "CMT_TOP_SW2A3_0", - "VBRK_SW2A3" + "BRAM_ER1BEG1_3", + "CLBLM_ER1BEG1" ], [ - "CMT_TOP_EE4BEG1_0", - "VBRK_EE4BEG1" + "BRAM_ER1BEG2_3", + "CLBLM_ER1BEG2" ], [ - "CMT_TOP_LH9_0", - "VBRK_LH9" + "BRAM_ER1BEG3_3", + "CLBLM_ER1BEG3" ], [ - "CMT_TOP_ER1BEG0_0", - "VBRK_ER1BEG0" + "BRAM_LH1_3", + "CLBLM_LH1" ], [ - "CMT_TOP_WL1END3_0", - "VBRK_WL1END3" + "BRAM_LH2_3", + "CLBLM_LH2" ], [ - "CMT_TOP_NE4C3_0", - "VBRK_NE4C3" + "BRAM_LH3_3", + "CLBLM_LH3" ], [ - "CMT_TOP_LH8_0", - "VBRK_LH8" + "BRAM_LH4_3", + "CLBLM_LH4" ], [ - "CMT_TOP_SW4END0_0", - "VBRK_SW4END0" + "BRAM_LH5_3", + "CLBLM_LH5" ], [ - "CMT_TOP_EE2A1_0", - "VBRK_EE2A1" + "BRAM_LH6_3", + "CLBLM_LH6" ], [ - "CMT_TOP_SW4A0_0", - "VBRK_SW4A0" + "BRAM_LH7_3", + "CLBLM_LH7" ], [ - "CMT_TOP_LH12_0", - "VBRK_LH12" + "BRAM_LH8_3", + "CLBLM_LH8" ], [ - "CMT_TOP_SE4BEG0_0", - "VBRK_SE4BEG0" + "BRAM_LH9_3", + "CLBLM_LH9" ], [ - "CMT_TOP_SE4BEG3_0", - "VBRK_SE4BEG3" + "BRAM_LH10_3", + "CLBLM_LH10" ], [ - "CMT_TOP_SE2A2_0", - "VBRK_SE2A2" + "BRAM_LH11_3", + "CLBLM_LH11" ], [ - "CMT_TOP_SW4A3_0", - "VBRK_SW4A3" + "BRAM_LH12_3", + "CLBLM_LH12" ], [ - "CMT_TOP_NE4C0_0", - "VBRK_NE4C0" + "BRAM_MONITOR_N_3", + "CLBLM_MONITOR_N" ], [ - "CMT_TOP_EL1BEG2_0", - "VBRK_EL1BEG2" + "BRAM_MONITOR_P_3", + "CLBLM_MONITOR_P" ], [ - "CMT_TOP_WW4A0_0", - "VBRK_WW4A0" + "BRAM_NE2A0_3", + "CLBLM_NE2A0" ], [ - "CMT_TOP_LH1_0", - "VBRK_LH1" + "BRAM_NE2A1_3", + "CLBLM_NE2A1" ], [ - "CMT_TOP_EE2A2_0", - "VBRK_EE2A2" + "BRAM_NE2A2_3", + "CLBLM_NE2A2" ], [ - "CMT_TOP_EE4B0_0", - "VBRK_EE4B0" + "BRAM_NE2A3_3", + "CLBLM_NE2A3" ], [ - "CMT_TOP_NW4END0_0", - "VBRK_NW4END0" + "BRAM_NE4BEG0_3", + "CLBLM_NE4BEG0" ], [ - "CMT_TOP_EE2BEG2_0", - "VBRK_EE2BEG2" + "BRAM_NE4BEG1_3", + "CLBLM_NE4BEG1" ], [ - "CMT_TOP_NW4A1_0", - "VBRK_NW4A1" + "BRAM_NE4BEG2_3", + "CLBLM_NE4BEG2" ], [ - "CMT_TOP_NE4BEG3_0", - "VBRK_NE4BEG3" + "BRAM_NE4BEG3_3", + "CLBLM_NE4BEG3" ], [ - "CMT_TOP_EE4A1_0", - "VBRK_EE4A1" + "BRAM_NE4C0_3", + "CLBLM_NE4C0" ], [ - "CMT_TOP_EE4A3_0", - "VBRK_EE4A3" + "BRAM_NE4C1_3", + "CLBLM_NE4C1" ], [ - "CMT_TOP_NW4END1_0", - "VBRK_NW4END1" + "BRAM_NE4C2_3", + "CLBLM_NE4C2" ], [ - "CMT_TOP_NE4BEG0_0", - "VBRK_NE4BEG0" + "BRAM_NE4C3_3", + "CLBLM_NE4C3" ], [ - "CMT_TOP_WR1END1_0", - "VBRK_WR1END1" + "BRAM_NW2A0_3", + "CLBLM_NW2A0" ], [ - "CMT_TOP_SE4BEG1_0", - "VBRK_SE4BEG1" + "BRAM_NW2A1_3", + "CLBLM_NW2A1" ], [ - "CMT_TOP_EE4BEG3_0", - "VBRK_EE4BEG3" + "BRAM_NW2A2_3", + "CLBLM_NW2A2" ], [ - "CMT_TOP_NE4BEG2_0", - "VBRK_NE4BEG2" + "BRAM_NW2A3_3", + "CLBLM_NW2A3" ], [ - "CMT_TOP_NW4A3_0", - "VBRK_NW4A3" + "BRAM_NW4A0_3", + "CLBLM_NW4A0" ], [ - "CMT_TOP_WW2A2_0", - "VBRK_WW2A2" + "BRAM_NW4A1_3", + "CLBLM_NW4A1" ], [ - "CMT_TOP_SW4A1_0", - "VBRK_SW4A1" + "BRAM_NW4A2_3", + "CLBLM_NW4A2" ], [ - "CMT_TOP_SW4END1_0", - "VBRK_SW4END1" + "BRAM_NW4A3_3", + "CLBLM_NW4A3" ], [ - "CMT_TOP_EE2A3_0", - "VBRK_EE2A3" + "BRAM_NW4END0_3", + "CLBLM_NW4END0" ], [ - "CMT_TOP_EE2BEG1_0", - "VBRK_EE2BEG1" + "BRAM_NW4END1_3", + "CLBLM_NW4END1" ], [ - "CMT_TOP_NE4C1_0", - "VBRK_NE4C1" + "BRAM_NW4END2_3", + "CLBLM_NW4END2" ], [ - "CMT_TOP_NE2A0_0", - "VBRK_NE2A0" + "BRAM_NW4END3_3", + "CLBLM_NW4END3" ], [ - "CMT_TOP_NW4A2_0", - "VBRK_NW4A2" + "BRAM_SE2A0_3", + "CLBLM_SE2A0" ], [ - "CMT_TOP_LH6_0", - "VBRK_LH6" + "BRAM_SE2A1_3", + "CLBLM_SE2A1" ], [ - "CMT_TOP_EE4A2_0", - "VBRK_EE4A2" + "BRAM_SE2A2_3", + "CLBLM_SE2A2" ], [ - "CMT_TOP_EE4B2_0", - "VBRK_EE4B2" + "BRAM_SE2A3_3", + "CLBLM_SE2A3" ], [ - "CMT_TOP_ER1BEG1_0", - "VBRK_ER1BEG1" + "BRAM_SE4BEG0_3", + "CLBLM_SE4BEG0" ], [ - "CMT_TOP_LH4_0", - "VBRK_LH4" + "BRAM_SE4BEG1_3", + "CLBLM_SE4BEG1" ], [ - "CMT_TOP_LH11_0", - "VBRK_LH11" + "BRAM_SE4BEG2_3", + "CLBLM_SE4BEG2" ], [ - "CMT_TOP_EL1BEG1_0", - "VBRK_EL1BEG1" + "BRAM_SE4BEG3_3", + "CLBLM_SE4BEG3" ], [ - "CMT_TOP_NW4END2_0", - "VBRK_NW4END2" + "BRAM_SE4C0_3", + "CLBLM_SE4C0" ], [ - "CMT_TOP_SE4BEG2_0", - "VBRK_SE4BEG2" + "BRAM_SE4C1_3", + "CLBLM_SE4C1" ], [ - "CMT_TOP_SE2A0_0", - "VBRK_SE2A0" + "BRAM_SE4C2_3", + "CLBLM_SE4C2" ], [ - "CMT_TOP_WW4END2_0", - "VBRK_WW4END2" + "BRAM_SE4C3_3", + "CLBLM_SE4C3" ], [ - "CMT_TOP_NE2A1_0", - "VBRK_NE2A1" + "BRAM_SW2A0_3", + "CLBLM_SW2A0" ], [ - "CMT_TOP_WR1END0_0", - "VBRK_WR1END0" + "BRAM_SW2A1_3", + "CLBLM_SW2A1" ], [ - "CMT_TOP_WR1END3_0", - "VBRK_WR1END3" + "BRAM_SW2A2_3", + "CLBLM_SW2A2" ], [ - "CMT_TOP_WW4B1_0", - "VBRK_WW4B1" + "BRAM_SW2A3_3", + "CLBLM_SW2A3" ], [ - "CMT_TOP_EE4C2_0", - "VBRK_EE4C2" + "BRAM_SW4A0_3", + "CLBLM_SW4A0" ], [ - "CMT_TOP_WW4C0_0", - "VBRK_WW4C0" + "BRAM_SW4A1_3", + "CLBLM_SW4A1" ], [ - "CMT_TOP_SW4END2_0", - "VBRK_SW4END2" + "BRAM_SW4A2_3", + "CLBLM_SW4A2" ], [ - "CMT_TOP_NW2A3_0", - "VBRK_NW2A3" + "BRAM_SW4A3_3", + "CLBLM_SW4A3" ], [ - "CMT_TOP_WW2END1_0", - "VBRK_WW2END1" + "BRAM_SW4END0_3", + "CLBLM_SW4END0" ], [ - "CMT_TOP_SE4C3_0", - "VBRK_SE4C3" + "BRAM_SW4END1_3", + "CLBLM_SW4END1" ], [ - "CMT_TOP_WW4A2_0", - "VBRK_WW4A2" + "BRAM_SW4END2_3", + "CLBLM_SW4END2" ], [ - "CMT_TOP_WR1END2_0", - "VBRK_WR1END2" + "BRAM_SW4END3_3", + "CLBLM_SW4END3" ], [ - "CMT_TOP_WW4C1_0", - "VBRK_WW4C1" + "BRAM_WL1END0_3", + "CLBLM_WL1END0" ], [ - "CMT_TOP_WW2END0_0", - "VBRK_WW2END0" + "BRAM_WL1END1_3", + "CLBLM_WL1END1" ], [ - "CMT_TOP_SW4A2_0", - "VBRK_SW4A2" + "BRAM_WL1END2_3", + "CLBLM_WL1END2" ], [ - "CMT_TOP_LH3_0", - "VBRK_LH3" + "BRAM_WL1END3_3", + "CLBLM_WL1END3" ], [ - "CMT_TOP_SE4C2_0", - "VBRK_SE4C2" + "BRAM_WR1END0_3", + "CLBLM_WR1END0" ], [ - "CMT_TOP_NE4BEG1_0", - "VBRK_NE4BEG1" + "BRAM_WR1END1_3", + "CLBLM_WR1END1" ], [ - "CMT_TOP_EE4C3_0", - "VBRK_EE4C3" + "BRAM_WR1END2_3", + "CLBLM_WR1END2" ], [ - "CMT_TOP_SW2A1_0", - "VBRK_SW2A1" + "BRAM_WR1END3_3", + "CLBLM_WR1END3" ], [ - "CMT_TOP_NW4A0_0", - "VBRK_NW4A0" + "BRAM_WW2A0_3", + "CLBLM_WW2A0" ], [ - "CMT_TOP_WW4C3_0", - "VBRK_WW4C3" + "BRAM_WW2A1_3", + "CLBLM_WW2A1" ], [ - "CMT_TOP_EE4BEG2_0", - "VBRK_EE4BEG2" + "BRAM_WW2A2_3", + "CLBLM_WW2A2" ], [ - "CMT_TOP_SW2A0_0", - "VBRK_SW2A0" + "BRAM_WW2A3_3", + "CLBLM_WW2A3" ], [ - "CMT_TOP_NW2A0_0", - "VBRK_NW2A0" + "BRAM_WW2END0_3", + "CLBLM_WW2END0" ], [ - "CMT_TOP_SW2A2_0", - "VBRK_SW2A2" + "BRAM_WW2END1_3", + "CLBLM_WW2END1" ], [ - "CMT_TOP_ER1BEG2_0", - "VBRK_ER1BEG2" + "BRAM_WW2END2_3", + "CLBLM_WW2END2" ], [ - "CMT_TOP_EE4C0_0", - "VBRK_EE4C0" + "BRAM_WW2END3_3", + "CLBLM_WW2END3" ], [ - "CMT_TOP_LH10_0", - "VBRK_LH10" + "BRAM_WW4A0_3", + "CLBLM_WW4A0" ], [ - "CMT_TOP_EE4A0_0", - "VBRK_EE4A0" + "BRAM_WW4A1_3", + "CLBLM_WW4A1" ], [ - "CMT_TOP_WW4END3_0", - "VBRK_WW4END3" + "BRAM_WW4A2_3", + "CLBLM_WW4A2" ], [ - "CMT_TOP_LH5_0", - "VBRK_LH5" + "BRAM_WW4A3_3", + "CLBLM_WW4A3" ], [ - "CMT_TOP_SW4END3_0", - "VBRK_SW4END3" + "BRAM_WW4B0_3", + "CLBLM_WW4B0" ], [ - "CMT_TOP_EE4B1_0", - "VBRK_EE4B1" + "BRAM_WW4B1_3", + "CLBLM_WW4B1" ], [ - "CMT_TOP_EL1BEG3_0", - "VBRK_EL1BEG3" + "BRAM_WW4B2_3", + "CLBLM_WW4B2" ], [ - "CMT_TOP_WW4A3_0", - "VBRK_WW4A3" + "BRAM_WW4B3_3", + "CLBLM_WW4B3" ], [ - "CMT_TOP_WL1END0_0", - "VBRK_WL1END0" + "BRAM_WW4C0_3", + "CLBLM_WW4C0" ], [ - "CMT_TOP_SE4C0_0", - "VBRK_SE4C0" + "BRAM_WW4C1_3", + "CLBLM_WW4C1" ], [ - "CMT_TOP_WL1END2_0", - "VBRK_WL1END2" + "BRAM_WW4C2_3", + "CLBLM_WW4C2" ], [ - "CMT_TOP_WL1END1_0", - "VBRK_WL1END1" + "BRAM_WW4C3_3", + "CLBLM_WW4C3" ], [ - "CMT_TOP_WW2A3_0", - "VBRK_WW2A3" + "BRAM_WW4END0_3", + "CLBLM_WW4END0" ], [ - "CMT_TOP_ER1BEG3_0", - "VBRK_ER1BEG3" + "BRAM_WW4END1_3", + "CLBLM_WW4END1" + ], + [ + "BRAM_WW4END2_3", + "CLBLM_WW4END2" + ], + [ + "BRAM_WW4END3_3", + "CLBLM_WW4END3" ] ] }, @@ -14473,6813 +14369,3641 @@ -2 ], "tile_types": [ - "GTX_COMMON", - "VBRK_EXT" + "BRAM_L", + "CLBLM_R" ], "wire_pairs": [ [ - "GTXE2_FAN1_2", - "VBRK_EXT_FAN1" + "BRAM_EE2A0_2", + "CLBLM_EE2A0" ], [ - "GTXE2_FAN2_2", - "VBRK_EXT_FAN2" + "BRAM_EE2A1_2", + "CLBLM_EE2A1" ], [ - "GTXE2_IMUX41_2", - "VBRK_EXT_IMUX41" + "BRAM_EE2A2_2", + "CLBLM_EE2A2" ], [ - "GTXE2_IMUX11_2", - "VBRK_EXT_IMUX11" + "BRAM_EE2A3_2", + "CLBLM_EE2A3" ], [ - "GTXE2_LOGIC_OUTS_B10_2", - "VBRK_EXT_LOGIC_OUTS_B10" + "BRAM_EE2BEG0_2", + "CLBLM_EE2BEG0" ], [ - "GTXE2_IMUX22_2", - "VBRK_EXT_IMUX22" + "BRAM_EE2BEG1_2", + "CLBLM_EE2BEG1" ], [ - "GTXE2_IMUX26_2", - "VBRK_EXT_IMUX26" + "BRAM_EE2BEG2_2", + "CLBLM_EE2BEG2" ], [ - "GTXE2_LOGIC_OUTS_B9_2", - "VBRK_EXT_LOGIC_OUTS_B9" + "BRAM_EE2BEG3_2", + "CLBLM_EE2BEG3" ], [ - "GTXE2_CTRL0_2", - "VBRK_EXT_CTRL0" + "BRAM_EE4A0_2", + "CLBLM_EE4A0" ], [ - "GTXE2_FAN7_2", - "VBRK_EXT_FAN7" + "BRAM_EE4A1_2", + "CLBLM_EE4A1" ], [ - "GTXE2_IMUX23_2", - "VBRK_EXT_IMUX23" + "BRAM_EE4A2_2", + "CLBLM_EE4A2" ], [ - "GTXE2_IMUX20_2", - "VBRK_EXT_IMUX20" + "BRAM_EE4A3_2", + "CLBLM_EE4A3" ], [ - "GTXE2_IMUX12_2", - "VBRK_EXT_IMUX12" + "BRAM_EE4B0_2", + "CLBLM_EE4B0" ], [ - "GTXE2_IMUX37_2", - "VBRK_EXT_IMUX37" + "BRAM_EE4B1_2", + "CLBLM_EE4B1" ], [ - "GTXE2_FAN6_2", - "VBRK_EXT_FAN6" + "BRAM_EE4B2_2", + "CLBLM_EE4B2" ], [ - "GTXE2_FAN4_2", - "VBRK_EXT_FAN4" + "BRAM_EE4B3_2", + "CLBLM_EE4B3" ], [ - "GTXE2_IMUX5_2", - "VBRK_EXT_IMUX5" + "BRAM_EE4BEG0_2", + "CLBLM_EE4BEG0" ], [ - "GTXE2_IMUX13_2", - "VBRK_EXT_IMUX13" + "BRAM_EE4BEG1_2", + "CLBLM_EE4BEG1" ], [ - "GTXE2_IMUX31_2", - "VBRK_EXT_IMUX31" + "BRAM_EE4BEG2_2", + "CLBLM_EE4BEG2" ], [ - "GTXE2_IMUX32_2", - "VBRK_EXT_IMUX32" + "BRAM_EE4BEG3_2", + "CLBLM_EE4BEG3" ], [ - "GTXE2_IMUX35_2", - "VBRK_EXT_IMUX35" + "BRAM_EE4C0_2", + "CLBLM_EE4C0" ], [ - "GTXE2_IMUX24_2", - "VBRK_EXT_IMUX24" + "BRAM_EE4C1_2", + "CLBLM_EE4C1" ], [ - "GTXE2_IMUX27_2", - "VBRK_EXT_IMUX27" + "BRAM_EE4C2_2", + "CLBLM_EE4C2" ], [ - "GTXE2_IMUX33_2", - "VBRK_EXT_IMUX33" + "BRAM_EE4C3_2", + "CLBLM_EE4C3" ], [ - "GTXE2_FAN5_2", - "VBRK_EXT_FAN5" + "BRAM_EL1BEG0_2", + "CLBLM_EL1BEG0" ], [ - "GTXE2_IMUX39_2", - "VBRK_EXT_IMUX39" + "BRAM_EL1BEG1_2", + "CLBLM_EL1BEG1" ], [ - "GTXE2_CTRL1_2", - "VBRK_EXT_CTRL1" + "BRAM_EL1BEG2_2", + "CLBLM_EL1BEG2" ], [ - "GTXE2_BYP3_2", - "VBRK_EXT_BYP3" + "BRAM_EL1BEG3_2", + "CLBLM_EL1BEG3" ], [ - "GTXE2_IMUX4_2", - "VBRK_EXT_IMUX4" + "BRAM_ER1BEG0_2", + "CLBLM_ER1BEG0" ], [ - "GTXE2_IMUX17_2", - "VBRK_EXT_IMUX17" + "BRAM_ER1BEG1_2", + "CLBLM_ER1BEG1" ], [ - "GTXE2_BYP2_2", - "VBRK_EXT_BYP2" + "BRAM_ER1BEG2_2", + "CLBLM_ER1BEG2" ], [ - "GTXE2_IMUX14_2", - "VBRK_EXT_IMUX14" + "BRAM_ER1BEG3_2", + "CLBLM_ER1BEG3" ], [ - "GTXE2_LOGIC_OUTS_B14_2", - "VBRK_EXT_LOGIC_OUTS_B14" + "BRAM_LH1_2", + "CLBLM_LH1" ], [ - "GTXE2_IMUX43_2", - "VBRK_EXT_IMUX43" + "BRAM_LH2_2", + "CLBLM_LH2" ], [ - "GTXE2_BYP1_2", - "VBRK_EXT_BYP1" + "BRAM_LH3_2", + "CLBLM_LH3" ], [ - "GTXE2_IMUX34_2", - "VBRK_EXT_IMUX34" + "BRAM_LH4_2", + "CLBLM_LH4" ], [ - "GTXE2_BYP5_2", - "VBRK_EXT_BYP5" + "BRAM_LH5_2", + "CLBLM_LH5" ], [ - "GTXE2_IMUX47_2", - "VBRK_EXT_IMUX47" + "BRAM_LH6_2", + "CLBLM_LH6" ], [ - "GTXE2_IMUX30_2", - "VBRK_EXT_IMUX30" + "BRAM_LH7_2", + "CLBLM_LH7" ], [ - "GTXE2_IMUX3_2", - "VBRK_EXT_IMUX3" + "BRAM_LH8_2", + "CLBLM_LH8" ], [ - "GTXE2_IMUX44_2", - "VBRK_EXT_IMUX44" + "BRAM_LH9_2", + "CLBLM_LH9" ], [ - "GTXE2_IMUX1_2", - "VBRK_EXT_IMUX1" + "BRAM_LH10_2", + "CLBLM_LH10" ], [ - "GTXE2_IMUX18_2", - "VBRK_EXT_IMUX18" + "BRAM_LH11_2", + "CLBLM_LH11" ], [ - "GTXE2_BYP6_2", - "VBRK_EXT_BYP6" + "BRAM_LH12_2", + "CLBLM_LH12" ], [ - "GTXE2_BYP7_2", - "VBRK_EXT_BYP7" + "BRAM_MONITOR_N_2", + "CLBLM_MONITOR_N" ], [ - "GTXE2_CLK0_2", - "VBRK_EXT_CLK0" + "BRAM_MONITOR_P_2", + "CLBLM_MONITOR_P" ], [ - "GTXE2_BYP0_2", - "VBRK_EXT_BYP0" + "BRAM_NE2A0_2", + "CLBLM_NE2A0" ], [ - "GTXE2_FAN0_2", - "VBRK_EXT_FAN0" + "BRAM_NE2A1_2", + "CLBLM_NE2A1" ], [ - "GTXE2_IMUX10_2", - "VBRK_EXT_IMUX10" + "BRAM_NE2A2_2", + "CLBLM_NE2A2" ], [ - "GTXE2_IMUX7_2", - "VBRK_EXT_IMUX7" + "BRAM_NE2A3_2", + "CLBLM_NE2A3" ], [ - "GTXE2_IMUX25_2", - "VBRK_EXT_IMUX25" + "BRAM_NE4BEG0_2", + "CLBLM_NE4BEG0" ], [ - "GTXE2_IMUX0_2", - "VBRK_EXT_IMUX0" + "BRAM_NE4BEG1_2", + "CLBLM_NE4BEG1" ], [ - "GTXE2_IMUX29_2", - "VBRK_EXT_IMUX29" + "BRAM_NE4BEG2_2", + "CLBLM_NE4BEG2" ], [ - "GTXE2_IMUX46_2", - "VBRK_EXT_IMUX46" + "BRAM_NE4BEG3_2", + "CLBLM_NE4BEG3" ], [ - "GTXE2_IMUX21_2", - "VBRK_EXT_IMUX21" + "BRAM_NE4C0_2", + "CLBLM_NE4C0" ], [ - "GTXE2_IMUX45_2", - "VBRK_EXT_IMUX45" + "BRAM_NE4C1_2", + "CLBLM_NE4C1" ], [ - "GTXE2_IMUX38_2", - "VBRK_EXT_IMUX38" + "BRAM_NE4C2_2", + "CLBLM_NE4C2" ], [ - "GTXE2_LOGIC_OUTS_B19_2", - "VBRK_EXT_LOGIC_OUTS_B19" + "BRAM_NE4C3_2", + "CLBLM_NE4C3" ], [ - "GTXE2_BYP4_2", - "VBRK_EXT_BYP4" + "BRAM_NW2A0_2", + "CLBLM_NW2A0" ], [ - "GTXE2_IMUX28_2", - "VBRK_EXT_IMUX28" + "BRAM_NW2A1_2", + "CLBLM_NW2A1" ], [ - "GTXE2_FAN3_2", - "VBRK_EXT_FAN3" + "BRAM_NW2A2_2", + "CLBLM_NW2A2" ], [ - "GTXE2_IMUX2_2", - "VBRK_EXT_IMUX2" + "BRAM_NW2A3_2", + "CLBLM_NW2A3" ], [ - "GTXE2_IMUX9_2", - "VBRK_EXT_IMUX9" + "BRAM_NW4A0_2", + "CLBLM_NW4A0" ], [ - "GTXE2_CLK1_2", - "VBRK_EXT_CLK1" + "BRAM_NW4A1_2", + "CLBLM_NW4A1" ], [ - "GTXE2_IMUX8_2", - "VBRK_EXT_IMUX8" + "BRAM_NW4A2_2", + "CLBLM_NW4A2" ], [ - "GTXE2_IMUX15_2", - "VBRK_EXT_IMUX15" + "BRAM_NW4A3_2", + "CLBLM_NW4A3" ], [ - "GTXE2_IMUX42_2", - "VBRK_EXT_IMUX42" + "BRAM_NW4END0_2", + "CLBLM_NW4END0" ], [ - "GTXE2_IMUX40_2", - "VBRK_EXT_IMUX40" + "BRAM_NW4END1_2", + "CLBLM_NW4END1" ], [ - "GTXE2_IMUX16_2", - "VBRK_EXT_IMUX16" + "BRAM_NW4END2_2", + "CLBLM_NW4END2" ], [ - "GTXE2_IMUX36_2", - "VBRK_EXT_IMUX36" + "BRAM_NW4END3_2", + "CLBLM_NW4END3" ], [ - "GTXE2_IMUX19_2", - "VBRK_EXT_IMUX19" + "BRAM_SE2A0_2", + "CLBLM_SE2A0" ], [ - "GTXE2_IMUX6_2", - "VBRK_EXT_IMUX6" + "BRAM_SE2A1_2", + "CLBLM_SE2A1" + ], + [ + "BRAM_SE2A2_2", + "CLBLM_SE2A2" + ], + [ + "BRAM_SE2A3_2", + "CLBLM_SE2A3" + ], + [ + "BRAM_SE4BEG0_2", + "CLBLM_SE4BEG0" + ], + [ + "BRAM_SE4BEG1_2", + "CLBLM_SE4BEG1" + ], + [ + "BRAM_SE4BEG2_2", + "CLBLM_SE4BEG2" + ], + [ + "BRAM_SE4BEG3_2", + "CLBLM_SE4BEG3" + ], + [ + "BRAM_SE4C0_2", + "CLBLM_SE4C0" + ], + [ + "BRAM_SE4C1_2", + "CLBLM_SE4C1" + ], + [ + "BRAM_SE4C2_2", + "CLBLM_SE4C2" + ], + [ + "BRAM_SE4C3_2", + "CLBLM_SE4C3" + ], + [ + "BRAM_SW2A0_2", + "CLBLM_SW2A0" + ], + [ + "BRAM_SW2A1_2", + "CLBLM_SW2A1" + ], + [ + "BRAM_SW2A2_2", + "CLBLM_SW2A2" + ], + [ + "BRAM_SW2A3_2", + "CLBLM_SW2A3" + ], + [ + "BRAM_SW4A0_2", + "CLBLM_SW4A0" + ], + [ + "BRAM_SW4A1_2", + "CLBLM_SW4A1" + ], + [ + "BRAM_SW4A2_2", + "CLBLM_SW4A2" + ], + [ + "BRAM_SW4A3_2", + "CLBLM_SW4A3" + ], + [ + "BRAM_SW4END0_2", + "CLBLM_SW4END0" + ], + [ + "BRAM_SW4END1_2", + "CLBLM_SW4END1" + ], + [ + "BRAM_SW4END2_2", + "CLBLM_SW4END2" + ], + [ + "BRAM_SW4END3_2", + "CLBLM_SW4END3" + ], + [ + "BRAM_WL1END0_2", + "CLBLM_WL1END0" + ], + [ + "BRAM_WL1END1_2", + "CLBLM_WL1END1" + ], + [ + "BRAM_WL1END2_2", + "CLBLM_WL1END2" + ], + [ + "BRAM_WL1END3_2", + "CLBLM_WL1END3" + ], + [ + "BRAM_WR1END0_2", + "CLBLM_WR1END0" + ], + [ + "BRAM_WR1END1_2", + "CLBLM_WR1END1" + ], + [ + "BRAM_WR1END2_2", + "CLBLM_WR1END2" + ], + [ + "BRAM_WR1END3_2", + "CLBLM_WR1END3" + ], + [ + "BRAM_WW2A0_2", + "CLBLM_WW2A0" + ], + [ + "BRAM_WW2A1_2", + "CLBLM_WW2A1" + ], + [ + "BRAM_WW2A2_2", + "CLBLM_WW2A2" + ], + [ + "BRAM_WW2A3_2", + "CLBLM_WW2A3" + ], + [ + "BRAM_WW2END0_2", + "CLBLM_WW2END0" + ], + [ + "BRAM_WW2END1_2", + "CLBLM_WW2END1" + ], + [ + "BRAM_WW2END2_2", + "CLBLM_WW2END2" + ], + [ + "BRAM_WW2END3_2", + "CLBLM_WW2END3" + ], + [ + "BRAM_WW4A0_2", + "CLBLM_WW4A0" + ], + [ + "BRAM_WW4A1_2", + "CLBLM_WW4A1" + ], + [ + "BRAM_WW4A2_2", + "CLBLM_WW4A2" + ], + [ + "BRAM_WW4A3_2", + "CLBLM_WW4A3" + ], + [ + "BRAM_WW4B0_2", + "CLBLM_WW4B0" + ], + [ + "BRAM_WW4B1_2", + "CLBLM_WW4B1" + ], + [ + "BRAM_WW4B2_2", + "CLBLM_WW4B2" + ], + [ + "BRAM_WW4B3_2", + "CLBLM_WW4B3" + ], + [ + "BRAM_WW4C0_2", + "CLBLM_WW4C0" + ], + [ + "BRAM_WW4C1_2", + "CLBLM_WW4C1" + ], + [ + "BRAM_WW4C2_2", + "CLBLM_WW4C2" + ], + [ + "BRAM_WW4C3_2", + "CLBLM_WW4C3" + ], + [ + "BRAM_WW4END0_2", + "CLBLM_WW4END0" + ], + [ + "BRAM_WW4END1_2", + "CLBLM_WW4END1" + ], + [ + "BRAM_WW4END2_2", + "CLBLM_WW4END2" + ], + [ + "BRAM_WW4END3_2", + "CLBLM_WW4END3" + ] + ] + }, + { + "grid_deltas": [ + -1, + -1 + ], + "tile_types": [ + "BRAM_L", + "CLBLM_R" + ], + "wire_pairs": [ + [ + "BRAM_EE2A0_1", + "CLBLM_EE2A0" + ], + [ + "BRAM_EE2A1_1", + "CLBLM_EE2A1" + ], + [ + "BRAM_EE2A2_1", + "CLBLM_EE2A2" + ], + [ + "BRAM_EE2A3_1", + "CLBLM_EE2A3" + ], + [ + "BRAM_EE2BEG0_1", + "CLBLM_EE2BEG0" + ], + [ + "BRAM_EE2BEG1_1", + "CLBLM_EE2BEG1" + ], + [ + "BRAM_EE2BEG2_1", + "CLBLM_EE2BEG2" + ], + [ + "BRAM_EE2BEG3_1", + "CLBLM_EE2BEG3" + ], + [ + "BRAM_EE4A0_1", + "CLBLM_EE4A0" + ], + [ + "BRAM_EE4A1_1", + "CLBLM_EE4A1" + ], + [ + "BRAM_EE4A2_1", + "CLBLM_EE4A2" + ], + [ + "BRAM_EE4A3_1", + "CLBLM_EE4A3" + ], + [ + "BRAM_EE4B0_1", + "CLBLM_EE4B0" + ], + [ + "BRAM_EE4B1_1", + "CLBLM_EE4B1" + ], + [ + "BRAM_EE4B2_1", + "CLBLM_EE4B2" + ], + [ + "BRAM_EE4B3_1", + "CLBLM_EE4B3" + ], + [ + "BRAM_EE4BEG0_1", + "CLBLM_EE4BEG0" + ], + [ + "BRAM_EE4BEG1_1", + "CLBLM_EE4BEG1" + ], + [ + "BRAM_EE4BEG2_1", + "CLBLM_EE4BEG2" + ], + [ + "BRAM_EE4BEG3_1", + "CLBLM_EE4BEG3" + ], + [ + "BRAM_EE4C0_1", + "CLBLM_EE4C0" + ], + [ + "BRAM_EE4C1_1", + "CLBLM_EE4C1" + ], + [ + "BRAM_EE4C2_1", + "CLBLM_EE4C2" + ], + [ + "BRAM_EE4C3_1", + "CLBLM_EE4C3" + ], + [ + "BRAM_EL1BEG0_1", + "CLBLM_EL1BEG0" + ], + [ + "BRAM_EL1BEG1_1", + "CLBLM_EL1BEG1" + ], + [ + "BRAM_EL1BEG2_1", + "CLBLM_EL1BEG2" + ], + [ + "BRAM_EL1BEG3_1", + "CLBLM_EL1BEG3" + ], + [ + "BRAM_ER1BEG0_1", + "CLBLM_ER1BEG0" + ], + [ + "BRAM_ER1BEG1_1", + "CLBLM_ER1BEG1" + ], + [ + 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[ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_FIFO36_CASCADEOUTA_1", + "HCLK_BRAM_CASCADEA_L" + ], + [ + "BRAM_FIFO36_CASCADEOUTB_1", + "HCLK_BRAM_CASCADEB_L" ] ] }, { "grid_deltas": [ - 1, - 0 + 0, + 1 ], "tile_types": [ - "CLK_PMV2_SVT", + "BRAM_L", + "HCLK_BRAM" + ], + "wire_pairs": [ + [ + "BRAM_CASCINBOT_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" + ], + [ + "BRAM_FIFO36_CASCADEINA", + "HCLK_BRAM_CASCADEA_L" + ], + [ + "BRAM_FIFO36_CASCADEINB", + "HCLK_BRAM_CASCADEB_L" + ], + [ + "BRAM_PMVBRAM_O", + "HCLK_BRAM_PMVBRAM_O" + ], + [ + "BRAM_PMVBRAM_ODIV2", + "HCLK_BRAM_PMVBRAM_ODIV2" + ], + [ + "BRAM_PMVBRAM_ODIV4", + "HCLK_BRAM_PMVBRAM_ODIV4" + ], + [ + "BRAM_PMVBRAM_SELECT1", + "HCLK_BRAM_PMVBRAM_SELECT1" + ], + [ + "BRAM_PMVBRAM_SELECT2", + "HCLK_BRAM_PMVBRAM_SELECT2" + ], + [ + "BRAM_PMVBRAM_SELECT3", + "HCLK_BRAM_PMVBRAM_SELECT3" + ], + [ + "BRAM_PMVBRAM_SELECT4", + "HCLK_BRAM_PMVBRAM_SELECT4" + ] + ] + }, + { + "grid_deltas": [ + -1, + -4 + ], + "tile_types": [ + "BRAM_L", "VBRK" ], "wire_pairs": [ [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_LH8", - "VBRK_LH8" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_EE2A0", + "BRAM_EE2A0_4", "VBRK_EE2A0" ], [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_LH2", - "VBRK_LH2" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLK_FEED_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLK_FEED_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLK_FEED_EE4BEG2", - "VBRK_EE4BEG2" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLK_FEED_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLK_FEED_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLK_FEED_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLK_FEED_LH7", - "VBRK_LH7" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLK_FEED_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLK_FEED_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLK_FEED_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLK_FEED_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLK_FEED_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLK_FEED_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLK_FEED_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLK_FEED_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLK_FEED_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLK_FEED_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLK_FEED_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLK_FEED_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLK_FEED_LH12", - "VBRK_LH12" - ], - [ - "CLK_FEED_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLK_FEED_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLK_FEED_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLK_FEED_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLK_FEED_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLK_FEED_EE2A1", + "BRAM_EE2A1_4", "VBRK_EE2A1" ], [ - "CLK_FEED_EE4B0", - "VBRK_EE4B0" + "BRAM_EE2A2_4", + "VBRK_EE2A2" ], [ - "CLK_FEED_SW4A2", - "VBRK_SW4A2" + "BRAM_EE2A3_4", + "VBRK_EE2A3" ], [ - "CLK_FEED_EE4A0", + "BRAM_EE2BEG0_4", + "VBRK_EE2BEG0" + ], + [ + "BRAM_EE2BEG1_4", + "VBRK_EE2BEG1" + ], + [ + "BRAM_EE2BEG2_4", + "VBRK_EE2BEG2" + ], + [ + "BRAM_EE2BEG3_4", + "VBRK_EE2BEG3" + ], + [ + "BRAM_EE4A0_4", "VBRK_EE4A0" ], [ - "CLK_FEED_WW4END1", - "VBRK_WW4END1" + "BRAM_EE4A1_4", + "VBRK_EE4A1" ], [ - "CLK_FEED_EE4B1", + "BRAM_EE4A2_4", + "VBRK_EE4A2" + ], + [ + "BRAM_EE4A3_4", + "VBRK_EE4A3" + ], + [ + "BRAM_EE4B0_4", + "VBRK_EE4B0" + ], + [ + "BRAM_EE4B1_4", "VBRK_EE4B1" ], [ - "CLK_FEED_NE2A2", - "VBRK_NE2A2" + "BRAM_EE4B2_4", + "VBRK_EE4B2" ], [ - "CLK_FEED_SE4BEG2", - "VBRK_SE4BEG2" + "BRAM_EE4B3_4", + "VBRK_EE4B3" ], [ - "CLK_FEED_WL1END0", - "VBRK_WL1END0" + "BRAM_EE4BEG0_4", + "VBRK_EE4BEG0" ], [ - "CLK_FEED_WW4C2", - "VBRK_WW4C2" + "BRAM_EE4BEG1_4", + "VBRK_EE4BEG1" ], [ - "CLK_FEED_NW2A2", - "VBRK_NW2A2" + "BRAM_EE4BEG2_4", + "VBRK_EE4BEG2" ], [ - "CLK_FEED_SE4BEG0", - "VBRK_SE4BEG0" + "BRAM_EE4BEG3_4", + "VBRK_EE4BEG3" ], [ - "CLK_FEED_LH3", + "BRAM_EE4C0_4", + "VBRK_EE4C0" + ], + [ + "BRAM_EE4C1_4", + "VBRK_EE4C1" + ], + [ + "BRAM_EE4C2_4", + "VBRK_EE4C2" + ], + [ + "BRAM_EE4C3_4", + "VBRK_EE4C3" + ], + [ + "BRAM_EL1BEG0_4", + "VBRK_EL1BEG0" + ], + [ + "BRAM_EL1BEG1_4", + "VBRK_EL1BEG1" + ], + [ + "BRAM_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EL1BEG3_4", + "VBRK_EL1BEG3" + ], + [ + "BRAM_ER1BEG0_4", + "VBRK_ER1BEG0" + ], + [ + "BRAM_ER1BEG1_4", + "VBRK_ER1BEG1" + ], + [ + "BRAM_ER1BEG2_4", + "VBRK_ER1BEG2" + ], + [ + "BRAM_ER1BEG3_4", + "VBRK_ER1BEG3" + ], + [ + "BRAM_LH1_4", + "VBRK_LH1" + ], + [ + "BRAM_LH2_4", + "VBRK_LH2" + ], + [ + "BRAM_LH3_4", "VBRK_LH3" ], [ - "CLK_FEED_WW4A1", - "VBRK_WW4A1" + "BRAM_LH4_4", + "VBRK_LH4" ], [ - "CLK_FEED_WW2A1", - "VBRK_WW2A1" + "BRAM_LH5_4", + "VBRK_LH5" ], [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" + "BRAM_LH6_4", + "VBRK_LH6" ], [ - "CLK_FEED_SE4BEG3", + "BRAM_LH7_4", + "VBRK_LH7" + ], + [ + "BRAM_LH8_4", + "VBRK_LH8" + ], + [ + "BRAM_LH9_4", + "VBRK_LH9" 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"VBRK_SW4A0" + ], + [ + "BRAM_SW4A1_4", + "VBRK_SW4A1" + ], + [ + "BRAM_SW4A2_4", + "VBRK_SW4A2" + ], + [ + "BRAM_SW4A3_4", + "VBRK_SW4A3" + ], + [ + "BRAM_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "BRAM_SW4END1_4", + "VBRK_SW4END1" + ], + [ + "BRAM_SW4END2_4", + "VBRK_SW4END2" + ], + [ + "BRAM_SW4END3_4", + "VBRK_SW4END3" + ], + [ + "BRAM_WL1END0_4", + "VBRK_WL1END0" + ], + [ + "BRAM_WL1END1_4", + "VBRK_WL1END1" + ], + [ + "BRAM_WL1END2_4", + "VBRK_WL1END2" + ], + [ + "BRAM_WL1END3_4", + "VBRK_WL1END3" + ], + [ + "BRAM_WR1END0_4", + "VBRK_WR1END0" + ], + [ + "BRAM_WR1END1_4", + "VBRK_WR1END1" + ], + [ + "BRAM_WR1END2_4", + "VBRK_WR1END2" + ], + [ + "BRAM_WR1END3_4", + "VBRK_WR1END3" + ], + [ + "BRAM_WW2A0_4", + "VBRK_WW2A0" + ], + [ + "BRAM_WW2A1_4", + "VBRK_WW2A1" + ], + [ + "BRAM_WW2A2_4", + "VBRK_WW2A2" + ], + [ + "BRAM_WW2A3_4", + "VBRK_WW2A3" + ], + [ + "BRAM_WW2END0_4", + "VBRK_WW2END0" + ], + [ + "BRAM_WW2END1_4", + "VBRK_WW2END1" + ], + [ + "BRAM_WW2END2_4", + "VBRK_WW2END2" + ], + [ + "BRAM_WW2END3_4", + "VBRK_WW2END3" + ], + [ + "BRAM_WW4A0_4", + "VBRK_WW4A0" + ], + [ + "BRAM_WW4A1_4", + "VBRK_WW4A1" + ], + [ + "BRAM_WW4A2_4", + "VBRK_WW4A2" + ], + [ + "BRAM_WW4A3_4", + "VBRK_WW4A3" + ], + [ + "BRAM_WW4B0_4", + "VBRK_WW4B0" + ], + [ + "BRAM_WW4B1_4", + "VBRK_WW4B1" + ], + [ + "BRAM_WW4B2_4", + "VBRK_WW4B2" + ], + [ + "BRAM_WW4B3_4", "VBRK_WW4B3" ], [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" + "BRAM_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "BRAM_WW4C1_4", + "VBRK_WW4C1" + ], + [ + "BRAM_WW4C2_4", + "VBRK_WW4C2" + ], + [ + "BRAM_WW4C3_4", + "VBRK_WW4C3" + ], + [ + "BRAM_WW4END0_4", + "VBRK_WW4END0" + ], + [ + "BRAM_WW4END1_4", + "VBRK_WW4END1" + ], + [ + "BRAM_WW4END2_4", + "VBRK_WW4END2" + ], + [ + "BRAM_WW4END3_4", + "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, - 6 + -3 ], "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "PCIE_SW2A0_4", - "INT_INTERFACE_SW2A0" - ], - [ - "PCIE_NW4END3_4", - "INT_INTERFACE_NW4END3" - ], - [ - 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- "MONITOR_SW4END3_7", - "VFRAME_SW4END3" - ], - [ - "MONITOR_NE4BEG2_7", - "VFRAME_NE4BEG2" - ], - [ - "MONITOR_NE4BEG1_7", - "VFRAME_NE4BEG1" - ], - [ - "MONITOR_EE4C3_7", - "VFRAME_EE4C3" - ], - [ - "MONITOR_IMUX27_7", - "VFRAME_IMUX27" - ], - [ - "MONITOR_NW4A2_7", - "VFRAME_NW4A2" - ], - [ - "MONITOR_IMUX47_7", - "VFRAME_IMUX47" - ], - [ - "MONITOR_EE2A3_7", - "VFRAME_EE2A3" - ], - [ - "MONITOR_WW4A0_7", - "VFRAME_WW4A0" - ], - [ - "MONITOR_NW4A3_7", - "VFRAME_NW4A3" - ], - [ - "MONITOR_WL1END0_7", - "VFRAME_WL1END0" - ], - [ - "MONITOR_IMUX44_7", - "VFRAME_IMUX44" - ], - [ - "MONITOR_EL1BEG1_7", - "VFRAME_EL1BEG1" - ], - [ - "MONITOR_CLK1_7", - "VFRAME_CLK1" - ], - [ - "MONITOR_WW4END3_7", - "VFRAME_WW4END3" - ], - [ - "MONITOR_WW4END0_7", - "VFRAME_WW4END0" - ], - [ - "MONITOR_WW2A0_7", - "VFRAME_WW2A0" - ], - [ - "MONITOR_LH9_7", - "VFRAME_LH9" - ], - [ - "MONITOR_SE4C3_7", - "VFRAME_SE4C3" - ], - [ - "MONITOR_ER1BEG0_7", - "VFRAME_ER1BEG0" - ], - [ - "MONITOR_IMUX42_7", - "VFRAME_IMUX42" - ], - [ - "MONITOR_IMUX31_7", - "VFRAME_IMUX31" - ], - [ - "MONITOR_IMUX23_7", - "VFRAME_IMUX23" - ], - [ - "MONITOR_WW2END0_7", - "VFRAME_WW2END0" - ], - [ - "MONITOR_SE4BEG3_7", - "VFRAME_SE4BEG3" - ], - [ - "MONITOR_LH4_7", - "VFRAME_LH4" - ], - [ - "MONITOR_EE4C1_7", - "VFRAME_EE4C1" - ], - [ - "MONITOR_NW4END0_7", - "VFRAME_NW4END0" - ], - [ - "MONITOR_BYP0_7", - "VFRAME_BYP0" - ], - [ - "MONITOR_WW4A1_7", - "VFRAME_WW4A1" - ], - [ - "MONITOR_SE4BEG1_7", - "VFRAME_SE4BEG1" - ], - [ - "MONITOR_ER1BEG2_7", - "VFRAME_ER1BEG2" - ], - [ - "MONITOR_IMUX14_7", - "VFRAME_IMUX14" - ], - [ - "MONITOR_IMUX1_7", - "VFRAME_IMUX1" - ], - [ - "MONITOR_IMUX8_7", - "VFRAME_IMUX8" - ], - [ - "MONITOR_WW4B1_7", - "VFRAME_WW4B1" - ], - [ - "MONITOR_LH1_7", - "VFRAME_LH1" - ], - [ - "MONITOR_CTRL0_7", - "VFRAME_CTRL0" - ], - [ - "MONITOR_IMUX11_7", - "VFRAME_IMUX11" - ], - [ - "MONITOR_IMUX20_7", - "VFRAME_IMUX20" - ], - [ - "MONITOR_IMUX4_7", - "VFRAME_IMUX4" - ], - [ - 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"MONITOR_EE4B1_7", - "VFRAME_EE4B1" - ], - [ - "MONITOR_WW4C1_7", - "VFRAME_WW4C1" - ], - [ - "MONITOR_IMUX5_7", - "VFRAME_IMUX5" - ], - [ - "MONITOR_LH10_7", - "VFRAME_LH10" - ], - [ - "MONITOR_IMUX13_7", - "VFRAME_IMUX13" - ], - [ - "MONITOR_SW2A0_7", - "VFRAME_SW2A0" - ], - [ - "MONITOR_WW4B3_7", - "VFRAME_WW4B3" ], [ - "MONITOR_WW4A2_7", - "VFRAME_WW4A2" + "BRAM_SE4BEG2_2", + "VBRK_SE4BEG2" ], [ - "MONITOR_IMUX21_7", - "VFRAME_IMUX21" + "BRAM_SE4BEG3_2", + "VBRK_SE4BEG3" ], [ - "MONITOR_NW2A3_7", - "VFRAME_NW2A3" + "BRAM_SE4C0_2", + "VBRK_SE4C0" ], [ - "MONITOR_SW4END2_7", - "VFRAME_SW4END2" + "BRAM_SE4C1_2", + "VBRK_SE4C1" ], [ - "MONITOR_BYP2_7", - "VFRAME_BYP2" + "BRAM_SE4C2_2", + "VBRK_SE4C2" ], [ - "MONITOR_IMUX12_7", - "VFRAME_IMUX12" + "BRAM_SE4C3_2", + "VBRK_SE4C3" ], [ - "MONITOR_SW4A0_7", - "VFRAME_SW4A0" + "BRAM_SW2A0_2", + "VBRK_SW2A0" ], [ - "MONITOR_SE2A1_7", - "VFRAME_SE2A1" + "BRAM_SW2A1_2", + "VBRK_SW2A1" ], [ - "MONITOR_NE4C1_7", - "VFRAME_NE4C1" + "BRAM_SW2A2_2", + "VBRK_SW2A2" ], [ - "MONITOR_WR1END0_7", - "VFRAME_WR1END0" + "BRAM_SW2A3_2", + "VBRK_SW2A3" ], [ - "MONITOR_EE4B3_7", - "VFRAME_EE4B3" + "BRAM_SW4A0_2", + "VBRK_SW4A0" ], [ - "MONITOR_EE4A0_7", - "VFRAME_EE4A0" + "BRAM_SW4A1_2", + "VBRK_SW4A1" ], [ - "MONITOR_NW4A1_7", - "VFRAME_NW4A1" + "BRAM_SW4A2_2", + "VBRK_SW4A2" ], [ - "MONITOR_IMUX18_7", - "VFRAME_IMUX18" + "BRAM_SW4A3_2", + "VBRK_SW4A3" ], [ - "MONITOR_SW2A2_7", - "VFRAME_SW2A2" + "BRAM_SW4END0_2", + "VBRK_SW4END0" ], [ - "MONITOR_ER1BEG3_7", - "VFRAME_ER1BEG3" + "BRAM_SW4END1_2", + "VBRK_SW4END1" ], [ - "MONITOR_NE4C0_7", - "VFRAME_NE4C0" + "BRAM_SW4END2_2", + "VBRK_SW4END2" ], [ - "MONITOR_EE2A0_7", - "VFRAME_EE2A0" + "BRAM_SW4END3_2", + "VBRK_SW4END3" ], [ - "MONITOR_NE4BEG0_7", - "VFRAME_NE4BEG0" + "BRAM_WL1END0_2", + "VBRK_WL1END0" ], [ - "MONITOR_IMUX30_7", - "VFRAME_IMUX30" + "BRAM_WL1END1_2", + "VBRK_WL1END1" ], [ - "MONITOR_IMUX36_7", - "VFRAME_IMUX36" + "BRAM_WL1END2_2", + "VBRK_WL1END2" ], [ - "MONITOR_SW4END1_7", - "VFRAME_SW4END1" + "BRAM_WL1END3_2", + "VBRK_WL1END3" ], [ - "MONITOR_EE2A2_7", - "VFRAME_EE2A2" + "BRAM_WR1END0_2", + "VBRK_WR1END0" ], [ - "MONITOR_EE2BEG1_7", - "VFRAME_EE2BEG1" + "BRAM_WR1END1_2", + "VBRK_WR1END1" ], [ - "MONITOR_IMUX3_7", - "VFRAME_IMUX3" + "BRAM_WR1END2_2", + "VBRK_WR1END2" ], [ - "MONITOR_IMUX15_7", - "VFRAME_IMUX15" + "BRAM_WR1END3_2", + "VBRK_WR1END3" ], [ - "MONITOR_WW2A2_7", - "VFRAME_WW2A2" + "BRAM_WW2A0_2", + "VBRK_WW2A0" ], [ - "MONITOR_IMUX45_7", - "VFRAME_IMUX45" + "BRAM_WW2A1_2", + "VBRK_WW2A1" ], [ - "MONITOR_IMUX37_7", - "VFRAME_IMUX37" + "BRAM_WW2A2_2", + "VBRK_WW2A2" ], [ - "MONITOR_LH2_7", - "VFRAME_LH2" + "BRAM_WW2A3_2", + "VBRK_WW2A3" ], [ - "MONITOR_EE4A1_7", - "VFRAME_EE4A1" + "BRAM_WW2END0_2", + "VBRK_WW2END0" ], [ - "MONITOR_IMUX46_7", - "VFRAME_IMUX46" + "BRAM_WW2END1_2", + "VBRK_WW2END1" ], [ - "MONITOR_EE2BEG2_7", - "VFRAME_EE2BEG2" + "BRAM_WW2END2_2", + "VBRK_WW2END2" ], [ - "MONITOR_FAN4_7", - "VFRAME_FAN4" + "BRAM_WW2END3_2", + "VBRK_WW2END3" ], [ - "MONITOR_LH3_7", - "VFRAME_LH3" + "BRAM_WW4A0_2", + "VBRK_WW4A0" ], [ - "MONITOR_EE4A3_7", - "VFRAME_EE4A3" + "BRAM_WW4A1_2", + "VBRK_WW4A1" ], [ - "MONITOR_LH12_7", - "VFRAME_LH12" + "BRAM_WW4A2_2", + "VBRK_WW4A2" ], [ - "MONITOR_EE4C2_7", - "VFRAME_EE4C2" + "BRAM_WW4A3_2", + "VBRK_WW4A3" ], [ - "MONITOR_EE4BEG0_7", - "VFRAME_EE4BEG0" + "BRAM_WW4B0_2", + "VBRK_WW4B0" ], [ - "MONITOR_SW2A3_7", - "VFRAME_SW2A3" + "BRAM_WW4B1_2", + "VBRK_WW4B1" ], [ - "MONITOR_SE4BEG0_7", - "VFRAME_SE4BEG0" + "BRAM_WW4B2_2", + "VBRK_WW4B2" ], [ - "MONITOR_WW4A3_7", - "VFRAME_WW4A3" + "BRAM_WW4B3_2", + "VBRK_WW4B3" ], [ - "MONITOR_WW4C0_7", - "VFRAME_WW4C0" + "BRAM_WW4C0_2", + "VBRK_WW4C0" ], [ - "MONITOR_SW2A1_7", - "VFRAME_SW2A1" + "BRAM_WW4C1_2", + "VBRK_WW4C1" ], [ - "MONITOR_IMUX39_7", - "VFRAME_IMUX39" + "BRAM_WW4C2_2", + "VBRK_WW4C2" ], [ - "MONITOR_NE4C3_7", - "VFRAME_NE4C3" + "BRAM_WW4C3_2", + "VBRK_WW4C3" ], [ - "MONITOR_IMUX19_7", - "VFRAME_IMUX19" + "BRAM_WW4END0_2", + "VBRK_WW4END0" ], [ - "MONITOR_LH6_7", - "VFRAME_LH6" + "BRAM_WW4END1_2", + "VBRK_WW4END1" ], [ - "MONITOR_NW4END3_7", - "VFRAME_NW4END3" + "BRAM_WW4END2_2", + "VBRK_WW4END2" ], [ - "MONITOR_IMUX10_7", - "VFRAME_IMUX10" + "BRAM_WW4END3_2", + "VBRK_WW4END3" ] ] }, @@ -21294,424 +18018,328 @@ ], "wire_pairs": [ [ - "BRAM_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "BRAM_ER1BEG0_1", - "VBRK_ER1BEG0" + "BRAM_EE2A0_1", + "VBRK_EE2A0" ], [ "BRAM_EE2A1_1", "VBRK_EE2A1" ], [ - "BRAM_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "BRAM_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "BRAM_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "BRAM_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "BRAM_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "BRAM_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "BRAM_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "BRAM_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "BRAM_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "BRAM_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "BRAM_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "BRAM_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "BRAM_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "BRAM_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "BRAM_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "BRAM_LH9_1", - "VBRK_LH9" - ], - [ - "BRAM_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "BRAM_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "BRAM_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "BRAM_WL1END0_1", - "VBRK_WL1END0" + "BRAM_EE2A2_1", + "VBRK_EE2A2" ], [ "BRAM_EE2A3_1", "VBRK_EE2A3" ], - [ - "BRAM_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "BRAM_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "BRAM_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "BRAM_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "BRAM_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "BRAM_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "BRAM_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "BRAM_LH10_1", - "VBRK_LH10" - ], - [ - "BRAM_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "BRAM_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "BRAM_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "BRAM_LH3_1", - "VBRK_LH3" - ], - [ - "BRAM_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "BRAM_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "BRAM_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "BRAM_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "BRAM_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "BRAM_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "BRAM_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "BRAM_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "BRAM_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "BRAM_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "BRAM_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "BRAM_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "BRAM_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "BRAM_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "BRAM_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "BRAM_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "BRAM_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "BRAM_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "BRAM_EE4C3_1", - "VBRK_EE4C3" - ], [ "BRAM_EE2BEG0_1", "VBRK_EE2BEG0" ], - [ - "BRAM_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "BRAM_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "BRAM_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "BRAM_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "BRAM_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "BRAM_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "BRAM_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "BRAM_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "BRAM_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "BRAM_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "BRAM_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "BRAM_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "BRAM_LH4_1", - "VBRK_LH4" - ], - [ - "BRAM_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "BRAM_LH1_1", - "VBRK_LH1" - ], - [ - "BRAM_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "BRAM_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "BRAM_LH2_1", - "VBRK_LH2" - ], - [ - "BRAM_LH7_1", - "VBRK_LH7" - ], - [ - "BRAM_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "BRAM_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "BRAM_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "BRAM_LH12_1", - "VBRK_LH12" - ], - [ - "BRAM_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "BRAM_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "BRAM_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "BRAM_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "BRAM_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "BRAM_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "BRAM_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "BRAM_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "BRAM_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "BRAM_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "BRAM_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "BRAM_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "BRAM_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "BRAM_LH8_1", - "VBRK_LH8" - ], [ "BRAM_EE2BEG1_1", "VBRK_EE2BEG1" ], [ - "BRAM_SE4BEG1_1", - "VBRK_SE4BEG1" + "BRAM_EE2BEG2_1", + "VBRK_EE2BEG2" ], [ - "BRAM_NW4END0_1", - "VBRK_NW4END0" + "BRAM_EE2BEG3_1", + "VBRK_EE2BEG3" ], [ - "BRAM_WR1END0_1", - "VBRK_WR1END0" + "BRAM_EE4A0_1", + "VBRK_EE4A0" ], [ - "BRAM_WW2A3_1", - "VBRK_WW2A3" + "BRAM_EE4A1_1", + "VBRK_EE4A1" ], [ - "BRAM_EE2A0_1", - "VBRK_EE2A0" + "BRAM_EE4A2_1", + "VBRK_EE4A2" ], [ - "BRAM_SE4C2_1", - "VBRK_SE4C2" + "BRAM_EE4A3_1", + "VBRK_EE4A3" ], [ - "BRAM_SE2A3_1", - "VBRK_SE2A3" + "BRAM_EE4B0_1", + "VBRK_EE4B0" + ], + [ + "BRAM_EE4B1_1", + "VBRK_EE4B1" + ], + [ + "BRAM_EE4B2_1", + "VBRK_EE4B2" + ], + [ + "BRAM_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "BRAM_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "BRAM_EE4BEG1_1", + "VBRK_EE4BEG1" + ], + [ + "BRAM_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "BRAM_EE4BEG3_1", + "VBRK_EE4BEG3" + ], + [ + "BRAM_EE4C0_1", + "VBRK_EE4C0" + ], + [ + "BRAM_EE4C1_1", + "VBRK_EE4C1" + ], + [ + "BRAM_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "BRAM_EE4C3_1", + "VBRK_EE4C3" + ], + [ + "BRAM_EL1BEG0_1", + "VBRK_EL1BEG0" + ], + [ + "BRAM_EL1BEG1_1", + "VBRK_EL1BEG1" + ], + [ + "BRAM_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "BRAM_EL1BEG3_1", + "VBRK_EL1BEG3" + ], + [ + "BRAM_ER1BEG0_1", + "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_1", "VBRK_ER1BEG1" ], + [ + "BRAM_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "BRAM_ER1BEG3_1", + "VBRK_ER1BEG3" + ], + [ + "BRAM_LH1_1", + "VBRK_LH1" + ], + [ + "BRAM_LH2_1", + "VBRK_LH2" + ], + [ + "BRAM_LH3_1", + "VBRK_LH3" + ], + [ + "BRAM_LH4_1", + "VBRK_LH4" + ], + [ + "BRAM_LH5_1", + "VBRK_LH5" + ], + [ + "BRAM_LH6_1", + "VBRK_LH6" + ], + [ + "BRAM_LH7_1", + "VBRK_LH7" + ], + [ + "BRAM_LH8_1", + "VBRK_LH8" + ], + [ + "BRAM_LH9_1", + "VBRK_LH9" + ], + [ + "BRAM_LH10_1", + "VBRK_LH10" + ], + [ + "BRAM_LH11_1", + "VBRK_LH11" + ], + [ + "BRAM_LH12_1", + "VBRK_LH12" + ], + [ + "BRAM_MONITOR_N_1", + "VBRK_MONITOR_N" + ], + [ + "BRAM_MONITOR_P_1", + "VBRK_MONITOR_P" + ], + [ + "BRAM_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "BRAM_NE2A1_1", + "VBRK_NE2A1" + ], + [ + "BRAM_NE2A2_1", + "VBRK_NE2A2" + ], + [ + "BRAM_NE2A3_1", + "VBRK_NE2A3" + ], + [ + "BRAM_NE4BEG0_1", + "VBRK_NE4BEG0" + ], + [ + "BRAM_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "BRAM_NE4BEG2_1", + "VBRK_NE4BEG2" + ], + [ + "BRAM_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "BRAM_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "BRAM_NE4C1_1", + "VBRK_NE4C1" + ], + [ + "BRAM_NE4C2_1", + "VBRK_NE4C2" + ], [ "BRAM_NE4C3_1", "VBRK_NE4C3" ], [ - "BRAM_WR1END2_1", - "VBRK_WR1END2" + "BRAM_NW2A0_1", + "VBRK_NW2A0" ], [ - "BRAM_SW2A2_1", - "VBRK_SW2A2" + "BRAM_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "BRAM_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "BRAM_NW2A3_1", + "VBRK_NW2A3" + ], + [ + "BRAM_NW4A0_1", + "VBRK_NW4A0" + ], + [ + "BRAM_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "BRAM_NW4A2_1", + "VBRK_NW4A2" + ], + [ + "BRAM_NW4A3_1", + "VBRK_NW4A3" + ], + [ + "BRAM_NW4END0_1", + "VBRK_NW4END0" + ], + [ + "BRAM_NW4END1_1", + "VBRK_NW4END1" + ], + [ + "BRAM_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "BRAM_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "BRAM_SE2A0_1", + "VBRK_SE2A0" + ], + [ + "BRAM_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "BRAM_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "BRAM_SE2A3_1", + "VBRK_SE2A3" + ], + [ + "BRAM_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "BRAM_SE4BEG1_1", + "VBRK_SE4BEG1" + ], + [ + "BRAM_SE4BEG2_1", + "VBRK_SE4BEG2" + ], + [ + "BRAM_SE4BEG3_1", + "VBRK_SE4BEG3" + ], + [ + "BRAM_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "BRAM_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "BRAM_SE4C2_1", + "VBRK_SE4C2" ], [ "BRAM_SE4C3_1", @@ -21721,15697 +18349,17045 @@ "BRAM_SW2A0_1", "VBRK_SW2A0" ], + [ + "BRAM_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "BRAM_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "BRAM_SW2A3_1", + "VBRK_SW2A3" + ], [ "BRAM_SW4A0_1", "VBRK_SW4A0" ], [ - "BRAM_WW4C1_1", - "VBRK_WW4C1" + "BRAM_SW4A1_1", + "VBRK_SW4A1" ], [ - "BRAM_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "BRAM_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "BRAM_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "BRAM_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "BRAM_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "BRAM_LH11_1", - "VBRK_LH11" - ], - [ - "BRAM_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "BRAM_WW2A2_1", - "VBRK_WW2A2" + "BRAM_SW4A2_1", + "VBRK_SW4A2" ], [ "BRAM_SW4A3_1", "VBRK_SW4A3" ], [ - "BRAM_SE2A2_1", - "VBRK_SE2A2" + "BRAM_SW4END0_1", + "VBRK_SW4END0" ], [ - "BRAM_LH6_1", + "BRAM_SW4END1_1", + "VBRK_SW4END1" + ], + [ + "BRAM_SW4END2_1", + "VBRK_SW4END2" + ], + [ + "BRAM_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "BRAM_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "BRAM_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "BRAM_WL1END2_1", + "VBRK_WL1END2" + ], + [ + "BRAM_WL1END3_1", + "VBRK_WL1END3" + ], + [ + "BRAM_WR1END0_1", + "VBRK_WR1END0" + ], + [ + "BRAM_WR1END1_1", + "VBRK_WR1END1" + ], + [ + "BRAM_WR1END2_1", + "VBRK_WR1END2" + ], + [ + "BRAM_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "BRAM_WW2A0_1", + "VBRK_WW2A0" + ], + [ + "BRAM_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "BRAM_WW2A2_1", + "VBRK_WW2A2" + ], + [ + "BRAM_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "BRAM_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "BRAM_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "BRAM_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "BRAM_WW2END3_1", + "VBRK_WW2END3" + ], + [ + "BRAM_WW4A0_1", + "VBRK_WW4A0" + ], + [ + "BRAM_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "BRAM_WW4A2_1", + "VBRK_WW4A2" + ], + [ + "BRAM_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "BRAM_WW4B0_1", + "VBRK_WW4B0" + ], + [ + "BRAM_WW4B1_1", + "VBRK_WW4B1" + ], + [ + "BRAM_WW4B2_1", + "VBRK_WW4B2" + ], + [ + "BRAM_WW4B3_1", + "VBRK_WW4B3" + ], + [ + "BRAM_WW4C0_1", + "VBRK_WW4C0" + ], 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"CFG_CENTER_EE2BEG1_18", + "INT_FEEDTHRU_2_EE2BEG1" ], [ - "CLK_HROW_WR1END3_0", - "INT_INTERFACE_WR1END3" + "CFG_CENTER_EE2BEG2_18", + "INT_FEEDTHRU_2_EE2BEG2" ], [ - "CLK_HROW_SW4END0_0", - "INT_INTERFACE_SW4END0" + "CFG_CENTER_EE2BEG3_18", + "INT_FEEDTHRU_2_EE2BEG3" ], [ - "CLK_HROW_LH9_0", - "INT_INTERFACE_LH9" + "CFG_CENTER_EE4A0_18", + "INT_FEEDTHRU_2_EE4A0" ], [ - "CLK_BUFG_IMUX10_0", - "INT_INTERFACE_IMUX10" + "CFG_CENTER_EE4A1_18", + "INT_FEEDTHRU_2_EE4A1" ], [ - "CLK_BUFG_LOGIC_OUTS_B1_0", - "INT_INTERFACE_LOGIC_OUTS_B1" + "CFG_CENTER_EE4A2_18", + "INT_FEEDTHRU_2_EE4A2" ], [ - "CLK_HROW_WR1END1_0", - "INT_INTERFACE_WR1END1" + "CFG_CENTER_EE4A3_18", + "INT_FEEDTHRU_2_EE4A3" ], [ - "CLK_HROW_SW4END2_0", - "INT_INTERFACE_SW4END2" + "CFG_CENTER_EE4B0_18", + "INT_FEEDTHRU_2_EE4B0" ], [ - "CLK_HROW_SE4C0_0", - "INT_INTERFACE_SE4C0" + "CFG_CENTER_EE4B1_18", + "INT_FEEDTHRU_2_EE4B1" ], [ - "CLK_HROW_SE2A0_0", - "INT_INTERFACE_SE2A0" + "CFG_CENTER_EE4B2_18", + "INT_FEEDTHRU_2_EE4B2" ], [ - "CLK_BUFG_IMUX12_0", - "INT_INTERFACE_IMUX12" + "CFG_CENTER_EE4B3_18", + "INT_FEEDTHRU_2_EE4B3" ], [ - "CLK_BUFG_IMUX31_0", - "INT_INTERFACE_IMUX31" + "CFG_CENTER_EE4BEG0_18", + "INT_FEEDTHRU_2_EE4BEG0" ], [ - "CLK_HROW_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" + "CFG_CENTER_EE4BEG1_18", + "INT_FEEDTHRU_2_EE4BEG1" ], [ - "CLK_BUFG_IMUX44_0", - "INT_INTERFACE_IMUX44" + "CFG_CENTER_EE4BEG2_18", + "INT_FEEDTHRU_2_EE4BEG2" ], [ - "CLK_BUFG_IMUX18_0", - "INT_INTERFACE_IMUX18" + "CFG_CENTER_EE4BEG3_18", + "INT_FEEDTHRU_2_EE4BEG3" ], [ - "CLK_HROW_LH2_0", - "INT_INTERFACE_LH2" + "CFG_CENTER_EE4C0_18", + "INT_FEEDTHRU_2_EE4C0" ], [ - "CLK_BUFG_IMUX43_0", - "INT_INTERFACE_IMUX43" + "CFG_CENTER_EE4C1_18", + "INT_FEEDTHRU_2_EE4C1" ], [ - "CLK_HROW_WW4END0_0", - "INT_INTERFACE_WW4END0" + "CFG_CENTER_EE4C2_18", + "INT_FEEDTHRU_2_EE4C2" ], [ - "CLK_HROW_FAN2_0", - "INT_INTERFACE_FAN2" + "CFG_CENTER_EE4C3_18", + "INT_FEEDTHRU_2_EE4C3" ], [ - "CLK_BUFG_IMUX40_0", - "INT_INTERFACE_IMUX40" + "CFG_CENTER_EL1BEG0_18", + "INT_FEEDTHRU_2_EL1BEG0" ], [ - "CLK_HROW_SE2A3_0", - "INT_INTERFACE_SE2A3" + "CFG_CENTER_EL1BEG1_18", + "INT_FEEDTHRU_2_EL1BEG1" ], [ - "CLK_HROW_SE4C2_0", - "INT_INTERFACE_SE4C2" + "CFG_CENTER_EL1BEG2_18", + "INT_FEEDTHRU_2_EL1BEG2" ], [ - "CLK_HROW_EE4B0_0", - "INT_INTERFACE_EE4B0" + "CFG_CENTER_EL1BEG3_18", + "INT_FEEDTHRU_2_EL1BEG3" ], [ - "CLK_HROW_WW2A1_0", - "INT_INTERFACE_WW2A1" + "CFG_CENTER_ER1BEG0_18", + "INT_FEEDTHRU_2_ER1BEG0" ], [ - "CLK_BUFG_IMUX11_0", - "INT_INTERFACE_IMUX11" + "CFG_CENTER_ER1BEG1_18", + "INT_FEEDTHRU_2_ER1BEG1" ], [ - "CLK_HROW_NE2A1_0", - "INT_INTERFACE_NE2A1" + "CFG_CENTER_ER1BEG2_18", + "INT_FEEDTHRU_2_ER1BEG2" ], [ - "CLK_HROW_SW4END3_0", - "INT_INTERFACE_SW4END3" + "CFG_CENTER_ER1BEG3_18", + "INT_FEEDTHRU_2_ER1BEG3" ], [ - "CLK_BUFG_IMUX34_0", - "INT_INTERFACE_IMUX34" + "CFG_CENTER_LH1_18", + "INT_FEEDTHRU_2_LH1" ], [ - "CLK_HROW_NW4A0_0", - "INT_INTERFACE_NW4A0" + "CFG_CENTER_LH2_18", + "INT_FEEDTHRU_2_LH2" ], [ - "CLK_HROW_NW4END2_0", - "INT_INTERFACE_NW4END2" + "CFG_CENTER_LH3_18", + "INT_FEEDTHRU_2_LH3" ], [ - "CLK_HROW_WW2A2_0", - "INT_INTERFACE_WW2A2" + "CFG_CENTER_LH4_18", + "INT_FEEDTHRU_2_LH4" ], [ - "CLK_BUFG_LOGIC_OUTS_B6_0", - "INT_INTERFACE_LOGIC_OUTS_B6" + "CFG_CENTER_LH5_18", + "INT_FEEDTHRU_2_LH5" ], [ - "CLK_HROW_WW4B1_0", - "INT_INTERFACE_WW4B1" + "CFG_CENTER_LH6_18", + "INT_FEEDTHRU_2_LH6" ], [ - "CLK_BUFG_IMUX6_0", - "INT_INTERFACE_IMUX6" + "CFG_CENTER_LH7_18", + "INT_FEEDTHRU_2_LH7" ], [ - "CLK_HROW_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" + "CFG_CENTER_LH8_18", + "INT_FEEDTHRU_2_LH8" ], [ - "CLK_HROW_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" + "CFG_CENTER_LH9_18", + "INT_FEEDTHRU_2_LH9" ], [ - "CLK_BUFG_LOGIC_OUTS_B4_0", - "INT_INTERFACE_LOGIC_OUTS_B4" + "CFG_CENTER_LH10_18", + "INT_FEEDTHRU_2_LH10" ], [ - "CLK_HROW_WW4C3_0", - "INT_INTERFACE_WW4C3" + "CFG_CENTER_LH11_18", + "INT_FEEDTHRU_2_LH11" ], [ - "CLK_BUFG_IMUX23_0", - "INT_INTERFACE_IMUX23" + "CFG_CENTER_LH12_18", + "INT_FEEDTHRU_2_LH12" ], [ - "CLK_HROW_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" + "CFG_CENTER_NE2A0_18", + "INT_FEEDTHRU_2_NE2A0" ], [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" + "CFG_CENTER_NE2A1_18", + "INT_FEEDTHRU_2_NE2A1" ], [ - "CLK_HROW_WL1END2_0", - "INT_INTERFACE_WL1END2" + "CFG_CENTER_NE2A2_18", + "INT_FEEDTHRU_2_NE2A2" ], [ - "CLK_BUFG_IMUX32_0", - "INT_INTERFACE_IMUX32" + "CFG_CENTER_NE2A3_18", + "INT_FEEDTHRU_2_NE2A3" ], [ - "CLK_HROW_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" + "CFG_CENTER_NE4BEG0_18", + "INT_FEEDTHRU_2_NE4BEG0" ], [ - "CLK_HROW_WW4B2_0", - "INT_INTERFACE_WW4B2" + "CFG_CENTER_NE4BEG1_18", + "INT_FEEDTHRU_2_NE4BEG1" ], [ - "CLK_HROW_NE4C3_0", - "INT_INTERFACE_NE4C3" + "CFG_CENTER_NE4BEG2_18", + "INT_FEEDTHRU_2_NE4BEG2" ], [ - "CLK_BUFG_IMUX14_0", - "INT_INTERFACE_IMUX14" + "CFG_CENTER_NE4BEG3_18", + "INT_FEEDTHRU_2_NE4BEG3" ], [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" + "CFG_CENTER_NE4C0_18", + "INT_FEEDTHRU_2_NE4C0" ], [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" + "CFG_CENTER_NE4C1_18", + "INT_FEEDTHRU_2_NE4C1" ], [ - "CLK_HROW_LH7_0", - "INT_INTERFACE_LH7" + "CFG_CENTER_NE4C2_18", + "INT_FEEDTHRU_2_NE4C2" ], [ - "CLK_BUFG_IMUX42_0", - "INT_INTERFACE_IMUX42" + "CFG_CENTER_NE4C3_18", + "INT_FEEDTHRU_2_NE4C3" ], [ - "CLK_BUFG_LOGIC_OUTS_B3_0", - "INT_INTERFACE_LOGIC_OUTS_B3" + "CFG_CENTER_NW2A0_18", + "INT_FEEDTHRU_2_NW2A0" ], [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" + "CFG_CENTER_NW2A1_18", + "INT_FEEDTHRU_2_NW2A1" ], [ - "CLK_BUFG_IMUX46_0", - "INT_INTERFACE_IMUX46" + "CFG_CENTER_NW2A2_18", + "INT_FEEDTHRU_2_NW2A2" ], [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" + "CFG_CENTER_NW2A3_18", + "INT_FEEDTHRU_2_NW2A3" ], [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" + "CFG_CENTER_NW4A0_18", + "INT_FEEDTHRU_2_NW4A0" ], [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" + "CFG_CENTER_NW4A1_18", + "INT_FEEDTHRU_2_NW4A1" ], [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" + "CFG_CENTER_NW4A2_18", + "INT_FEEDTHRU_2_NW4A2" ], [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" + "CFG_CENTER_NW4A3_18", + "INT_FEEDTHRU_2_NW4A3" ], [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" + "CFG_CENTER_NW4END0_18", + "INT_FEEDTHRU_2_NW4END0" ], [ - "CLK_HROW_NW4A3_0", - "INT_INTERFACE_NW4A3" + "CFG_CENTER_NW4END1_18", + "INT_FEEDTHRU_2_NW4END1" ], [ - "CLK_HROW_WW4END1_0", - "INT_INTERFACE_WW4END1" + "CFG_CENTER_NW4END2_18", + "INT_FEEDTHRU_2_NW4END2" ], [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" + "CFG_CENTER_NW4END3_18", + "INT_FEEDTHRU_2_NW4END3" ], [ - "CLK_BUFG_IMUX24_0", - "INT_INTERFACE_IMUX24" + "CFG_CENTER_SE2A0_18", + "INT_FEEDTHRU_2_SE2A0" ], [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" + "CFG_CENTER_SE2A1_18", + "INT_FEEDTHRU_2_SE2A1" ], [ - "CLK_BUFG_IMUX9_0", - "INT_INTERFACE_IMUX9" + "CFG_CENTER_SE2A2_18", + "INT_FEEDTHRU_2_SE2A2" ], [ - "CLK_BUFG_IMUX35_0", - "INT_INTERFACE_IMUX35" + "CFG_CENTER_SE2A3_18", + "INT_FEEDTHRU_2_SE2A3" ], [ - "CLK_HROW_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" + "CFG_CENTER_SE4BEG0_18", + "INT_FEEDTHRU_2_SE4BEG0" ], [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" + "CFG_CENTER_SE4BEG1_18", + "INT_FEEDTHRU_2_SE4BEG1" ], [ - "CLK_HROW_EE2A1_0", - "INT_INTERFACE_EE2A1" + "CFG_CENTER_SE4BEG2_18", + "INT_FEEDTHRU_2_SE4BEG2" ], [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" + "CFG_CENTER_SE4BEG3_18", + "INT_FEEDTHRU_2_SE4BEG3" ], [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" + "CFG_CENTER_SE4C0_18", + "INT_FEEDTHRU_2_SE4C0" ], [ - "CLK_HROW_EE4C2_0", - "INT_INTERFACE_EE4C2" + "CFG_CENTER_SE4C1_18", + "INT_FEEDTHRU_2_SE4C1" ], [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" + "CFG_CENTER_SE4C2_18", + "INT_FEEDTHRU_2_SE4C2" ], [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" + "CFG_CENTER_SE4C3_18", + "INT_FEEDTHRU_2_SE4C3" ], [ - "CLK_HROW_BYP7_0", - "INT_INTERFACE_BYP7" + "CFG_CENTER_SW2A0_18", + "INT_FEEDTHRU_2_SW2A0" ], [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" + "CFG_CENTER_SW2A1_18", + "INT_FEEDTHRU_2_SW2A1" ], [ - "CLK_HROW_FAN6_0", - "INT_INTERFACE_FAN6" + "CFG_CENTER_SW2A2_18", + "INT_FEEDTHRU_2_SW2A2" ], [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" + "CFG_CENTER_SW2A3_18", + "INT_FEEDTHRU_2_SW2A3" ], [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" + "CFG_CENTER_SW4A0_18", + "INT_FEEDTHRU_2_SW4A0" ], [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" + "CFG_CENTER_SW4A1_18", + "INT_FEEDTHRU_2_SW4A1" ], [ - "CLK_BUFG_LOGIC_OUTS_B0_0", - "INT_INTERFACE_LOGIC_OUTS_B0" + "CFG_CENTER_SW4A2_18", + "INT_FEEDTHRU_2_SW4A2" ], [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" + "CFG_CENTER_SW4A3_18", + "INT_FEEDTHRU_2_SW4A3" ], [ - "CLK_BUFG_IMUX47_0", - "INT_INTERFACE_IMUX47" + "CFG_CENTER_SW4END0_18", + "INT_FEEDTHRU_2_SW4END0" ], [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" + "CFG_CENTER_SW4END1_18", + "INT_FEEDTHRU_2_SW4END1" ], [ - "CLK_HROW_EE4A3_0", - "INT_INTERFACE_EE4A3" + "CFG_CENTER_SW4END2_18", + "INT_FEEDTHRU_2_SW4END2" ], [ - "CLK_BUFG_IMUX25_0", - "INT_INTERFACE_IMUX25" + "CFG_CENTER_SW4END3_18", + "INT_FEEDTHRU_2_SW4END3" ], [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" + "CFG_CENTER_WL1END0_18", + "INT_FEEDTHRU_2_WL1END0" ], [ - "CLK_BUFG_IMUX2_0", - "INT_INTERFACE_IMUX2" + "CFG_CENTER_WL1END1_18", + "INT_FEEDTHRU_2_WL1END1" ], [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" + "CFG_CENTER_WL1END2_18", + "INT_FEEDTHRU_2_WL1END2" ], [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" + "CFG_CENTER_WL1END3_18", + "INT_FEEDTHRU_2_WL1END3" ], [ - "CLK_BUFG_IMUX7_0", - "INT_INTERFACE_IMUX7" + "CFG_CENTER_WR1END0_18", + "INT_FEEDTHRU_2_WR1END0" ], [ - "CLK_HROW_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" + "CFG_CENTER_WR1END1_18", + "INT_FEEDTHRU_2_WR1END1" ], [ - "CLK_BUFG_IMUX45_0", - "INT_INTERFACE_IMUX45" + "CFG_CENTER_WR1END2_18", + "INT_FEEDTHRU_2_WR1END2" ], [ - "CLK_HROW_NE2A3_0", - "INT_INTERFACE_NE2A3" + "CFG_CENTER_WR1END3_18", + "INT_FEEDTHRU_2_WR1END3" ], [ - "CLK_BUFG_IMUX33_0", - "INT_INTERFACE_IMUX33" + "CFG_CENTER_WW2A0_18", + "INT_FEEDTHRU_2_WW2A0" ], [ - "CLK_BUFG_IMUX39_0", - "INT_INTERFACE_IMUX39" + "CFG_CENTER_WW2A1_18", + "INT_FEEDTHRU_2_WW2A1" ], [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" + "CFG_CENTER_WW2A2_18", + "INT_FEEDTHRU_2_WW2A2" ], [ - "CLK_HROW_EE4A0_0", - "INT_INTERFACE_EE4A0" + "CFG_CENTER_WW2A3_18", + "INT_FEEDTHRU_2_WW2A3" ], [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" + "CFG_CENTER_WW2END0_18", + "INT_FEEDTHRU_2_WW2END0" ], [ - "CLK_BUFG_IMUX17_0", - "INT_INTERFACE_IMUX17" + "CFG_CENTER_WW2END1_18", + "INT_FEEDTHRU_2_WW2END1" ], [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" + "CFG_CENTER_WW2END2_18", + "INT_FEEDTHRU_2_WW2END2" ], [ - "CLK_HROW_WW2END0_0", - "INT_INTERFACE_WW2END0" + "CFG_CENTER_WW2END3_18", + "INT_FEEDTHRU_2_WW2END3" ], [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" + "CFG_CENTER_WW4A0_18", + "INT_FEEDTHRU_2_WW4A0" ], [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" + "CFG_CENTER_WW4A1_18", + "INT_FEEDTHRU_2_WW4A1" ], [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" + "CFG_CENTER_WW4A2_18", + "INT_FEEDTHRU_2_WW4A2" ], [ - "CLK_HROW_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" + "CFG_CENTER_WW4A3_18", + "INT_FEEDTHRU_2_WW4A3" ], [ - "CLK_BUFG_IMUX37_0", - "INT_INTERFACE_IMUX37" + "CFG_CENTER_WW4B0_18", + "INT_FEEDTHRU_2_WW4B0" ], [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" + "CFG_CENTER_WW4B1_18", + "INT_FEEDTHRU_2_WW4B1" ], [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" + "CFG_CENTER_WW4B2_18", + "INT_FEEDTHRU_2_WW4B2" ], [ - "CLK_BUFG_IMUX19_0", - "INT_INTERFACE_IMUX19" + "CFG_CENTER_WW4B3_18", + "INT_FEEDTHRU_2_WW4B3" ], [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" + "CFG_CENTER_WW4C0_18", + "INT_FEEDTHRU_2_WW4C0" ], [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" + "CFG_CENTER_WW4C1_18", + "INT_FEEDTHRU_2_WW4C1" ], [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" + "CFG_CENTER_WW4C2_18", + "INT_FEEDTHRU_2_WW4C2" ], [ - "CLK_BUFG_IMUX36_0", - "INT_INTERFACE_IMUX36" + "CFG_CENTER_WW4C3_18", + "INT_FEEDTHRU_2_WW4C3" ], [ - "CLK_HROW_WR1END2_0", - "INT_INTERFACE_WR1END2" + "CFG_CENTER_WW4END0_18", + "INT_FEEDTHRU_2_WW4END0" ], [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" + "CFG_CENTER_WW4END1_18", + "INT_FEEDTHRU_2_WW4END1" ], [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" + "CFG_CENTER_WW4END2_18", + "INT_FEEDTHRU_2_WW4END2" ], [ - "CLK_HROW_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_BUFG_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_BUFG_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_HROW_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_BUFG_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_BUFG_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_BUFG_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_BUFG_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_0", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_BUFG_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_BUFG_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_BUFG_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_BUFG_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_BUFG_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_0", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_BUFG_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_BUFG_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_BUFG_IMUX22_0", - "INT_INTERFACE_IMUX22" - ] - ] - }, - { - "grid_deltas": [ - 5, - 10 - ], - "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_L" - ], - "wire_pairs": [ - [ - "PCIE_IMUX28_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT28" - ], - [ - "PCIE_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "PCIE_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "PCIE_IMUX3_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT3" - ], - [ - "PCIE_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "PCIE_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "PCIE_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "PCIE_IMUX1_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT1" - ], - [ - "PCIE_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "PCIE_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "PCIE_IMUX41_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT41" - ], - [ - "PCIE_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "PCIE_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "PCIE_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "PCIE_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "PCIE_IMUX23_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT23" - ], - [ - "PCIE_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "PCIE_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "PCIE_FAN0_L_0", - "INT_INTERFACE_FAN0" - ], - [ - "PCIE_FAN6_L_0", - "INT_INTERFACE_FAN6" - ], - [ - "PCIE_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "PCIE_IMUX36_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT36" - ], - [ - "PCIE_BYP5_L_0", - "INT_INTERFACE_BYP5" - ], - [ - "PCIE_SE4C0_0", - "INT_INTERFACE_SE4C0" - ], - [ - "PCIE_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "PCIE_LOGIC_OUTS_B6_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B6" - ], - [ - "PCIE_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "PCIE_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "PCIE_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "PCIE_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "PCIE_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "PCIE_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "PCIE_LOGIC_OUTS_B19_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B19" - ], - [ - "PCIE_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "PCIE_IMUX17_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT17" - ], - [ - "PCIE_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "PCIE_CLK1_L_0", - "INT_INTERFACE_CLK1" - ], - [ - "PCIE_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "PCIE_IMUX39_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT39" - ], - [ - "PCIE_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "PCIE_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "PCIE_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "PCIE_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "PCIE_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "PCIE_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "PCIE_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "PCIE_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "PCIE_LH1_0", - "INT_INTERFACE_LH1" - ], - [ - "PCIE_IMUX25_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT25" - ], - [ - "PCIE_IMUX40_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT40" - ], - [ - "PCIE_IMUX14_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT14" - ], - [ - "PCIE_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "PCIE_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "PCIE_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "PCIE_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "PCIE_IMUX32_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT32" - ], - [ - "PCIE_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "PCIE_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "PCIE_LOGIC_OUTS_B13_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B13" - ], - [ - "PCIE_IMUX46_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT46" - ], - [ - "PCIE_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "PCIE_LOGIC_OUTS_B17_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B17" - ], - [ - "PCIE_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "PCIE_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "PCIE_LOGIC_OUTS_B20_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B20" - ], - [ - "PCIE_IMUX21_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT21" - ], - [ - "PCIE_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "PCIE_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "PCIE_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "PCIE_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "PCIE_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "PCIE_LOGIC_OUTS_B21_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B21" - ], - [ - "PCIE_FAN4_L_0", - "INT_INTERFACE_FAN4" - ], - [ - "PCIE_IMUX12_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT12" - ], - [ - "PCIE_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "PCIE_BYP7_L_0", - "INT_INTERFACE_BYP7" - ], - [ - "PCIE_IMUX45_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT45" - ], - [ - "PCIE_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "PCIE_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "PCIE_LOGIC_OUTS_B9_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B9" - ], - [ - "PCIE_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "PCIE_IMUX33_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT33" - ], - [ - "PCIE_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "PCIE_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "PCIE_LOGIC_OUTS_B16_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B16" - ], - [ - "PCIE_IMUX38_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT38" - ], - [ - "PCIE_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "PCIE_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "PCIE_BYP1_L_0", - "INT_INTERFACE_BYP1" - ], - [ - "PCIE_LOGIC_OUTS_B22_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B22" - ], - [ - "PCIE_IMUX5_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT5" - ], - [ - "PCIE_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "PCIE_SE2A0_0", - "INT_INTERFACE_SE2A0" - ], - [ - "PCIE_BYP6_L_0", - "INT_INTERFACE_BYP6" - ], - [ - "PCIE_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "PCIE_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "PCIE_LOGIC_OUTS_B10_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B10" - ], - [ - "PCIE_IMUX16_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT16" - ], - [ - "PCIE_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "PCIE_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "PCIE_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "PCIE_FAN3_L_0", - "INT_INTERFACE_FAN3" - ], - [ - "PCIE_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "PCIE_LOGIC_OUTS_B1_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B1" - ], - [ - "PCIE_LOGIC_OUTS_B3_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B3" - ], - [ - "PCIE_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "PCIE_IMUX0_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT0" - ], - [ - "PCIE_IMUX24_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT24" - ], - [ - "PCIE_IMUX8_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT8" - ], - [ - "PCIE_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "PCIE_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "PCIE_IMUX11_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT11" - ], - [ - "PCIE_LOGIC_OUTS_B14_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B14" - ], - [ - "PCIE_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "PCIE_LOGIC_OUTS_B0_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B0" - ], - [ - "PCIE_CTRL0_L_0", - "INT_INTERFACE_CTRL0" - ], - [ - "PCIE_CTRL1_L_0", - "INT_INTERFACE_CTRL1" - ], - [ - "PCIE_IMUX47_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT47" - ], - [ - "PCIE_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "PCIE_IMUX13_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT13" - ], - [ - "PCIE_IMUX15_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT15" - ], - [ - "PCIE_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "PCIE_NW4END2_0", - "INT_INTERFACE_NW4END2" - ], - [ - "PCIE_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "PCIE_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "PCIE_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "PCIE_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "PCIE_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "PCIE_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "PCIE_IMUX27_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT27" - ], - [ - "PCIE_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "PCIE_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "PCIE_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "PCIE_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "PCIE_IMUX31_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT31" - ], - [ - "PCIE_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "PCIE_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "PCIE_IMUX34_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT34" - ], - [ - "PCIE_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "PCIE_IMUX9_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT9" - ], - [ - "PCIE_IMUX26_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT26" - ], - [ - "PCIE_IMUX42_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT42" - ], - [ - "PCIE_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "PCIE_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "PCIE_IMUX20_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT20" - ], - [ - "PCIE_IMUX4_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT4" - ], - [ - "PCIE_IMUX35_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT35" - ], - [ - "PCIE_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "PCIE_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "PCIE_FAN5_L_0", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "PCIE_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "PCIE_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "PCIE_IMUX10_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT10" - ], - [ - "PCIE_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "PCIE_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "PCIE_LOGIC_OUTS_B4_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B4" - ], - [ - "PCIE_FAN2_L_0", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_BYP0_L_0", - "INT_INTERFACE_BYP0" - ], - [ - "PCIE_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "PCIE_SW4END0_0", - "INT_INTERFACE_SW4END0" - ], - [ - "PCIE_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "PCIE_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "PCIE_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "PCIE_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "PCIE_IMUX30_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT30" - ], - [ - "PCIE_BYP3_L_0", - "INT_INTERFACE_BYP3" - ], - [ - "PCIE_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "PCIE_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "PCIE_LH9_0", - "INT_INTERFACE_LH9" - ], - [ - "PCIE_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "PCIE_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "PCIE_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" - ], - [ - "PCIE_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "PCIE_LOGIC_OUTS_B8_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B8" - ], - [ - "PCIE_IMUX22_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT22" - ], - [ - "PCIE_IMUX43_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT43" - ], - [ - "PCIE_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "PCIE_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "PCIE_LOGIC_OUTS_B15_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B15" - ], - [ - "PCIE_IMUX37_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT37" - ], - [ - "PCIE_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "PCIE_CLK0_L_0", - "INT_INTERFACE_CLK0" - ], - [ - "PCIE_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "PCIE_LOGIC_OUTS_B2_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B2" - ], - [ - "PCIE_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "PCIE_WR1END3_0", - "INT_INTERFACE_WR1END3" - ], - [ - "PCIE_LOGIC_OUTS_B18_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B18" - ], - [ - "PCIE_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "PCIE_IMUX18_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT18" - ], - [ - "PCIE_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "PCIE_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "PCIE_IMUX2_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT2" - ], - [ - "PCIE_LOGIC_OUTS_B11_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "PCIE_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "PCIE_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "PCIE_FAN1_L_0", - "INT_INTERFACE_FAN1" - ], - [ - "PCIE_BYP2_L_0", - "INT_INTERFACE_BYP2" - ], - [ - "PCIE_LOGIC_OUTS_B7_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B7" - ], - [ - "PCIE_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "PCIE_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "PCIE_BYP4_L_0", - "INT_INTERFACE_BYP4" - ], - [ - "PCIE_LOGIC_OUTS_B12_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B12" - ], - [ - "PCIE_LOGIC_OUTS_B23_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B23" - ], - [ - "PCIE_IMUX19_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT19" - ], - [ - "PCIE_IMUX6_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT6" - ], - [ - "PCIE_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "PCIE_IMUX7_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT7" - ], - [ - "PCIE_IMUX44_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT44" - ], - [ - "PCIE_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "PCIE_IMUX29_L_0", - "PCIE_INT_INTERFACE_IMUX_L_OUT29" - ], - [ - "PCIE_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "PCIE_WL1END2_0", - "INT_INTERFACE_WL1END2" - ], - [ - "PCIE_LOGIC_OUTS_B5_L_0", - "INT_INTERFACE_LOGIC_OUTS_L_B5" - ], - [ - "PCIE_FAN7_L_0", - "INT_INTERFACE_FAN7" - ], - [ - "PCIE_SW4END2_0", - "INT_INTERFACE_SW4END2" + "CFG_CENTER_WW4END3_18", + "INT_FEEDTHRU_2_WW4END3" ] ] }, @@ -37426,208 +35402,248 @@ ], "wire_pairs": [ [ - "CFG_CENTER_WW2A2_17", - "INT_FEEDTHRU_2_WW2A2" - ], - [ - "CFG_CENTER_WW2END1_17", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_WW4C3_17", - "INT_FEEDTHRU_2_WW4C3" - ], - [ - "CFG_CENTER_EE2BEG0_17", - "INT_FEEDTHRU_2_EE2BEG0" + "CFG_CENTER_EE2A0_17", + "INT_FEEDTHRU_2_EE2A0" ], [ "CFG_CENTER_EE2A1_17", "INT_FEEDTHRU_2_EE2A1" ], [ - "CFG_CENTER_WW4C2_17", - "INT_FEEDTHRU_2_WW4C2" - ], - [ - "CFG_CENTER_EE4BEG3_17", - "INT_FEEDTHRU_2_EE4BEG3" - ], - [ - "CFG_CENTER_SW4A3_17", - "INT_FEEDTHRU_2_SW4A3" - ], - [ - "CFG_CENTER_WW2A1_17", - "INT_FEEDTHRU_2_WW2A1" - ], - [ - "CFG_CENTER_NE4C3_17", - "INT_FEEDTHRU_2_NE4C3" - ], - [ - "CFG_CENTER_LH6_17", - "INT_FEEDTHRU_2_LH6" - ], - [ - "CFG_CENTER_EE4C3_17", - "INT_FEEDTHRU_2_EE4C3" - ], - [ - "CFG_CENTER_EE4B2_17", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_EE4A0_17", - "INT_FEEDTHRU_2_EE4A0" - ], - [ - "CFG_CENTER_ER1BEG2_17", - "INT_FEEDTHRU_2_ER1BEG2" - ], - [ - "CFG_CENTER_WW4A3_17", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_EE4A1_17", - "INT_FEEDTHRU_2_EE4A1" - ], - [ - "CFG_CENTER_SW4END2_17", - "INT_FEEDTHRU_2_SW4END2" - ], - [ - "CFG_CENTER_WW4END1_17", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_LH3_17", - "INT_FEEDTHRU_2_LH3" - ], - [ - "CFG_CENTER_WR1END0_17", - "INT_FEEDTHRU_2_WR1END0" - ], - [ - "CFG_CENTER_WW2END3_17", - "INT_FEEDTHRU_2_WW2END3" - ], - [ - "CFG_CENTER_SE2A1_17", - "INT_FEEDTHRU_2_SE2A1" - ], - [ - "CFG_CENTER_SW2A1_17", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_EE4C0_17", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_SE4BEG2_17", - "INT_FEEDTHRU_2_SE4BEG2" - ], - [ - "CFG_CENTER_WW4B0_17", - "INT_FEEDTHRU_2_WW4B0" - ], - [ - "CFG_CENTER_EL1BEG3_17", - "INT_FEEDTHRU_2_EL1BEG3" - ], - [ - "CFG_CENTER_SE2A0_17", - "INT_FEEDTHRU_2_SE2A0" - ], - [ - "CFG_CENTER_WL1END3_17", - "INT_FEEDTHRU_2_WL1END3" - ], - [ - "CFG_CENTER_LH2_17", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_NE4C0_17", - "INT_FEEDTHRU_2_NE4C0" - ], - [ - "CFG_CENTER_NW2A1_17", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_WW4END2_17", - "INT_FEEDTHRU_2_WW4END2" - ], - [ - "CFG_CENTER_EL1BEG0_17", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_ER1BEG1_17", - "INT_FEEDTHRU_2_ER1BEG1" - ], - [ - "CFG_CENTER_WR1END2_17", - "INT_FEEDTHRU_2_WR1END2" - ], - [ - "CFG_CENTER_EE4A2_17", - "INT_FEEDTHRU_2_EE4A2" - ], - [ - "CFG_CENTER_SW2A0_17", - "INT_FEEDTHRU_2_SW2A0" - ], - [ - "CFG_CENTER_WW4A2_17", - "INT_FEEDTHRU_2_WW4A2" - ], - [ - "CFG_CENTER_WW4END0_17", - "INT_FEEDTHRU_2_WW4END0" - ], - [ - "CFG_CENTER_EE2A0_17", - "INT_FEEDTHRU_2_EE2A0" - ], - [ - "CFG_CENTER_WW2END2_17", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_NE4C1_17", - "INT_FEEDTHRU_2_NE4C1" - ], - [ - "CFG_CENTER_WL1END2_17", - "INT_FEEDTHRU_2_WL1END2" - ], - [ - "CFG_CENTER_NW4END3_17", - "INT_FEEDTHRU_2_NW4END3" + "CFG_CENTER_EE2A2_17", + "INT_FEEDTHRU_2_EE2A2" ], [ "CFG_CENTER_EE2A3_17", "INT_FEEDTHRU_2_EE2A3" ], + [ + "CFG_CENTER_EE2BEG0_17", + "INT_FEEDTHRU_2_EE2BEG0" + ], + [ + "CFG_CENTER_EE2BEG1_17", + "INT_FEEDTHRU_2_EE2BEG1" + ], + [ + "CFG_CENTER_EE2BEG2_17", + "INT_FEEDTHRU_2_EE2BEG2" + ], + [ + "CFG_CENTER_EE2BEG3_17", + "INT_FEEDTHRU_2_EE2BEG3" + ], + [ + "CFG_CENTER_EE4A0_17", + "INT_FEEDTHRU_2_EE4A0" + ], + [ + "CFG_CENTER_EE4A1_17", + "INT_FEEDTHRU_2_EE4A1" + ], + [ + "CFG_CENTER_EE4A2_17", + "INT_FEEDTHRU_2_EE4A2" + ], + [ + "CFG_CENTER_EE4A3_17", + "INT_FEEDTHRU_2_EE4A3" + ], [ "CFG_CENTER_EE4B0_17", "INT_FEEDTHRU_2_EE4B0" ], + [ + "CFG_CENTER_EE4B1_17", + "INT_FEEDTHRU_2_EE4B1" + ], + [ + "CFG_CENTER_EE4B2_17", + "INT_FEEDTHRU_2_EE4B2" + ], + [ + "CFG_CENTER_EE4B3_17", + "INT_FEEDTHRU_2_EE4B3" + ], + [ + "CFG_CENTER_EE4BEG0_17", + "INT_FEEDTHRU_2_EE4BEG0" + ], + [ + "CFG_CENTER_EE4BEG1_17", + "INT_FEEDTHRU_2_EE4BEG1" + ], + [ + "CFG_CENTER_EE4BEG2_17", + "INT_FEEDTHRU_2_EE4BEG2" + ], + [ + "CFG_CENTER_EE4BEG3_17", + "INT_FEEDTHRU_2_EE4BEG3" + ], + [ + "CFG_CENTER_EE4C0_17", + "INT_FEEDTHRU_2_EE4C0" + ], + [ + "CFG_CENTER_EE4C1_17", + "INT_FEEDTHRU_2_EE4C1" + ], + [ + "CFG_CENTER_EE4C2_17", + "INT_FEEDTHRU_2_EE4C2" + ], + [ + "CFG_CENTER_EE4C3_17", + "INT_FEEDTHRU_2_EE4C3" + ], + [ + "CFG_CENTER_EL1BEG0_17", + "INT_FEEDTHRU_2_EL1BEG0" + ], + [ + "CFG_CENTER_EL1BEG1_17", + "INT_FEEDTHRU_2_EL1BEG1" + ], + [ + "CFG_CENTER_EL1BEG2_17", + "INT_FEEDTHRU_2_EL1BEG2" + ], + [ + "CFG_CENTER_EL1BEG3_17", + "INT_FEEDTHRU_2_EL1BEG3" + ], + [ + "CFG_CENTER_ER1BEG0_17", + "INT_FEEDTHRU_2_ER1BEG0" + ], + [ + "CFG_CENTER_ER1BEG1_17", + "INT_FEEDTHRU_2_ER1BEG1" + ], + [ + "CFG_CENTER_ER1BEG2_17", + "INT_FEEDTHRU_2_ER1BEG2" + ], + [ + "CFG_CENTER_ER1BEG3_17", + "INT_FEEDTHRU_2_ER1BEG3" + ], + [ + "CFG_CENTER_LH1_17", + "INT_FEEDTHRU_2_LH1" + ], + [ + "CFG_CENTER_LH2_17", + "INT_FEEDTHRU_2_LH2" + ], + [ + "CFG_CENTER_LH3_17", + "INT_FEEDTHRU_2_LH3" + ], + [ + "CFG_CENTER_LH4_17", + "INT_FEEDTHRU_2_LH4" + ], + [ + "CFG_CENTER_LH5_17", + "INT_FEEDTHRU_2_LH5" + ], + [ + "CFG_CENTER_LH6_17", + "INT_FEEDTHRU_2_LH6" + ], + [ + "CFG_CENTER_LH7_17", + "INT_FEEDTHRU_2_LH7" + ], + [ + "CFG_CENTER_LH8_17", + "INT_FEEDTHRU_2_LH8" + ], + [ + "CFG_CENTER_LH9_17", + "INT_FEEDTHRU_2_LH9" + ], + [ + "CFG_CENTER_LH10_17", + "INT_FEEDTHRU_2_LH10" + ], + [ + "CFG_CENTER_LH11_17", + "INT_FEEDTHRU_2_LH11" + ], + [ + "CFG_CENTER_LH12_17", + "INT_FEEDTHRU_2_LH12" + ], + [ + "CFG_CENTER_NE2A0_17", + "INT_FEEDTHRU_2_NE2A0" + ], + [ + "CFG_CENTER_NE2A1_17", + "INT_FEEDTHRU_2_NE2A1" + ], + [ + "CFG_CENTER_NE2A2_17", + "INT_FEEDTHRU_2_NE2A2" + ], + [ + "CFG_CENTER_NE2A3_17", + "INT_FEEDTHRU_2_NE2A3" + ], [ "CFG_CENTER_NE4BEG0_17", "INT_FEEDTHRU_2_NE4BEG0" ], [ - "CFG_CENTER_WW4A1_17", - "INT_FEEDTHRU_2_WW4A1" + "CFG_CENTER_NE4BEG1_17", + "INT_FEEDTHRU_2_NE4BEG1" ], [ - "CFG_CENTER_SW2A3_17", - "INT_FEEDTHRU_2_SW2A3" + "CFG_CENTER_NE4BEG2_17", + "INT_FEEDTHRU_2_NE4BEG2" + ], + [ + "CFG_CENTER_NE4BEG3_17", + "INT_FEEDTHRU_2_NE4BEG3" + ], + [ + "CFG_CENTER_NE4C0_17", + "INT_FEEDTHRU_2_NE4C0" + ], + [ + "CFG_CENTER_NE4C1_17", + "INT_FEEDTHRU_2_NE4C1" + ], + [ + "CFG_CENTER_NE4C2_17", + "INT_FEEDTHRU_2_NE4C2" + ], + [ + "CFG_CENTER_NE4C3_17", + "INT_FEEDTHRU_2_NE4C3" + ], + [ + "CFG_CENTER_NW2A0_17", + "INT_FEEDTHRU_2_NW2A0" + ], + [ + "CFG_CENTER_NW2A1_17", + "INT_FEEDTHRU_2_NW2A1" + ], + [ + "CFG_CENTER_NW2A2_17", + "INT_FEEDTHRU_2_NW2A2" + ], + [ + "CFG_CENTER_NW2A3_17", + "INT_FEEDTHRU_2_NW2A3" + ], + [ + "CFG_CENTER_NW4A0_17", + "INT_FEEDTHRU_2_NW4A0" ], [ "CFG_CENTER_NW4A1_17", @@ -37638,288 +35654,330056 @@ "INT_FEEDTHRU_2_NW4A2" ], [ - "CFG_CENTER_WW4C0_17", - "INT_FEEDTHRU_2_WW4C0" - ], - [ - "CFG_CENTER_SW4END0_17", - "INT_FEEDTHRU_2_SW4END0" - ], - [ - "CFG_CENTER_SE4BEG0_17", - "INT_FEEDTHRU_2_SE4BEG0" - ], - [ - "CFG_CENTER_LH5_17", - "INT_FEEDTHRU_2_LH5" - ], - [ - "CFG_CENTER_EE4A3_17", - "INT_FEEDTHRU_2_EE4A3" - ], - [ - "CFG_CENTER_WW4B1_17", - "INT_FEEDTHRU_2_WW4B1" + "CFG_CENTER_NW4A3_17", + "INT_FEEDTHRU_2_NW4A3" ], [ "CFG_CENTER_NW4END0_17", "INT_FEEDTHRU_2_NW4END0" ], - [ - "CFG_CENTER_EE4B3_17", - "INT_FEEDTHRU_2_EE4B3" - ], - [ - "CFG_CENTER_NE2A0_17", - "INT_FEEDTHRU_2_NE2A0" - ], - [ - "CFG_CENTER_WW2A3_17", - "INT_FEEDTHRU_2_WW2A3" - ], - [ - "CFG_CENTER_LH10_17", - "INT_FEEDTHRU_2_LH10" - ], - [ - "CFG_CENTER_WW4B2_17", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_LH11_17", - "INT_FEEDTHRU_2_LH11" - ], [ "CFG_CENTER_NW4END1_17", "INT_FEEDTHRU_2_NW4END1" ], - [ - "CFG_CENTER_EE4BEG1_17", - "INT_FEEDTHRU_2_EE4BEG1" - ], - [ - "CFG_CENTER_WW4A0_17", - "INT_FEEDTHRU_2_WW4A0" - ], - [ - "CFG_CENTER_WW2END0_17", - "INT_FEEDTHRU_2_WW2END0" - ], - [ - "CFG_CENTER_EE4C1_17", - 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"CLK_BUFG_REBUF_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CLK_BUFG_REBUF_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CLK_BUFG_REBUF_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CLK_BUFG_REBUF_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CLK_BUFG_REBUF_NE4C0_0", + "VBRK_NE4C0" + ], + [ + "CLK_BUFG_REBUF_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CLK_BUFG_REBUF_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CLK_BUFG_REBUF_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CLK_BUFG_REBUF_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CLK_BUFG_REBUF_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CLK_BUFG_REBUF_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CLK_BUFG_REBUF_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CLK_BUFG_REBUF_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CLK_BUFG_REBUF_NW4A1_0", + "VBRK_NW4A1" + ], + [ + "CLK_BUFG_REBUF_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CLK_BUFG_REBUF_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CLK_BUFG_REBUF_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CLK_BUFG_REBUF_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CLK_BUFG_REBUF_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CLK_BUFG_REBUF_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CLK_BUFG_REBUF_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CLK_BUFG_REBUF_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CLK_BUFG_REBUF_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CLK_BUFG_REBUF_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CLK_BUFG_REBUF_SE4BEG0_0", + "VBRK_SE4BEG0" + ], + [ + "CLK_BUFG_REBUF_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CLK_BUFG_REBUF_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CLK_BUFG_REBUF_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CLK_BUFG_REBUF_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CLK_BUFG_REBUF_SE4C1_0", + "VBRK_SE4C1" + ], + [ + "CLK_BUFG_REBUF_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CLK_BUFG_REBUF_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CLK_BUFG_REBUF_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CLK_BUFG_REBUF_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CLK_BUFG_REBUF_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CLK_BUFG_REBUF_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CLK_BUFG_REBUF_SW4A0_0", + "VBRK_SW4A0" + ], + [ + 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"CLK_BUFG_REBUF_WW2A3_0", + "VBRK_WW2A3" + ], + [ + "CLK_BUFG_REBUF_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CLK_BUFG_REBUF_WW2END1_0", + "VBRK_WW2END1" + ], + [ + "CLK_BUFG_REBUF_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CLK_BUFG_REBUF_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CLK_BUFG_REBUF_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CLK_BUFG_REBUF_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CLK_BUFG_REBUF_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CLK_BUFG_REBUF_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CLK_BUFG_REBUF_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CLK_BUFG_REBUF_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CLK_BUFG_REBUF_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CLK_BUFG_REBUF_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CLK_BUFG_REBUF_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CLK_BUFG_REBUF_WW4C1_0", + "VBRK_WW4C1" + ], + [ + "CLK_BUFG_REBUF_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CLK_BUFG_REBUF_WW4C3_0", + "VBRK_WW4C3" + ], + [ + "CLK_BUFG_REBUF_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CLK_BUFG_REBUF_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CLK_BUFG_REBUF_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CLK_BUFG_REBUF_WW4END3_0", + "VBRK_WW4END3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -4 + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "CLK_FEED" + ], + "wire_pairs": [ + [ + "CLK_BUFG_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_BUFG_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_BUFG_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_BUFG_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_BUFG_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "CLK_BUFG_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_BUFG_CK_GCLK6", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_BUFG_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_BUFG_CK_GCLK8", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_BUFG_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_BUFG_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_BUFG_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_BUFG_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_BUFG_CK_GCLK13", + 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"CLK_BUFG_TOP_R_CK_MUXED27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_BUFG_TOP_R_CK_MUXED31", + "CLK_FEED_R_CK_BUFG_CASC31" + ] + ] + }, + { + "grid_deltas": [ + -1, + -3 + ], + "tile_types": [ + "CLK_BUFG_TOP_R", + "INT_INTERFACE_R" + ], + "wire_pairs": [ + [ + "CLK_BUFG_IMUX0_3", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_BUFG_IMUX1_3", + "INT_INTERFACE_IMUX1" + ], + [ + "CLK_BUFG_IMUX2_3", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_BUFG_IMUX3_3", + "INT_INTERFACE_IMUX3" + ], + [ + "CLK_BUFG_IMUX4_3", + "INT_INTERFACE_IMUX4" + ], + [ + "CLK_BUFG_IMUX5_3", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_BUFG_IMUX6_3", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_BUFG_IMUX7_3", + "INT_INTERFACE_IMUX7" + ], + [ + "CLK_BUFG_IMUX8_3", + "INT_INTERFACE_IMUX8" + ], + [ + "CLK_BUFG_IMUX9_3", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_BUFG_IMUX10_3", + "INT_INTERFACE_IMUX10" + ], + [ + "CLK_BUFG_IMUX11_3", + "INT_INTERFACE_IMUX11" + ], + [ + "CLK_BUFG_IMUX12_3", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_BUFG_IMUX13_3", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_BUFG_IMUX14_3", + "INT_INTERFACE_IMUX14" + ], + [ + "CLK_BUFG_IMUX15_3", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_BUFG_IMUX16_3", + "INT_INTERFACE_IMUX16" + ], + [ + "CLK_BUFG_IMUX17_3", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_BUFG_IMUX18_3", + "INT_INTERFACE_IMUX18" + ], + [ + "CLK_BUFG_IMUX19_3", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_BUFG_IMUX20_3", + "INT_INTERFACE_IMUX20" + ], + [ + "CLK_BUFG_IMUX21_3", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_BUFG_IMUX22_3", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_BUFG_IMUX23_3", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_BUFG_IMUX24_3", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_BUFG_IMUX25_3", + "INT_INTERFACE_IMUX25" + ], + [ + "CLK_BUFG_IMUX26_3", + "INT_INTERFACE_IMUX26" + ], + [ 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"HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_BRAM", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_BRAM_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_BRAM_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_BRAM_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_BRAM_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_BRAM_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_BRAM_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_BRAM_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_BRAM_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_BRAM_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_BRAM_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_BRAM_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_BRAM_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_BRAM_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_BRAM_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_CLB" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CLB_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CLB_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CLB_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CLB_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CLB_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CLB_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CLB_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CLB_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CLB_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CLB_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CLB_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CLB_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CLB_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CLB_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CLB_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CLB_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CLB_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CLB_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CLB_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CLB_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CLB_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CLB_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CLB_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CLB_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CLB_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CLB_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CLB_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CLB_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CLB_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CLB_CK_IN13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_CLB_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_CLB_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_CLB_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_CLB_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_DSP_R" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_DSP_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_DSP_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_DSP_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_DSP_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_DSP_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_DSP_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_DSP_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_DSP_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_DSP_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_DSP_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_DSP_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_DSP_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_DSP_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_DSP_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_DSP_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_DSP_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_DSP_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_DSP_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_DSP_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_DSP_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_DSP_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_DSP_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_DSP_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_DSP_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_DSP_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_DSP_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_DSP_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_DSP_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_DSP_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_DSP_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_L_BOT_UTURN" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_R" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" ] ] }, @@ -37934,92 +365718,88020 @@ ], "wire_pairs": [ [ - "HCLK_CLB_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CLB_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_CK_IN10" + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" ], [ "HCLK_CLB_CK_BUFHCLK1", "HCLK_CK_BUFHCLK1" ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_CK_IN11" - ], [ "HCLK_CLB_CK_BUFHCLK2", "HCLK_CK_BUFHCLK2" ], - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_CK_IN12" - ], [ "HCLK_CLB_CK_BUFHCLK3", "HCLK_CK_BUFHCLK3" ], [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" ], [ "HCLK_CLB_CK_BUFHCLK7", "HCLK_CK_BUFHCLK7" ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], [ "HCLK_CLB_CK_IN4", "HCLK_CK_IN4" ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], [ "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" ], [ "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CLB", + "HCLK_VFRAME" + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_VFRAME_CK_IN8" + ], + [ + "HCLK_CLB_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_VFRAME_CK_IN12" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_FIFO_L" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CMT", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_CLK_0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_MUX_CLK_1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_MUX_CLK_2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_MUX_CLK_3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_MUX_CLK_4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_MUX_CLK_5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_MUX_CLK_6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_MUX_CLK_7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_MUX_CLK_8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_MUX_CLK_9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_MUX_CLK_10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_MUX_CLK_11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_MUX_CLK_12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_MUX_CLK_13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_FIFO_L" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_FIFO_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_FIFO_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_CMT_L", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_DSP_L", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK10" + ], + [ + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_BUFHCLK11" + ], + [ + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_BUFRCLK0" + ], + [ + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_INT_INTERFACE_CK_BUFRCLK1" + ], + [ + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_CK_BUFRCLK2" + ], + [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_INT_INTERFACE_CK_BUFRCLK3" + ], + [ + "HCLK_DSP_CK_IN0", + "HCLK_INT_INTERFACE_CK_IN0" + ], + [ + "HCLK_DSP_CK_IN1", + "HCLK_INT_INTERFACE_CK_IN1" + ], + [ + "HCLK_DSP_CK_IN2", + "HCLK_INT_INTERFACE_CK_IN2" + ], + [ + "HCLK_DSP_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN3" + ], + [ + "HCLK_DSP_CK_IN4", + "HCLK_INT_INTERFACE_CK_IN4" + ], + [ + "HCLK_DSP_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN5" + ], + [ + "HCLK_DSP_CK_IN6", + "HCLK_INT_INTERFACE_CK_IN6" + ], + [ + "HCLK_DSP_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN7" + ], + [ + "HCLK_DSP_CK_IN8", + "HCLK_INT_INTERFACE_CK_IN8" + ], + [ + "HCLK_DSP_CK_IN9", + "HCLK_INT_INTERFACE_CK_IN9" + ], + [ + "HCLK_DSP_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN10" + ], + [ + "HCLK_DSP_CK_IN11", + "HCLK_INT_INTERFACE_CK_IN11" + ], + [ + "HCLK_DSP_CK_IN12", + "HCLK_INT_INTERFACE_CK_IN12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_INT_INTERFACE_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_DSP_R", + "HCLK_VBRK" + ], + "wire_pairs": [ + [ + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ], + [ + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_DSP_CK_BUFHCLK10", + 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"HCLK_DSP_CK_IN12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_DSP_CK_IN13", + "HCLK_VBRK_MUX_CLK13" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_FEEDTHRU_1", + "HCLK_FEEDTHRU_1" + ], + "wire_pairs": [ + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_1_CK_BUFHCLK0" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_1_CK_BUFHCLK1" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_1_CK_BUFHCLK2" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_1_CK_BUFHCLK3" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_1_CK_BUFHCLK4" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_1_CK_BUFHCLK5" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_1_CK_BUFHCLK6" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_1_CK_BUFHCLK7" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_1_CK_BUFHCLK8" + ], + [ + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_1_CK_BUFHCLK9" + ], + [ + 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"HCLK_INT_INTERFACE_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_FIFO_L", + "HCLK_INT_INTERFACE" + ], + "wire_pairs": [ + [ + "HCLK_FIFO_CCIO0", + "HCLK_INT_INTERFACE_CCIO0" + ], + [ + "HCLK_FIFO_CCIO1", + "HCLK_INT_INTERFACE_CCIO1" + ], + [ + "HCLK_FIFO_CCIO2", + "HCLK_INT_INTERFACE_CCIO2" + ], + [ + "HCLK_FIFO_CCIO3", + "HCLK_INT_INTERFACE_CCIO3" + ], + [ + "HCLK_FIFO_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK0" + ], + [ + "HCLK_FIFO_CK_BUFHCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK1" + ], + [ + "HCLK_FIFO_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2" + ], + [ + "HCLK_FIFO_CK_BUFHCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK3" + ], + [ + "HCLK_FIFO_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_BUFHCLK4" + ], + [ + "HCLK_FIFO_CK_BUFHCLK5", + "HCLK_INT_INTERFACE_CK_BUFHCLK5" + ], + [ + "HCLK_FIFO_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK6" + ], + [ + "HCLK_FIFO_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CK_BUFHCLK7" + ], + [ + "HCLK_FIFO_CK_BUFHCLK8", + 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"HCLK_INT_INTERFACE", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CCIO0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_INT_INTERFACE_CCIO2", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_INT_INTERFACE", + "HCLK_VFRAME" + ], + "wire_pairs": [ + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_VFRAME_CK_BUFHCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_VFRAME_CK_BUFHCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK6" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFRCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_VFRAME_CK_IN1" + ], + [ + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_VFRAME_CK_IN3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN4", + "HCLK_VFRAME_CK_IN4" + ], + [ + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_VFRAME_CK_IN6" + ], + [ + "HCLK_INT_INTERFACE_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "HCLK_INT_INTERFACE_CK_IN8", + "HCLK_VFRAME_CK_IN8" + ], + [ + "HCLK_INT_INTERFACE_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "HCLK_INT_INTERFACE_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ], + [ + "HCLK_INT_INTERFACE_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "HCLK_INT_INTERFACE_CK_IN12", + "HCLK_VFRAME_CK_IN12" + ], + [ + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_IOB", + "HCLK_IOI" + ], + "wire_pairs": [ + [ + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOI_CK_BUFHCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOI_CK_BUFHCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK2", + "HCLK_IOI_CK_BUFHCLK2" + ], + [ + "HCLK_IOB_CK_BUFHCLK3", + "HCLK_IOI_CK_BUFHCLK3" + ], + [ + "HCLK_IOB_CK_BUFHCLK4", + "HCLK_IOI_CK_BUFHCLK4" + ], + [ + "HCLK_IOB_CK_BUFHCLK5", + "HCLK_IOI_CK_BUFHCLK5" + ], + [ + "HCLK_IOB_CK_BUFHCLK6", + "HCLK_IOI_CK_BUFHCLK6" + ], + [ + "HCLK_IOB_CK_BUFHCLK7", + "HCLK_IOI_CK_BUFHCLK7" + ], + [ + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOI_CK_BUFHCLK8" + ], + [ + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOI_CK_BUFHCLK9" + ], + [ + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOI_CK_BUFHCLK10" + ], + [ + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOI_CK_BUFHCLK11" + ], + [ + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOI_CK_BUFRCLK0" + ], + [ + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFRCLK1" + ], + [ + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOI_CK_BUFRCLK2" + ], + [ + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOI_CK_BUFRCLK3" + ], + [ + "HCLK_IOB_PERFCLK0", + "HCLK_IOI_IOCLK_PLL0" + ], + [ + "HCLK_IOB_PERFCLK1", + "HCLK_IOI_IOCLK_PLL1" + ], + [ + "HCLK_IOB_PERFCLK2", + "HCLK_IOI_IOCLK_PLL2" + ], + [ + "HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_IOB", + "HCLK_IOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOI_CK_BUFHCLK0" + ], + [ + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOI_CK_BUFHCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK2", + "HCLK_IOI_CK_BUFHCLK2" + ], + [ + "HCLK_IOB_CK_BUFHCLK3", + "HCLK_IOI_CK_BUFHCLK3" + ], + [ + "HCLK_IOB_CK_BUFHCLK4", + "HCLK_IOI_CK_BUFHCLK4" + ], + [ + "HCLK_IOB_CK_BUFHCLK5", + "HCLK_IOI_CK_BUFHCLK5" + ], + [ + "HCLK_IOB_CK_BUFHCLK6", + "HCLK_IOI_CK_BUFHCLK6" + ], + [ + "HCLK_IOB_CK_BUFHCLK7", + "HCLK_IOI_CK_BUFHCLK7" + ], + [ + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOI_CK_BUFHCLK8" + ], + [ + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOI_CK_BUFHCLK9" + ], + [ + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOI_CK_BUFHCLK10" + ], + [ + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOI_CK_BUFHCLK11" + ], + [ + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOI_CK_BUFRCLK0" + ], + [ + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFRCLK1" + ], + [ + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOI_CK_BUFRCLK2" + ], + [ + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOI_CK_BUFRCLK3" + ], + [ + "HCLK_IOB_PERFCLK0", + "HCLK_IOI_IOCLK_PLL0" + ], + [ + "HCLK_IOB_PERFCLK1", + "HCLK_IOI_IOCLK_PLL1" + ], + [ + "HCLK_IOB_PERFCLK2", + "HCLK_IOI_IOCLK_PLL2" + ], + [ + "HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ] + ] + }, + { + "grid_deltas": [ + -1, + 0 + ], + "tile_types": [ + "HCLK_IOI", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "HCLK_IOI", + "RIOI" + ], + "wire_pairs": [ + [ + "HCLK_IOI_DCI_DCIDONE", + "IOI_DCI_DCIDONE" + ], + [ + "HCLK_IOI_DCI_TSTHLN", + "IOI_DCI_TSTHLN" + ], + [ + "HCLK_IOI_DCI_TSTHLP", + "IOI_DCI_TSTHLP" + ], + [ + "HCLK_IOI_DCI_TSTRST", + "IOI_DCI_TSTRST0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "RIOI_I2GCLK_TOP1" + ], + [ + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" + ], + [ + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" + ], + [ + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" + ], + [ + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" + ], + [ + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" + ], + [ + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" + ], + [ + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" + ], + [ + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ] + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "tile_types": [ + "HCLK_IOI", + "RIOI" + ], + "wire_pairs": [ + [ + "HCLK_IOI_DCI_TSTCLK", + "IOI_DCI_TSTCLK" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "RIOI_I2GCLK_BOT1" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "RIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ], + [ + "HCLK_IOI_IDELAYCTRL_RDY", + "IOI_IDELAYCTRL_RDY" + ], + [ + "HCLK_IOI_INT_DCI_EN", + "IOI_INT_DCI_EN" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX2", + "IOI_IMUX_RC2" + ], + [ + "HCLK_IOI_RCLK_IMUX3", + "IOI_IMUX_RC3" + ], + [ + "HCLK_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2" + ], + [ + "HCLK_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3" + ], + [ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_IOI3", + "HCLK_TERM" + ], + "wire_pairs": [ + [ + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_TERM_CK_BUFHCLK0" + ], + [ + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_TERM_CK_BUFHCLK1" + ], + [ + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_TERM_CK_BUFHCLK2" + ], + [ + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK3" + ], + [ + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_TERM_CK_BUFHCLK4" + ], + [ + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_TERM_CK_BUFHCLK5" + ], + [ + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK6" + ], + [ + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_TERM_CK_BUFHCLK7" + ], + [ + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_TERM_CK_BUFHCLK8" + ], + [ + "HCLK_IOI_CK_BUFHCLK9", + "HCLK_TERM_CK_BUFHCLK9" + ], + [ + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFHCLK10" + ], + [ + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK11" + ], + [ + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_TERM_CK_BUFRCLK0" + ], + [ + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_TERM_CK_BUFRCLK1" + ], + [ + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_TERM_CK_BUFRCLK2" + ], + [ + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_TERM_CK_BUFRCLK3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_TERM_CCIO2" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_TERM_CCIO3" + ], + [ + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_TERM_CCIO0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_TERM_CCIO1" + ], + [ + "HCLK_IOI_IOCLK_PLL0", + "HCLK_TERM_PERFCLK0" + ], + [ + "HCLK_IOI_IOCLK_PLL1", + "HCLK_TERM_PERFCLK1" + ], + [ + "HCLK_IOI_IOCLK_PLL2", + "HCLK_TERM_PERFCLK2" + ], + [ + "HCLK_IOI_IOCLK_PLL3", + "HCLK_TERM_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "HCLK_IOI3", + "LIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_TOP0", + "LIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_I2IOCLK_TOP1", + "LIOI_I2GCLK_TOP1" + ], + [ + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IDELAYCTRL_DNPULSEOUT" + ], + [ + "HCLK_IOI_IDELAYCTRL_RST", + "IOI_IDELAYCTRL_RST" + ], + [ + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_IDELAYCTRL_UPPULSEOUT" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_TOP5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX0", + "IOI_IMUX_RC0" + ], + [ + "HCLK_IOI_RCLK_IMUX1", + "IOI_IMUX_RC1" + ], + [ + "HCLK_RCLK_DIV_CE0", + "IOI_RCLK_DIV_CE0" + ], + [ + "HCLK_RCLK_DIV_CE1", + "IOI_RCLK_DIV_CE1" + ], + [ + "HCLK_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0" + ], + [ + "HCLK_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1" + ] + ] + }, + { + "grid_deltas": [ + 0, + 2 + ], + "tile_types": [ + "HCLK_IOI3", + "LIOI3" + ], + "wire_pairs": [ + [ + "HCLK_IOI_I2IOCLK_BOT0", + "LIOI_I2GCLK_BOT1" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "LIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ], + [ + "HCLK_IOI_IDELAYCTRL_RDY", + "IOI_IDELAYCTRL_RDY" + ], + [ + "HCLK_IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT1", + "IOI_LEAF_GCLK1" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT2", + "IOI_LEAF_GCLK2" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT4", + "IOI_LEAF_GCLK4" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_IOI_RCLK2IO3", + "IOI_RCLK_FORIO3" + ], + [ + "HCLK_IOI_RCLK_IMUX2", + "IOI_IMUX_RC2" + ], + [ + "HCLK_IOI_RCLK_IMUX3", + "IOI_IMUX_RC3" + ], + [ + "HCLK_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2" + ], + [ + "HCLK_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3" + ], + [ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ] + ] + }, + { + "grid_deltas": [ + 1, + 0 + ], + "tile_types": [ + "HCLK_L", + "HCLK_R" + ], + "wire_pairs": [ + [ + "HCLK_CCIO0", + "HCLK_CCIO0" + ], + [ + "HCLK_CCIO1", + "HCLK_CCIO1" + ], + [ + "HCLK_CCIO2", + "HCLK_CCIO2" + ], + [ + "HCLK_CCIO3", + "HCLK_CCIO3" + ], + [ + "HCLK_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ], + [ + "HCLK_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CK_INOUT_L0", + "HCLK_CK_OUTIN_R4" + ], + [ + "HCLK_CK_INOUT_L1", + "HCLK_CK_OUTIN_R5" + ], + [ + "HCLK_CK_INOUT_L2", + "HCLK_CK_OUTIN_R6" + ], + [ + "HCLK_CK_INOUT_L3", + "HCLK_CK_OUTIN_R7" + ], + [ + "HCLK_CK_INOUT_L4", + "HCLK_CK_OUTIN_R0" + ], + [ + "HCLK_CK_INOUT_L5", + "HCLK_CK_OUTIN_R1" + ], + [ + "HCLK_CK_INOUT_L6", + "HCLK_CK_OUTIN_R2" + ], + [ + "HCLK_CK_INOUT_L7", + "HCLK_CK_OUTIN_R3" + ], + [ + "HCLK_CK_OUTIN_L0", + "HCLK_CK_INOUT_R0" + ], + [ + "HCLK_CK_OUTIN_L1", + "HCLK_CK_INOUT_R1" + ], + [ + "HCLK_CK_OUTIN_L2", + "HCLK_CK_INOUT_R2" + ], + [ + "HCLK_CK_OUTIN_L3", + "HCLK_CK_INOUT_R3" + ], + [ + "HCLK_CK_OUTIN_L4", + "HCLK_CK_INOUT_R4" + ], + [ + "HCLK_CK_OUTIN_L5", + "HCLK_CK_INOUT_R5" + ], + [ + "HCLK_CK_OUTIN_L6", + "HCLK_CK_INOUT_R6" + ], + [ + "HCLK_CK_OUTIN_L7", + "HCLK_CK_INOUT_R7" + ], + [ + "HCLK_INT_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_INT_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_INT_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_INT_PERFCLK3", + "HCLK_INT_PERFCLK3" + ] + ] + }, + { + "grid_deltas": [ + 0, + -1 + ], + "tile_types": [ + "HCLK_L", + "INT_L" + ], + "wire_pairs": [ + [ + "HCLK_BYP_BOUNCE2", + "BYP_BOUNCE_N3_2" + ], + [ + "HCLK_BYP_BOUNCE3", + "BYP_BOUNCE_N3_3" + ], + [ + "HCLK_BYP_BOUNCE6", + "BYP_BOUNCE_N3_6" + ], + [ + "HCLK_BYP_BOUNCE7", + "BYP_BOUNCE_N3_7" + ], + [ + "HCLK_EL1BEG3", + "EL1BEG_N3" + ], + [ + "HCLK_EL1END_S3_0", + "EL1END0" + ], + [ + "HCLK_ER1BEG_S0", + "ER1BEG0" + ], + [ + "HCLK_ER1END3", + "ER1END_N3_3" + ], + [ + "HCLK_FAN_BOUNCE_S3_0", + "FAN_BOUNCE0" + ], + [ + "HCLK_FAN_BOUNCE_S3_2", + "FAN_BOUNCE2" + ], + [ + "HCLK_FAN_BOUNCE_S3_4", + "FAN_BOUNCE4" + ], + [ + "HCLK_FAN_BOUNCE_S3_6", + "FAN_BOUNCE6" + ], + [ + "HCLK_LEAF_CLK_B_TOPL0", + "GCLK_L_B6" + ], + [ + "HCLK_LEAF_CLK_B_TOPL1", + "GCLK_L_B7" + ], + [ + "HCLK_LEAF_CLK_B_TOPL2", + "GCLK_L_B8" + ], + [ + "HCLK_LEAF_CLK_B_TOPL3", + "GCLK_L_B9" + ], + [ + "HCLK_LEAF_CLK_B_TOPL4", + "GCLK_L_B10" + ], + [ + "HCLK_LEAF_CLK_B_TOPL5", + "GCLK_L_B11" + ], + [ + "HCLK_LV0", + "LV_L1" + ], + [ + "HCLK_LV1", + "LV_L2" + ], + [ + "HCLK_LV2", + "LV_L3" + ], + [ + "HCLK_LV3", + "LV_L4" + ], + [ + "HCLK_LV4", + "LV_L5" + ], + [ + "HCLK_LV5", + "LV_L6" + ], + [ + "HCLK_LV6", + "LV_L7" + ], + [ + "HCLK_LV7", + "LV_L8" + ], + [ + "HCLK_LV8", + "LV_L9" + ], + [ + "HCLK_LV9", + "LV_L10" + ], + [ + "HCLK_LV10", + "LV_L11" + ], + [ + "HCLK_LV11", + "LV_L12" + ], + [ + "HCLK_LV12", + "LV_L13" + ], + [ + "HCLK_LV13", + "LV_L14" + ], + [ + "HCLK_LV14", + "LV_L15" + ], + [ + "HCLK_LV15", + "LV_L16" + ], + [ + "HCLK_LV16", + "LV_L17" + ], + [ + "HCLK_LV17", + "LV_L18" + ], + [ + "HCLK_LVB1", + "LVB_L1" + ], + [ + "HCLK_LVB2", + "LVB_L2" + ], + [ + "HCLK_LVB3", + "LVB_L3" + ], + [ + "HCLK_LVB4", + "LVB_L4" + ], + [ + "HCLK_LVB5", + "LVB_L5" + ], + [ + "HCLK_LVB6", + "LVB_L6" + ], + [ + "HCLK_LVB7", + "LVB_L7" + ], + [ + "HCLK_LVB8", + "LVB_L8" + ], + [ + "HCLK_LVB9", + "LVB_L9" + ], + [ + "HCLK_LVB10", + "LVB_L10" + ], + [ + "HCLK_LVB11", + "LVB_L11" + ], + [ + "HCLK_LVB12", + "LVB_L12" + ], + [ + "HCLK_NE2BEG0", + "NE2A0" + ], + [ + "HCLK_NE2BEG1", + "NE2A1" + ], + [ + "HCLK_NE2BEG2", + "NE2A2" + ], + [ + "HCLK_NE2BEG3", + "NE2A3" + ], + [ + "HCLK_NE2END_S3_0", + "NE2END0" + ], + [ + "HCLK_NE6A0", + "NE6B0" + ], + [ + "HCLK_NE6A1", + "NE6B1" + ], + [ + "HCLK_NE6A2", + "NE6B2" + ], + [ + "HCLK_NE6A3", + "NE6B3" + ], + [ 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"NW2A0" + ], + [ + "HCLK_NW2A1", + "NW2A1" + ], + [ + "HCLK_NW2A2", + "NW2A2" + ], + [ + "HCLK_NW2A3", + "NW2A3" + ], + [ + "HCLK_NW2END_S0_0", + "NW2END0" + ], + [ + "HCLK_NW6A0", + "NW6B0" + ], + [ + "HCLK_NW6A1", + "NW6B1" + ], + [ + "HCLK_NW6A2", + "NW6B2" + ], + [ + "HCLK_NW6A3", + "NW6B3" + ], + [ + "HCLK_NW6B0", + "NW6C0" + ], + [ + "HCLK_NW6B1", + "NW6C1" + ], + [ + "HCLK_NW6B2", + "NW6C2" + ], + [ + "HCLK_NW6B3", + "NW6C3" + ], + [ + "HCLK_NW6C0", + "NW6D0" + ], + [ + "HCLK_NW6C1", + "NW6D1" + ], + [ + "HCLK_NW6C2", + "NW6D2" + ], + [ + "HCLK_NW6C3", + "NW6D3" + ], + [ + "HCLK_NW6D0", + "NW6E0" + ], + [ + "HCLK_NW6D1", + "NW6E1" + ], + [ + "HCLK_NW6D2", + "NW6E2" + ], + [ + "HCLK_NW6D3", + "NW6E3" + ], + [ + "HCLK_NW6END_S0_0", + "NW6END0" + ], + [ + "HCLK_SE2A0", + "SE2BEG0" + ], + [ + "HCLK_SE2A1", + "SE2BEG1" + ], + [ + "HCLK_SE2A2", + "SE2BEG2" + ], + [ + "HCLK_SE2A3", + "SE2BEG3" + ], + [ + "HCLK_SE6B0", + "SE6A0" + ], + [ + "HCLK_SE6B1", + "SE6A1" + ], + [ + "HCLK_SE6B2", + "SE6A2" + ], + [ + "HCLK_SE6B3", + "SE6A3" + ], + [ + "HCLK_SE6C0", + "SE6B0" + ], + [ + "HCLK_SE6C1", + "SE6B1" + ], + [ + "HCLK_SE6C2", + "SE6B2" + ], + [ + "HCLK_SE6C3", + "SE6B3" + ], + [ + "HCLK_SE6D0", + "SE6C0" + ], + [ + "HCLK_SE6D1", + "SE6C1" + ], + [ + "HCLK_SE6D2", + "SE6C2" + ], + [ + "HCLK_SE6D3", + "SE6C3" + ], + [ + "HCLK_SE6E0", + "SE6D0" + ], + [ + "HCLK_SE6E1", + "SE6D1" + ], + [ + "HCLK_SE6E2", + "SE6D2" + ], + [ + "HCLK_SE6E3", + "SE6D3" + ], + [ + "HCLK_SL1END0", + "SL1BEG0" + ], + [ + "HCLK_SL1END1", + "SL1BEG1" + ], + [ + "HCLK_SL1END2", + "SL1BEG2" + ], + [ + "HCLK_SL1END3", + "SL1BEG3" + ], + [ + "HCLK_SR1BEG3", + "SR1BEG3" + ], + [ + "HCLK_SR1END1", + "SR1BEG1" + ], + [ + "HCLK_SR1END2", + "SR1BEG2" + ], + [ + "HCLK_SR1END_N3_3", + "SR1END_N3_3" + ], + [ + "HCLK_SS2A0", + "SS2BEG0" + ], + [ + "HCLK_SS2A1", + "SS2BEG1" + ], + [ + "HCLK_SS2A2", + "SS2BEG2" + ], + [ + "HCLK_SS2A3", + "SS2A3" + ], + [ + "HCLK_SS2BEG3", + "SS2BEG3" + ], + [ + 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"PCIE_INT_INTERFACE_IMUX_OUT37" + ], + [ + "PCIE_IMUX38_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT38" + ], + [ + "PCIE_IMUX39_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT39" + ], + [ + "PCIE_IMUX40_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT40" + ], + [ + "PCIE_IMUX41_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT41" + ], + [ + "PCIE_IMUX42_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT42" + ], + [ + "PCIE_IMUX43_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT43" + ], + [ + "PCIE_IMUX44_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT44" + ], + [ + "PCIE_IMUX45_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT45" + ], + [ + "PCIE_IMUX46_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT46" + ], + [ + "PCIE_IMUX47_R_10", + "PCIE_INT_INTERFACE_IMUX_OUT47" + ], + [ + "PCIE_LH1_10", + "INT_INTERFACE_LH1" + ], + [ + "PCIE_LH2_10", + "INT_INTERFACE_LH2" + ], + [ + "PCIE_LH3_10", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_LH4_10", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_LH5_10", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_LH6_10", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_LH7_10", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_LH8_10", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_LH9_10", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_LH10_10", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_LH11_10", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_LH12_10", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_10", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_10", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_10", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_10", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_10", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_10", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_10", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_10", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_10", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_10", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_10", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_10", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_10", + "INT_INTERFACE_LOGIC_OUTS_B12" + ], + [ + "PCIE_LOGIC_OUTS_B13_R_10", + "INT_INTERFACE_LOGIC_OUTS_B13" + ], + [ + "PCIE_LOGIC_OUTS_B14_R_10", + "INT_INTERFACE_LOGIC_OUTS_B14" + ], + [ + "PCIE_LOGIC_OUTS_B15_R_10", + "INT_INTERFACE_LOGIC_OUTS_B15" + ], + [ + "PCIE_LOGIC_OUTS_B16_R_10", + "INT_INTERFACE_LOGIC_OUTS_B16" + ], + [ + "PCIE_LOGIC_OUTS_B17_R_10", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_10", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_10", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_10", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_10", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_10", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_10", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_NE2A0_10", + "INT_INTERFACE_NE2A0" + ], + [ + "PCIE_NE2A1_10", + "INT_INTERFACE_NE2A1" + ], + [ + "PCIE_NE2A2_10", + "INT_INTERFACE_NE2A2" + ], + [ + "PCIE_NE2A3_10", + "INT_INTERFACE_NE2A3" + ], + [ + "PCIE_NE4BEG0_10", + "INT_INTERFACE_NE4BEG0" + ], + [ + "PCIE_NE4BEG1_10", + "INT_INTERFACE_NE4BEG1" + ], + [ + "PCIE_NE4BEG2_10", + "INT_INTERFACE_NE4BEG2" + ], + [ + "PCIE_NE4BEG3_10", + "INT_INTERFACE_NE4BEG3" + ], + [ + "PCIE_NE4C0_10", + "INT_INTERFACE_NE4C0" + ], + [ + "PCIE_NE4C1_10", + "INT_INTERFACE_NE4C1" + ], + [ + "PCIE_NE4C2_10", + "INT_INTERFACE_NE4C2" + ], + [ + "PCIE_NE4C3_10", + "INT_INTERFACE_NE4C3" + ], + [ + "PCIE_NW2A0_10", + "INT_INTERFACE_NW2A0" + ], + [ + "PCIE_NW2A1_10", + "INT_INTERFACE_NW2A1" + ], + [ + "PCIE_NW2A2_10", + "INT_INTERFACE_NW2A2" + ], + [ + "PCIE_NW2A3_10", + "INT_INTERFACE_NW2A3" + ], + [ + "PCIE_NW4A0_10", + "INT_INTERFACE_NW4A0" + ], + [ + "PCIE_NW4A1_10", + "INT_INTERFACE_NW4A1" + ], + [ + "PCIE_NW4A2_10", + "INT_INTERFACE_NW4A2" + ], + [ + "PCIE_NW4A3_10", + "INT_INTERFACE_NW4A3" + ], + [ + "PCIE_NW4END0_10", + "INT_INTERFACE_NW4END0" + ], + [ + "PCIE_NW4END1_10", + "INT_INTERFACE_NW4END1" + ], + [ + "PCIE_NW4END2_10", + "INT_INTERFACE_NW4END2" + ], + [ + "PCIE_NW4END3_10", + "INT_INTERFACE_NW4END3" + ], + [ + "PCIE_SE2A0_10", + "INT_INTERFACE_SE2A0" + ], + [ + "PCIE_SE2A1_10", + "INT_INTERFACE_SE2A1" + ], + [ + "PCIE_SE2A2_10", + "INT_INTERFACE_SE2A2" + ], + [ + "PCIE_SE2A3_10", + "INT_INTERFACE_SE2A3" + ], + [ + "PCIE_SE4BEG0_10", + "INT_INTERFACE_SE4BEG0" + ], + [ + "PCIE_SE4BEG1_10", + "INT_INTERFACE_SE4BEG1" + ], + [ + "PCIE_SE4BEG2_10", + "INT_INTERFACE_SE4BEG2" + ], + [ + "PCIE_SE4BEG3_10", + "INT_INTERFACE_SE4BEG3" + ], + [ + "PCIE_SE4C0_10", + "INT_INTERFACE_SE4C0" + ], + [ + "PCIE_SE4C1_10", + "INT_INTERFACE_SE4C1" + ], + [ + "PCIE_SE4C2_10", + "INT_INTERFACE_SE4C2" + ], + [ + "PCIE_SE4C3_10", + "INT_INTERFACE_SE4C3" + ], + [ + "PCIE_SW2A0_10", + "INT_INTERFACE_SW2A0" + ], + [ + "PCIE_SW2A1_10", + "INT_INTERFACE_SW2A1" + ], + [ + "PCIE_SW2A2_10", + "INT_INTERFACE_SW2A2" + ], + [ + "PCIE_SW2A3_10", + "INT_INTERFACE_SW2A3" + ], + [ + "PCIE_SW4A0_10", + "INT_INTERFACE_SW4A0" + ], + [ + "PCIE_SW4A1_10", + "INT_INTERFACE_SW4A1" + ], + [ + "PCIE_SW4A2_10", + "INT_INTERFACE_SW4A2" + ], + [ + "PCIE_SW4A3_10", + "INT_INTERFACE_SW4A3" + ], + [ + "PCIE_SW4END0_10", + "INT_INTERFACE_SW4END0" + ], + [ + "PCIE_SW4END1_10", + "INT_INTERFACE_SW4END1" + ], + [ + "PCIE_SW4END2_10", + "INT_INTERFACE_SW4END2" + ], + [ + "PCIE_SW4END3_10", + "INT_INTERFACE_SW4END3" + ], + [ + "PCIE_WL1END0_10", + "INT_INTERFACE_WL1END0" + ], + [ + "PCIE_WL1END1_10", + "INT_INTERFACE_WL1END1" + ], + [ + "PCIE_WL1END2_10", + "INT_INTERFACE_WL1END2" + ], + [ + "PCIE_WL1END3_10", + "INT_INTERFACE_WL1END3" + ], + [ + "PCIE_WR1END0_10", + "INT_INTERFACE_WR1END0" + ], + [ + "PCIE_WR1END1_10", + "INT_INTERFACE_WR1END1" + ], + [ + "PCIE_WR1END2_10", + "INT_INTERFACE_WR1END2" + ], + [ + "PCIE_WR1END3_10", + "INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WW2A0_10", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WW2A1_10", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_WW2A2_10", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_WW2A3_10", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_WW2END0_10", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_WW2END1_10", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_WW2END2_10", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_WW2END3_10", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WW4A0_10", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_WW4A1_10", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_WW4A2_10", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_WW4A3_10", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_WW4B0_10", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_WW4B1_10", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WW4B2_10", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WW4B3_10", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW4C0_10", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_WW4C1_10", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WW4C2_10", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_WW4C3_10", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_WW4END0_10", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WW4END1_10", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_WW4END2_10", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WW4END3_10", + "INT_INTERFACE_WW4END3" ] ] }, @@ -38037,4389 +453749,873 @@ "PCIE_BYP0_R_9", "INT_INTERFACE_BYP0" ], - [ - "PCIE_IMUX43_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT43" - ], - [ - "PCIE_IMUX37_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT37" - ], - [ - "PCIE_NE2A2_9", - "INT_INTERFACE_NE2A2" - ], - [ - "PCIE_WW2A2_9", - "INT_INTERFACE_WW2A2" - ], - [ - "PCIE_WR1END2_9", - "INT_INTERFACE_WR1END2" - ], - [ - "PCIE_NE4BEG0_9", - "INT_INTERFACE_NE4BEG0" - ], - [ - "PCIE_LOGIC_OUTS_B5_R_9", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "PCIE_MONITOR_N_9", - "INT_INTERFACE_MONITOR_N" - ], - [ - "PCIE_SW4A0_9", - "INT_INTERFACE_SW4A0" - ], - [ - "PCIE_IMUX28_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT28" - ], - [ - "PCIE_LOGIC_OUTS_B2_R_9", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "PCIE_EL1BEG0_9", - "INT_INTERFACE_EL1BEG0" - ], - [ - "PCIE_EE4BEG1_9", - "INT_INTERFACE_EE4BEG1" - ], - [ - "PCIE_IMUX41_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT41" - ], - [ - "PCIE_IMUX3_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT3" - ], - [ - "PCIE_LOGIC_OUTS_B4_R_9", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "PCIE_IMUX0_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT0" - ], - [ - "PCIE_IMUX31_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT31" - ], - [ - "PCIE_EL1BEG2_9", - "INT_INTERFACE_EL1BEG2" - ], - [ - "PCIE_IMUX15_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT15" - ], - [ - "PCIE_LOGIC_OUTS_B23_R_9", - "INT_INTERFACE_LOGIC_OUTS_B23" - ], - [ - "PCIE_BYP5_R_9", - "INT_INTERFACE_BYP5" - ], - [ - "PCIE_LOGIC_OUTS_B10_R_9", - "INT_INTERFACE_LOGIC_OUTS_B10" - ], - [ - "PCIE_WW4END3_9", - "INT_INTERFACE_WW4END3" - ], - [ - "PCIE_IMUX18_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT18" - ], - [ - "PCIE_NE4C2_9", - "INT_INTERFACE_NE4C2" - ], - [ - "PCIE_NW4END1_9", - "INT_INTERFACE_NW4END1" - ], - [ - "PCIE_EE2A3_9", - "INT_INTERFACE_EE2A3" - ], - [ - "PCIE_WW4C0_9", - "INT_INTERFACE_WW4C0" - ], - [ - "PCIE_NW4A0_9", - "INT_INTERFACE_NW4A0" - ], - [ - "PCIE_EE2BEG2_9", - "INT_INTERFACE_EE2BEG2" - ], - [ - "PCIE_ER1BEG2_9", - "INT_INTERFACE_ER1BEG2" - ], - [ - "PCIE_FAN5_R_9", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_LH7_9", - "INT_INTERFACE_LH7" - ], - [ - "PCIE_NE2A1_9", - "INT_INTERFACE_NE2A1" - ], - [ - "PCIE_WW4C3_9", - "INT_INTERFACE_WW4C3" - ], - [ - "PCIE_LH9_9", - "INT_INTERFACE_LH9" - ], - [ - "PCIE_EE2A2_9", - "INT_INTERFACE_EE2A2" - ], - [ - "PCIE_WW4B2_9", - "INT_INTERFACE_WW4B2" - ], - [ - "PCIE_IMUX14_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT14" - ], - [ - "PCIE_BYP4_R_9", - "INT_INTERFACE_BYP4" - ], - [ - "PCIE_NW4A3_9", - "INT_INTERFACE_NW4A3" - ], - [ - "PCIE_IMUX47_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT47" - ], - [ - "PCIE_MONITOR_P_9", - "INT_INTERFACE_MONITOR_P" - ], - [ - "PCIE_NE4BEG3_9", - "INT_INTERFACE_NE4BEG3" - ], - [ - "PCIE_WL1END1_9", - "INT_INTERFACE_WL1END1" - ], - [ - "PCIE_NE4C1_9", - "INT_INTERFACE_NE4C1" - ], - [ - "PCIE_SE2A0_9", - "INT_INTERFACE_SE2A0" - ], - [ - "PCIE_WL1END0_9", - "INT_INTERFACE_WL1END0" - ], - [ - "PCIE_WW2A0_9", - "INT_INTERFACE_WW2A0" - ], - [ - "PCIE_IMUX13_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT13" - ], - [ - "PCIE_IMUX25_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT25" - ], - [ - "PCIE_WL1END2_9", - "INT_INTERFACE_WL1END2" - ], - [ - "PCIE_WW4A3_9", - "INT_INTERFACE_WW4A3" - ], - [ - "PCIE_LH4_9", - "INT_INTERFACE_LH4" - ], - [ - "PCIE_LOGIC_OUTS_B14_R_9", - "INT_INTERFACE_LOGIC_OUTS_B14" - ], - [ - "PCIE_IMUX20_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT20" - ], - [ - "PCIE_WR1END3_9", - "INT_INTERFACE_WR1END3" - ], - [ - "PCIE_IMUX17_R_9", - "PCIE_INT_INTERFACE_IMUX_OUT17" - ], - [ - "PCIE_EE2A1_9", - "INT_INTERFACE_EE2A1" - ], - [ - "PCIE_SW4END2_9", - "INT_INTERFACE_SW4END2" - ], - [ - "PCIE_EE2BEG0_9", - "INT_INTERFACE_EE2BEG0" - ], - [ - "PCIE_WW4C2_9", - "INT_INTERFACE_WW4C2" - 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"VFRAME_IMUX17" - ], - [ - "CFG_CENTER_SE4BEG1_10", - "VFRAME_SE4BEG1" - ], - [ - "CFG_CENTER_NW4END3_10", - "VFRAME_NW4END3" - ], - [ - "CFG_CENTER_EE2A1_10", - "VFRAME_EE2A1" - ], - [ - "CFG_CENTER_WW4A2_10", - "VFRAME_WW4A2" - ], - [ - "CFG_CENTER_EE4A0_10", - "VFRAME_EE4A0" - ], - [ - "CFG_CENTER_NW4A1_10", - "VFRAME_NW4A1" - ], - [ - "CFG_CENTER_IMUX12_10", - "VFRAME_IMUX12" - ], - [ - "CFG_CENTER_NE4BEG1_10", - "VFRAME_NE4BEG1" - ], - [ - "CFG_CENTER_IMUX35_10", - "VFRAME_IMUX35" - ], - [ - "CFG_CENTER_FAN6_10", - "VFRAME_FAN6" - ], - [ - "CFG_CENTER_WR1END1_10", - "VFRAME_WR1END1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -3 - ], - "tile_types": [ - "CMT_TOP_L_UPPER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW2END3_8", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_EE2A1_8", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_WW2A2_8", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_SW2A0_8", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_WW2END0_8", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WW4END0_8", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_NW2A0_8", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_LH7_8", - "VBRK_LH7" - ], - [ - "CMT_TOP_EE2BEG3_8", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_SW4END2_8", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_LH1_8", - "VBRK_LH1" - ], - [ - "CMT_TOP_WW4B0_8", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_NE2A1_8", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_SE2A1_8", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_SE4BEG1_8", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_WW4END1_8", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_MONITOR_P_8", - "VBRK_MONITOR_P" - ], - [ - "CMT_TOP_NW2A2_8", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WL1END2_8", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_NW4END1_8", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_EL1BEG2_8", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_WW4A0_8", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_NW4END3_8", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW4C3_8", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_EL1BEG1_8", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_EE4C3_8", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_ER1BEG2_8", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_WW4A3_8", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_WW4END3_8", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_SW4A1_8", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_NE4BEG1_8", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_EE2BEG2_8", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_WL1END3_8", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_LH9_8", - "VBRK_LH9" - ], - [ - "CMT_TOP_NE4C2_8", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_LH12_8", - "VBRK_LH12" - ], - [ - "CMT_TOP_WW4C0_8", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_SE2A0_8", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_EE4C0_8", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_EE4B1_8", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_WW4A2_8", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_EE4C1_8", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_WW2A3_8", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_SE4BEG3_8", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_SW4A3_8", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_SW2A3_8", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_WW4END2_8", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_EE2A3_8", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_WR1END2_8", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_LH10_8", - "VBRK_LH10" - ], - [ - "CMT_TOP_SW4END3_8", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_NW4END0_8", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_EE4B2_8", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_SE4C0_8", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_SE4C1_8", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_NE4BEG2_8", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_SW2A2_8", - "VBRK_SW2A2" + "PCIE_NE4C2_9", + "INT_INTERFACE_NE4C2" ], [ - "CMT_TOP_SE4C3_8", - "VBRK_SE4C3" + "PCIE_NE4C3_9", + "INT_INTERFACE_NE4C3" ], [ - "CMT_TOP_LH8_8", - "VBRK_LH8" + "PCIE_NW2A0_9", + "INT_INTERFACE_NW2A0" ], [ - "CMT_TOP_WR1END0_8", - "VBRK_WR1END0" + "PCIE_NW2A1_9", + "INT_INTERFACE_NW2A1" ], [ - "CMT_TOP_WL1END0_8", - "VBRK_WL1END0" + "PCIE_NW2A2_9", + "INT_INTERFACE_NW2A2" ], [ - "CMT_TOP_SW4A0_8", - "VBRK_SW4A0" + "PCIE_NW2A3_9", + "INT_INTERFACE_NW2A3" ], [ - "CMT_TOP_EE4A2_8", - "VBRK_EE4A2" + "PCIE_NW4A0_9", + "INT_INTERFACE_NW4A0" ], [ - "CMT_TOP_WW2A0_8", - "VBRK_WW2A0" + "PCIE_NW4A1_9", + "INT_INTERFACE_NW4A1" ], [ - "CMT_TOP_NE2A3_8", - "VBRK_NE2A3" + "PCIE_NW4A2_9", + "INT_INTERFACE_NW4A2" ], [ - "CMT_TOP_SW4END0_8", - "VBRK_SW4END0" + "PCIE_NW4A3_9", + "INT_INTERFACE_NW4A3" ], [ - "CMT_TOP_WW2END2_8", - "VBRK_WW2END2" + "PCIE_NW4END0_9", + "INT_INTERFACE_NW4END0" ], [ - "CMT_TOP_NW2A1_8", - "VBRK_NW2A1" + "PCIE_NW4END1_9", + "INT_INTERFACE_NW4END1" ], [ - "CMT_TOP_EE4B3_8", - "VBRK_EE4B3" + "PCIE_NW4END2_9", + "INT_INTERFACE_NW4END2" ], [ - "CMT_TOP_LH6_8", - "VBRK_LH6" + "PCIE_NW4END3_9", + "INT_INTERFACE_NW4END3" ], [ - "CMT_TOP_WW4C2_8", - "VBRK_WW4C2" + "PCIE_SE2A0_9", + "INT_INTERFACE_SE2A0" ], [ - "CMT_TOP_NE4C3_8", - "VBRK_NE4C3" + "PCIE_SE2A1_9", + "INT_INTERFACE_SE2A1" ], [ - "CMT_TOP_WW4B2_8", - "VBRK_WW4B2" + "PCIE_SE2A2_9", + "INT_INTERFACE_SE2A2" ], [ - "CMT_TOP_ER1BEG0_8", - "VBRK_ER1BEG0" + "PCIE_SE2A3_9", + "INT_INTERFACE_SE2A3" ], [ - "CMT_TOP_EE4BEG1_8", - "VBRK_EE4BEG1" + "PCIE_SE4BEG0_9", + "INT_INTERFACE_SE4BEG0" ], [ - "CMT_TOP_SE4C2_8", - "VBRK_SE4C2" + "PCIE_SE4BEG1_9", + "INT_INTERFACE_SE4BEG1" ], [ - "CMT_TOP_NW4END2_8", - "VBRK_NW4END2" + "PCIE_SE4BEG2_9", + "INT_INTERFACE_SE4BEG2" ], [ - "CMT_TOP_SE2A3_8", - "VBRK_SE2A3" + "PCIE_SE4BEG3_9", + "INT_INTERFACE_SE4BEG3" ], [ - "CMT_TOP_SW4A2_8", - "VBRK_SW4A2" + "PCIE_SE4C0_9", + "INT_INTERFACE_SE4C0" ], [ - "CMT_TOP_WL1END1_8", - "VBRK_WL1END1" + "PCIE_SE4C1_9", + "INT_INTERFACE_SE4C1" ], [ - "CMT_TOP_WW4B1_8", - "VBRK_WW4B1" + "PCIE_SE4C2_9", + "INT_INTERFACE_SE4C2" ], [ - "CMT_TOP_EE4BEG0_8", - "VBRK_EE4BEG0" + "PCIE_SE4C3_9", + "INT_INTERFACE_SE4C3" ], [ - "CMT_TOP_EE4BEG2_8", - "VBRK_EE4BEG2" + "PCIE_SW2A0_9", + "INT_INTERFACE_SW2A0" ], [ - "CMT_TOP_SE4BEG2_8", - "VBRK_SE4BEG2" + "PCIE_SW2A1_9", + "INT_INTERFACE_SW2A1" ], [ - "CMT_TOP_ER1BEG3_8", - "VBRK_ER1BEG3" + "PCIE_SW2A2_9", + "INT_INTERFACE_SW2A2" ], [ - "CMT_TOP_LH4_8", - "VBRK_LH4" + "PCIE_SW2A3_9", + "INT_INTERFACE_SW2A3" ], [ - "CMT_TOP_EE4A1_8", - "VBRK_EE4A1" + "PCIE_SW4A0_9", + "INT_INTERFACE_SW4A0" ], [ - "CMT_TOP_EE2A0_8", - "VBRK_EE2A0" + "PCIE_SW4A1_9", + "INT_INTERFACE_SW4A1" ], [ - "CMT_TOP_LH5_8", - "VBRK_LH5" + "PCIE_SW4A2_9", + "INT_INTERFACE_SW4A2" ], [ - "CMT_TOP_EE4A0_8", - "VBRK_EE4A0" + "PCIE_SW4A3_9", + "INT_INTERFACE_SW4A3" ], [ - "CMT_TOP_SW4END1_8", - "VBRK_SW4END1" + "PCIE_SW4END0_9", + "INT_INTERFACE_SW4END0" ], [ - "CMT_TOP_EE2A2_8", - "VBRK_EE2A2" + "PCIE_SW4END1_9", + "INT_INTERFACE_SW4END1" ], [ - "CMT_TOP_WR1END1_8", - "VBRK_WR1END1" + "PCIE_SW4END2_9", + "INT_INTERFACE_SW4END2" ], [ - "CMT_TOP_NW4A2_8", - "VBRK_NW4A2" + "PCIE_SW4END3_9", + "INT_INTERFACE_SW4END3" ], [ - "CMT_TOP_EL1BEG3_8", - "VBRK_EL1BEG3" + "PCIE_WL1END0_9", + "INT_INTERFACE_WL1END0" ], [ - "CMT_TOP_EE2BEG0_8", - "VBRK_EE2BEG0" + "PCIE_WL1END1_9", + "INT_INTERFACE_WL1END1" ], [ - "CMT_TOP_SW2A1_8", - "VBRK_SW2A1" + "PCIE_WL1END2_9", + "INT_INTERFACE_WL1END2" ], [ - "CMT_TOP_LH3_8", - "VBRK_LH3" + "PCIE_WL1END3_9", + "INT_INTERFACE_WL1END3" ], [ - "CMT_TOP_WW4A1_8", - "VBRK_WW4A1" + "PCIE_WR1END0_9", + "INT_INTERFACE_WR1END0" ], [ - "CMT_TOP_WW4B3_8", - "VBRK_WW4B3" + "PCIE_WR1END1_9", + "INT_INTERFACE_WR1END1" ], [ - "CMT_TOP_WR1END3_8", - "VBRK_WR1END3" + "PCIE_WR1END2_9", + "INT_INTERFACE_WR1END2" ], [ - "CMT_TOP_NE2A2_8", - "VBRK_NE2A2" + "PCIE_WR1END3_9", + "INT_INTERFACE_WR1END3" ], [ - "CMT_TOP_WW4C1_8", - "VBRK_WW4C1" + "PCIE_WW2A0_9", + "INT_INTERFACE_WW2A0" ], [ - "CMT_TOP_NW2A3_8", - "VBRK_NW2A3" + "PCIE_WW2A1_9", + "INT_INTERFACE_WW2A1" ], [ - "CMT_TOP_LH11_8", - "VBRK_LH11" + "PCIE_WW2A2_9", + "INT_INTERFACE_WW2A2" ], [ - "CMT_TOP_NE4C1_8", - "VBRK_NE4C1" + "PCIE_WW2A3_9", + "INT_INTERFACE_WW2A3" ], [ - "CMT_TOP_WW2END1_8", - "VBRK_WW2END1" + "PCIE_WW2END0_9", + "INT_INTERFACE_WW2END0" ], [ - "CMT_TOP_NW4A1_8", - "VBRK_NW4A1" + "PCIE_WW2END1_9", + "INT_INTERFACE_WW2END1" ], [ - "CMT_TOP_NE4BEG0_8", - "VBRK_NE4BEG0" + "PCIE_WW2END2_9", + "INT_INTERFACE_WW2END2" ], [ - "CMT_TOP_SE4BEG0_8", - "VBRK_SE4BEG0" + "PCIE_WW2END3_9", + "INT_INTERFACE_WW2END3" ], [ - "CMT_TOP_NW4A0_8", - "VBRK_NW4A0" + "PCIE_WW4A0_9", + "INT_INTERFACE_WW4A0" ], [ - "CMT_TOP_WW2A1_8", - "VBRK_WW2A1" + "PCIE_WW4A1_9", + "INT_INTERFACE_WW4A1" ], [ - "CMT_TOP_EL1BEG0_8", - "VBRK_EL1BEG0" + "PCIE_WW4A2_9", + "INT_INTERFACE_WW4A2" ], [ - "CMT_TOP_EE4A3_8", - "VBRK_EE4A3" + "PCIE_WW4A3_9", + "INT_INTERFACE_WW4A3" ], [ - "CMT_TOP_EE4B0_8", - "VBRK_EE4B0" + "PCIE_WW4B0_9", + "INT_INTERFACE_WW4B0" ], [ - "CMT_TOP_NE2A0_8", - "VBRK_NE2A0" + "PCIE_WW4B1_9", + "INT_INTERFACE_WW4B1" ], [ - "CMT_TOP_EE2BEG1_8", - "VBRK_EE2BEG1" + "PCIE_WW4B2_9", + "INT_INTERFACE_WW4B2" ], [ - "CMT_TOP_NW4A3_8", - "VBRK_NW4A3" + "PCIE_WW4B3_9", + "INT_INTERFACE_WW4B3" ], [ - "CMT_TOP_EE4C2_8", - "VBRK_EE4C2" + "PCIE_WW4C0_9", + "INT_INTERFACE_WW4C0" ], [ - "CMT_TOP_EE4BEG3_8", - "VBRK_EE4BEG3" + "PCIE_WW4C1_9", + "INT_INTERFACE_WW4C1" ], [ - "CMT_TOP_LH2_8", - "VBRK_LH2" + "PCIE_WW4C2_9", + "INT_INTERFACE_WW4C2" ], [ - "CMT_TOP_MONITOR_N_8", - "VBRK_MONITOR_N" + "PCIE_WW4C3_9", + "INT_INTERFACE_WW4C3" ], [ - "CMT_TOP_SE2A2_8", - "VBRK_SE2A2" + "PCIE_WW4END0_9", + "INT_INTERFACE_WW4END0" ], [ - "CMT_TOP_NE4BEG3_8", - "VBRK_NE4BEG3" + "PCIE_WW4END1_9", + "INT_INTERFACE_WW4END1" ], [ - "CMT_TOP_ER1BEG1_8", - "VBRK_ER1BEG1" + "PCIE_WW4END2_9", + "INT_INTERFACE_WW4END2" ], [ - "CMT_TOP_NE4C0_8", - "VBRK_NE4C0" + "PCIE_WW4END3_9", + "INT_INTERFACE_WW4END3" ] ] }, @@ -42429,5464 +454625,880 @@ 2 ], "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" ], "wire_pairs": [ [ - "CLK_HROW_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_NW2A3_2", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_IMUX14_2", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_IMUX17_2", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_IMUX15_2", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_IMUX42_2", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_LH4_2", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_BYP6_2", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_SW4A2_2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE4B1_2", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_WW2END2_2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_EE4A0_2", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_NE4BEG2_2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_IMUX19_2", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_MONITOR_N_2", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_IMUX16_2", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4A0_2", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WR1END3_2", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_BYP0_2", + "PCIE_BYP0_R_8", "INT_INTERFACE_BYP0" ], [ - "CLK_HROW_IMUX20_2", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_IMUX27_2", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_IMUX5_2", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_SW4END3_2", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_IMUX31_2", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_SE4BEG3_2", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NW2A2_2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_LH10_2", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_LH6_2", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_IMUX44_2", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_IMUX47_2", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_SW4A3_2", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NW4A0_2", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_BYP3_2", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX2_2", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_IMUX11_2", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SE4BEG2_2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_NE4C3_2", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_NW4END0_2", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_IMUX6_2", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_CLK0_2", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WR1END2_2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX32_2", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NE2A1_2", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_LH9_2", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_FAN3_2", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_LH2_2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_SE2A1_2", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE2A0_2", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4B3_2", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_CTRL0_2", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX23_2", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_ER1BEG2_2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX12_2", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SW2A3_2", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_EE4BEG0_2", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX37_2", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_FAN2_2", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_LH1_2", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WR1END1_2", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_NW4A3_2", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_BYP4_2", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_IMUX40_2", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_IMUX39_2", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_EE2A2_2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_WW4B0_2", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_EL1BEG2_2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX8_2", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_LH11_2", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_IMUX29_2", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX43_2", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_EE4C0_2", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_BYP5_2", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_WW2A3_2", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_WW4END2_2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_FAN6_2", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4C2_2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SE4BEG1_2", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NW4A1_2", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_EE2A1_2", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_IMUX18_2", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_WW4B2_2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_WW2A1_2", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX7_2", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_IMUX9_2", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4A3_2", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_NE2A3_2", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_FAN1_2", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_SE4BEG0_2", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_IMUX3_2", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_SE4C0_2", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW4END0_2", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WW4A3_2", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EE2BEG3_2", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_SE4C1_2", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX45_2", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_EE4BEG2_2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW4C3_2", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW2END3_2", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW2END0_2", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_WR1END0_2", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE2BEG0_2", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_MONITOR_P_2", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_EE4B2_2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NE4BEG0_2", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NE4C1_2", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_IMUX22_2", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_NW4END2_2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EL1BEG0_2", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SW2A1_2", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4BEG3_2", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_WW4C1_2", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_SW4A1_2", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_WW2A2_2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_WW4B3_2", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_LH12_2", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_EE2BEG1_2", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_NW4END1_2", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WL1END0_2", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NE2A2_2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_WW4END1_2", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_CTRL1_2", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW4END3_2", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_NW4END3_2", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SE2A2_2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_BYP1_2", + "PCIE_BYP1_R_8", "INT_INTERFACE_BYP1" ], [ - "CLK_HROW_FAN7_2", - "INT_INTERFACE_FAN7" + "PCIE_BYP2_R_8", + "INT_INTERFACE_BYP2" ], [ - "CLK_HROW_EL1BEG3_2", - "INT_INTERFACE_EL1BEG3" + "PCIE_BYP3_R_8", + "INT_INTERFACE_BYP3" ], [ - "CLK_HROW_IMUX35_2", - "INT_INTERFACE_IMUX35" + "PCIE_BYP4_R_8", + "INT_INTERFACE_BYP4" ], [ - "CLK_HROW_ER1BEG0_2", - "INT_INTERFACE_ER1BEG0" + "PCIE_BYP5_R_8", + "INT_INTERFACE_BYP5" ], [ - "CLK_HROW_WL1END2_2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_SE2A3_2", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_EE4BEG1_2", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_IMUX36_2", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_BYP7_2", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_LH3_2", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_SW2A0_2", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_IMUX21_2", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_NE2A0_2", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_IMUX33_2", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX46_2", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_FAN0_2", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX13_2", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_IMUX30_2", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX24_2", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_EE4B0_2", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_EE4A2_2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE4C2_2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_EE4BEG3_2", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_IMUX26_2", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_SE2A0_2", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_WW2A0_2", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW4C0_2", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_LH5_2", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_IMUX0_2", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_WW4A2_2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_WW2END1_2", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_NW2A0_2", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_FAN5_2", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_FAN4_2", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_SE4C2_2", - "INT_INTERFACE_SE4C2" - ] - ] - }, - { - "grid_deltas": [ - 1, - -3 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_LH6_4", - "VBRK_LH6" - ], - [ - "CMT_TOP_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_SE4C0_4", - "VBRK_SE4C0" - ], - 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"INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_IMUX29_6", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX3_6", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_CLK0_6", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW4END2_6", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_IMUX40_6", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_BYP0_6", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_SW4A3_6", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX1_6", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_EE4A1_6", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_SW2A0_6", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH6_6", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_EE2BEG0_6", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_EE4A3_6", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_EE4C0_6", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_WW4B0_6", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_EE4A2_6", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_BYP3_6", - "INT_INTERFACE_BYP3" - ] - ] - }, - { - "grid_deltas": [ - 0, - 5 - ], - "tile_types": [ - "BRAM_L", - "BRAM_L" - ], - "wire_pairs": [ - [ - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "BRAM_CASCOUT_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU4", - "BRAM_CASCOUT_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "BRAM_CASCOUT_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "BRAM_CASCOUT_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "BRAM_CASCOUT_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU13", - "BRAM_CASCOUT_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "BRAM_CASCOUT_ADDRBWRADDRU5" - ], - [ - "BRAM_FIFO36_CASCADEINB", - "BRAM_FIFO36_CASCADEOUTB_1" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "BRAM_CASCOUT_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU8", - "BRAM_CASCOUT_ADDRARDADDRU8" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "BRAM_CASCOUT_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU9" - ], - [ - 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"BRAM_CASCOUT_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "BRAM_CASCOUT_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU6", - "BRAM_CASCOUT_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRARDADDRU7" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU3", - "BRAM_CASCOUT_ADDRARDADDRU3" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU14", - "BRAM_CASCOUT_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU5", - "BRAM_CASCOUT_ADDRARDADDRU5" - ] - ] - }, - { - "grid_deltas": [ - 1, - 4 - ], - "tile_types": [ - "CMT_FIFO_L", - "INT_INTERFACE_L" - ], - "wire_pairs": [ - [ - "CMT_FIFO_WW4B3_2", - "INT_INTERFACE_WW4B3" - ], - [ - "CMT_FIFO_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CMT_FIFO_L_BYP7_2", - "INT_INTERFACE_BYP7" - ], - [ - "CMT_FIFO_L_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "CMT_FIFO_SE4C0_2", - "INT_INTERFACE_SE4C0" - ], - [ - "CMT_FIFO_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CMT_FIFO_WW4C2_2", - "INT_INTERFACE_WW4C2" - ], - [ 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"INT_INTERFACE_BYP0" - ], - [ - "CMT_FIFO_NW2A2_2", - "INT_INTERFACE_NW2A2" - ], - [ - "CMT_FIFO_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CMT_FIFO_L_FAN5_2", - "INT_INTERFACE_FAN5" - ], - [ - "CMT_FIFO_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CMT_FIFO_WW4A0_2", - "INT_INTERFACE_WW4A0" - ], - [ - "CMT_FIFO_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CMT_FIFO_NW4A0_2", - "INT_INTERFACE_NW4A0" - ], - [ - "CMT_FIFO_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CMT_FIFO_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS11_2", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "CMT_FIFO_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CMT_FIFO_LH3_2", - "INT_INTERFACE_LH3" - ], - [ - "CMT_FIFO_SE4C2_2", - "INT_INTERFACE_SE4C2" - ], - [ - "CMT_FIFO_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CMT_FIFO_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CMT_FIFO_L_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "CMT_FIFO_EE2A0_2", + "PCIE_EE2A0_8", "INT_INTERFACE_EE2A0" ], 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"INT_INTERFACE_IMUX13" - ], - [ - "CMT_FIFO_L_FAN6_2", - "INT_INTERFACE_FAN6" - ], - [ - "CMT_FIFO_LH5_2", - "INT_INTERFACE_LH5" - ], - [ - "CMT_FIFO_L_CTRL0_2", - "INT_INTERFACE_CTRL0" - ], - [ - "CMT_FIFO_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CMT_FIFO_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CMT_FIFO_L_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CMT_FIFO_L_IMUX22_2", - "INT_INTERFACE_IMUX22" - ], - [ - "CMT_FIFO_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "CMT_FIFO_SE4BEG3_2", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CMT_FIFO_EE2BEG0_2", + "PCIE_EE2BEG0_8", "INT_INTERFACE_EE2BEG0" ], [ - "CMT_FIFO_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CMT_FIFO_L_IMUX40_2", - "INT_INTERFACE_IMUX40" - ], - [ - "CMT_FIFO_L_CLK0_2", - "INT_INTERFACE_CLK0" - ], - [ - "CMT_FIFO_L_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CMT_FIFO_WW2A0_2", - "INT_INTERFACE_WW2A0" - ], - [ - "CMT_FIFO_EE4C0_2", - "INT_INTERFACE_EE4C0" - ], - [ - "CMT_FIFO_L_IMUX15_2", - "INT_INTERFACE_IMUX15" - ], - [ - "CMT_FIFO_NW2A3_2", - "INT_INTERFACE_NW2A3" - ], - [ - "CMT_FIFO_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CMT_FIFO_L_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CMT_FIFO_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CMT_FIFO_PHASER_TO_IO_ICLK_2", - "INT_INTERFACE_PHASER_TO_IO_ICLK" - ], - [ - "CMT_FIFO_EE2BEG1_2", + "PCIE_EE2BEG1_8", "INT_INTERFACE_EE2BEG1" ], [ - "CMT_FIFO_SW4END0_2", - "INT_INTERFACE_SW4END0" + "PCIE_EE2BEG2_8", + "INT_INTERFACE_EE2BEG2" ], [ - "CMT_FIFO_L_LOGIC_OUTS15_2", - "INT_INTERFACE_LOGIC_OUTS_L_B15" + "PCIE_EE2BEG3_8", + "INT_INTERFACE_EE2BEG3" ], [ - "CMT_FIFO_L_IMUX38_2", - "INT_INTERFACE_IMUX38" + "PCIE_EE4A0_8", + "INT_INTERFACE_EE4A0" ], [ - "CMT_FIFO_WL1END1_2", - "INT_INTERFACE_WL1END1" + "PCIE_EE4A1_8", + "INT_INTERFACE_EE4A1" ], [ - "CMT_FIFO_L_IMUX14_2", - "INT_INTERFACE_IMUX14" + "PCIE_EE4A2_8", + "INT_INTERFACE_EE4A2" ], [ - "CMT_FIFO_NE2A3_2", - "INT_INTERFACE_NE2A3" + "PCIE_EE4A3_8", + "INT_INTERFACE_EE4A3" ], [ - "CMT_FIFO_WR1END2_2", - "INT_INTERFACE_WR1END2" + "PCIE_EE4B0_8", + "INT_INTERFACE_EE4B0" ], [ - "CMT_FIFO_L_IMUX30_2", - "INT_INTERFACE_IMUX30" - ], - [ - "CMT_FIFO_SW4A1_2", - "INT_INTERFACE_SW4A1" - ], - [ - "CMT_FIFO_LH4_2", - "INT_INTERFACE_LH4" - ], - [ - "CMT_FIFO_WW4END2_2", - "INT_INTERFACE_WW4END2" - ], - [ - "CMT_FIFO_WW4C1_2", - "INT_INTERFACE_WW4C1" - ], - [ - "CMT_FIFO_NE4C3_2", - "INT_INTERFACE_NE4C3" - ], - [ - "CMT_FIFO_MONITOR_N_2", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CMT_FIFO_EL1BEG3_2", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CMT_FIFO_L_IMUX5_2", - "INT_INTERFACE_IMUX5" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS20_2", - "INT_INTERFACE_LOGIC_OUTS_L_B20" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS19_2", - "INT_INTERFACE_LOGIC_OUTS_L_B19" - ], - [ - "CMT_FIFO_L_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CMT_FIFO_NE4BEG0_2", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CMT_FIFO_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", - 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"SW6A2" - ], - [ - "CLBLL_LH9", - "LH9" - ], - [ - "CLBLL_BYP5", - "BYP5" - ], - [ - "CLBLL_NE4BEG0", - "NE6BEG0" - ], - [ - "CLBLL_NE4BEG2", - "NE6BEG2" - ], - [ - "CLBLL_IMUX25", - "IMUX25" - ], - [ - "CLBLL_LH7", - "LH7" - ], - [ - "CLBLL_LH4", - "LH4" - ], - [ - "CLBLL_NW4END1", - "NW6END1" - ], - [ - "CLBLL_EE4BEG3", - "EE4BEG3" - ], - [ - "CLBLL_EL1BEG3", - "EL1BEG3" - ], - [ - "CLBLL_EL1BEG0", - "EL1BEG0" - ], - [ - "CLBLL_SE4C2", - "SE6E2" - ], - [ - "CLBLL_IMUX35", - "IMUX35" - ], - [ - "CLBLL_WW2A0", - "WW2A0" - ], - [ - "CLBLL_IMUX13", - "IMUX13" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_PMV_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_PMV_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_PMV_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "CLK_PMV_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_PMV_SW4END2_0", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_PMV_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_PMV_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_PMV_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_PMV_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_PMV_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_PMV_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_PMV_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_PMV_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_PMV_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_PMV_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_PMV_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_PMV_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_PMV_LH9_0", - "INT_INTERFACE_LH9" - ], - [ - "CLK_PMV_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_PMV_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_PMV_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_PMV_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_PMV_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_SE4C0_0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_PMV_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_PMV_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_PMV_MONITOR_N_0", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_PMV_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_PMV_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_PMV_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_PMV_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_MONITOR_P_0", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_PMV_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_PMV_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_PMV_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_PMV_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_PMV_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_PMV_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_PMV_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_PMV_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_PMV_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_PMV_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_PMV_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_PMV_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_PMV_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_NW4END2_0", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_PMV_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_PMV_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_PMV_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_PMV_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_PMV_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_PMV_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_PMV_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_PMV_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_PMV_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_PMV_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_PMV_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_PMV_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_PMV_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_PMV_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_PMV_WR1END3_0", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_PMV_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_PMV_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_PMV_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_PMV_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_PMV_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_PMV_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_PMV_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_PMV_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_PMV_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_PMV_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_PMV_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_PMV_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_PMV_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_PMV_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_PMV_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_PMV_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_PMV_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_PMV_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_PMV_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_PMV_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_PMV_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_PMV_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_PMV_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_PMV_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_PMV_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_PMV_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_PMV_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_PMV_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_PMV_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_PMV_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_PMV_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_PMV_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_PMV_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_PMV_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_PMV_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_PMV_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_PMV_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_PMV_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_PMV_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_PMV_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_PMV_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_PMV_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_PMV_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_PMV_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_PMV_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_PMV_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_PMV_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_PMV_LH1_0", + "PCIE_LH1_7", "INT_INTERFACE_LH1" ], [ - "CLK_PMV_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" + "PCIE_LH2_7", + "INT_INTERFACE_LH2" ], [ - "CLK_PMV_IMUX15_0", - "INT_INTERFACE_IMUX15" + "PCIE_LH3_7", + "INT_INTERFACE_LH3" ], [ - "CLK_PMV_NE2A2_0", - "INT_INTERFACE_NE2A2" + "PCIE_LH4_7", + "INT_INTERFACE_LH4" ], [ - "CLK_PMV_IMUX41_0", - "INT_INTERFACE_IMUX41" + "PCIE_LH5_7", + "INT_INTERFACE_LH5" ], [ - "CLK_PMV_EE4C1_0", - "INT_INTERFACE_EE4C1" + "PCIE_LH6_7", + "INT_INTERFACE_LH6" ], [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" + "PCIE_LH7_7", + "INT_INTERFACE_LH7" ], [ - "CLK_PMV_EE4A0_0", - "INT_INTERFACE_EE4A0" + "PCIE_LH8_7", + "INT_INTERFACE_LH8" ], [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" + "PCIE_LH9_7", + "INT_INTERFACE_LH9" ], [ - "CLK_PMV_SE2A0_0", - "INT_INTERFACE_SE2A0" + "PCIE_LH10_7", + "INT_INTERFACE_LH10" ], [ - "CLK_PMV_EE2A2_0", - "INT_INTERFACE_EE2A2" + "PCIE_LH11_7", + "INT_INTERFACE_LH11" ], [ - "CLK_PMV_WL1END2_0", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_PMV_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_PMV_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_LH12_0", + "PCIE_LH12_7", "INT_INTERFACE_LH12" ], [ - "CLK_PMV_IMUX42_0", - "INT_INTERFACE_IMUX42" + "PCIE_LOGIC_OUTS_B0_R_7", + "INT_INTERFACE_LOGIC_OUTS_B0" ], [ - "CLK_PMV_SW2A1_0", - "INT_INTERFACE_SW2A1" + "PCIE_LOGIC_OUTS_B1_R_7", + "INT_INTERFACE_LOGIC_OUTS_B1" ], [ - "CLK_PMV_SW4END0_0", - "INT_INTERFACE_SW4END0" + "PCIE_LOGIC_OUTS_B2_R_7", + "INT_INTERFACE_LOGIC_OUTS_B2" ], [ - "CLK_PMV_SW4A1_0", - "INT_INTERFACE_SW4A1" + "PCIE_LOGIC_OUTS_B3_R_7", + "INT_INTERFACE_LOGIC_OUTS_B3" ], [ - "CLK_PMV_EE4A1_0", - "INT_INTERFACE_EE4A1" + "PCIE_LOGIC_OUTS_B4_R_7", + "INT_INTERFACE_LOGIC_OUTS_B4" ], [ - "CLK_PMV_FAN4_0", - "INT_INTERFACE_FAN4" + "PCIE_LOGIC_OUTS_B5_R_7", + "INT_INTERFACE_LOGIC_OUTS_B5" ], [ - "CLK_PMV_SE2A2_0", - "INT_INTERFACE_SE2A2" + "PCIE_LOGIC_OUTS_B6_R_7", + "INT_INTERFACE_LOGIC_OUTS_B6" ], [ - "CLK_PMV_NE2A0_0", + "PCIE_LOGIC_OUTS_B7_R_7", + "INT_INTERFACE_LOGIC_OUTS_B7" + ], + [ + "PCIE_LOGIC_OUTS_B8_R_7", + "INT_INTERFACE_LOGIC_OUTS_B8" + ], + [ + "PCIE_LOGIC_OUTS_B9_R_7", + "INT_INTERFACE_LOGIC_OUTS_B9" + ], + [ + "PCIE_LOGIC_OUTS_B10_R_7", + "INT_INTERFACE_LOGIC_OUTS_B10" + ], + [ + "PCIE_LOGIC_OUTS_B11_R_7", + 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[ - "CFG_CENTER_SE2A2_16", - "VFRAME_SE2A2" - ], - [ - "CFG_CENTER_IMUX10_16", - "VFRAME_IMUX10" - ], - [ - "CFG_CENTER_NW4END2_16", - "VFRAME_NW4END2" - ], - [ - "CFG_CENTER_EE2A1_16", - "VFRAME_EE2A1" - ], - [ - "CFG_CENTER_EE4B3_16", - "VFRAME_EE4B3" - ], - [ - "CFG_CENTER_IMUX24_16", - "VFRAME_IMUX24" - ], - [ - "CFG_CENTER_WW4C1_16", - "VFRAME_WW4C1" - ], - [ - "CFG_CENTER_LH2_16", - "VFRAME_LH2" - ], - [ - "CFG_CENTER_LH12_16", - "VFRAME_LH12" - ], - [ - "CFG_CENTER_SE4C2_16", - "VFRAME_SE4C2" - ], - [ - "CFG_CENTER_WW4END0_16", - "VFRAME_WW4END0" - ], - [ - "CFG_CENTER_FAN7_16", - "VFRAME_FAN7" - ], - [ - "CFG_CENTER_EE4BEG1_16", - "VFRAME_EE4BEG1" - ], - [ - "CFG_CENTER_SW2A1_16", - "VFRAME_SW2A1" - ], - [ - "CFG_CENTER_WW4C2_16", - "VFRAME_WW4C2" - ], - [ - "CFG_CENTER_FAN3_16", - "VFRAME_FAN3" - ], - [ - "CFG_CENTER_EE2A2_16", - "VFRAME_EE2A2" - ], - [ - "CFG_CENTER_LH5_16", - "VFRAME_LH5" - ], - [ - "CFG_CENTER_IMUX34_16", - "VFRAME_IMUX34" - ], - [ - "CFG_CENTER_IMUX39_16", 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], - [ - "CFG_CENTER_EE2A0_16", - "VFRAME_EE2A0" - ], - [ - "CFG_CENTER_IMUX38_16", - "VFRAME_IMUX38" - ], - [ - "CFG_CENTER_SW4END2_16", - "VFRAME_SW4END2" - ], - [ - "CFG_CENTER_IMUX9_16", - "VFRAME_IMUX9" - ], - [ - "CFG_CENTER_IMUX41_16", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_IMUX37_16", - "VFRAME_IMUX37" - ], - [ - "CFG_CENTER_EE4A1_16", - "VFRAME_EE4A1" - ], - [ - "CFG_CENTER_BYP3_16", - "VFRAME_BYP3" - ], - [ - "CFG_CENTER_CTRL1_16", - "VFRAME_CTRL1" - ], - [ - "CFG_CENTER_IMUX26_16", - "VFRAME_IMUX26" - ], - [ - "CFG_CENTER_WR1END0_16", - "VFRAME_WR1END0" - ], - [ - "CFG_CENTER_IMUX0_16", - "VFRAME_IMUX0" - ], - [ - "CFG_CENTER_SE4C1_16", - "VFRAME_SE4C1" - ], - [ - "CFG_CENTER_SE2A0_16", - "VFRAME_SE2A0" - ], - [ - "CFG_CENTER_WW2END1_16", - "VFRAME_WW2END1" - ], - [ - "CFG_CENTER_ER1BEG3_16", - "VFRAME_ER1BEG3" - ], - [ - "CFG_CENTER_SE2A3_16", - "VFRAME_SE2A3" - ], - [ - "CFG_CENTER_IMUX21_16", - "VFRAME_IMUX21" - ], - [ - "CFG_CENTER_WW4END2_16", - "VFRAME_WW4END2" - ], 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"VFRAME_IMUX17" + "PCIE_WW2A0_7", + "INT_INTERFACE_WW2A0" ], [ - "CFG_CENTER_WW4B1_16", - "VFRAME_WW4B1" + "PCIE_WW2A1_7", + "INT_INTERFACE_WW2A1" ], [ - "CFG_CENTER_CLK0_16", - "VFRAME_CLK0" + "PCIE_WW2A2_7", + "INT_INTERFACE_WW2A2" ], [ - "CFG_CENTER_SE4C0_16", - "VFRAME_SE4C0" + "PCIE_WW2A3_7", + "INT_INTERFACE_WW2A3" ], [ - "CFG_CENTER_EE4A2_16", - "VFRAME_EE4A2" + "PCIE_WW2END0_7", + "INT_INTERFACE_WW2END0" ], [ - "CFG_CENTER_IMUX33_16", - "VFRAME_IMUX33" + "PCIE_WW2END1_7", + "INT_INTERFACE_WW2END1" ], [ - "CFG_CENTER_EE4B0_16", - "VFRAME_EE4B0" + "PCIE_WW2END2_7", + "INT_INTERFACE_WW2END2" ], [ - "CFG_CENTER_NE4BEG2_16", - "VFRAME_NE4BEG2" + "PCIE_WW2END3_7", + "INT_INTERFACE_WW2END3" ], [ - "CFG_CENTER_WL1END2_16", - "VFRAME_WL1END2" + "PCIE_WW4A0_7", + "INT_INTERFACE_WW4A0" ], [ - "CFG_CENTER_IMUX3_16", - "VFRAME_IMUX3" + "PCIE_WW4A1_7", + "INT_INTERFACE_WW4A1" ], [ - "CFG_CENTER_SE2A1_16", - "VFRAME_SE2A1" + "PCIE_WW4A2_7", + "INT_INTERFACE_WW4A2" ], [ - "CFG_CENTER_LH8_16", - "VFRAME_LH8" + "PCIE_WW4A3_7", + "INT_INTERFACE_WW4A3" ], [ - "CFG_CENTER_BYP1_16", - "VFRAME_BYP1" + "PCIE_WW4B0_7", + "INT_INTERFACE_WW4B0" ], [ - "CFG_CENTER_IMUX23_16", - "VFRAME_IMUX23" + "PCIE_WW4B1_7", + "INT_INTERFACE_WW4B1" ], [ - "CFG_CENTER_EE4A3_16", - "VFRAME_EE4A3" + "PCIE_WW4B2_7", + "INT_INTERFACE_WW4B2" ], [ - "CFG_CENTER_IMUX16_16", - "VFRAME_IMUX16" + "PCIE_WW4B3_7", + "INT_INTERFACE_WW4B3" ], [ - "CFG_CENTER_IMUX40_16", - "VFRAME_IMUX40" + "PCIE_WW4C0_7", + "INT_INTERFACE_WW4C0" ], [ - "CFG_CENTER_IMUX20_16", - "VFRAME_IMUX20" + "PCIE_WW4C1_7", + "INT_INTERFACE_WW4C1" ], [ - "CFG_CENTER_NW4A2_16", - "VFRAME_NW4A2" + "PCIE_WW4C2_7", + "INT_INTERFACE_WW4C2" ], [ - "CFG_CENTER_FAN4_16", - "VFRAME_FAN4" + "PCIE_WW4C3_7", + "INT_INTERFACE_WW4C3" ], [ - "CFG_CENTER_FAN5_16", - "VFRAME_FAN5" + "PCIE_WW4END0_7", + "INT_INTERFACE_WW4END0" ], [ - "CFG_CENTER_IMUX46_16", - "VFRAME_IMUX46" + "PCIE_WW4END1_7", + "INT_INTERFACE_WW4END1" ], [ - "CFG_CENTER_NE2A2_16", - "VFRAME_NE2A2" + "PCIE_WW4END2_7", + "INT_INTERFACE_WW4END2" ], [ - "CFG_CENTER_IMUX6_16", - "VFRAME_IMUX6" + "PCIE_WW4END3_7", + "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, - -1 + 4 ], "tile_types": [ - "RIOI", - "R_TERM_INT" + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" ], "wire_pairs": [ [ - "IOI_LOGIC_OUTS4_1", - "TERM_INT_LOGIC_OUTS_L_B4" + "PCIE_BYP0_R_6", + "INT_INTERFACE_BYP0" ], [ - "IOI_LOGIC_OUTS9_1", - "TERM_INT_LOGIC_OUTS_L_B9" + "PCIE_BYP1_R_6", + "INT_INTERFACE_BYP1" ], [ - "IOI_IMUX27_1", - "TERM_INT_IMUX27" + "PCIE_BYP2_R_6", + "INT_INTERFACE_BYP2" ], [ - "IOI_IMUX45_1", - "TERM_INT_IMUX45" + "PCIE_BYP3_R_6", + "INT_INTERFACE_BYP3" ], [ - "IOI_IMUX40_1", - "TERM_INT_IMUX40" + "PCIE_BYP4_R_6", + "INT_INTERFACE_BYP4" ], [ - "IOI_IMUX28_1", - "TERM_INT_IMUX28" + "PCIE_BYP5_R_6", + "INT_INTERFACE_BYP5" ], [ - "IOI_IMUX17_1", - "TERM_INT_IMUX17" + "PCIE_BYP6_R_6", + "INT_INTERFACE_BYP6" ], [ - "IOI_IMUX21_1", - "TERM_INT_IMUX21" + "PCIE_BYP7_R_6", + "INT_INTERFACE_BYP7" ], [ - "IOI_BLOCK_OUTS1_1", - "TERM_INT_BLOCK_OUTS_L_B1" + "PCIE_CLK0_R_6", + "INT_INTERFACE_CLK0" ], [ - "IOI_LOGIC_OUTS0_1", - "TERM_INT_LOGIC_OUTS_L_B0" + "PCIE_CLK1_R_6", + "INT_INTERFACE_CLK1" ], [ - "IOI_IMUX37_1", - "TERM_INT_IMUX37" + "PCIE_CTRL0_R_6", + "INT_INTERFACE_CTRL0" ], [ - "IOI_IMUX5_1", - "TERM_INT_IMUX5" + "PCIE_CTRL1_R_6", + "INT_INTERFACE_CTRL1" ], [ - "IOI_IMUX12_1", - "TERM_INT_IMUX12" + "PCIE_EE2A0_6", + "INT_INTERFACE_EE2A0" ], [ - "IOI_IMUX34_1", - "TERM_INT_IMUX34" + "PCIE_EE2A1_6", + "INT_INTERFACE_EE2A1" ], [ - "IOI_LOGIC_OUTS20_1", - "TERM_INT_LOGIC_OUTS_L_B20" + "PCIE_EE2A2_6", + "INT_INTERFACE_EE2A2" ], [ - "IOI_LOGIC_OUTS21_1", - "TERM_INT_LOGIC_OUTS_L_B21" + "PCIE_EE2A3_6", + "INT_INTERFACE_EE2A3" ], [ - "IOI_IMUX18_1", - "TERM_INT_IMUX18" + "PCIE_EE2BEG0_6", + "INT_INTERFACE_EE2BEG0" ], [ - "IOI_BYP3_1", - "TERM_INT_BYP3" + "PCIE_EE2BEG1_6", + "INT_INTERFACE_EE2BEG1" ], [ - "IOI_LOGIC_OUTS22_1", - "TERM_INT_LOGIC_OUTS_L_B22" + "PCIE_EE2BEG2_6", + "INT_INTERFACE_EE2BEG2" ], [ - "IOI_IMUX4_1", - "TERM_INT_IMUX4" + "PCIE_EE2BEG3_6", + "INT_INTERFACE_EE2BEG3" ], [ - "IOI_BLOCK_OUTS0_1", - "TERM_INT_BLOCK_OUTS_L_B0" + "PCIE_EE4A0_6", + "INT_INTERFACE_EE4A0" ], [ - "IOI_IMUX10_1", - "TERM_INT_IMUX10" + "PCIE_EE4A1_6", + "INT_INTERFACE_EE4A1" ], [ - "IOI_CLK0_1", - "TERM_INT_CLK0" + "PCIE_EE4A2_6", + "INT_INTERFACE_EE4A2" ], [ - "IOI_FAN3_1", - "TERM_INT_FAN3" + "PCIE_EE4A3_6", + "INT_INTERFACE_EE4A3" ], [ - "IOI_IMUX46_1", - "TERM_INT_IMUX46" + "PCIE_EE4B0_6", + "INT_INTERFACE_EE4B0" ], [ - "IOI_FAN6_1", - "TERM_INT_FAN6" + "PCIE_EE4B1_6", + "INT_INTERFACE_EE4B1" ], [ - "IOI_LOGIC_OUTS13_1", - "TERM_INT_LOGIC_OUTS_L_B13" + "PCIE_EE4B2_6", + "INT_INTERFACE_EE4B2" ], [ - "IOI_LOGIC_OUTS19_1", - "TERM_INT_LOGIC_OUTS_L_B19" + "PCIE_EE4B3_6", + "INT_INTERFACE_EE4B3" ], [ - "IOI_LOGIC_OUTS11_1", - "TERM_INT_LOGIC_OUTS_L_B11" + "PCIE_EE4BEG0_6", + "INT_INTERFACE_EE4BEG0" ], [ - "IOI_BYP7_1", - "TERM_INT_BYP7" + "PCIE_EE4BEG1_6", + "INT_INTERFACE_EE4BEG1" ], [ - "IOI_FAN4_1", - "TERM_INT_FAN4" + "PCIE_EE4BEG2_6", + "INT_INTERFACE_EE4BEG2" ], [ - "IOI_IMUX31_1", - "TERM_INT_IMUX31" + "PCIE_EE4BEG3_6", + "INT_INTERFACE_EE4BEG3" ], [ - "IOI_LOGIC_OUTS15_1", - "TERM_INT_LOGIC_OUTS_L_B15" + "PCIE_EE4C0_6", + "INT_INTERFACE_EE4C0" ], [ - "IOI_LOGIC_OUTS7_1", - "TERM_INT_LOGIC_OUTS_L_B7" + "PCIE_EE4C1_6", + "INT_INTERFACE_EE4C1" ], [ - "IOI_FAN5_1", - "TERM_INT_FAN5" + "PCIE_EE4C2_6", + "INT_INTERFACE_EE4C2" ], [ - "IOI_IMUX23_1", - "TERM_INT_IMUX23" + "PCIE_EE4C3_6", + "INT_INTERFACE_EE4C3" ], [ - "IOI_LOGIC_OUTS2_1", - "TERM_INT_LOGIC_OUTS_L_B2" + "PCIE_EL1BEG0_6", + "INT_INTERFACE_EL1BEG0" ], [ - "IOI_IMUX26_1", - "TERM_INT_IMUX26" + "PCIE_EL1BEG1_6", + "INT_INTERFACE_EL1BEG1" ], [ - "IOI_IMUX24_1", - "TERM_INT_IMUX24" + "PCIE_EL1BEG2_6", + "INT_INTERFACE_EL1BEG2" ], [ - "IOI_IMUX38_1", - "TERM_INT_IMUX38" + "PCIE_EL1BEG3_6", + "INT_INTERFACE_EL1BEG3" ], [ - "IOI_BLOCK_OUTS2_1", - "TERM_INT_BLOCK_OUTS_L_B2" + "PCIE_ER1BEG0_6", + "INT_INTERFACE_ER1BEG0" ], [ - "IOI_BYP2_1", - "TERM_INT_BYP2" + "PCIE_ER1BEG1_6", + "INT_INTERFACE_ER1BEG1" ], [ - "IOI_IMUX2_1", - "TERM_INT_IMUX2" + "PCIE_ER1BEG2_6", + "INT_INTERFACE_ER1BEG2" ], [ - "IOI_LOGIC_OUTS8_1", - "TERM_INT_LOGIC_OUTS_L_B8" + "PCIE_ER1BEG3_6", + "INT_INTERFACE_ER1BEG3" ], [ - "IOI_FAN2_1", - "TERM_INT_FAN2" + "PCIE_FAN0_R_6", + "INT_INTERFACE_FAN0" ], [ - "IOI_IMUX36_1", - "TERM_INT_IMUX36" + "PCIE_FAN1_R_6", + "INT_INTERFACE_FAN1" ], [ - "IOI_PHASER_TO_IO_ICLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" + "PCIE_FAN2_R_6", + "INT_INTERFACE_FAN2" ], [ - "IOI_BYP6_1", - "TERM_INT_BYP6" + "PCIE_FAN3_R_6", + "INT_INTERFACE_FAN3" ], [ - "IOI_LOGIC_OUTS6_1", - "TERM_INT_LOGIC_OUTS_L_B6" + "PCIE_FAN4_R_6", + "INT_INTERFACE_FAN4" ], [ - "IOI_IMUX32_1", - "TERM_INT_IMUX32" + "PCIE_FAN5_R_6", + "INT_INTERFACE_FAN5" ], [ - "IOI_LOGIC_OUTS14_1", - "TERM_INT_LOGIC_OUTS_L_B14" + "PCIE_FAN6_R_6", + "INT_INTERFACE_FAN6" ], [ - "IOI_IMUX11_1", - "TERM_INT_IMUX11" + "PCIE_FAN7_R_6", + "INT_INTERFACE_FAN7" ], [ - "IOI_IMUX7_1", - "TERM_INT_IMUX7" + "PCIE_IMUX0_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT0" ], [ - "IOI_FAN1_1", - "TERM_INT_FAN1" + "PCIE_IMUX1_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT1" ], [ - "IOI_LOGIC_OUTS18_1", - "TERM_INT_LOGIC_OUTS_L_B18" + "PCIE_IMUX2_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT2" ], [ - "IOI_IMUX19_1", - "TERM_INT_IMUX19" + "PCIE_IMUX3_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT3" ], [ - "IOI_IMUX0_1", - "TERM_INT_IMUX0" + "PCIE_IMUX4_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT4" ], [ - "IOI_IMUX39_1", - "TERM_INT_IMUX39" + "PCIE_IMUX5_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT5" ], [ - "IOI_IMUX41_1", - "TERM_INT_IMUX41" + "PCIE_IMUX6_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT6" ], [ - "IOI_IMUX9_1", - "TERM_INT_IMUX9" + "PCIE_IMUX7_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT7" ], [ - "IOI_PHASER_TO_IO_OCLK_0", - "L_TERM_INT_PHASER_TO_IO_OCLK" + "PCIE_IMUX8_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT8" ], [ - "IOI_LOGIC_OUTS5_1", - "TERM_INT_LOGIC_OUTS_L_B5" + "PCIE_IMUX9_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT9" ], [ - "IOI_LOGIC_OUTS12_1", - "TERM_INT_LOGIC_OUTS_L_B12" + "PCIE_IMUX10_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT10" ], [ - "IOI_IMUX43_1", - "TERM_INT_IMUX43" + "PCIE_IMUX11_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT11" ], [ - "IOI_FAN7_1", - "TERM_INT_FAN7" + "PCIE_IMUX12_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT12" ], [ - "IOI_IMUX1_1", - "TERM_INT_IMUX1" + "PCIE_IMUX13_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT13" ], [ - "IOI_IMUX47_1", - "TERM_INT_IMUX47" + "PCIE_IMUX14_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT14" ], [ - "IOI_IMUX22_1", - "TERM_INT_IMUX22" + "PCIE_IMUX15_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT15" ], [ - "IOI_CTRL1_1", - "TERM_INT_CTRL1" + "PCIE_IMUX16_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT16" ], [ - "IOI_PHASER_TO_IO_OCLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" + "PCIE_IMUX17_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT17" ], [ - "IOI_IMUX42_1", - "TERM_INT_IMUX42" + "PCIE_IMUX18_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT18" ], [ - "IOI_IMUX14_1", - "TERM_INT_IMUX14" + "PCIE_IMUX19_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT19" ], [ - "IOI_FAN0_1", - "TERM_INT_FAN0" + "PCIE_IMUX20_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT20" ], [ - "IOI_IMUX35_1", - "TERM_INT_IMUX35" + "PCIE_IMUX21_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT21" ], [ - "IOI_IMUX6_1", - "TERM_INT_IMUX6" + "PCIE_IMUX22_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT22" ], [ - "IOI_IMUX20_1", - "TERM_INT_IMUX20" + "PCIE_IMUX23_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT23" ], [ - "IOI_IMUX3_1", - "TERM_INT_IMUX3" + "PCIE_IMUX24_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT24" ], [ - "IOI_PHASER_TO_IO_ICLK_0", - "L_TERM_INT_PHASER_TO_IO_ICLK" + "PCIE_IMUX25_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT25" ], [ - "IOI_IMUX25_1", - "TERM_INT_IMUX25" + "PCIE_IMUX26_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT26" ], [ - "IOI_CTRL0_1", - "TERM_INT_CTRL0" + "PCIE_IMUX27_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT27" ], [ - "IOI_BYP4_1", - "TERM_INT_BYP4" + "PCIE_IMUX28_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT28" ], [ - "IOI_IMUX30_1", - "TERM_INT_IMUX30" + "PCIE_IMUX29_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT29" ], [ - "IOI_LOGIC_OUTS16_1", - "TERM_INT_LOGIC_OUTS_L_B16" + "PCIE_IMUX30_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT30" ], [ - "IOI_LOGIC_OUTS23_1", - "TERM_INT_LOGIC_OUTS_L_B23" + "PCIE_IMUX31_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT31" ], [ - "IOI_BYP5_1", - "TERM_INT_BYP5" + "PCIE_IMUX32_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT32" ], [ - "IOI_CLK1_1", - "TERM_INT_CLK1" + "PCIE_IMUX33_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT33" ], [ - "IOI_IMUX15_1", - "TERM_INT_IMUX15" + "PCIE_IMUX34_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT34" ], [ - "IOI_IMUX13_1", - "TERM_INT_IMUX13" + "PCIE_IMUX35_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT35" ], [ - "IOI_IMUX16_1", - "TERM_INT_IMUX16" + "PCIE_IMUX36_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT36" ], [ - "IOI_IMUX33_1", - "TERM_INT_IMUX33" + "PCIE_IMUX37_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT37" ], [ - "IOI_IMUX29_1", - "TERM_INT_IMUX29" + "PCIE_IMUX38_R_6", + "PCIE_INT_INTERFACE_IMUX_OUT38" ], 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"PCIE_LH3_6", + "INT_INTERFACE_LH3" + ], + [ + "PCIE_LH4_6", + "INT_INTERFACE_LH4" + ], + [ + "PCIE_LH5_6", + "INT_INTERFACE_LH5" + ], + [ + "PCIE_LH6_6", + "INT_INTERFACE_LH6" + ], + [ + "PCIE_LH7_6", + "INT_INTERFACE_LH7" + ], + [ + "PCIE_LH8_6", + "INT_INTERFACE_LH8" + ], + [ + "PCIE_LH9_6", + "INT_INTERFACE_LH9" + ], + [ + "PCIE_LH10_6", + "INT_INTERFACE_LH10" + ], + [ + "PCIE_LH11_6", + "INT_INTERFACE_LH11" + ], + [ + "PCIE_LH12_6", + "INT_INTERFACE_LH12" + ], + [ + "PCIE_LOGIC_OUTS_B0_R_6", + "INT_INTERFACE_LOGIC_OUTS_B0" + ], + [ + "PCIE_LOGIC_OUTS_B1_R_6", + "INT_INTERFACE_LOGIC_OUTS_B1" + ], + [ + "PCIE_LOGIC_OUTS_B2_R_6", + "INT_INTERFACE_LOGIC_OUTS_B2" + ], + [ + "PCIE_LOGIC_OUTS_B3_R_6", + "INT_INTERFACE_LOGIC_OUTS_B3" + ], + [ + "PCIE_LOGIC_OUTS_B4_R_6", + "INT_INTERFACE_LOGIC_OUTS_B4" + ], + [ + "PCIE_LOGIC_OUTS_B5_R_6", + "INT_INTERFACE_LOGIC_OUTS_B5" + ], + [ + "PCIE_LOGIC_OUTS_B6_R_6", + "INT_INTERFACE_LOGIC_OUTS_B6" + ], + [ + "PCIE_LOGIC_OUTS_B7_R_6", + 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"PCIE_WW4C0_6", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_WW4C1_6", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WW4C2_6", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_WW4C3_6", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_WW4END0_6", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WW4END1_6", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_WW4END2_6", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WW4END3_6", + "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ - 1, - -5 + -1, + 5 ], "tile_types": [ - "CLK_PMV", - "VBRK" + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" ], "wire_pairs": [ [ - "CLK_PMV_WW4B0_5", - "VBRK_WW4B0" + "PCIE_BYP0_R_5", + "INT_INTERFACE_BYP0" ], [ - "CLK_PMV_WR1END0_5", - "VBRK_WR1END0" + "PCIE_BYP1_R_5", + "INT_INTERFACE_BYP1" ], [ - "CLK_PMV_LH10_5", - "VBRK_LH10" + "PCIE_BYP2_R_5", + "INT_INTERFACE_BYP2" ], [ - "CLK_PMV_NW2A0_5", - "VBRK_NW2A0" + "PCIE_BYP3_R_5", + "INT_INTERFACE_BYP3" ], [ - "CLK_PMV_NW4END0_5", - "VBRK_NW4END0" + "PCIE_BYP4_R_5", + "INT_INTERFACE_BYP4" ], [ - "CLK_PMV_NE4BEG1_5", - "VBRK_NE4BEG1" + "PCIE_BYP5_R_5", + "INT_INTERFACE_BYP5" ], [ - "CLK_PMV_SE4BEG1_5", - "VBRK_SE4BEG1" + "PCIE_BYP6_R_5", + "INT_INTERFACE_BYP6" ], [ - "CLK_PMV_SW4END2_5", - "VBRK_SW4END2" + "PCIE_BYP7_R_5", + "INT_INTERFACE_BYP7" ], [ - "CLK_PMV_SE2A3_5", - "VBRK_SE2A3" + "PCIE_CLK0_R_5", + "INT_INTERFACE_CLK0" ], [ - "CLK_PMV_EE2BEG3_5", - "VBRK_EE2BEG3" + "PCIE_CLK1_R_5", + "INT_INTERFACE_CLK1" ], [ - "CLK_PMV_NW2A2_5", - "VBRK_NW2A2" + "PCIE_CTRL0_R_5", + "INT_INTERFACE_CTRL0" ], [ - "CLK_PMV_WW4END0_5", - "VBRK_WW4END0" + "PCIE_CTRL1_R_5", + "INT_INTERFACE_CTRL1" ], [ - "CLK_PMV_SE4C1_5", - "VBRK_SE4C1" + "PCIE_EE2A0_5", + "INT_INTERFACE_EE2A0" ], [ - "CLK_PMV_EE4BEG0_5", - "VBRK_EE4BEG0" + "PCIE_EE2A1_5", + "INT_INTERFACE_EE2A1" ], [ - "CLK_PMV_NE4C0_5", - "VBRK_NE4C0" + "PCIE_EE2A2_5", + "INT_INTERFACE_EE2A2" ], [ - "CLK_PMV_SW4A0_5", - "VBRK_SW4A0" + "PCIE_EE2A3_5", + "INT_INTERFACE_EE2A3" ], [ - "CLK_PMV_EL1BEG3_5", - "VBRK_EL1BEG3" + "PCIE_EE2BEG0_5", + "INT_INTERFACE_EE2BEG0" ], [ - "CLK_PMV_SW2A2_5", - "VBRK_SW2A2" + "PCIE_EE2BEG1_5", + "INT_INTERFACE_EE2BEG1" ], [ - "CLK_PMV_EE4C2_5", - "VBRK_EE4C2" + "PCIE_EE2BEG2_5", + "INT_INTERFACE_EE2BEG2" ], [ - "CLK_PMV_NE4BEG3_5", - "VBRK_NE4BEG3" + "PCIE_EE2BEG3_5", + "INT_INTERFACE_EE2BEG3" ], [ - "CLK_PMV_EE2BEG0_5", - "VBRK_EE2BEG0" + "PCIE_EE4A0_5", + "INT_INTERFACE_EE4A0" ], [ - "CLK_PMV_NE4C1_5", - "VBRK_NE4C1" + "PCIE_EE4A1_5", + "INT_INTERFACE_EE4A1" ], [ - "CLK_PMV_WL1END3_5", - "VBRK_WL1END3" + "PCIE_EE4A2_5", + "INT_INTERFACE_EE4A2" ], [ - "CLK_PMV_NE4BEG0_5", - "VBRK_NE4BEG0" + "PCIE_EE4A3_5", + "INT_INTERFACE_EE4A3" ], [ - "CLK_PMV_WR1END1_5", - "VBRK_WR1END1" + "PCIE_EE4B0_5", + "INT_INTERFACE_EE4B0" ], [ - "CLK_PMV_WW2END3_5", - "VBRK_WW2END3" + "PCIE_EE4B1_5", + "INT_INTERFACE_EE4B1" ], [ - "CLK_PMV_NW4END2_5", - "VBRK_NW4END2" + "PCIE_EE4B2_5", + "INT_INTERFACE_EE4B2" ], [ - "CLK_PMV_WW4B3_5", - "VBRK_WW4B3" + "PCIE_EE4B3_5", + "INT_INTERFACE_EE4B3" ], [ - "CLK_PMV_ER1BEG1_5", - "VBRK_ER1BEG1" + "PCIE_EE4BEG0_5", + "INT_INTERFACE_EE4BEG0" ], [ - "CLK_PMV_EE4B3_5", - "VBRK_EE4B3" + "PCIE_EE4BEG1_5", + "INT_INTERFACE_EE4BEG1" ], [ - "CLK_PMV_LH3_5", - "VBRK_LH3" + "PCIE_EE4BEG2_5", + "INT_INTERFACE_EE4BEG2" ], [ - "CLK_PMV_LH9_5", - "VBRK_LH9" + "PCIE_EE4BEG3_5", + "INT_INTERFACE_EE4BEG3" ], [ - "CLK_PMV_EL1BEG0_5", - "VBRK_EL1BEG0" + "PCIE_EE4C0_5", + "INT_INTERFACE_EE4C0" ], [ - "CLK_PMV_SW2A3_5", - "VBRK_SW2A3" + "PCIE_EE4C1_5", + "INT_INTERFACE_EE4C1" ], [ - "CLK_PMV_LH12_5", - "VBRK_LH12" + "PCIE_EE4C2_5", + "INT_INTERFACE_EE4C2" ], [ - "CLK_PMV_EE2A2_5", - "VBRK_EE2A2" + "PCIE_EE4C3_5", + "INT_INTERFACE_EE4C3" ], [ - "CLK_PMV_NE2A0_5", - "VBRK_NE2A0" + "PCIE_EL1BEG0_5", + "INT_INTERFACE_EL1BEG0" ], [ - "CLK_PMV_WW4C0_5", - "VBRK_WW4C0" + "PCIE_EL1BEG1_5", + "INT_INTERFACE_EL1BEG1" ], [ - "CLK_PMV_NW4END3_5", - "VBRK_NW4END3" + "PCIE_EL1BEG2_5", + "INT_INTERFACE_EL1BEG2" ], [ - "CLK_PMV_SE2A2_5", - "VBRK_SE2A2" + "PCIE_EL1BEG3_5", + "INT_INTERFACE_EL1BEG3" ], [ - "CLK_PMV_SE4BEG0_5", - "VBRK_SE4BEG0" + "PCIE_ER1BEG0_5", + "INT_INTERFACE_ER1BEG0" ], [ - "CLK_PMV_WW4A2_5", - "VBRK_WW4A2" + "PCIE_ER1BEG1_5", + "INT_INTERFACE_ER1BEG1" ], [ - "CLK_PMV_LH6_5", - "VBRK_LH6" + "PCIE_ER1BEG2_5", + "INT_INTERFACE_ER1BEG2" ], [ - "CLK_PMV_WW2END0_5", - "VBRK_WW2END0" + "PCIE_ER1BEG3_5", + "INT_INTERFACE_ER1BEG3" ], [ - "CLK_PMV_SE2A1_5", - "VBRK_SE2A1" + "PCIE_FAN0_R_5", + "INT_INTERFACE_FAN0" ], [ - "CLK_PMV_EE4A0_5", - "VBRK_EE4A0" + "PCIE_FAN1_R_5", + "INT_INTERFACE_FAN1" ], [ - "CLK_PMV_LH11_5", - "VBRK_LH11" + "PCIE_FAN2_R_5", + "INT_INTERFACE_FAN2" ], [ - "CLK_PMV_EE4BEG3_5", - "VBRK_EE4BEG3" + "PCIE_FAN3_R_5", + "INT_INTERFACE_FAN3" ], [ - "CLK_PMV_EE4A3_5", - "VBRK_EE4A3" + "PCIE_FAN4_R_5", + "INT_INTERFACE_FAN4" ], [ - "CLK_PMV_LH1_5", - "VBRK_LH1" + "PCIE_FAN5_R_5", + "INT_INTERFACE_FAN5" ], [ - "CLK_PMV_WW4B1_5", - "VBRK_WW4B1" + "PCIE_FAN6_R_5", + "INT_INTERFACE_FAN6" ], [ - "CLK_PMV_NW4A2_5", - "VBRK_NW4A2" + "PCIE_FAN7_R_5", + "INT_INTERFACE_FAN7" ], [ - "CLK_PMV_SE2A0_5", - "VBRK_SE2A0" + "PCIE_IMUX0_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT0" ], [ - "CLK_PMV_EE4BEG1_5", - "VBRK_EE4BEG1" + "PCIE_IMUX1_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT1" ], [ - "CLK_PMV_SW4END0_5", - "VBRK_SW4END0" + "PCIE_IMUX2_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT2" ], [ - "CLK_PMV_ER1BEG0_5", - "VBRK_ER1BEG0" + "PCIE_IMUX3_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT3" ], [ - "CLK_PMV_WL1END0_5", - "VBRK_WL1END0" + "PCIE_IMUX4_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT4" ], [ - "CLK_PMV_NW4END1_5", - "VBRK_NW4END1" + "PCIE_IMUX5_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT5" ], [ - "CLK_PMV_EE2BEG1_5", - "VBRK_EE2BEG1" + "PCIE_IMUX6_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT6" ], [ - "CLK_PMV_SW4A2_5", - "VBRK_SW4A2" + "PCIE_IMUX7_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT7" ], [ - "CLK_PMV_SW2A0_5", - "VBRK_SW2A0" + "PCIE_IMUX8_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT8" ], [ - "CLK_PMV_WW4C2_5", - "VBRK_WW4C2" + "PCIE_IMUX9_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT9" ], [ - "CLK_PMV_WW4END2_5", - "VBRK_WW4END2" + "PCIE_IMUX10_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT10" ], [ - "CLK_PMV_SE4C0_5", - "VBRK_SE4C0" + "PCIE_IMUX11_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT11" ], [ - "CLK_PMV_SE4BEG3_5", - "VBRK_SE4BEG3" + "PCIE_IMUX12_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT12" ], [ - "CLK_PMV_EE4A1_5", - "VBRK_EE4A1" + "PCIE_IMUX13_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT13" ], [ - "CLK_PMV_SE4C3_5", - "VBRK_SE4C3" + "PCIE_IMUX14_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT14" ], [ - "CLK_PMV_NW4A3_5", - "VBRK_NW4A3" + "PCIE_IMUX15_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT15" ], [ - "CLK_PMV_EE4C0_5", - "VBRK_EE4C0" + "PCIE_IMUX16_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT16" ], [ - "CLK_PMV_WW4END3_5", - "VBRK_WW4END3" + "PCIE_IMUX17_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT17" ], [ - "CLK_PMV_SW4A3_5", - "VBRK_SW4A3" + "PCIE_IMUX18_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT18" ], [ - "CLK_PMV_LH8_5", - "VBRK_LH8" + "PCIE_IMUX19_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT19" ], [ - "CLK_PMV_NE2A2_5", - "VBRK_NE2A2" + "PCIE_IMUX20_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT20" ], [ - "CLK_PMV_WR1END2_5", - "VBRK_WR1END2" + "PCIE_IMUX21_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT21" ], [ - "CLK_PMV_WW2A1_5", - "VBRK_WW2A1" + "PCIE_IMUX22_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT22" ], [ - "CLK_PMV_EE4C1_5", - "VBRK_EE4C1" + "PCIE_IMUX23_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT23" ], [ - "CLK_PMV_WW4END1_5", - "VBRK_WW4END1" + "PCIE_IMUX24_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT24" ], [ - "CLK_PMV_LH7_5", - "VBRK_LH7" + "PCIE_IMUX25_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT25" ], [ - "CLK_PMV_EE4A2_5", - "VBRK_EE4A2" + "PCIE_IMUX26_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT26" ], [ - "CLK_PMV_ER1BEG2_5", - "VBRK_ER1BEG2" + "PCIE_IMUX27_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT27" ], [ - "CLK_PMV_WW2END2_5", - "VBRK_WW2END2" + "PCIE_IMUX28_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT28" ], [ - "CLK_PMV_EE2A0_5", - "VBRK_EE2A0" + "PCIE_IMUX29_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT29" ], [ - "CLK_PMV_EE2A3_5", - "VBRK_EE2A3" + "PCIE_IMUX30_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT30" ], [ - "CLK_PMV_WW4A3_5", - "VBRK_WW4A3" + "PCIE_IMUX31_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT31" ], [ - "CLK_PMV_NE4C2_5", - "VBRK_NE4C2" + "PCIE_IMUX32_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT32" ], [ - "CLK_PMV_WW4B2_5", - "VBRK_WW4B2" + "PCIE_IMUX33_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT33" ], [ - "CLK_PMV_EE4B0_5", - "VBRK_EE4B0" + "PCIE_IMUX34_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT34" ], [ - "CLK_PMV_WL1END1_5", - "VBRK_WL1END1" + "PCIE_IMUX35_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT35" ], [ - "CLK_PMV_SW2A1_5", - "VBRK_SW2A1" + "PCIE_IMUX36_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT36" ], [ - "CLK_PMV_SW4END1_5", - "VBRK_SW4END1" + "PCIE_IMUX37_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT37" ], [ - "CLK_PMV_EE4B2_5", - "VBRK_EE4B2" + "PCIE_IMUX38_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT38" ], [ - "CLK_PMV_NE2A3_5", - "VBRK_NE2A3" + "PCIE_IMUX39_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT39" ], [ - "CLK_PMV_EE2A1_5", - "VBRK_EE2A1" + "PCIE_IMUX40_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT40" ], [ - "CLK_PMV_WW2END1_5", - "VBRK_WW2END1" + "PCIE_IMUX41_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT41" ], [ - "CLK_PMV_WW4A0_5", - "VBRK_WW4A0" + "PCIE_IMUX42_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT42" ], [ - "CLK_PMV_WW2A3_5", - "VBRK_WW2A3" + "PCIE_IMUX43_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT43" ], [ - "CLK_PMV_NW2A1_5", - "VBRK_NW2A1" + "PCIE_IMUX44_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT44" ], [ - "CLK_PMV_WW4C3_5", - "VBRK_WW4C3" + "PCIE_IMUX45_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT45" ], [ - "CLK_PMV_NW2A3_5", - "VBRK_NW2A3" + "PCIE_IMUX46_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT46" ], [ - "CLK_PMV_LH2_5", - "VBRK_LH2" + "PCIE_IMUX47_R_5", + "PCIE_INT_INTERFACE_IMUX_OUT47" ], [ - "CLK_PMV_EE4C3_5", - "VBRK_EE4C3" + "PCIE_LH1_5", + "INT_INTERFACE_LH1" ], [ - "CLK_PMV_EE2BEG2_5", - "VBRK_EE2BEG2" + "PCIE_LH2_5", + "INT_INTERFACE_LH2" ], [ - "CLK_PMV_LH4_5", - "VBRK_LH4" + "PCIE_LH3_5", + "INT_INTERFACE_LH3" ], [ - "CLK_PMV_LH5_5", - "VBRK_LH5" + "PCIE_LH4_5", + "INT_INTERFACE_LH4" ], [ - "CLK_PMV_SE4BEG2_5", - "VBRK_SE4BEG2" + "PCIE_LH5_5", + "INT_INTERFACE_LH5" ], [ - "CLK_PMV_WW4C1_5", - "VBRK_WW4C1" + "PCIE_LH6_5", + "INT_INTERFACE_LH6" ], [ - "CLK_PMV_SW4END3_5", - "VBRK_SW4END3" + "PCIE_LH7_5", + "INT_INTERFACE_LH7" ], [ - "CLK_PMV_EE4BEG2_5", - "VBRK_EE4BEG2" + "PCIE_LH8_5", + "INT_INTERFACE_LH8" ], [ - "CLK_PMV_WW2A0_5", - "VBRK_WW2A0" + "PCIE_LH9_5", + "INT_INTERFACE_LH9" ], [ - "CLK_PMV_NE4BEG2_5", - "VBRK_NE4BEG2" + "PCIE_LH10_5", + "INT_INTERFACE_LH10" ], [ - "CLK_PMV_ER1BEG3_5", - "VBRK_ER1BEG3" + "PCIE_LH11_5", + "INT_INTERFACE_LH11" ], [ - "CLK_PMV_WW4A1_5", - "VBRK_WW4A1" + "PCIE_LH12_5", + "INT_INTERFACE_LH12" ], [ - "CLK_PMV_WL1END2_5", - "VBRK_WL1END2" + "PCIE_LOGIC_OUTS_B0_R_5", + "INT_INTERFACE_LOGIC_OUTS_B0" ], [ - "CLK_PMV_WW2A2_5", - "VBRK_WW2A2" + "PCIE_LOGIC_OUTS_B1_R_5", + "INT_INTERFACE_LOGIC_OUTS_B1" ], [ - "CLK_PMV_WR1END3_5", - "VBRK_WR1END3" + "PCIE_LOGIC_OUTS_B2_R_5", + "INT_INTERFACE_LOGIC_OUTS_B2" ], [ - "CLK_PMV_NW4A1_5", - "VBRK_NW4A1" + "PCIE_LOGIC_OUTS_B3_R_5", + "INT_INTERFACE_LOGIC_OUTS_B3" ], [ - "CLK_PMV_EE4B1_5", - "VBRK_EE4B1" + "PCIE_LOGIC_OUTS_B4_R_5", + "INT_INTERFACE_LOGIC_OUTS_B4" ], [ - "CLK_PMV_EL1BEG2_5", - "VBRK_EL1BEG2" + "PCIE_LOGIC_OUTS_B5_R_5", + "INT_INTERFACE_LOGIC_OUTS_B5" ], [ - "CLK_PMV_SE4C2_5", - "VBRK_SE4C2" + "PCIE_LOGIC_OUTS_B6_R_5", + "INT_INTERFACE_LOGIC_OUTS_B6" ], [ - "CLK_PMV_NW4A0_5", - "VBRK_NW4A0" + "PCIE_LOGIC_OUTS_B7_R_5", + "INT_INTERFACE_LOGIC_OUTS_B7" ], [ - "CLK_PMV_NE4C3_5", - "VBRK_NE4C3" + "PCIE_LOGIC_OUTS_B8_R_5", + "INT_INTERFACE_LOGIC_OUTS_B8" ], [ - "CLK_PMV_NE2A1_5", - "VBRK_NE2A1" + "PCIE_LOGIC_OUTS_B9_R_5", + "INT_INTERFACE_LOGIC_OUTS_B9" ], [ - "CLK_PMV_SW4A1_5", - "VBRK_SW4A1" + "PCIE_LOGIC_OUTS_B10_R_5", + "INT_INTERFACE_LOGIC_OUTS_B10" ], [ - "CLK_PMV_EL1BEG1_5", - "VBRK_EL1BEG1" + "PCIE_LOGIC_OUTS_B11_R_5", + "INT_INTERFACE_LOGIC_OUTS_B11" + ], + [ + "PCIE_LOGIC_OUTS_B12_R_5", + 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"INT_INTERFACE_WR1END3" + ], + [ + "PCIE_WW2A0_1", + "INT_INTERFACE_WW2A0" + ], + [ + "PCIE_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "PCIE_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "PCIE_WW2A3_1", + "INT_INTERFACE_WW2A3" + ], + [ + "PCIE_WW2END0_1", + "INT_INTERFACE_WW2END0" + ], + [ + "PCIE_WW2END1_1", + "INT_INTERFACE_WW2END1" + ], + [ + "PCIE_WW2END2_1", + "INT_INTERFACE_WW2END2" + ], + [ + "PCIE_WW2END3_1", + "INT_INTERFACE_WW2END3" + ], + [ + "PCIE_WW4A0_1", + "INT_INTERFACE_WW4A0" + ], + [ + "PCIE_WW4A1_1", + "INT_INTERFACE_WW4A1" + ], + [ + "PCIE_WW4A2_1", + "INT_INTERFACE_WW4A2" + ], + [ + "PCIE_WW4A3_1", + "INT_INTERFACE_WW4A3" + ], + [ + "PCIE_WW4B0_1", + "INT_INTERFACE_WW4B0" + ], + [ + "PCIE_WW4B1_1", + "INT_INTERFACE_WW4B1" + ], + [ + "PCIE_WW4B2_1", + "INT_INTERFACE_WW4B2" + ], + [ + "PCIE_WW4B3_1", + "INT_INTERFACE_WW4B3" + ], + [ + "PCIE_WW4C0_1", + "INT_INTERFACE_WW4C0" + ], + [ + "PCIE_WW4C1_1", + "INT_INTERFACE_WW4C1" + ], + [ + "PCIE_WW4C2_1", + "INT_INTERFACE_WW4C2" + ], + [ + "PCIE_WW4C3_1", + "INT_INTERFACE_WW4C3" + ], + [ + "PCIE_WW4END0_1", + "INT_INTERFACE_WW4END0" + ], + [ + "PCIE_WW4END1_1", + "INT_INTERFACE_WW4END1" + ], + [ + "PCIE_WW4END2_1", + "INT_INTERFACE_WW4END2" + ], + [ + "PCIE_WW4END3_1", + "INT_INTERFACE_WW4END3" ] ] }, @@ -58509,27453 +461665,873 @@ 10 ], "tile_types": [ - "CFG_CENTER_BOT", - "INT_FEEDTHRU_2" + "PCIE_BOT", + "PCIE_INT_INTERFACE_R" ], "wire_pairs": [ [ - "CFG_CENTER_WW2END2_0", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_SW4END1_0", - "INT_FEEDTHRU_2_SW4END1" - ], - [ - "CFG_CENTER_LH2_0", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_LH3_0", - "INT_FEEDTHRU_2_LH3" - ], - [ - "CFG_CENTER_WR1END0_0", - "INT_FEEDTHRU_2_WR1END0" - ], - [ - "CFG_CENTER_WR1END1_0", - "INT_FEEDTHRU_2_WR1END1" - ], - [ - "CFG_CENTER_LH12_0", - "INT_FEEDTHRU_2_LH12" - ], - [ - "CFG_CENTER_EL1BEG1_0", - "INT_FEEDTHRU_2_EL1BEG1" - ], - [ - "CFG_CENTER_WW2END1_0", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - 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"CLBLM_EE4A0", - "DSP_EE4A0_3" - ], - [ - "CLBLM_WW4B1", - "DSP_WW4B1_3" - ], - [ - "CLBLM_NE4C0", - "DSP_NE4C0_3" - ], - [ - "CLBLM_SE4C1", - "DSP_SE4C1_3" - ], - [ - "CLBLM_LH9", - "DSP_LH9_3" - ], - [ - "CLBLM_EE2A1", - "DSP_EE2A1_3" - ], - [ - "CLBLM_ER1BEG1", - "DSP_ER1BEG1_3" - ], - [ - "CLBLM_NE4C1", - "DSP_NE4C1_3" - ], - [ - "CLBLM_SW4A2", - "DSP_SW4A2_3" - ], - [ - "CLBLM_WW4END1", - "DSP_WW4END1_3" - ], - [ - "CLBLM_WL1END0", - "DSP_WL1END0_3" - ], - [ - "CLBLM_NW4END1", - "DSP_NW4END1_3" - ], - [ - "CLBLM_NW2A1", - "DSP_NW2A1_3" - ], - [ - "CLBLM_NE2A1", - "DSP_NE2A1_3" - ], - [ - "CLBLM_WW2END1", - "DSP_WW2END1_3" - ], - [ - "CLBLM_WW4C1", - "DSP_WW4C1_3" - ], - [ - "CLBLM_NE2A2", - "DSP_NE2A2_3" - ], - [ - "CLBLM_NW4END2", - "DSP_NW4END2_3" - ], - [ - "CLBLM_SE4BEG2", - "DSP_SE4BEG2_3" - ], - [ - "CLBLM_EE4C3", - "DSP_EE4C3_3" - ], - [ - "CLBLM_SE4BEG3", - "DSP_SE4BEG3_3" - ], - [ - "CLBLM_WW4END2", - "DSP_WW4END2_3" - ], - [ - "CLBLM_NW4A3", - "DSP_NW4A3_3" - ], - [ - "CLBLM_LH7", - "DSP_LH7_3" - ], - [ - "CLBLM_EE4BEG1", - "DSP_EE4BEG1_3" - ], - [ - "CLBLM_WL1END3", - "DSP_WL1END3_3" - ], - [ - "CLBLM_MONITOR_N", - "DSP_MONITOR_N_3" - ], - [ - "CLBLM_SE4C2", - "DSP_SE4C2_3" - ], - [ - "CLBLM_EE2A3", - "DSP_EE2A3_3" - ], - [ - "CLBLM_MONITOR_P", - "DSP_MONITOR_P_3" - ], - [ - "CLBLM_WW4A3", - "DSP_WW4A3_3" - ], - [ - "CLBLM_NW4A1", - "DSP_NW4A1_3" - ], - [ - "CLBLM_EE2BEG2", - "DSP_EE2BEG2_3" - ], - [ - "CLBLM_NE2A0", - "DSP_NE2A0_3" - ], - [ - "CLBLM_SW4A1", - "DSP_SW4A1_3" - ], - [ - "CLBLM_WR1END0", - "DSP_WR1END0_3" - ], - [ - "CLBLM_NW2A2", - "DSP_NW2A2_3" - ], - [ - "CLBLM_NW2A0", - "DSP_NW2A0_3" - ], - [ - "CLBLM_EL1BEG1", - "DSP_EL1BEG1_3" - ], - [ - "CLBLM_WW2END3", - "DSP_WW2END3_3" - ], - [ - "CLBLM_WW2A3", - "DSP_WW2A3_3" - ], - [ - "CLBLM_NE2A3", - "DSP_NE2A3_3" - ], - [ - "CLBLM_SW2A1", - "DSP_SW2A1_3" - ], - [ - "CLBLM_SE4BEG0", - "DSP_SE4BEG0_3" - ], - [ - "CLBLM_NW4A2", - "DSP_NW4A2_3" - ], - [ - "CLBLM_WW4END3", - "DSP_WW4END3_3" - ], - [ - "CLBLM_LH1", - "DSP_LH1_3" - ], - [ - "CLBLM_SW2A0", - "DSP_SW2A0_3" - ], - [ - "CLBLM_WW4A0", - "DSP_WW4A0_3" - ], - [ - "CLBLM_ER1BEG0", - "DSP_ER1BEG0_3" - ], - [ - "CLBLM_EE2A0", - "DSP_EE2A0_3" - ], - [ - "CLBLM_SE2A1", - "DSP_SE2A1_3" - ], - [ - "CLBLM_LH10", - "DSP_LH10_3" - ], - [ - "CLBLM_EE4C0", - "DSP_EE4C0_3" - ], - [ - "CLBLM_EE4A1", - "DSP_EE4A1_3" - ], - [ - "CLBLM_SE2A3", - "DSP_SE2A3_3" - ] - ] - }, - { - "grid_deltas": [ - 0, - 5 - ], - "tile_types": [ - "CLK_FEED", - "CLK_HROW_BOT_R" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_HROW_BOT_R_CK_BUFG_CASCO4" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_HROW_BOT_R_CK_BUFG_CASCO7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_HROW_BOT_R_CK_BUFG_CASCO19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_HROW_BOT_R_CK_BUFG_CASCO5" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_HROW_BOT_R_CK_BUFG_CASCO29" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_HROW_BOT_R_CK_BUFG_CASCO3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_HROW_BOT_R_CK_BUFG_CASCO31" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_HROW_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_HROW_BOT_R_CK_BUFG_CASCO25" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_HROW_BOT_R_CK_BUFG_CASCO8" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_HROW_BOT_R_CK_BUFG_CASCO0" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_HROW_BOT_R_CK_BUFG_CASCO12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_HROW_BOT_R_CK_BUFG_CASCO22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_HROW_BOT_R_CK_BUFG_CASCO17" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_HROW_BOT_R_CK_BUFG_CASCO13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_HROW_BOT_R_CK_BUFG_CASCO21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_HROW_BOT_R_CK_BUFG_CASCO9" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_HROW_BOT_R_CK_BUFG_CASCO1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_HROW_BOT_R_CK_BUFG_CASCO24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_HROW_BOT_R_CK_BUFG_CASCO14" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_HROW_BOT_R_CK_BUFG_CASCO16" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_HROW_BOT_R_CK_BUFG_CASCO26" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_HROW_BOT_R_CK_BUFG_CASCO10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_HROW_BOT_R_CK_BUFG_CASCO6" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_HROW_BOT_R_CK_BUFG_CASCO18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_HROW_BOT_R_CK_BUFG_CASCO20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_HROW_BOT_R_CK_BUFG_CASCO23" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_HROW_BOT_R_CK_BUFG_CASCO11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_HROW_BOT_R_CK_BUFG_CASCO15" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_HROW_BOT_R_CK_BUFG_CASCO30" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_HROW_BOT_R_CK_BUFG_CASCO27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_HROW_BOT_R_CK_BUFG_CASCO2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_HROW_BOT_R_CK_BUFG_CASCO28" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK29" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "BRAM_INT_INTERFACE_L", - "INT_L" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_NE4BEG0", - "NE6A0" - ], - [ - "INT_INTERFACE_BRAM_IMUX45", - "IMUX_L45" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "IMUX_L31" - ], - [ - "INT_INTERFACE_WW2A3", - "WW2BEG3" - ], - [ - "INT_INTERFACE_WW4C3", - "WW4B3" - ], - [ - "INT_INTERFACE_BRAM_IMUX20", - "IMUX_L20" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "IMUX_L38" - ], - [ - "INT_INTERFACE_EE4B0", - "EE4C0" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "IMUX_L5" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "IMUX_L46" - ], - [ - "INT_INTERFACE_WW4B0", - "WW4A0" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "IMUX_L17" - ], - [ - "INT_INTERFACE_SW2A2", - "SW2A2" - ], - [ - "INT_INTERFACE_EL1BEG3", - "EL1END3" - ], - [ - "INT_INTERFACE_EE2BEG1", - "EE2A1" - ], - [ - "INT_INTERFACE_SE4BEG3", - "SE6A3" - ], - [ - "INT_INTERFACE_NE2A1", - "NE2END1" - ], - [ - "INT_INTERFACE_MONITOR_N", - "MONITOR_N" - ], - [ - "INT_INTERFACE_LH3", - "LH2" - ], - [ - "INT_INTERFACE_EE2BEG3", - "EE2A3" - ], - [ - "INT_INTERFACE_WW4END0", - "WW4C0" - ], - [ - "INT_INTERFACE_WW4A0", - "WW4BEG0" - ], - [ - "INT_INTERFACE_CLK1", - "CLK_L1" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "IMUX_L41" - ], - [ - "INT_INTERFACE_WW2A1", - "WW2BEG1" - ], - [ - "INT_INTERFACE_NE4C0", - "NE6END0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L5", - "LOGIC_OUTS_L5" - ], - [ - "INT_INTERFACE_EE4A2", - "EE4B2" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "IMUX_L44" - ], - [ - "INT_INTERFACE_SW2A0", - "SW2A0" - ], - [ - "INT_INTERFACE_ER1BEG2", - "ER1END2" - ], - [ - "INT_INTERFACE_NE2A0", - "NE2END0" - ], - [ - "INT_INTERFACE_BYP2", - "BYP_L2" - ], - [ - "INT_INTERFACE_WW4A2", - "WW4BEG2" - ], - [ - "INT_INTERFACE_EE4A1", - "EE4B1" - ], - [ - "INT_INTERFACE_EE4B2", - "EE4C2" - ], - [ - "INT_INTERFACE_NW4END1", - "NW6E1" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "IMUX_L6" - ], - [ - "INT_INTERFACE_BRAM_IMUX33", - "IMUX_L33" - ], - [ - "INT_INTERFACE_NW4A2", - "NW6BEG2" - ], - [ - "INT_INTERFACE_NE4C2", - "NE6END2" - ], - [ - "INT_INTERFACE_LH11", - "LH10" - ], - [ - "INT_INTERFACE_EE2A2", - "EE2END2" - ], - [ - "INT_INTERFACE_LH2", - "LH1" - ], - [ - "INT_INTERFACE_SE4C1", - "SE6END1" - ], - [ - "INT_INTERFACE_CTRL0", - "CTRL_L0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L8", - "LOGIC_OUTS_L8" - ], - [ - "INT_INTERFACE_ER1BEG1", - "ER1END1" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "IMUX_L15" - ], - [ - "INT_INTERFACE_BRAM_IMUX42", - "IMUX_L42" - ], - [ - "INT_INTERFACE_CTRL1", - "CTRL_L1" - ], - [ - "INT_INTERFACE_SE4C0", - "SE6END0" - ], - [ - "INT_INTERFACE_SE4BEG0", - "SE6A0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L13", - "LOGIC_OUTS_L13" - ], - [ - "INT_INTERFACE_EE4BEG3", - "EE4A3" - ], - [ - "INT_INTERFACE_BYP3", - "BYP_L3" - ], - [ - "INT_INTERFACE_EL1BEG1", - "EL1END1" - ], - [ - "INT_INTERFACE_WW2A0", - "WW2BEG0" - ], - [ - "INT_INTERFACE_LH9", - "LH8" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L0", - "LOGIC_OUTS_L0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L12", - "LOGIC_OUTS_L12" - ], - [ - "INT_INTERFACE_SW4A1", - "SW6BEG1" - ], - [ - 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"HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" - ], - [ - "BRAM_PMVBRAM_SELECT4", - "HCLK_BRAM_PMVBRAM_SELECT4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" - ], - [ - "BRAM_PMVBRAM_SELECT3", - "HCLK_BRAM_PMVBRAM_SELECT3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW2END3_8", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_EE2A1_8", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_WW2A2_8", - "VBRK_WW2A2" - ], - [ - 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"VBRK_WW2A1" - ], - [ - "CMT_TOP_EL1BEG0_8", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_EE4A3_8", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_EE4B0_8", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_NE2A0_8", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_EE2BEG1_8", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_NW4A3_8", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_EE4C2_8", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_EE4BEG3_8", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_LH2_8", - "VBRK_LH2" - ], - [ - "CMT_TOP_SE2A2_8", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_NE4BEG3_8", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_ER1BEG1_8", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_NE4C0_8", - "VBRK_NE4C0" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK23", - 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[ - "CFG_CENTER_SE4C0_1", - "INT_FEEDTHRU_2_SE4C0" - ], - [ - "CFG_CENTER_EL1BEG3_1", - "INT_FEEDTHRU_2_EL1BEG3" - ], - [ - "CFG_CENTER_WW4C2_1", - "INT_FEEDTHRU_2_WW4C2" - ], - [ - "CFG_CENTER_NE4BEG2_1", - "INT_FEEDTHRU_2_NE4BEG2" - ], - [ - "CFG_CENTER_EE4C2_1", - "INT_FEEDTHRU_2_EE4C2" - ], - [ - "CFG_CENTER_ER1BEG3_1", - "INT_FEEDTHRU_2_ER1BEG3" - ], - [ - "CFG_CENTER_NW2A3_1", - "INT_FEEDTHRU_2_NW2A3" - ], - [ - "CFG_CENTER_NW4A2_1", - "INT_FEEDTHRU_2_NW4A2" - ], - [ - "CFG_CENTER_WW4C1_1", - "INT_FEEDTHRU_2_WW4C1" - ], - [ - "CFG_CENTER_SE2A0_1", - "INT_FEEDTHRU_2_SE2A0" - ], - [ - "CFG_CENTER_EE4B2_1", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_LH10_1", - "INT_FEEDTHRU_2_LH10" - ], - [ - "CFG_CENTER_SW2A2_1", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_ER1BEG1_1", - "INT_FEEDTHRU_2_ER1BEG1" - ], - [ - "CFG_CENTER_EE4C0_1", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_LH12_1", - "INT_FEEDTHRU_2_LH12" - ] - ] - }, - { - "grid_deltas": [ - 0, - -2 - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", - "CLK_FEED_R_CK_GCLK11" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_DSP_L", - "HCLK_INT_INTERFACE" - ], - "wire_pairs": [ - [ - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], - [ - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "HCLK_DSP_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN10" - ], - [ - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "HCLK_DSP_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN9" - ], - [ - "HCLK_DSP_CK_IN3", - "HCLK_INT_INTERFACE_CK_IN3" - ], - [ - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "HCLK_DSP_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN6" - ], - [ - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "HCLK_DSP_CK_IN2", - "HCLK_INT_INTERFACE_CK_IN2" - ], - [ - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "HCLK_DSP_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN4" - ], - [ - "HCLK_DSP_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ], - [ - "HCLK_DSP_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN8" - ], - [ - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "HCLK_DSP_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "HCLK_DSP_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN0" - ], - [ - "HCLK_DSP_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN7" - ], - [ - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "HCLK_DSP_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN11" - ], - [ - "HCLK_DSP_CK_IN1", - "HCLK_INT_INTERFACE_CK_IN1" - ], - [ - "HCLK_DSP_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN5" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMV" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_PMV_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_PMV_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_PMV_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_PMV_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_PMV_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_PMV_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_PMV_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_PMV_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_PMV_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_PMV_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_PMV_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_PMV_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_PMV_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_PMV_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_PMV_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_PMV_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_PMV_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_PMV_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_PMV_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_PMV_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_PMV_R_CK_BUFG_CASC18" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_PMV_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_PMV_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_PMV_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_PMV_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_PMV_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_PMV_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_PMV_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_PMV_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_PMV_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_PMV_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_PMV_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_PMV_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_PMV_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_PMV_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_PMV_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_PMV_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_PMV_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_PMV_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_PMV_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_PMV_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_PMV_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_PMV_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_PMV_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_PMV_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_PMV_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_PMV_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_PMV_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_PMV_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_PMV_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_PMV_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_PMV_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_PMV_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_PMV_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_PMV_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_PMV_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_PMV_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_PMV_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_PMV_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_PMV_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_PMV_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_PMV_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_PMV_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_PMV_R_CK_BUFG_CASC16" - ] - ] - }, - { - "grid_deltas": [ - 1, - -2 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_WW4C1_5", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SE4BEG2_5", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE4BEG2_5", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NW2A3_5", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4BEG1_5", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_WW2A2_5", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_LH5_5", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4END2_5", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_WW4END3_5", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE4BEG3_5", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW2A0_5", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4B1_5", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE2BEG0_5", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE2A2_5", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EE4BEG0_5", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4C3_5", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW4A2_5", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_SE4C2_5", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_WW4B2_5", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_ER1BEG0_5", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WL1END1_5", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NE4BEG3_5", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EL1BEG1_5", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE2BEG3_5", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4END1_5", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EE4B3_5", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH2_5", - "VBRK_LH2" - ], - [ - "CLK_HROW_LH4_5", - "VBRK_LH4" - ], - [ - "CLK_HROW_LH1_5", - "VBRK_LH1" - ], - [ - "CLK_HROW_ER1BEG1_5", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW2A1_5", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_NW4A0_5", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NE4C0_5", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_SW4END2_5", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_LH3_5", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH9_5", - "VBRK_LH9" - ], - [ - "CLK_HROW_EE4A1_5", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WR1END3_5", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_SE4BEG1_5", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_NE4C1_5", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW4B1_5", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_NE2A0_5", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE4BEG2_5", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW2A3_5", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WL1END2_5", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_WW4C3_5", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_SE4C0_5", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW2END0_5", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_NE2A1_5", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG0_5", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_NE4C2_5", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_SW2A2_5", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_WW4END1_5", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WR1END0_5", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_WW4C0_5", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE2A3_5", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NE2A3_5", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_SW2A1_5", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_EL1BEG2_5", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4B3_5", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_EE4C0_5", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW2END2_5", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_NE4C3_5", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_EL1BEG0_5", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WR1END2_5", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4END0_5", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_NW2A0_5", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_NW4END2_5", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE4B2_5", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE2BEG2_5", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_EE4A3_5", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_LH8_5", - "VBRK_LH8" - ], - [ - "CLK_HROW_ER1BEG3_5", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NE4BEG1_5", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_LH11_5", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4A2_5", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WL1END3_5", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW4END0_5", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_EE4A0_5", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EE4B0_5", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_SW4A3_5", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_SE2A3_5", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SE4C3_5", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_SW4A0_5", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NW4A1_5", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_NE2A2_5", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WW2END1_5", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_SW4END1_5", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_EL1BEG3_5", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_SW4A1_5", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_SE4BEG3_5", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NW2A2_5", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_EE4C2_5", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_LH6_5", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4A3_5", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_SW4END3_5", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_WL1END0_5", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_NW4A2_5", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_LH7_5", - "VBRK_LH7" - ], - [ - "CLK_HROW_WW4C2_5", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_NW4END0_5", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4C1_5", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_NW4A3_5", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_SW2A3_5", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE2BEG1_5", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_ER1BEG2_5", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_WW4A0_5", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_SE4BEG0_5", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH12_5", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE2A1_5", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_WR1END1_5", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_LH10_5", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE2A2_5", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW4B0_5", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW2END3_5", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SW4A2_5", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NW4END3_5", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SE4C1_5", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_EE2A0_5", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_SW2A0_5", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SE2A0_5", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WW4A1_5", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NW2A1_5", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_EE2A1_5", - "VBRK_EE2A1" - ] - ] - }, - { - "grid_deltas": [ - 1, - 1 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH12_3", - "VBRK_LH12" - ], - [ - "CLK_HROW_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_LH8_3", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_LH1_3", - "VBRK_LH1" - ], - [ - "CLK_HROW_WW4C1_3", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH11_3", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH10_3", - "VBRK_LH10" - ], - [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_LH9_3", - "VBRK_LH9" - ], - [ - "CLK_HROW_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_SW4END1_3", - "VBRK_SW4END1" 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[ - "GTXE2_LOGIC_OUTS_B13_2", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_LOGIC_OUTS_B22_2", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTXE2_LOGIC_OUTS_B7_2", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTXE2_CTRL0_2", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_IMUX12_2", - "VBRK_EXT_IMUX12" - ], - [ - "GTXE2_IMUX37_2", - "VBRK_EXT_IMUX37" - ], - [ - "GTXE2_IMUX5_2", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_IMUX13_2", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_CTRL1_2", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_LOGIC_OUTS_B1_2", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_IMUX47_2", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_IMUX1_2", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_IMUX10_2", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_IMUX7_2", - "VBRK_EXT_IMUX7" - ], - [ - "GTXE2_LOGIC_OUTS_B8_2", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTXE2_FAN3_2", - "VBRK_EXT_FAN3" - ], - [ - "GTXE2_IMUX2_2", - "VBRK_EXT_IMUX2" - ], - [ - "GTXE2_IMUX15_2", - "VBRK_EXT_IMUX15" - ], - [ - "GTXE2_LOGIC_OUTS_B6_2", - "VBRK_EXT_LOGIC_OUTS_B6" - ], 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"VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTXE2_IMUX44_2", - "VBRK_EXT_IMUX44" - ], - [ - "GTXE2_IMUX18_2", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_LOGIC_OUTS_B3_2", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTXE2_IMUX28_2", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_IMUX42_2", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_IMUX19_2", - "VBRK_EXT_IMUX19" - ], - [ - "GTXE2_IMUX45_2", - "VBRK_EXT_IMUX45" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "DSP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "DSP_IMUX45_4", - "INT_INTERFACE_IMUX45" - ], - [ - "DSP_WR1END2_4", - "INT_INTERFACE_WR1END2" - ], - [ - "DSP_LOGIC_OUTS_B11_4", - "INT_INTERFACE_LOGIC_OUTS_B11" - ], - [ - "DSP_LOGIC_OUTS_B21_4", - "INT_INTERFACE_LOGIC_OUTS_B21" - ], - [ - "DSP_LOGIC_OUTS_B20_4", - "INT_INTERFACE_LOGIC_OUTS_B20" - ], - [ - "DSP_WW2END1_4", - "INT_INTERFACE_WW2END1" - ], - [ - "DSP_IMUX14_4", - "INT_INTERFACE_IMUX14" - ], - [ - "DSP_SW4A1_4", - "INT_INTERFACE_SW4A1" - ], - [ - "DSP_WW2END2_4", - "INT_INTERFACE_WW2END2" - ], - [ - "DSP_SE2A1_4", - "INT_INTERFACE_SE2A1" - ], - [ - "DSP_SE2A3_4", - "INT_INTERFACE_SE2A3" - ], - [ - "DSP_EL1BEG1_4", - "INT_INTERFACE_EL1BEG1" - ], - [ - "DSP_CTRL1_4", - "INT_INTERFACE_CTRL1" - ], - [ - "DSP_NW4A1_4", - "INT_INTERFACE_NW4A1" - ], - [ - "DSP_LH3_4", - "INT_INTERFACE_LH3" - ], - [ - "DSP_IMUX24_4", - "INT_INTERFACE_IMUX24" - ], - [ - "DSP_IMUX0_4", - "INT_INTERFACE_IMUX0" - ], - [ - "DSP_IMUX10_4", - "INT_INTERFACE_IMUX10" - ], - [ - "DSP_CLK0_4", - "INT_INTERFACE_CLK0" - ], - [ - "DSP_NW4A0_4", - "INT_INTERFACE_NW4A0" - ], - [ - "DSP_WW2END0_4", - "INT_INTERFACE_WW2END0" - ], - [ - "DSP_WW2END3_4", - "INT_INTERFACE_WW2END3" - ], - [ - "DSP_EE2A0_4", - "INT_INTERFACE_EE2A0" - ], - [ - "DSP_SE4C0_4", - "INT_INTERFACE_SE4C0" - ], - [ - "DSP_BYP4_4", - "INT_INTERFACE_BYP4" - ], - [ - "DSP_WL1END1_4", - "INT_INTERFACE_WL1END1" - ], - [ - "DSP_IMUX47_4", - "INT_INTERFACE_IMUX47" - ], - [ - "DSP_WW2A0_4", - "INT_INTERFACE_WW2A0" - ], - [ - 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"INT_INTERFACE_WL1END2" - ], - [ - "DSP_EL1BEG0_4", - "INT_INTERFACE_EL1BEG0" - ], - [ - "DSP_WW4END1_4", - "INT_INTERFACE_WW4END1" - ], - [ - "DSP_SW4END2_4", - "INT_INTERFACE_SW4END2" - ], - [ - "DSP_IMUX28_4", - "INT_INTERFACE_IMUX28" - ], - [ - "DSP_EE2BEG1_4", - "INT_INTERFACE_EE2BEG1" - ], - [ - "DSP_IMUX37_4", - "INT_INTERFACE_IMUX37" - ], - [ - "DSP_WW4B1_4", - "INT_INTERFACE_WW4B1" - ], - [ - "DSP_IMUX11_4", - "INT_INTERFACE_IMUX11" - ], - [ - "DSP_SE4BEG1_4", - "INT_INTERFACE_SE4BEG1" - ], - [ - "DSP_LOGIC_OUTS_B17_4", - "INT_INTERFACE_LOGIC_OUTS_B17" - ], - [ - "DSP_NW4A2_4", - "INT_INTERFACE_NW4A2" - ], - [ - "DSP_WW4A3_4", - "INT_INTERFACE_WW4A3" - ], - [ - "DSP_EE4BEG1_4", - "INT_INTERFACE_EE4BEG1" - ], - [ - "DSP_IMUX44_4", - "INT_INTERFACE_IMUX44" - ], - [ - "DSP_LH10_4", - "INT_INTERFACE_LH10" - ], - [ - "DSP_LOGIC_OUTS_B4_4", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "DSP_MONITOR_N_4", - "INT_INTERFACE_MONITOR_N" - ], - [ - "DSP_FAN4_4", - "INT_INTERFACE_FAN4" - ], - [ - "DSP_BYP7_4", - "INT_INTERFACE_BYP7" - ], - [ - "DSP_NE4C3_4", - "INT_INTERFACE_NE4C3" - ], - [ - "DSP_ER1BEG3_4", - "INT_INTERFACE_ER1BEG3" - ], - [ - "DSP_IMUX30_4", - "INT_INTERFACE_IMUX30" - ], - [ - "DSP_IMUX20_4", - "INT_INTERFACE_IMUX20" - ], - [ - "DSP_SW2A2_4", - "INT_INTERFACE_SW2A2" - ], - [ - "DSP_NE2A1_4", - "INT_INTERFACE_NE2A1" - ], - [ - "DSP_SE2A2_4", - "INT_INTERFACE_SE2A2" - ], - [ - "DSP_SE2A0_4", - "INT_INTERFACE_SE2A0" - ], - [ - "DSP_NW2A3_4", - "INT_INTERFACE_NW2A3" - ], - [ - "DSP_EE2BEG0_4", - "INT_INTERFACE_EE2BEG0" - ], - [ - "DSP_NW2A2_4", - "INT_INTERFACE_NW2A2" - ], - [ - "DSP_IMUX35_4", - "INT_INTERFACE_IMUX35" - ], - [ - "DSP_EE4B2_4", - "INT_INTERFACE_EE4B2" - ], - [ - "DSP_IMUX26_4", - "INT_INTERFACE_IMUX26" - ], - [ - "DSP_WR1END0_4", - "INT_INTERFACE_WR1END0" - ], - [ - "DSP_IMUX23_4", - "INT_INTERFACE_IMUX23" - ], - [ - "DSP_LH9_4", - "INT_INTERFACE_LH9" - ], - [ - "DSP_BYP0_4", + "PCIE_BYP0_R_0", "INT_INTERFACE_BYP0" ], [ - "DSP_IMUX7_4", - "INT_INTERFACE_IMUX7" + "PCIE_BYP1_R_0", + "INT_INTERFACE_BYP1" ], [ - "DSP_NW4END2_4", - "INT_INTERFACE_NW4END2" + "PCIE_BYP2_R_0", + "INT_INTERFACE_BYP2" ], [ - "DSP_SE4BEG0_4", - "INT_INTERFACE_SE4BEG0" + "PCIE_BYP3_R_0", + "INT_INTERFACE_BYP3" ], [ - "DSP_NE4C1_4", - "INT_INTERFACE_NE4C1" + "PCIE_BYP4_R_0", + "INT_INTERFACE_BYP4" ], [ - "DSP_EE4A3_4", + "PCIE_BYP5_R_0", + "INT_INTERFACE_BYP5" + ], + [ + "PCIE_BYP6_R_0", + "INT_INTERFACE_BYP6" + ], + [ + "PCIE_BYP7_R_0", + "INT_INTERFACE_BYP7" + ], + [ + "PCIE_CLK0_R_0", + "INT_INTERFACE_CLK0" + ], + [ + "PCIE_CLK1_R_0", + "INT_INTERFACE_CLK1" + ], + [ + "PCIE_CTRL0_R_0", + "INT_INTERFACE_CTRL0" + ], + [ + "PCIE_CTRL1_R_0", + "INT_INTERFACE_CTRL1" + ], + [ + "PCIE_EE2A0_0", + "INT_INTERFACE_EE2A0" + ], + [ + "PCIE_EE2A1_0", + "INT_INTERFACE_EE2A1" + ], + [ + "PCIE_EE2A2_0", + "INT_INTERFACE_EE2A2" + ], + [ + "PCIE_EE2A3_0", + "INT_INTERFACE_EE2A3" + ], + [ + "PCIE_EE2BEG0_0", + "INT_INTERFACE_EE2BEG0" + ], + [ + "PCIE_EE2BEG1_0", + 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"TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_IMUX44_1", - "TERM_INT_IMUX44" - ], - [ - "IOI_LOGIC_OUTS10_1", - "TERM_INT_LOGIC_OUTS_L_B10" - ] - ] - }, - { - "grid_deltas": [ - 1, - -4 - ], - "tile_types": [ - "BRAM_R", - "VBRK" - ], - "wire_pairs": [ - [ - "BRAM_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "BRAM_EE4C0_4", - "VBRK_EE4C0" - ], - [ - "BRAM_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "BRAM_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "BRAM_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "BRAM_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "BRAM_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "BRAM_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "BRAM_LH1_4", - "VBRK_LH1" - ], - [ - "BRAM_LH8_4", - "VBRK_LH8" - ], - [ - "BRAM_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "BRAM_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "BRAM_LH12_4", - "VBRK_LH12" - ], - [ - "BRAM_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "BRAM_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "BRAM_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "BRAM_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "BRAM_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "BRAM_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "BRAM_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "BRAM_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "BRAM_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "BRAM_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "BRAM_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "BRAM_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "BRAM_LH9_4", - "VBRK_LH9" - ], - [ - "BRAM_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "BRAM_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "BRAM_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "BRAM_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "BRAM_LH7_4", - "VBRK_LH7" - ], - [ - "BRAM_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "BRAM_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "BRAM_LH5_4", - "VBRK_LH5" - ], - [ - "BRAM_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "BRAM_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "BRAM_LH3_4", - "VBRK_LH3" - ], - [ - "BRAM_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "BRAM_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "BRAM_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "BRAM_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "BRAM_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "BRAM_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "BRAM_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "BRAM_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "BRAM_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "BRAM_LH10_4", - "VBRK_LH10" - ], - [ - "BRAM_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "BRAM_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "BRAM_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "BRAM_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "BRAM_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "BRAM_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "BRAM_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "BRAM_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "BRAM_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "BRAM_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "BRAM_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "BRAM_SE2A1_4", - "VBRK_SE2A1" - ], - [ - "BRAM_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "BRAM_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "BRAM_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "BRAM_LH11_4", - "VBRK_LH11" - ], - [ - "BRAM_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "BRAM_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "BRAM_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "BRAM_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "BRAM_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "BRAM_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "BRAM_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "BRAM_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "BRAM_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "BRAM_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "BRAM_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "BRAM_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "BRAM_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "BRAM_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "BRAM_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "BRAM_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "BRAM_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "BRAM_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "BRAM_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "BRAM_LH2_4", - "VBRK_LH2" - ], - [ - "BRAM_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "BRAM_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "BRAM_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "BRAM_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "BRAM_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "BRAM_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "BRAM_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "BRAM_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "BRAM_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "BRAM_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "BRAM_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "BRAM_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "BRAM_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "BRAM_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "BRAM_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "BRAM_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "BRAM_LH6_4", - "VBRK_LH6" - ], - [ - "BRAM_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "BRAM_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "BRAM_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "BRAM_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "BRAM_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "BRAM_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "BRAM_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "BRAM_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - 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- "VBRK_WL1END2" - ], - [ - "CMT_TOP_SE4C3_12", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_LH9_12", - "VBRK_LH9" - ], - [ - "CMT_TOP_WL1END1_12", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_SW4END0_12", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_EE2BEG2_12", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_SW2A2_12", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_EE4BEG2_12", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_SW4A1_12", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_SW2A1_12", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_EE2A1_12", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_SE2A2_12", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_WW2END2_12", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_NE4BEG3_12", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_NW4END3_12", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_SE4BEG1_12", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_EL1BEG1_12", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_NW2A1_12", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_WW4B2_12", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_SE4BEG2_12", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_SW4END2_12", - "VBRK_SW4END2" - ], - [ - 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"IOI_IMUX45_0", - "TERM_INT_IMUX45" - ], - [ - "IOI_LOGIC_OUTS1_0", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_LOGIC_OUTS3_0", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_IMUX32_0", - "TERM_INT_IMUX32" - ], - [ - "IOI_LOGIC_OUTS7_0", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_BYP2_0", - "TERM_INT_BYP2" - ], - [ - "IOI_IMUX46_0", - "TERM_INT_IMUX46" - ], - [ - "IOI_LOGIC_OUTS15_0", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_IMUX8_0", - "TERM_INT_IMUX8" - ], - [ - "IOI_LOGIC_OUTS5_0", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_IMUX2_0", - "TERM_INT_IMUX2" - ], - [ - "IOI_LOGIC_OUTS20_0", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_IMUX41_0", - "TERM_INT_IMUX41" - ], - [ - "IOI_IMUX28_0", - "TERM_INT_IMUX28" - ], - [ - "IOI_LOGIC_OUTS8_0", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_IMUX47_0", - "TERM_INT_IMUX47" - ], - [ - "IOI_IMUX26_0", - "TERM_INT_IMUX26" - ], - [ - "IOI_IMUX38_0", - "TERM_INT_IMUX38" - ], - [ - "IOI_IMUX0_0", - "TERM_INT_IMUX0" - ], - [ - "IOI_IMUX6_0", - "TERM_INT_IMUX6" - ], - [ - "IOI_IMUX44_0", - "TERM_INT_IMUX44" - ], - [ - "IOI_LOGIC_OUTS2_0", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "IOI_IMUX35_0", - "TERM_INT_IMUX35" - ], - [ - "IOI_FAN1_0", - "TERM_INT_FAN1" - ], - [ - "IOI_IMUX17_0", - "TERM_INT_IMUX17" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "GTX_COMMON", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTXE2_IMUX20_3", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_IMUX1_3", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_IMUX28_3", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_FAN6_3", - "VBRK_EXT_FAN6" - ], - [ - "GTXE2_IMUX39_3", - "VBRK_EXT_IMUX39" - ], - [ - "GTXE2_FAN2_3", - "VBRK_EXT_FAN2" - ], - [ - "GTXE2_IMUX38_3", - "VBRK_EXT_IMUX38" - ], - [ - "GTXE2_IMUX37_3", - "VBRK_EXT_IMUX37" - ], - [ - "GTXE2_LOGIC_OUTS_B21_3", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTXE2_IMUX42_3", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_BYP6_3", - "VBRK_EXT_BYP6" - ], - [ - "GTXE2_IMUX18_3", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_LOGIC_OUTS_B19_3", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTXE2_FAN5_3", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_CTRL0_3", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_CLK1_3", - "VBRK_EXT_CLK1" - ], - [ - "GTXE2_IMUX43_3", - "VBRK_EXT_IMUX43" - ], - [ - "GTXE2_IMUX41_3", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_IMUX7_3", - "VBRK_EXT_IMUX7" - ], - [ - "GTXE2_IMUX23_3", - "VBRK_EXT_IMUX23" - ], - [ - "GTXE2_IMUX19_3", - "VBRK_EXT_IMUX19" - ], - [ - "GTXE2_IMUX30_3", - "VBRK_EXT_IMUX30" - ], - [ - "GTXE2_IMUX13_3", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_FAN4_3", - "VBRK_EXT_FAN4" - ], - [ - "GTXE2_IMUX3_3", - "VBRK_EXT_IMUX3" - ], - [ - "GTXE2_IMUX9_3", - "VBRK_EXT_IMUX9" - ], - [ - "GTXE2_LOGIC_OUTS_B23_3", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTXE2_IMUX32_3", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_IMUX14_3", - "VBRK_EXT_IMUX14" - ], - [ - "GTXE2_IMUX40_3", - "VBRK_EXT_IMUX40" - ], - [ - "GTXE2_BYP7_3", - "VBRK_EXT_BYP7" - ], - [ - "GTXE2_IMUX17_3", - "VBRK_EXT_IMUX17" - ], - [ - "GTXE2_IMUX21_3", - "VBRK_EXT_IMUX21" - ], - [ - "GTXE2_FAN3_3", - "VBRK_EXT_FAN3" - ], - [ - "GTXE2_IMUX29_3", - "VBRK_EXT_IMUX29" - ], - [ - "GTXE2_LOGIC_OUTS_B9_3", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTXE2_IMUX25_3", - "VBRK_EXT_IMUX25" - ], - [ - "GTXE2_BYP3_3", - "VBRK_EXT_BYP3" - ], - [ - "GTXE2_IMUX2_3", - "VBRK_EXT_IMUX2" - ], - [ - "GTXE2_LOGIC_OUTS_B10_3", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTXE2_BYP0_3", - "VBRK_EXT_BYP0" - ], - [ - "GTXE2_IMUX26_3", - "VBRK_EXT_IMUX26" - ], - [ - "GTXE2_IMUX6_3", - "VBRK_EXT_IMUX6" - ], - [ - "GTXE2_IMUX11_3", - "VBRK_EXT_IMUX11" - ], - [ - "GTXE2_IMUX34_3", - "VBRK_EXT_IMUX34" - ], - [ - "GTXE2_IMUX44_3", - "VBRK_EXT_IMUX44" - ], - [ - "GTXE2_CLK0_3", - "VBRK_EXT_CLK0" - ], - [ - "GTXE2_IMUX5_3", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_BYP1_3", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_LOGIC_OUTS_B2_3", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTXE2_IMUX10_3", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_BYP4_3", - "VBRK_EXT_BYP4" - ], - [ - "GTXE2_IMUX0_3", - "VBRK_EXT_IMUX0" - ], - [ - "GTXE2_IMUX47_3", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_IMUX36_3", - "VBRK_EXT_IMUX36" - ], - [ - "GTXE2_IMUX12_3", - "VBRK_EXT_IMUX12" - ], - [ - "GTXE2_FAN7_3", - "VBRK_EXT_FAN7" - ], - [ - "GTXE2_CTRL1_3", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_IMUX35_3", - "VBRK_EXT_IMUX35" - ], - [ - "GTXE2_IMUX22_3", - "VBRK_EXT_IMUX22" - ], - [ - "GTXE2_IMUX33_3", - "VBRK_EXT_IMUX33" - ], - [ - "GTXE2_IMUX31_3", - "VBRK_EXT_IMUX31" - ], - [ - "GTXE2_FAN1_3", - "VBRK_EXT_FAN1" - ], - [ - "GTXE2_IMUX27_3", - "VBRK_EXT_IMUX27" - ], - [ - "GTXE2_BYP5_3", - "VBRK_EXT_BYP5" - ], - [ - "GTXE2_IMUX4_3", - "VBRK_EXT_IMUX4" - ], - [ - "GTXE2_IMUX15_3", - "VBRK_EXT_IMUX15" - ], - [ - "GTXE2_FAN0_3", - "VBRK_EXT_FAN0" - ], - [ - "GTXE2_BYP2_3", - "VBRK_EXT_BYP2" - ], - [ - "GTXE2_LOGIC_OUTS_B17_3", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTXE2_IMUX8_3", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX45_3", - "VBRK_EXT_IMUX45" - ], - [ - "GTXE2_IMUX16_3", - "VBRK_EXT_IMUX16" - ], - [ - "GTXE2_IMUX24_3", - "VBRK_EXT_IMUX24" - ], - [ - "GTXE2_IMUX46_3", - "VBRK_EXT_IMUX46" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_TERM" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_TERM_R_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_TERM_R_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_TERM_R_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_TERM_R_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_TERM_R_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_TERM_R_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_TERM_R_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_TERM_R_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_TERM_R_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_TERM_R_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_TERM_R_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_TERM_R_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_TERM_R_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_TERM_R_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_TERM_R_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_TERM_R_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_TERM_R_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_TERM_R_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_TERM_R_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_TERM_R_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_TERM_R_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_TERM_R_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_TERM_R_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_TERM_R_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_TERM_R_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_TERM_R_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_TERM_R_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_TERM_R_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_TERM_R_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_TERM_R_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_TERM_R_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_TERM_R_GCLK19" - ] - ] - }, - { - "grid_deltas": [ - 0, - -2 - ], - "tile_types": [ - "LIOI3", - "LIOI3_TBYTETERM" - ], - "wire_pairs": [ - [ - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK4" - ], - [ - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK0" - ], - [ - "IOI_IOCLK2", - "IOI_IOCLK2" - ], - [ - "IOI_IOCLK3", - "IOI_IOCLK3" - ], - [ - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE2" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_RCLK_FORIO3" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK3" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK2" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_LEAF_GCLK5" - ], - [ - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CE3" - ], - [ - "IOI_IMUX_RC3", - "IOI_IMUX_RC1" - ], - [ - "IOI_IOCLK1", - "IOI_IOCLK1" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO1" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO2" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK1" - ], - [ - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO0" - ], - [ - "IOI_IOCLK0", - "IOI_IOCLK0" - ], - [ - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1" - ], - [ - "IOI_IMUX_RC2", - "IOI_IMUX_RC0" - ] - ] - }, - { - "grid_deltas": [ - -1, - 4 - ], - "tile_types": [ - "BRAM_INT_INTERFACE_L", - "BRAM_L" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_WW4END2", - "BRAM_WW4END2_4" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_4" - ], - [ - "INT_INTERFACE_SW4A0", - "BRAM_SW4A0_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "BRAM_LOGIC_OUTS_B1_4" - ], - [ - "INT_INTERFACE_WW4C3", - "BRAM_WW4C3_4" - ], - [ - "INT_INTERFACE_LH3", - "BRAM_LH3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX11", - "BRAM_IMUX11_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_4" - ], - [ - "INT_INTERFACE_SE2A0", - "BRAM_SE2A0_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX33", - "BRAM_IMUX33_4" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "BRAM_LOGIC_OUTS_B5_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX42", - "BRAM_IMUX42_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_4" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX40", - "BRAM_IMUX40_UTURN_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "BRAM_LOGIC_OUTS_B20_4" - ], - [ - "INT_INTERFACE_WR1END1", - "BRAM_WR1END1_4" - ], - [ - "INT_INTERFACE_WW2END2", - "BRAM_WW2END2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_4" - ], - [ - "INT_INTERFACE_NW4A2", - "BRAM_NW4A2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX18", - "BRAM_IMUX18_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX24", - "BRAM_IMUX24_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_4" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_4" - ], - [ - "INT_INTERFACE_NE4C3", - "BRAM_NE4C3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX34", - "BRAM_IMUX34_4" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX33", - "BRAM_IMUX33_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX45", - "BRAM_IMUX45_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX11", - "BRAM_IMUX11_UTURN_4" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_4" - ], - [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_4" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_4" - ], - [ - "INT_INTERFACE_EE4BEG1", - "BRAM_EE4BEG1_4" - ], - [ - "INT_INTERFACE_ER1BEG0", - "BRAM_ER1BEG0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX8", - "BRAM_IMUX8_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "BRAM_IMUX1_4" - ], - [ - "INT_INTERFACE_NW2A2", - "BRAM_NW2A2_4" - ], - [ - "INT_INTERFACE_LH2", - "BRAM_LH2_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "BRAM_LOGIC_OUTS_B3_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX36", - "BRAM_IMUX36_UTURN_4" - ], - [ - "INT_INTERFACE_WW4B0", - "BRAM_WW4B0_4" - ], - [ - "INT_INTERFACE_SW4A3", - "BRAM_SW4A3_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "BRAM_LOGIC_OUTS_B2_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "BRAM_LOGIC_OUTS_B12_4" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_4" - ], - [ - "INT_INTERFACE_BYP2", - "BRAM_BYP2_4" - ], - [ - "INT_INTERFACE_EE4C2", - "BRAM_EE4C2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX40", - "BRAM_IMUX40_4" - ], - [ - "INT_INTERFACE_BYP4", - "BRAM_BYP4_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "BRAM_LOGIC_OUTS_B21_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX47", - "BRAM_IMUX47_UTURN_4" - ], - [ - "INT_INTERFACE_SE4BEG3", - "BRAM_SE4BEG3_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX20", - "BRAM_IMUX20_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "BRAM_IMUX38_4" - ], - [ - "INT_INTERFACE_NE4C0", - "BRAM_NE4C0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX32", - "BRAM_IMUX32_UTURN_4" - ], - [ - "INT_INTERFACE_FAN0", - "BRAM_FAN0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX28", - "BRAM_IMUX28_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX31", - "BRAM_IMUX31_UTURN_4" - ], - [ - "INT_INTERFACE_LH12", - "BRAM_LH12_4" - ], - [ - "INT_INTERFACE_MONITOR_P", - "BRAM_MONITOR_P_4" - ], - [ - "INT_INTERFACE_NE2A2", - "BRAM_NE2A2_4" - ], - [ - "INT_INTERFACE_EE4C3", - "BRAM_EE4C3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "BRAM_IMUX17_4" - ], - [ - "INT_INTERFACE_WW4END1", - "BRAM_WW4END1_4" - ], - [ - "INT_INTERFACE_LH5", - "BRAM_LH5_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX42", - "BRAM_IMUX42_4" - ], - [ - "INT_INTERFACE_EE4B2", - "BRAM_EE4B2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX29", - "BRAM_IMUX29_UTURN_4" - ], - [ - "INT_INTERFACE_WW4C2", - "BRAM_WW4C2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX46", - "BRAM_IMUX46_UTURN_4" - ], - [ - "INT_INTERFACE_SW4A1", - "BRAM_SW4A1_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "BRAM_IMUX8_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "BRAM_IMUX10_UTURN_4" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_4" - ], - [ - "INT_INTERFACE_LH9", - "BRAM_LH9_4" - ], - [ - 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"PCIE_INT_INTERFACE_IMUX_L_OUT6" - ], - [ - "PCIE_SW4A3_4", - "INT_INTERFACE_SW4A3" - ], - [ - "PCIE_LH5_4", - "INT_INTERFACE_LH5" - ], - [ - "PCIE_EE4BEG2_4", - "INT_INTERFACE_EE4BEG2" - ], - [ - "PCIE_IMUX36_L_4", - "PCIE_INT_INTERFACE_IMUX_L_OUT36" - ] - ] - }, - { - "grid_deltas": [ - 1, - -1 - ], - "tile_types": [ - "CLK_PMV", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_PMV_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_PMV_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_PMV_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_PMV_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_PMV_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CLK_PMV_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_PMV_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_PMV_LH6_1", - "VBRK_LH6" - ], - [ - "CLK_PMV_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_PMV_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_PMV_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_PMV_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_PMV_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_PMV_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_PMV_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_PMV_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_PMV_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_PMV_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_PMV_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_PMV_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_PMV_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_PMV_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_PMV_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_PMV_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_PMV_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CLK_PMV_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_PMV_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_PMV_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_PMV_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_PMV_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_PMV_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_PMV_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_PMV_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_PMV_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_PMV_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_PMV_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_PMV_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_PMV_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_PMV_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_PMV_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_PMV_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_PMV_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_PMV_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_PMV_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_PMV_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_PMV_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_PMV_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_PMV_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_PMV_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CLK_PMV_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_PMV_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_PMV_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CLK_PMV_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_PMV_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_PMV_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_PMV_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CLK_PMV_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ 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"VBRK_SW4END2" - ], - [ - "CLK_PMV_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_PMV_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_PMV_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_PMV_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_PMV_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_PMV_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_PMV_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_PMV_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_PMV_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_PMV_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_PMV_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_PMV_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_PMV_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_PMV_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CLK_PMV_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CLK_PMV_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_PMV_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_PMV_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_PMV_LH1_1", - "VBRK_LH1" - ], - [ - "CLK_PMV_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_PMV_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_PMV_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_PMV_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_PMV_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_PMV_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_PMV_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_PMV_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_PMV_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_PMV_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_PMV_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_PMV_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_PMV_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_PMV_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_PMV_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CLK_PMV_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_PMV_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_PMV_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_PMV_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_PMV_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_PMV_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CLK_PMV_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_PMV_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CLK_PMV_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_PMV_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_PMV_EL1BEG0_1", - "VBRK_EL1BEG0" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_PMV2", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_FEED_WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_FEED_NW2A0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_FEED_MONITOR_N", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_PMV_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_FEED_LH1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_FEED_WW2END2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_FEED_EE2A3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_PMV_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_FEED_ER1BEG1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_FEED_SE2A1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_FEED_WW4END3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_FEED_NW4END1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_FEED_LH10", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_FEED_WL1END1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_PMV_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_PMV_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_FEED_WR1END1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_FEED_EL1BEG1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_FEED_SE4BEG2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_PMV_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_FEED_EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_FEED_SW2A1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_FEED_EE4A3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_FEED_WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_PMV_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_FEED_NE4BEG0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_FEED_SW2A2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_FEED_SE4C3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_PMV_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_FEED_SE4BEG1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_FEED_EL1BEG3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_FEED_EL1BEG2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_FEED_NE4BEG3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_FEED_EE4B2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_FEED_NW2A1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_FEED_LH5", - "INT_INTERFACE_LH5" - ], - [ - "CLK_PMV_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_FEED_WW4C1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_FEED_WW4B0", - "INT_INTERFACE_WW4B0" - ], - [ - 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"CLK_FEED_WL1END3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_PMV_LOGIC_OUTS19_0", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "CLK_FEED_NW4A2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_PMV_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_FEED_EE2BEG2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_FEED_NE2A3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_FEED_SE2A3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_PMV_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_PMV_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_FEED_SE2A0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_FEED_WL1END2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_FEED_SW4A0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_FEED_SE4C0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_PMV_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_FEED_WW4A0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_FEED_NE4C2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_FEED_NE4C3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_FEED_LH3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_FEED_SE2A2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_FEED_NW4END2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_FEED_SE4BEG3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_PMV_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_FEED_WR1END3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_PMV_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_FEED_WW4B2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_PMV_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_FEED_SW4END3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_FEED_NW4END0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_FEED_NE4BEG1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_FEED_LH8", - "INT_INTERFACE_LH8" - ], - [ - "CLK_PMV_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_FEED_EE4B3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_FEED_WW4C2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_FEED_WW2A2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_FEED_SW4A2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_FEED_LH9", - "INT_INTERFACE_LH9" - ], - [ - "CLK_PMV_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_FEED_EE4BEG0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_FEED_EE4BEG3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_PMV_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_FEED_EE2BEG0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_FEED_EE4B0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_FEED_EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_FEED_SW4A1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_FEED_WW4A1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_FEED_SE4C1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_FEED_SE4C2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_PMV_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_FEED_SW4END0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_FEED_EE2A1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_FEED_LH6", - "INT_INTERFACE_LH6" - ], - [ - "CLK_FEED_EE4A1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_FEED_EE2BEG3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_FEED_SE4BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_FEED_LH7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_FEED_EL1BEG0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_FEED_LH11", - "INT_INTERFACE_LH11" - ], - [ - "CLK_FEED_WR1END2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_FEED_WW4END0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_FEED_WW4B3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_FEED_NW4A3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_FEED_WW2A1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_PMV_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_PMV_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_FEED_SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_FEED_ER1BEG0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_PMV_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_FEED_ER1BEG2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_PMV_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_FEED_WW4A3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_FEED_EE4BEG2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_FEED_EE4A2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_EE2A0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_PMV_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_FEED_NW2A2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_FEED_WW4A2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_FEED_WW2END1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_FEED_WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_FEED_LH4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_FEED_EE2BEG1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_LOGIC_OUTS5_0", + "PCIE_LOGIC_OUTS_B5_R_0", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" + "PCIE_LOGIC_OUTS_B6_R_0", + "INT_INTERFACE_LOGIC_OUTS_B6" ], [ - "CLK_PMV_IMUX5_0", - "INT_INTERFACE_IMUX5" + "PCIE_LOGIC_OUTS_B7_R_0", + "INT_INTERFACE_LOGIC_OUTS_B7" ], [ - "CLK_FEED_NE4BEG2", - "INT_INTERFACE_NE4BEG2" + "PCIE_LOGIC_OUTS_B8_R_0", + "INT_INTERFACE_LOGIC_OUTS_B8" ], [ - "CLK_FEED_EE4C0", - "INT_INTERFACE_EE4C0" + "PCIE_LOGIC_OUTS_B9_R_0", + "INT_INTERFACE_LOGIC_OUTS_B9" ], [ - "CLK_PMV_IMUX42_0", - "INT_INTERFACE_IMUX42" + "PCIE_LOGIC_OUTS_B10_R_0", + "INT_INTERFACE_LOGIC_OUTS_B10" ], [ - "CLK_FEED_LH12", - "INT_INTERFACE_LH12" + "PCIE_LOGIC_OUTS_B11_R_0", + "INT_INTERFACE_LOGIC_OUTS_B11" ], [ - "CLK_FEED_NE2A2", - "INT_INTERFACE_NE2A2" + "PCIE_LOGIC_OUTS_B12_R_0", + "INT_INTERFACE_LOGIC_OUTS_B12" ], [ - "CLK_FEED_WW4END1", - "INT_INTERFACE_WW4END1" + "PCIE_LOGIC_OUTS_B13_R_0", + "INT_INTERFACE_LOGIC_OUTS_B13" ], [ - "CLK_FEED_EE4BEG1", - "INT_INTERFACE_EE4BEG1" + "PCIE_LOGIC_OUTS_B14_R_0", + "INT_INTERFACE_LOGIC_OUTS_B14" ], [ - "CLK_PMV_FAN4_0", - "INT_INTERFACE_FAN4" + "PCIE_LOGIC_OUTS_B15_R_0", + "INT_INTERFACE_LOGIC_OUTS_B15" ], [ - "CLK_FEED_LH2", - "INT_INTERFACE_LH2" + "PCIE_LOGIC_OUTS_B16_R_0", + "INT_INTERFACE_LOGIC_OUTS_B16" ], [ - "CLK_FEED_NE2A0", + "PCIE_LOGIC_OUTS_B17_R_0", + "INT_INTERFACE_LOGIC_OUTS_B17" + ], + [ + "PCIE_LOGIC_OUTS_B18_R_0", + "INT_INTERFACE_LOGIC_OUTS_B18" + ], + [ + "PCIE_LOGIC_OUTS_B19_R_0", + "INT_INTERFACE_LOGIC_OUTS_B19" + ], + [ + "PCIE_LOGIC_OUTS_B20_R_0", + "INT_INTERFACE_LOGIC_OUTS_B20" + ], + [ + "PCIE_LOGIC_OUTS_B21_R_0", + "INT_INTERFACE_LOGIC_OUTS_B21" + ], + [ + "PCIE_LOGIC_OUTS_B22_R_0", + "INT_INTERFACE_LOGIC_OUTS_B22" + ], + [ + "PCIE_LOGIC_OUTS_B23_R_0", + "INT_INTERFACE_LOGIC_OUTS_B23" + ], + [ + "PCIE_NE2A0_0", "INT_INTERFACE_NE2A0" ], [ - "CLK_PMV_CLK0_0", - "INT_INTERFACE_CLK0" + "PCIE_NE2A1_0", + "INT_INTERFACE_NE2A1" ], [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" + "PCIE_NE2A2_0", + "INT_INTERFACE_NE2A2" ], [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_FEED_NW4A0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_NW4END3", - "INT_INTERFACE_NW4END3" - ] - ] - }, - { - "grid_deltas": [ - 1, - -1 - ], - "tile_types": [ - "CMT_TOP_R_UPPER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW4A1_6", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_EE4B1_6", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_NE4C0_6", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_WW2END2_6", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_EL1BEG0_6", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WW4B3_6", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_SW2A3_6", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_WW2END3_6", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_EE4C1_6", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_SW4END0_6", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_SE4C1_6", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_LH6_6", - "VBRK_LH6" - ], - [ - "CMT_TOP_SE4BEG2_6", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_SW4A1_6", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_WR1END0_6", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_WR1END1_6", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_NW4END0_6", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_WW2END1_6", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_SE2A3_6", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_EE4BEG2_6", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_WL1END1_6", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_NW2A3_6", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_NW4A1_6", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_NE4C3_6", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_NE4BEG3_6", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_NW2A1_6", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_LH3_6", - "VBRK_LH3" - ], - [ - "CMT_TOP_SW4END1_6", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_LH10_6", - "VBRK_LH10" - ], - [ - "CMT_TOP_LH9_6", - "VBRK_LH9" - ], - [ - "CMT_TOP_EE2BEG1_6", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_WW4B1_6", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WW4END2_6", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_NW4END1_6", - "VBRK_NW4END1" - ], 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"INT_INTERFACE_WR1END0" + "PCIE_SE2A3_0", + "INT_INTERFACE_SE2A3" ], [ - "PCIE_IMUX15_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT15" + "PCIE_SE4BEG0_0", + "INT_INTERFACE_SE4BEG0" ], [ - "PCIE_WW4END1_9", - "INT_INTERFACE_WW4END1" - ], - [ - "PCIE_BYP6_L_9", - "INT_INTERFACE_BYP6" - ], - [ - "PCIE_BYP3_L_9", - "INT_INTERFACE_BYP3" - ], - [ - "PCIE_IMUX1_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT1" - ], - [ - "PCIE_SE4C3_9", - "INT_INTERFACE_SE4C3" - ], - [ - "PCIE_LOGIC_OUTS_B10_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B10" - ], - [ - "PCIE_EL1BEG3_9", - "INT_INTERFACE_EL1BEG3" - ], - [ - "PCIE_IMUX28_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT28" - ], - [ - "PCIE_NE4C3_9", - "INT_INTERFACE_NE4C3" - ], - [ - "PCIE_LH1_9", - "INT_INTERFACE_LH1" - ], - [ - "PCIE_EE4BEG2_9", - "INT_INTERFACE_EE4BEG2" - ], - [ - "PCIE_ER1BEG3_9", - "INT_INTERFACE_ER1BEG3" - ], - [ - "PCIE_EE2BEG1_9", - "INT_INTERFACE_EE2BEG1" - ], - [ - "PCIE_EE4BEG0_9", - "INT_INTERFACE_EE4BEG0" - ], - [ - "PCIE_IMUX31_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT31" - ], - [ - "PCIE_IMUX23_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT23" - ], - [ - "PCIE_LOGIC_OUTS_B4_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B4" - ], - [ - "PCIE_SE4BEG2_9", - "INT_INTERFACE_SE4BEG2" - ], - [ - "PCIE_IMUX18_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT18" - ], - [ - "PCIE_FAN7_L_9", - "INT_INTERFACE_FAN7" - ], - [ - "PCIE_FAN3_L_9", - "INT_INTERFACE_FAN3" - ], - [ - "PCIE_CLK1_L_9", - "INT_INTERFACE_CLK1" - ], - [ - "PCIE_WW4B1_9", - "INT_INTERFACE_WW4B1" - ], - [ - "PCIE_LH5_9", - "INT_INTERFACE_LH5" - ], - [ - "PCIE_EE2BEG3_9", - "INT_INTERFACE_EE2BEG3" - ], - [ - "PCIE_IMUX13_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT13" - ], - [ - "PCIE_ER1BEG1_9", - "INT_INTERFACE_ER1BEG1" - ], - [ - "PCIE_SE4BEG1_9", + "PCIE_SE4BEG1_0", "INT_INTERFACE_SE4BEG1" ], [ - "PCIE_EE4B2_9", - "INT_INTERFACE_EE4B2" + "PCIE_SE4BEG2_0", + "INT_INTERFACE_SE4BEG2" ], [ - "PCIE_SW4END3_9", - "INT_INTERFACE_SW4END3" - ], - [ - "PCIE_IMUX11_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT11" - ], - [ - "PCIE_LOGIC_OUTS_B16_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B16" - ], - [ - "PCIE_IMUX38_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT38" - ], - [ - "PCIE_WR1END1_9", - "INT_INTERFACE_WR1END1" - ], - [ - "PCIE_LH6_9", - "INT_INTERFACE_LH6" - ], - [ - "PCIE_WW2END0_9", - "INT_INTERFACE_WW2END0" - ], - [ - "PCIE_LOGIC_OUTS_B22_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B22" - ], - [ - "PCIE_IMUX4_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT4" - ], - [ - "PCIE_SW4END1_9", - "INT_INTERFACE_SW4END1" - ], - [ - "PCIE_EE4A3_9", - "INT_INTERFACE_EE4A3" - ], - [ - "PCIE_NE4BEG1_9", - "INT_INTERFACE_NE4BEG1" - ], - [ - "PCIE_IMUX9_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT9" - ], - [ - "PCIE_IMUX40_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT40" - ], - [ - "PCIE_NW2A0_9", - "INT_INTERFACE_NW2A0" - ], - [ - "PCIE_SE4C1_9", - "INT_INTERFACE_SE4C1" - ], - [ - "PCIE_LOGIC_OUTS_B21_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B21" - ], - [ - "PCIE_FAN5_L_9", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_LOGIC_OUTS_B2_L_9", - "INT_INTERFACE_LOGIC_OUTS_L_B2" - ], - [ - "PCIE_IMUX30_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT30" - ], - [ - "PCIE_LH3_9", - "INT_INTERFACE_LH3" - ], - [ - "PCIE_WW4B3_9", - "INT_INTERFACE_WW4B3" - ], - [ - "PCIE_EE4A1_9", - "INT_INTERFACE_EE4A1" - ], - [ - "PCIE_SE4BEG3_9", + "PCIE_SE4BEG3_0", "INT_INTERFACE_SE4BEG3" ], [ - "PCIE_SW2A1_9", - "INT_INTERFACE_SW2A1" + "PCIE_SE4C0_0", + "INT_INTERFACE_SE4C0" ], [ - "PCIE_EL1BEG1_9", - "INT_INTERFACE_EL1BEG1" + "PCIE_SE4C1_0", + "INT_INTERFACE_SE4C1" ], [ - "PCIE_LH8_9", - "INT_INTERFACE_LH8" + "PCIE_SE4C2_0", + "INT_INTERFACE_SE4C2" ], [ - "PCIE_EE4A2_9", - "INT_INTERFACE_EE4A2" + "PCIE_SE4C3_0", + "INT_INTERFACE_SE4C3" ], [ - "PCIE_NE2A0_9", - "INT_INTERFACE_NE2A0" - ], - [ - "PCIE_IMUX27_L_9", - "PCIE_INT_INTERFACE_IMUX_L_OUT27" - ] - ] - }, - { - "grid_deltas": [ - -1, - 3 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NW4END3_1", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_BYP4_1", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_SW2A0_1", + "PCIE_SW2A0_0", "INT_INTERFACE_SW2A0" ], [ - "CLK_HROW_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" + "PCIE_SW2A1_0", + "INT_INTERFACE_SW2A1" ], [ - "CLK_HROW_CTRL0_1", - "INT_INTERFACE_CTRL0" + "PCIE_SW2A2_0", + "INT_INTERFACE_SW2A2" ], [ - "CLK_HROW_LH7_1", - "INT_INTERFACE_LH7" + "PCIE_SW2A3_0", + "INT_INTERFACE_SW2A3" ], [ - "CLK_HROW_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_IMUX3_1", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_ER1BEG1_1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SW4A0_1", + "PCIE_SW4A0_0", "INT_INTERFACE_SW4A0" ], [ - "CLK_HROW_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_IMUX22_1", - "INT_INTERFACE_IMUX22" - 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"INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_SW4A1_1", + "PCIE_SW4A1_0", "INT_INTERFACE_SW4A1" ], [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], 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"INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_LH6_1", - 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"CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_IMUX39_1", - "INT_INTERFACE_IMUX39" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "BRKH_DSP_L", - "DSP_L" - ], - "wire_pairs": [ - [ - "BRKH_DSP_BCIN7", - "DSP_0_BCIN7" - ], - [ - "BRKH_DSP_ACIN24", - "DSP_0_ACIN24" - ], - [ - "BRKH_DSP_PCIN46", - "DSP_0_PCIN46" - ], - [ - "BRKH_DSP_PCIN0", - "DSP_0_PCIN0" - ], - [ - "BRKH_DSP_PCIN2", - "DSP_0_PCIN2" - ], - [ - "BRKH_DSP_ACIN11", - "DSP_0_ACIN11" - ], - [ - "BRKH_DSP_ACIN5", - "DSP_0_ACIN5" - ], - [ - "BRKH_DSP_ACIN12", - "DSP_0_ACIN12" - ], - [ - "BRKH_DSP_PCIN7", - "DSP_0_PCIN7" - ], - [ - "BRKH_DSP_BCIN16", - "DSP_0_BCIN16" - ], - [ - "BRKH_DSP_PCIN10", - "DSP_0_PCIN10" - ], - [ - "BRKH_DSP_PCIN11", - "DSP_0_PCIN11" - ], - [ - "BRKH_DSP_PCIN26", - "DSP_0_PCIN26" - ], - [ - "BRKH_DSP_BCIN9", - "DSP_0_BCIN9" - ], - [ - "BRKH_DSP_BCIN1", - "DSP_0_BCIN1" - ], - [ - "BRKH_DSP_BCIN6", - "DSP_0_BCIN6" - ], - [ - "BRKH_DSP_PCIN3", - "DSP_0_PCIN3" - ], - [ - "BRKH_DSP_PCIN33", - "DSP_0_PCIN33" - ], - [ - "BRKH_DSP_PCIN6", - "DSP_0_PCIN6" - ], - [ - "BRKH_DSP_ACIN17", - "DSP_0_ACIN17" - ], - [ - "BRKH_DSP_PCIN31", - "DSP_0_PCIN31" - ], - [ - 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- ], - [ - "CFG_CENTER_WW4END2_12", - "INT_FEEDTHRU_2_WW4END2" - ], - [ - "CFG_CENTER_ER1BEG2_12", - "INT_FEEDTHRU_2_ER1BEG2" - ], - [ - "CFG_CENTER_EE2BEG0_12", - "INT_FEEDTHRU_2_EE2BEG0" - ], - [ - "CFG_CENTER_NW4END2_12", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_EE2A2_12", - "INT_FEEDTHRU_2_EE2A2" - ], - [ - "CFG_CENTER_EE4BEG2_12", - "INT_FEEDTHRU_2_EE4BEG2" - ], - [ - "CFG_CENTER_SW4END2_12", - "INT_FEEDTHRU_2_SW4END2" - ], - [ - "CFG_CENTER_NE4BEG2_12", - "INT_FEEDTHRU_2_NE4BEG2" - ], - [ - "CFG_CENTER_WW2END1_12", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_SE4BEG2_12", - "INT_FEEDTHRU_2_SE4BEG2" - ], - [ - "CFG_CENTER_EE2BEG2_12", - "INT_FEEDTHRU_2_EE2BEG2" - ], - [ - "CFG_CENTER_SW2A3_12", - "INT_FEEDTHRU_2_SW2A3" - ], - [ - "CFG_CENTER_EE4C1_12", - "INT_FEEDTHRU_2_EE4C1" - ], - [ - "CFG_CENTER_EE4B0_12", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_EE4B2_12", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_LH4_12", - "INT_FEEDTHRU_2_LH4" - ], - [ - "CFG_CENTER_SE2A0_12", - "INT_FEEDTHRU_2_SE2A0" - ], - [ - "CFG_CENTER_NE4C1_12", - "INT_FEEDTHRU_2_NE4C1" - ], - [ - "CFG_CENTER_WW4A0_12", - "INT_FEEDTHRU_2_WW4A0" - ], - [ - "CFG_CENTER_WW2A2_12", - "INT_FEEDTHRU_2_WW2A2" - ], - [ - "CFG_CENTER_SE2A3_12", - "INT_FEEDTHRU_2_SE2A3" - ], - [ - "CFG_CENTER_SW4A1_12", - "INT_FEEDTHRU_2_SW4A1" - ], - [ - "CFG_CENTER_LH2_12", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_WL1END0_12", - "INT_FEEDTHRU_2_WL1END0" - ], - [ - "CFG_CENTER_SE4C2_12", - "INT_FEEDTHRU_2_SE4C2" - ], - [ - "CFG_CENTER_SE4C3_12", - "INT_FEEDTHRU_2_SE4C3" - ], - [ - "CFG_CENTER_EE4BEG1_12", - "INT_FEEDTHRU_2_EE4BEG1" - ], - [ - "CFG_CENTER_WW4C1_12", - "INT_FEEDTHRU_2_WW4C1" - ], - [ - "CFG_CENTER_NE2A3_12", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_WW4A2_12", - "INT_FEEDTHRU_2_WW4A2" - ], - [ - "CFG_CENTER_NW2A2_12", - "INT_FEEDTHRU_2_NW2A2" - ], - [ - "CFG_CENTER_EE4A1_12", - "INT_FEEDTHRU_2_EE4A1" - ], - [ - "CFG_CENTER_WW4END0_12", - "INT_FEEDTHRU_2_WW4END0" - ], - [ - "CFG_CENTER_EE4B3_12", - "INT_FEEDTHRU_2_EE4B3" - ], - [ - "CFG_CENTER_EE4C0_12", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_LH9_12", - "INT_FEEDTHRU_2_LH9" - ], - [ - "CFG_CENTER_WW4END3_12", - "INT_FEEDTHRU_2_WW4END3" - ], - [ - "CFG_CENTER_EE4C2_12", - "INT_FEEDTHRU_2_EE4C2" - ], - [ - "CFG_CENTER_NW4A2_12", - "INT_FEEDTHRU_2_NW4A2" - ], - [ - "CFG_CENTER_WW2A1_12", - "INT_FEEDTHRU_2_WW2A1" - ], - [ - "CFG_CENTER_EE2A1_12", - "INT_FEEDTHRU_2_EE2A1" - ], - [ - "CFG_CENTER_LH8_12", - "INT_FEEDTHRU_2_LH8" - ], - [ - "CFG_CENTER_LH11_12", - "INT_FEEDTHRU_2_LH11" - ], - [ - "CFG_CENTER_NE4BEG0_12", - "INT_FEEDTHRU_2_NE4BEG0" - ], - [ - "CFG_CENTER_NW4A3_12", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_NW4END3_12", - "INT_FEEDTHRU_2_NW4END3" - ], - [ - "CFG_CENTER_WR1END3_12", - "INT_FEEDTHRU_2_WR1END3" - ], - [ - "CFG_CENTER_EE4A0_12", - "INT_FEEDTHRU_2_EE4A0" - ], - [ - "CFG_CENTER_NW2A3_12", - "INT_FEEDTHRU_2_NW2A3" - ], - [ - "CFG_CENTER_EL1BEG1_12", - "INT_FEEDTHRU_2_EL1BEG1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 2 - ], - "tile_types": [ - "GTX_CHANNEL_1", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTXE2_IMUX39_3", - "VBRK_EXT_IMUX39" - ], - [ - "GTXE2_IMUX37_3", - "VBRK_EXT_IMUX37" - ], - [ - "GTXE2_BYP6_3", - "VBRK_EXT_BYP6" - ], - [ - "GTXE2_LOGIC_OUTS_B20_3", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTXE2_IMUX23_3", - "VBRK_EXT_IMUX23" - ], - [ - "GTXE2_LOGIC_OUTS_B11_3", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTXE2_FAN4_3", - "VBRK_EXT_FAN4" - ], - [ - "GTXE2_IMUX9_3", - "VBRK_EXT_IMUX9" - ], - [ - "GTXE2_IMUX17_3", - "VBRK_EXT_IMUX17" - ], - [ - "GTXE2_IMUX21_3", - "VBRK_EXT_IMUX21" - ], - [ - "GTXE2_BYP3_3", - "VBRK_EXT_BYP3" - ], - [ - "GTXE2_IMUX11_3", - "VBRK_EXT_IMUX11" - ], - [ - "GTXE2_IMUX44_3", - "VBRK_EXT_IMUX44" - ], - [ - "GTXE2_BYP4_3", - "VBRK_EXT_BYP4" - ], - [ - "GTXE2_IMUX0_3", - "VBRK_EXT_IMUX0" - ], - [ - "GTXE2_IMUX33_3", - "VBRK_EXT_IMUX33" - ], - [ - "GTXE2_IMUX31_3", - "VBRK_EXT_IMUX31" - ], - [ - "GTXE2_FAN1_3", - "VBRK_EXT_FAN1" - ], - [ - "GTXE2_BYP5_3", - "VBRK_EXT_BYP5" - ], - [ - "GTXE2_IMUX4_3", - "VBRK_EXT_IMUX4" - ], - [ - "GTXE2_LOGIC_OUTS_B17_3", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTXE2_IMUX45_3", - "VBRK_EXT_IMUX45" - ], - [ - "GTXE2_LOGIC_OUTS_B22_3", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTXE2_LOGIC_OUTS_B15_3", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTXE2_FAN6_3", - "VBRK_EXT_FAN6" - ], - [ - "GTXE2_FAN2_3", - "VBRK_EXT_FAN2" - ], - [ - "GTXE2_LOGIC_OUTS_B21_3", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTXE2_LOGIC_OUTS_B19_3", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTXE2_FAN5_3", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_LOGIC_OUTS_B0_3", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTXE2_IMUX7_3", - "VBRK_EXT_IMUX7" - ], - [ - "GTXE2_IMUX30_3", - "VBRK_EXT_IMUX30" - ], - [ - "GTXE2_IMUX19_3", - "VBRK_EXT_IMUX19" - ], - [ - "GTXE2_IMUX3_3", - "VBRK_EXT_IMUX3" - ], - [ - "GTXE2_LOGIC_OUTS_B12_3", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTXE2_LOGIC_OUTS_B23_3", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTXE2_LOGIC_OUTS_B14_3", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTXE2_LOGIC_OUTS_B3_3", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTXE2_IMUX26_3", - "VBRK_EXT_IMUX26" - ], - [ - "GTXE2_CLK0_3", - "VBRK_EXT_CLK0" - ], - [ - "GTXE2_BYP1_3", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_IMUX12_3", - "VBRK_EXT_IMUX12" - ], - [ - "GTXE2_FAN7_3", - "VBRK_EXT_FAN7" - ], - [ - "GTXE2_IMUX27_3", - "VBRK_EXT_IMUX27" - ], - [ - "GTXE2_IMUX8_3", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX16_3", - "VBRK_EXT_IMUX16" - ], - [ - "GTXE2_IMUX46_3", - "VBRK_EXT_IMUX46" - ], - [ - "GTXE2_LOGIC_OUTS_B16_3", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTXE2_IMUX20_3", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_LOGIC_OUTS_B5_3", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTXE2_IMUX42_3", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_IMUX18_3", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_CLK1_3", - "VBRK_EXT_CLK1" - ], - [ - "GTXE2_LOGIC_OUTS_B8_3", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTXE2_IMUX43_3", - "VBRK_EXT_IMUX43" - ], - [ - "GTXE2_LOGIC_OUTS_B13_3", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_IMUX32_3", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_IMUX40_3", - "VBRK_EXT_IMUX40" - ], - [ - "GTXE2_IMUX29_3", - "VBRK_EXT_IMUX29" - ], - [ - "GTXE2_LOGIC_OUTS_B9_3", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTXE2_IMUX25_3", - "VBRK_EXT_IMUX25" - ], - [ - "GTXE2_IMUX10_3", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_CTRL1_3", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_LOGIC_OUTS_B4_3", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTXE2_FAN0_3", - "VBRK_EXT_FAN0" - ], - [ - "GTXE2_BYP2_3", - "VBRK_EXT_BYP2" - ], - [ - "GTXE2_LOGIC_OUTS_B2_3", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTXE2_IMUX1_3", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_IMUX28_3", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_IMUX38_3", - "VBRK_EXT_IMUX38" - ], - [ - "GTXE2_LOGIC_OUTS_B7_3", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTXE2_CTRL0_3", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_IMUX41_3", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_IMUX13_3", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_LOGIC_OUTS_B1_3", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_IMUX14_3", - "VBRK_EXT_IMUX14" + "PCIE_WW2END3_0", + "INT_INTERFACE_WW2END3" ], [ - "GTXE2_BYP7_3", - "VBRK_EXT_BYP7" + "PCIE_WW4A0_0", + "INT_INTERFACE_WW4A0" ], [ - "GTXE2_FAN3_3", - "VBRK_EXT_FAN3" + "PCIE_WW4A1_0", + "INT_INTERFACE_WW4A1" ], [ - "GTXE2_LOGIC_OUTS_B6_3", - "VBRK_EXT_LOGIC_OUTS_B6" + "PCIE_WW4A2_0", + "INT_INTERFACE_WW4A2" ], [ - "GTXE2_LOGIC_OUTS_B10_3", - "VBRK_EXT_LOGIC_OUTS_B10" + "PCIE_WW4A3_0", + "INT_INTERFACE_WW4A3" ], [ - "GTXE2_IMUX2_3", - "VBRK_EXT_IMUX2" + "PCIE_WW4B0_0", + "INT_INTERFACE_WW4B0" ], [ - "GTXE2_BYP0_3", - "VBRK_EXT_BYP0" + "PCIE_WW4B1_0", + "INT_INTERFACE_WW4B1" ], [ - "GTXE2_IMUX6_3", - "VBRK_EXT_IMUX6" + "PCIE_WW4B2_0", + "INT_INTERFACE_WW4B2" ], [ - "GTXE2_IMUX34_3", - "VBRK_EXT_IMUX34" + "PCIE_WW4B3_0", + "INT_INTERFACE_WW4B3" ], [ - "GTXE2_IMUX5_3", - "VBRK_EXT_IMUX5" + "PCIE_WW4C0_0", + "INT_INTERFACE_WW4C0" ], [ - "GTXE2_IMUX47_3", - "VBRK_EXT_IMUX47" + "PCIE_WW4C1_0", + "INT_INTERFACE_WW4C1" ], [ - "GTXE2_IMUX36_3", - "VBRK_EXT_IMUX36" + "PCIE_WW4C2_0", + "INT_INTERFACE_WW4C2" ], [ - "GTXE2_IMUX22_3", - "VBRK_EXT_IMUX22" + "PCIE_WW4C3_0", + "INT_INTERFACE_WW4C3" ], [ - "GTXE2_IMUX35_3", - "VBRK_EXT_IMUX35" + "PCIE_WW4END0_0", + "INT_INTERFACE_WW4END0" ], [ - "GTXE2_IMUX15_3", - "VBRK_EXT_IMUX15" + "PCIE_WW4END1_0", + "INT_INTERFACE_WW4END1" ], [ - "GTXE2_IMUX24_3", - "VBRK_EXT_IMUX24" + "PCIE_WW4END2_0", + "INT_INTERFACE_WW4END2" ], [ - "GTXE2_LOGIC_OUTS_B18_3", - "VBRK_EXT_LOGIC_OUTS_B18" + "PCIE_WW4END3_0", + "INT_INTERFACE_WW4END3" ] ] }, @@ -85965,4405 +462541,7953 @@ -10 ], "tile_types": [ - "CFG_CENTER_MID", - "CFG_CENTER_TOP" + "PCIE_BOT", + "PCIE_TOP" ], "wire_pairs": [ [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA31" + "PCIE_CFGAERROOTERRCORRERRRECEIVED", + "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA14" + "PCIE_CFGAERROOTERRFATALERRRECEIVED", + "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA24" + "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", + "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA13" + "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", + "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA11" + "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", + "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA19" + "PCIE_CFGCOMMANDBUSMASTERENABLE", + "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA28" + "PCIE_CFGCOMMANDINTERRUPTDISABLE", + "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA25" + "PCIE_CFGCOMMANDIOENABLE", + "PCIE_TOP_CFGCOMMANDIOENABLE" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA12" + "PCIE_CFGCOMMANDMEMENABLE", + "PCIE_TOP_CFGCOMMANDMEMENABLE" ], [ - "CFG_CENTER_MID_ICAP1_CLK", - "CFG_CENTER_TOP_ICAP1_CLK" + "PCIE_CFGDEVCONTROL2ARIFORWARDEN", + "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA22" + "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA16" + "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", + "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA17" + "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA29" + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA30" + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA23" + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2" ], [ - "CFG_CENTER_MID_DNA_PORT_CLK", - "CFG_CENTER_TOP_DNA_PORT_CLK" + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA20" + "PCIE_CFGDEVCONTROL2IDOCPLEN", + "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA26" + "PCIE_CFGDEVCONTROL2IDOREQEN", + "PCIE_TOP_CFGDEVCONTROL2IDOREQEN" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA21" + "PCIE_CFGDEVCONTROL2LTREN", + "PCIE_TOP_CFGDEVCONTROL2LTREN" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA15" + "PCIE_CFGDEVID0", + "PCIE_TOP_CFGDEVID0" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA18" + "PCIE_CFGDEVID1", + "PCIE_TOP_CFGDEVID1" ], [ - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA27" + "PCIE_CFGDEVID2", + "PCIE_TOP_CFGDEVID2" + ], + [ + "PCIE_CFGDEVID3", + "PCIE_TOP_CFGDEVID3" + ], + [ + "PCIE_CFGDEVID4", + "PCIE_TOP_CFGDEVID4" + ], + [ + "PCIE_CFGDEVID5", + "PCIE_TOP_CFGDEVID5" + ], + [ + "PCIE_CFGDEVID6", + "PCIE_TOP_CFGDEVID6" + ], + [ + "PCIE_CFGDEVID7", + "PCIE_TOP_CFGDEVID7" + ], + [ + "PCIE_CFGDEVID8", + "PCIE_TOP_CFGDEVID8" + ], + [ + "PCIE_CFGDEVID9", + "PCIE_TOP_CFGDEVID9" + ], + [ + "PCIE_CFGDEVID10", + "PCIE_TOP_CFGDEVID10" + ], + [ + "PCIE_CFGDEVID11", + "PCIE_TOP_CFGDEVID11" + ], + [ + "PCIE_CFGDEVID12", + "PCIE_TOP_CFGDEVID12" + ], + [ + "PCIE_CFGDEVID13", + "PCIE_TOP_CFGDEVID13" + ], + [ + "PCIE_CFGDEVID14", + "PCIE_TOP_CFGDEVID14" + ], + [ + "PCIE_CFGDEVID15", + "PCIE_TOP_CFGDEVID15" + ], + [ + "PCIE_CFGDSN57", + "PCIE_TOP_CFGDSN57" + ], + [ + "PCIE_CFGDSN58", + "PCIE_TOP_CFGDSN58" + ], + [ + "PCIE_CFGDSN59", + "PCIE_TOP_CFGDSN59" + ], + [ + "PCIE_CFGDSN60", + "PCIE_TOP_CFGDSN60" + ], + [ + "PCIE_CFGDSN61", + "PCIE_TOP_CFGDSN61" + ], + [ + "PCIE_CFGDSN62", + "PCIE_TOP_CFGDSN62" + ], + [ + "PCIE_CFGDSN63", + "PCIE_TOP_CFGDSN63" + ], + [ + "PCIE_CFGERRAERHEADERLOG0", + "PCIE_TOP_CFGERRAERHEADERLOG0" + ], + [ + "PCIE_CFGERRAERHEADERLOG1", + "PCIE_TOP_CFGERRAERHEADERLOG1" + ], + [ + "PCIE_CFGERRAERHEADERLOG2", + "PCIE_TOP_CFGERRAERHEADERLOG2" + ], + [ + "PCIE_CFGERRAERHEADERLOG3", + "PCIE_TOP_CFGERRAERHEADERLOG3" + ], + [ + "PCIE_CFGERRAERHEADERLOG4", + "PCIE_TOP_CFGERRAERHEADERLOG4" + ], + [ + "PCIE_CFGERRAERHEADERLOG5", + "PCIE_TOP_CFGERRAERHEADERLOG5" + ], + [ + "PCIE_CFGERRAERHEADERLOG6", + "PCIE_TOP_CFGERRAERHEADERLOG6" + ], + [ + "PCIE_CFGERRAERHEADERLOG7", + "PCIE_TOP_CFGERRAERHEADERLOG7" + ], + [ + "PCIE_CFGERRAERHEADERLOG8", + "PCIE_TOP_CFGERRAERHEADERLOG8" + ], + [ + "PCIE_CFGERRAERHEADERLOG9", + "PCIE_TOP_CFGERRAERHEADERLOG9" + ], + [ + "PCIE_CFGERRAERHEADERLOG10", + "PCIE_TOP_CFGERRAERHEADERLOG10" + ], + [ + "PCIE_CFGERRAERHEADERLOG11", + "PCIE_TOP_CFGERRAERHEADERLOG11" + ], + [ + "PCIE_CFGERRLOCKEDN", + "PCIE_TOP_CFGERRLOCKEDN" + ], + [ + "PCIE_CFGERRNORECOVERYN", + "PCIE_TOP_CFGERRNORECOVERYN" + ], + [ + "PCIE_CFGERRTLPCPLHEADER26", + "PCIE_TOP_CFGERRTLPCPLHEADER26" + ], + [ + "PCIE_CFGERRTLPCPLHEADER27", + "PCIE_TOP_CFGERRTLPCPLHEADER27" + ], + [ + "PCIE_CFGERRTLPCPLHEADER28", + "PCIE_TOP_CFGERRTLPCPLHEADER28" + ], + [ + "PCIE_CFGERRTLPCPLHEADER29", + "PCIE_TOP_CFGERRTLPCPLHEADER29" + ], + [ + "PCIE_CFGERRTLPCPLHEADER30", + "PCIE_TOP_CFGERRTLPCPLHEADER30" + ], + [ + "PCIE_CFGERRTLPCPLHEADER31", + "PCIE_TOP_CFGERRTLPCPLHEADER31" + ], + [ + "PCIE_CFGERRTLPCPLHEADER32", + "PCIE_TOP_CFGERRTLPCPLHEADER32" + ], + [ + "PCIE_CFGERRTLPCPLHEADER33", + "PCIE_TOP_CFGERRTLPCPLHEADER33" + ], + [ + "PCIE_CFGERRTLPCPLHEADER34", + "PCIE_TOP_CFGERRTLPCPLHEADER34" + ], + [ + "PCIE_CFGERRTLPCPLHEADER35", + "PCIE_TOP_CFGERRTLPCPLHEADER35" + ], + [ + "PCIE_CFGERRTLPCPLHEADER36", + "PCIE_TOP_CFGERRTLPCPLHEADER36" + ], + [ + "PCIE_CFGERRTLPCPLHEADER37", + "PCIE_TOP_CFGERRTLPCPLHEADER37" + ], + [ + "PCIE_CFGERRTLPCPLHEADER38", + "PCIE_TOP_CFGERRTLPCPLHEADER38" + ], + [ + "PCIE_CFGERRTLPCPLHEADER39", + "PCIE_TOP_CFGERRTLPCPLHEADER39" + ], + [ + "PCIE_CFGERRTLPCPLHEADER40", + "PCIE_TOP_CFGERRTLPCPLHEADER40" + ], + [ + "PCIE_CFGERRTLPCPLHEADER41", + "PCIE_TOP_CFGERRTLPCPLHEADER41" + ], + [ + "PCIE_CFGERRTLPCPLHEADER42", + "PCIE_TOP_CFGERRTLPCPLHEADER42" + ], + [ + "PCIE_CFGERRTLPCPLHEADER43", + "PCIE_TOP_CFGERRTLPCPLHEADER43" + ], + [ + "PCIE_CFGERRTLPCPLHEADER44", + "PCIE_TOP_CFGERRTLPCPLHEADER44" + ], + [ + "PCIE_CFGERRTLPCPLHEADER45", + "PCIE_TOP_CFGERRTLPCPLHEADER45" + ], + [ + "PCIE_CFGERRTLPCPLHEADER46", + "PCIE_TOP_CFGERRTLPCPLHEADER46" + ], + [ + "PCIE_CFGERRTLPCPLHEADER47", + "PCIE_TOP_CFGERRTLPCPLHEADER47" + ], + [ + "PCIE_CFGINTERRUPTDI0", + "PCIE_TOP_CFGINTERRUPTDI0" + ], + [ + "PCIE_CFGINTERRUPTN", + "PCIE_TOP_CFGINTERRUPTN" + ], + [ + "PCIE_CFGLINKCONTROLASPMCONTROL1", + "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1" + ], + [ + "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN" + ], + [ + "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", + "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN" + ], + [ + "PCIE_CFGLINKCONTROLCLOCKPMEN", + "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN" + ], + [ + "PCIE_CFGLINKCONTROLCOMMONCLOCK", + "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK" + ], + [ + "PCIE_CFGLINKCONTROLEXTENDEDSYNC", + "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC" + ], + [ + "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", + "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS" + ], + [ + "PCIE_CFGLINKCONTROLLINKDISABLE", + "PCIE_TOP_CFGLINKCONTROLLINKDISABLE" + ], + [ + "PCIE_CFGLINKCONTROLRCB", + "PCIE_TOP_CFGLINKCONTROLRCB" + ], + [ + "PCIE_CFGLINKCONTROLRETRAINLINK", + "PCIE_TOP_CFGLINKCONTROLRETRAINLINK" + ], + [ + "PCIE_CFGMGMTDO16", + "PCIE_TOP_CFGMGMTDO16" + ], + [ + "PCIE_CFGMGMTDO17", + "PCIE_TOP_CFGMGMTDO17" + ], + [ + "PCIE_CFGMGMTDO18", + "PCIE_TOP_CFGMGMTDO18" + ], + [ + "PCIE_CFGMGMTDO19", + "PCIE_TOP_CFGMGMTDO19" + ], + [ + "PCIE_CFGMGMTDO20", + "PCIE_TOP_CFGMGMTDO20" + ], + [ + "PCIE_CFGMGMTDO21", + "PCIE_TOP_CFGMGMTDO21" + ], + [ + "PCIE_CFGMGMTDO22", + "PCIE_TOP_CFGMGMTDO22" + ], + [ + "PCIE_CFGMGMTDO23", + "PCIE_TOP_CFGMGMTDO23" + ], + [ + "PCIE_CFGMGMTDO24", + "PCIE_TOP_CFGMGMTDO24" + ], + [ + "PCIE_CFGMGMTDO25", + "PCIE_TOP_CFGMGMTDO25" + ], + [ + "PCIE_CFGMGMTDO26", + "PCIE_TOP_CFGMGMTDO26" + ], + [ + "PCIE_CFGMGMTDO27", + "PCIE_TOP_CFGMGMTDO27" + ], + [ + "PCIE_CFGMGMTDO28", + "PCIE_TOP_CFGMGMTDO28" + ], + [ + "PCIE_CFGMGMTDO29", + "PCIE_TOP_CFGMGMTDO29" + ], + [ + "PCIE_CFGMGMTDO30", + "PCIE_TOP_CFGMGMTDO30" + ], + [ + "PCIE_CFGPCIELINKSTATE1", + "PCIE_TOP_CFGPCIELINKSTATE1" + ], + [ + "PCIE_CFGPCIELINKSTATE2", + "PCIE_TOP_CFGPCIELINKSTATE2" + ], + [ + "PCIE_CFGPMCSRPMEEN", + "PCIE_TOP_CFGPMCSRPMEEN" + ], + [ + "PCIE_CFGPMCSRPMESTATUS", + "PCIE_TOP_CFGPMCSRPMESTATUS" + ], + [ + "PCIE_CFGPMCSRPOWERSTATE0", + "PCIE_TOP_CFGPMCSRPOWERSTATE0" + ], + [ + "PCIE_CFGPMCSRPOWERSTATE1", + "PCIE_TOP_CFGPMCSRPOWERSTATE1" + ], + [ + "PCIE_CFGPMRCVASREQL1N", + "PCIE_TOP_CFGPMRCVASREQL1N" + ], + [ + "PCIE_CFGPMRCVENTERL1N", + "PCIE_TOP_CFGPMRCVENTERL1N" + ], + [ + "PCIE_CFGPMRCVENTERL23N", + "PCIE_TOP_CFGPMRCVENTERL23N" + ], + [ + "PCIE_CFGPMRCVREQACKN", + "PCIE_TOP_CFGPMRCVREQACKN" + ], + [ + "PCIE_CFGTRANSACTION", + "PCIE_TOP_CFGTRANSACTION" + ], + [ + "PCIE_CFGTRANSACTIONADDR0", + "PCIE_TOP_CFGTRANSACTIONADDR0" + ], + [ + "PCIE_CFGTRANSACTIONADDR1", + "PCIE_TOP_CFGTRANSACTIONADDR1" + ], + [ + "PCIE_CFGTRANSACTIONADDR2", + "PCIE_TOP_CFGTRANSACTIONADDR2" + ], + [ + "PCIE_CFGTRANSACTIONADDR3", + "PCIE_TOP_CFGTRANSACTIONADDR3" + ], + [ + "PCIE_CFGTRANSACTIONADDR4", + "PCIE_TOP_CFGTRANSACTIONADDR4" + ], + [ + "PCIE_CFGTRANSACTIONADDR5", + "PCIE_TOP_CFGTRANSACTIONADDR5" + ], + [ + "PCIE_CFGTRANSACTIONADDR6", + "PCIE_TOP_CFGTRANSACTIONADDR6" + ], + [ + "PCIE_CFGTRANSACTIONTYPE", + "PCIE_TOP_CFGTRANSACTIONTYPE" + ], + [ + "PCIE_CFGVCTCVCMAP0", + "PCIE_TOP_CFGVCTCVCMAP0" + ], + [ + "PCIE_CFGVCTCVCMAP1", + "PCIE_TOP_CFGVCTCVCMAP1" + ], + [ + "PCIE_CFGVCTCVCMAP2", + "PCIE_TOP_CFGVCTCVCMAP2" + ], + [ + "PCIE_CFGVCTCVCMAP3", + "PCIE_TOP_CFGVCTCVCMAP3" + ], + [ + "PCIE_CFGVCTCVCMAP4", + "PCIE_TOP_CFGVCTCVCMAP4" + ], + [ + "PCIE_CFGVCTCVCMAP5", + "PCIE_TOP_CFGVCTCVCMAP5" + ], + [ + "PCIE_CFGVCTCVCMAP6", + "PCIE_TOP_CFGVCTCVCMAP6" + ], + [ + "PCIE_CFGVENDID0", + "PCIE_TOP_CFGVENDID0" + ], + [ + "PCIE_DBGMODE0", + "PCIE_TOP_DBGMODE0" + ], + [ + "PCIE_DBGVECA0", + "PCIE_TOP_DBGVECA0" + ], + [ + "PCIE_DBGVECA1", + "PCIE_TOP_DBGVECA1" + ], + [ + "PCIE_DBGVECA2", + "PCIE_TOP_DBGVECA2" + ], + [ + "PCIE_DBGVECA3", + "PCIE_TOP_DBGVECA3" + ], + [ + "PCIE_DBGVECA4", + "PCIE_TOP_DBGVECA4" + ], + [ + "PCIE_DBGVECA5", + "PCIE_TOP_DBGVECA5" + ], + [ + "PCIE_DBGVECA6", + "PCIE_TOP_DBGVECA6" + ], + [ + "PCIE_DBGVECA7", + "PCIE_TOP_DBGVECA7" + ], + [ + "PCIE_DBGVECA8", + "PCIE_TOP_DBGVECA8" + ], + [ + "PCIE_DBGVECA9", + "PCIE_TOP_DBGVECA9" + ], + [ + "PCIE_DBGVECA10", + "PCIE_TOP_DBGVECA10" + ], + [ + "PCIE_DBGVECA11", + "PCIE_TOP_DBGVECA11" + ], + [ + "PCIE_DBGVECA12", + "PCIE_TOP_DBGVECA12" + ], + [ + "PCIE_DBGVECA13", + "PCIE_TOP_DBGVECA13" + ], + [ + "PCIE_DBGVECA14", + "PCIE_TOP_DBGVECA14" + ], + [ + "PCIE_DBGVECA15", + "PCIE_TOP_DBGVECA15" + ], + [ + "PCIE_DBGVECA16", + "PCIE_TOP_DBGVECA16" + ], + [ + "PCIE_DBGVECA17", + "PCIE_TOP_DBGVECA17" + ], + [ + "PCIE_DBGVECA18", + "PCIE_TOP_DBGVECA18" + ], + [ + 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"PCIE_LH8_2" ], [ - "CMT_FIFO_L_BYP4_7", - "INT_INTERFACE_BYP4" + "INT_INTERFACE_LH9", + "PCIE_LH9_2" ], [ - "CMT_FIFO_L_CLK1_7", - "INT_INTERFACE_CLK1" + "INT_INTERFACE_LH10", + "PCIE_LH10_2" ], [ - "CMT_FIFO_L_IMUX16_7", - "INT_INTERFACE_IMUX16" + "INT_INTERFACE_LH11", + "PCIE_LH11_2" ], [ - "CMT_FIFO_L_FAN2_7", - "INT_INTERFACE_FAN2" + "INT_INTERFACE_LH12", + "PCIE_LH12_2" ], [ - "CMT_FIFO_SW2A0_7", - "INT_INTERFACE_SW2A0" + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "PCIE_LOGIC_OUTS_B0_L_2" ], [ - "CMT_FIFO_NE4BEG1_7", - "INT_INTERFACE_NE4BEG1" + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "PCIE_LOGIC_OUTS_B1_L_2" ], [ - "CMT_FIFO_WL1END1_7", - "INT_INTERFACE_WL1END1" + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "PCIE_LOGIC_OUTS_B2_L_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS1_7", - "INT_INTERFACE_LOGIC_OUTS_B1" + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "PCIE_LOGIC_OUTS_B3_L_2" ], [ - "CMT_FIFO_SW4A1_7", - "INT_INTERFACE_SW4A1" + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "PCIE_LOGIC_OUTS_B4_L_2" ], [ - "CMT_FIFO_L_IMUX13_7", - "INT_INTERFACE_IMUX13" + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "PCIE_LOGIC_OUTS_B5_L_2" ], [ - "CMT_FIFO_EE4B3_7", - "INT_INTERFACE_EE4B3" + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "PCIE_LOGIC_OUTS_B6_L_2" ], [ - "CMT_FIFO_EE2BEG2_7", - "INT_INTERFACE_EE2BEG2" + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "PCIE_LOGIC_OUTS_B7_L_2" ], [ - "CMT_FIFO_L_IMUX34_7", - "INT_INTERFACE_IMUX34" + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "PCIE_LOGIC_OUTS_B8_L_2" ], [ - "CMT_FIFO_NW4A3_7", - "INT_INTERFACE_NW4A3" + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "PCIE_LOGIC_OUTS_B9_L_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS10_7", - "INT_INTERFACE_LOGIC_OUTS_B10" + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "PCIE_LOGIC_OUTS_B10_L_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS0_7", - "INT_INTERFACE_LOGIC_OUTS_B0" + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "PCIE_LOGIC_OUTS_B11_L_2" ], [ - "CMT_FIFO_L_IMUX33_7", - "INT_INTERFACE_IMUX33" + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "PCIE_LOGIC_OUTS_B12_L_2" ], [ - "CMT_FIFO_L_IMUX3_7", - "INT_INTERFACE_IMUX3" + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "PCIE_LOGIC_OUTS_B13_L_2" ], [ - "CMT_FIFO_SE4BEG1_7", - "INT_INTERFACE_SE4BEG1" + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "PCIE_LOGIC_OUTS_B14_L_2" ], [ - "CMT_FIFO_NE2A0_7", - "INT_INTERFACE_NE2A0" + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "PCIE_LOGIC_OUTS_B15_L_2" ], [ - "CMT_FIFO_SW4END2_7", - "INT_INTERFACE_SW4END2" + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "PCIE_LOGIC_OUTS_B16_L_2" ], [ - "CMT_FIFO_L_IMUX43_7", - "INT_INTERFACE_IMUX43" + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "PCIE_LOGIC_OUTS_B17_L_2" ], [ - "CMT_FIFO_WL1END3_7", - "INT_INTERFACE_WL1END3" + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "PCIE_LOGIC_OUTS_B18_L_2" ], [ - "CMT_FIFO_L_IMUX10_7", - "INT_INTERFACE_IMUX10" + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "PCIE_LOGIC_OUTS_B19_L_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS22_7", - "INT_INTERFACE_LOGIC_OUTS_B22" + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "PCIE_LOGIC_OUTS_B20_L_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS15_7", - "INT_INTERFACE_LOGIC_OUTS_B15" + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "PCIE_LOGIC_OUTS_B21_L_2" ], [ - "CMT_FIFO_WW4B1_7", - "INT_INTERFACE_WW4B1" + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "PCIE_LOGIC_OUTS_B22_L_2" ], [ - "CMT_FIFO_SW2A3_7", - "INT_INTERFACE_SW2A3" + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "PCIE_LOGIC_OUTS_B23_L_2" ], [ - "CMT_FIFO_L_FAN5_7", - "INT_INTERFACE_FAN5" + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_2" ], [ - "CMT_FIFO_WW4B0_7", - "INT_INTERFACE_WW4B0" + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_2" ], [ - "CMT_FIFO_SE4C0_7", - "INT_INTERFACE_SE4C0" + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_2" ], [ - "CMT_FIFO_L_IMUX45_7", - "INT_INTERFACE_IMUX45" + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_2" ], [ - "CMT_FIFO_L_IMUX27_7", - "INT_INTERFACE_IMUX27" + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_2" ], [ - "CMT_FIFO_L_IMUX17_7", - "INT_INTERFACE_IMUX17" + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_2" ], [ - "CMT_FIFO_WW4A3_7", - "INT_INTERFACE_WW4A3" + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS7_7", - "INT_INTERFACE_LOGIC_OUTS_B7" + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_2" ], [ - "CMT_FIFO_L_IMUX35_7", - "INT_INTERFACE_IMUX35" + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_2" ], [ - "CMT_FIFO_WR1END1_7", - "INT_INTERFACE_WR1END1" + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_2" ], [ - "CMT_FIFO_PHASER_TO_IO_ICLK_7", - "INT_INTERFACE_PHASER_TO_IO_ICLK" + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_2" ], [ - "CMT_FIFO_EE4BEG3_7", - "INT_INTERFACE_EE4BEG3" + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_2" ], [ - "CMT_FIFO_ER1BEG3_7", - "INT_INTERFACE_ER1BEG3" + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_2" ], [ - "CMT_FIFO_L_BYP0_7", - "INT_INTERFACE_BYP0" + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_2" ], [ - "CMT_FIFO_SW4A0_7", - "INT_INTERFACE_SW4A0" + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_2" ], [ - "CMT_FIFO_L_IMUX8_7", - "INT_INTERFACE_IMUX8" + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS4_7", - "INT_INTERFACE_LOGIC_OUTS_B4" + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_2" ], [ - "CMT_FIFO_L_FAN0_7", - "INT_INTERFACE_FAN0" + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_2" ], [ - "CMT_FIFO_ER1BEG2_7", - "INT_INTERFACE_ER1BEG2" + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_2" ], [ - "CMT_FIFO_L_CTRL0_7", - "INT_INTERFACE_CTRL0" + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_2" ], [ - "CMT_FIFO_L_IMUX2_7", - "INT_INTERFACE_IMUX2" + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_2" ], [ - "CMT_FIFO_LH6_7", - "INT_INTERFACE_LH6" + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_2" ], [ - "CMT_FIFO_LH1_7", - "INT_INTERFACE_LH1" + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_2" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90" + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_2" ], [ - "CMT_FIFO_L_IMUX36_7", - "INT_INTERFACE_IMUX36" + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_2" ], [ - "CMT_FIFO_L_BYP1_7", - "INT_INTERFACE_BYP1" + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_2" ], [ - "CMT_FIFO_WW4C3_7", - "INT_INTERFACE_WW4C3" + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_2" ], [ - "CMT_FIFO_SE2A0_7", - "INT_INTERFACE_SE2A0" + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_2" ], [ - "CMT_FIFO_L_FAN7_7", - "INT_INTERFACE_FAN7" + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_2" ], [ - "CMT_FIFO_WW4C2_7", - "INT_INTERFACE_WW4C2" + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_2" ], [ - "CMT_FIFO_SW4A3_7", - "INT_INTERFACE_SW4A3" + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_2" ], [ - "CMT_FIFO_EE4B1_7", - "INT_INTERFACE_EE4B1" + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_2" ], [ - "CMT_FIFO_WW4A1_7", - "INT_INTERFACE_WW4A1" + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_2" ], [ - "CMT_FIFO_LH7_7", - "INT_INTERFACE_LH7" + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_2" ], [ - "CMT_FIFO_EE4C1_7", - "INT_INTERFACE_EE4C1" + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_2" ], [ - "CMT_FIFO_L_IMUX40_7", - "INT_INTERFACE_IMUX40" + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_2" ], [ - "CMT_FIFO_WR1END3_7", - "INT_INTERFACE_WR1END3" + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_2" ], [ - "CMT_FIFO_LH4_7", - "INT_INTERFACE_LH4" + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_2" ], [ - "CMT_FIFO_WW4B3_7", - "INT_INTERFACE_WW4B3" + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_2" ], [ - "CMT_FIFO_NW2A0_7", - "INT_INTERFACE_NW2A0" + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_2" ], [ - "CMT_FIFO_EE4C3_7", - "INT_INTERFACE_EE4C3" + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_2" ], [ - "CMT_FIFO_EE2BEG3_7", - "INT_INTERFACE_EE2BEG3" + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_2" ], [ - "CMT_FIFO_SW2A2_7", - "INT_INTERFACE_SW2A2" + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_2" ], [ - "CMT_FIFO_SE4BEG3_7", - "INT_INTERFACE_SE4BEG3" + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS21_7", - "INT_INTERFACE_LOGIC_OUTS_B21" + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_2" ], [ - "CMT_FIFO_SE4C2_7", - "INT_INTERFACE_SE4C2" + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_2" ], [ - "CMT_FIFO_EE2A2_7", - "INT_INTERFACE_EE2A2" + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_2" ], [ - "CMT_FIFO_LH2_7", - "INT_INTERFACE_LH2" + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_2" ], [ - "CMT_FIFO_L_IMUX31_7", - "INT_INTERFACE_IMUX31" + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS9_7", - "INT_INTERFACE_LOGIC_OUTS_B9" + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_2" ], [ - "CMT_FIFO_L_IMUX41_7", - "INT_INTERFACE_IMUX41" + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_2" ], [ - "CMT_FIFO_L_IMUX23_7", - "INT_INTERFACE_IMUX23" + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_2" ], [ - "CMT_FIFO_L_BYP3_7", - "INT_INTERFACE_BYP3" + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_2" ], [ - "CMT_FIFO_WW4A0_7", - "INT_INTERFACE_WW4A0" + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_2" ], [ - "CMT_FIFO_NW4A2_7", - "INT_INTERFACE_NW4A2" + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_2" ], [ - "CMT_FIFO_WW4END1_7", - "INT_INTERFACE_WW4END1" + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_2" ], [ - "CMT_FIFO_WW4END0_7", - "INT_INTERFACE_WW4END0" + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS14_7", - "INT_INTERFACE_LOGIC_OUTS_B14" + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_2" ], [ - "CMT_FIFO_NW4END0_7", - "INT_INTERFACE_NW4END0" + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_2" ], [ - "CMT_FIFO_L_BYP7_7", - "INT_INTERFACE_BYP7" + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_2" ], [ - "CMT_FIFO_WW2A2_7", - "INT_INTERFACE_WW2A2" + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_2" ], [ - "CMT_FIFO_NE4C0_7", - "INT_INTERFACE_NE4C0" + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_2" ], [ - "CMT_FIFO_L_IMUX25_7", - "INT_INTERFACE_IMUX25" + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_2" ], [ - "CMT_FIFO_EE4A0_7", - "INT_INTERFACE_EE4A0" + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_2" ], [ - "CMT_FIFO_EE4C0_7", - "INT_INTERFACE_EE4C0" + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_2" ], [ - "CMT_FIFO_WL1END2_7", - "INT_INTERFACE_WL1END2" + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_2" ], [ - "CMT_FIFO_EE4A2_7", - "INT_INTERFACE_EE4A2" + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS5_7", - "INT_INTERFACE_LOGIC_OUTS_B5" + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_2" ], [ - "CMT_FIFO_L_IMUX24_7", - "INT_INTERFACE_IMUX24" + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS3_7", - "INT_INTERFACE_LOGIC_OUTS_B3" + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS11_7", - "INT_INTERFACE_LOGIC_OUTS_B11" + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_2" ], [ - "CMT_FIFO_NE4C3_7", - "INT_INTERFACE_NE4C3" + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS8_7", - "INT_INTERFACE_LOGIC_OUTS_B8" + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_2" ], [ - "CMT_FIFO_WW4C0_7", - "INT_INTERFACE_WW4C0" + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_2" ], [ - "CMT_FIFO_LH8_7", - "INT_INTERFACE_LH8" + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_2" ], [ - "CMT_FIFO_EE4A3_7", - "INT_INTERFACE_EE4A3" + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_2" ], [ - "CMT_FIFO_L_IMUX46_7", - "INT_INTERFACE_IMUX46" + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_2" ], [ - "CMT_FIFO_L_IMUX44_7", - "INT_INTERFACE_IMUX44" + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_2" ], [ - "CMT_FIFO_EE4B2_7", - "INT_INTERFACE_EE4B2" + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_2" ], [ - "CMT_FIFO_WW2A3_7", - "INT_INTERFACE_WW2A3" + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_2" ], [ - "CMT_FIFO_NW2A2_7", - "INT_INTERFACE_NW2A2" + "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "PCIE_IMUX0_L_2" ], [ - "CMT_FIFO_L_BYP2_7", - "INT_INTERFACE_BYP2" + "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "PCIE_IMUX1_L_2" ], [ - "CMT_FIFO_EE4BEG0_7", - "INT_INTERFACE_EE4BEG0" + "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "PCIE_IMUX2_L_2" ], [ - "CMT_FIFO_WR1END2_7", - "INT_INTERFACE_WR1END2" + "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "PCIE_IMUX3_L_2" ], [ - "CMT_FIFO_SW4END3_7", - "INT_INTERFACE_SW4END3" + "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "PCIE_IMUX4_L_2" ], [ - "CMT_FIFO_NW2A1_7", - "INT_INTERFACE_NW2A1" + "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "PCIE_IMUX5_L_2" ], [ - "CMT_FIFO_WL1END0_7", - "INT_INTERFACE_WL1END0" + "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "PCIE_IMUX6_L_2" ], [ - "CMT_FIFO_WW4A2_7", - "INT_INTERFACE_WW4A2" + "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "PCIE_IMUX7_L_2" ], [ - "CMT_FIFO_EE2BEG1_7", - "INT_INTERFACE_EE2BEG1" + "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "PCIE_IMUX8_L_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS6_7", - "INT_INTERFACE_LOGIC_OUTS_B6" + "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "PCIE_IMUX9_L_2" ], [ - "CMT_FIFO_WW2END2_7", - "INT_INTERFACE_WW2END2" + "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "PCIE_IMUX10_L_2" ], [ - "CMT_FIFO_LH12_7", - "INT_INTERFACE_LH12" + "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "PCIE_IMUX11_L_2" ], [ - "CMT_FIFO_WW4END2_7", - "INT_INTERFACE_WW4END2" + "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "PCIE_IMUX12_L_2" ], [ - "CMT_FIFO_LH3_7", - "INT_INTERFACE_LH3" + "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "PCIE_IMUX13_L_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS12_7", - "INT_INTERFACE_LOGIC_OUTS_B12" + "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "PCIE_IMUX14_L_2" ], [ - "CMT_FIFO_EE2A3_7", - "INT_INTERFACE_EE2A3" + "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "PCIE_IMUX15_L_2" ], [ - "CMT_FIFO_L_IMUX26_7", - "INT_INTERFACE_IMUX26" + "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "PCIE_IMUX16_L_2" ], [ - "CMT_FIFO_L_CTRL1_7", - "INT_INTERFACE_CTRL1" + "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "PCIE_IMUX17_L_2" ], [ - "CMT_FIFO_L_IMUX20_7", - "INT_INTERFACE_IMUX20" + "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "PCIE_IMUX18_L_2" ], [ - "CMT_FIFO_NW2A3_7", - "INT_INTERFACE_NW2A3" + "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "PCIE_IMUX19_L_2" ], [ - "CMT_FIFO_LH5_7", - "INT_INTERFACE_LH5" + "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "PCIE_IMUX20_L_2" ], [ - "CMT_FIFO_SE4BEG2_7", - "INT_INTERFACE_SE4BEG2" + "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "PCIE_IMUX21_L_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS23_7", - "INT_INTERFACE_LOGIC_OUTS_B23" + "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "PCIE_IMUX22_L_2" ], [ - "CMT_FIFO_SE2A2_7", - "INT_INTERFACE_SE2A2" + "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "PCIE_IMUX23_L_2" ], [ - "CMT_FIFO_WW2A0_7", - "INT_INTERFACE_WW2A0" + "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "PCIE_IMUX24_L_2" ], [ - "CMT_FIFO_L_IMUX28_7", - "INT_INTERFACE_IMUX28" + "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "PCIE_IMUX25_L_2" ], [ - "CMT_FIFO_L_FAN3_7", - "INT_INTERFACE_FAN3" + "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "PCIE_IMUX26_L_2" ], [ - "CMT_FIFO_L_IMUX4_7", - "INT_INTERFACE_IMUX4" + "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "PCIE_IMUX27_L_2" ], [ - "CMT_FIFO_EL1BEG2_7", - "INT_INTERFACE_EL1BEG2" + "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "PCIE_IMUX28_L_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS17_7", - "INT_INTERFACE_LOGIC_OUTS_B17" + "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "PCIE_IMUX29_L_2" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", - "INT_INTERFACE_PHASER_TO_IO_OCLK" + "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "PCIE_IMUX30_L_2" ], [ - "CMT_FIFO_EL1BEG0_7", - "INT_INTERFACE_EL1BEG0" + "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "PCIE_IMUX31_L_2" ], [ - "CMT_FIFO_L_IMUX14_7", - "INT_INTERFACE_IMUX14" + "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "PCIE_IMUX32_L_2" ], [ - "CMT_FIFO_NE2A2_7", - "INT_INTERFACE_NE2A2" + "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "PCIE_IMUX33_L_2" ], [ - "CMT_FIFO_L_IMUX1_7", - "INT_INTERFACE_IMUX1" + "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "PCIE_IMUX34_L_2" ], [ - "CMT_FIFO_EE4A1_7", - "INT_INTERFACE_EE4A1" + "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "PCIE_IMUX35_L_2" ], [ - "CMT_FIFO_WW2END0_7", - "INT_INTERFACE_WW2END0" + "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "PCIE_IMUX36_L_2" ], [ - "CMT_FIFO_L_IMUX32_7", - "INT_INTERFACE_IMUX32" + "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "PCIE_IMUX37_L_2" ], [ - "CMT_FIFO_NW4END2_7", - "INT_INTERFACE_NW4END2" + "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "PCIE_IMUX38_L_2" ], [ - "CMT_FIFO_SE4C1_7", - "INT_INTERFACE_SE4C1" + "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "PCIE_IMUX39_L_2" ], [ - "CMT_FIFO_L_IMUX21_7", - "INT_INTERFACE_IMUX21" + "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "PCIE_IMUX40_L_2" ], [ - "CMT_FIFO_L_IMUX22_7", - "INT_INTERFACE_IMUX22" + "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "PCIE_IMUX41_L_2" ], [ - "CMT_FIFO_SW2A1_7", - "INT_INTERFACE_SW2A1" + "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "PCIE_IMUX42_L_2" ], [ - "CMT_FIFO_L_IMUX29_7", - "INT_INTERFACE_IMUX29" + "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "PCIE_IMUX43_L_2" ], [ - "CMT_FIFO_L_IMUX12_7", - "INT_INTERFACE_IMUX12" + "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "PCIE_IMUX44_L_2" ], [ - "CMT_FIFO_L_FAN1_7", - "INT_INTERFACE_FAN1" + "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "PCIE_IMUX45_L_2" ], [ - "CMT_FIFO_L_IMUX42_7", - "INT_INTERFACE_IMUX42" + "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "PCIE_IMUX46_L_2" ], [ - "CMT_FIFO_L_FAN6_7", - "INT_INTERFACE_FAN6" - ], - [ - "CMT_FIFO_SE4C3_7", - "INT_INTERFACE_SE4C3" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS20_7", - "INT_INTERFACE_LOGIC_OUTS_B20" - ], - [ - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS18_7", - "INT_INTERFACE_LOGIC_OUTS_B18" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS19_7", - "INT_INTERFACE_LOGIC_OUTS_B19" + "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "PCIE_IMUX47_L_2" ] ] }, { "grid_deltas": [ - -1, - -3 + -5, + 3 ], "tile_types": [ - "DSP_R", - "INT_INTERFACE_R" + "PCIE_INT_INTERFACE_L", + "PCIE_TOP" ], "wire_pairs": [ [ - "DSP_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" + "INT_INTERFACE_BYP0", + "PCIE_BYP0_L_3" ], [ - "DSP_FAN0_3", - "INT_INTERFACE_FAN0" + "INT_INTERFACE_BYP1", + "PCIE_BYP1_L_3" ], [ - "DSP_IMUX25_3", - "INT_INTERFACE_IMUX25" + "INT_INTERFACE_BYP2", + "PCIE_BYP2_L_3" ], [ - "DSP_SE2A3_3", - "INT_INTERFACE_SE2A3" + "INT_INTERFACE_BYP3", + "PCIE_BYP3_L_3" ], [ - "DSP_NW4END1_3", - "INT_INTERFACE_NW4END1" + "INT_INTERFACE_BYP4", + "PCIE_BYP4_L_3" ], [ - "DSP_WW2END1_3", - "INT_INTERFACE_WW2END1" + "INT_INTERFACE_BYP5", + "PCIE_BYP5_L_3" ], [ - "DSP_EE4B0_3", - "INT_INTERFACE_EE4B0" + "INT_INTERFACE_BYP6", + "PCIE_BYP6_L_3" ], [ - "DSP_IMUX24_3", - "INT_INTERFACE_IMUX24" + "INT_INTERFACE_BYP7", + "PCIE_BYP7_L_3" ], [ - "DSP_NW2A3_3", - "INT_INTERFACE_NW2A3" + "INT_INTERFACE_CLK0", + "PCIE_CLK0_L_3" ], [ - "DSP_SE4C2_3", - "INT_INTERFACE_SE4C2" + "INT_INTERFACE_CLK1", + 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"INT_INTERFACE_IMUX0" + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_3" ], [ - "DSP_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_3" ], [ - "DSP_LOGIC_OUTS_B19_3", - "INT_INTERFACE_LOGIC_OUTS_B19" + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_3" ], [ - "DSP_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_3" ], [ - "DSP_EE4B3_3", - "INT_INTERFACE_EE4B3" + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_3" ], [ - "DSP_IMUX29_3", - "INT_INTERFACE_IMUX29" + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_3" ], [ - "DSP_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_3" ], [ - "DSP_IMUX35_3", - "INT_INTERFACE_IMUX35" + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_3" ], [ - "DSP_IMUX42_3", - "INT_INTERFACE_IMUX42" + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_3" ], [ - "DSP_WW4C3_3", - "INT_INTERFACE_WW4C3" + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_3" ], [ - "DSP_IMUX8_3", - "INT_INTERFACE_IMUX8" + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_3" ], [ - "DSP_NW4A0_3", - "INT_INTERFACE_NW4A0" + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_3" ], [ - "DSP_IMUX16_3", - "INT_INTERFACE_IMUX16" + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_3" ], [ - "DSP_LOGIC_OUTS_B16_3", - "INT_INTERFACE_LOGIC_OUTS_B16" + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_3" ], [ - "DSP_IMUX30_3", - "INT_INTERFACE_IMUX30" + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_3" ], [ - "DSP_WW2END0_3", - "INT_INTERFACE_WW2END0" + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_3" ], [ - "DSP_WW2A0_3", - "INT_INTERFACE_WW2A0" + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_3" ], [ - "DSP_CTRL1_3", - "INT_INTERFACE_CTRL1" + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_3" ], [ - "DSP_NE4C1_3", - "INT_INTERFACE_NE4C1" + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_3" ], [ - "DSP_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_3" ], [ - "DSP_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_3" ], [ - "DSP_EE4BEG0_3", - "INT_INTERFACE_EE4BEG0" + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_3" ], [ - "DSP_LOGIC_OUTS_B0_3", - "INT_INTERFACE_LOGIC_OUTS_B0" + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_3" ], [ - "DSP_IMUX6_3", - "INT_INTERFACE_IMUX6" + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_3" ], [ - "DSP_WW4B2_3", - "INT_INTERFACE_WW4B2" + "INT_INTERFACE_FAN0", + "PCIE_FAN0_L_3" ], [ - "DSP_SW4END0_3", - "INT_INTERFACE_SW4END0" + "INT_INTERFACE_FAN1", + "PCIE_FAN1_L_3" ], [ - "DSP_IMUX46_3", - "INT_INTERFACE_IMUX46" + "INT_INTERFACE_FAN2", + "PCIE_FAN2_L_3" ], [ - "DSP_EE4A0_3", - "INT_INTERFACE_EE4A0" + "INT_INTERFACE_FAN3", + "PCIE_FAN3_L_3" ], [ - "DSP_WW2END2_3", - "INT_INTERFACE_WW2END2" + "INT_INTERFACE_FAN4", + "PCIE_FAN4_L_3" ], [ - "DSP_IMUX21_3", - "INT_INTERFACE_IMUX21" + "INT_INTERFACE_FAN5", + "PCIE_FAN5_L_3" ], [ - "DSP_FAN5_3", - "INT_INTERFACE_FAN5" + "INT_INTERFACE_FAN6", + "PCIE_FAN6_L_3" ], [ - "DSP_IMUX15_3", - "INT_INTERFACE_IMUX15" + "INT_INTERFACE_FAN7", + "PCIE_FAN7_L_3" ], [ - "DSP_FAN4_3", - "INT_INTERFACE_FAN4" + "INT_INTERFACE_LH1", + "PCIE_LH1_3" ], [ - "DSP_LH9_3", - "INT_INTERFACE_LH9" + "INT_INTERFACE_LH2", + "PCIE_LH2_3" ], [ - "DSP_WW2A1_3", - "INT_INTERFACE_WW2A1" + "INT_INTERFACE_LH3", + "PCIE_LH3_3" ], [ - "DSP_CLK1_3", - "INT_INTERFACE_CLK1" + "INT_INTERFACE_LH4", + "PCIE_LH4_3" ], [ - "DSP_WR1END1_3", - "INT_INTERFACE_WR1END1" + "INT_INTERFACE_LH5", + "PCIE_LH5_3" ], [ - "DSP_EE2A1_3", - "INT_INTERFACE_EE2A1" + "INT_INTERFACE_LH6", + "PCIE_LH6_3" ], [ - "DSP_NW4A1_3", - "INT_INTERFACE_NW4A1" + "INT_INTERFACE_LH7", + "PCIE_LH7_3" ], [ - "DSP_LH8_3", - "INT_INTERFACE_LH8" + "INT_INTERFACE_LH8", + "PCIE_LH8_3" ], [ - "DSP_IMUX13_3", - "INT_INTERFACE_IMUX13" + "INT_INTERFACE_LH9", + "PCIE_LH9_3" ], [ - "DSP_NW4END0_3", - "INT_INTERFACE_NW4END0" + "INT_INTERFACE_LH10", + "PCIE_LH10_3" ], [ - "DSP_SE4BEG2_3", - "INT_INTERFACE_SE4BEG2" + "INT_INTERFACE_LH11", + "PCIE_LH11_3" ], [ - "DSP_IMUX22_3", - "INT_INTERFACE_IMUX22" + "INT_INTERFACE_LH12", + "PCIE_LH12_3" ], [ - "DSP_IMUX47_3", - "INT_INTERFACE_IMUX47" + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "PCIE_LOGIC_OUTS_B0_L_3" ], [ - "DSP_IMUX5_3", - "INT_INTERFACE_IMUX5" + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "PCIE_LOGIC_OUTS_B1_L_3" ], [ - "DSP_WW4B0_3", - "INT_INTERFACE_WW4B0" + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "PCIE_LOGIC_OUTS_B2_L_3" ], [ - "DSP_SW4END1_3", - "INT_INTERFACE_SW4END1" + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "PCIE_LOGIC_OUTS_B3_L_3" ], [ - "DSP_LH11_3", - "INT_INTERFACE_LH11" + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "PCIE_LOGIC_OUTS_B4_L_3" ], [ - "DSP_SW2A3_3", - "INT_INTERFACE_SW2A3" + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "PCIE_LOGIC_OUTS_B5_L_3" ], [ - "DSP_NW4A3_3", - "INT_INTERFACE_NW4A3" + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "PCIE_LOGIC_OUTS_B6_L_3" ], [ - "DSP_WR1END2_3", - "INT_INTERFACE_WR1END2" + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "PCIE_LOGIC_OUTS_B7_L_3" ], [ - "DSP_SE2A1_3", - "INT_INTERFACE_SE2A1" + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "PCIE_LOGIC_OUTS_B8_L_3" ], [ - "DSP_EE4B1_3", - "INT_INTERFACE_EE4B1" + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "PCIE_LOGIC_OUTS_B9_L_3" ], [ - "DSP_WW2A2_3", - "INT_INTERFACE_WW2A2" + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "PCIE_LOGIC_OUTS_B10_L_3" ], [ - "DSP_NW2A1_3", - "INT_INTERFACE_NW2A1" + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "PCIE_LOGIC_OUTS_B11_L_3" ], [ - "DSP_LOGIC_OUTS_B23_3", - "INT_INTERFACE_LOGIC_OUTS_B23" + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "PCIE_LOGIC_OUTS_B12_L_3" ], [ - "DSP_IMUX40_3", - "INT_INTERFACE_IMUX40" + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "PCIE_LOGIC_OUTS_B13_L_3" ], [ - "DSP_BYP6_3", - "INT_INTERFACE_BYP6" + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "PCIE_LOGIC_OUTS_B14_L_3" ], [ - "DSP_SW2A0_3", - "INT_INTERFACE_SW2A0" + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "PCIE_LOGIC_OUTS_B15_L_3" ], [ - "DSP_NE4BEG3_3", - "INT_INTERFACE_NE4BEG3" + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "PCIE_LOGIC_OUTS_B16_L_3" ], [ - "DSP_IMUX2_3", - "INT_INTERFACE_IMUX2" + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "PCIE_LOGIC_OUTS_B17_L_3" ], [ - "DSP_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "PCIE_LOGIC_OUTS_B18_L_3" ], [ - "DSP_FAN1_3", - "INT_INTERFACE_FAN1" + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "PCIE_LOGIC_OUTS_B19_L_3" ], [ - "DSP_WW4END3_3", - "INT_INTERFACE_WW4END3" + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "PCIE_LOGIC_OUTS_B20_L_3" ], [ - "DSP_SW2A2_3", - "INT_INTERFACE_SW2A2" + "INT_INTERFACE_LOGIC_OUTS_L_B21", + "PCIE_LOGIC_OUTS_B21_L_3" ], [ - "DSP_EE2A2_3", - "INT_INTERFACE_EE2A2" + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "PCIE_LOGIC_OUTS_B22_L_3" ], [ - "DSP_IMUX28_3", - "INT_INTERFACE_IMUX28" + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "PCIE_LOGIC_OUTS_B23_L_3" ], [ - "DSP_WW4C1_3", - "INT_INTERFACE_WW4C1" + "INT_INTERFACE_MONITOR_N", + "PCIE_MONITOR_N_3" ], [ - "DSP_LH6_3", - "INT_INTERFACE_LH6" + "INT_INTERFACE_MONITOR_P", + "PCIE_MONITOR_P_3" ], [ - "DSP_LOGIC_OUTS_B10_3", - "INT_INTERFACE_LOGIC_OUTS_B10" + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_3" ], [ - "DSP_IMUX33_3", - "INT_INTERFACE_IMUX33" + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_3" ], [ - "DSP_WL1END1_3", - "INT_INTERFACE_WL1END1" + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_3" ], [ - "DSP_IMUX18_3", - "INT_INTERFACE_IMUX18" + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_3" ], [ - "DSP_IMUX9_3", - "INT_INTERFACE_IMUX9" + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_3" ], [ - "DSP_IMUX36_3", - "INT_INTERFACE_IMUX36" + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_3" ], [ - "DSP_NE2A2_3", - "INT_INTERFACE_NE2A2" + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_3" ], [ - "DSP_LOGIC_OUTS_B8_3", - "INT_INTERFACE_LOGIC_OUTS_B8" + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_3" ], [ - "DSP_LOGIC_OUTS_B22_3", - "INT_INTERFACE_LOGIC_OUTS_B22" + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_3" ], [ - "DSP_EE2A3_3", - "INT_INTERFACE_EE2A3" + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_3" ], [ - "DSP_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_3" ], [ - "DSP_LH5_3", - "INT_INTERFACE_LH5" + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_3" ], [ - "DSP_SW4A2_3", - "INT_INTERFACE_SW4A2" + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_3" ], [ - "DSP_IMUX10_3", - "INT_INTERFACE_IMUX10" + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_3" ], [ - "DSP_WW4B3_3", - "INT_INTERFACE_WW4B3" + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_3" ], [ - "DSP_LOGIC_OUTS_B1_3", - "INT_INTERFACE_LOGIC_OUTS_B1" + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_3" ], [ - "DSP_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_3" ], [ - "DSP_LOGIC_OUTS_B14_3", - "INT_INTERFACE_LOGIC_OUTS_B14" + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_3" ], [ - "DSP_LOGIC_OUTS_B5_3", - "INT_INTERFACE_LOGIC_OUTS_B5" + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_3" ], [ - "DSP_NW4END3_3", - "INT_INTERFACE_NW4END3" + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_3" ], [ - "DSP_IMUX44_3", - "INT_INTERFACE_IMUX44" + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_3" ], [ - "DSP_WW4A1_3", - "INT_INTERFACE_WW4A1" + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_3" ], [ - "DSP_EE4A1_3", - "INT_INTERFACE_EE4A1" + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_3" ], [ - "DSP_SE2A0_3", - "INT_INTERFACE_SE2A0" + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_3" ], [ - "DSP_WW4END0_3", - "INT_INTERFACE_WW4END0" + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_3" ], [ - "DSP_SW4A3_3", - "INT_INTERFACE_SW4A3" + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_3" ], [ - "DSP_WW2END3_3", - "INT_INTERFACE_WW2END3" + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_3" ], [ - "DSP_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_3" ], [ - "DSP_WW4C2_3", - "INT_INTERFACE_WW4C2" + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_3" ], [ - "DSP_IMUX17_3", - "INT_INTERFACE_IMUX17" + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_3" ], [ - "DSP_EE4C2_3", - "INT_INTERFACE_EE4C2" + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_3" ], [ - "DSP_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_3" ], [ - "DSP_WW4A0_3", - "INT_INTERFACE_WW4A0" + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_3" ], [ - "DSP_IMUX23_3", - "INT_INTERFACE_IMUX23" + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_3" ], [ - "DSP_EE2A0_3", - "INT_INTERFACE_EE2A0" + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_3" ], [ - "DSP_WW4C0_3", - "INT_INTERFACE_WW4C0" + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_3" ], [ - "DSP_IMUX26_3", - "INT_INTERFACE_IMUX26" + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_3" ], [ - "DSP_IMUX1_3", - "INT_INTERFACE_IMUX1" + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_3" ], [ - "DSP_NE4C2_3", - "INT_INTERFACE_NE4C2" + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_3" ], [ - "DSP_NE2A0_3", - "INT_INTERFACE_NE2A0" + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_3" ], [ - "DSP_IMUX4_3", - "INT_INTERFACE_IMUX4" + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_3" ], [ - "DSP_SE4C3_3", - "INT_INTERFACE_SE4C3" + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_3" ], [ - "DSP_IMUX14_3", - "INT_INTERFACE_IMUX14" + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_3" ], [ - "DSP_IMUX19_3", - "INT_INTERFACE_IMUX19" + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_3" ], [ - "DSP_FAN6_3", - "INT_INTERFACE_FAN6" + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_3" ], [ - "DSP_NW4A2_3", - "INT_INTERFACE_NW4A2" + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_3" ], [ - "DSP_WR1END0_3", - "INT_INTERFACE_WR1END0" + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_3" ], [ - "DSP_BYP4_3", - "INT_INTERFACE_BYP4" + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_3" ], [ - "DSP_LH4_3", - "INT_INTERFACE_LH4" + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_3" ], [ - "DSP_LOGIC_OUTS_B2_3", - "INT_INTERFACE_LOGIC_OUTS_B2" + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_3" ], [ - "DSP_IMUX32_3", - "INT_INTERFACE_IMUX32" + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_3" ], [ - "DSP_BYP2_3", - "INT_INTERFACE_BYP2" + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_3" ], [ - "DSP_SE4BEG1_3", - "INT_INTERFACE_SE4BEG1" + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_3" ], [ - "DSP_LOGIC_OUTS_B21_3", - "INT_INTERFACE_LOGIC_OUTS_B21" + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_3" ], [ - "DSP_WR1END3_3", - "INT_INTERFACE_WR1END3" + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_3" ], [ - "DSP_WL1END0_3", - "INT_INTERFACE_WL1END0" + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_3" ], [ - "DSP_IMUX20_3", - "INT_INTERFACE_IMUX20" + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_3" ], [ - "DSP_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_3" ], [ - "DSP_LOGIC_OUTS_B17_3", - "INT_INTERFACE_LOGIC_OUTS_B17" + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_3" ], [ - "DSP_IMUX7_3", - "INT_INTERFACE_IMUX7" + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_3" ], [ - "DSP_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_3" ], [ - "DSP_FAN7_3", - "INT_INTERFACE_FAN7" + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_3" ], [ - "DSP_WL1END2_3", - "INT_INTERFACE_WL1END2" + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_3" ], [ - "DSP_LOGIC_OUTS_B11_3", - "INT_INTERFACE_LOGIC_OUTS_B11" + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_3" ], [ - "DSP_EE4C1_3", - "INT_INTERFACE_EE4C1" + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_3" ], [ - "DSP_IMUX12_3", - "INT_INTERFACE_IMUX12" + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_3" ], [ - "DSP_LH3_3", - "INT_INTERFACE_LH3" + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_3" ], [ - "DSP_BYP3_3", - "INT_INTERFACE_BYP3" + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_3" ], [ - "DSP_LOGIC_OUTS_B7_3", - "INT_INTERFACE_LOGIC_OUTS_B7" + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_3" ], [ - "DSP_IMUX3_3", - "INT_INTERFACE_IMUX3" + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_3" ], [ - "DSP_WW4A2_3", - "INT_INTERFACE_WW4A2" + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_3" ], [ - "DSP_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_3" ], [ - "DSP_BYP1_3", - "INT_INTERFACE_BYP1" + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_3" ], [ - "DSP_CLK0_3", - "INT_INTERFACE_CLK0" + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_3" ], [ - "DSP_SE4C0_3", - "INT_INTERFACE_SE4C0" + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_3" ], [ - "DSP_NW4END2_3", - "INT_INTERFACE_NW4END2" + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_3" ], [ - "DSP_SE2A2_3", - "INT_INTERFACE_SE2A2" + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_3" ], [ - "DSP_LOGIC_OUTS_B18_3", - "INT_INTERFACE_LOGIC_OUTS_B18" + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_3" ], [ - "DSP_IMUX11_3", - "INT_INTERFACE_IMUX11" + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_3" ], [ - "DSP_IMUX31_3", - "INT_INTERFACE_IMUX31" + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_3" ], [ - "DSP_BYP7_3", - "INT_INTERFACE_BYP7" + "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "PCIE_IMUX0_L_3" ], [ - "DSP_EE4B2_3", - "INT_INTERFACE_EE4B2" + "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "PCIE_IMUX1_L_3" ], [ - "DSP_MONITOR_N_3", - "INT_INTERFACE_MONITOR_N" + "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "PCIE_IMUX2_L_3" ], [ - "DSP_IMUX37_3", - "INT_INTERFACE_IMUX37" + "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "PCIE_IMUX3_L_3" ], [ - "DSP_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" + "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "PCIE_IMUX4_L_3" ], [ - "DSP_FAN2_3", - "INT_INTERFACE_FAN2" + "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "PCIE_IMUX5_L_3" ], [ - "DSP_NE2A3_3", - "INT_INTERFACE_NE2A3" + "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "PCIE_IMUX6_L_3" ], [ - "DSP_IMUX34_3", - "INT_INTERFACE_IMUX34" + "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "PCIE_IMUX7_L_3" ], [ - "DSP_LH12_3", - "INT_INTERFACE_LH12" + "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "PCIE_IMUX8_L_3" ], [ - "DSP_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" + "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "PCIE_IMUX9_L_3" ], [ - "DSP_LOGIC_OUTS_B15_3", - "INT_INTERFACE_LOGIC_OUTS_B15" + "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "PCIE_IMUX10_L_3" ], [ - "DSP_WW4B1_3", - "INT_INTERFACE_WW4B1" + "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "PCIE_IMUX11_L_3" ], [ - "DSP_IMUX38_3", - "INT_INTERFACE_IMUX38" + "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "PCIE_IMUX12_L_3" ], [ - "DSP_WW4END2_3", - "INT_INTERFACE_WW4END2" + "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "PCIE_IMUX13_L_3" ], [ - "DSP_SW4END2_3", - "INT_INTERFACE_SW4END2" + "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "PCIE_IMUX14_L_3" ], [ - "DSP_FAN3_3", - "INT_INTERFACE_FAN3" + "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "PCIE_IMUX15_L_3" ], [ - "DSP_BYP5_3", - "INT_INTERFACE_BYP5" + "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "PCIE_IMUX16_L_3" ], [ - "DSP_IMUX43_3", - "INT_INTERFACE_IMUX43" + "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "PCIE_IMUX17_L_3" ], [ - "DSP_LH2_3", - "INT_INTERFACE_LH2" + "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "PCIE_IMUX18_L_3" ], [ - "DSP_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" + "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "PCIE_IMUX19_L_3" ], [ - "DSP_CTRL0_3", - "INT_INTERFACE_CTRL0" + "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "PCIE_IMUX20_L_3" ], [ - "DSP_WW2A3_3", - "INT_INTERFACE_WW2A3" + "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "PCIE_IMUX21_L_3" ], [ - "DSP_IMUX41_3", - "INT_INTERFACE_IMUX41" + "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "PCIE_IMUX22_L_3" ], [ - "DSP_IMUX39_3", - "INT_INTERFACE_IMUX39" + "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "PCIE_IMUX23_L_3" ], [ - "DSP_EE4A3_3", - "INT_INTERFACE_EE4A3" + "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "PCIE_IMUX24_L_3" ], [ - "DSP_SW2A1_3", - "INT_INTERFACE_SW2A1" + "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "PCIE_IMUX25_L_3" ], [ - "DSP_SW4A0_3", - "INT_INTERFACE_SW4A0" + "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "PCIE_IMUX26_L_3" ], [ - "DSP_WW4END1_3", - "INT_INTERFACE_WW4END1" + "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "PCIE_IMUX27_L_3" ], [ - "DSP_EE4A2_3", - "INT_INTERFACE_EE4A2" + "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "PCIE_IMUX28_L_3" ], [ - "DSP_NW2A2_3", - "INT_INTERFACE_NW2A2" + "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "PCIE_IMUX29_L_3" ], [ - "DSP_IMUX45_3", - "INT_INTERFACE_IMUX45" + "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "PCIE_IMUX30_L_3" ], [ - "DSP_NW2A0_3", - "INT_INTERFACE_NW2A0" + "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "PCIE_IMUX31_L_3" ], [ - "DSP_IMUX27_3", - "INT_INTERFACE_IMUX27" + "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "PCIE_IMUX32_L_3" ], [ - "DSP_LOGIC_OUTS_B20_3", - "INT_INTERFACE_LOGIC_OUTS_B20" + "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "PCIE_IMUX33_L_3" ], [ - "DSP_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" + 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"PCIE_NE4C2_1" ], [ - "CMT_FIFO_EE4A3_11", - "INT_INTERFACE_EE4A3" + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_1" ], [ - "CMT_FIFO_L_CLK0_11", - "INT_INTERFACE_CLK0" + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_1" ], [ - "CMT_FIFO_EL1BEG1_11", - "INT_INTERFACE_EL1BEG1" + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_1" ], [ - "CMT_FIFO_L_IMUX29_11", - "INT_INTERFACE_IMUX29" + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_1" ], [ - "CMT_FIFO_EL1BEG3_11", - "INT_INTERFACE_EL1BEG3" + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_1" ], [ - "CMT_FIFO_EE4BEG0_11", - "INT_INTERFACE_EE4BEG0" + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_1" ], [ - "CMT_FIFO_SW4A1_11", - "INT_INTERFACE_SW4A1" + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_1" ], [ - "CMT_FIFO_ER1BEG0_11", - "INT_INTERFACE_ER1BEG0" + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_1" ], [ - "CMT_FIFO_SW4END1_11", - "INT_INTERFACE_SW4END1" + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_1" ], [ - "CMT_FIFO_WW2END0_11", - "INT_INTERFACE_WW2END0" + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS8_11", - "INT_INTERFACE_LOGIC_OUTS_B8" + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_1" ], [ - "CMT_FIFO_WW4A3_11", - "INT_INTERFACE_WW4A3" + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_1" ], [ - "CMT_FIFO_L_IMUX1_11", - "INT_INTERFACE_IMUX1" + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_1" ], [ - "CMT_FIFO_L_IMUX35_11", - "INT_INTERFACE_IMUX35" + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_1" ], [ - "CMT_FIFO_NE4C3_11", - "INT_INTERFACE_NE4C3" + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_1" ], [ - "CMT_FIFO_SW2A2_11", - "INT_INTERFACE_SW2A2" + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_1" ], [ - "CMT_FIFO_L_FAN2_11", - "INT_INTERFACE_FAN2" + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_1" ], [ - "CMT_FIFO_SW2A1_11", - "INT_INTERFACE_SW2A1" + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_1" ], [ - "CMT_FIFO_EE4B1_11", - "INT_INTERFACE_EE4B1" + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS1_11", - "INT_INTERFACE_LOGIC_OUTS_B1" + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_1" ], [ - "CMT_FIFO_L_IMUX15_11", - "INT_INTERFACE_IMUX15" + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_1" ], [ - "CMT_FIFO_L_CLK1_11", - "INT_INTERFACE_CLK1" + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS9_11", - "INT_INTERFACE_LOGIC_OUTS_B9" + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_1" ], [ - "CMT_FIFO_WR1END0_11", - "INT_INTERFACE_WR1END0" + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_1" ], [ - "CMT_FIFO_L_IMUX37_11", - "INT_INTERFACE_IMUX37" + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_1" ], [ - "CMT_FIFO_EE2A3_11", - "INT_INTERFACE_EE2A3" + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_1" ], [ - "CMT_FIFO_WR1END3_11", - "INT_INTERFACE_WR1END3" + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_1" ], [ - "CMT_FIFO_NW2A0_11", - "INT_INTERFACE_NW2A0" + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_1" ], [ - "CMT_FIFO_L_IMUX27_11", - "INT_INTERFACE_IMUX27" + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_1" ], [ - "CMT_FIFO_WL1END3_11", - "INT_INTERFACE_WL1END3" + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_1" ], [ - "CMT_FIFO_LH6_11", - "INT_INTERFACE_LH6" + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_1" ], [ - "CMT_FIFO_EE4A0_11", - "INT_INTERFACE_EE4A0" + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_1" ], [ - "CMT_FIFO_LH4_11", - "INT_INTERFACE_LH4" + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_1" ], [ - "CMT_FIFO_L_IMUX36_11", - "INT_INTERFACE_IMUX36" + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_1" ], [ - "CMT_FIFO_LH11_11", - "INT_INTERFACE_LH11" + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_1" ], [ - "CMT_FIFO_L_IMUX26_11", - "INT_INTERFACE_IMUX26" + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_1" ], [ - "CMT_FIFO_L_IMUX2_11", - "INT_INTERFACE_IMUX2" + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_1" ], [ - "CMT_FIFO_L_IMUX25_11", - "INT_INTERFACE_IMUX25" + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_1" ], [ - "CMT_FIFO_L_IMUX5_11", - "INT_INTERFACE_IMUX5" + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_1" ], [ - "CMT_FIFO_NE4C0_11", - "INT_INTERFACE_NE4C0" + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_1" ], [ - "CMT_FIFO_L_IMUX7_11", - "INT_INTERFACE_IMUX7" + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_1" ], [ - "CMT_FIFO_SW4A0_11", - "INT_INTERFACE_SW4A0" + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_1" ], [ - "CMT_FIFO_L_IMUX40_11", - "INT_INTERFACE_IMUX40" + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_1" ], [ - "CMT_FIFO_LH7_11", - "INT_INTERFACE_LH7" + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_1" ], [ - "CMT_FIFO_NW4END3_11", - "INT_INTERFACE_NW4END3" + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_1" ], [ - "CMT_FIFO_EE2A2_11", - "INT_INTERFACE_EE2A2" + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_1" ], [ - "CMT_FIFO_SW2A0_11", - "INT_INTERFACE_SW2A0" + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_1" ], [ - "CMT_FIFO_L_IMUX41_11", - "INT_INTERFACE_IMUX41" + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_1" ], [ - "CMT_FIFO_L_IMUX10_11", - "INT_INTERFACE_IMUX10" + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_1" ], [ - "CMT_FIFO_NW2A3_11", - "INT_INTERFACE_NW2A3" + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_1" ], [ - "CMT_FIFO_L_IMUX18_11", - "INT_INTERFACE_IMUX18" + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_1" ], [ - "CMT_FIFO_SE2A0_11", - "INT_INTERFACE_SE2A0" + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_1" ], [ - "CMT_FIFO_L_FAN4_11", - "INT_INTERFACE_FAN4" + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_1" ], [ - "CMT_FIFO_NE2A1_11", - "INT_INTERFACE_NE2A1" + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_1" ], [ - "CMT_FIFO_WW4B2_11", - "INT_INTERFACE_WW4B2" + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_1" ], [ - "CMT_FIFO_L_BYP2_11", - "INT_INTERFACE_BYP2" + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS22_11", - "INT_INTERFACE_LOGIC_OUTS_B22" + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_1" ], [ - "CMT_FIFO_NW4END2_11", - "INT_INTERFACE_NW4END2" + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_1" ], [ - "CMT_FIFO_NE4BEG2_11", - "INT_INTERFACE_NE4BEG2" + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_1" ], [ - "CMT_FIFO_WW4A2_11", - "INT_INTERFACE_WW4A2" + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_1" ], [ - "CMT_FIFO_L_IMUX24_11", - "INT_INTERFACE_IMUX24" + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_1" ], [ - "CMT_FIFO_EE4A1_11", - "INT_INTERFACE_EE4A1" + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_1" ], [ - "CMT_FIFO_L_IMUX33_11", - "INT_INTERFACE_IMUX33" + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_1" ], [ - "CMT_FIFO_L_BYP0_11", - "INT_INTERFACE_BYP0" + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_1" ], [ - "CMT_FIFO_NE4C2_11", - "INT_INTERFACE_NE4C2" + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS4_11", - "INT_INTERFACE_LOGIC_OUTS_B4" + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS13_11", - "INT_INTERFACE_LOGIC_OUTS_B13" + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_1" ], [ - "CMT_FIFO_SW4END3_11", - "INT_INTERFACE_SW4END3" + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_1" ], [ - "CMT_FIFO_L_IMUX9_11", - "INT_INTERFACE_IMUX9" + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_1" ], [ - "CMT_FIFO_WW4END3_11", - "INT_INTERFACE_WW4END3" + "PCIE_INT_INTERFACE_IMUX_OUT0", + "PCIE_IMUX0_R_1" ], [ - "CMT_FIFO_L_IMUX21_11", - "INT_INTERFACE_IMUX21" + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_IMUX1_R_1" ], [ - "CMT_FIFO_NW4A2_11", - "INT_INTERFACE_NW4A2" + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_IMUX2_R_1" ], [ - "CMT_FIFO_WW4END2_11", - "INT_INTERFACE_WW4END2" + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_IMUX3_R_1" ], [ - "CMT_FIFO_L_IMUX45_11", - "INT_INTERFACE_IMUX45" + "PCIE_INT_INTERFACE_IMUX_OUT4", + "PCIE_IMUX4_R_1" ], [ - "CMT_FIFO_L_IMUX23_11", - "INT_INTERFACE_IMUX23" + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_IMUX5_R_1" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_IMUX6_R_1" ], [ - "CMT_FIFO_L_IMUX32_11", - "INT_INTERFACE_IMUX32" + "PCIE_INT_INTERFACE_IMUX_OUT7", + "PCIE_IMUX7_R_1" ], [ - "CMT_FIFO_SE2A3_11", - "INT_INTERFACE_SE2A3" + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_IMUX8_R_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS17_11", - "INT_INTERFACE_LOGIC_OUTS_B17" + "PCIE_INT_INTERFACE_IMUX_OUT9", + "PCIE_IMUX9_R_1" ], [ - "CMT_FIFO_LH10_11", - "INT_INTERFACE_LH10" + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_IMUX10_R_1" ], [ - "CMT_FIFO_WW4B0_11", - "INT_INTERFACE_WW4B0" + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_IMUX11_R_1" ], [ - "CMT_FIFO_ER1BEG3_11", - "INT_INTERFACE_ER1BEG3" + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_IMUX12_R_1" ], [ - "CMT_FIFO_SW4A2_11", - "INT_INTERFACE_SW4A2" + "PCIE_INT_INTERFACE_IMUX_OUT13", + "PCIE_IMUX13_R_1" ], [ - "CMT_FIFO_L_IMUX13_11", - "INT_INTERFACE_IMUX13" + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_IMUX14_R_1" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", - "INT_INTERFACE_PHASER_TO_IO_OCLK" + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_IMUX15_R_1" ], [ - "CMT_FIFO_L_IMUX31_11", - "INT_INTERFACE_IMUX31" + "PCIE_INT_INTERFACE_IMUX_OUT16", + "PCIE_IMUX16_R_1" ], [ - "CMT_FIFO_L_BYP1_11", - "INT_INTERFACE_BYP1" + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_IMUX17_R_1" ], [ - "CMT_FIFO_NW4A0_11", - "INT_INTERFACE_NW4A0" + "PCIE_INT_INTERFACE_IMUX_OUT18", + "PCIE_IMUX18_R_1" ], [ - "CMT_FIFO_EE4C0_11", - "INT_INTERFACE_EE4C0" + "PCIE_INT_INTERFACE_IMUX_OUT19", + "PCIE_IMUX19_R_1" ], [ - "CMT_FIFO_SE4C3_11", - "INT_INTERFACE_SE4C3" + "PCIE_INT_INTERFACE_IMUX_OUT20", + "PCIE_IMUX20_R_1" ], [ - "CMT_FIFO_NW4END0_11", - "INT_INTERFACE_NW4END0" + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_IMUX21_R_1" ], [ - "CMT_FIFO_L_FAN1_11", - "INT_INTERFACE_FAN1" + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_IMUX22_R_1" ], [ - "CMT_FIFO_L_IMUX6_11", - "INT_INTERFACE_IMUX6" + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_IMUX23_R_1" ], [ - "CMT_FIFO_WW2END3_11", - "INT_INTERFACE_WW2END3" + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_IMUX24_R_1" ], [ - "CMT_FIFO_WW2END1_11", - "INT_INTERFACE_WW2END1" + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_IMUX25_R_1" ], [ - "CMT_FIFO_EL1BEG2_11", - "INT_INTERFACE_EL1BEG2" + "PCIE_INT_INTERFACE_IMUX_OUT26", + "PCIE_IMUX26_R_1" ], [ - "CMT_FIFO_SE4C1_11", - "INT_INTERFACE_SE4C1" + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_IMUX27_R_1" ], [ - "CMT_FIFO_NW4END1_11", - "INT_INTERFACE_NW4END1" + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_IMUX28_R_1" ], [ - "CMT_FIFO_L_IMUX16_11", - "INT_INTERFACE_IMUX16" + "PCIE_INT_INTERFACE_IMUX_OUT29", + "PCIE_IMUX29_R_1" ], [ - "CMT_FIFO_LH2_11", - "INT_INTERFACE_LH2" + "PCIE_INT_INTERFACE_IMUX_OUT30", + "PCIE_IMUX30_R_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS20_11", - "INT_INTERFACE_LOGIC_OUTS_B20" + "PCIE_INT_INTERFACE_IMUX_OUT31", + "PCIE_IMUX31_R_1" ], [ - "CMT_FIFO_WL1END1_11", - "INT_INTERFACE_WL1END1" + "PCIE_INT_INTERFACE_IMUX_OUT32", + "PCIE_IMUX32_R_1" ], [ - "CMT_FIFO_WW4END1_11", - "INT_INTERFACE_WW4END1" + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_IMUX33_R_1" ], [ - "CMT_FIFO_WW2END2_11", - "INT_INTERFACE_WW2END2" + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_IMUX34_R_1" ], [ - "CMT_FIFO_LH1_11", - "INT_INTERFACE_LH1" + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_IMUX35_R_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS12_11", - "INT_INTERFACE_LOGIC_OUTS_B12" + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_IMUX36_R_1" ], [ - "CMT_FIFO_L_IMUX39_11", - "INT_INTERFACE_IMUX39" + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_IMUX37_R_1" ], [ - "CMT_FIFO_NE4BEG3_11", - "INT_INTERFACE_NE4BEG3" + "PCIE_INT_INTERFACE_IMUX_OUT38", + "PCIE_IMUX38_R_1" ], [ - "CMT_FIFO_NE4BEG0_11", - "INT_INTERFACE_NE4BEG0" + "PCIE_INT_INTERFACE_IMUX_OUT39", + "PCIE_IMUX39_R_1" ], [ - "CMT_FIFO_WR1END1_11", - "INT_INTERFACE_WR1END1" + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_IMUX40_R_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS6_11", - "INT_INTERFACE_LOGIC_OUTS_B6" + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_IMUX41_R_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS0_11", - "INT_INTERFACE_LOGIC_OUTS_B0" + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_IMUX42_R_1" ], [ - "CMT_FIFO_L_LOGIC_OUTS19_11", - "INT_INTERFACE_LOGIC_OUTS_B19" + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_IMUX43_R_1" ], [ - "CMT_FIFO_NW4A3_11", - "INT_INTERFACE_NW4A3" + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_IMUX44_R_1" ], [ - "CMT_FIFO_SE4C2_11", - "INT_INTERFACE_SE4C2" + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_IMUX45_R_1" ], [ - "CMT_FIFO_L_IMUX8_11", - "INT_INTERFACE_IMUX8" + "PCIE_INT_INTERFACE_IMUX_OUT46", + "PCIE_IMUX46_R_1" ], [ - "CMT_FIFO_SE4BEG0_11", - "INT_INTERFACE_SE4BEG0" + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_IMUX47_R_1" ] ] }, @@ -90373,7921 +470497,1757 @@ 2 ], "tile_types": [ - "CMT_FIFO_R", - "CMT_TOP_R_LOWER_T" + "PCIE_INT_INTERFACE_R", + "PCIE_TOP" ], "wire_pairs": [ [ - "CMT_FIFO_L_IMUX31_6", - "CMT_TOP_IMUX31_3" + "INT_INTERFACE_BYP0", + "PCIE_BYP0_R_2" ], [ - "CMT_FIFO_NW4A0_7", - "CMT_TOP_NW4A0_4" + "INT_INTERFACE_BYP1", + "PCIE_BYP1_R_2" ], [ - "CMT_FIFO_WW4A0_10", - "CMT_TOP_WW4A0_7" + "INT_INTERFACE_BYP2", + "PCIE_BYP2_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_2" + "INT_INTERFACE_BYP3", + "PCIE_BYP3_R_2" ], [ - "CMT_FIFO_EE2BEG1_6", - "CMT_TOP_EE2BEG1_3" + "INT_INTERFACE_BYP4", + "PCIE_BYP4_R_2" ], [ - "CMT_FIFO_EL1BEG1_11", - "CMT_TOP_EL1BEG1_8" + "INT_INTERFACE_BYP5", + "PCIE_BYP5_R_2" ], [ - "CMT_FIFO_L_IMUX18_6", - "CMT_TOP_IMUX18_3" + "INT_INTERFACE_BYP6", + "PCIE_BYP6_R_2" ], [ - "CMT_FIFO_L_IMUX37_4", - "CMT_TOP_IMUX37_1" + "INT_INTERFACE_BYP7", + "PCIE_BYP7_R_2" ], [ - "CMT_FIFO_L_IMUX46_8", - "CMT_TOP_IMUX46_5" + "INT_INTERFACE_CLK0", + "PCIE_CLK0_R_2" ], [ - "CMT_FIFO_WW2END0_8", - "CMT_TOP_WW2END0_5" + "INT_INTERFACE_CLK1", + "PCIE_CLK1_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS5_9", - "CMT_TOP_LOGIC_OUTS_L_B5_6" + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_R_2" ], [ - "CMT_FIFO_SE4C2_8", - "CMT_TOP_SE4C2_5" + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_R_2" ], [ - "CMT_FIFO_SW2A0_11", - "CMT_TOP_SW2A0_8" + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_2" ], [ - "CMT_FIFO_EE4A0_8", - "CMT_TOP_EE4A0_5" + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_2" ], [ - "CMT_FIFO_LH1_10", - "CMT_TOP_LH1_7" + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_2" ], [ - "CMT_FIFO_L_IMUX16_3", - "CMT_TOP_IMUX16_0" + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_2" ], [ - "CMT_FIFO_EE2A2_4", - "CMT_TOP_EE2A2_1" + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_2" ], [ - "CMT_FIFO_SW4END2_9", - "CMT_TOP_SW4END2_6" + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_2" ], [ - "CMT_FIFO_L_BYP2_5", - "CMT_TOP_BYP2_2" + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_2" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", - "CMT_TOP_OCLKDIV_3" + "INT_INTERFACE_EE2BEG3", + "PCIE_EE2BEG3_2" ], [ - "CMT_FIFO_WW4END1_3", - "CMT_TOP_WW4END1_0" + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_2" ], [ - "CMT_FIFO_L_BYP0_8", - "CMT_TOP_BYP0_5" + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_2" ], [ - "CMT_FIFO_L_CTRL0_10", - "CMT_TOP_CTRL0_7" + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_2" ], [ - "CMT_FIFO_LH9_8", - "CMT_TOP_LH9_5" + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_2" ], [ - "CMT_FIFO_L_FAN6_6", - "CMT_TOP_FAN6_3" + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_2" ], [ - "CMT_FIFO_NW4END3_3", - "CMT_TOP_NW4END3_0" + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_2" ], [ - "CMT_FIFO_L_CTRL0_8", - "CMT_TOP_CTRL0_5" + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_2" ], [ - "CMT_FIFO_L_CLK0_7", - "CMT_TOP_CLK0_4" + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_2" ], [ - "CMT_FIFO_L_FAN5_10", - "CMT_TOP_FAN5_7" + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_2" ], [ - "CMT_FIFO_L_IMUX6_11", - "CMT_TOP_IMUX6_8" + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_4" + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_2" ], [ - "CMT_FIFO_L_IMUX4_10", - "CMT_TOP_IMUX4_7" + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_2" ], [ - "CMT_FIFO_WL1END0_4", - "CMT_TOP_WL1END0_1" + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_2" ], [ - "CMT_FIFO_L_IMUX15_4", - "CMT_TOP_IMUX15_1" + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_2" ], [ - "CMT_FIFO_WW4C3_3", - "CMT_TOP_WW4C3_0" + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_2" ], [ - "CMT_FIFO_L_IMUX24_3", - "CMT_TOP_IMUX24_0" + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_2" ], [ - "CMT_FIFO_L_IMUX13_6", - "CMT_TOP_IMUX13_3" + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_2" ], [ - "CMT_FIFO_LH11_8", - "CMT_TOP_LH11_5" + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_2" ], [ - "CMT_FIFO_L_IMUX15_5", - "CMT_TOP_IMUX15_2" + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_2" ], [ - "CMT_FIFO_EE2BEG1_3", - "CMT_TOP_EE2BEG1_0" + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_2" ], [ - "CMT_FIFO_WW4B2_11", - "CMT_TOP_WW4B2_8" + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_2" ], [ - "CMT_FIFO_WW4A3_3", - "CMT_TOP_WW4A3_0" + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_2" ], [ - "CMT_FIFO_WL1END2_7", - "CMT_TOP_WL1END2_4" + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_2" ], [ - "CMT_FIFO_SE4C1_8", - "CMT_TOP_SE4C1_5" + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_2" ], [ - "CMT_FIFO_L_IMUX3_7", - "CMT_TOP_IMUX3_4" + "INT_INTERFACE_FAN0", + "PCIE_FAN0_R_2" ], [ - "CMT_FIFO_L_IMUX46_4", - "CMT_TOP_IMUX46_1" + "INT_INTERFACE_FAN1", + "PCIE_FAN1_R_2" ], [ - "CMT_FIFO_L_IMUX47_4", - "CMT_TOP_IMUX47_1" + "INT_INTERFACE_FAN2", + "PCIE_FAN2_R_2" ], [ - "CMT_FIFO_L_IMUX24_8", - "CMT_TOP_IMUX24_5" + "INT_INTERFACE_FAN3", + "PCIE_FAN3_R_2" ], [ - "CMT_FIFO_SE2A0_9", - "CMT_TOP_SE2A0_6" + "INT_INTERFACE_FAN4", + "PCIE_FAN4_R_2" ], [ - "CMT_FIFO_WW2A3_5", - "CMT_TOP_WW2A3_2" + "INT_INTERFACE_FAN5", + "PCIE_FAN5_R_2" ], [ - "CMT_FIFO_L_IMUX36_4", - "CMT_TOP_IMUX36_1" + "INT_INTERFACE_FAN6", + "PCIE_FAN6_R_2" ], [ - "CMT_FIFO_SW2A2_5", - "CMT_TOP_SW2A2_2" + "INT_INTERFACE_FAN7", + "PCIE_FAN7_R_2" ], [ - "CMT_FIFO_SE4BEG3_3", - "CMT_TOP_SE4BEG3_0" + "INT_INTERFACE_LH1", + "PCIE_LH1_2" ], [ - "CMT_FIFO_L_IMUX29_8", - "CMT_TOP_IMUX29_5" + "INT_INTERFACE_LH2", + "PCIE_LH2_2" ], [ - "CMT_FIFO_WW4C1_8", - "CMT_TOP_WW4C1_5" + "INT_INTERFACE_LH3", + "PCIE_LH3_2" ], [ - "CMT_FIFO_L_IMUX41_7", - "CMT_TOP_IMUX41_4" + "INT_INTERFACE_LH4", + "PCIE_LH4_2" ], [ - "CMT_FIFO_NW2A3_8", - "CMT_TOP_NW2A3_5" + "INT_INTERFACE_LH5", + "PCIE_LH5_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_3" + "INT_INTERFACE_LH6", + "PCIE_LH6_2" ], [ - "CMT_FIFO_EE2BEG0_7", - "CMT_TOP_EE2BEG0_4" + "INT_INTERFACE_LH7", + "PCIE_LH7_2" ], [ - "CMT_FIFO_L_IMUX15_3", - "CMT_TOP_IMUX15_0" + "INT_INTERFACE_LH8", + "PCIE_LH8_2" ], [ - "CMT_FIFO_L_IMUX5_7", - "CMT_TOP_IMUX5_4" + "INT_INTERFACE_LH9", + "PCIE_LH9_2" ], [ - "CMT_FIFO_L_IMUX39_7", - "CMT_TOP_IMUX39_4" + "INT_INTERFACE_LH10", + "PCIE_LH10_2" ], [ - "CMT_FIFO_NE2A2_6", - "CMT_TOP_NE2A2_3" + "INT_INTERFACE_LH11", + "PCIE_LH11_2" ], [ - "CMT_FIFO_L_IMUX42_10", - "CMT_TOP_IMUX42_7" + "INT_INTERFACE_LH12", + "PCIE_LH12_2" ], [ - "CMT_FIFO_NE4C2_4", - "CMT_TOP_NE4C2_1" + "INT_INTERFACE_LOGIC_OUTS_B0", + "PCIE_LOGIC_OUTS_B0_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_4" + "INT_INTERFACE_LOGIC_OUTS_B1", + "PCIE_LOGIC_OUTS_B1_R_2" ], [ - "CMT_FIFO_WW4END1_10", - "CMT_TOP_WW4END1_7" + "INT_INTERFACE_LOGIC_OUTS_B2", + "PCIE_LOGIC_OUTS_B2_R_2" ], [ - "CMT_FIFO_L_IMUX10_8", - "CMT_TOP_IMUX10_5" + "INT_INTERFACE_LOGIC_OUTS_B3", + "PCIE_LOGIC_OUTS_B3_R_2" ], [ - "CMT_FIFO_WW2END0_7", - "CMT_TOP_WW2END0_4" + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_LOGIC_OUTS_B4_R_2" ], [ - "CMT_FIFO_SW2A0_5", - "CMT_TOP_SW2A0_2" + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_LOGIC_OUTS_B5_R_2" ], [ - "CMT_FIFO_L_BYP0_6", - "CMT_TOP_BYP0_3" + "INT_INTERFACE_LOGIC_OUTS_B6", + "PCIE_LOGIC_OUTS_B6_R_2" ], [ - "CMT_FIFO_LH6_4", - "CMT_TOP_LH6_1" + "INT_INTERFACE_LOGIC_OUTS_B7", + "PCIE_LOGIC_OUTS_B7_R_2" ], [ - "CMT_FIFO_L_FAN1_3", - "CMT_TOP_FAN1_0" + "INT_INTERFACE_LOGIC_OUTS_B8", + "PCIE_LOGIC_OUTS_B8_R_2" ], [ - "CMT_FIFO_L_IMUX10_7", - "CMT_TOP_IMUX10_4" + "INT_INTERFACE_LOGIC_OUTS_B9", + "PCIE_LOGIC_OUTS_B9_R_2" ], [ - "CMT_FIFO_NW2A1_7", - "CMT_TOP_NW2A1_4" + "INT_INTERFACE_LOGIC_OUTS_B10", + "PCIE_LOGIC_OUTS_B10_R_2" ], [ - "CMT_FIFO_ER1BEG2_5", - "CMT_TOP_ER1BEG2_2" + "INT_INTERFACE_LOGIC_OUTS_B11", + "PCIE_LOGIC_OUTS_B11_R_2" ], [ - "CMT_FIFO_WR1END0_8", - "CMT_TOP_WR1END0_5" + "INT_INTERFACE_LOGIC_OUTS_B12", + "PCIE_LOGIC_OUTS_B12_R_2" ], [ - "CMT_FIFO_SE4C3_6", - "CMT_TOP_SE4C3_3" + "INT_INTERFACE_LOGIC_OUTS_B13", + "PCIE_LOGIC_OUTS_B13_R_2" ], [ - "CMT_FIFO_L_IMUX9_6", - "CMT_TOP_IMUX9_3" + "INT_INTERFACE_LOGIC_OUTS_B14", + "PCIE_LOGIC_OUTS_B14_R_2" ], [ - "CMT_FIFO_NW2A0_9", - "CMT_TOP_NW2A0_6" + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_LOGIC_OUTS_B15_R_2" ], [ - "CMT_FIFO_L_IMUX16_6", - "CMT_TOP_IMUX16_3" + "INT_INTERFACE_LOGIC_OUTS_B16", + "PCIE_LOGIC_OUTS_B16_R_2" ], [ - "CMT_FIFO_LH8_5", - "CMT_TOP_LH8_2" + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_LOGIC_OUTS_B17_R_2" ], [ - "CMT_FIFO_LH4_5", - "CMT_TOP_LH4_2" + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_LOGIC_OUTS_B18_R_2" ], [ - "CMT_FIFO_L_IMUX44_6", - "CMT_TOP_IMUX44_3" + "INT_INTERFACE_LOGIC_OUTS_B19", + "PCIE_LOGIC_OUTS_B19_R_2" ], [ - "CMT_FIFO_L_IMUX17_3", - "CMT_TOP_IMUX17_0" + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_LOGIC_OUTS_B20_R_2" ], [ - "CMT_FIFO_EL1BEG2_6", - "CMT_TOP_EL1BEG2_3" + "INT_INTERFACE_LOGIC_OUTS_B21", + "PCIE_LOGIC_OUTS_B21_R_2" ], [ - "CMT_FIFO_L_BYP1_10", - "CMT_TOP_BYP1_7" + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_LOGIC_OUTS_B22_R_2" ], [ - "CMT_FIFO_WW2END1_3", - "CMT_TOP_WW2END1_0" + "INT_INTERFACE_LOGIC_OUTS_B23", + "PCIE_LOGIC_OUTS_B23_R_2" ], [ - "CMT_FIFO_NW4END1_9", - "CMT_TOP_NW4END1_6" + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_2" ], [ - "CMT_FIFO_WW4C3_11", - "CMT_TOP_WW4C3_8" + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_2" ], [ - "CMT_FIFO_L_IMUX21_7", - "CMT_TOP_IMUX21_4" + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_2" ], [ - "CMT_FIFO_NE4BEG1_3", - "CMT_TOP_NE4BEG1_0" + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_2" ], [ - "CMT_FIFO_WW4A2_8", - "CMT_TOP_WW4A2_5" + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_2" ], [ - "CMT_FIFO_EE2A1_6", - "CMT_TOP_EE2A1_3" + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_4" + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_2" ], [ - "CMT_FIFO_EE2A2_6", - "CMT_TOP_EE2A2_3" + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS15_9", - "CMT_TOP_LOGIC_OUTS_L_B15_6" + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_2" ], [ - "CMT_FIFO_L_IMUX12_4", - "CMT_TOP_IMUX12_1" + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_2" ], [ - "CMT_FIFO_WW2END3_4", - "CMT_TOP_WW2END3_1" + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_2" ], [ - "CMT_FIFO_WW4END0_8", - "CMT_TOP_WW4END0_5" + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_2" + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_2" ], [ - "CMT_FIFO_WW2END0_3", - "CMT_TOP_WW2END0_0" + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_2" ], [ - "CMT_FIFO_L_PHASER_RDENABLE", - "CMT_PHASER_OUT_B_RDEN_TOFIFO" + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_2" + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_8" + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_2" ], [ - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", - "CMT_TOP_ICLKDIV_2" + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_2" ], [ - "CMT_FIFO_L_IMUX47_5", - "CMT_TOP_IMUX47_2" + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_2" ], [ - "CMT_FIFO_L_IMUX17_11", - "CMT_TOP_IMUX17_8" + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_2" ], [ - "CMT_FIFO_L_BYP4_8", - "CMT_TOP_BYP4_5" + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_5" + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_4" + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_2" ], [ - "CMT_FIFO_EE2BEG2_6", - "CMT_TOP_EE2BEG2_3" + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_2" ], [ - "CMT_FIFO_EE4B2_10", - "CMT_TOP_EE4B2_7" + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_8" + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_2" ], [ - "CMT_FIFO_SW2A1_8", - "CMT_TOP_SW2A1_5" + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_2" ], [ - "CMT_FIFO_L_FAN1_9", - "CMT_TOP_FAN1_6" + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_2" ], [ - "CMT_FIFO_SW4A0_11", - "CMT_TOP_SW4A0_8" + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_2" ], [ - "CMT_FIFO_LH5_6", - "CMT_TOP_LH5_3" + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_2" ], [ - "CMT_FIFO_SW2A1_6", - "CMT_TOP_SW2A1_3" + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_2" ], [ - "CMT_FIFO_WR1END0_4", - "CMT_TOP_WR1END0_1" + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_2" ], [ - "CMT_FIFO_L_FAN7_6", - "CMT_TOP_FAN7_3" + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_2" ], [ - "CMT_FIFO_EE4B3_5", - "CMT_TOP_EE4B3_2" + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_2" ], [ - "CMT_FIFO_WR1END3_7", - "CMT_TOP_WR1END3_4" + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_2" ], [ - "CMT_FIFO_LH3_8", - "CMT_TOP_LH3_5" + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_2" ], [ - "CMT_FIFO_LH4_8", - "CMT_TOP_LH4_5" + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_2" ], [ - "CMT_FIFO_NE4BEG2_4", - "CMT_TOP_NE4BEG2_1" + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_2" ], [ - "CMT_FIFO_SE2A0_8", - "CMT_TOP_SE2A0_5" + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_2" ], [ - "CMT_FIFO_LH11_11", - "CMT_TOP_LH11_8" + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_2" ], [ - "CMT_FIFO_SW4A3_8", - "CMT_TOP_SW4A3_5" + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_2" ], [ - "CMT_FIFO_L_IMUX28_5", - "CMT_TOP_IMUX28_2" + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_2" ], [ - "CMT_FIFO_WW4B3_10", - "CMT_TOP_WW4B3_7" + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_2" ], [ - "CMT_FIFO_WW2A3_9", - "CMT_TOP_WW2A3_6" + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_2" ], [ - "CMT_FIFO_NE4C3_3", - "CMT_TOP_NE4C3_0" + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_2" ], [ - "CMT_FIFO_SE4C3_9", - "CMT_TOP_SE4C3_6" + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_2" ], [ - "CMT_FIFO_L_IMUX5_3", - "CMT_TOP_IMUX5_0" + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_2" ], [ - "CMT_FIFO_L_BYP2_11", - "CMT_TOP_BYP2_8" + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_2" ], [ - "CMT_FIFO_WR1END3_9", - "CMT_TOP_WR1END3_6" + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_2" ], [ - "CMT_FIFO_LH7_5", - "CMT_TOP_LH7_2" + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_2" ], [ - "CMT_FIFO_SW2A2_8", - "CMT_TOP_SW2A2_5" + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_2" ], [ - "CMT_FIFO_EE4B2_8", - "CMT_TOP_EE4B2_5" + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_2" ], [ - "CMT_FIFO_SE4C0_8", - "CMT_TOP_SE4C0_5" + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_2" ], [ - "CMT_FIFO_SE2A0_10", - "CMT_TOP_SE2A0_7" + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_2" ], [ - "CMT_FIFO_EE4C1_5", - "CMT_TOP_EE4C1_2" + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_3" + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_2" ], [ - "CMT_FIFO_L_IMUX41_9", - "CMT_TOP_IMUX41_6" + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_2" ], [ - "CMT_FIFO_NW4END3_5", - "CMT_TOP_NW4END3_2" + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_7" + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_2" ], [ - "CMT_FIFO_NE2A2_11", - "CMT_TOP_NE2A2_8" + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_2" ], [ - "CMT_FIFO_EE2A0_11", - "CMT_TOP_EE2A0_8" + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_2" ], [ - "CMT_FIFO_L_IMUX37_11", - "CMT_TOP_IMUX37_8" + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_2" ], [ - "CMT_FIFO_MONITOR_P_6", - "CMT_TOP_MONITOR_P_3" + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_2" ], [ - "CMT_FIFO_L_IMUX38_4", - "CMT_TOP_IMUX38_1" + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_2" ], [ - "CMT_FIFO_WW4A1_9", - "CMT_TOP_WW4A1_6" + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_2" + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_2" ], [ - "CMT_FIFO_EE4A0_5", - "CMT_TOP_EE4A0_2" + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_2" ], [ - "CMT_FIFO_EL1BEG0_11", - "CMT_TOP_EL1BEG0_8" + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_2" ], [ - "CMT_FIFO_SW2A3_7", - "CMT_TOP_SW2A3_4" + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_2" ], [ - "CMT_FIFO_L_BYP1_7", - "CMT_TOP_BYP1_4" + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_2" ], [ - "CMT_FIFO_L_FAN4_8", - "CMT_TOP_FAN4_5" + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_2" ], [ - "CMT_FIFO_EE4C1_7", - "CMT_TOP_EE4C1_4" + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_2" ], [ - "CMT_FIFO_L_IMUX40_6", - "CMT_TOP_IMUX40_3" + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_2" ], [ - "CMT_FIFO_ER1BEG0_7", - "CMT_TOP_ER1BEG0_4" + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_2" + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_2" + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_2" ], [ - "CMT_FIFO_ER1BEG1_9", - "CMT_TOP_ER1BEG1_6" + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_2" ], [ - "CMT_FIFO_WW4C0_11", - "CMT_TOP_WW4C0_8" + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_2" ], [ - "CMT_FIFO_EE2BEG1_7", - "CMT_TOP_EE2BEG1_4" + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_2" ], [ - "CMT_FIFO_L_BYP4_5", - "CMT_TOP_BYP4_2" + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_2" ], [ - "CMT_FIFO_L_IMUX10_11", - "CMT_TOP_IMUX10_8" + "PCIE_INT_INTERFACE_IMUX_OUT0", + "PCIE_IMUX0_R_2" ], [ - "CMT_FIFO_L_IMUX25_6", - "CMT_TOP_IMUX25_3" + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_IMUX1_R_2" ], [ - "CMT_FIFO_L_IMUX33_9", - "CMT_TOP_IMUX33_6" + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_IMUX2_R_2" ], [ - "CMT_FIFO_L_IMUX26_4", - "CMT_TOP_IMUX26_1" + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_IMUX3_R_2" ], [ - "CMT_FIFO_SW4END1_9", - "CMT_TOP_SW4END1_6" + "PCIE_INT_INTERFACE_IMUX_OUT4", + "PCIE_IMUX4_R_2" ], [ - "CMT_FIFO_EE4B0_10", - "CMT_TOP_EE4B0_7" + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_IMUX5_R_2" ], [ - "CMT_FIFO_WW2END1_8", - "CMT_TOP_WW2END1_5" + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_IMUX6_R_2" ], [ - "CMT_FIFO_SE4C3_5", - "CMT_TOP_SE4C3_2" + "PCIE_INT_INTERFACE_IMUX_OUT7", + "PCIE_IMUX7_R_2" ], [ - "CMT_FIFO_L_IMUX47_3", - "CMT_TOP_IMUX47_0" + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_IMUX8_R_2" ], [ - "CMT_FIFO_WL1END0_3", - "CMT_TOP_WL1END0_0" + "PCIE_INT_INTERFACE_IMUX_OUT9", + "PCIE_IMUX9_R_2" ], [ - "CMT_FIFO_L_IMUX37_3", - "CMT_TOP_IMUX37_0" + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_IMUX10_R_2" ], [ - "CMT_FIFO_SW4A1_8", - "CMT_TOP_SW4A1_5" + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_IMUX11_R_2" ], [ - "CMT_FIFO_L_IMUX38_9", - "CMT_TOP_IMUX38_6" + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_IMUX12_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_7" + "PCIE_INT_INTERFACE_IMUX_OUT13", + "PCIE_IMUX13_R_2" ], [ - "CMT_FIFO_NE4C2_10", - "CMT_TOP_NE4C2_7" + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_IMUX14_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_1" + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_IMUX15_R_2" ], [ - "CMT_FIFO_L_IMUX37_6", - "CMT_TOP_IMUX37_3" + "PCIE_INT_INTERFACE_IMUX_OUT16", + "PCIE_IMUX16_R_2" ], [ - "CMT_FIFO_L_IMUX35_4", - "CMT_TOP_IMUX35_1" + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_IMUX17_R_2" ], [ - "CMT_FIFO_NE4C3_6", - "CMT_TOP_NE4C3_3" + "PCIE_INT_INTERFACE_IMUX_OUT18", + "PCIE_IMUX18_R_2" ], [ - "CMT_FIFO_L_IMUX43_10", - "CMT_TOP_IMUX43_7" + "PCIE_INT_INTERFACE_IMUX_OUT19", + "PCIE_IMUX19_R_2" ], [ - "CMT_FIFO_EE4B2_9", - "CMT_TOP_EE4B2_6" + "PCIE_INT_INTERFACE_IMUX_OUT20", + "PCIE_IMUX20_R_2" ], [ - "CMT_FIFO_NW4END2_10", - "CMT_TOP_NW4END2_7" + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_IMUX21_R_2" ], [ - "CMT_FIFO_SW4A3_4", - "CMT_TOP_SW4A3_1" + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_IMUX22_R_2" ], [ - "CMT_FIFO_L_BYP4_3", - "CMT_TOP_BYP4_0" + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_IMUX23_R_2" ], [ - "CMT_FIFO_SE2A3_9", - "CMT_TOP_SE2A3_6" + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_IMUX24_R_2" ], [ - "CMT_FIFO_EL1BEG0_6", - "CMT_TOP_EL1BEG0_3" + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_IMUX25_R_2" ], [ - "CMT_FIFO_L_IMUX30_8", - "CMT_TOP_IMUX30_5" + "PCIE_INT_INTERFACE_IMUX_OUT26", + "PCIE_IMUX26_R_2" ], [ - "CMT_FIFO_L_IMUX16_7", - "CMT_TOP_IMUX16_4" + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_IMUX27_R_2" ], [ - "CMT_FIFO_SE2A1_3", - "CMT_TOP_SE2A1_0" + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_IMUX28_R_2" ], [ - "CMT_FIFO_WR1END3_8", - "CMT_TOP_WR1END3_5" + "PCIE_INT_INTERFACE_IMUX_OUT29", + "PCIE_IMUX29_R_2" ], [ - "CMT_FIFO_WW2A2_6", - "CMT_TOP_WW2A2_3" + "PCIE_INT_INTERFACE_IMUX_OUT30", + "PCIE_IMUX30_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_3" + "PCIE_INT_INTERFACE_IMUX_OUT31", + "PCIE_IMUX31_R_2" ], [ - "CMT_FIFO_L_BYP2_7", - "CMT_TOP_BYP2_4" + "PCIE_INT_INTERFACE_IMUX_OUT32", + "PCIE_IMUX32_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_0" + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_IMUX33_R_2" ], [ - "CMT_FIFO_WR1END1_7", - "CMT_TOP_WR1END1_4" + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_IMUX34_R_2" ], [ - "CMT_FIFO_L_IMUX33_6", - "CMT_TOP_IMUX33_3" + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_IMUX35_R_2" ], [ - "CMT_FIFO_WW2A2_11", - "CMT_TOP_WW2A2_8" + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_IMUX36_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_7" + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_IMUX37_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_0" + "PCIE_INT_INTERFACE_IMUX_OUT38", + "PCIE_IMUX38_R_2" ], [ - "CMT_FIFO_L_IMUX33_5", - "CMT_TOP_IMUX33_2" + "PCIE_INT_INTERFACE_IMUX_OUT39", + "PCIE_IMUX39_R_2" ], [ - "CMT_FIFO_L_FAN5_4", - "CMT_TOP_FAN5_1" + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_IMUX40_R_2" ], [ - "CMT_FIFO_L_BYP7_9", - "CMT_TOP_BYP7_6" + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_IMUX41_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_4" + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_IMUX42_R_2" ], [ - "CMT_FIFO_EE4BEG2_9", - "CMT_TOP_EE4BEG2_6" + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_IMUX43_R_2" ], [ - "CMT_FIFO_SE4BEG0_5", - "CMT_TOP_SE4BEG0_2" + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_IMUX44_R_2" ], [ - "CMT_FIFO_L_LOGIC_OUTS5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_1" + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_IMUX45_R_2" ], [ - "CMT_FIFO_WW2A0_6", - "CMT_TOP_WW2A0_3" + "PCIE_INT_INTERFACE_IMUX_OUT46", + "PCIE_IMUX46_R_2" ], [ - "CMT_FIFO_EE4B1_5", - "CMT_TOP_EE4B1_2" - ], - [ - "CMT_FIFO_NE4C3_5", - "CMT_TOP_NE4C3_2" - ], - [ - "CMT_FIFO_SW2A1_4", - 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"INT_INTERFACE_EE4B0", + "PCIE_EE4B0_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_1" + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_3" ], [ - "CMT_FIFO_NE2A1_3", - "CMT_TOP_NE2A1_0" + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_3" ], [ - "CMT_FIFO_NW2A0_10", - "CMT_TOP_NW2A0_7" + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_7" + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_3" ], [ - "CMT_FIFO_EE2BEG0_9", - "CMT_TOP_EE2BEG0_6" + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_3" ], [ - "CMT_FIFO_L_IMUX3_3", - "CMT_TOP_IMUX3_0" + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_3" ], [ - "CMT_FIFO_EE2BEG2_10", - "CMT_TOP_EE2BEG2_7" + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_3" ], [ - "CMT_FIFO_LH1_4", - "CMT_TOP_LH1_1" + "INT_INTERFACE_EE4C0", + "PCIE_EE4C0_3" ], [ - "CMT_FIFO_EE4B1_4", - "CMT_TOP_EE4B1_1" + "INT_INTERFACE_EE4C1", + "PCIE_EE4C1_3" ], [ - "CMT_FIFO_NW4A2_5", - "CMT_TOP_NW4A2_2" + "INT_INTERFACE_EE4C2", + "PCIE_EE4C2_3" ], [ - "CMT_FIFO_WW4C2_4", - "CMT_TOP_WW4C2_1" + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_3" ], [ - "CMT_FIFO_NW4A2_9", - "CMT_TOP_NW4A2_6" + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_3" ], [ - "CMT_FIFO_L_IMUX18_10", - "CMT_TOP_IMUX18_7" + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_3" ], [ - "CMT_FIFO_NE4C2_6", - "CMT_TOP_NE4C2_3" + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_3" ], [ - "CMT_FIFO_NW4A0_6", - "CMT_TOP_NW4A0_3" + "INT_INTERFACE_EL1BEG3", + "PCIE_EL1BEG3_3" ], [ - "CMT_FIFO_L_FAN6_11", - "CMT_TOP_FAN6_8" + "INT_INTERFACE_ER1BEG0", + "PCIE_ER1BEG0_3" ], [ - "CMT_FIFO_L_IMUX21_3", - "CMT_TOP_IMUX21_0" + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_3" ], [ - "CMT_FIFO_SE2A2_3", - "CMT_TOP_SE2A2_0" + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_3" ], [ - "CMT_FIFO_L_BYP1_11", - "CMT_TOP_BYP1_8" + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_3" ], [ - "CMT_FIFO_L_IMUX43_4", - "CMT_TOP_IMUX43_1" + "INT_INTERFACE_FAN0", + "PCIE_FAN0_R_3" ], [ - "CMT_FIFO_ER1BEG3_4", - "CMT_TOP_ER1BEG3_1" + "INT_INTERFACE_FAN1", + "PCIE_FAN1_R_3" ], [ - "CMT_FIFO_WW4C0_8", - "CMT_TOP_WW4C0_5" + "INT_INTERFACE_FAN2", + "PCIE_FAN2_R_3" ], [ - "CMT_FIFO_NW4A3_10", - "CMT_TOP_NW4A3_7" + "INT_INTERFACE_FAN3", + "PCIE_FAN3_R_3" ], [ - "CMT_FIFO_SE4BEG2_9", - "CMT_TOP_SE4BEG2_6" + "INT_INTERFACE_FAN4", + "PCIE_FAN4_R_3" ], [ - "CMT_FIFO_L_BYP5_3", - "CMT_TOP_BYP5_0" + "INT_INTERFACE_FAN5", + "PCIE_FAN5_R_3" ], [ - "CMT_FIFO_ER1BEG3_3", - "CMT_TOP_ER1BEG3_0" + "INT_INTERFACE_FAN6", + "PCIE_FAN6_R_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_7" + "INT_INTERFACE_FAN7", + "PCIE_FAN7_R_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_3" + "INT_INTERFACE_LH1", + "PCIE_LH1_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_0" + "INT_INTERFACE_LH2", + "PCIE_LH2_3" ], [ - "CMT_FIFO_L_IMUX4_7", - "CMT_TOP_IMUX4_4" + "INT_INTERFACE_LH3", + "PCIE_LH3_3" ], [ - "CMT_FIFO_NE4BEG2_5", - "CMT_TOP_NE4BEG2_2" + "INT_INTERFACE_LH4", + "PCIE_LH4_3" ], [ - "CMT_FIFO_SE4BEG3_7", - "CMT_TOP_SE4BEG3_4" + "INT_INTERFACE_LH5", + "PCIE_LH5_3" ], [ - "CMT_FIFO_EL1BEG1_7", - "CMT_TOP_EL1BEG1_4" + "INT_INTERFACE_LH6", + "PCIE_LH6_3" ], [ - "CMT_FIFO_EE4BEG0_3", - "CMT_TOP_EE4BEG0_0" + "INT_INTERFACE_LH7", + "PCIE_LH7_3" ], [ - "CMT_FIFO_EL1BEG1_4", - "CMT_TOP_EL1BEG1_1" + "INT_INTERFACE_LH8", + "PCIE_LH8_3" ], [ - "CMT_FIFO_LH3_3", - "CMT_TOP_LH3_0" + "INT_INTERFACE_LH9", + "PCIE_LH9_3" ], [ - "CMT_FIFO_NE4C2_9", - "CMT_TOP_NE4C2_6" + "INT_INTERFACE_LH10", + "PCIE_LH10_3" ], [ - "CMT_FIFO_L_BYP2_6", - "CMT_TOP_BYP2_3" + "INT_INTERFACE_LH11", + "PCIE_LH11_3" ], [ - "CMT_FIFO_L_BYP2_8", - "CMT_TOP_BYP2_5" + "INT_INTERFACE_LH12", + "PCIE_LH12_3" ], [ - "CMT_FIFO_NW4END1_5", - "CMT_TOP_NW4END1_2" + "INT_INTERFACE_LOGIC_OUTS_B0", + "PCIE_LOGIC_OUTS_B0_R_3" ], [ - "CMT_FIFO_WW4C0_3", - "CMT_TOP_WW4C0_0" + "INT_INTERFACE_LOGIC_OUTS_B1", + "PCIE_LOGIC_OUTS_B1_R_3" ], [ - "CMT_FIFO_NW4A1_7", - "CMT_TOP_NW4A1_4" + "INT_INTERFACE_LOGIC_OUTS_B2", + "PCIE_LOGIC_OUTS_B2_R_3" ], [ - "CMT_FIFO_WL1END1_9", - "CMT_TOP_WL1END1_6" + "INT_INTERFACE_LOGIC_OUTS_B3", + "PCIE_LOGIC_OUTS_B3_R_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_8" + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_LOGIC_OUTS_B4_R_3" ], [ - "CMT_FIFO_LH4_10", - "CMT_TOP_LH4_7" + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_LOGIC_OUTS_B5_R_3" ], [ - "CMT_FIFO_WW4END0_5", - "CMT_TOP_WW4END0_2" + "INT_INTERFACE_LOGIC_OUTS_B6", + "PCIE_LOGIC_OUTS_B6_R_3" ], [ - "CMT_FIFO_NE2A1_5", - "CMT_TOP_NE2A1_2" + "INT_INTERFACE_LOGIC_OUTS_B7", + "PCIE_LOGIC_OUTS_B7_R_3" ], [ - "CMT_FIFO_EE4B0_9", - "CMT_TOP_EE4B0_6" + "INT_INTERFACE_LOGIC_OUTS_B8", + "PCIE_LOGIC_OUTS_B8_R_3" ], [ - "CMT_FIFO_L_IMUX27_5", - "CMT_TOP_IMUX27_2" + "INT_INTERFACE_LOGIC_OUTS_B9", + "PCIE_LOGIC_OUTS_B9_R_3" ], [ - "CMT_FIFO_L_IMUX21_8", - "CMT_TOP_IMUX21_5" + "INT_INTERFACE_LOGIC_OUTS_B10", + "PCIE_LOGIC_OUTS_B10_R_3" ], [ - "CMT_FIFO_WW4C0_9", - "CMT_TOP_WW4C0_6" + "INT_INTERFACE_LOGIC_OUTS_B11", + "PCIE_LOGIC_OUTS_B11_R_3" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", - "CMT_TOP_OCLK_3" + "INT_INTERFACE_LOGIC_OUTS_B12", + "PCIE_LOGIC_OUTS_B12_R_3" ], [ - "CMT_FIFO_L_IMUX23_6", - "CMT_TOP_IMUX23_3" + "INT_INTERFACE_LOGIC_OUTS_B13", + "PCIE_LOGIC_OUTS_B13_R_3" ], [ - "CMT_FIFO_EE4A3_10", - "CMT_TOP_EE4A3_7" + "INT_INTERFACE_LOGIC_OUTS_B14", + "PCIE_LOGIC_OUTS_B14_R_3" ], [ - "CMT_FIFO_WW2END1_11", - "CMT_TOP_WW2END1_8" + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_LOGIC_OUTS_B15_R_3" ], [ - "CMT_FIFO_PHASER_TO_IO_ICLK_8", - "CMT_TOP_ICLK_5" + "INT_INTERFACE_LOGIC_OUTS_B16", + "PCIE_LOGIC_OUTS_B16_R_3" ], [ - "CMT_FIFO_SW4A1_3", - "CMT_TOP_SW4A1_0" + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_LOGIC_OUTS_B17_R_3" ], [ - "CMT_FIFO_L_IMUX9_9", - "CMT_TOP_IMUX9_6" + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_LOGIC_OUTS_B18_R_3" ], [ - "CMT_FIFO_EE4C2_10", - "CMT_TOP_EE4C2_7" + "INT_INTERFACE_LOGIC_OUTS_B19", + "PCIE_LOGIC_OUTS_B19_R_3" ], [ - "CMT_FIFO_WW2END2_8", - "CMT_TOP_WW2END2_5" + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_LOGIC_OUTS_B20_R_3" ], [ - "CMT_FIFO_SE4C1_5", - "CMT_TOP_SE4C1_2" + "INT_INTERFACE_LOGIC_OUTS_B21", + "PCIE_LOGIC_OUTS_B21_R_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_8" + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_LOGIC_OUTS_B22_R_3" ], [ - "CMT_FIFO_NW4END2_8", - "CMT_TOP_NW4END2_5" + "INT_INTERFACE_LOGIC_OUTS_B23", + "PCIE_LOGIC_OUTS_B23_R_3" ], [ - "CMT_FIFO_EE2BEG2_3", - "CMT_TOP_EE2BEG2_0" + "INT_INTERFACE_MONITOR_N", + "PCIE_MONITOR_N_3" ], [ - "CMT_FIFO_WW4B3_8", - "CMT_TOP_WW4B3_5" + "INT_INTERFACE_MONITOR_P", + "PCIE_MONITOR_P_3" ], [ - "CMT_FIFO_WR1END2_6", - "CMT_TOP_WR1END2_3" + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_0" + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_3" ], [ - "CMT_FIFO_L_IMUX22_8", - "CMT_TOP_IMUX22_5" + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_4" + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_3" ], [ - "CMT_FIFO_EL1BEG0_10", - "CMT_TOP_EL1BEG0_7" + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_3" ], [ - "CMT_FIFO_L_IMUX36_8", - "CMT_TOP_IMUX36_5" + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_3" ], [ - "CMT_FIFO_LH4_4", - "CMT_TOP_LH4_1" + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_3" ], [ - "CMT_FIFO_NE4C0_3", - "CMT_TOP_NE4C0_0" + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_3" ], [ - "CMT_FIFO_L_FAN6_7", - "CMT_TOP_FAN6_4" + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_3" ], [ - "CMT_FIFO_L_IMUX14_10", - "CMT_TOP_IMUX14_7" + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_3" ], [ - "CMT_FIFO_L_IMUX40_10", - "CMT_TOP_IMUX40_7" + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_3" ], [ - "CMT_FIFO_L_BYP4_7", - "CMT_TOP_BYP4_4" + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_3" ], [ - "CMT_FIFO_L_FAN1_6", - "CMT_TOP_FAN1_3" + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_3" ], [ - "CMT_FIFO_L_IMUX34_3", - "CMT_TOP_IMUX34_0" + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_3" ], [ - "CMT_FIFO_LH12_8", - "CMT_TOP_LH12_5" + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_3" ], [ - "CMT_FIFO_EE4C2_6", - "CMT_TOP_EE4C2_3" + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_3" ], [ - "CMT_FIFO_SE2A3_4", - "CMT_TOP_SE2A3_1" + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_3" ], [ - "CMT_FIFO_EE2A3_8", - "CMT_TOP_EE2A3_5" + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_3" ], [ - "CMT_FIFO_SW4END2_3", - "CMT_TOP_SW4END2_0" + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_1" + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_3" ], [ - "CMT_FIFO_L_IMUX30_4", - "CMT_TOP_IMUX30_1" + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_3" ], [ - "CMT_FIFO_EE2A3_11", - "CMT_TOP_EE2A3_8" + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_3" ], [ - "CMT_FIFO_L_FAN0_10", - "CMT_TOP_FAN0_7" + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_3" ], [ - "CMT_FIFO_L_IMUX11_7", - "CMT_TOP_IMUX11_4" + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_3" ], [ - "CMT_FIFO_SE2A3_6", - "CMT_TOP_SE2A3_3" + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_3" ], [ - "CMT_FIFO_L_IMUX33_8", - "CMT_TOP_IMUX33_5" + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_3" ], [ - "CMT_FIFO_EE4A2_3", - "CMT_TOP_EE4A2_0" + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_3" ], [ - "CMT_FIFO_NE4C0_11", - "CMT_TOP_NE4C0_8" + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_3" ], [ - "CMT_FIFO_WW2A2_4", - "CMT_TOP_WW2A2_1" + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_3" ], [ - "CMT_FIFO_WW2END2_3", - "CMT_TOP_WW2END2_0" + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_3" ], [ - "CMT_FIFO_LH2_11", - "CMT_TOP_LH2_8" + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_3" ], [ - "CMT_FIFO_L_BYP0_5", - "CMT_TOP_BYP0_2" + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_3" ], [ - "CMT_FIFO_L_IMUX0_8", - "CMT_TOP_IMUX0_5" + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_3" ], [ - "CMT_FIFO_LH1_7", - "CMT_TOP_LH1_4" + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_3" ], [ - "CMT_FIFO_WW4B0_3", - "CMT_TOP_WW4B0_0" + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_3" ], [ - "CMT_FIFO_L_IMUX36_10", - "CMT_TOP_IMUX36_7" + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_3" ], [ - "CMT_FIFO_LH5_10", - "CMT_TOP_LH5_7" + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_7" + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_3" ], [ - "CMT_FIFO_L_FAN5_6", - "CMT_TOP_FAN5_3" + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_3" ], [ - "CMT_FIFO_WW4END2_10", - "CMT_TOP_WW4END2_7" + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_7" + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_3" ], [ - "CMT_FIFO_WL1END0_7", - "CMT_TOP_WL1END0_4" + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_3" ], [ - "CMT_FIFO_L_IMUX8_7", - "CMT_TOP_IMUX8_4" + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_3" ], [ - "CMT_FIFO_EL1BEG0_8", - "CMT_TOP_EL1BEG0_5" + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_3" ], [ - "CMT_FIFO_NW4A2_3", - "CMT_TOP_NW4A2_0" + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_3" ], [ - "CMT_FIFO_WL1END0_6", - "CMT_TOP_WL1END0_3" + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_3" ], [ - "CMT_FIFO_NE4BEG2_9", - "CMT_TOP_NE4BEG2_6" + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_3" ], [ - "CMT_FIFO_LH5_9", - "CMT_TOP_LH5_6" + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_4" + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_3" ], [ - "CMT_FIFO_ER1BEG2_8", - "CMT_TOP_ER1BEG2_5" + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_3" ], [ - "CMT_FIFO_L_IMUX12_7", - "CMT_TOP_IMUX12_4" + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_3" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", - "CMT_TOP_OCLK_2" + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_3" ], [ - "CMT_FIFO_SW2A1_3", - "CMT_TOP_SW2A1_0" + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_3" ], [ - "CMT_FIFO_L_FAN4_3", - "CMT_TOP_FAN4_0" + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_3" ], [ - "CMT_FIFO_WW2A3_6", - "CMT_TOP_WW2A3_3" + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_3" ], [ - "CMT_FIFO_NW4END0_5", - "CMT_TOP_NW4END0_2" + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_3" ], [ - "CMT_FIFO_NE4C1_4", - "CMT_TOP_NE4C1_1" + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_3" ], [ - "CMT_FIFO_SE4BEG0_7", - "CMT_TOP_SE4BEG0_4" + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_3" ], [ - "CMT_FIFO_NW4A3_9", - "CMT_TOP_NW4A3_6" + "INT_INTERFACE_WW2A2", + "PCIE_WW2A2_3" ], [ - "CMT_FIFO_WR1END2_7", - "CMT_TOP_WR1END2_4" + "INT_INTERFACE_WW2A3", + "PCIE_WW2A3_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_8" + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_3" ], [ - "CMT_FIFO_PHASER_TO_IO_ICLK_9", - "CMT_TOP_ICLK_6" + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_3" ], [ - "CMT_FIFO_L_IMUX27_4", - "CMT_TOP_IMUX27_1" + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_3" ], [ - "CMT_FIFO_NE4C1_3", - "CMT_TOP_NE4C1_0" + "INT_INTERFACE_WW2END3", + "PCIE_WW2END3_3" ], [ - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", - "CMT_TOP_OCLKDIV_1" + "INT_INTERFACE_WW4A0", + "PCIE_WW4A0_3" ], [ - "CMT_FIFO_WL1END1_10", - "CMT_TOP_WL1END1_7" + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_3" ], [ - "CMT_FIFO_L_IMUX20_6", - "CMT_TOP_IMUX20_3" + "INT_INTERFACE_WW4A2", + "PCIE_WW4A2_3" ], [ - "CMT_FIFO_L_IMUX21_10", - "CMT_TOP_IMUX21_7" + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_3" ], [ - "CMT_FIFO_WW4A2_5", - "CMT_TOP_WW4A2_2" + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_3" ], [ - "CMT_FIFO_EE4A0_6", - "CMT_TOP_EE4A0_3" + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_3" ], [ - "CMT_FIFO_WW2A1_4", - "CMT_TOP_WW2A1_1" + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_3" ], [ - "CMT_FIFO_L_IMUX26_7", - "CMT_TOP_IMUX26_4" + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_3" ], [ - "CMT_FIFO_L_IMUX13_3", - "CMT_TOP_IMUX13_0" + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_3" ], [ - "CMT_FIFO_L_IMUX40_8", - "CMT_TOP_IMUX40_5" + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_3" ], [ - "CMT_FIFO_WW4A1_7", - "CMT_TOP_WW4A1_4" + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_3" ], [ - "CMT_FIFO_EE2BEG3_11", - "CMT_TOP_EE2BEG3_8" + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_3" ], [ - "CMT_FIFO_WW2END2_9", - "CMT_TOP_WW2END2_6" + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_3" ], [ - "CMT_FIFO_WL1END1_4", - "CMT_TOP_WL1END1_1" + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_3" ], [ - "CMT_FIFO_NE4BEG3_7", - "CMT_TOP_NE4BEG3_4" + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_3" ], [ - "CMT_FIFO_L_IMUX23_9", - "CMT_TOP_IMUX23_6" + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_3" ], [ - "CMT_FIFO_EE4C3_5", - "CMT_TOP_EE4C3_2" + "PCIE_INT_INTERFACE_IMUX_OUT0", + "PCIE_IMUX0_R_3" ], [ - "CMT_FIFO_L_IMUX32_4", - "CMT_TOP_IMUX32_1" + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_IMUX1_R_3" ], [ - "CMT_FIFO_NW2A0_8", - "CMT_TOP_NW2A0_5" + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_IMUX2_R_3" ], [ - "CMT_FIFO_L_CLK0_11", - "CMT_TOP_CLK0_8" + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_IMUX3_R_3" ], [ - "CMT_FIFO_L_IMUX9_11", - "CMT_TOP_IMUX9_8" + "PCIE_INT_INTERFACE_IMUX_OUT4", + "PCIE_IMUX4_R_3" ], [ - "CMT_FIFO_NW4A2_4", - "CMT_TOP_NW4A2_1" + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_IMUX5_R_3" ], [ - "CMT_FIFO_NE4BEG3_5", - "CMT_TOP_NE4BEG3_2" + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_IMUX6_R_3" ], [ - "CMT_FIFO_L_IMUX16_9", - "CMT_TOP_IMUX16_6" + "PCIE_INT_INTERFACE_IMUX_OUT7", + "PCIE_IMUX7_R_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_5" + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_IMUX8_R_3" ], [ - "CMT_FIFO_L_IMUX2_6", - "CMT_TOP_IMUX2_3" + "PCIE_INT_INTERFACE_IMUX_OUT9", + "PCIE_IMUX9_R_3" ], [ - "CMT_FIFO_LH2_4", - "CMT_TOP_LH2_1" + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_IMUX10_R_3" ], [ - "CMT_FIFO_L_FAN3_5", - "CMT_TOP_FAN3_2" + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_IMUX11_R_3" ], [ - "CMT_FIFO_SW2A3_8", - "CMT_TOP_SW2A3_5" + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_IMUX12_R_3" ], [ - "CMT_FIFO_WW2A3_8", - "CMT_TOP_WW2A3_5" + "PCIE_INT_INTERFACE_IMUX_OUT13", + "PCIE_IMUX13_R_3" ], [ - "CMT_FIFO_NE4BEG1_6", - "CMT_TOP_NE4BEG1_3" + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_IMUX14_R_3" ], [ - "CMT_FIFO_WW4C0_6", - "CMT_TOP_WW4C0_3" + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_IMUX15_R_3" ], [ - "CMT_FIFO_EE2BEG2_8", - "CMT_TOP_EE2BEG2_5" + "PCIE_INT_INTERFACE_IMUX_OUT16", + "PCIE_IMUX16_R_3" ], [ - "CMT_FIFO_L_IMUX2_10", - "CMT_TOP_IMUX2_7" + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_IMUX17_R_3" ], [ - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", - "CMT_TOP_ICLKDIV_8" + "PCIE_INT_INTERFACE_IMUX_OUT18", + "PCIE_IMUX18_R_3" ], [ - "CMT_FIFO_L_IMUX47_8", - "CMT_TOP_IMUX47_5" + "PCIE_INT_INTERFACE_IMUX_OUT19", + "PCIE_IMUX19_R_3" ], [ - "CMT_FIFO_EE2BEG2_4", - "CMT_TOP_EE2BEG2_1" + "PCIE_INT_INTERFACE_IMUX_OUT20", + "PCIE_IMUX20_R_3" ], [ - "CMT_FIFO_L_IMUX8_3", - "CMT_TOP_IMUX8_0" + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_IMUX21_R_3" ], [ - "CMT_FIFO_WL1END3_4", - "CMT_TOP_WL1END3_1" + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_IMUX22_R_3" ], [ - "CMT_FIFO_EE4A3_6", - "CMT_TOP_EE4A3_3" + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_IMUX23_R_3" ], [ - "CMT_FIFO_SE4BEG2_3", - "CMT_TOP_SE4BEG2_0" + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_IMUX24_R_3" ], [ - "CMT_FIFO_EE2BEG1_4", - "CMT_TOP_EE2BEG1_1" + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_IMUX25_R_3" ], [ - "CMT_FIFO_L_LOGIC_OUTS4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_2" + "PCIE_INT_INTERFACE_IMUX_OUT26", + "PCIE_IMUX26_R_3" ], [ - "CMT_FIFO_SW2A2_3", - "CMT_TOP_SW2A2_0" + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_IMUX27_R_3" ], [ - "CMT_FIFO_SE2A2_10", - "CMT_TOP_SE2A2_7" + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_IMUX28_R_3" ], [ - "CMT_FIFO_EE4B1_11", - "CMT_TOP_EE4B1_8" + "PCIE_INT_INTERFACE_IMUX_OUT29", + "PCIE_IMUX29_R_3" ], [ - "CMT_FIFO_L_BYP5_5", - "CMT_TOP_BYP5_2" + "PCIE_INT_INTERFACE_IMUX_OUT30", + "PCIE_IMUX30_R_3" ], [ - "CMT_FIFO_NE4BEG1_10", - "CMT_TOP_NE4BEG1_7" + "PCIE_INT_INTERFACE_IMUX_OUT31", + "PCIE_IMUX31_R_3" ], [ - "CMT_FIFO_L_IMUX16_5", - "CMT_TOP_IMUX16_2" + "PCIE_INT_INTERFACE_IMUX_OUT32", + "PCIE_IMUX32_R_3" ], [ - "CMT_FIFO_L_BYP2_10", - "CMT_TOP_BYP2_7" + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_IMUX33_R_3" ], [ - "CMT_FIFO_SW4END2_5", - "CMT_TOP_SW4END2_2" + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_IMUX34_R_3" ], [ - "CMT_FIFO_NW4END3_7", - "CMT_TOP_NW4END3_4" + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_IMUX35_R_3" ], [ - "CMT_FIFO_L_IMUX22_5", - "CMT_TOP_IMUX22_2" + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_IMUX36_R_3" ], [ - "CMT_FIFO_L_BYP3_3", - "CMT_TOP_BYP3_0" + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_IMUX37_R_3" ], [ - "CMT_FIFO_WW4A0_8", - "CMT_TOP_WW4A0_5" + "PCIE_INT_INTERFACE_IMUX_OUT38", + "PCIE_IMUX38_R_3" ], [ - "CMT_FIFO_EE2A2_5", - "CMT_TOP_EE2A2_2" + "PCIE_INT_INTERFACE_IMUX_OUT39", + "PCIE_IMUX39_R_3" ], [ - "CMT_FIFO_EE4A2_5", - "CMT_TOP_EE4A2_2" + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_IMUX40_R_3" ], [ - "CMT_FIFO_WW4B1_5", - "CMT_TOP_WW4B1_2" + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_IMUX41_R_3" ], [ - "CMT_FIFO_EE4C3_3", - "CMT_TOP_EE4C3_0" + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_IMUX42_R_3" ], [ - "CMT_FIFO_NW4END0_4", - "CMT_TOP_NW4END0_1" + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_IMUX43_R_3" ], [ - "CMT_FIFO_SW2A3_3", - "CMT_TOP_SW2A3_0" + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_IMUX44_R_3" ], [ - "CMT_FIFO_EE4C2_3", - "CMT_TOP_EE4C2_0" + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_IMUX45_R_3" ], [ - "CMT_FIFO_L_IMUX26_8", - "CMT_TOP_IMUX26_5" + "PCIE_INT_INTERFACE_IMUX_OUT46", + "PCIE_IMUX46_R_3" ], [ - "CMT_FIFO_SW2A1_10", - "CMT_TOP_SW2A1_7" + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_IMUX47_R_3" ] ] }, @@ -98302,124 +472262,132 @@ ], "wire_pairs": [ [ - "INT_INTERFACE_NW2A1", - "PCIE_NW2A1_4" + "INT_INTERFACE_BYP0", + "PCIE_BYP0_R_4" ], [ - "INT_INTERFACE_SE4C0", - "PCIE_SE4C0_4" + "INT_INTERFACE_BYP1", + "PCIE_BYP1_R_4" ], [ - "INT_INTERFACE_ER1BEG3", - "PCIE_ER1BEG3_4" + "INT_INTERFACE_BYP2", + "PCIE_BYP2_R_4" ], [ - "INT_INTERFACE_WW4C3", - "PCIE_WW4C3_4" + "INT_INTERFACE_BYP3", + "PCIE_BYP3_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT7", - "PCIE_IMUX7_R_4" + "INT_INTERFACE_BYP4", + "PCIE_BYP4_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT42", - "PCIE_IMUX42_R_4" + "INT_INTERFACE_BYP5", + "PCIE_BYP5_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT3", - "PCIE_IMUX3_R_4" + "INT_INTERFACE_BYP6", + "PCIE_BYP6_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT28", - "PCIE_IMUX28_R_4" + "INT_INTERFACE_BYP7", + "PCIE_BYP7_R_4" ], [ - "INT_INTERFACE_WR1END3", - "PCIE_WR1END3_4" + "INT_INTERFACE_CLK0", + "PCIE_CLK0_R_4" ], [ - "INT_INTERFACE_SE4C1", - "PCIE_SE4C1_4" + "INT_INTERFACE_CLK1", + "PCIE_CLK1_R_4" ], [ - "INT_INTERFACE_SW4A2", - "PCIE_SW4A2_4" + "INT_INTERFACE_CTRL0", + "PCIE_CTRL0_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT36", - "PCIE_IMUX36_R_4" + "INT_INTERFACE_CTRL1", + "PCIE_CTRL1_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT32", - "PCIE_IMUX32_R_4" + "INT_INTERFACE_EE2A0", + "PCIE_EE2A0_4" ], [ - "INT_INTERFACE_LOGIC_OUTS_B18", - "PCIE_LOGIC_OUTS_B18_R_4" + "INT_INTERFACE_EE2A1", + "PCIE_EE2A1_4" ], [ - "INT_INTERFACE_WW2END0", - "PCIE_WW2END0_4" + "INT_INTERFACE_EE2A2", + "PCIE_EE2A2_4" ], [ - "INT_INTERFACE_NW4END3", - "PCIE_NW4END3_4" + "INT_INTERFACE_EE2A3", + "PCIE_EE2A3_4" ], [ - "INT_INTERFACE_WW4B1", - "PCIE_WW4B1_4" + "INT_INTERFACE_EE2BEG0", + "PCIE_EE2BEG0_4" ], [ - "INT_INTERFACE_NE4C3", - "PCIE_NE4C3_4" + "INT_INTERFACE_EE2BEG1", + "PCIE_EE2BEG1_4" ], [ - "INT_INTERFACE_EE4B2", - "PCIE_EE4B2_4" - ], - [ - "INT_INTERFACE_LH1", - "PCIE_LH1_4" - ], - [ - "INT_INTERFACE_WW4C1", - "PCIE_WW4C1_4" - ], - [ - "INT_INTERFACE_LH11", - "PCIE_LH11_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT29", - "PCIE_IMUX29_R_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B16", - "PCIE_LOGIC_OUTS_B16_R_4" - ], - [ - "INT_INTERFACE_NW2A0", - "PCIE_NW2A0_4" + "INT_INTERFACE_EE2BEG2", + "PCIE_EE2BEG2_4" ], [ "INT_INTERFACE_EE2BEG3", "PCIE_EE2BEG3_4" ], [ - "INT_INTERFACE_WW4END2", - "PCIE_WW4END2_4" + "INT_INTERFACE_EE4A0", + "PCIE_EE4A0_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT17", - "PCIE_IMUX17_R_4" + "INT_INTERFACE_EE4A1", + "PCIE_EE4A1_4" ], [ - "INT_INTERFACE_LH9", - "PCIE_LH9_4" + "INT_INTERFACE_EE4A2", + "PCIE_EE4A2_4" ], [ - "INT_INTERFACE_WW4C0", - "PCIE_WW4C0_4" + "INT_INTERFACE_EE4A3", + "PCIE_EE4A3_4" + ], + [ + "INT_INTERFACE_EE4B0", + "PCIE_EE4B0_4" + ], + [ + "INT_INTERFACE_EE4B1", + "PCIE_EE4B1_4" + ], + [ + "INT_INTERFACE_EE4B2", + "PCIE_EE4B2_4" + ], + [ + "INT_INTERFACE_EE4B3", + "PCIE_EE4B3_4" + ], + [ + "INT_INTERFACE_EE4BEG0", + "PCIE_EE4BEG0_4" + ], + [ + "INT_INTERFACE_EE4BEG1", + "PCIE_EE4BEG1_4" + ], + [ + "INT_INTERFACE_EE4BEG2", + "PCIE_EE4BEG2_4" + ], + [ + "INT_INTERFACE_EE4BEG3", + "PCIE_EE4BEG3_4" ], [ "INT_INTERFACE_EE4C0", @@ -98429,538 +472397,454 @@ "INT_INTERFACE_EE4C1", "PCIE_EE4C1_4" ], - [ - "INT_INTERFACE_EE4A0", - "PCIE_EE4A0_4" - ], - [ - "INT_INTERFACE_LH12", - "PCIE_LH12_4" - ], - [ - "INT_INTERFACE_WW2END1", - "PCIE_WW2END1_4" - ], - [ - "INT_INTERFACE_NE2A3", - "PCIE_NE2A3_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT46", - "PCIE_IMUX46_R_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B9", - "PCIE_LOGIC_OUTS_B9_R_4" - ], - [ - "INT_INTERFACE_SE2A1", - "PCIE_SE2A1_4" - ], - [ - "INT_INTERFACE_EE2BEG0", - "PCIE_EE2BEG0_4" - ], - [ - "INT_INTERFACE_LH8", - "PCIE_LH8_4" - ], - [ - "INT_INTERFACE_EE4B1", - "PCIE_EE4B1_4" - ], - [ - "INT_INTERFACE_ER1BEG2", - "PCIE_ER1BEG2_4" - ], - [ - "INT_INTERFACE_WW4C2", - "PCIE_WW4C2_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT4", - "PCIE_IMUX4_R_4" - ], - [ - "INT_INTERFACE_SE4BEG1", - "PCIE_SE4BEG1_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B15", - "PCIE_LOGIC_OUTS_B15_R_4" - ], - [ - "INT_INTERFACE_EE4BEG1", - "PCIE_EE4BEG1_4" - ], - [ - "INT_INTERFACE_NE4BEG1", - "PCIE_NE4BEG1_4" - ], - [ - "INT_INTERFACE_WW4B2", - "PCIE_WW4B2_4" - ], [ "INT_INTERFACE_EE4C2", "PCIE_EE4C2_4" ], [ - "INT_INTERFACE_BYP1", - "PCIE_BYP1_R_4" + "INT_INTERFACE_EE4C3", + "PCIE_EE4C3_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT16", - "PCIE_IMUX16_R_4" + "INT_INTERFACE_EL1BEG0", + "PCIE_EL1BEG0_4" ], [ - "INT_INTERFACE_LOGIC_OUTS_B21", - "PCIE_LOGIC_OUTS_B21_R_4" + "INT_INTERFACE_EL1BEG1", + "PCIE_EL1BEG1_4" ], [ - "INT_INTERFACE_EE4A1", - "PCIE_EE4A1_4" - ], - [ - "INT_INTERFACE_BYP3", - "PCIE_BYP3_R_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B2", - "PCIE_LOGIC_OUTS_B2_R_4" - ], - [ - "INT_INTERFACE_LH3", - "PCIE_LH3_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT47", - "PCIE_IMUX47_R_4" + "INT_INTERFACE_EL1BEG2", + "PCIE_EL1BEG2_4" ], [ "INT_INTERFACE_EL1BEG3", "PCIE_EL1BEG3_4" ], - [ - "INT_INTERFACE_FAN5", - "PCIE_FAN5_R_4" - ], - [ - "INT_INTERFACE_SE4BEG2", - "PCIE_SE4BEG2_4" - ], - [ - "INT_INTERFACE_SW4A3", - "PCIE_SW4A3_4" - ], - [ - "INT_INTERFACE_NE2A0", - "PCIE_NE2A0_4" - ], - [ - "INT_INTERFACE_WL1END2", - "PCIE_WL1END2_4" - ], - [ - "INT_INTERFACE_CLK0", - "PCIE_CLK0_R_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B0", - "PCIE_LOGIC_OUTS_B0_R_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B12", - "PCIE_LOGIC_OUTS_B12_R_4" - ], - [ - "INT_INTERFACE_WW2A1", - "PCIE_WW2A1_4" - ], - [ - "INT_INTERFACE_LH7", - "PCIE_LH7_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B13", - "PCIE_LOGIC_OUTS_B13_R_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT15", - "PCIE_IMUX15_R_4" - ], - [ - "INT_INTERFACE_SW2A2", - "PCIE_SW2A2_4" - ], - [ - "INT_INTERFACE_SW4A0", - "PCIE_SW4A0_4" - ], - [ - "INT_INTERFACE_WL1END0", - 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"PCIE_IMUX2_R_4" - ], - [ - "INT_INTERFACE_WL1END1", - "PCIE_WL1END1_4" - ], - [ - "INT_INTERFACE_WW4B3", - "PCIE_WW4B3_4" - ], - [ - "INT_INTERFACE_SW2A3", - "PCIE_SW2A3_4" - ], - [ - "INT_INTERFACE_BYP6", - "PCIE_BYP6_R_4" - ], - [ - "INT_INTERFACE_CLK1", - "PCIE_CLK1_R_4" - ], - [ - "INT_INTERFACE_WW4B0", - "PCIE_WW4B0_4" - ], - [ - "INT_INTERFACE_LH10", - "PCIE_LH10_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT45", - "PCIE_IMUX45_R_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT8", - "PCIE_IMUX8_R_4" - ], - [ - "INT_INTERFACE_SE4C3", - "PCIE_SE4C3_4" - ], [ "INT_INTERFACE_ER1BEG0", "PCIE_ER1BEG0_4" ], [ - "INT_INTERFACE_NE4BEG2", - "PCIE_NE4BEG2_4" + "INT_INTERFACE_ER1BEG1", + "PCIE_ER1BEG1_4" ], [ - "INT_INTERFACE_BYP7", - "PCIE_BYP7_R_4" + "INT_INTERFACE_ER1BEG2", + "PCIE_ER1BEG2_4" ], [ - "INT_INTERFACE_LH4", - "PCIE_LH4_4" - ], - [ - "INT_INTERFACE_EE2A3", - "PCIE_EE2A3_4" - ], - [ - "INT_INTERFACE_FAN1", - "PCIE_FAN1_R_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B17", - "PCIE_LOGIC_OUTS_B17_R_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B5", - "PCIE_LOGIC_OUTS_B5_R_4" - ], - [ - "INT_INTERFACE_WW4END1", - "PCIE_WW4END1_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT35", - "PCIE_IMUX35_R_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT21", - "PCIE_IMUX21_R_4" - ], - [ - "INT_INTERFACE_WW4END0", - "PCIE_WW4END0_4" - ], - [ - "INT_INTERFACE_WW4A3", - "PCIE_WW4A3_4" + "INT_INTERFACE_ER1BEG3", + "PCIE_ER1BEG3_4" ], [ "INT_INTERFACE_FAN0", "PCIE_FAN0_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT14", - "PCIE_IMUX14_R_4" + "INT_INTERFACE_FAN1", + "PCIE_FAN1_R_4" ], [ - "INT_INTERFACE_NE4C0", - "PCIE_NE4C0_4" + "INT_INTERFACE_FAN2", + "PCIE_FAN2_R_4" ], [ - "INT_INTERFACE_NW2A3", - "PCIE_NW2A3_4" + "INT_INTERFACE_FAN3", + "PCIE_FAN3_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT11", - "PCIE_IMUX11_R_4" + "INT_INTERFACE_FAN4", + "PCIE_FAN4_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT33", - "PCIE_IMUX33_R_4" + "INT_INTERFACE_FAN5", + "PCIE_FAN5_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT18", - "PCIE_IMUX18_R_4" + "INT_INTERFACE_FAN6", + "PCIE_FAN6_R_4" + ], + [ + "INT_INTERFACE_FAN7", + "PCIE_FAN7_R_4" + ], + [ + "INT_INTERFACE_LH1", + "PCIE_LH1_4" + ], + [ + "INT_INTERFACE_LH2", + "PCIE_LH2_4" + ], + [ + "INT_INTERFACE_LH3", + "PCIE_LH3_4" + ], + [ + "INT_INTERFACE_LH4", + "PCIE_LH4_4" + ], + [ + "INT_INTERFACE_LH5", + "PCIE_LH5_4" + ], + [ + "INT_INTERFACE_LH6", + "PCIE_LH6_4" + ], + [ + "INT_INTERFACE_LH7", + "PCIE_LH7_4" + ], + [ + "INT_INTERFACE_LH8", + "PCIE_LH8_4" + ], + [ + "INT_INTERFACE_LH9", + "PCIE_LH9_4" + ], + [ + "INT_INTERFACE_LH10", + "PCIE_LH10_4" + ], + [ + "INT_INTERFACE_LH11", + "PCIE_LH11_4" + ], + [ + "INT_INTERFACE_LH12", + "PCIE_LH12_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B0", + "PCIE_LOGIC_OUTS_B0_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B1", + "PCIE_LOGIC_OUTS_B1_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B2", + "PCIE_LOGIC_OUTS_B2_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B3", + "PCIE_LOGIC_OUTS_B3_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_LOGIC_OUTS_B4_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_LOGIC_OUTS_B5_R_4" ], [ "INT_INTERFACE_LOGIC_OUTS_B6", "PCIE_LOGIC_OUTS_B6_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT13", - "PCIE_IMUX13_R_4" + "INT_INTERFACE_LOGIC_OUTS_B7", + "PCIE_LOGIC_OUTS_B7_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT26", - "PCIE_IMUX26_R_4" + "INT_INTERFACE_LOGIC_OUTS_B8", + "PCIE_LOGIC_OUTS_B8_R_4" ], [ - "INT_INTERFACE_EE4A2", - "PCIE_EE4A2_4" + "INT_INTERFACE_LOGIC_OUTS_B9", + "PCIE_LOGIC_OUTS_B9_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT20", - "PCIE_IMUX20_R_4" + "INT_INTERFACE_LOGIC_OUTS_B10", + "PCIE_LOGIC_OUTS_B10_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT10", - "PCIE_IMUX10_R_4" + "INT_INTERFACE_LOGIC_OUTS_B11", + "PCIE_LOGIC_OUTS_B11_R_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT22", - "PCIE_IMUX22_R_4" + "INT_INTERFACE_LOGIC_OUTS_B12", + "PCIE_LOGIC_OUTS_B12_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B13", + "PCIE_LOGIC_OUTS_B13_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B14", + "PCIE_LOGIC_OUTS_B14_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_LOGIC_OUTS_B15_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B16", + "PCIE_LOGIC_OUTS_B16_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_LOGIC_OUTS_B17_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_LOGIC_OUTS_B18_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B19", + "PCIE_LOGIC_OUTS_B19_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_LOGIC_OUTS_B20_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B21", + "PCIE_LOGIC_OUTS_B21_R_4" + ], + [ + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_LOGIC_OUTS_B22_R_4" ], [ "INT_INTERFACE_LOGIC_OUTS_B23", "PCIE_LOGIC_OUTS_B23_R_4" ], + [ + "INT_INTERFACE_NE2A0", + "PCIE_NE2A0_4" + ], + [ + "INT_INTERFACE_NE2A1", + "PCIE_NE2A1_4" + ], + [ + "INT_INTERFACE_NE2A2", + "PCIE_NE2A2_4" + ], + [ + "INT_INTERFACE_NE2A3", + "PCIE_NE2A3_4" + ], + [ + "INT_INTERFACE_NE4BEG0", + "PCIE_NE4BEG0_4" + ], + [ + "INT_INTERFACE_NE4BEG1", + "PCIE_NE4BEG1_4" + ], + [ + "INT_INTERFACE_NE4BEG2", + "PCIE_NE4BEG2_4" + ], + [ + "INT_INTERFACE_NE4BEG3", + "PCIE_NE4BEG3_4" + ], + [ + "INT_INTERFACE_NE4C0", + "PCIE_NE4C0_4" + ], + [ + "INT_INTERFACE_NE4C1", + "PCIE_NE4C1_4" + ], + [ + "INT_INTERFACE_NE4C2", + "PCIE_NE4C2_4" + ], + [ + "INT_INTERFACE_NE4C3", + "PCIE_NE4C3_4" + ], + [ + "INT_INTERFACE_NW2A0", + "PCIE_NW2A0_4" + ], + [ + "INT_INTERFACE_NW2A1", + "PCIE_NW2A1_4" + ], + [ + "INT_INTERFACE_NW2A2", + "PCIE_NW2A2_4" + ], + [ + "INT_INTERFACE_NW2A3", + "PCIE_NW2A3_4" + ], + [ + "INT_INTERFACE_NW4A0", + "PCIE_NW4A0_4" + ], + [ + "INT_INTERFACE_NW4A1", + "PCIE_NW4A1_4" + ], + [ + "INT_INTERFACE_NW4A2", + "PCIE_NW4A2_4" + ], + [ + "INT_INTERFACE_NW4A3", + "PCIE_NW4A3_4" + ], + [ + "INT_INTERFACE_NW4END0", + "PCIE_NW4END0_4" + ], + [ + "INT_INTERFACE_NW4END1", + "PCIE_NW4END1_4" + ], + [ + "INT_INTERFACE_NW4END2", + "PCIE_NW4END2_4" + ], + [ + "INT_INTERFACE_NW4END3", + "PCIE_NW4END3_4" + ], + [ + "INT_INTERFACE_SE2A0", + "PCIE_SE2A0_4" + ], + [ + "INT_INTERFACE_SE2A1", + "PCIE_SE2A1_4" + ], + [ + "INT_INTERFACE_SE2A2", + "PCIE_SE2A2_4" + ], + [ + "INT_INTERFACE_SE2A3", + "PCIE_SE2A3_4" + ], + [ + "INT_INTERFACE_SE4BEG0", + "PCIE_SE4BEG0_4" + ], + [ + "INT_INTERFACE_SE4BEG1", + "PCIE_SE4BEG1_4" + ], + [ + "INT_INTERFACE_SE4BEG2", + "PCIE_SE4BEG2_4" + ], + [ + "INT_INTERFACE_SE4BEG3", + "PCIE_SE4BEG3_4" + ], + [ + "INT_INTERFACE_SE4C0", + "PCIE_SE4C0_4" + ], + [ + "INT_INTERFACE_SE4C1", + "PCIE_SE4C1_4" + ], + [ + "INT_INTERFACE_SE4C2", + "PCIE_SE4C2_4" + ], + [ + "INT_INTERFACE_SE4C3", + "PCIE_SE4C3_4" + ], + [ + "INT_INTERFACE_SW2A0", + "PCIE_SW2A0_4" + ], + [ + "INT_INTERFACE_SW2A1", + "PCIE_SW2A1_4" + ], + [ + "INT_INTERFACE_SW2A2", + "PCIE_SW2A2_4" + ], + [ + "INT_INTERFACE_SW2A3", + "PCIE_SW2A3_4" + ], + [ + "INT_INTERFACE_SW4A0", + "PCIE_SW4A0_4" + ], + [ + "INT_INTERFACE_SW4A1", + "PCIE_SW4A1_4" + ], + [ + "INT_INTERFACE_SW4A2", + "PCIE_SW4A2_4" + ], + [ + "INT_INTERFACE_SW4A3", + "PCIE_SW4A3_4" + ], + [ + "INT_INTERFACE_SW4END0", + "PCIE_SW4END0_4" + ], + [ + "INT_INTERFACE_SW4END1", + "PCIE_SW4END1_4" + ], + [ + "INT_INTERFACE_SW4END2", + "PCIE_SW4END2_4" + ], + [ + "INT_INTERFACE_SW4END3", + "PCIE_SW4END3_4" + ], + [ + "INT_INTERFACE_WL1END0", + "PCIE_WL1END0_4" + ], + [ + "INT_INTERFACE_WL1END1", + "PCIE_WL1END1_4" + ], + [ + "INT_INTERFACE_WL1END2", + "PCIE_WL1END2_4" + ], + [ + "INT_INTERFACE_WL1END3", + "PCIE_WL1END3_4" + ], + [ + "INT_INTERFACE_WR1END0", + "PCIE_WR1END0_4" + ], + [ + "INT_INTERFACE_WR1END1", + "PCIE_WR1END1_4" + ], + [ + "INT_INTERFACE_WR1END2", + "PCIE_WR1END2_4" + ], + [ + "INT_INTERFACE_WR1END3", + "PCIE_WR1END3_4" + ], + [ + "INT_INTERFACE_WW2A0", + "PCIE_WW2A0_4" + ], + [ + "INT_INTERFACE_WW2A1", + "PCIE_WW2A1_4" + ], [ "INT_INTERFACE_WW2A2", "PCIE_WW2A2_4" @@ -98970,840 +472854,276 @@ "PCIE_WW2A3_4" ], [ - "PCIE_INT_INTERFACE_IMUX_OUT39", - "PCIE_IMUX39_R_4" + "INT_INTERFACE_WW2END0", + "PCIE_WW2END0_4" ], [ - "INT_INTERFACE_NW4A3", - "PCIE_NW4A3_4" + "INT_INTERFACE_WW2END1", + "PCIE_WW2END1_4" + ], + [ + "INT_INTERFACE_WW2END2", + "PCIE_WW2END2_4" ], [ "INT_INTERFACE_WW2END3", "PCIE_WW2END3_4" ], - [ - "INT_INTERFACE_EE2A1", - "PCIE_EE2A1_4" - ], - [ - "INT_INTERFACE_WW4END3", - "PCIE_WW4END3_4" - ], - [ - "INT_INTERFACE_BYP4", - "PCIE_BYP4_R_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT43", - "PCIE_IMUX43_R_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT30", - "PCIE_IMUX30_R_4" - ], - [ - "INT_INTERFACE_SW2A0", - "PCIE_SW2A0_4" - ], - [ - "INT_INTERFACE_FAN4", - "PCIE_FAN4_R_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT27", - "PCIE_IMUX27_R_4" - ], - [ - "INT_INTERFACE_NW4END1", - "PCIE_NW4END1_4" - ], - [ - "INT_INTERFACE_ER1BEG1", - "PCIE_ER1BEG1_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT6", - "PCIE_IMUX6_R_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B14", - "PCIE_LOGIC_OUTS_B14_R_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT12", - "PCIE_IMUX12_R_4" - ], - [ - "INT_INTERFACE_NW4A1", - "PCIE_NW4A1_4" - ], - [ - "INT_INTERFACE_SE2A2", - "PCIE_SE2A2_4" - ], - [ - "INT_INTERFACE_WW2A0", - "PCIE_WW2A0_4" - ], - [ - "INT_INTERFACE_SW4END3", - "PCIE_SW4END3_4" - ], - [ - "INT_INTERFACE_FAN3", - "PCIE_FAN3_R_4" - ], [ "INT_INTERFACE_WW4A0", "PCIE_WW4A0_4" ], [ - "INT_INTERFACE_NE2A2", - "PCIE_NE2A2_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT44", - "PCIE_IMUX44_R_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT9", - "PCIE_IMUX9_R_4" - ], - [ - "INT_INTERFACE_LH6", - "PCIE_LH6_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B10", - "PCIE_LOGIC_OUTS_B10_R_4" - ], - [ - "INT_INTERFACE_EL1BEG0", - "PCIE_EL1BEG0_4" - ], - [ - "INT_INTERFACE_SW4A1", - "PCIE_SW4A1_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT1", - "PCIE_IMUX1_R_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B7", - "PCIE_LOGIC_OUTS_B7_R_4" - ], - [ - "INT_INTERFACE_NW4A2", - "PCIE_NW4A2_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B4", - "PCIE_LOGIC_OUTS_B4_R_4" + "INT_INTERFACE_WW4A1", + "PCIE_WW4A1_4" ], [ "INT_INTERFACE_WW4A2", "PCIE_WW4A2_4" ], [ - "INT_INTERFACE_SW2A1", - "PCIE_SW2A1_4" + "INT_INTERFACE_WW4A3", + "PCIE_WW4A3_4" ], [ - "INT_INTERFACE_SE2A0", - "PCIE_SE2A0_4" + "INT_INTERFACE_WW4B0", + "PCIE_WW4B0_4" ], [ - "INT_INTERFACE_EE4C3", - "PCIE_EE4C3_4" + "INT_INTERFACE_WW4B1", + "PCIE_WW4B1_4" ], [ - "INT_INTERFACE_SE4C2", - "PCIE_SE4C2_4" + "INT_INTERFACE_WW4B2", + "PCIE_WW4B2_4" ], [ - "INT_INTERFACE_NW2A2", - "PCIE_NW2A2_4" + "INT_INTERFACE_WW4B3", + "PCIE_WW4B3_4" ], [ - "INT_INTERFACE_EE4A3", - "PCIE_EE4A3_4" + "INT_INTERFACE_WW4C0", + "PCIE_WW4C0_4" + ], + [ + "INT_INTERFACE_WW4C1", + "PCIE_WW4C1_4" + ], + [ + "INT_INTERFACE_WW4C2", + "PCIE_WW4C2_4" + ], + [ + "INT_INTERFACE_WW4C3", + "PCIE_WW4C3_4" + ], + [ + "INT_INTERFACE_WW4END0", + "PCIE_WW4END0_4" + ], + [ + "INT_INTERFACE_WW4END1", + "PCIE_WW4END1_4" + ], + [ + "INT_INTERFACE_WW4END2", + "PCIE_WW4END2_4" + ], + [ + "INT_INTERFACE_WW4END3", + "PCIE_WW4END3_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT0", + "PCIE_IMUX0_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_IMUX1_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_IMUX2_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT3", + "PCIE_IMUX3_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT4", + "PCIE_IMUX4_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_IMUX5_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_IMUX6_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT7", + "PCIE_IMUX7_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT8", + "PCIE_IMUX8_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT9", + "PCIE_IMUX9_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT10", + "PCIE_IMUX10_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT11", + "PCIE_IMUX11_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT12", + "PCIE_IMUX12_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT13", + "PCIE_IMUX13_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_IMUX14_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_IMUX15_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT16", + "PCIE_IMUX16_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_IMUX17_R_4" + ], + [ + "PCIE_INT_INTERFACE_IMUX_OUT18", + "PCIE_IMUX18_R_4" ], [ "PCIE_INT_INTERFACE_IMUX_OUT19", "PCIE_IMUX19_R_4" ], [ - "INT_INTERFACE_EL1BEG2", - "PCIE_EL1BEG2_4" + "PCIE_INT_INTERFACE_IMUX_OUT20", + "PCIE_IMUX20_R_4" ], [ - "INT_INTERFACE_EE2A2", - "PCIE_EE2A2_4" + "PCIE_INT_INTERFACE_IMUX_OUT21", + "PCIE_IMUX21_R_4" ], [ - "INT_INTERFACE_EL1BEG1", - "PCIE_EL1BEG1_4" + "PCIE_INT_INTERFACE_IMUX_OUT22", + "PCIE_IMUX22_R_4" ], [ - "INT_INTERFACE_SE2A3", - "PCIE_SE2A3_4" - ], - [ - "INT_INTERFACE_NE4BEG0", - "PCIE_NE4BEG0_4" - ], - [ - "INT_INTERFACE_NW4END2", - "PCIE_NW4END2_4" - ], - [ - "INT_INTERFACE_LH5", - "PCIE_LH5_4" + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_IMUX23_R_4" ], [ "PCIE_INT_INTERFACE_IMUX_OUT24", "PCIE_IMUX24_R_4" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_LH10_0", - "VBRK_LH10" - ], - [ - "CLK_HROW_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_LH6_0", - "VBRK_LH6" - ], - [ - "CLK_HROW_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_NW4A1_0", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_LH8_0", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_LH1_0", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_LH5_0", - "VBRK_LH5" - ], - [ - "CLK_HROW_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_HROW_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_LH12_0", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_LH7_0", - "VBRK_LH7" - ], - [ - "CLK_HROW_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH11_0", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4A2_0", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_LH2_0", - "VBRK_LH2" - ], - [ - "CLK_HROW_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH9_0", - "VBRK_LH9" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_FEEDTHRU_1", - "HCLK_FEEDTHRU_1" - ], - "wire_pairs": [ - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_FEEDTHRU_1_CK_BUFRCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_FEEDTHRU_1_CK_BUFRCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_FEEDTHRU_1_CK_IN11" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_FEEDTHRU_1_CK_BUFHCLK5" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_FEEDTHRU_1_CK_BUFHCLK7" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_FEEDTHRU_1_CK_BUFHCLK4" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_FEEDTHRU_1_CK_BUFHCLK3" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_FEEDTHRU_1_CK_BUFHCLK0" + "PCIE_INT_INTERFACE_IMUX_OUT25", + "PCIE_IMUX25_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_FEEDTHRU_1_CK_IN1" + "PCIE_INT_INTERFACE_IMUX_OUT26", + "PCIE_IMUX26_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_FEEDTHRU_1_CK_IN0" + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_IMUX27_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_FEEDTHRU_1_CK_BUFHCLK2" + "PCIE_INT_INTERFACE_IMUX_OUT28", + "PCIE_IMUX28_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_FEEDTHRU_1_CK_BUFHCLK6" + "PCIE_INT_INTERFACE_IMUX_OUT29", + "PCIE_IMUX29_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_FEEDTHRU_1_CK_IN2" + "PCIE_INT_INTERFACE_IMUX_OUT30", + "PCIE_IMUX30_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_FEEDTHRU_1_CK_BUFHCLK8" + "PCIE_INT_INTERFACE_IMUX_OUT31", + "PCIE_IMUX31_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_FEEDTHRU_1_CK_BUFRCLK3" + "PCIE_INT_INTERFACE_IMUX_OUT32", + "PCIE_IMUX32_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_FEEDTHRU_1_CK_IN10" + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_IMUX33_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_FEEDTHRU_1_CK_BUFHCLK1" + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_IMUX34_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_FEEDTHRU_1_CK_IN8" + "PCIE_INT_INTERFACE_IMUX_OUT35", + "PCIE_IMUX35_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_FEEDTHRU_1_CK_IN12" + "PCIE_INT_INTERFACE_IMUX_OUT36", + "PCIE_IMUX36_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_FEEDTHRU_1_CK_IN6" + "PCIE_INT_INTERFACE_IMUX_OUT37", + "PCIE_IMUX37_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_FEEDTHRU_1_CK_IN5" + "PCIE_INT_INTERFACE_IMUX_OUT38", + "PCIE_IMUX38_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_FEEDTHRU_1_CK_BUFRCLK0" + "PCIE_INT_INTERFACE_IMUX_OUT39", + "PCIE_IMUX39_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_FEEDTHRU_1_CK_IN3" + "PCIE_INT_INTERFACE_IMUX_OUT40", + "PCIE_IMUX40_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_FEEDTHRU_1_CK_BUFHCLK10" + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_IMUX41_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_FEEDTHRU_1_CK_IN4" + "PCIE_INT_INTERFACE_IMUX_OUT42", + "PCIE_IMUX42_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_FEEDTHRU_1_CK_BUFHCLK11" + "PCIE_INT_INTERFACE_IMUX_OUT43", + "PCIE_IMUX43_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_FEEDTHRU_1_CK_IN13" + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_IMUX44_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN9", - "HCLK_FEEDTHRU_1_CK_IN9" + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_IMUX45_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_FEEDTHRU_1_CK_BUFHCLK9" + "PCIE_INT_INTERFACE_IMUX_OUT46", + "PCIE_IMUX46_R_4" ], [ - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_FEEDTHRU_1_CK_IN7" + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_IMUX47_R_4" ] ] }, @@ -99817,30 +473137,10 @@ "RIOI" ], "wire_pairs": [ - [ - "IOB_PU_INT_EN_0", - "RIOI_PU_INT_EN_0" - ], - [ - "IOB_T0", - "RIOI_T0" - ], - [ - "IOB_O0", - "RIOI_O0" - ], - [ - "IOB_T1", - "RIOI_T1" - ], [ "IOB_DCI_T_TERM0", "RIOI_DCI_T_TERM0" ], - [ - "IOB_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE0" - ], [ "IOB_DCI_T_TERM1", "RIOI_DCI_T_TERM1" @@ -99850,3096 +473150,68 @@ "RIOI_DIFF_TERM_INT_EN" ], [ - "RIOB_MONITOR_P", - "IOI_MONITOR_P" - ], - [ - "IOB_IBUF_DISABLE1", - "RIOI_IBUF_DISABLE1" + "IOB_IBUF0", + "RIOI_IBUF0" ], [ "IOB_IBUF1", "RIOI_IBUF1" ], + [ + "IOB_IBUF_DISABLE0", + "RIOI_IBUF_DISABLE0" + ], + [ + "IOB_IBUF_DISABLE1", + "RIOI_IBUF_DISABLE1" + ], [ "IOB_KEEPER_INT_EN_0", "RIOI_KEEPER_INT_EN_0" ], - [ - "IOB_PD_INT_EN_0", - "RIOI_PD_INT_EN_0" - ], - [ - "IOB_IBUF0", - "RIOI_IBUF0" - ], - [ - "RIOB_MONITOR_N", - "IOI_MONITOR_N" - ], [ "IOB_KEEPER_INT_EN_1", "RIOI_KEEPER_INT_EN_1" ], [ - "IOB_PD_INT_EN_1", - "RIOI_PD_INT_EN_1" + "IOB_O0", + "RIOI_O0" ], [ "IOB_O1", "RIOI_O1" ], + [ + "IOB_PD_INT_EN_0", + "RIOI_PD_INT_EN_0" + ], + [ + "IOB_PD_INT_EN_1", + "RIOI_PD_INT_EN_1" + ], + [ + "IOB_PU_INT_EN_0", + "RIOI_PU_INT_EN_0" + ], [ "IOB_PU_INT_EN_1", "RIOI_PU_INT_EN_1" - ] - ] - }, - { - "grid_deltas": [ - 1, - -3 - ], - "tile_types": [ - "CFG_CENTER_TOP", - "VFRAME" - ], - "wire_pairs": [ - [ - "CFG_CENTER_FAN1_3", - "VFRAME_FAN1" - ], - [ - "CFG_CENTER_IMUX9_3", - "VFRAME_IMUX9" - ], - [ - "CFG_CENTER_EE4C0_3", - "VFRAME_EE4C0" - ], - [ - "CFG_CENTER_NW2A3_3", - "VFRAME_NW2A3" - ], - [ - "CFG_CENTER_IMUX38_3", - "VFRAME_IMUX38" - ], - [ - "CFG_CENTER_IMUX37_3", - "VFRAME_IMUX37" - ], - [ - "CFG_CENTER_SE4C1_3", - "VFRAME_SE4C1" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B17_3", - "VFRAME_LOGIC_OUTS_B17" - ], - [ - "CFG_CENTER_NE4C0_3", - "VFRAME_NE4C0" - ], - [ - "CFG_CENTER_WW4B1_3", - "VFRAME_WW4B1" - ], - [ - "CFG_CENTER_LH4_3", - "VFRAME_LH4" - ], - [ - "CFG_CENTER_EL1BEG0_3", - "VFRAME_EL1BEG0" - ], - [ - "CFG_CENTER_SW4A3_3", - "VFRAME_SW4A3" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B19_3", - "VFRAME_LOGIC_OUTS_B19" - ], - [ - "CFG_CENTER_WR1END0_3", - "VFRAME_WR1END0" - ], - [ - "CFG_CENTER_IMUX16_3", - "VFRAME_IMUX16" - ], - [ - "CFG_CENTER_SE4BEG0_3", - "VFRAME_SE4BEG0" - ], - [ - "CFG_CENTER_NE4C1_3", - "VFRAME_NE4C1" - ], - [ - "CFG_CENTER_EE4BEG3_3", - "VFRAME_EE4BEG3" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B20_3", - "VFRAME_LOGIC_OUTS_B20" - ], - [ - "CFG_CENTER_NW4END0_3", - "VFRAME_NW4END0" - ], - [ - "CFG_CENTER_SW4A0_3", - "VFRAME_SW4A0" - ], - [ - "CFG_CENTER_EE2BEG0_3", - "VFRAME_EE2BEG0" - ], - [ - "CFG_CENTER_LH3_3", - "VFRAME_LH3" - ], - [ - "CFG_CENTER_SE2A1_3", - "VFRAME_SE2A1" - ], - [ - "CFG_CENTER_IMUX30_3", - "VFRAME_IMUX30" - ], - [ - "CFG_CENTER_SE2A3_3", - "VFRAME_SE2A3" - ], - [ - "CFG_CENTER_IMUX7_3", - "VFRAME_IMUX7" - ], - [ - "CFG_CENTER_NE4BEG1_3", - "VFRAME_NE4BEG1" - ], - [ - "CFG_CENTER_BYP5_3", - "VFRAME_BYP5" - ], - [ - "CFG_CENTER_IMUX23_3", - "VFRAME_IMUX23" - ], - [ - "CFG_CENTER_WL1END0_3", - "VFRAME_WL1END0" - ], - [ - "CFG_CENTER_BYP2_3", - "VFRAME_BYP2" - ], - [ - "CFG_CENTER_IMUX15_3", - "VFRAME_IMUX15" - ], - [ - "CFG_CENTER_BYP0_3", - "VFRAME_BYP0" - ], - [ - "CFG_CENTER_SW4END0_3", - "VFRAME_SW4END0" - ], - [ - "CFG_CENTER_IMUX18_3", - "VFRAME_IMUX18" - ], - [ - "CFG_CENTER_IMUX34_3", - "VFRAME_IMUX34" - ], - [ - "CFG_CENTER_EE4C1_3", - "VFRAME_EE4C1" - ], - [ - "CFG_CENTER_ER1BEG1_3", - "VFRAME_ER1BEG1" - ], - [ - "CFG_CENTER_NE4C3_3", - "VFRAME_NE4C3" - ], - [ - "CFG_CENTER_IMUX31_3", - "VFRAME_IMUX31" - ], - [ - "CFG_CENTER_NW2A2_3", - "VFRAME_NW2A2" - ], - [ - "CFG_CENTER_EE4B2_3", - "VFRAME_EE4B2" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B18_3", - "VFRAME_LOGIC_OUTS_B18" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B16_3", - "VFRAME_LOGIC_OUTS_B16" - ], - [ - "CFG_CENTER_NE2A0_3", - "VFRAME_NE2A0" - ], - [ - "CFG_CENTER_SE4BEG3_3", - "VFRAME_SE4BEG3" - ], - [ - "CFG_CENTER_WW4A0_3", - "VFRAME_WW4A0" - ], - [ - "CFG_CENTER_EE4B0_3", - "VFRAME_EE4B0" - ], - [ - "CFG_CENTER_FAN5_3", - "VFRAME_FAN5" - ], - [ - "CFG_CENTER_IMUX46_3", - "VFRAME_IMUX46" - ], - [ - "CFG_CENTER_WW2A0_3", - "VFRAME_WW2A0" - ], - [ - "CFG_CENTER_NE4BEG3_3", - "VFRAME_NE4BEG3" - ], - [ - "CFG_CENTER_IMUX24_3", - "VFRAME_IMUX24" - ], - [ - "CFG_CENTER_WW4A1_3", - "VFRAME_WW4A1" - ], - [ - "CFG_CENTER_WL1END1_3", - "VFRAME_WL1END1" - ], - [ - "CFG_CENTER_EL1BEG2_3", - "VFRAME_EL1BEG2" - ], - [ - "CFG_CENTER_IMUX29_3", - "VFRAME_IMUX29" - ], - [ - "CFG_CENTER_FAN4_3", - "VFRAME_FAN4" - ], - [ - "CFG_CENTER_WW4A2_3", - "VFRAME_WW4A2" - ], - [ - "CFG_CENTER_BYP1_3", - "VFRAME_BYP1" - ], - [ - "CFG_CENTER_FAN7_3", - "VFRAME_FAN7" - ], - [ - "CFG_CENTER_ER1BEG3_3", - "VFRAME_ER1BEG3" - ], - [ - "CFG_CENTER_SE2A0_3", - "VFRAME_SE2A0" - ], - [ - "CFG_CENTER_IMUX43_3", - "VFRAME_IMUX43" - ], - [ - "CFG_CENTER_NW4A3_3", - "VFRAME_NW4A3" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B22_3", - "VFRAME_LOGIC_OUTS_B22" - ], - [ - "CFG_CENTER_IMUX2_3", - "VFRAME_IMUX2" - ], - [ - "CFG_CENTER_IMUX35_3", - "VFRAME_IMUX35" - ], - [ - "CFG_CENTER_IMUX14_3", - "VFRAME_IMUX14" - ], - [ - "CFG_CENTER_IMUX36_3", - "VFRAME_IMUX36" - ], - [ - "CFG_CENTER_WR1END1_3", - "VFRAME_WR1END1" - ], - [ - "CFG_CENTER_IMUX17_3", - "VFRAME_IMUX17" - ], - [ - "CFG_CENTER_WW2A3_3", - "VFRAME_WW2A3" - ], - [ - "CFG_CENTER_NW4END2_3", - "VFRAME_NW4END2" - ], - [ - "CFG_CENTER_SE4C0_3", - "VFRAME_SE4C0" - ], - [ - "CFG_CENTER_NE4BEG0_3", - "VFRAME_NE4BEG0" - ], - [ - "CFG_CENTER_LH5_3", - "VFRAME_LH5" - ], - [ - "CFG_CENTER_IMUX12_3", - "VFRAME_IMUX12" - ], - [ - "CFG_CENTER_EE4C2_3", - "VFRAME_EE4C2" - ], - [ - "CFG_CENTER_IMUX13_3", - "VFRAME_IMUX13" - ], - [ - "CFG_CENTER_WW4END0_3", - "VFRAME_WW4END0" - ], - [ - "CFG_CENTER_SW4A1_3", - "VFRAME_SW4A1" - ], - [ - "CFG_CENTER_EE2A3_3", - "VFRAME_EE2A3" - ], - [ - "CFG_CENTER_IMUX40_3", - "VFRAME_IMUX40" - ], - [ - "CFG_CENTER_EE4C3_3", - "VFRAME_EE4C3" - ], - [ - "CFG_CENTER_IMUX45_3", - "VFRAME_IMUX45" - ], - [ - "CFG_CENTER_WW4C2_3", - "VFRAME_WW4C2" - ], - [ - "CFG_CENTER_IMUX3_3", - "VFRAME_IMUX3" - ], - [ - "CFG_CENTER_NW2A1_3", - "VFRAME_NW2A1" - ], - [ - "CFG_CENTER_IMUX10_3", - "VFRAME_IMUX10" - ], - [ - "CFG_CENTER_SW4END3_3", - "VFRAME_SW4END3" - ], - [ - "CFG_CENTER_IMUX0_3", - "VFRAME_IMUX0" - ], - [ - "CFG_CENTER_WW4A3_3", - "VFRAME_WW4A3" - ], - [ - "CFG_CENTER_IMUX22_3", - "VFRAME_IMUX22" - ], - [ - "CFG_CENTER_LH7_3", - "VFRAME_LH7" - ], - [ - "CFG_CENTER_IMUX42_3", - "VFRAME_IMUX42" - ], - [ - "CFG_CENTER_LH6_3", - "VFRAME_LH6" - ], - [ - "CFG_CENTER_NW4A0_3", - "VFRAME_NW4A0" - ], - [ - "CFG_CENTER_IMUX32_3", - "VFRAME_IMUX32" - ], - [ - "CFG_CENTER_BYP4_3", - "VFRAME_BYP4" - ], - [ - "CFG_CENTER_WL1END3_3", - "VFRAME_WL1END3" - ], - [ - "CFG_CENTER_WW4B2_3", - "VFRAME_WW4B2" - ], - [ - "CFG_CENTER_SW2A0_3", - "VFRAME_SW2A0" - ], - [ - "CFG_CENTER_WW4END3_3", - "VFRAME_WW4END3" - ], - [ - "CFG_CENTER_NW2A0_3", - "VFRAME_NW2A0" - ], - [ - "CFG_CENTER_EE4B3_3", - "VFRAME_EE4B3" - ], - [ - "CFG_CENTER_NE2A3_3", - "VFRAME_NE2A3" - ], - [ - "CFG_CENTER_WW4B3_3", - "VFRAME_WW4B3" - ], - [ - "CFG_CENTER_FAN2_3", - "VFRAME_FAN2" - ], - [ - "CFG_CENTER_LH1_3", - "VFRAME_LH1" - ], - [ - "CFG_CENTER_IMUX33_3", - "VFRAME_IMUX33" - ], - [ - "CFG_CENTER_SE4C2_3", - "VFRAME_SE4C2" - ], - [ - "CFG_CENTER_EE2BEG2_3", - "VFRAME_EE2BEG2" - ], - [ - "CFG_CENTER_WW4END1_3", - "VFRAME_WW4END1" - ], - [ - "CFG_CENTER_NW4END3_3", - "VFRAME_NW4END3" - ], - [ - "CFG_CENTER_EE4A3_3", - "VFRAME_EE4A3" - ], - [ - "CFG_CENTER_ER1BEG0_3", - "VFRAME_ER1BEG0" - ], - [ - "CFG_CENTER_IMUX19_3", - "VFRAME_IMUX19" - ], - [ - "CFG_CENTER_LH2_3", - "VFRAME_LH2" - ], - [ - "CFG_CENTER_EE2BEG1_3", - "VFRAME_EE2BEG1" - ], - [ - "CFG_CENTER_NW4END1_3", - "VFRAME_NW4END1" - ], - [ - "CFG_CENTER_WR1END2_3", - "VFRAME_WR1END2" - ], - [ - "CFG_CENTER_EE4BEG0_3", - "VFRAME_EE4BEG0" - ], - [ - "CFG_CENTER_LH12_3", - "VFRAME_LH12" - ], - [ - "CFG_CENTER_IMUX27_3", - "VFRAME_IMUX27" - ], - [ - "CFG_CENTER_IMUX5_3", - "VFRAME_IMUX5" - ], - [ - "CFG_CENTER_WW4C1_3", - "VFRAME_WW4C1" - ], - [ - "CFG_CENTER_WR1END3_3", - "VFRAME_WR1END3" - ], - [ - "CFG_CENTER_WL1END2_3", - "VFRAME_WL1END2" - ], - [ - "CFG_CENTER_WW2END1_3", - "VFRAME_WW2END1" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B21_3", - "VFRAME_LOGIC_OUTS_B21" - ], - [ - "CFG_CENTER_NE4C2_3", - "VFRAME_NE4C2" - ], - [ - "CFG_CENTER_SW4END2_3", - "VFRAME_SW4END2" - ], - [ - "CFG_CENTER_EE2A0_3", - "VFRAME_EE2A0" - ], - [ - "CFG_CENTER_EE4BEG2_3", - "VFRAME_EE4BEG2" - ], - [ - "CFG_CENTER_IMUX41_3", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_CLK0_3", - "VFRAME_CLK0" - ], - [ - "CFG_CENTER_EE2A1_3", - "VFRAME_EE2A1" - ], - [ - "CFG_CENTER_SW2A1_3", - "VFRAME_SW2A1" - ], - [ - "CFG_CENTER_IMUX20_3", - "VFRAME_IMUX20" - ], - [ - "CFG_CENTER_LH9_3", - "VFRAME_LH9" - ], - [ - "CFG_CENTER_BYP7_3", - "VFRAME_BYP7" - ], - [ - "CFG_CENTER_SW4A2_3", - "VFRAME_SW4A2" - ], - [ - "CFG_CENTER_LH8_3", - "VFRAME_LH8" - ], - [ - "CFG_CENTER_IMUX11_3", - "VFRAME_IMUX11" - ], - [ - "CFG_CENTER_EE4A2_3", - "VFRAME_EE4A2" - ], - [ - "CFG_CENTER_WW4C0_3", - "VFRAME_WW4C0" - ], - [ - "CFG_CENTER_IMUX44_3", - "VFRAME_IMUX44" - ], - [ - "CFG_CENTER_WW2END2_3", - "VFRAME_WW2END2" - ], - [ - "CFG_CENTER_EE4A1_3", - "VFRAME_EE4A1" - ], - [ - "CFG_CENTER_ER1BEG2_3", - "VFRAME_ER1BEG2" - ], - [ - "CFG_CENTER_LH10_3", - "VFRAME_LH10" - ], - [ - "CFG_CENTER_NE2A1_3", - "VFRAME_NE2A1" - ], - [ - "CFG_CENTER_SW4END1_3", - "VFRAME_SW4END1" - ], - [ - "CFG_CENTER_IMUX28_3", - "VFRAME_IMUX28" - ], - [ - "CFG_CENTER_SE2A2_3", - "VFRAME_SE2A2" - ], - [ - "CFG_CENTER_EL1BEG1_3", - "VFRAME_EL1BEG1" - ], - [ - "CFG_CENTER_WW2END3_3", - "VFRAME_WW2END3" - ], - [ - "CFG_CENTER_CLK1_3", - "VFRAME_CLK1" - ], - [ - "CFG_CENTER_IMUX26_3", - "VFRAME_IMUX26" - ], - [ - "CFG_CENTER_IMUX4_3", - "VFRAME_IMUX4" - ], - [ - "CFG_CENTER_WW2END0_3", - "VFRAME_WW2END0" - ], - [ - "CFG_CENTER_EE2A2_3", - "VFRAME_EE2A2" - ], - [ - "CFG_CENTER_CTRL1_3", - "VFRAME_CTRL1" - ], - [ - "CFG_CENTER_IMUX47_3", - "VFRAME_IMUX47" - ], - [ - "CFG_CENTER_FAN3_3", - "VFRAME_FAN3" - ], - [ - "CFG_CENTER_BYP3_3", - "VFRAME_BYP3" - ], - [ - "CFG_CENTER_SW2A2_3", - "VFRAME_SW2A2" - ], - [ - "CFG_CENTER_WW2A2_3", - "VFRAME_WW2A2" - ], - [ - "CFG_CENTER_FAN0_3", - "VFRAME_FAN0" - ], - [ - "CFG_CENTER_SE4C3_3", - "VFRAME_SE4C3" - ], - [ - "CFG_CENTER_EE4BEG1_3", - "VFRAME_EE4BEG1" - ], - [ - "CFG_CENTER_BYP6_3", - "VFRAME_BYP6" - ], - [ - "CFG_CENTER_FAN6_3", - "VFRAME_FAN6" - ], - [ - "CFG_CENTER_SW2A3_3", - "VFRAME_SW2A3" - ], - [ - "CFG_CENTER_EE4B1_3", - "VFRAME_EE4B1" - ], - [ - "CFG_CENTER_IMUX21_3", - "VFRAME_IMUX21" - ], - [ - "CFG_CENTER_NE4BEG2_3", - "VFRAME_NE4BEG2" - ], - [ - "CFG_CENTER_SE4BEG2_3", - "VFRAME_SE4BEG2" - ], - [ - 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"WW4BEG0" - ], - [ - "CLBLL_LOGIC_OUTS19", - "LOGIC_OUTS_L19" - ], - [ - "CLBLL_IMUX16", - "IMUX_L16" - ], - [ - "CLBLL_IMUX15", - "IMUX_L15" - ], - [ - "CLBLL_IMUX11", - "IMUX_L11" - ], - [ - "CLBLL_BYP7", - "BYP_L7" - ], - [ - "CLBLL_ER1BEG0", - "ER1END0" - ], - [ - "CLBLL_EE4BEG0", - "EE4A0" - ], - [ - "CLBLL_LOGIC_OUTS7", - "LOGIC_OUTS_L7" - ], - [ - "CLBLL_EE2A2", - "EE2END2" - ], - [ - "CLBLL_IMUX42", - "IMUX_L42" - ], - [ - "CLBLL_WW2A2", - "WW2BEG2" - ], - [ - "CLBLL_LOGIC_OUTS22", - "LOGIC_OUTS_L22" - ], - [ - "CLBLL_BYP1", - "BYP_L1" - ], - [ - "CLBLL_WW4A1", - "WW4BEG1" - ], - [ - "CLBLL_CLK1", - "CLK_L1" - ], - [ - "CLBLL_WR1END3", - "WR1BEG3" - ], - [ - "CLBLL_LOGIC_OUTS5", - "LOGIC_OUTS_L5" - ], - [ - "CLBLL_IMUX34", - "IMUX_L34" - ], - [ - "CLBLL_IMUX33", - "IMUX_L33" - ], - [ - "CLBLL_WW4B1", - "WW4A1" - ], - [ - "CLBLL_NE4BEG2", - "NE6A2" - ], - [ - "CLBLL_BYP6", - "BYP_L6" - ], - [ - "CLBLL_LOGIC_OUTS18", - "LOGIC_OUTS_L18" - ], - [ - "CLBLL_WL1END3", - "WL1BEG3" - ], - [ - "CLBLL_ER1BEG2", - "ER1END2" - ], - [ - "CLBLL_WW4END0", - "WW4C0" - ], - [ - "CLBLL_NW4A1", - "NW6BEG1" - ], - [ - "CLBLL_FAN0", - "FAN_L0" - ], - [ - "CLBLL_EE4C2", - "EE4END2" - ], - [ - "CLBLL_IMUX24", - "IMUX_L24" - ], - [ - "CLBLL_FAN2", - "FAN_L2" - ], - [ - "CLBLL_WW4B0", - "WW4A0" - ], - [ - "CLBLL_LOGIC_OUTS21", - "LOGIC_OUTS_L21" - ], - [ - "CLBLL_LH2", - "LH1" - ], - [ - "CLBLL_IMUX6", - "IMUX_L6" - ], - [ - "CLBLL_BYP2", - "BYP_L2" - ], - [ - "CLBLL_IMUX5", - "IMUX_L5" - ], - [ - "CLBLL_LOGIC_OUTS3", - "LOGIC_OUTS_L3" - ], - [ - "CLBLL_SE2A2", - "SE2END2" ], [ - "CLBLL_IMUX12", - "IMUX_L12" + "IOB_T0", + "RIOI_T0" ], [ - "CLBLL_SW4A1", - "SW6BEG1" + "IOB_T1", + "RIOI_T1" ], [ - "CLBLL_WW4C0", - "WW4B0" + "RIOB_MONITOR_N", + "IOI_MONITOR_N" ], [ - "CLBLL_LOGIC_OUTS11", - "LOGIC_OUTS_L11" + "RIOB_MONITOR_P", + "IOI_MONITOR_P" ] ] }, @@ -102949,7561 +473221,85 @@ 0 ], "tile_types": [ - "CLBLL_L", - "CLBLM_R" + "RIOB18", + "RIOI_TBYTESRC" ], "wire_pairs": [ [ - "CLBLL_LH3", - "CLBLM_LH3" + "IOB_DCI_T_TERM0", + "RIOI_DCI_T_TERM0" ], [ - "CLBLL_EE4C3", - "CLBLM_EE4C3" + "IOB_DCI_T_TERM1", + "RIOI_DCI_T_TERM1" ], [ - "CLBLL_WW2A1", - "CLBLM_WW2A1" + "IOB_DIFF_TERM_INT_EN", + "RIOI_DIFF_TERM_INT_EN" ], [ - "CLBLL_WW4C2", - "CLBLM_WW4C2" + "IOB_IBUF0", + "RIOI_IBUF0" ], [ - "CLBLL_SW4END2", - "CLBLM_SW4END2" + "IOB_IBUF1", + "RIOI_IBUF1" ], [ - "CLBLL_SE4BEG3", - "CLBLM_SE4BEG3" + "IOB_IBUF_DISABLE0", + "RIOI_IBUF_DISABLE0" ], [ - "CLBLL_EE2BEG1", - "CLBLM_EE2BEG1" + "IOB_IBUF_DISABLE1", + "RIOI_IBUF_DISABLE1" ], [ - "CLBLL_WW4END2", - "CLBLM_WW4END2" + "IOB_KEEPER_INT_EN_0", + "RIOI_KEEPER_INT_EN_0" ], [ - "CLBLL_EL1BEG3", - "CLBLM_EL1BEG3" + "IOB_KEEPER_INT_EN_1", + "RIOI_KEEPER_INT_EN_1" ], [ - "CLBLL_WW4B2", - "CLBLM_WW4B2" + "IOB_O0", + "RIOI_O0" ], [ - "CLBLL_EE2A0", - "CLBLM_EE2A0" + "IOB_O1", + "RIOI_O1" ], [ - "CLBLL_ER1BEG1", - "CLBLM_ER1BEG1" + "IOB_PD_INT_EN_0", + "RIOI_PD_INT_EN_0" ], [ - "CLBLL_SW4END1", - "CLBLM_SW4END1" + "IOB_PD_INT_EN_1", + "RIOI_PD_INT_EN_1" ], [ - "CLBLL_NW4END1", - "CLBLM_NW4END1" + "IOB_PU_INT_EN_0", + "RIOI_PU_INT_EN_0" ], [ - "CLBLL_SW4A1", - "CLBLM_SW4A1" + "IOB_PU_INT_EN_1", + "RIOI_PU_INT_EN_1" ], [ - "CLBLL_NE4BEG2", - "CLBLM_NE4BEG2" + "IOB_T0", + "RIOI_T0" ], [ - "CLBLL_EE4C0", - "CLBLM_EE4C0" + "IOB_T1", + "RIOI_T1" ], [ - "CLBLL_LH5", - "CLBLM_LH5" + "RIOB_MONITOR_N", + "IOI_MONITOR_N" ], [ - "CLBLL_LH4", - "CLBLM_LH4" - ], - [ - "CLBLL_NW4A0", - "CLBLM_NW4A0" - ], - [ - "CLBLL_NW4A2", - "CLBLM_NW4A2" - ], - [ - "CLBLL_WL1END2", - "CLBLM_WL1END2" - ], - [ - "CLBLL_SE4C3", - "CLBLM_SE4C3" - ], - [ - "CLBLL_SW4END0", - "CLBLM_SW4END0" - ], - [ - "CLBLL_EL1BEG2", - "CLBLM_EL1BEG2" - ], - [ - "CLBLL_SE4C2", - "CLBLM_SE4C2" - ], - [ - "CLBLL_EE4A1", - "CLBLM_EE4A1" - ], - [ - "CLBLL_WW4C0", - "CLBLM_WW4C0" - ], - [ - "CLBLL_NW2A1", - "CLBLM_NW2A1" - ], - [ - "CLBLL_SE4BEG0", - "CLBLM_SE4BEG0" - ], - [ - "CLBLL_NW4END2", - "CLBLM_NW4END2" - ], - [ - "CLBLL_WW2END0", - "CLBLM_WW2END0" - ], - [ - "CLBLL_NE4BEG0", - "CLBLM_NE4BEG0" - ], - [ - "CLBLL_SW4A3", - "CLBLM_SW4A3" - ], - [ - "CLBLL_WW4A2", - "CLBLM_WW4A2" - ], - [ - "CLBLL_NE2A1", - "CLBLM_NE2A1" - ], - [ - "CLBLL_SE2A0", - "CLBLM_SE2A0" - ], - [ - "CLBLL_ER1BEG0", - "CLBLM_ER1BEG0" - ], - [ - "CLBLL_EE2BEG3", - "CLBLM_EE2BEG3" - ], - [ - "CLBLL_SW2A1", - "CLBLM_SW2A1" - ], - [ - "CLBLL_LH9", - "CLBLM_LH9" - ], - [ - "CLBLL_EE2A2", - "CLBLM_EE2A2" - ], - [ - "CLBLL_SW4A2", - "CLBLM_SW4A2" - ], - [ - "CLBLL_SE4C0", - "CLBLM_SE4C0" - ], - [ - "CLBLL_WR1END0", - "CLBLM_WR1END0" - ], - [ - "CLBLL_SW2A3", - "CLBLM_SW2A3" - ], - [ - "CLBLL_LH11", - "CLBLM_LH11" - ], - [ - "CLBLL_NW2A0", - "CLBLM_NW2A0" - ], - [ - "CLBLL_EE4B3", - "CLBLM_EE4B3" - ], - [ - "CLBLL_WL1END0", - "CLBLM_WL1END0" - ], - [ - "CLBLL_SE4BEG2", - "CLBLM_SE4BEG2" - ], - [ - "CLBLL_SW4A0", - "CLBLM_SW4A0" - ], - [ - "CLBLL_EE4B1", - "CLBLM_EE4B1" - ], - [ - "CLBLL_WW4END0", - "CLBLM_WW4END0" - ], - [ - "CLBLL_EE4BEG0", - "CLBLM_EE4BEG0" - ], - [ - "CLBLL_WW2END2", - "CLBLM_WW2END2" - ], - [ - "CLBLL_EE4A2", - "CLBLM_EE4A2" - ], - [ - "CLBLL_WW4END1", - "CLBLM_WW4END1" - ], - [ - "CLBLL_WL1END1", - "CLBLM_WL1END1" - ], - [ - "CLBLL_WW4B1", - "CLBLM_WW4B1" - ], - [ - "CLBLL_MONITOR_P", - "CLBLM_MONITOR_P" - ], - [ - "CLBLL_WW2A3", - "CLBLM_WW2A3" - ], - [ - "CLBLL_EE2BEG0", - "CLBLM_EE2BEG0" - ], - [ - "CLBLL_WR1END2", - "CLBLM_WR1END2" - ], - [ - "CLBLL_WR1END1", - "CLBLM_WR1END1" - ], - [ - "CLBLL_NE2A2", - "CLBLM_NE2A2" - ], - [ - "CLBLL_NW4A3", - "CLBLM_NW4A3" - ], - [ - "CLBLL_WW2END3", - "CLBLM_WW2END3" - ], - [ - "CLBLL_WW2A0", - "CLBLM_WW2A0" - ], - [ - "CLBLL_EE4BEG2", - "CLBLM_EE4BEG2" - ], - [ - "CLBLL_WW4A1", - "CLBLM_WW4A1" - ], - [ - "CLBLL_SE2A2", - "CLBLM_SE2A2" - ], - [ - "CLBLL_SE4BEG1", - "CLBLM_SE4BEG1" - ], - [ - "CLBLL_NW4END3", - "CLBLM_NW4END3" - ], - [ - "CLBLL_EE2A3", - "CLBLM_EE2A3" - ], - [ - "CLBLL_NE4C1", - "CLBLM_NE4C1" - ], - [ - "CLBLL_WR1END3", - "CLBLM_WR1END3" - ], - [ - "CLBLL_LH7", - "CLBLM_LH7" - ], - [ - "CLBLL_EE4BEG3", - "CLBLM_EE4BEG3" - ], - [ - "CLBLL_LH12", - "CLBLM_LH12" - ], - [ - "CLBLL_WW4END3", - "CLBLM_WW4END3" - ], - [ - "CLBLL_NE4BEG1", - "CLBLM_NE4BEG1" - ], - [ - "CLBLL_WW4C1", - "CLBLM_WW4C1" - ], - [ - "CLBLL_NE4C3", - "CLBLM_NE4C3" - ], - [ - "CLBLL_EE2A1", - "CLBLM_EE2A1" - ], - [ - "CLBLL_NW2A3", - "CLBLM_NW2A3" - ], - [ - "CLBLL_EL1BEG1", - "CLBLM_EL1BEG1" - ], - [ - "CLBLL_SW2A2", - "CLBLM_SW2A2" - ], - [ - "CLBLL_SE2A3", - "CLBLM_SE2A3" - ], - [ - "CLBLL_EE4BEG1", - "CLBLM_EE4BEG1" - ], - [ - "CLBLL_WW2A2", - "CLBLM_WW2A2" - ], - [ - "CLBLL_SW4END3", - "CLBLM_SW4END3" - ], - [ - "CLBLL_NW2A2", - "CLBLM_NW2A2" - ], - [ - "CLBLL_EE2BEG2", - "CLBLM_EE2BEG2" - ], - [ - "CLBLL_NE4C2", - "CLBLM_NE4C2" - ], - [ - "CLBLL_WW4A3", - "CLBLM_WW4A3" - ], - [ - "CLBLL_EE4B0", - "CLBLM_EE4B0" - ], - [ - "CLBLL_LH10", - "CLBLM_LH10" - ], - [ - "CLBLL_WW4B0", - "CLBLM_WW4B0" - ], - [ - "CLBLL_SE2A1", - "CLBLM_SE2A1" - ], - [ - "CLBLL_NW4END0", - "CLBLM_NW4END0" - ], - [ - "CLBLL_MONITOR_N", - "CLBLM_MONITOR_N" - ], - [ - "CLBLL_SW2A0", - "CLBLM_SW2A0" - ], - [ - "CLBLL_WW2END1", - "CLBLM_WW2END1" - ], - [ - "CLBLL_NE4BEG3", - "CLBLM_NE4BEG3" - ], - [ - "CLBLL_LH6", - "CLBLM_LH6" - ], - [ - "CLBLL_NE2A0", - "CLBLM_NE2A0" - ], - [ - "CLBLL_ER1BEG3", - "CLBLM_ER1BEG3" - ], - [ - "CLBLL_SE4C1", - "CLBLM_SE4C1" - ], - [ - "CLBLL_EE4A3", - "CLBLM_EE4A3" - ], - [ - "CLBLL_WW4B3", - "CLBLM_WW4B3" - ], - [ - "CLBLL_NE2A3", - "CLBLM_NE2A3" - ], - [ - "CLBLL_EE4C1", - "CLBLM_EE4C1" - ], - [ - "CLBLL_EE4C2", - "CLBLM_EE4C2" - ], - [ - "CLBLL_WW4A0", - "CLBLM_WW4A0" - ], - [ - "CLBLL_ER1BEG2", - "CLBLM_ER1BEG2" - ], - [ - "CLBLL_LH8", - "CLBLM_LH8" - ], - [ - "CLBLL_EE4A0", - "CLBLM_EE4A0" - ], - [ - "CLBLL_EE4B2", - "CLBLM_EE4B2" - ], - [ - "CLBLL_LH2", - "CLBLM_LH2" - ], - [ - "CLBLL_EL1BEG0", - "CLBLM_EL1BEG0" - ], - [ - "CLBLL_LH1", - "CLBLM_LH1" - ], - [ - "CLBLL_NE4C0", - "CLBLM_NE4C0" - ], - [ - "CLBLL_WL1END3", - "CLBLM_WL1END3" - ], - [ - "CLBLL_WW4C3", - "CLBLM_WW4C3" - ], - [ - "CLBLL_NW4A1", - "CLBLM_NW4A1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -1 - ], - "tile_types": [ - "DSP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "DSP_LOGIC_OUTS_B11_1", - "INT_INTERFACE_LOGIC_OUTS_B11" - ], - [ - "DSP_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "DSP_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "DSP_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "DSP_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "DSP_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "DSP_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "DSP_LOGIC_OUTS_B4_1", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "DSP_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "DSP_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "DSP_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "DSP_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "DSP_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "DSP_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "DSP_MONITOR_P_1", - "INT_INTERFACE_MONITOR_P" - ], - [ - "DSP_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "DSP_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "DSP_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "DSP_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "DSP_EE4C2_1", - "INT_INTERFACE_EE4C2" - ], - [ - "DSP_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "DSP_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "DSP_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "DSP_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "DSP_LOGIC_OUTS_B10_1", - "INT_INTERFACE_LOGIC_OUTS_B10" - ], - [ - "DSP_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "DSP_LOGIC_OUTS_B20_1", - "INT_INTERFACE_LOGIC_OUTS_B20" - ], - [ - "DSP_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "DSP_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "DSP_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "DSP_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "DSP_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "DSP_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "DSP_MONITOR_N_1", - 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"IOI_PHASER_TO_IO_ICLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" - ], - [ - "IOI_BYP6_1", - "TERM_INT_BYP6" - ], - [ - "IOI_LOGIC_OUTS6_1", - "TERM_INT_LOGIC_OUTS_L_B6" - ], - [ - "IOI_IMUX32_1", - "TERM_INT_IMUX32" - ], - [ - "IOI_LOGIC_OUTS14_1", - "TERM_INT_LOGIC_OUTS_L_B14" - ], - [ - "IOI_IMUX11_1", - "TERM_INT_IMUX11" - ], - [ - "IOI_IMUX7_1", - "TERM_INT_IMUX7" - ], - [ - "IOI_FAN1_1", - "TERM_INT_FAN1" - ], - [ - "IOI_LOGIC_OUTS18_1", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "IOI_IMUX19_1", - "TERM_INT_IMUX19" - ], - [ - "IOI_IMUX0_1", - "TERM_INT_IMUX0" - ], - [ - "IOI_IMUX39_1", - "TERM_INT_IMUX39" - ], - [ - "IOI_IMUX41_1", - "TERM_INT_IMUX41" - ], - [ - "IOI_IMUX9_1", - "TERM_INT_IMUX9" - ], - [ - "IOI_PHASER_TO_IO_OCLK_0", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_LOGIC_OUTS5_1", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_LOGIC_OUTS12_1", - "TERM_INT_LOGIC_OUTS_L_B12" - ], - [ - "IOI_IMUX43_1", - "TERM_INT_IMUX43" - ], - [ - "IOI_FAN7_1", - "TERM_INT_FAN7" - ], - [ - "IOI_IMUX1_1", - "TERM_INT_IMUX1" - ], - [ - "IOI_IMUX47_1", - "TERM_INT_IMUX47" - ], - [ - "IOI_IMUX22_1", - "TERM_INT_IMUX22" - ], - [ - "IOI_CTRL1_1", - "TERM_INT_CTRL1" - ], - [ - "IOI_PHASER_TO_IO_OCLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "IOI_IMUX42_1", - "TERM_INT_IMUX42" - ], - [ - "IOI_IMUX14_1", - "TERM_INT_IMUX14" - ], - [ - "IOI_FAN0_1", - "TERM_INT_FAN0" - ], - [ - "IOI_IMUX35_1", - "TERM_INT_IMUX35" - ], - [ - "IOI_IMUX6_1", - "TERM_INT_IMUX6" - ], - [ - "IOI_IMUX20_1", - "TERM_INT_IMUX20" - ], - [ - "IOI_IMUX3_1", - "TERM_INT_IMUX3" - ], - [ - "IOI_PHASER_TO_IO_ICLK_0", - "L_TERM_INT_PHASER_TO_IO_ICLK" - ], - [ - "IOI_IMUX25_1", - "TERM_INT_IMUX25" - ], - [ - "IOI_CTRL0_1", - "TERM_INT_CTRL0" - ], - [ - "IOI_BYP4_1", - "TERM_INT_BYP4" - ], - [ - "IOI_IMUX30_1", - "TERM_INT_IMUX30" - ], - [ - "IOI_LOGIC_OUTS23_1", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "IOI_BYP5_1", - "TERM_INT_BYP5" - ], - [ - "IOI_CLK1_1", - "TERM_INT_CLK1" - ], - [ - "IOI_IMUX15_1", - "TERM_INT_IMUX15" - ], - [ - "IOI_IMUX13_1", - "TERM_INT_IMUX13" - ], - [ - "IOI_IMUX16_1", - "TERM_INT_IMUX16" - ], - [ - "IOI_IMUX33_1", - "TERM_INT_IMUX33" - ], - [ - "IOI_IMUX29_1", - "TERM_INT_IMUX29" - ], - [ - "IOI_LOGIC_OUTS17_1", - "TERM_INT_LOGIC_OUTS_L_B17" - ], - [ - "IOI_BYP1_1", - "TERM_INT_BYP1" - ], - [ - "IOI_LOGIC_OUTS3_1", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_BYP0_1", - "TERM_INT_BYP0" - ], - [ - "IOI_IMUX8_1", - "TERM_INT_IMUX8" - ], - [ - "IOI_LOGIC_OUTS1_1", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_IMUX44_1", - "TERM_INT_IMUX44" - ], - [ - "IOI_LOGIC_OUTS10_1", - "TERM_INT_LOGIC_OUTS_L_B10" - ] - ] - }, - { - "grid_deltas": [ - 1, - 2 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_LH2_2", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_LH3_2", - "VBRK_LH3" - ], - [ - "CLK_HROW_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_LH4_2", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_LH5_2", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_LH7_2", - "VBRK_LH7" - ], - [ - "CLK_HROW_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_LH9_2", - "VBRK_LH9" - ], - [ - "CLK_HROW_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH1_2", - "VBRK_LH1" - ], - [ - "CLK_HROW_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_LH10_2", - "VBRK_LH10" - ], - [ - "CLK_HROW_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH6_2", - "VBRK_LH6" - ], - [ - "CLK_HROW_LH8_2", - "VBRK_LH8" - ], - [ - "CLK_HROW_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH11_2", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_LH12_2", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_SW4END2_2", - "VBRK_SW4END2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 2 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WW4A1_6", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_EE4B1_6", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_NE4C0_6", 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"DSP_NW4END2_4", - "INT_INTERFACE_NW4END2" - ], - [ - "DSP_SE4BEG0_4", - "INT_INTERFACE_SE4BEG0" - ], - [ - "DSP_NE4C1_4", - "INT_INTERFACE_NE4C1" - ], - [ - "DSP_EE4A3_4", - "INT_INTERFACE_EE4A3" - ], - [ - "DSP_IMUX34_4", - "INT_INTERFACE_IMUX34" - ], - [ - "DSP_SE4C3_4", - "INT_INTERFACE_SE4C3" - ], - [ - "DSP_IMUX3_4", - "INT_INTERFACE_IMUX3" - ], - [ - "DSP_WW4C2_4", - "INT_INTERFACE_WW4C2" - ], - [ - "DSP_IMUX29_4", - "INT_INTERFACE_IMUX29" - ], - [ - "DSP_SE4C2_4", - "INT_INTERFACE_SE4C2" - ], - [ - "DSP_LH2_4", - "INT_INTERFACE_LH2" - ], - [ - "DSP_IMUX42_4", - "INT_INTERFACE_IMUX42" - ], - [ - "DSP_ER1BEG2_4", - "INT_INTERFACE_ER1BEG2" - ], - [ - "DSP_WW4END0_4", - "INT_INTERFACE_WW4END0" - ], - [ - "DSP_NW4END3_4", - "INT_INTERFACE_NW4END3" - ], - [ - "DSP_FAN6_4", - "INT_INTERFACE_FAN6" - ], - [ - "DSP_IMUX2_4", - "INT_INTERFACE_IMUX2" - ], - [ - "DSP_WW4C0_4", - "INT_INTERFACE_WW4C0" - ], - [ - "DSP_WW4B2_4", - "INT_INTERFACE_WW4B2" - ], - [ - "DSP_NE4C0_4", - "INT_INTERFACE_NE4C0" - ], - [ - "DSP_IMUX12_4", - "INT_INTERFACE_IMUX12" - ], - [ - "DSP_EE4BEG3_4", - "INT_INTERFACE_EE4BEG3" - ], - [ - "DSP_LOGIC_OUTS_B9_4", - "INT_INTERFACE_LOGIC_OUTS_L_B9" - ], - [ - "DSP_BYP3_4", - "INT_INTERFACE_BYP3" - ], - [ - "DSP_SE4BEG2_4", - "INT_INTERFACE_SE4BEG2" - ], - [ - "DSP_IMUX41_4", - "INT_INTERFACE_IMUX41" - ], - [ - "DSP_LH6_4", - "INT_INTERFACE_LH6" - ], - [ - "DSP_LOGIC_OUTS_B3_4", - "INT_INTERFACE_LOGIC_OUTS_L_B3" - ], - [ - "DSP_EE4B1_4", - "INT_INTERFACE_EE4B1" - ], - [ - "DSP_LOGIC_OUTS_B18_4", - "INT_INTERFACE_LOGIC_OUTS_L_B18" - ], - [ - "DSP_IMUX9_4", - "INT_INTERFACE_IMUX9" - ], - [ - "DSP_IMUX13_4", - "INT_INTERFACE_IMUX13" - ], - [ - "DSP_IMUX19_4", - "INT_INTERFACE_IMUX19" - ], - [ - "DSP_IMUX17_4", - "INT_INTERFACE_IMUX17" - ], - [ - "DSP_IMUX22_4", - "INT_INTERFACE_IMUX22" - ], - [ - "DSP_WW4A2_4", - "INT_INTERFACE_WW4A2" - ], - [ - "DSP_WR1END1_4", - "INT_INTERFACE_WR1END1" - ], - [ - "DSP_BYP6_4", - "INT_INTERFACE_BYP6" - ], - [ - "DSP_LOGIC_OUTS_B19_4", - "INT_INTERFACE_LOGIC_OUTS_L_B19" - ], - [ - "DSP_IMUX36_4", - "INT_INTERFACE_IMUX36" - ], - [ - "DSP_IMUX5_4", - "INT_INTERFACE_IMUX5" - ], - [ - "DSP_SW4A0_4", - "INT_INTERFACE_SW4A0" - ], - [ - "DSP_NE2A2_4", - "INT_INTERFACE_NE2A2" - ], - [ - "DSP_LH7_4", - "INT_INTERFACE_LH7" - ], - [ - "DSP_EE4A2_4", - "INT_INTERFACE_EE4A2" - ], - [ - "DSP_IMUX8_4", - "INT_INTERFACE_IMUX8" - ], - [ - "DSP_LOGIC_OUTS_B22_4", - "INT_INTERFACE_LOGIC_OUTS_L_B22" - ], - [ - "DSP_IMUX1_4", - "INT_INTERFACE_IMUX1" - ], - [ - "DSP_LH4_4", - "INT_INTERFACE_LH4" - ], - [ - "DSP_SW2A0_4", - "INT_INTERFACE_SW2A0" - ], - [ - "DSP_LH11_4", - "INT_INTERFACE_LH11" - ], - [ - "DSP_LOGIC_OUTS_B23_4", - "INT_INTERFACE_LOGIC_OUTS_L_B23" - ], - [ - "DSP_EE4C0_4", - "INT_INTERFACE_EE4C0" - ], - [ - "DSP_BYP5_4", - "INT_INTERFACE_BYP5" - ], - [ - "DSP_WL1END0_4", - "INT_INTERFACE_WL1END0" - ], - [ - "DSP_NE4BEG3_4", - "INT_INTERFACE_NE4BEG3" - ], - [ - "DSP_SW4END3_4", - "INT_INTERFACE_SW4END3" - ], - [ - "DSP_NE4C2_4", - "INT_INTERFACE_NE4C2" - ], - [ - "DSP_EL1BEG2_4", - "INT_INTERFACE_EL1BEG2" - ], - [ - "DSP_LH5_4", - "INT_INTERFACE_LH5" - ], - [ - "DSP_EE4A0_4", - "INT_INTERFACE_EE4A0" - ], - [ - "DSP_FAN5_4", - "INT_INTERFACE_FAN5" - ], - [ - "DSP_WW4B3_4", - "INT_INTERFACE_WW4B3" - ], - [ - "DSP_NW4END1_4", - "INT_INTERFACE_NW4END1" - ], - [ - "DSP_EE4A1_4", - "INT_INTERFACE_EE4A1" - ], - [ - "DSP_EE2A3_4", - "INT_INTERFACE_EE2A3" - ], - [ - "DSP_ER1BEG1_4", - "INT_INTERFACE_ER1BEG1" - ], - [ - "DSP_FAN1_4", - "INT_INTERFACE_FAN1" - ], - [ - "DSP_EL1BEG3_4", - "INT_INTERFACE_EL1BEG3" - ], - [ - "DSP_NE2A3_4", - "INT_INTERFACE_NE2A3" - ], - [ - "DSP_IMUX33_4", - "INT_INTERFACE_IMUX33" - ], - [ - "DSP_WW4A0_4", - "INT_INTERFACE_WW4A0" - ], - [ - "DSP_IMUX21_4", - "INT_INTERFACE_IMUX21" - ], - [ - "DSP_IMUX15_4", - "INT_INTERFACE_IMUX15" - ], - [ - "DSP_WW4END3_4", - "INT_INTERFACE_WW4END3" - ], - [ - "DSP_FAN0_4", - "INT_INTERFACE_FAN0" - ], - [ - "DSP_ER1BEG0_4", - "INT_INTERFACE_ER1BEG0" - ], - [ - "DSP_WW4C3_4", - "INT_INTERFACE_WW4C3" - ], - [ - "DSP_SE4C1_4", - "INT_INTERFACE_SE4C1" - ], - [ - "DSP_NW2A1_4", - "INT_INTERFACE_NW2A1" - ], - [ - "DSP_EE4C3_4", - "INT_INTERFACE_EE4C3" - ], - [ - "DSP_LOGIC_OUTS_B12_4", - "INT_INTERFACE_LOGIC_OUTS_L_B12" - ], - [ - "DSP_EE4BEG2_4", - "INT_INTERFACE_EE4BEG2" - ], - [ - "DSP_WW4B0_4", - "INT_INTERFACE_WW4B0" - ], - [ - "DSP_LOGIC_OUTS_B21_4", - "INT_INTERFACE_LOGIC_OUTS_L_B21" - ], - [ - "DSP_EE2BEG3_4", - "INT_INTERFACE_EE2BEG3" - ], - [ - "DSP_WR1END3_4", - "INT_INTERFACE_WR1END3" - ], - [ - "DSP_EE4C2_4", - "INT_INTERFACE_EE4C2" - ], - [ - "DSP_SW2A1_4", - "INT_INTERFACE_SW2A1" - ], - [ - "DSP_LH1_4", - "INT_INTERFACE_LH1" - ], - [ - "DSP_WW4A1_4", - "INT_INTERFACE_WW4A1" + "RIOB_MONITOR_P", + "IOI_MONITOR_P" ] ] }, @@ -110513,7621 +473309,85 @@ 0 ], "tile_types": [ - "CLBLM_R", - "INT_R" + "RIOB18", + "RIOI_TBYTETERM" ], "wire_pairs": [ [ - "CLBLM_WW4END0", - "WW4END0" + "IOB_DCI_T_TERM0", + "RIOI_DCI_T_TERM0" ], [ - "CLBLM_IMUX45", - "IMUX45" + "IOB_DCI_T_TERM1", + "RIOI_DCI_T_TERM1" ], [ - "CLBLM_BYP0", - "BYP0" + "IOB_DIFF_TERM_INT_EN", + "RIOI_DIFF_TERM_INT_EN" ], [ - "CLBLM_SE2A0", - "SE2A0" + "IOB_IBUF0", + "RIOI_IBUF0" ], [ - "CLBLM_SE4BEG2", - "SE6BEG2" + "IOB_IBUF1", + "RIOI_IBUF1" ], [ - "CLBLM_IMUX1", - "IMUX1" + "IOB_IBUF_DISABLE0", + "RIOI_IBUF_DISABLE0" ], [ - "CLBLM_SW4END1", - "SW6END1" + "IOB_IBUF_DISABLE1", + "RIOI_IBUF_DISABLE1" ], [ - "CLBLM_IMUX26", - "IMUX26" + "IOB_KEEPER_INT_EN_0", + "RIOI_KEEPER_INT_EN_0" ], [ - "CLBLM_IMUX9", - "IMUX9" + "IOB_KEEPER_INT_EN_1", + "RIOI_KEEPER_INT_EN_1" ], [ - "CLBLM_NW4A1", - "NW6A1" + "IOB_O0", + "RIOI_O0" ], [ - "CLBLM_SE2A2", - "SE2A2" + "IOB_O1", + "RIOI_O1" ], [ - "CLBLM_WW2END3", - "WW2END3" + "IOB_PD_INT_EN_0", + "RIOI_PD_INT_EN_0" ], [ - "CLBLM_SE4C1", - "SE6E1" + "IOB_PD_INT_EN_1", + "RIOI_PD_INT_EN_1" ], [ - "CLBLM_WW2A3", - "WW2A3" + "IOB_PU_INT_EN_0", + "RIOI_PU_INT_EN_0" ], [ - "CLBLM_MONITOR_P", - "MONITOR_P" + "IOB_PU_INT_EN_1", + "RIOI_PU_INT_EN_1" ], [ - "CLBLM_IMUX11", - "IMUX11" + "IOB_T0", + "RIOI_T0" ], [ - "CLBLM_NE2A1", - "NE2A1" + "IOB_T1", + "RIOI_T1" ], [ - "CLBLM_IMUX31", - "IMUX31" + "RIOB_MONITOR_N", + "IOI_MONITOR_N" ], [ - "CLBLM_WW4C1", - "WW4C1" - ], - [ - "CLBLM_SW4A1", - "SW6A1" - ], - [ - "CLBLM_WW4B3", - "WW4B3" - ], - [ - "CLBLM_LH6", - "LH6" - ], - [ - "CLBLM_WW2A0", - "WW2A0" - ], - [ - "CLBLM_EE4A3", - "EE4A3" - ], - [ - "CLBLM_WW4END1", - "WW4END1" - ], - [ - "CLBLM_SW4END2", - "SW6END2" - ], - [ - "CLBLM_SE4BEG3", - "SE6BEG3" - ], - [ - "CLBLM_CTRL0", - "CTRL0" - ], - [ - "CLBLM_IMUX16", - "IMUX16" - ], - [ - "CLBLM_NE4C1", - "NE6E1" - ], - [ - "CLBLM_IMUX36", - "IMUX36" - ], - [ - "CLBLM_NE4BEG1", - "NE6BEG1" - ], - [ - "CLBLM_IMUX5", - "IMUX5" - ], - [ - "CLBLM_FAN1", - "FAN1" - ], - [ - "CLBLM_IMUX13", - "IMUX13" - ], - [ - "CLBLM_ER1BEG3", - "ER1BEG3" - ], - [ - "CLBLM_BYP2", - "BYP2" - ], - [ - "CLBLM_WW2END2", - "WW2END2" - ], - [ - "CLBLM_WW2END0", - "WW2END0" - ], - [ - "CLBLM_IMUX28", - "IMUX28" - ], - [ - "CLBLM_EE2A3", - "EE2A3" - ], - [ - "CLBLM_EE4C1", - "EE4C1" - ], - [ - "CLBLM_WW4END3", - "WW4END3" - ], - [ - "CLBLM_LH11", - "LH11" - ], - [ - "CLBLM_IMUX43", - "IMUX43" - ], - [ - "CLBLM_EE4BEG3", - "EE4BEG3" - ], - [ - "CLBLM_LOGIC_OUTS3", - "LOGIC_OUTS3" - ], - [ - "CLBLM_LOGIC_OUTS2", - "LOGIC_OUTS2" - ], - [ - "CLBLM_BYP6", - "BYP6" - ], - [ - "CLBLM_IMUX44", - "IMUX44" - ], - [ - "CLBLM_FAN2", - "FAN2" - ], - [ - "CLBLM_WR1END1", - "WR1END1" - ], - [ - "CLBLM_IMUX4", - "IMUX4" - ], - [ - "CLBLM_EE2A2", - "EE2A2" - ], - [ - "CLBLM_LH3", - "LH3" - ], - [ - "CLBLM_WW4A2", - "WW4A2" - ], - [ - "CLBLM_IMUX27", - "IMUX27" - ], - [ - "CLBLM_WL1END2", - "WL1END2" - ], - [ - "CLBLM_LOGIC_OUTS7", - "LOGIC_OUTS7" - ], - [ - "CLBLM_IMUX22", - "IMUX22" - ], - [ - "CLBLM_EE4C2", - "EE4C2" - ], - [ - "CLBLM_LOGIC_OUTS23", - "LOGIC_OUTS23" - ], - [ - "CLBLM_EE4BEG2", - "EE4BEG2" - ], - [ - "CLBLM_EE4BEG0", - "EE4BEG0" - ], - [ - "CLBLM_LH4", - "LH4" - ], - [ - "CLBLM_SW4A3", - "SW6A3" - ], - [ - "CLBLM_BYP4", - "BYP4" - ], - [ - "CLBLM_LOGIC_OUTS10", - "LOGIC_OUTS10" - ], - [ - "CLBLM_FAN3", - "FAN3" - ], - [ - "CLBLM_SW2A2", - "SW2END2" - ], - [ - "CLBLM_IMUX17", - "IMUX17" - ], - [ - "CLBLM_LOGIC_OUTS9", - "LOGIC_OUTS9" - ], - [ - "CLBLM_LH7", - "LH7" - ], - [ - "CLBLM_WW4B1", - "WW4B1" - ], - [ - "CLBLM_NW4A3", - "NW6A3" - ], - [ - "CLBLM_EE4B2", - "EE4B2" - ], - [ - "CLBLM_WL1END0", - "WL1END0" - ], - [ - "CLBLM_NW2A0", - "NW2END0" - ], - [ - "CLBLM_CLK1", - "CLK1" - ], - [ - "CLBLM_IMUX23", - "IMUX23" - ], - [ - "CLBLM_EE4B0", - "EE4B0" - ], - [ - "CLBLM_IMUX20", - "IMUX20" - ], - [ - "CLBLM_SW4A0", - "SW6A0" - ], - [ - "CLBLM_LOGIC_OUTS15", - "LOGIC_OUTS15" - ], - [ - "CLBLM_NE4C0", - "NE6E0" - ], - [ - "CLBLM_LOGIC_OUTS21", - "LOGIC_OUTS21" - ], - [ - "CLBLM_WW2A2", - "WW2A2" - ], - [ - "CLBLM_IMUX39", - "IMUX39" - ], - [ - "CLBLM_SE4BEG0", - "SE6BEG0" - ], - [ - "CLBLM_ER1BEG2", - "ER1BEG2" - ], - [ - "CLBLM_EE4C0", - "EE4C0" - ], - [ - "CLBLM_SW2A1", - "SW2END1" - ], - [ - "CLBLM_LH2", - "LH2" - ], - [ - "CLBLM_EE4C3", - "EE4C3" - ], - [ - "CLBLM_LOGIC_OUTS12", - "LOGIC_OUTS12" - ], - [ - "CLBLM_SW4END0", - "SW6END0" - ], - [ - "CLBLM_EE2A1", - "EE2A1" - ], - [ - "CLBLM_IMUX40", - "IMUX40" - ], - [ - "CLBLM_LH8", - "LH8" - ], - [ - "CLBLM_IMUX12", - "IMUX12" - ], - [ - "CLBLM_EE2BEG2", - "EE2BEG2" - ], - [ - "CLBLM_BYP7", - "BYP7" - ], - [ - "CLBLM_LH5", - "LH5" - ], - [ - "CLBLM_IMUX33", - "IMUX33" - ], - [ - "CLBLM_SE4C0", - "SE6E0" - ], - [ - "CLBLM_LH10", - "LH10" - ], - [ - "CLBLM_SE2A3", - "SE2A3" - ], - [ - "CLBLM_IMUX8", - "IMUX8" - ], - [ - "CLBLM_BYP3", - "BYP3" - ], - [ - "CLBLM_LOGIC_OUTS4", - "LOGIC_OUTS4" - ], - [ - "CLBLM_SE4BEG1", - "SE6BEG1" - ], - [ - "CLBLM_LOGIC_OUTS6", - "LOGIC_OUTS6" - ], - [ - "CLBLM_IMUX32", - "IMUX32" - ], - [ - "CLBLM_SW2A3", - "SW2END3" - ], - [ - "CLBLM_SW4END3", - "SW6END3" - ], - [ - "CLBLM_EL1BEG0", - "EL1BEG0" - ], - [ - "CLBLM_SE4C3", - "SE6E3" - ], - [ - "CLBLM_WW4B2", - "WW4B2" - ], - [ - "CLBLM_IMUX0", - "IMUX0" - ], - [ - "CLBLM_BYP5", - "BYP5" - ], - [ - "CLBLM_WW2A1", - "WW2A1" - ], - [ - "CLBLM_SW4A2", - "SW6A2" - ], - [ - "CLBLM_EE4B1", - "EE4B1" - ], - [ - "CLBLM_LOGIC_OUTS16", - "LOGIC_OUTS16" - ], - [ - "CLBLM_IMUX14", - "IMUX14" - ], - [ - "CLBLM_EL1BEG3", - "EL1BEG3" - ], - [ - "CLBLM_LOGIC_OUTS14", - "LOGIC_OUTS14" - ], - [ - "CLBLM_LOGIC_OUTS0", - "LOGIC_OUTS0" - ], - [ - "CLBLM_ER1BEG0", - "ER1BEG0" - ], - [ - "CLBLM_IMUX30", - "IMUX30" - ], - [ - "CLBLM_IMUX21", - "IMUX21" - ], - [ - "CLBLM_FAN5", - "FAN5" - ], - [ - "CLBLM_EE2BEG1", - "EE2BEG1" - ], - [ - "CLBLM_WW4A3", - "WW4A3" - ], - [ - "CLBLM_NW2A3", - "NW2END3" - ], - [ - "CLBLM_WW4A1", - "WW4A1" - ], - [ - "CLBLM_LOGIC_OUTS18", - "LOGIC_OUTS18" - ], - [ - "CLBLM_EE2A0", - "EE2A0" - ], - [ - "CLBLM_NW4END0", - "NW6END0" - ], - [ - "CLBLM_IMUX42", - "IMUX42" - ], - [ - "CLBLM_IMUX18", - "IMUX18" - ], - [ - "CLBLM_NE4BEG2", - "NE6BEG2" - ], - [ - "CLBLM_WW4C3", - "WW4C3" - ], - [ - "CLBLM_IMUX2", - "IMUX2" - ], - [ - "CLBLM_NW4END1", - "NW6END1" - ], - [ - "CLBLM_LOGIC_OUTS5", - "LOGIC_OUTS5" - ], - [ - "CLBLM_FAN7", - "FAN7" - ], - [ - "CLBLM_IMUX25", - "IMUX25" - ], - [ - "CLBLM_WL1END3", - "WL1END3" - ], - [ - "CLBLM_LH1", - "LH1" - ], - [ - "CLBLM_EE4A1", - "EE4A1" - ], - [ - "CLBLM_LOGIC_OUTS11", - "LOGIC_OUTS11" - ], - [ - "CLBLM_IMUX7", - "IMUX7" - ], - [ - "CLBLM_NE2A0", - "NE2A0" - ], - [ - "CLBLM_WW4C2", - "WW4C2" - ], - [ - "CLBLM_LOGIC_OUTS22", - "LOGIC_OUTS22" - ], - [ - "CLBLM_LH9", - "LH9" - ], - [ - "CLBLM_IMUX35", - "IMUX35" - ], - [ - "CLBLM_LOGIC_OUTS20", - "LOGIC_OUTS20" - ], - [ - "CLBLM_WL1END1", - "WL1END1" - ], - [ - "CLBLM_EE4A2", - "EE4A2" - ], - [ - "CLBLM_EE2BEG3", - "EE2BEG3" - ], - [ - "CLBLM_IMUX34", - "IMUX34" - ], - [ - "CLBLM_WR1END0", - "WR1END0" - ], - [ - "CLBLM_BYP1", - "BYP1" - ], - [ - "CLBLM_NE4C3", - "NE6E3" - ], - [ - "CLBLM_CLK0", - "CLK0" - ], - [ - "CLBLM_NW4A0", - "NW6A0" - ], - [ - "CLBLM_IMUX41", - "IMUX41" - ], - [ - "CLBLM_IMUX6", - "IMUX6" - ], - [ - "CLBLM_NW2A1", - "NW2END1" - ], - [ - "CLBLM_EE2BEG0", - "EE2BEG0" - ], - [ - "CLBLM_IMUX3", - "IMUX3" - ], - [ - "CLBLM_WR1END3", - "WR1END3" - ], - [ - "CLBLM_EE4BEG1", - "EE4BEG1" - ], - [ - "CLBLM_IMUX46", - "IMUX46" - ], - [ - "CLBLM_LOGIC_OUTS8", - "LOGIC_OUTS8" - ], - [ - "CLBLM_FAN6", - "FAN6" - ], - [ - "CLBLM_EL1BEG2", - "EL1BEG2" - ], - [ - "CLBLM_IMUX24", - "IMUX24" - ], - [ - "CLBLM_IMUX10", - "IMUX10" - ], - [ - "CLBLM_SE2A1", - "SE2A1" - ], - [ - "CLBLM_NE2A2", - "NE2A2" - ], - [ - "CLBLM_NE4BEG3", - "NE6BEG3" - ], - [ - "CLBLM_LOGIC_OUTS13", - "LOGIC_OUTS13" - ], - [ - "CLBLM_NW4A2", - "NW6A2" - ], - [ - "CLBLM_SW2A0", - "SW2END0" - ], - [ - "CLBLM_NW4END3", - "NW6END3" - ], - [ - "CLBLM_IMUX19", - "IMUX19" - ], - [ - "CLBLM_IMUX15", - "IMUX15" - ], - [ - "CLBLM_WW2END1", - "WW2END1" - ], - [ - "CLBLM_IMUX37", - "IMUX37" - ], - [ - "CLBLM_IMUX29", - "IMUX29" - ], - [ - "CLBLM_EE4A0", - "EE4A0" - ], - [ - "CLBLM_LOGIC_OUTS17", - "LOGIC_OUTS17" - ], - [ - "CLBLM_MONITOR_N", - "MONITOR_N" - ], - [ - "CLBLM_EL1BEG1", - "EL1BEG1" - ], - [ - "CLBLM_WW4A0", - "WW4A0" - ], - [ - "CLBLM_NE2A3", - "NE2A3" - ], - [ - "CLBLM_WW4END2", - "WW4END2" - ], - [ - "CLBLM_IMUX47", - "IMUX47" - ], - [ - "CLBLM_LOGIC_OUTS19", - "LOGIC_OUTS19" - ], - [ - "CLBLM_LOGIC_OUTS1", - "LOGIC_OUTS1" - ], - [ - "CLBLM_NW4END2", - "NW6END2" - ], - [ - "CLBLM_IMUX38", - "IMUX38" - ], - [ - "CLBLM_SE4C2", - "SE6E2" - ], - [ - "CLBLM_ER1BEG1", - "ER1BEG1" - ], - [ - "CLBLM_FAN0", - "FAN0" - ], - [ - "CLBLM_WW4C0", - "WW4C0" - ], - [ - "CLBLM_NE4BEG0", - "NE6BEG0" - ], - [ - "CLBLM_FAN4", - "FAN4" - ], - [ - "CLBLM_NE4C2", - "NE6E2" - ], - [ - "CLBLM_WR1END2", - "WR1END2" - ], - [ - "CLBLM_WW4B0", - "WW4B0" - ], - [ - "CLBLM_NW2A2", - "NW2END2" - ], - [ - "CLBLM_LH12", - "LH12" - ], - [ - "CLBLM_EE4B3", - "EE4B3" - ], - [ - "CLBLM_CTRL1", - "CTRL1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_BUFG_IMUX33_2", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_NW2A3_2", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_2", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_BUFG_IMUX9_2", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_IMUX35_2", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_LH4_2", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_BYP6_2", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_SW4A2_2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE4B1_2", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_BUFG_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WW2END2_2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_2", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_BUFG_IMUX2_2", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_EE4A0_2", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_NE4BEG2_2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_BUFG_IMUX45_2", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_WW4A0_2", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WR1END3_2", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_2", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_BYP0_2", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_BUFG_IMUX12_2", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SW4END3_2", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_BUFG_IMUX5_2", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_SE4BEG3_2", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NW2A2_2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_LH10_2", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_LH6_2", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_SW4A3_2", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_NW4A0_2", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_BYP3_2", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_BUFG_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_BUFG_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_SE4BEG2_2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_NE4C3_2", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_BUFG_IMUX42_2", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_2", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_NW4END0_2", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_CLK0_2", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WR1END2_2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_BUFG_IMUX17_2", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_NE2A1_2", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_LH9_2", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_FAN3_2", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_LH2_2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_SE2A1_2", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE2A0_2", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4B3_2", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_CTRL0_2", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_BUFG_IMUX29_2", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_BUFG_IMUX43_2", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_ER1BEG2_2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_BUFG_IMUX6_2", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_SW2A3_2", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_EE4BEG0_2", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_FAN2_2", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_LH1_2", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WR1END1_2", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_NW4A3_2", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_BYP4_2", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_BUFG_IMUX3_2", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_BUFG_IMUX7_2", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WW4B0_2", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_EE2A2_2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EL1BEG2_2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_LH11_2", - "INT_INTERFACE_LH11" - ], - [ - "CLK_BUFG_IMUX37_2", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_EE4C0_2", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_BYP5_2", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_WW2A3_2", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_WW4END2_2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_BUFG_IMUX26_2", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_BUFG_IMUX22_2", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_FAN6_2", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4C2_2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SE4BEG1_2", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NW4A1_2", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_EE2A1_2", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_WW4B2_2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_WW2A1_2", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_EE4A3_2", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_BUFG_IMUX13_2", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_NE2A3_2", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_FAN1_2", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_BUFG_IMUX0_2", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_BUFG_IMUX15_2", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SE4BEG0_2", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_IMUX30_2", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_BUFG_IMUX8_2", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX21_2", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_SE4C0_2", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW4END0_2", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WW4A3_2", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EE2BEG3_2", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_SE4C1_2", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_BUFG_IMUX46_2", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_EE4BEG2_2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW4C3_2", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW2END3_2", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW2END0_2", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_WR1END0_2", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_BUFG_IMUX18_2", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_IMUX27_2", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_IMUX23_2", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_EE2BEG0_2", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_EE4B2_2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NE4BEG0_2", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_2", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_HROW_NE4C1_2", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_NW4END2_2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EL1BEG0_2", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_2", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_BUFG_IMUX36_2", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_BUFG_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_SW2A1_2", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4BEG3_2", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_WW4C1_2", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_SW4A1_2", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_WW2A2_2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_WW4B3_2", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_LH12_2", - "INT_INTERFACE_LH12" - ], - [ - "CLK_BUFG_IMUX44_2", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_BUFG_IMUX20_2", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_EE2BEG1_2", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_2", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_HROW_NW4END1_2", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_BUFG_IMUX14_2", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_BUFG_IMUX40_2", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_WL1END0_2", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NE2A2_2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_BUFG_IMUX16_2", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4END1_2", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_CTRL1_2", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_NW4END3_2", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SE2A2_2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_BYP1_2", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_BUFG_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_FAN7_2", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_EL1BEG3_2", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_ER1BEG0_2", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_WL1END2_2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_SE2A3_2", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_EE4BEG1_2", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_BUFG_IMUX31_2", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX47_2", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_LH3_2", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_SW2A0_2", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_BYP7_2", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_BUFG_IMUX11_2", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_NE2A0_2", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_IMUX39_2", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_FAN0_2", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_2", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_WW4END3_2", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_EE4B0_2", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_EE4A2_2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE4C2_2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_EE4BEG3_2", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_WW2A0_2", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SE2A0_2", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_WW4C0_2", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_LH5_2", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_WW4A2_2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_WW2END1_2", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_BUFG_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_NW2A0_2", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_BUFG_IMUX19_2", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_FAN5_2", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_BUFG_IMUX32_2", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_FAN4_2", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_BUFG_IMUX24_2", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_SE4C2_2", - "INT_INTERFACE_SE4C2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 1 - ], - "tile_types": [ - "BRAM_INT_INTERFACE_R", - "BRAM_R" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX27", - "BRAM_IMUX27_UTURN_1" - ], - [ - "INT_INTERFACE_EE4BEG3", - "BRAM_EE4BEG3_1" - ], - [ - "INT_INTERFACE_EL1BEG1", - "BRAM_EL1BEG1_1" - ], - [ - "INT_INTERFACE_EE4A0", - "BRAM_EE4A0_1" - ], - [ - "INT_INTERFACE_WW4C2", - "BRAM_WW4C2_1" - ], - [ - "INT_INTERFACE_SW2A3", - "BRAM_SW2A3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX13", - "BRAM_IMUX13_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "BRAM_IMUX37_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "BRAM_IMUX4_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "BRAM_IMUX31_1" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_1" - ], - [ - "INT_INTERFACE_BYP5", - "BRAM_BYP5_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B13", - "BRAM_LOGIC_OUTS_B13_1" - ], - [ - "INT_INTERFACE_FAN7", - "BRAM_FAN7_1" - ], - [ - "INT_INTERFACE_WW2END1", - "BRAM_WW2END1_1" - ], - [ - "INT_INTERFACE_NE4C2", - "BRAM_NE4C2_1" - ], - [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B2", - "BRAM_LOGIC_OUTS_B2_1" - ], - [ - "INT_INTERFACE_ER1BEG2", - "BRAM_ER1BEG2_1" - ], - [ - "INT_INTERFACE_BYP2", - "BRAM_BYP2_1" - ], - [ - "INT_INTERFACE_SE4C1", - "BRAM_SE4C1_1" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_1" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_1" - ], - [ - "INT_INTERFACE_WW4B2", - "BRAM_WW4B2_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B23", - 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"CLK_HROW_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_NW4END2_0", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_WL1END2_0", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_MONITOR_N_0", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_MONITOR_P_0", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_IMUX46_0", - "INT_INTERFACE_IMUX46" - ] - ] - }, - { - "grid_deltas": [ - 1, - -3 - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH12_3", - "VBRK_LH12" - ], - [ - "CLK_HROW_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_LH8_3", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_MONITOR_N_3", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_MONITOR_P_3", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_LH1_3", - "VBRK_LH1" - ], - [ - "CLK_HROW_WW4C1_3", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH11_3", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH10_3", - "VBRK_LH10" - ], - [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_LH9_3", - "VBRK_LH9" - ], - [ - "CLK_HROW_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_SE2A2_3", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_LH6_3", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_LH7_3", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SW2A0_3", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH2_3", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW4C2_3", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_LH5_3", - "VBRK_LH5" - ], - [ - "CLK_HROW_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_LH4_3", - "VBRK_LH4" - ], - [ - "CLK_HROW_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WL1END2_3", - "VBRK_WL1END2" + "RIOB_MONITOR_P", + "IOI_MONITOR_P" ] ] }, @@ -118142,96852 +473402,56 @@ ], "wire_pairs": [ [ - "IOB_T0", - "RIOI_T0" - ], - [ - "IOB_O0", - "RIOI_O0" - ], - [ - "IOB_KEEPER_INT_EN_1", - "RIOI_KEEPER_INT_EN_1" + "IOB_DCI_T_TERM0", + "RIOI_DCI_T_TERM0" ], [ "IOB_IBUF0", "RIOI_IBUF0" ], [ - "IOB_DCI_T_TERM0", - "RIOI_DCI_T_TERM0" + "IOB_IBUF_DISABLE0", + "RIOI_IBUF_DISABLE0" + ], + [ + "IOB_KEEPER_INT_EN_1", + "RIOI_KEEPER_INT_EN_1" + ], + [ + "IOB_O0", + "RIOI_O0" ], [ "IOB_PD_INT_EN_1", "RIOI_PD_INT_EN_1" ], - [ - "IOB_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE0" - ], [ "IOB_PU_INT_EN_1", "RIOI_PU_INT_EN_1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 11 - ], - "tile_types": [ - "CFG_CENTER_MID", - "INT_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "CFG_CENTER_WW2END2_0", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_SW4END1_0", - "INT_FEEDTHRU_2_SW4END1" - ], - [ - "CFG_CENTER_LH2_0", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_LH3_0", - "INT_FEEDTHRU_2_LH3" - ], - [ - "CFG_CENTER_WR1END0_0", - "INT_FEEDTHRU_2_WR1END0" - ], - [ - "CFG_CENTER_WR1END1_0", - "INT_FEEDTHRU_2_WR1END1" - ], - [ - "CFG_CENTER_LH12_0", - "INT_FEEDTHRU_2_LH12" - ], - [ - "CFG_CENTER_EL1BEG1_0", - "INT_FEEDTHRU_2_EL1BEG1" - ], - [ - "CFG_CENTER_WW2END1_0", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_EE4C0_0", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_NE4BEG3_0", - "INT_FEEDTHRU_2_NE4BEG3" - ], - [ - "CFG_CENTER_WL1END1_0", - "INT_FEEDTHRU_2_WL1END1" - ], - [ - "CFG_CENTER_WW2A1_0", - "INT_FEEDTHRU_2_WW2A1" - ], - [ - "CFG_CENTER_NE2A2_0", - "INT_FEEDTHRU_2_NE2A2" - ], - [ - "CFG_CENTER_NE4C2_0", - "INT_FEEDTHRU_2_NE4C2" - ], - [ - "CFG_CENTER_SW4A0_0", - "INT_FEEDTHRU_2_SW4A0" - ], - [ - "CFG_CENTER_SW2A1_0", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_EL1BEG2_0", - "INT_FEEDTHRU_2_EL1BEG2" - ], - [ - "CFG_CENTER_EE4C2_0", - "INT_FEEDTHRU_2_EE4C2" - ], - [ - "CFG_CENTER_WW4END0_0", - "INT_FEEDTHRU_2_WW4END0" - ], - [ - "CFG_CENTER_NE4BEG1_0", - "INT_FEEDTHRU_2_NE4BEG1" - ], - [ - "CFG_CENTER_WW4A0_0", - "INT_FEEDTHRU_2_WW4A0" - ], - [ - "CFG_CENTER_NW2A0_0", - "INT_FEEDTHRU_2_NW2A0" - ], - [ - "CFG_CENTER_NW2A2_0", - "INT_FEEDTHRU_2_NW2A2" - ], - [ - "CFG_CENTER_WW4A3_0", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_SW2A0_0", - "INT_FEEDTHRU_2_SW2A0" - ], - [ - "CFG_CENTER_NW2A1_0", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_WW2A2_0", - "INT_FEEDTHRU_2_WW2A2" - ], - [ - "CFG_CENTER_LH8_0", - "INT_FEEDTHRU_2_LH8" - ], - [ - "CFG_CENTER_SE2A2_0", - "INT_FEEDTHRU_2_SE2A2" - ], - [ - "CFG_CENTER_NW4A2_0", - "INT_FEEDTHRU_2_NW4A2" - ], - [ - "CFG_CENTER_NE2A1_0", - "INT_FEEDTHRU_2_NE2A1" - ], - [ - "CFG_CENTER_EE4B0_0", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_NE4BEG0_0", - "INT_FEEDTHRU_2_NE4BEG0" - ], - [ - "CFG_CENTER_SE4BEG0_0", - "INT_FEEDTHRU_2_SE4BEG0" - ], - [ - "CFG_CENTER_WW4A1_0", - "INT_FEEDTHRU_2_WW4A1" - ], - [ - "CFG_CENTER_WW2A0_0", - "INT_FEEDTHRU_2_WW2A0" - ], - [ - "CFG_CENTER_WW4B3_0", - "INT_FEEDTHRU_2_WW4B3" - ], - [ - "CFG_CENTER_SE4C2_0", - "INT_FEEDTHRU_2_SE4C2" - ], - [ - "CFG_CENTER_SW4END0_0", - "INT_FEEDTHRU_2_SW4END0" - ], - [ - "CFG_CENTER_WW4B2_0", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_SW2A2_0", - "INT_FEEDTHRU_2_SW2A2" - ], - [ - "CFG_CENTER_SE2A1_0", - "INT_FEEDTHRU_2_SE2A1" - ], - [ - "CFG_CENTER_NE2A0_0", - "INT_FEEDTHRU_2_NE2A0" - ], - [ - "CFG_CENTER_EE2A1_0", - "INT_FEEDTHRU_2_EE2A1" - ], - [ - "CFG_CENTER_WW4B0_0", - "INT_FEEDTHRU_2_WW4B0" - ], - [ - "CFG_CENTER_SW4A2_0", - "INT_FEEDTHRU_2_SW4A2" - ], - [ - "CFG_CENTER_WW4B1_0", - "INT_FEEDTHRU_2_WW4B1" - ], - [ - "CFG_CENTER_WW4END2_0", - "INT_FEEDTHRU_2_WW4END2" - ], - [ - "CFG_CENTER_EE4BEG0_0", - "INT_FEEDTHRU_2_EE4BEG0" - ], - [ - "CFG_CENTER_SW4A3_0", - "INT_FEEDTHRU_2_SW4A3" - ], - [ - "CFG_CENTER_LH5_0", - "INT_FEEDTHRU_2_LH5" - ], - [ - "CFG_CENTER_WW4END3_0", - "INT_FEEDTHRU_2_WW4END3" - ], - [ - "CFG_CENTER_WW4END1_0", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_NE4BEG2_0", - "INT_FEEDTHRU_2_NE4BEG2" - ], - [ - "CFG_CENTER_EE4BEG1_0", - "INT_FEEDTHRU_2_EE4BEG1" - ], - [ - "CFG_CENTER_SE4C1_0", - "INT_FEEDTHRU_2_SE4C1" - ], - [ - "CFG_CENTER_NW4END2_0", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_ER1BEG3_0", - "INT_FEEDTHRU_2_ER1BEG3" - ], - [ - "CFG_CENTER_LH11_0", - "INT_FEEDTHRU_2_LH11" - ], - [ - "CFG_CENTER_EE4B2_0", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_LH6_0", - "INT_FEEDTHRU_2_LH6" - ], - [ - "CFG_CENTER_WW4C2_0", - "INT_FEEDTHRU_2_WW4C2" - ], - [ - "CFG_CENTER_EE4A2_0", - "INT_FEEDTHRU_2_EE4A2" - ], - [ - "CFG_CENTER_WW2END0_0", - "INT_FEEDTHRU_2_WW2END0" - ], - [ - "CFG_CENTER_NW4END3_0", - "INT_FEEDTHRU_2_NW4END3" - ], - [ - "CFG_CENTER_NE4C3_0", - "INT_FEEDTHRU_2_NE4C3" - ], - [ - "CFG_CENTER_NW4A3_0", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_WW4C0_0", - "INT_FEEDTHRU_2_WW4C0" - ], - [ - "CFG_CENTER_EE2BEG0_0", - "INT_FEEDTHRU_2_EE2BEG0" - ], - [ - "CFG_CENTER_LH9_0", - "INT_FEEDTHRU_2_LH9" - ], - [ - "CFG_CENTER_NW2A3_0", - "INT_FEEDTHRU_2_NW2A3" - ], - [ - "CFG_CENTER_EE4C1_0", - "INT_FEEDTHRU_2_EE4C1" - ], - [ - "CFG_CENTER_WW4C3_0", - "INT_FEEDTHRU_2_WW4C3" - ], - [ - "CFG_CENTER_WW4C1_0", - "INT_FEEDTHRU_2_WW4C1" - ], - [ - "CFG_CENTER_WL1END3_0", - "INT_FEEDTHRU_2_WL1END3" - ], - [ - "CFG_CENTER_EE2A3_0", - "INT_FEEDTHRU_2_EE2A3" - ], - [ - "CFG_CENTER_WL1END2_0", - "INT_FEEDTHRU_2_WL1END2" - ], - [ - "CFG_CENTER_EE2A2_0", - "INT_FEEDTHRU_2_EE2A2" - ], - [ - "CFG_CENTER_SW4END2_0", - "INT_FEEDTHRU_2_SW4END2" - ], - [ - "CFG_CENTER_LH4_0", - "INT_FEEDTHRU_2_LH4" - ], - [ - "CFG_CENTER_WW2A3_0", - "INT_FEEDTHRU_2_WW2A3" - ], - [ - "CFG_CENTER_EE4BEG3_0", - "INT_FEEDTHRU_2_EE4BEG3" - ], - [ - "CFG_CENTER_ER1BEG1_0", - "INT_FEEDTHRU_2_ER1BEG1" - ], - [ - "CFG_CENTER_NE2A3_0", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_ER1BEG2_0", - "INT_FEEDTHRU_2_ER1BEG2" - ], - [ - "CFG_CENTER_SE4BEG1_0", - "INT_FEEDTHRU_2_SE4BEG1" - ], - [ - "CFG_CENTER_SE4BEG2_0", - "INT_FEEDTHRU_2_SE4BEG2" - ], - [ - "CFG_CENTER_EE4A0_0", - "INT_FEEDTHRU_2_EE4A0" - ], - [ - "CFG_CENTER_SW2A3_0", - "INT_FEEDTHRU_2_SW2A3" - ], - [ - "CFG_CENTER_LH7_0", - "INT_FEEDTHRU_2_LH7" - ], - [ - "CFG_CENTER_NE4C0_0", - "INT_FEEDTHRU_2_NE4C0" - ], - [ - "CFG_CENTER_EL1BEG3_0", - "INT_FEEDTHRU_2_EL1BEG3" - ], - [ - "CFG_CENTER_NW4A0_0", - "INT_FEEDTHRU_2_NW4A0" - ], - [ - "CFG_CENTER_NW4END0_0", - "INT_FEEDTHRU_2_NW4END0" - ], - [ - "CFG_CENTER_EE2A0_0", - "INT_FEEDTHRU_2_EE2A0" - ], - [ - "CFG_CENTER_EE4B3_0", - "INT_FEEDTHRU_2_EE4B3" - ], - [ - "CFG_CENTER_EE4A3_0", - "INT_FEEDTHRU_2_EE4A3" - ], - [ - "CFG_CENTER_EE4C3_0", - "INT_FEEDTHRU_2_EE4C3" - ], - [ - "CFG_CENTER_SW4A1_0", - "INT_FEEDTHRU_2_SW4A1" - ], - [ - "CFG_CENTER_WR1END3_0", - "INT_FEEDTHRU_2_WR1END3" - ], - [ - "CFG_CENTER_ER1BEG0_0", - "INT_FEEDTHRU_2_ER1BEG0" - ], - [ - "CFG_CENTER_EE2BEG2_0", - "INT_FEEDTHRU_2_EE2BEG2" - ], - [ - "CFG_CENTER_SE4BEG3_0", - "INT_FEEDTHRU_2_SE4BEG3" - ], - [ - "CFG_CENTER_WR1END2_0", - "INT_FEEDTHRU_2_WR1END2" - ], - [ - "CFG_CENTER_EE4B1_0", - "INT_FEEDTHRU_2_EE4B1" - ], - [ - "CFG_CENTER_EE4BEG2_0", - "INT_FEEDTHRU_2_EE4BEG2" - ], - [ - "CFG_CENTER_NE4C1_0", - "INT_FEEDTHRU_2_NE4C1" - ], - [ - "CFG_CENTER_LH1_0", - "INT_FEEDTHRU_2_LH1" - ], - [ - "CFG_CENTER_EE2BEG3_0", - "INT_FEEDTHRU_2_EE2BEG3" - ], - [ - "CFG_CENTER_EL1BEG0_0", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_WL1END0_0", - "INT_FEEDTHRU_2_WL1END0" - ], - [ - "CFG_CENTER_WW4A2_0", - "INT_FEEDTHRU_2_WW4A2" - ], - [ - "CFG_CENTER_WW2END3_0", - "INT_FEEDTHRU_2_WW2END3" - ], - [ - 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- [ - "CLK_HROW_CK_BUFHCLK_L8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "CLK_HROW_CK_BUFHCLK_L0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "CLK_HROW_CK_IN_L13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "CLK_HROW_CK_BUFRCLK_L3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "CLK_HROW_CK_IN_L1", - "HCLK_INT_INTERFACE_CK_IN1" - ], - [ - "CLK_HROW_CK_BUFRCLK_L1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ] - ] - }, - { - "grid_deltas": [ - 1, - -6 - ], - "tile_types": [ - "CMT_TOP_R_UPPER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_NE2A2_10", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_SE4C0_10", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_NE4BEG2_10", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_NE4C0_10", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_EE4C0_10", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_NE4C2_10", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_WL1END0_10", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WW4A2_10", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_SE4BEG2_10", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_SE4C2_10", - "VBRK_SE4C2" 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"CMT_TOP_EE4A2_10", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_NW4A1_10", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_NW2A2_10", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_SW4END2_10", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_LH8_10", - "VBRK_LH8" - ], - [ - "CMT_TOP_SW4END3_10", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_NW4A3_10", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_WW4END0_10", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_EE4BEG3_10", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_WR1END3_10", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_SE2A3_10", - "VBRK_SE2A3" - ] - ] - }, - { - "grid_deltas": [ - -1, - -1 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_NE2A1_4", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_IMUX8_4", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WL1END2_4", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WR1END2_4", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_IMUX46_4", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_IMUX15_4", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_EL1BEG0_4", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_IMUX17_4", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_WW4C2_4", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW4END1_4", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_IMUX35_4", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_LH9_4", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NW2A2_4", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_LH10_4", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_IMUX0_4", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX13_4", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_MONITOR_N_4", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_BYP6_4", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX32_4", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX47_4", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_WW2END3_4", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_IMUX31_4", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_WW4END2_4", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_WR1END0_4", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_NE2A3_4", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_EE4C3_4", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_IMUX7_4", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE2A3_4", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX29_4", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_SE4BEG2_4", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_SW4A3_4", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NW4A3_4", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_WW4B0_4", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_IMUX16_4", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4B2_4", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_SE4C0_4", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW4A0_4", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_FAN5_4", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_IMUX9_4", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_NW2A1_4", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_IMUX5_4", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_LH12_4", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_NW4END3_4", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SE2A0_4", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_NW4END2_4", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_NE4C0_4", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_NW2A3_4", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_EE4A2_4", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_NW4A0_4", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX26_4", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WW4A1_4", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW4A2_4", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_IMUX44_4", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH11_4", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE4B2_4", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_WW4B1_4", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_CTRL1_4", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX20_4", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_WL1END0_4", - "INT_INTERFACE_WL1END0" - ], - [ - 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"CLK_HROW_IMUX18_4", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX39_4", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_EE2BEG1_4", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_EE4C1_4", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_EE2A2_4", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE2BEG0_4", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_EE4B1_4", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_EL1BEG1_4", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_SE4BEG3_4", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_EE4B3_4", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX21_4", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_SE2A3_4", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_LH5_4", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NE2A0_4", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_LH1_4", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_SW4A2_4", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_SW4END0_4", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_SW4END3_4", - "INT_INTERFACE_SW4END3" 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"CLK_FEED_R_CK_BUFG_CASC11", - "CLK_PMV_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_PMV_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_PMV_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_PMV_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_PMV_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_PMV_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_PMV_R_CK_BUFG_CASC18" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_PMV_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_PMV_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_PMV_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_PMV_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_PMV_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_PMV_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_PMV_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_PMV_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_PMV_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_PMV_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_PMV_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_PMV_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_PMV_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_PMV_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_PMV_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_PMV_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_PMV_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_PMV_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_PMV_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_PMV_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_PMV_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_PMV_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_PMV_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_PMV_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_PMV_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_PMV_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_PMV_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_PMV_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_PMV_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_PMV_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_PMV_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_PMV_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_PMV_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_PMV_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_PMV_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_PMV_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_PMV_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_PMV_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_PMV_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_PMV_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_PMV_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_PMV_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_PMV_R_CK_BUFG_CASC16" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_FEED", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_LH8", - "VBRK_LH8" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_LH2", - "VBRK_LH2" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLK_FEED_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLK_FEED_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLK_FEED_EE4BEG2", - "VBRK_EE4BEG2" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLK_FEED_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLK_FEED_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLK_FEED_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLK_FEED_LH7", - "VBRK_LH7" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLK_FEED_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLK_FEED_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLK_FEED_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLK_FEED_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLK_FEED_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLK_FEED_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLK_FEED_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLK_FEED_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLK_FEED_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLK_FEED_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLK_FEED_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLK_FEED_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLK_FEED_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLK_FEED_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLK_FEED_LH12", - "VBRK_LH12" - ], - [ - "CLK_FEED_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLK_FEED_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLK_FEED_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLK_FEED_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLK_FEED_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLK_FEED_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLK_FEED_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLK_FEED_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLK_FEED_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLK_FEED_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLK_FEED_EE4B1", - "VBRK_EE4B1" - ], - [ - "CLK_FEED_NE2A2", - "VBRK_NE2A2" - ], - [ - "CLK_FEED_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLK_FEED_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLK_FEED_WW4C2", - "VBRK_WW4C2" - ], - [ - "CLK_FEED_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLK_FEED_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLK_FEED_LH3", - "VBRK_LH3" - ], - [ - "CLK_FEED_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLK_FEED_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLK_FEED_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLK_FEED_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_WR1END0_7", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE4B0_7", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_WW4END1_7", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_EE2BEG0_7", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_WL1END2_7", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_NW4END3_7", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_IMUX6_7", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_LH5_7", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_FAN2_7", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_NE4C3_7", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_WW4A2_7", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_LH4_7", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_EE4C2_7", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_IMUX12_7", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_EE4B3_7", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_EE4BEG2_7", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_LH11_7", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_SW4END0_7", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EE4A2_7", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_CLK0_7", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_IMUX19_7", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_WW4A0_7", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NW4END1_7", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_LH3_7", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_NE2A3_7", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_NE4BEG1_7", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_SW4A0_7", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_IMUX15_7", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SW4END2_7", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_IMUX13_7", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_NE2A1_7", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_WW4A1_7", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_IMUX10_7", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_WW4B1_7", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_IMUX45_7", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_NE4BEG3_7", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE2BEG3_7", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_NW2A3_7", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WL1END1_7", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX26_7", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_EE4A0_7", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_IMUX0_7", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_CTRL1_7", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW2END3_7", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_FAN0_7", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_SE4BEG1_7", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_IMUX34_7", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_EE4A3_7", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SW4A2_7", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_SE4C3_7", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_BYP2_7", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NW4END0_7", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_ER1BEG2_7", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_WW4C1_7", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_BYP1_7", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SW4A3_7", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX37_7", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_SW4END1_7", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EE2A3_7", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX25_7", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EE4A1_7", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_LH7_7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_EE2A1_7", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_BYP3_7", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_WW4B0_7", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_NW2A2_7", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_EE2A2_7", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_BYP4_7", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_BYP5_7", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_IMUX36_7", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_IMUX23_7", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_IMUX8_7", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_IMUX46_7", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_IMUX1_7", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_EE4BEG0_7", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_EE4C1_7", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_WW4C3_7", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_NE4C0_7", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX39_7", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_IMUX7_7", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_IMUX14_7", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_NE4C2_7", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX31_7", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_SE4C2_7", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_WW4C2_7", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_EE2BEG2_7", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_ER1BEG3_7", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_NE4BEG0_7", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_IMUX44_7", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH10_7", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_EL1BEG2_7", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX47_7", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_IMUX32_7", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_SE4C0_7", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_LH1_7", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX27_7", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_NW2A1_7", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_WW4END0_7", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_SE4C1_7", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX16_7", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_ER1BEG1_7", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_EL1BEG0_7", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_NE2A0_7", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_IMUX29_7", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_FAN1_7", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_IMUX22_7", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_IMUX42_7", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_IMUX11_7", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_WW2A1_7", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX3_7", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_WW2A2_7", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_WW2END2_7", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_WW4B2_7", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_SW2A0_7", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_SE2A3_7", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_LH9_7", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_SE2A0_7", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_WL1END3_7", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX43_7", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_EE2BEG1_7", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_BYP0_7", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_NW4A3_7", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_FAN4_7", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_NW2A0_7", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_SW4A1_7", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_IMUX9_7", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_IMUX21_7", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_LH6_7", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_WW4END3_7", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_CTRL0_7", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX2_7", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_IMUX40_7", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_EE4BEG1_7", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_FAN5_7", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_WR1END1_7", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_EE4BEG3_7", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_LH2_7", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_SE4BEG2_7", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_LH12_7", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WW4A3_7", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_IMUX4_7", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_EE2A0_7", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_FAN7_7", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_EE4B2_7", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_WL1END0_7", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_IMUX17_7", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_NE2A2_7", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_NE4BEG2_7", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SE2A2_7", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_IMUX28_7", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX41_7", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_NW4A2_7", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_NW4A1_7", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_WW4B3_7", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_IMUX20_7", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_SW2A2_7", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW4C0_7", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_EE4C0_7", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_BYP6_7", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX38_7", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX24_7", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX33_7", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_WR1END2_7", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_SE4BEG3_7", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_EE4B1_7", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_WW2A3_7", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_WW2A0_7", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_NW4A0_7", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_NW4END2_7", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_CLK1_7", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_NE4C1_7", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_BYP7_7", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_SW4END3_7", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_SE2A1_7", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EL1BEG1_7", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX18_7", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_SE4BEG0_7", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX5_7", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_WR1END3_7", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_IMUX35_7", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SW2A1_7", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_ER1BEG0_7", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_WW2END0_7", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_EL1BEG3_7", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_FAN3_7", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_EE4C3_7", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_LH8_7", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_FAN6_7", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_SW2A3_7", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_WW4END2_7", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_WW2END1_7", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_IMUX30_7", - "INT_INTERFACE_IMUX30" - ] - ] - }, - { - "grid_deltas": [ - 1, - 1 - ], - "tile_types": [ - "CMT_TOP_R_UPPER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_LH6_4", - "VBRK_LH6" - ], - [ - "CMT_TOP_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_LH9_4", - "VBRK_LH9" - ], - [ - "CMT_TOP_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_LH1_4", - "VBRK_LH1" - ], - [ - "CMT_TOP_LH2_4", - "VBRK_LH2" - ], - [ - "CMT_TOP_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_LH5_4", - "VBRK_LH5" - ], - [ - "CMT_TOP_LH4_4", - "VBRK_LH4" - ], - [ - "CMT_TOP_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_EE2A1_4", - "VBRK_EE2A1" - ], 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"VBRK_SW2A0" - ], - [ - "BRAM_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "BRAM_LH3_0", - "VBRK_LH3" - ], - [ - "BRAM_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "BRAM_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "BRAM_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "BRAM_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "BRAM_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "BRAM_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "BRAM_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "BRAM_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "BRAM_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "BRAM_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "BRAM_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "BRAM_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "BRAM_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "BRAM_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "BRAM_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "BRAM_LH1_0", - "VBRK_LH1" - ], - [ - "BRAM_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "BRAM_NW4A1_0", - "VBRK_NW4A1" - ], - [ - "BRAM_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "BRAM_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "BRAM_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "BRAM_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "BRAM_LH8_0", - "VBRK_LH8" - ], - [ - "BRAM_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "BRAM_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "BRAM_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "BRAM_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "BRAM_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "BRAM_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "BRAM_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "BRAM_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "BRAM_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "BRAM_LH2_0", - "VBRK_LH2" - ], - [ - "BRAM_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "BRAM_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "BRAM_MONITOR_N_0", - "VBRK_MONITOR_N" - ], - [ - "BRAM_LH6_0", - "VBRK_LH6" - ], - [ - "BRAM_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "BRAM_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "BRAM_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "BRAM_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "BRAM_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "BRAM_LH10_0", - "VBRK_LH10" - ], - [ - "BRAM_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "BRAM_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "BRAM_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "BRAM_LH7_0", - "VBRK_LH7" - ], - [ - "BRAM_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "BRAM_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "BRAM_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "BRAM_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "BRAM_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "BRAM_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "BRAM_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "BRAM_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "BRAM_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "BRAM_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "BRAM_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "BRAM_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "BRAM_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "BRAM_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "BRAM_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "BRAM_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "BRAM_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "BRAM_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "BRAM_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "BRAM_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "BRAM_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "BRAM_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "BRAM_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "BRAM_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "BRAM_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "BRAM_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "BRAM_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "BRAM_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "BRAM_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "BRAM_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "BRAM_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "BRAM_LH5_0", - "VBRK_LH5" - ], - [ - "BRAM_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "BRAM_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "BRAM_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "BRAM_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "BRAM_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "BRAM_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "BRAM_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "BRAM_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "BRAM_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "BRAM_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "BRAM_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "BRAM_EE4A2_0", - "VBRK_EE4A2" - ], - [ - "BRAM_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "BRAM_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "BRAM_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "BRAM_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "BRAM_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "BRAM_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "BRAM_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "BRAM_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "BRAM_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "BRAM_LH12_0", - "VBRK_LH12" - ], - [ - "BRAM_LH4_0", - "VBRK_LH4" - ], - [ - "BRAM_LH11_0", - "VBRK_LH11" - ], - [ - "BRAM_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "BRAM_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "BRAM_MONITOR_P_0", - "VBRK_MONITOR_P" - ], - [ - "BRAM_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "BRAM_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "BRAM_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "BRAM_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "BRAM_EE4BEG3_0", - "VBRK_EE4BEG3" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "GTX_CHANNEL_1", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTXE2_IMUX36_9", - "VBRK_EXT_IMUX36" - ], - [ - "GTXE2_LOGIC_OUTS_B12_9", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTXE2_BYP1_9", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_LOGIC_OUTS_B23_9", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTXE2_IMUX31_9", - "VBRK_EXT_IMUX31" - ], - [ - "GTXE2_IMUX0_9", - "VBRK_EXT_IMUX0" - ], - [ - "GTXE2_LOGIC_OUTS_B15_9", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTXE2_IMUX1_9", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_LOGIC_OUTS_B18_9", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTXE2_IMUX9_9", - "VBRK_EXT_IMUX9" - ], - [ - "GTXE2_IMUX32_9", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_IMUX41_9", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_FAN5_9", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_IMUX45_9", - "VBRK_EXT_IMUX45" - ], - [ - "GTXE2_IMUX20_9", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_FAN2_9", - "VBRK_EXT_FAN2" - ], - [ - "GTXE2_IMUX47_9", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_IMUX43_9", - "VBRK_EXT_IMUX43" - ], - [ - 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"HCLK_FEEDTHRU_2_CK_IN12" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_FEEDTHRU_2_CK_BUFRCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_FEEDTHRU_2_CK_IN8" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_FEEDTHRU_2_CK_BUFRCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_FEEDTHRU_2_CK_IN6" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_FEEDTHRU_2_CK_IN10" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_FEEDTHRU_2_CK_BUFHCLK11" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_FEEDTHRU_2_CK_BUFHCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_FEEDTHRU_2_CK_IN11" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_FEEDTHRU_2_CK_IN4" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_FEEDTHRU_2_CK_BUFHCLK9" - ] - ] - }, - { - "grid_deltas": [ - 0, - -8 - ], - "tile_types": [ - "CMT_TOP_L_LOWER_T", - "HCLK_CMT_L" - ], - "wire_pairs": [ - [ - "CMT_PHASER_BOT_IRANKB0", - "HCLK_CMT_PHY_CONTROL_IRANKB0" - ], - [ - "CMT_LR_LOWER_T_CLK_IN1_HCLK", - "HCLK_CMT_MUX_MMCM_CLKIN1" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM7", - "HCLK_CMT_MUX_CLK_MMCM7" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM12", - "HCLK_CMT_MUX_CLK_MMCM12" - ], - [ - "CMT_LR_LOWER_T_CLK_IN3_HCLK", - "HCLK_CMT_MUX_MMCM_CLKFBIN" - ], - [ - "CMT_PHASER_DOWN_PHASERREF1", - "HCLK_CMT_BUFMR_PHASEREF1" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM10", - "HCLK_CMT_MUX_CLK_MMCM10" - ], - [ - "CMT_PHASER_BOT_IRANKA0", - "HCLK_CMT_PHY_CONTROL_IRANKA0" - ], - [ - "MMCM_CLK_FREQBB_REBUFOUT1", - "HCLK_CMT_FREQ_REF_NS1" - ], - [ - "CMT_PHASER_IN_B_RCLK1", - "HCLK_CMT_PHASERIN_RCLK1" - ], - [ - "CMT_PHASER_IN_A_RCLK0", - "HCLK_CMT_PHASERIN_RCLK0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM9", - "HCLK_CMT_MUX_CLK_MMCM9" - ], - [ - "CMT_LR_LOWER_T_CLK_PERF0", - "HCLK_CMT_MUX_MMCM_MUXED0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM3", - "HCLK_CMT_MUX_CLK_MMCM3" - ], - [ - "CMT_BOT_HCLKMUX_CLKINT_1", - "HCLK_CMT_MUX_CLKINT_1" - ], - [ - "CMT_LR_LOWER_T_CLK_PERF2", - "HCLK_CMT_MUX_MMCM_MUXED2" - ], - [ - "CMT_PHASER_BOT_IBURSTPENDING0", - "HCLK_CMT_IBURSTPENDING0" - ], - [ - "CMT_PHASER_BOT_ENCALIB1", - "HCLK_CMT_ECALIB1" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM6", - "HCLK_CMT_MUX_CLK_MMCM6" - ], - [ - "MMCM_CLK_FREQBB_REBUFOUT0", - "HCLK_CMT_FREQ_REF_NS0" - ], - [ - "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "HCLK_CMT_PHASEREF_BELOW1" - ], - [ - "CMT_PHASER_BOT_SYNC_BB", - "HCLK_CMT_PHY_SYNC_BB" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM2", - "HCLK_CMT_MUX_CLK_MMCM2" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM11", - "HCLK_CMT_MUX_CLK_MMCM11" - ], - [ - "CMT_PHASER_BOT_IRANKB1", - "HCLK_CMT_PHY_CONTROL_IRANKB1" - ], - [ - "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "HCLK_CMT_PHASEREF_ABOVE0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM0", - "HCLK_CMT_MUX_CLK_MMCM0" - ], - [ - "CMT_LR_LOWER_T_CLK_IN2_HCLK", - "HCLK_CMT_MUX_MMCM_CLKIN2" - ], - [ - "MMCM_CLK_FREQBB_REBUFOUT2", - "HCLK_CMT_FREQ_REF_NS2" - ], - [ - "CMT_PHASER_BOT_ENCALIB0", - "HCLK_CMT_ECALIB0" - ], - [ - "CMT_PHASER_BOT_OBURSTPENDING1", - "HCLK_CMT_OBURSTPENDING1" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM13", - "HCLK_CMT_MUX_CLK_MMCM13" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM5", - "HCLK_CMT_MUX_CLK_MMCM5" - ], - [ - "CMT_BOT_HCLKMUX_CLKINT_0", - "HCLK_CMT_MUX_CLKINT_0" - ], - [ - "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "HCLK_CMT_PHASEREF_BELOW0" - ], - [ - "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "HCLK_CMT_PHASEREF_ABOVE1" - ], - [ - "CMT_PHASER_BOT_REFMUX_2", - "HCLK_CMT_FREQ_PHASER_REFMUX_2" - ], - [ - "CMT_PHASER_BOT_REFMUX_0", - "HCLK_CMT_FREQ_PHASER_REFMUX_0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM1", - "HCLK_CMT_MUX_CLK_MMCM1" - ], - [ - "CMT_PHASER_BOT_IBURSTPENDING1", - "HCLK_CMT_IBURSTPENDING1" - ], - [ - "CMT_PHASER_BOT_IRANKA1", - "HCLK_CMT_PHY_CONTROL_IRANKA1" - ], - [ - "MMCM_CLK_FREQBB_REBUFOUT3", - "HCLK_CMT_FREQ_REF_NS3" - ], - [ - "CMT_PHASER_BOT_OBURSTPENDING0", - "HCLK_CMT_OBURSTPENDING0" - ], - [ - "CMT_PHASER_BOT_REFMUX_1", - "HCLK_CMT_FREQ_PHASER_REFMUX_1" - ], - [ - "CMT_PHASER_DOWN_PHASERREF0", - "HCLK_CMT_BUFMR_PHASEREF0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM8", - "HCLK_CMT_MUX_CLK_MMCM8" - ], - [ - "CMT_LR_LOWER_T_CLK_PERF1", - "HCLK_CMT_MUX_MMCM_MUXED1" - ], - [ - "CMT_LR_LOWER_T_CLK_PERF3", - "HCLK_CMT_MUX_MMCM_MUXED3" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM4", - "HCLK_CMT_MUX_CLK_MMCM4" - ] - ] - }, - { - "grid_deltas": [ - -1, -2 ], "tile_types": [ - "GTX_CHANNEL_1", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTXE2_IMUX21_7", - "VBRK_EXT_IMUX21" - ], - [ - "GTXE2_LOGIC_OUTS_B9_7", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTXE2_LOGIC_OUTS_B20_7", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTXE2_IMUX30_7", - "VBRK_EXT_IMUX30" - ], - [ - "GTXE2_IMUX32_7", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_CTRL0_7", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_LOGIC_OUTS_B6_7", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTXE2_IMUX16_7", - "VBRK_EXT_IMUX16" - ], - [ - "GTXE2_LOGIC_OUTS_B8_7", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTXE2_IMUX22_7", - "VBRK_EXT_IMUX22" - ], - [ - "GTXE2_BYP1_7", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_LOGIC_OUTS_B11_7", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTXE2_LOGIC_OUTS_B4_7", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTXE2_LOGIC_OUTS_B23_7", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTXE2_LOGIC_OUTS_B1_7", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_IMUX46_7", - "VBRK_EXT_IMUX46" - ], - [ - "GTXE2_LOGIC_OUTS_B0_7", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTXE2_LOGIC_OUTS_B3_7", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTXE2_IMUX20_7", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_IMUX37_7", - "VBRK_EXT_IMUX37" - ], - [ - "GTXE2_LOGIC_OUTS_B7_7", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTXE2_IMUX8_7", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX7_7", - "VBRK_EXT_IMUX7" - ], - [ - "GTXE2_BYP4_7", - "VBRK_EXT_BYP4" - ], - [ - "GTXE2_IMUX27_7", - "VBRK_EXT_IMUX27" - ], - [ - "GTXE2_FAN3_7", - "VBRK_EXT_FAN3" - ], - [ - "GTXE2_BYP3_7", - "VBRK_EXT_BYP3" - ], - [ - "GTXE2_IMUX29_7", - "VBRK_EXT_IMUX29" - ], - [ - "GTXE2_FAN4_7", - "VBRK_EXT_FAN4" - ], - [ - "GTXE2_LOGIC_OUTS_B14_7", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTXE2_IMUX0_7", - "VBRK_EXT_IMUX0" - ], - [ - "GTXE2_IMUX12_7", - "VBRK_EXT_IMUX12" - ], - [ - "GTXE2_LOGIC_OUTS_B10_7", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTXE2_IMUX47_7", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_IMUX25_7", - "VBRK_EXT_IMUX25" - ], - [ - "GTXE2_IMUX44_7", - "VBRK_EXT_IMUX44" - ], - [ - "GTXE2_FAN5_7", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_IMUX43_7", - "VBRK_EXT_IMUX43" - ], - [ - "GTXE2_IMUX6_7", - "VBRK_EXT_IMUX6" - ], - [ - "GTXE2_CLK0_7", - "VBRK_EXT_CLK0" - ], - [ - "GTXE2_IMUX41_7", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_IMUX35_7", - "VBRK_EXT_IMUX35" - ], - [ - "GTXE2_IMUX24_7", - "VBRK_EXT_IMUX24" - ], - [ - "GTXE2_LOGIC_OUTS_B2_7", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTXE2_IMUX33_7", - "VBRK_EXT_IMUX33" - ], - [ - "GTXE2_IMUX13_7", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_LOGIC_OUTS_B22_7", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTXE2_LOGIC_OUTS_B13_7", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_FAN7_7", - "VBRK_EXT_FAN7" - ], - [ - "GTXE2_BYP0_7", - "VBRK_EXT_BYP0" - ], - [ - "GTXE2_LOGIC_OUTS_B5_7", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTXE2_IMUX3_7", - "VBRK_EXT_IMUX3" - ], - [ - "GTXE2_IMUX1_7", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_FAN6_7", - "VBRK_EXT_FAN6" - ], - [ - "GTXE2_IMUX45_7", - "VBRK_EXT_IMUX45" - ], - [ - "GTXE2_IMUX28_7", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_IMUX42_7", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_FAN0_7", - "VBRK_EXT_FAN0" - ], - [ - "GTXE2_IMUX2_7", - "VBRK_EXT_IMUX2" - ], - [ - "GTXE2_IMUX4_7", - "VBRK_EXT_IMUX4" - ], - [ - "GTXE2_CLK1_7", - "VBRK_EXT_CLK1" - ], - [ - "GTXE2_IMUX23_7", - "VBRK_EXT_IMUX23" - ], - [ - "GTXE2_IMUX14_7", - "VBRK_EXT_IMUX14" - ], - [ - "GTXE2_IMUX36_7", - "VBRK_EXT_IMUX36" - ], - [ - "GTXE2_FAN2_7", - "VBRK_EXT_FAN2" - ], - [ - "GTXE2_BYP7_7", - "VBRK_EXT_BYP7" - ], - [ - "GTXE2_LOGIC_OUTS_B16_7", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTXE2_LOGIC_OUTS_B12_7", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTXE2_IMUX38_7", - "VBRK_EXT_IMUX38" - ], - [ - "GTXE2_IMUX5_7", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_BYP6_7", - "VBRK_EXT_BYP6" - ], - [ - "GTXE2_CTRL1_7", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_IMUX31_7", - "VBRK_EXT_IMUX31" - ], - [ - "GTXE2_LOGIC_OUTS_B15_7", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTXE2_IMUX11_7", - "VBRK_EXT_IMUX11" - ], - [ - "GTXE2_BYP2_7", - "VBRK_EXT_BYP2" - ], - [ - "GTXE2_IMUX39_7", - "VBRK_EXT_IMUX39" - ], - [ - "GTXE2_FAN1_7", - "VBRK_EXT_FAN1" - ], - [ - "GTXE2_IMUX10_7", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_BYP5_7", - "VBRK_EXT_BYP5" - ], - [ - "GTXE2_IMUX34_7", - "VBRK_EXT_IMUX34" - ], - [ - "GTXE2_IMUX18_7", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_IMUX26_7", - "VBRK_EXT_IMUX26" - ], - [ - "GTXE2_IMUX9_7", - "VBRK_EXT_IMUX9" - ], - [ - "GTXE2_LOGIC_OUTS_B18_7", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTXE2_IMUX17_7", - "VBRK_EXT_IMUX17" - ], - [ - "GTXE2_IMUX15_7", - "VBRK_EXT_IMUX15" - ], - [ - "GTXE2_LOGIC_OUTS_B19_7", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTXE2_IMUX19_7", - "VBRK_EXT_IMUX19" - ], - [ - "GTXE2_IMUX40_7", - "VBRK_EXT_IMUX40" - ] - ] - }, - { - "grid_deltas": [ - 1, - 4 - ], - "tile_types": [ - "INT_FEEDTHRU_2", - "MONITOR_MID_FUJI2" - ], - "wire_pairs": [ - [ - "INT_FEEDTHRU_2_WW4A1", - "MONITOR_WW4A1_4" - ], - [ - "INT_FEEDTHRU_2_WW4C0", - "MONITOR_WW4C0_4" - ], - [ - "INT_FEEDTHRU_2_NW2A2", - "MONITOR_NW2A2_4" - ], - [ - "INT_FEEDTHRU_2_LH2", - "MONITOR_LH2_4" - ], - [ - "INT_FEEDTHRU_2_SW4A0", - "MONITOR_SW4A0_4" - ], - [ - "INT_FEEDTHRU_2_WW2A3", - "MONITOR_WW2A3_4" - ], - [ - "INT_FEEDTHRU_2_NW2A0", - "MONITOR_NW2A0_4" - ], - [ - "INT_FEEDTHRU_2_WW2A0", - "MONITOR_WW2A0_4" - ], - [ - "INT_FEEDTHRU_2_NE2A0", - "MONITOR_NE2A0_4" - ], - [ - "INT_FEEDTHRU_2_SE4C2", - "MONITOR_SE4C2_4" - ], - [ - "INT_FEEDTHRU_2_EE4BEG2", - "MONITOR_EE4BEG2_4" - ], - [ - "INT_FEEDTHRU_2_EL1BEG0", - "MONITOR_EL1BEG0_4" - ], - [ - "INT_FEEDTHRU_2_MONITOR_P", - "MONITOR_HORIZ_VAUXP2" - ], - [ - "INT_FEEDTHRU_2_LH7", - "MONITOR_LH7_4" - ], - [ - "INT_FEEDTHRU_2_WW4B2", - "MONITOR_WW4B2_4" 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"LIOI3", - "LIOI3_SING" - ], - "wire_pairs": [ - [ - "IOI_LEAF_GCLK0", - "IOI_SING_LEAF_GCLK0" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_SING_RCLK_FORIO3" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_SING_LEAF_GCLK2" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_SING_LEAF_GCLK4" - ], - [ - "IOI_IOCLK3", - "IOI_SING_IOCLK3" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_SING_LEAF_GCLK5" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_SING_RCLK_FORIO1" - ], - [ - "IOI_IOCLK2", - "IOI_SING_IOCLK2" - ], - [ - "IOI_RCLK_FORIO0", - "IOI_SING_RCLK_FORIO0" - ], - [ - "IOI_IOCLK1", - "IOI_SING_IOCLK1" - ], - [ - "IOI_TBYTEIN", - "IOI_SING_TBYTEIN" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_SING_LEAF_GCLK1" - ], - [ - "IOI_IOCLK0", - "IOI_SING_IOCLK0" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_SING_RCLK_FORIO2" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_SING_LEAF_GCLK3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 3 - ], - "tile_types": [ - "GTX_CHANNEL_1", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTXE2_IMUX11_2", - "VBRK_EXT_IMUX11" - ], - [ - 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"GTXE2_LOGIC_OUTS_B19_2", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTXE2_FAN2_2", - "VBRK_EXT_FAN2" - ], - [ - "GTXE2_IMUX41_2", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_LOGIC_OUTS_B10_2", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTXE2_IMUX26_2", - "VBRK_EXT_IMUX26" - ], - [ - "GTXE2_LOGIC_OUTS_B5_2", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTXE2_IMUX23_2", - "VBRK_EXT_IMUX23" - ], - [ - "GTXE2_IMUX35_2", - "VBRK_EXT_IMUX35" - ], - [ - "GTXE2_LOGIC_OUTS_B23_2", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTXE2_IMUX31_2", - "VBRK_EXT_IMUX31" - ], - [ - "GTXE2_IMUX24_2", - "VBRK_EXT_IMUX24" - ], - [ - "GTXE2_IMUX14_2", - "VBRK_EXT_IMUX14" - ], - [ - "GTXE2_BYP5_2", - "VBRK_EXT_BYP5" - ], - [ - "GTXE2_IMUX30_2", - "VBRK_EXT_IMUX30" - ], - [ - "GTXE2_IMUX3_2", - "VBRK_EXT_IMUX3" - ], - [ - "GTXE2_CLK0_2", - "VBRK_EXT_CLK0" - ], - [ - "GTXE2_IMUX0_2", - "VBRK_EXT_IMUX0" - ], - [ - "GTXE2_IMUX21_2", - "VBRK_EXT_IMUX21" - ], - [ - "GTXE2_BYP4_2", - "VBRK_EXT_BYP4" - ], - [ - "GTXE2_IMUX40_2", - "VBRK_EXT_IMUX40" - ], - [ - "GTXE2_CLK1_2", - "VBRK_EXT_CLK1" - ], - [ - "GTXE2_IMUX8_2", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX36_2", - "VBRK_EXT_IMUX36" - ], - [ - "GTXE2_LOGIC_OUTS_B13_2", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_LOGIC_OUTS_B22_2", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTXE2_LOGIC_OUTS_B7_2", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTXE2_CTRL0_2", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_IMUX12_2", - "VBRK_EXT_IMUX12" - ], - [ - "GTXE2_IMUX37_2", - "VBRK_EXT_IMUX37" - ], - [ - "GTXE2_IMUX5_2", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_IMUX13_2", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_CTRL1_2", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_LOGIC_OUTS_B1_2", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_IMUX47_2", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_IMUX1_2", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_IMUX10_2", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_IMUX7_2", - "VBRK_EXT_IMUX7" - ], - [ - "GTXE2_LOGIC_OUTS_B8_2", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTXE2_FAN3_2", - "VBRK_EXT_FAN3" - ], - [ - "GTXE2_IMUX2_2", - "VBRK_EXT_IMUX2" - ], - [ - "GTXE2_IMUX15_2", - "VBRK_EXT_IMUX15" - ], - [ - "GTXE2_LOGIC_OUTS_B6_2", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTXE2_FAN1_2", - "VBRK_EXT_FAN1" - ], - [ - "GTXE2_LOGIC_OUTS_B11_2", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTXE2_LOGIC_OUTS_B16_2", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTXE2_LOGIC_OUTS_B18_2", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTXE2_IMUX20_2", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_LOGIC_OUTS_B0_2", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTXE2_FAN6_2", - "VBRK_EXT_FAN6" - ], - [ - "GTXE2_FAN4_2", - "VBRK_EXT_FAN4" - ], - [ - "GTXE2_IMUX32_2", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_LOGIC_OUTS_B20_2", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTXE2_LOGIC_OUTS_B2_2", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTXE2_IMUX33_2", - "VBRK_EXT_IMUX33" - ], - [ - "GTXE2_FAN5_2", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_BYP3_2", - "VBRK_EXT_BYP3" - ], - [ - "GTXE2_IMUX4_2", - "VBRK_EXT_IMUX4" - ], - [ - "GTXE2_IMUX17_2", - "VBRK_EXT_IMUX17" - ], - [ - "GTXE2_BYP1_2", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_IMUX34_2", - "VBRK_EXT_IMUX34" - ], - [ - "GTXE2_LOGIC_OUTS_B21_2", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTXE2_IMUX44_2", - "VBRK_EXT_IMUX44" - ], - [ - "GTXE2_IMUX18_2", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_LOGIC_OUTS_B3_2", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTXE2_IMUX28_2", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_IMUX42_2", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_IMUX19_2", - "VBRK_EXT_IMUX19" - ], - [ - "GTXE2_IMUX45_2", - "VBRK_EXT_IMUX45" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMV2" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "DSP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "DSP_LOGIC_OUTS_B20_2", - "INT_INTERFACE_LOGIC_OUTS_B20" - ], - [ - "DSP_LOGIC_OUTS_B15_2", - "INT_INTERFACE_LOGIC_OUTS_B15" - ], - [ - "DSP_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "DSP_WW2A3_2", - "INT_INTERFACE_WW2A3" - ], - [ - "DSP_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "DSP_NW4END1_2", - "INT_INTERFACE_NW4END1" - ], - [ - "DSP_EE4B3_2", - "INT_INTERFACE_EE4B3" - ], - [ - "DSP_LOGIC_OUTS_B0_2", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "DSP_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "DSP_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "DSP_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "DSP_CLK0_2", - "INT_INTERFACE_CLK0" - ], - [ - "DSP_FAN0_2", - "INT_INTERFACE_FAN0" - ], - [ - "DSP_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "DSP_LOGIC_OUTS_B22_2", - "INT_INTERFACE_LOGIC_OUTS_B22" - ], - [ - "DSP_SE4C0_2", - "INT_INTERFACE_SE4C0" - ], - [ - "DSP_SW2A1_2", - "INT_INTERFACE_SW2A1" - ], - [ - "DSP_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "DSP_ER1BEG0_2", - "INT_INTERFACE_ER1BEG0" - ], - [ - "DSP_LOGIC_OUTS_B13_2", - "INT_INTERFACE_LOGIC_OUTS_B13" - ], - [ - "DSP_FAN4_2", - "INT_INTERFACE_FAN4" - ], - [ - "DSP_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ - "DSP_IMUX5_2", - "INT_INTERFACE_IMUX5" - ], - [ - "DSP_WW2A2_2", - "INT_INTERFACE_WW2A2" - ], - [ - "DSP_LOGIC_OUTS_B17_2", - "INT_INTERFACE_LOGIC_OUTS_B17" - ], - [ - "DSP_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "DSP_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "DSP_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "DSP_IMUX44_2", - "INT_INTERFACE_IMUX44" - ], - [ - "DSP_IMUX42_2", - "INT_INTERFACE_IMUX42" - ], - [ - "DSP_EE4BEG2_2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "DSP_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "DSP_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "DSP_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "DSP_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "DSP_NE2A0_2", - "INT_INTERFACE_NE2A0" - ], - [ - "DSP_IMUX36_2", - "INT_INTERFACE_IMUX36" - ], - [ - "DSP_SW4A3_2", - "INT_INTERFACE_SW4A3" - ], - [ - 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"INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_MONITOR_N_0", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_MONITOR_P_0", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_IMUX46_0", - "INT_INTERFACE_IMUX46" - ] - ] - }, - { - "grid_deltas": [ - 0, - 5 - ], - "tile_types": [ - "CMT_TOP_L_UPPER_B", - "HCLK_CMT_L" - ], - "wire_pairs": [ - [ - "CMT_PHY_CONTROL_IRANKA0", - "HCLK_CMT_PHY_CONTROL_IRANKA0" - ], - [ - "CMT_PHASER_UP_PHASERREF_BELOW1", - "HCLK_CMT_PHASEREF_BELOW1" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL4", - "HCLK_CMT_MUX_CLK_PLL4" - ], - [ - "CMT_PHASER_IN_C_RCLK2", - "HCLK_CMT_PHASERIN_RCLK2" - ], - [ - "CMT_R_TOP_UPPER_B_CLKFBIN", - "HCLK_CMT_MUX_PLLE2_CLKFBIN" - ], - [ - "CMT_L_TOP_UPPER_B_CLKINT_2", - "HCLK_CMT_MUX_CLKINT_2" - ], - [ - "CMT_PHY_CONTROL_IBURSTPENDING1", - "HCLK_CMT_IBURSTPENDING1" - ], - [ - "CMT_FREQ_PHASER_REFMUX_1", - "HCLK_CMT_FREQ_PHASER_REFMUX_1" - ], - [ - "CMT_PHASER_UP_PHASERREF0", - "HCLK_CMT_BUFMR_PHASEREF0" - ], - [ - "CMT_PHASER_UP_PHASERREF_ABOVE1", - "HCLK_CMT_PHASEREF_ABOVE1" - ], - [ - "CMT_PHASER_UP_PHASERREF_ABOVE0", - "HCLK_CMT_PHASEREF_ABOVE0" - ], - [ - "PLL_CLK_FREQBB_REBUFOUT1", - "HCLK_CMT_FREQ_REF_NS1" - ], - [ - "CMT_PHY_CONTROL_OBURSTPENDING1", - "HCLK_CMT_OBURSTPENDING1" - ], - [ - "CMT_PHASER_UP_PHASERREF1", - "HCLK_CMT_BUFMR_PHASEREF1" - ], - [ - "PLL_CLK_FREQBB_REBUFOUT2", - "HCLK_CMT_FREQ_REF_NS2" - ], - [ - "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "HCLK_CMT_PREF_TMUXOUT" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL7", - "HCLK_CMT_MUX_CLK_PLL7" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL3", - "HCLK_CMT_MUX_CLK_PLL3" - ], - [ - "CMT_PHASER_REF_CLKOUT_TOHCLK", - "HCLK_CMT_PREF_CLKOUT" - ], - [ - "CMT_FREQ_PHASER_REFMUX_2", - "HCLK_CMT_FREQ_PHASER_REFMUX_2" - ], - [ - "CMT_PHY_CONTROL_ECALIB1", - "HCLK_CMT_ECALIB1" - ], - [ - "CMT_PHY_CONTROL_IRANKB0", - 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"CMT_TOP_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_NE2A0_1", - "VBRK_NE2A0" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_PMV2_SVT", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_FEED_WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_FEED_NW2A0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_PMV_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_FEED_LH1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_FEED_WW2END2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_FEED_EE2A3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_PMV_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_FEED_ER1BEG1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_FEED_SE2A1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_FEED_WW4END3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_FEED_NW4END1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_FEED_LH10", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_FEED_WL1END1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_PMV_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_PMV_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_FEED_WR1END1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_FEED_EL1BEG1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_FEED_SE4BEG2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_PMV_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_FEED_EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_FEED_SW2A1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_FEED_EE4A3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_FEED_WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_PMV_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_FEED_NE4BEG0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_FEED_SW2A2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_FEED_SE4C3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_PMV_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_FEED_SE4BEG1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_FEED_EL1BEG3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_FEED_EL1BEG2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_FEED_NE4BEG3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_FEED_EE4B2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_FEED_NW2A1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_FEED_LH5", - "INT_INTERFACE_LH5" - ], - [ - "CLK_PMV_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_FEED_WW4C1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_FEED_WW4B0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_FEED_SW2A0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_FEED_NW2A3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_FEED_WR1END0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_FEED_NW4A1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_FEED_SW4A3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_FEED_NE4C1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_FEED_WW4C0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_FEED_WW2A3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_PMV_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_FEED_SW4END1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_FEED_WW4B1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_FEED_EE4A0", - "INT_INTERFACE_EE4A0" - ], - [ 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- ], - [ - "CLK_PMV_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_FEED_WW4A0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_FEED_NE4C2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_FEED_NE4C3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_FEED_LH3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_FEED_SE2A2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_FEED_NW4END2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_FEED_SE4BEG3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_PMV_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_FEED_WR1END3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_PMV_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_FEED_WW4B2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_PMV_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_FEED_SW4END3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_FEED_NW4END0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_FEED_NE4BEG1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_FEED_LH8", - "INT_INTERFACE_LH8" - ], - [ - "CLK_PMV_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_FEED_EE4B3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_FEED_WW4C2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_FEED_WW2A2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_FEED_SW4A2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_FEED_LH9", - "INT_INTERFACE_LH9" - ], - [ - "CLK_PMV_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_FEED_EE4BEG0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_FEED_EE4BEG3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_PMV_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_FEED_EE2BEG0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_FEED_EE4B0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_FEED_EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_FEED_SW4A1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_FEED_WW4A1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_FEED_SE4C1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_FEED_SE4C2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_PMV_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_FEED_SW4END0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_FEED_EE2A1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_FEED_LH6", - "INT_INTERFACE_LH6" - ], - [ - "CLK_FEED_EE4A1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_FEED_EE2BEG3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_FEED_SE4BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_FEED_LH7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_FEED_EL1BEG0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_FEED_LH11", - "INT_INTERFACE_LH11" - ], - [ - "CLK_FEED_WR1END2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_FEED_WW4END0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_FEED_WW4B3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_FEED_NW4A3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_FEED_WW2A1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_PMV_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_PMV_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_FEED_SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_FEED_ER1BEG0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_PMV_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_FEED_ER1BEG2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_PMV_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_FEED_WW4A3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_FEED_EE4BEG2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_FEED_EE4A2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_EE2A0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_PMV_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_FEED_NW2A2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_FEED_WW4A2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_FEED_WW2END1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_FEED_WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_FEED_LH4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_FEED_EE2BEG1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_LOGIC_OUTS5_0", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_FEED_NE4BEG2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_FEED_EE4C0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_FEED_LH12", - "INT_INTERFACE_LH12" - ], - [ - "CLK_FEED_NE2A2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_FEED_WW4END1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_FEED_EE4BEG1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_PMV_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_FEED_LH2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_FEED_NE2A0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_FEED_NW4A0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_NW4END3", - "INT_INTERFACE_NW4END3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_INT_INTERFACE", - "HCLK_TERM" - ], - "wire_pairs": [ - [ - "HCLK_INT_INTERFACE_CCIO0", - "HCLK_TERM_CCIO0" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_TERM_PERFCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_TERM_CK_BUFRCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_TERM_CK_BUFHCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_TERM_CK_BUFRCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_TERM_CK_BUFHCLK5" - ], - [ - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_TERM_CCIO3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_TERM_CK_BUFHCLK6" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_TERM_CK_BUFHCLK4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_TERM_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_TERM_CCIO1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_TERM_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_TERM_CK_BUFHCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_TERM_CK_BUFHCLK10" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_TERM_CK_BUFHCLK9" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_TERM_CK_BUFHCLK0" - ], - [ - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_TERM_CCIO2" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_TERM_PERFCLK1" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_TERM_PERFCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_TERM_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_TERM_CK_BUFRCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_TERM_CK_BUFHCLK1" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_TERM_PERFCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_TERM_CK_BUFHCLK11" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLBLL_L", - "VBRK" - ], - "wire_pairs": [ - [ - "CLBLL_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLBLL_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLBLL_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLBLL_EE4B1", - "VBRK_EE4B1" - ], - [ - "CLBLL_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLBLL_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLBLL_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLBLL_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLBLL_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLBLL_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLBLL_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLBLL_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLBLL_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLBLL_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLBLL_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLBLL_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLBLL_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLBLL_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLBLL_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLBLL_LH11", - "VBRK_LH11" - ], - [ - "CLBLL_LH3", - "VBRK_LH3" - ], - [ - "CLBLL_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLBLL_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLBLL_LH6", - "VBRK_LH6" - ], - [ - "CLBLL_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLBLL_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLBLL_WW4C2", - "VBRK_WW4C2" - ], - [ - "CLBLL_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLBLL_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLBLL_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLBLL_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLBLL_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLBLL_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLBLL_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLBLL_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLBLL_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLBLL_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLBLL_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLBLL_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLBLL_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLBLL_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLBLL_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLBLL_LH5", - "VBRK_LH5" - ], - [ - "CLBLL_LH1", - "VBRK_LH1" - ], - [ - "CLBLL_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLBLL_LH7", - "VBRK_LH7" - ], - [ - "CLBLL_LH10", - "VBRK_LH10" - ], - [ - "CLBLL_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLBLL_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLBLL_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLBLL_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLBLL_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLBLL_NE2A2", - "VBRK_NE2A2" - ], - [ - "CLBLL_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLBLL_LH2", - "VBRK_LH2" - ], - [ - "CLBLL_LH9", - "VBRK_LH9" - ], - [ - "CLBLL_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLBLL_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLBLL_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLBLL_LH8", - "VBRK_LH8" - ], - [ - "CLBLL_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLBLL_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLBLL_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLBLL_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLBLL_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLBLL_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLBLL_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLBLL_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLBLL_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLBLL_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLBLL_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLBLL_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLBLL_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLBLL_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLBLL_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLBLL_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLBLL_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLBLL_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLBLL_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLBLL_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLBLL_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLBLL_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLBLL_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLBLL_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLBLL_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLBLL_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLBLL_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLBLL_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLBLL_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLBLL_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLBLL_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLBLL_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLBLL_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLBLL_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLBLL_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLBLL_EE4BEG2", - "VBRK_EE4BEG2" - ], - [ - "CLBLL_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLBLL_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLBLL_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLBLL_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLBLL_LH12", - "VBRK_LH12" - ], - [ - "CLBLL_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLBLL_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLBLL_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLBLL_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLBLL_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLBLL_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLBLL_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLBLL_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLBLL_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLBLL_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLBLL_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLBLL_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLBLL_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLBLL_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLBLL_LH4", - "VBRK_LH4" - ], - [ - "CLBLL_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLBLL_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLBLL_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLBLL_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLBLL_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLBLL_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLBLL_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLBLL_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLBLL_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLBLL_SW4A2", - "VBRK_SW4A2" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "BRAM_L", - "HCLK_BRAM" - ], - "wire_pairs": [ - [ - "BRAM_FIFO36_CASCADEINB", - "HCLK_BRAM_CASCADEB_L" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" - ], - [ - "BRAM_PMVBRAM_SELECT1", - "HCLK_BRAM_PMVBRAM_SELECT1" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" - ], - [ - "BRAM_PMVBRAM_ODIV2", - "HCLK_BRAM_PMVBRAM_ODIV2" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" - ], - [ - "BRAM_PMVBRAM_SELECT2", - "HCLK_BRAM_PMVBRAM_SELECT2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" - ], - [ - "BRAM_FIFO36_CASCADEINA", - "HCLK_BRAM_CASCADEA_L" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" - ], - [ - "BRAM_PMVBRAM_ODIV4", - "HCLK_BRAM_PMVBRAM_ODIV4" - ], - [ - "BRAM_PMVBRAM_O", - "HCLK_BRAM_PMVBRAM_O" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" - ], - [ - "BRAM_PMVBRAM_SELECT4", - "HCLK_BRAM_PMVBRAM_SELECT4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" - ], - [ - "BRAM_PMVBRAM_SELECT3", - "HCLK_BRAM_PMVBRAM_SELECT3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" - ] - ] - }, - { - "grid_deltas": [ - 1, - -4 - ], - "tile_types": [ - "CMT_TOP_R_LOWER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_EE2A2_5", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_WL1END2_5", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_WW4END0_5", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_LH9_5", - "VBRK_LH9" - ], - [ - "CMT_TOP_WW4B2_5", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_LH3_5", - "VBRK_LH3" - ], - [ - "CMT_TOP_EE4BEG0_5", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW4C0_5", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_SE2A1_5", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_WR1END1_5", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_SW4A2_5", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_WW4END2_5", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_EE4C3_5", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_SW2A0_5", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_NW2A0_5", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_WW4A3_5", - "VBRK_WW4A3" - ], - [ - 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], - [ - "PCIE_CLK0_L_17", - "INT_INTERFACE_CLK0" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "INT_R", - "PCIE_INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "NW2END2", - "INT_INTERFACE_NW2A2" - ], - [ - "LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS8" - ], - [ - "NE6E1", - "INT_INTERFACE_NE4C1" - ], - [ - "EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "EE4BEG1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "IMUX45", - "PCIE_INT_INTERFACE_IMUX45" - ], - [ - "LOGIC_OUTS12", - "INT_INTERFACE_LOGIC_OUTS12" - ], - [ - "EE2A1", - "INT_INTERFACE_EE2A1" - ], - [ - "SE6E2", - "INT_INTERFACE_SE4C2" - ], - [ - "EE4A1", - "INT_INTERFACE_EE4A1" - ], - [ - "LOGIC_OUTS7", - "INT_INTERFACE_LOGIC_OUTS7" - ], - [ - "LH5", - "INT_INTERFACE_LH5" - ], - [ - "IMUX36", - "PCIE_INT_INTERFACE_IMUX36" - ], - [ - "IMUX1", - "PCIE_INT_INTERFACE_IMUX1" - ], - [ - "WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "SW6END1", - "INT_INTERFACE_SW4END1" - ], - [ - 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], - [ - "GTXE2_INT_INTERFACE_IMUX3", - "IMUX3" - ], - [ - "INT_INTERFACE_WW4B0", - "WW4B0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS22", - "LOGIC_OUTS22" - ], - [ - "INT_INTERFACE_WL1END1", - "WL1END1" - ], - [ - "INT_INTERFACE_EE4A0", - "EE4A0" - ] - ] - }, - { - "grid_deltas": [ - -1, - -3 - ], - "tile_types": [ - "BRAM_L", - "CLBLM_R" - ], - "wire_pairs": [ - [ - "BRAM_EE2BEG0_3", - "CLBLM_EE2BEG0" - ], - [ - "BRAM_EE4C3_3", - "CLBLM_EE4C3" - ], - [ - "BRAM_ER1BEG0_3", - "CLBLM_ER1BEG0" - ], - [ - "BRAM_WW4A0_3", - "CLBLM_WW4A0" - ], - [ - "BRAM_EE2A2_3", - "CLBLM_EE2A2" - ], - [ - "BRAM_SE4C2_3", - "CLBLM_SE4C2" - ], - [ - "BRAM_NE4C3_3", - "CLBLM_NE4C3" - ], - [ - "BRAM_WW2A3_3", - "CLBLM_WW2A3" - ], - [ - "BRAM_EE2BEG3_3", - "CLBLM_EE2BEG3" - ], - [ - "BRAM_EE2A1_3", - "CLBLM_EE2A1" - ], - [ - "BRAM_EE4B2_3", - "CLBLM_EE4B2" - ], - [ - "BRAM_WW4A1_3", - "CLBLM_WW4A1" - ], - [ - "BRAM_WW4END0_3", - "CLBLM_WW4END0" - ], - [ - "BRAM_SE4C1_3", - "CLBLM_SE4C1" - ], - [ - "BRAM_LH8_3", - "CLBLM_LH8" - ], - [ - "BRAM_EE4BEG1_3", - "CLBLM_EE4BEG1" - ], - [ - "BRAM_EE4BEG2_3", - "CLBLM_EE4BEG2" - ], - [ - "BRAM_WW4B3_3", - "CLBLM_WW4B3" - ], - [ - "BRAM_EE2A3_3", - "CLBLM_EE2A3" - ], - [ - "BRAM_EE2BEG2_3", - "CLBLM_EE2BEG2" - ], - [ - "BRAM_LH11_3", - "CLBLM_LH11" - ], - [ - "BRAM_LH2_3", - "CLBLM_LH2" - ], - [ - "BRAM_SW4END0_3", - "CLBLM_SW4END0" - ], - [ - "BRAM_NW4A2_3", - "CLBLM_NW4A2" - ], - [ - "BRAM_NE2A3_3", - "CLBLM_NE2A3" - ], - [ - "BRAM_ER1BEG2_3", - "CLBLM_ER1BEG2" - ], - [ - "BRAM_WW2A0_3", - "CLBLM_WW2A0" - ], - [ - "BRAM_NW4A1_3", - "CLBLM_NW4A1" - ], - [ - "BRAM_SW2A3_3", - "CLBLM_SW2A3" - ], - [ - "BRAM_NE4BEG3_3", - "CLBLM_NE4BEG3" - ], - [ - "BRAM_NW2A3_3", - "CLBLM_NW2A3" - ], - [ - "BRAM_EE4B0_3", - "CLBLM_EE4B0" - ], - [ - "BRAM_EE4B3_3", - "CLBLM_EE4B3" - ], - [ - "BRAM_EE4A1_3", - "CLBLM_EE4A1" - ], - [ - "BRAM_SE2A3_3", - "CLBLM_SE2A3" - ], - [ - "BRAM_EE4BEG3_3", - "CLBLM_EE4BEG3" - ], - [ - "BRAM_WW4B1_3", - "CLBLM_WW4B1" - ], - [ - "BRAM_WW2A1_3", - "CLBLM_WW2A1" - ], - [ - "BRAM_WL1END1_3", - "CLBLM_WL1END1" - ], - [ - "BRAM_LH5_3", - "CLBLM_LH5" - ], - [ - "BRAM_SE2A0_3", - "CLBLM_SE2A0" - ], - [ - "BRAM_LH4_3", - "CLBLM_LH4" - ], - [ - "BRAM_LH12_3", - "CLBLM_LH12" - ], - [ - "BRAM_NE2A2_3", - "CLBLM_NE2A2" - ], - [ - "BRAM_NE4BEG0_3", - "CLBLM_NE4BEG0" - ], - [ - "BRAM_WW4B2_3", - "CLBLM_WW4B2" - ], - [ - "BRAM_WW4C3_3", - "CLBLM_WW4C3" - ], - [ - "BRAM_MONITOR_N_3", - "CLBLM_MONITOR_N" - ], - [ - "BRAM_NE4C0_3", - "CLBLM_NE4C0" - ], - [ - "BRAM_NW4END2_3", - "CLBLM_NW4END2" - ], - [ - "BRAM_WR1END3_3", - "CLBLM_WR1END3" - ], - [ - "BRAM_SE2A1_3", - "CLBLM_SE2A1" - ], - [ - "BRAM_WR1END1_3", - "CLBLM_WR1END1" - ], - [ - "BRAM_WW2A2_3", - "CLBLM_WW2A2" - ], - [ - "BRAM_WL1END3_3", - "CLBLM_WL1END3" - ], - [ - "BRAM_EE4A3_3", - "CLBLM_EE4A3" - ], - [ - "BRAM_EE4B1_3", - "CLBLM_EE4B1" - ], - [ - "BRAM_EE2A0_3", - "CLBLM_EE2A0" - ], - [ - "BRAM_WL1END2_3", - "CLBLM_WL1END2" - ], - [ - "BRAM_WR1END0_3", - "CLBLM_WR1END0" - ], - [ - "BRAM_SW4END2_3", - "CLBLM_SW4END2" - ], - [ - "BRAM_SW2A2_3", - "CLBLM_SW2A2" - ], - [ - "BRAM_WW4C0_3", - "CLBLM_WW4C0" - ], - [ - "BRAM_NE4C1_3", - "CLBLM_NE4C1" - ], - [ - "BRAM_SW2A0_3", - "CLBLM_SW2A0" - ], - [ - "BRAM_NW2A2_3", - "CLBLM_NW2A2" - ], - [ - "BRAM_EE4C0_3", - "CLBLM_EE4C0" - ], - [ - "BRAM_EE4C1_3", - "CLBLM_EE4C1" - ], - [ - "BRAM_LH1_3", - "CLBLM_LH1" - ], - [ - "BRAM_WW2END2_3", - "CLBLM_WW2END2" - ], - [ - "BRAM_WR1END2_3", - "CLBLM_WR1END2" - ], - [ - "BRAM_WW2END1_3", - "CLBLM_WW2END1" - ], - [ - "BRAM_SE4BEG2_3", - "CLBLM_SE4BEG2" - ], - [ - "BRAM_NW2A0_3", - "CLBLM_NW2A0" - ], - [ - "BRAM_MONITOR_P_3", - "CLBLM_MONITOR_P" - ], - [ - "BRAM_EL1BEG1_3", - "CLBLM_EL1BEG1" - ], - [ - "BRAM_SW4A2_3", - "CLBLM_SW4A2" - ], - [ - "BRAM_WW4END3_3", - "CLBLM_WW4END3" - ], - [ - "BRAM_LH7_3", - "CLBLM_LH7" - ], - [ - "BRAM_WW4END2_3", - "CLBLM_WW4END2" - ], - [ - "BRAM_NW2A1_3", - "CLBLM_NW2A1" - ], - [ - "BRAM_EL1BEG2_3", - "CLBLM_EL1BEG2" - ], - [ - "BRAM_NE4BEG1_3", - "CLBLM_NE4BEG1" - ], - [ - "BRAM_WW4A3_3", - "CLBLM_WW4A3" - ], - [ - "BRAM_LH9_3", - "CLBLM_LH9" - ], - [ - "BRAM_WW2END3_3", - "CLBLM_WW2END3" - ], - [ - "BRAM_SE4BEG0_3", - "CLBLM_SE4BEG0" - ], - [ - "BRAM_EE2BEG1_3", - "CLBLM_EE2BEG1" - ], - [ - "BRAM_SE4BEG3_3", - "CLBLM_SE4BEG3" - ], - [ - "BRAM_WW4B0_3", - "CLBLM_WW4B0" - ], - [ - "BRAM_EE4A2_3", - "CLBLM_EE4A2" - ], - [ - "BRAM_NW4A0_3", - "CLBLM_NW4A0" - ], - [ - "BRAM_SW4END3_3", - "CLBLM_SW4END3" - ], - [ - "BRAM_NE4C2_3", - "CLBLM_NE4C2" - ], - [ - "BRAM_ER1BEG3_3", - "CLBLM_ER1BEG3" - ], - [ - "BRAM_NW4END1_3", - "CLBLM_NW4END1" - ], - [ - "BRAM_SE4C0_3", - "CLBLM_SE4C0" - ], - [ - "BRAM_NE2A0_3", - "CLBLM_NE2A0" - ], - [ - "BRAM_LH6_3", - "CLBLM_LH6" - ], - [ - "BRAM_NE2A1_3", - "CLBLM_NE2A1" - ], - [ - "BRAM_EE4A0_3", - "CLBLM_EE4A0" - ], - [ - "BRAM_SW4A3_3", - "CLBLM_SW4A3" - ], - [ - "BRAM_SE4C3_3", - "CLBLM_SE4C3" - ], - [ - "BRAM_WW4C1_3", - "CLBLM_WW4C1" - ], - [ - "BRAM_LH10_3", - "CLBLM_LH10" - ], - [ - "BRAM_SW4A1_3", - "CLBLM_SW4A1" - ], - [ - "BRAM_WW2END0_3", - "CLBLM_WW2END0" - ], - [ - "BRAM_EL1BEG0_3", - "CLBLM_EL1BEG0" - ], - [ - "BRAM_SW2A1_3", - "CLBLM_SW2A1" - ], - [ - "BRAM_EL1BEG3_3", - "CLBLM_EL1BEG3" - ], - [ - "BRAM_NW4END3_3", - "CLBLM_NW4END3" - ], - [ - "BRAM_WW4END1_3", - "CLBLM_WW4END1" - ], - [ - "BRAM_WL1END0_3", - "CLBLM_WL1END0" - ], - [ - "BRAM_NW4A3_3", - "CLBLM_NW4A3" - ], - [ - "BRAM_SE4BEG1_3", - "CLBLM_SE4BEG1" - ], - [ - "BRAM_ER1BEG1_3", - "CLBLM_ER1BEG1" - ], - [ - "BRAM_SW4A0_3", - "CLBLM_SW4A0" - ], - [ - "BRAM_NE4BEG2_3", - "CLBLM_NE4BEG2" - ], - [ - "BRAM_LH3_3", - "CLBLM_LH3" - ], - [ - "BRAM_EE4BEG0_3", - "CLBLM_EE4BEG0" - ], - [ - "BRAM_SW4END1_3", - "CLBLM_SW4END1" - ], - [ - "BRAM_SE2A2_3", - "CLBLM_SE2A2" - ], - [ - "BRAM_NW4END0_3", - "CLBLM_NW4END0" - ], - [ - "BRAM_EE4C2_3", - "CLBLM_EE4C2" - ], - [ - "BRAM_WW4C2_3", - "CLBLM_WW4C2" - ], - [ - "BRAM_WW4A2_3", - "CLBLM_WW4A2" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "BRAM_L", - "VBRK" - ], - "wire_pairs": [ - [ - "BRAM_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "BRAM_LH1_2", - "VBRK_LH1" - ], - [ - "BRAM_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "BRAM_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "BRAM_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "BRAM_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "BRAM_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "BRAM_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "BRAM_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "BRAM_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "BRAM_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "BRAM_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "BRAM_LH5_2", - "VBRK_LH5" - ], - [ - "BRAM_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "BRAM_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "BRAM_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "BRAM_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "BRAM_LH3_2", - "VBRK_LH3" - ], - [ - "BRAM_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "BRAM_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "BRAM_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "BRAM_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "BRAM_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "BRAM_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "BRAM_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "BRAM_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "BRAM_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "BRAM_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "BRAM_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "BRAM_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "BRAM_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "BRAM_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "BRAM_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "BRAM_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "BRAM_LH12_2", - "VBRK_LH12" - ], - [ - "BRAM_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "BRAM_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "BRAM_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "BRAM_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "BRAM_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "BRAM_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "BRAM_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "BRAM_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "BRAM_LH8_2", - "VBRK_LH8" - ], - [ - "BRAM_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "BRAM_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "BRAM_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "BRAM_LH4_2", - "VBRK_LH4" - ], - [ - "BRAM_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "BRAM_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "BRAM_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "BRAM_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "BRAM_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "BRAM_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "BRAM_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "BRAM_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "BRAM_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "BRAM_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "BRAM_LH9_2", - "VBRK_LH9" - ], - [ - "BRAM_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "BRAM_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "BRAM_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "BRAM_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "BRAM_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "BRAM_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "BRAM_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "BRAM_LH10_2", - "VBRK_LH10" - ], - [ - "BRAM_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "BRAM_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "BRAM_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "BRAM_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "BRAM_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "BRAM_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "BRAM_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "BRAM_LH11_2", - "VBRK_LH11" - ], - [ - "BRAM_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "BRAM_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "BRAM_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "BRAM_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "BRAM_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "BRAM_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "BRAM_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "BRAM_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "BRAM_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "BRAM_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "BRAM_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "BRAM_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "BRAM_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "BRAM_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "BRAM_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "BRAM_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "BRAM_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "BRAM_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "BRAM_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "BRAM_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "BRAM_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "BRAM_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "BRAM_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "BRAM_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "BRAM_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "BRAM_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "BRAM_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "BRAM_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "BRAM_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "BRAM_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "BRAM_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "BRAM_LH2_2", - "VBRK_LH2" - ], - [ - "BRAM_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "BRAM_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "BRAM_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "BRAM_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "BRAM_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "BRAM_NE4C1_2", - "VBRK_NE4C1" - ], - [ - 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"VBRK_WW2END2" - ], - [ - "CLK_HROW_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_LH8_3", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_LH1_3", - "VBRK_LH1" - ], - [ - "CLK_HROW_WW4C1_3", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH11_3", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH10_3", - "VBRK_LH10" - ], - [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_LH9_3", - "VBRK_LH9" - ], - [ - "CLK_HROW_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_SE2A2_3", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_LH6_3", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_LH7_3", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SW2A0_3", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH2_3", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW4C2_3", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_LH5_3", - "VBRK_LH5" - ], - [ - "CLK_HROW_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_LH4_3", - "VBRK_LH4" - ], - [ - "CLK_HROW_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WL1END2_3", - "VBRK_WL1END2" - ] - ] - }, - { - "grid_deltas": [ - -1, - -1 - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_BUFG_REBUF_WW2A3_1", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_BUFG_REBUF_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_BUFG_REBUF_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_BUFG_REBUF_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_REBUF_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_BUFG_REBUF_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_BUFG_REBUF_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_BUFG_REBUF_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_BUFG_REBUF_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_BUFG_REBUF_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_BUFG_REBUF_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_BUFG_REBUF_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_BUFG_REBUF_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_REBUF_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_BUFG_REBUF_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_BUFG_REBUF_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_BUFG_REBUF_MONITOR_N_1", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_BUFG_REBUF_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_BUFG_REBUF_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_BUFG_REBUF_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_BUFG_REBUF_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_BUFG_REBUF_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_BUFG_REBUF_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_BUFG_REBUF_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_BUFG_REBUF_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_BUFG_REBUF_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_BUFG_REBUF_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_REBUF_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_BUFG_REBUF_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_BUFG_REBUF_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_BUFG_REBUF_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_BUFG_REBUF_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_BUFG_REBUF_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_BUFG_REBUF_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_REBUF_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_BUFG_REBUF_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_REBUF_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_BUFG_REBUF_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_BUFG_REBUF_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_BUFG_REBUF_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_BUFG_REBUF_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_BUFG_REBUF_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_BUFG_REBUF_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_REBUF_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_BUFG_REBUF_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_BUFG_REBUF_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_BUFG_REBUF_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_REBUF_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_BUFG_REBUF_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_BUFG_REBUF_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_BUFG_REBUF_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_BUFG_REBUF_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_REBUF_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_BUFG_REBUF_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_BUFG_REBUF_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_BUFG_REBUF_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_BUFG_REBUF_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_BUFG_REBUF_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_BUFG_REBUF_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_BUFG_REBUF_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_BUFG_REBUF_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_BUFG_REBUF_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_BUFG_REBUF_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_BUFG_REBUF_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_BUFG_REBUF_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_BUFG_REBUF_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_BUFG_REBUF_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_BUFG_REBUF_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_BUFG_REBUF_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_BUFG_REBUF_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_BUFG_REBUF_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_BUFG_REBUF_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_REBUF_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_BUFG_REBUF_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_BUFG_REBUF_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_BUFG_REBUF_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_BUFG_REBUF_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_BUFG_REBUF_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_BUFG_REBUF_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - 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- ], - [ - "BRAM_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "BRAM_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "BRAM_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "BRAM_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "BRAM_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "BRAM_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "BRAM_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "BRAM_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "BRAM_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "BRAM_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "BRAM_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "BRAM_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "BRAM_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "BRAM_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "BRAM_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "BRAM_LH11_1", - "VBRK_LH11" - ], - [ - "BRAM_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "BRAM_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "BRAM_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "BRAM_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "BRAM_LH6_1", - "VBRK_LH6" - ], - [ - "BRAM_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "BRAM_LH5_1", - "VBRK_LH5" - ], - [ - "BRAM_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "BRAM_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "BRAM_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "BRAM_WW4B1_1", - "VBRK_WW4B1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -3 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_WW2A0_6", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_NW4END1_6", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SE4C0_6", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_IMUX16_6", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX19_6", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_NE4C3_6", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX27_6", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_NE4C0_6", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_SW4END0_6", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_SE4C3_6", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_WW4C1_6", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_FAN4_6", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_WW4END1_6", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_IMUX9_6", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_NW2A3_6", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SW4END1_6", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_IMUX44_6", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_IMUX34_6", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_EE4B2_6", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NE2A0_6", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_SE2A0_6", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_LH9_6", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NW4A1_6", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_SW2A3_6", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_IMUX21_6", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_WW2END1_6", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_IMUX0_6", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_NW4A3_6", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_SE4C1_6", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_WL1END0_6", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_NE4BEG0_6", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_SE4C2_6", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_LH10_6", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_NW2A1_6", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE4C2_6", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WW4C0_6", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_IMUX42_6", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_BYP6_6", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_NW4END3_6", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_WW4C2_6", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW4A2_6", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_EE4B0_6", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_ER1BEG3_6", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_BYP5_6", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_MONITOR_P_6", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_BYP2_6", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE2A1_6", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_IMUX39_6", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_WL1END1_6", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_NE4BEG1_6", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_IMUX33_6", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_EL1BEG3_6", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_WW4A3_6", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_SW4A0_6", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_SE2A2_6", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW4A2_6", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_LH7_6", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_WW2A1_6", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_EE4C1_6", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_FAN3_6", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_WW4C3_6", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_IMUX31_6", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_IMUX28_6", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_NW4A0_6", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX12_6", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_MONITOR_N_6", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_IMUX38_6", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_WL1END3_6", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_EE4BEG2_6", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_IMUX17_6", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_SE2A1_6", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_NE4BEG2_6", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SE2A3_6", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_LH1_6", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_FAN7_6", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_EE2BEG3_6", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_IMUX2_6", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_IMUX22_6", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_BYP7_6", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_EE4BEG3_6", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_WW4B2_6", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EL1BEG1_6", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX10_6", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_IMUX15_6", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_IMUX37_6", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_CTRL0_6", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_LH2_6", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_IMUX8_6", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_IMUX13_6", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_ER1BEG1_6", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4END3_6", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_ER1BEG2_6", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_IMUX24_6", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX35_6", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX26_6", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_SE4BEG1_6", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_CLK1_6", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_EE4A0_6", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_IMUX4_6", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_FAN2_6", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_IMUX45_6", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SW2A1_6", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_BYP4_6", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_EE2BEG1_6", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_EE2A0_6", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE2A2_6", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_WR1END2_6", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_FAN0_6", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX14_6", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_NW4END2_6", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_LH12_6", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_SW2A2_6", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_SE4BEG2_6", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_EE4C3_6", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_BYP1_6", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_IMUX47_6", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_IMUX36_6", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4B3_6", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_SW4A1_6", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_SE4BEG3_6", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_WW4B3_6", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_SW4END3_6", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WL1END2_6", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_NW4A2_6", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_IMUX23_6", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_LH8_6", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_EE2A1_6", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_EE2A3_6", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX5_6", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX25_6", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EE2BEG2_6", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_LH11_6", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_WW2END3_6", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW2END2_6", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_ER1BEG0_6", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_WW4A0_6", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NW2A0_6", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_FAN5_6", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_CTRL1_6", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX18_6", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_FAN6_6", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_NE4C2_6", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_SE4BEG0_6", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_NW2A2_6", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_LH4_6", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_FAN1_6", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_WW2A2_6", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_WW2A3_6", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_NE4C1_6", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_EE4B1_6", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_EL1BEG2_6", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX32_6", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX7_6", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WR1END1_6", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_LH5_6", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NE2A2_6", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_SW4END2_6", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_IMUX43_6", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_LH3_6", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_WW2END0_6", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_IMUX46_6", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_NE4BEG3_6", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_WR1END3_6", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_IMUX6_6", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_WW4B1_6", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WR1END0_6", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE4BEG0_6", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_IMUX20_6", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_IMUX30_6", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_EE4BEG1_6", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EL1BEG0_6", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_IMUX11_6", - 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"INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_BUFG_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_BUFG_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_BUFG_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_BUFG_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_BUFG_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_BUFG_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_MONITOR_P_1", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_BUFG_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_BUFG_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_1", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_BUFG_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_BUFG_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_BUFG_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_1", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_BUFG_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_BUFG_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_BUFG_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_1", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_BUFG_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_BUFG_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_BUFG_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_BUFG_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_FEEDTHRU_1", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_VBRK_MUX_CLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ] - ] - }, - { - "grid_deltas": [ - 1, - 2 - ], - "tile_types": [ - "CMT_FIFO_R", - "CMT_TOP_R_UPPER_B" - ], - "wire_pairs": [ - [ - "CMT_FIFO_EL1BEG3_6", - "CMT_TOP_EL1BEG3_6" - ], - [ - "CMT_FIFO_NW4END2_2", - "CMT_TOP_NW4END2_2" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_6" - ], - [ - "CMT_FIFO_L_IMUX28_3", - "CMT_TOP_IMUX28_3" - ], - [ - "CMT_FIFO_WW2A3_2", - "CMT_TOP_WW2A3_2" - ], - [ - "CMT_FIFO_EE4C0_11", - "CMT_TOP_EE4C0_11" - ], - [ - "CMT_FIFO_EL1BEG1_2", - "CMT_TOP_EL1BEG1_2" - ], - [ - "CMT_FIFO_EL1BEG2_8", - "CMT_TOP_EL1BEG2_8" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_10" - ], - [ - "CMT_FIFO_L_IMUX39_10", - "CMT_TOP_IMUX39_10" - ], - [ - "CMT_FIFO_SW2A0_0", - "CMT_TOP_SW2A0_0" - ], - [ - "CMT_FIFO_SE2A3_3", - "CMT_TOP_SE2A3_3" - ], - [ - "CMT_FIFO_EE2BEG0_2", - "CMT_TOP_EE2BEG0_2" - ], - [ - "CMT_FIFO_L_IMUX13_9", - "CMT_TOP_IMUX13_9" - ], - [ - "CMT_FIFO_SE4BEG0_9", - "CMT_TOP_SE4BEG0_9" - ], - [ - "CMT_FIFO_L_IMUX27_9", - "CMT_TOP_IMUX27_9" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_5" - ], - [ - "CMT_FIFO_SE2A0_10", - "CMT_TOP_SE2A0_10" - ], - [ - "CMT_FIFO_NW2A3_9", - "CMT_TOP_NW2A3_9" - ], - [ - "CMT_FIFO_L_IMUX23_2", - "CMT_TOP_IMUX23_2" - ], - [ - "CMT_FIFO_SW4A3_7", - "CMT_TOP_SW4A3_7" - ], - [ - "CMT_FIFO_L_FAN2_7", - "CMT_TOP_FAN2_7" - ], - [ - "CMT_FIFO_L_BYP5_1", - "CMT_TOP_BYP5_1" - ], - [ - "CMT_FIFO_EE2A0_4", - "CMT_TOP_EE2A0_4" - ], - [ - "CMT_FIFO_LH2_9", - "CMT_TOP_LH2_9" - ], - [ - "CMT_FIFO_EE4BEG3_0", - "CMT_TOP_EE4BEG3_0" - ], - [ - "CMT_FIFO_WL1END2_7", - "CMT_TOP_WL1END2_7" - ], - [ - "CMT_FIFO_L_IMUX4_10", - "CMT_TOP_IMUX4_10" - ], - [ - "CMT_FIFO_NE4C2_2", - "CMT_TOP_NE4C2_2" - ], - [ - "CMT_FIFO_WW4END1_7", - "CMT_TOP_WW4END1_7" - ], - [ - "CMT_FIFO_L_IMUX6_9", - "CMT_TOP_IMUX6_9" - ], - [ - "CMT_FIFO_L_IMUX35_7", - "CMT_TOP_IMUX35_7" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_11" - ], - [ - "CMT_FIFO_L_FAN7_1", - "CMT_TOP_FAN7_1" - ], - [ - "CMT_FIFO_WR1END0_2", - "CMT_TOP_WR1END0_2" - ], - [ - "CMT_FIFO_LH12_1", - "CMT_TOP_LH12_1" - ], - [ - "CMT_FIFO_WR1END0_10", - "CMT_TOP_WR1END0_10" - ], - [ - "CMT_FIFO_WW4B2_8", - "CMT_TOP_WW4B2_8" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_3" - ], - [ - "CMT_FIFO_L_IMUX31_7", - "CMT_TOP_IMUX31_7" - ], - [ - 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"INT_INTERFACE_LOGIC_OUTS_L_B17", - "BRAM_LOGIC_OUTS_B17_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX22", - "BRAM_IMUX22_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "BRAM_LOGIC_OUTS_B1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX45", - "BRAM_IMUX45_3" - ], - [ - "INT_INTERFACE_SE4BEG1", - "BRAM_SE4BEG1_3" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_3" - ], - [ - "INT_INTERFACE_SE4BEG3", - "BRAM_SE4BEG3_3" - ], - [ - "INT_INTERFACE_CTRL1", - "BRAM_CTRL1_3" - ], - [ - "INT_INTERFACE_NE2A1", - "BRAM_NE2A1_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX36", - "BRAM_IMUX36_UTURN_3" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "BRAM_LOGIC_OUTS_B23_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "BRAM_IMUX37_3" - ], - [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX11", - "BRAM_IMUX11_UTURN_3" - ], - [ - "INT_INTERFACE_WR1END1", - "BRAM_WR1END1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX20", - "BRAM_IMUX20_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "BRAM_LOGIC_OUTS_B4_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX32", - "BRAM_IMUX32_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "BRAM_IMUX17_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX15", - "BRAM_IMUX15_UTURN_3" - ], - [ - "INT_INTERFACE_WW2A1", - "BRAM_WW2A1_3" - ], - [ - "INT_INTERFACE_EE2BEG0", - "BRAM_EE2BEG0_3" - ], - [ - "INT_INTERFACE_LH11", - "BRAM_LH11_3" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX24", - "BRAM_IMUX24_UTURN_3" - ], - [ - "INT_INTERFACE_SE4BEG0", - "BRAM_SE4BEG0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX12", - "BRAM_IMUX12_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "BRAM_LOGIC_OUTS_B5_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX25", - "BRAM_IMUX25_UTURN_3" - ], - [ - "INT_INTERFACE_FAN4", - "BRAM_FAN4_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX28", - "BRAM_IMUX28_UTURN_3" - ], - [ - "INT_INTERFACE_NW4END0", - "BRAM_NW4END0_3" - ], - [ - "INT_INTERFACE_NE4BEG2", - "BRAM_NE4BEG2_3" - ], - [ - "INT_INTERFACE_WW4A1", - "BRAM_WW4A1_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX26", - "BRAM_IMUX26_UTURN_3" - ], - [ - "INT_INTERFACE_WW2A2", - "BRAM_WW2A2_3" - ], - [ - "INT_INTERFACE_FAN6", - "BRAM_FAN6_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "BRAM_LOGIC_OUTS_B18_3" - ], - [ - "INT_INTERFACE_SE2A3", - "BRAM_SE2A3_3" - ], - [ - "INT_INTERFACE_NW4END2", - "BRAM_NW4END2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX39", - "BRAM_IMUX39_UTURN_3" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_3" - ], - [ - "INT_INTERFACE_BYP4", - "BRAM_BYP4_3" - ], - [ - "INT_INTERFACE_WW2END1", - "BRAM_WW2END1_3" - ], - [ - "INT_INTERFACE_LH7", - "BRAM_LH7_3" - ] - ] - }, - { - "grid_deltas": [ - 1, - -2 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_LH2_2", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_LH3_2", - "VBRK_LH3" - ], - [ - "CLK_HROW_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_LH4_2", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_LH5_2", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE4C0_2", - "VBRK_EE4C0" - ], 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"CLK_HROW_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_LH9_2", - "VBRK_LH9" - ], - [ - "CLK_HROW_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH1_2", - "VBRK_LH1" - ], - [ - "CLK_HROW_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_LH10_2", - "VBRK_LH10" - ], - [ - "CLK_HROW_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH6_2", - "VBRK_LH6" - ], - [ - "CLK_HROW_LH8_2", - "VBRK_LH8" - ], - [ - "CLK_HROW_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH11_2", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_LH12_2", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_SW4END2_2", - "VBRK_SW4END2" - ] - ] - }, - { - "grid_deltas": [ - 1, - -3 - ], - "tile_types": [ - "MONITOR_MID_FUJI2", - "VFRAME" - ], - "wire_pairs": [ - [ - "MONITOR_SE4BEG3_3", - "VFRAME_SE4BEG3" - ], - [ - "MONITOR_FAN3_3", - "VFRAME_FAN3" - ], - [ - "MONITOR_IMUX29_3", - "VFRAME_IMUX29" - ], - [ - "MONITOR_LH1_3", - "VFRAME_LH1" - ], - [ - "MONITOR_LH5_3", - "VFRAME_LH5" - ], - [ - "MONITOR_EE4BEG0_3", - "VFRAME_EE4BEG0" - ], - [ - "MONITOR_WW4END0_3", - "VFRAME_WW4END0" - ], - [ - "MONITOR_EE4BEG2_3", - "VFRAME_EE4BEG2" - ], - [ - "MONITOR_EE4A2_3", - "VFRAME_EE4A2" - ], - [ - "MONITOR_IMUX32_3", - "VFRAME_IMUX32" - ], - [ - "MONITOR_EL1BEG3_3", - "VFRAME_EL1BEG3" - ], - [ - "MONITOR_NW4END1_3", - "VFRAME_NW4END1" - ], - [ - "MONITOR_IMUX30_3", - "VFRAME_IMUX30" - ], - [ - "MONITOR_IMUX42_3", - "VFRAME_IMUX42" - ], - [ - "MONITOR_BYP4_3", - "VFRAME_BYP4" - ], - [ - "MONITOR_NE4C2_3", - "VFRAME_NE4C2" - ], - [ - "MONITOR_EE2BEG1_3", - "VFRAME_EE2BEG1" - ], - [ - "MONITOR_EE4BEG1_3", - "VFRAME_EE4BEG1" - ], - [ - "MONITOR_CLK0_3", - "VFRAME_CLK0" - ], - [ - "MONITOR_EE2BEG3_3", - "VFRAME_EE2BEG3" - ], - [ - "MONITOR_SW2A3_3", - "VFRAME_SW2A3" - ], - [ - "MONITOR_NW2A2_3", - "VFRAME_NW2A2" - ], - [ - "MONITOR_EE4A3_3", - "VFRAME_EE4A3" - ], - [ - "MONITOR_IMUX5_3", - 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"INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_BYP7_5", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_IMUX31_5", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_SW4A0_5", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NW4A3_5", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_IMUX17_5", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_EE4B1_5", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_WW2A3_5", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_NW4A0_5", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_SE2A3_5", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_NE4BEG3_5", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_WW4A0_5", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NW2A2_5", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_IMUX26_5", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WW4C3_5", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_IMUX3_5", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_WW2END0_5", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH11_5", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE4C0_5", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EL1BEG1_5", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_FAN0_5", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_CTRL0_5", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_ER1BEG0_5", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_NW2A3_5", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SW4END1_5", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_FAN3_5", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX4_5", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_SW4END2_5", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE4A1_5", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_IMUX36_5", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_SW2A3_5", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_WR1END3_5", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_FAN2_5", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_IMUX38_5", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX9_5", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_WW4END2_5", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_CTRL1_5", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX37_5", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_LH12_5", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WW2END3_5", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_IMUX7_5", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_NW4A1_5", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX16_5", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX13_5", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_WW2A2_5", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_NW2A1_5", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE2BEG2_5", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX32_5", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX27_5", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_WL1END0_5", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_SW2A0_5", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_IMUX35_5", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX0_5", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_SW4END0_5", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_IMUX12_5", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_IMUX47_5", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_IMUX25_5", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_SW4END3_5", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_IMUX39_5", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_NE4BEG1_5", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_IMUX21_5", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX28_5", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_WW4A3_5", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_WW2A0_5", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_EE4C1_5", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_SE4BEG2_5", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_BYP4_5", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_ER1BEG1_5", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4B0_5", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_IMUX18_5", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_SE4C3_5", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE2BEG3_5", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_BYP1_5", - "INT_INTERFACE_BYP1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_NW4A0_4", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_NE4BEG0_4", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_PMV_SE4BEG3_4", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_WW4END0_4", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_PMV_WW4A3_4", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_PMV_EE2BEG0_4", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_EL1BEG0_4", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_PMV_EE4A1_4", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_PMV_IMUX24_4", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_PMV_IMUX37_4", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_PMV_EE4BEG2_4", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_FAN6_4", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_PMV_LH7_4", - "INT_INTERFACE_LH7" - ], - [ - "CLK_PMV_LH2_4", - "INT_INTERFACE_LH2" - ], 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"INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_BYP0_4", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_PMV_IMUX16_4", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_EE4B3_4", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_NE2A3_4", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_PMV_CLK0_4", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_PMV_WW4B0_4", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_PMV_WW4C0_4", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_PMV_IMUX34_4", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_EE4C0_4", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_NW4A1_4", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_PMV_EE4C3_4", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_PMV_IMUX21_4", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_WW4A2_4", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_EE4C2_4", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_PMV_NW4END2_4", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_EL1BEG3_4", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_PMV_NE2A0_4", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_FAN3_4", - "INT_INTERFACE_FAN3" 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"CLK_PMV_EL1BEG1_4", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_IMUX38_4", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_PMV_BYP1_4", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_NE2A1_4", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_WW2A2_4", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_PMV_SW2A2_4", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_PMV_WL1END2_4", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_PMV_IMUX20_4", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_WW2A0_4", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_WW2END1_4", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_PMV_FAN5_4", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_WR1END2_4", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_IMUX47_4", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_WW4END3_4", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_PMV_EE2A1_4", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_NW4A2_4", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_PMV_WW2END2_4", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_PMV_IMUX10_4", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_PMV_IMUX9_4", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_SE4C1_4", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_PMV_NW2A1_4", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_NE4C0_4", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_PMV_SW2A0_4", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_PMV_LH6_4", - "INT_INTERFACE_LH6" - ], - [ - "CLK_PMV_IMUX6_4", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_PMV_IMUX33_4", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_IMUX35_4", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_PMV_WL1END1_4", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_PMV_SW4END1_4", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_PMV_SW4A2_4", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_EE4A2_4", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_WW4A1_4", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_PMV_IMUX28_4", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_PMV_EE2BEG1_4", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_FAN1_4", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_IMUX29_4", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_PMV_IMUX36_4", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_PMV_LH10_4", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_LH4_4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_PMV_WW4C1_4", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_PMV_EE4B2_4", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_ER1BEG0_4", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_PMV_IMUX44_4", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_PMV_IMUX32_4", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_PMV_IMUX39_4", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_PMV_NE4BEG1_4", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_PMV_BYP3_4", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_IMUX7_4", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_SW4END2_4", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_PMV_IMUX3_4", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_NE4C3_4", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_PMV_SE2A2_4", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_NW2A3_4", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_PMV_LH11_4", - "INT_INTERFACE_LH11" - ], - [ - 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"INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_2" - ], - [ - "INT_INTERFACE_NE2A0", - "BRAM_NE2A0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B15", - "BRAM_LOGIC_OUTS_B15_2" - ], - [ - "INT_INTERFACE_SE4C2", - "BRAM_SE4C2_2" - ], - [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B21", - "BRAM_LOGIC_OUTS_B21_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "BRAM_IMUX37_2" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX27", - "BRAM_IMUX27_2" - ], - [ - "INT_INTERFACE_SW4END2", - "BRAM_SW4END2_2" - ], - [ - "INT_INTERFACE_EE4A3", - "BRAM_EE4A3_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B3", - "BRAM_LOGIC_OUTS_B3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX22", - "BRAM_IMUX22_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX19", - "BRAM_IMUX19_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX26", - "BRAM_IMUX26_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX18", - "BRAM_IMUX18_2" - ], - [ - "INT_INTERFACE_EE4C2", - "BRAM_EE4C2_2" - ], - [ - "INT_INTERFACE_SE2A2", - "BRAM_SE2A2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX43", - "BRAM_IMUX43_2" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX35", - "BRAM_IMUX35_UTURN_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B4", - "BRAM_LOGIC_OUTS_B4_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX18", - "BRAM_IMUX18_UTURN_2" - ], - [ - "INT_INTERFACE_FAN7", - "BRAM_FAN7_2" - ], - [ - "INT_INTERFACE_EL1BEG0", - "BRAM_EL1BEG0_2" - ], - [ - "INT_INTERFACE_NE4C2", - "BRAM_NE4C2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "BRAM_IMUX4_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B2", - "BRAM_LOGIC_OUTS_B2_2" - ], - [ - "INT_INTERFACE_NW2A2", - "BRAM_NW2A2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX3", - "BRAM_IMUX3_UTURN_2" - ], - [ - "INT_INTERFACE_NE4C0", - "BRAM_NE4C0_2" - ], - [ - "INT_INTERFACE_MONITOR_N", - "BRAM_MONITOR_N_2" - ], - [ - "INT_INTERFACE_EE2BEG1", - "BRAM_EE2BEG1_2" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_2" - ], - [ - "INT_INTERFACE_LH5", - "BRAM_LH5_2" - ], - [ - "INT_INTERFACE_ER1BEG2", - "BRAM_ER1BEG2_2" - ], - [ - "INT_INTERFACE_CTRL0", - "BRAM_CTRL0_2" - ], - [ - "INT_INTERFACE_SW4A0", - "BRAM_SW4A0_2" - ], - [ - "INT_INTERFACE_ER1BEG3", - "BRAM_ER1BEG3_2" - ], - [ - "INT_INTERFACE_MONITOR_P", - "BRAM_MONITOR_P_2" - ], - [ - "INT_INTERFACE_CTRL1", - "BRAM_CTRL1_2" - ], - [ - "INT_INTERFACE_SW4END0", - "BRAM_SW4END0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX36", - "BRAM_IMUX36_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX34", - "BRAM_IMUX34_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX31", - "BRAM_IMUX31_UTURN_2" - ], - [ - "INT_INTERFACE_WW2A2", - "BRAM_WW2A2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX19", - "BRAM_IMUX19_2" - ], - [ - "INT_INTERFACE_WW4C2", - "BRAM_WW4C2_2" - ], - [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B23", - "BRAM_LOGIC_OUTS_B23_2" - ], - [ - "INT_INTERFACE_EE2BEG0", - "BRAM_EE2BEG0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B5", - "BRAM_LOGIC_OUTS_B5_2" - ], - [ - "INT_INTERFACE_NW4A1", - "BRAM_NW4A1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "BRAM_IMUX44_2" - ], - [ - "INT_INTERFACE_FAN5", - "BRAM_FAN5_2" - ], - [ - "INT_INTERFACE_WL1END2", - "BRAM_WL1END2_2" - ], - [ - "INT_INTERFACE_EE4C0", - "BRAM_EE4C0_2" - ], - [ - "INT_INTERFACE_NE4BEG0", - "BRAM_NE4BEG0_2" - ], - [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX38", - "BRAM_IMUX38_UTURN_2" - ], - [ - "INT_INTERFACE_BYP3", - "BRAM_BYP3_2" - ], - [ - "INT_INTERFACE_WW2A3", - "BRAM_WW2A3_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B9", - "BRAM_LOGIC_OUTS_B9_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX34", - "BRAM_IMUX34_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX30", - "BRAM_IMUX30_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX37", - "BRAM_IMUX37_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX24", - "BRAM_IMUX24_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX14", - "BRAM_IMUX14_UTURN_2" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_2" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_2" - ], - [ - "INT_INTERFACE_WW4C0", - "BRAM_WW4C0_2" - ], - [ - "INT_INTERFACE_LH11", - "BRAM_LH11_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "BRAM_IMUX5_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_2" - ], - [ - "INT_INTERFACE_WW2A0", - "BRAM_WW2A0_2" - ], - [ - "INT_INTERFACE_WW2END3", - "BRAM_WW2END3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX39", - "BRAM_IMUX39_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B0", - "BRAM_LOGIC_OUTS_B0_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX26", - "BRAM_IMUX26_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX9", - "BRAM_IMUX9_UTURN_2" - ], - [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_2" - ], - [ - "INT_INTERFACE_EE2BEG3", - "BRAM_EE2BEG3_2" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX33", - "BRAM_IMUX33_2" - ], - [ - "INT_INTERFACE_LH4", - "BRAM_LH4_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B6", - "BRAM_LOGIC_OUTS_B6_2" - ], - [ - "INT_INTERFACE_WW4B1", - "BRAM_WW4B1_2" - ], - [ - "INT_INTERFACE_WL1END3", - "BRAM_WL1END3_2" - ], - [ - "INT_INTERFACE_CLK0", - "BRAM_CLK0_2" - ], - [ - "INT_INTERFACE_EE4A0", - "BRAM_EE4A0_2" - ], - [ - "INT_INTERFACE_WW2END2", - "BRAM_WW2END2_2" - ], - [ - "INT_INTERFACE_NW2A0", - "BRAM_NW2A0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX35", - "BRAM_IMUX35_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX36", - "BRAM_IMUX36_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX46", - "BRAM_IMUX46_UTURN_2" - ], - [ - "INT_INTERFACE_LH9", - "BRAM_LH9_2" - ], - [ - "INT_INTERFACE_WW2END1", - "BRAM_WW2END1_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B22", - "BRAM_LOGIC_OUTS_B22_2" - ], - [ - "INT_INTERFACE_EE4C1", - "BRAM_EE4C1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "BRAM_IMUX6_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX16", - "BRAM_IMUX16_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX5", - "BRAM_IMUX5_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX39", - "BRAM_IMUX39_UTURN_2" - ], - [ - "INT_INTERFACE_SW2A3", - "BRAM_SW2A3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX24", - "BRAM_IMUX24_2" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX45", - "BRAM_IMUX45_UTURN_2" - ], - [ - "INT_INTERFACE_NW4A0", - "BRAM_NW4A0_2" - ], - [ - "INT_INTERFACE_LH6", - "BRAM_LH6_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX21", - "BRAM_IMUX21_UTURN_2" - ], - [ - "INT_INTERFACE_NE4BEG2", - "BRAM_NE4BEG2_2" - ], - [ - "INT_INTERFACE_EE4B2", - "BRAM_EE4B2_2" - ], - [ - "INT_INTERFACE_EE4C3", - "BRAM_EE4C3_2" - ], - [ - "INT_INTERFACE_NE4C1", - "BRAM_NE4C1_2" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_DSP_L", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "HCLK_DSP_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_DSP_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_DSP_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_DSP_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_DSP_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_DSP_CK_IN9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_DSP_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_DSP_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_DSP_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_DSP_CK_IN0", - "HCLK_VBRK_MUX_CLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_DSP_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_DSP_CK_IN3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_DSP_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_DSP_CK_IN2", - "HCLK_VBRK_MUX_CLK2" + "IOI_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1_1" ] ] }, @@ -215006,29 +473470,49 @@ "IOI_DCI_TSTRST0" ], [ - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK4" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_RCLK_FORIO3" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO2" + "IOI_IMUX_RC0", + "IOI_IMUX_RC2" ], [ "IOI_IMUX_RC1", "IOI_IMUX_RC3" ], [ - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO0" + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" ], [ "IOI_LEAF_GCLK3", "IOI_LEAF_GCLK3" ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ], [ "IOI_LEAF_GCLK5", "IOI_LEAF_GCLK5" @@ -215038,40024 +473522,276 @@ "IOI_RCLK_DIV_CE2_1" ], [ - "IOI_IOCLK2", - "IOI_IOCLK2" + "IOI_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3_1" ], [ - "IOI_IOCLK1", - "IOI_IOCLK1" + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" ], [ - "IOI_IOCLK0", - "IOI_IOCLK0" + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" ], [ - "IOI_IOCLK3", - "IOI_IOCLK3" + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" ], [ "IOI_TBYTEIN", "IOI_TBYTEIN" ], - [ - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1" - ], - [ - "RIOI_I2GCLK_TOP0", - "RIOI_I2GCLK_TOP1" - ], - [ - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK0" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO1" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK2" - ], [ "RIOI_I2GCLK_BOT1", "RIOI_I2GCLK_TOP0" ], [ - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK1" - ], - [ - "IOI_IMUX_RC0", - "IOI_IMUX_RC2" + "RIOI_I2GCLK_TOP0", + "RIOI_I2GCLK_TOP1" ] ] }, { "grid_deltas": [ - 1, - 2 - ], - "tile_types": [ - "INT_FEEDTHRU_2", - "MONITOR_TOP_FUJI2" - ], - "wire_pairs": [ - [ - "INT_FEEDTHRU_2_NW4A2", - "MONITOR_NW4A2_2" - ], - [ - "INT_FEEDTHRU_2_WW4END1", - "MONITOR_WW4END1_2" - ], - [ - "INT_FEEDTHRU_2_NE4C0", - "MONITOR_NE4C0_2" - ], - [ - "INT_FEEDTHRU_2_SW4END3", - "MONITOR_SW4END3_2" - ], - [ - "INT_FEEDTHRU_2_SE2A1", - "MONITOR_SE2A1_2" - ], - [ - "INT_FEEDTHRU_2_WR1END3", - "MONITOR_WR1END3_2" - ], - [ - "INT_FEEDTHRU_2_WW4END2", - "MONITOR_WW4END2_2" - ], - [ - "INT_FEEDTHRU_2_SE4C0", - "MONITOR_SE4C0_2" - ], - [ - "INT_FEEDTHRU_2_MONITOR_P", - "MONITOR_HORIZ_VAUXP0" - ], - [ - "INT_FEEDTHRU_2_EL1BEG1", - "MONITOR_EL1BEG1_2" - ], - [ - "INT_FEEDTHRU_2_EE4A2", - "MONITOR_EE4A2_2" - ], - [ - "INT_FEEDTHRU_2_EE4B0", - "MONITOR_EE4B0_2" - ], - [ - "INT_FEEDTHRU_2_WW2A1", - "MONITOR_WW2A1_2" - ], - [ - "INT_FEEDTHRU_2_NW4END1", - "MONITOR_NW4END1_2" - ], - [ - "INT_FEEDTHRU_2_WW2END1", - "MONITOR_WW2END1_2" - ], - [ - "INT_FEEDTHRU_2_WR1END2", - "MONITOR_WR1END2_2" - ], - [ - "INT_FEEDTHRU_2_WL1END3", - "MONITOR_WL1END3_2" - ], - [ - "INT_FEEDTHRU_2_LH1", - "MONITOR_LH1_2" - ], - [ - "INT_FEEDTHRU_2_EE4A0", - "MONITOR_EE4A0_2" - ], - [ - "INT_FEEDTHRU_2_NE2A2", - "MONITOR_NE2A2_2" - ], - [ - "INT_FEEDTHRU_2_EE4BEG1", - "MONITOR_EE4BEG1_2" - ], - [ - "INT_FEEDTHRU_2_NW4A0", - "MONITOR_NW4A0_2" - ], - [ - "INT_FEEDTHRU_2_NE4C2", - "MONITOR_NE4C2_2" - ], - [ - "INT_FEEDTHRU_2_WL1END1", - "MONITOR_WL1END1_2" - ], - [ - "INT_FEEDTHRU_2_EE4BEG3", - "MONITOR_EE4BEG3_2" - ], - [ - "INT_FEEDTHRU_2_SW2A0", - "MONITOR_SW2A0_2" - ], - [ - "INT_FEEDTHRU_2_NW4END3", - "MONITOR_NW4END3_2" - ], - [ - "INT_FEEDTHRU_2_LH12", - "MONITOR_LH12_2" - ], - [ - "INT_FEEDTHRU_2_EE4B1", - "MONITOR_EE4B1_2" - ], - [ - "INT_FEEDTHRU_2_WL1END2", - "MONITOR_WL1END2_2" - ], - [ - "INT_FEEDTHRU_2_EE4B3", - "MONITOR_EE4B3_2" - ], - [ - "INT_FEEDTHRU_2_WR1END0", - "MONITOR_WR1END0_2" - ], - [ - "INT_FEEDTHRU_2_NW2A3", - "MONITOR_NW2A3_2" - ], - [ - "INT_FEEDTHRU_2_WW4C1", - "MONITOR_WW4C1_2" - ], - [ - "INT_FEEDTHRU_2_EE4C0", - "MONITOR_EE4C0_2" - ], - [ - "INT_FEEDTHRU_2_EL1BEG3", - "MONITOR_EL1BEG3_2" - ], - [ - "INT_FEEDTHRU_2_WW4A1", - "MONITOR_WW4A1_2" - ], - [ - "INT_FEEDTHRU_2_WW4C0", - "MONITOR_WW4C0_2" - ], - [ - "INT_FEEDTHRU_2_SE4BEG3", - "MONITOR_SE4BEG3_2" - ], - [ - "INT_FEEDTHRU_2_WW2A3", - "MONITOR_WW2A3_2" - ], - [ - "INT_FEEDTHRU_2_SW2A1", - "MONITOR_SW2A1_2" - ], - [ - "INT_FEEDTHRU_2_EE2BEG2", - "MONITOR_EE2BEG2_2" - ], - [ - "INT_FEEDTHRU_2_WW2END0", - "MONITOR_WW2END0_2" - ], - [ - "INT_FEEDTHRU_2_SE4BEG0", - "MONITOR_SE4BEG0_2" - ], - [ - "INT_FEEDTHRU_2_ER1BEG1", - "MONITOR_ER1BEG1_2" - ], - [ - "INT_FEEDTHRU_2_WW4A0", - "MONITOR_WW4A0_2" - ], - [ - "INT_FEEDTHRU_2_NW4A3", - "MONITOR_NW4A3_2" - ], - [ - "INT_FEEDTHRU_2_EE4C2", - "MONITOR_EE4C2_2" - ], - [ - "INT_FEEDTHRU_2_WW2A2", - "MONITOR_WW2A2_2" - ], - [ - "INT_FEEDTHRU_2_LH3", - "MONITOR_LH3_2" - ], - [ - "INT_FEEDTHRU_2_LH10", - "MONITOR_LH10_2" - ], - [ - "INT_FEEDTHRU_2_WW4END0", - "MONITOR_WW4END0_2" - ], - [ - "INT_FEEDTHRU_2_NE4BEG0", - "MONITOR_NE4BEG0_2" - ], - [ - "INT_FEEDTHRU_2_EE2BEG1", - "MONITOR_EE2BEG1_2" - ], - [ - "INT_FEEDTHRU_2_NE2A3", - "MONITOR_NE2A3_2" - ], - [ - "INT_FEEDTHRU_2_WW4C2", - "MONITOR_WW4C2_2" - ], - [ - "INT_FEEDTHRU_2_SE2A0", - "MONITOR_SE2A0_2" - ], - [ - "INT_FEEDTHRU_2_ER1BEG2", - "MONITOR_ER1BEG2_2" - ], - [ - "INT_FEEDTHRU_2_EE4B2", - "MONITOR_EE4B2_2" - ], - [ - "INT_FEEDTHRU_2_WW2END2", - "MONITOR_WW2END2_2" - ], - [ - "INT_FEEDTHRU_2_WW4A3", - "MONITOR_WW4A3_2" - ], - [ - "INT_FEEDTHRU_2_ER1BEG3", - "MONITOR_ER1BEG3_2" - ], - [ - "INT_FEEDTHRU_2_SW4A3", - "MONITOR_SW4A3_2" - ], - [ - "INT_FEEDTHRU_2_EL1BEG0", - "MONITOR_EL1BEG0_2" - ], - [ - "INT_FEEDTHRU_2_WW4A2", - "MONITOR_WW4A2_2" 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[ - "HCLK_L", - "INT_L" - ], - "wire_pairs": [ - [ - "HCLK_BYP_BOUNCE7", - "BYP_BOUNCE_N3_7" - ], - [ - "HCLK_NN2A1", - "NN2END1" - ], - [ - "HCLK_SE2A3", - "SE2BEG3" - ], - [ - "HCLK_NN6A1", - "NN6B1" - ], - [ - "HCLK_NE6C0", - "NE6D0" - ], - [ - "HCLK_LVB2", - "LVB_L2" - ], - [ - "HCLK_NW6D1", - "NW6E1" - ], - [ - "HCLK_SS6A1", - "SS6BEG1" - ], - [ - "HCLK_WW2END3", - "WW2END_N0_3" - ], - [ - "HCLK_SE6E1", - "SE6D1" - ], - [ - "HCLK_LVB8", - "LVB_L8" - ], - [ - "HCLK_SW6C1", - "SW6B1" - ], - [ - "HCLK_EL1BEG3", - "EL1BEG_N3" - ], - [ - "HCLK_LV6", - "LV_L7" - ], - [ - "HCLK_NN6BEG0", - "NN6A0" - ], - [ - "HCLK_LV13", - "LV_L14" - ], - [ - "HCLK_WL1END3", - "WL1END_N1_3" - ], - [ - "HCLK_LVB3", - "LVB_L3" - ], - [ - "HCLK_NL1BEG2", - "NL1END2" - ], - [ - "HCLK_NE6B0", - "NE6C0" - ], - [ - "HCLK_SS6END3", - "SS6E3" - ], - [ - "HCLK_NW6A3", - "NW6B3" - ], - [ - "HCLK_SE6D0", - "SE6C0" - ], - [ - "HCLK_FAN_BOUNCE_S3_0", - "FAN_BOUNCE0" - ], - [ - "HCLK_NE6A1", - "NE6B1" - ], - [ - "HCLK_SE6D3", - "SE6C3" - ], - [ - "HCLK_SW6B0", - "SW6A0" - ], - [ - "HCLK_NE6C1", - "NE6D1" - ], - [ - "HCLK_NN2A0", - "NN2END0" - ], - [ - "HCLK_SW6B1", - "SW6A1" - ], - [ - "HCLK_BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" - ], - [ - "HCLK_NN6END_S1_0", - "NN6END0" - ], - [ - "HCLK_NW6A2", - "NW6B2" - ], - [ - "HCLK_SW2A3", - "SW2BEG3" - ], - [ - "HCLK_LV17", - "LV_L18" - ], - [ - "HCLK_LV12", - "LV_L13" - ], - [ - "HCLK_NE6A0", - "NE6B0" - ], - [ - "HCLK_LV1", - "LV_L2" - ], - [ - "HCLK_SW6D0", - "SW6C0" - ], - [ - "HCLK_SS6B2", - "SS6A2" - ], - [ - "HCLK_SR1END1", - "SR1BEG1" - ], - [ - "HCLK_SE6B0", - "SE6A0" - ], - [ - "HCLK_NW2A1", - "NW2A1" - ], - [ - "HCLK_LVB10", - "LVB_L10" - ], - [ - "HCLK_NR1BEG2", - "NR1END2" - ], - [ - "HCLK_NE6B1", - "NE6C1" - ], - [ - "HCLK_SS6B1", - "SS6A1" - ], - [ - "HCLK_FAN_BOUNCE_S3_2", - "FAN_BOUNCE2" - ], - [ - "HCLK_LEAF_CLK_B_TOPL3", - "GCLK_L_B9" - ], - [ - "HCLK_NE6D3", - "NE6E3" - ], - [ - "HCLK_SS6C0", - "SS6B0" - ], - [ - "HCLK_NE6D2", - "NE6E2" - ], - [ - "HCLK_NW6B2", - "NW6C2" - ], - [ - "HCLK_SS6B0", - "SS6A0" - ], - [ - "HCLK_LVB5", - "LVB_L5" - ], - [ - "HCLK_SE6B1", - "SE6A1" - ], - [ - "HCLK_SS6B3", - "SS6A3" - ], - [ - "HCLK_NN6C3", - "NN6D3" - ], - [ - "HCLK_NW6C1", - "NW6D1" - ], - [ - "HCLK_SS6END0", - "SS6E0" - ], - [ - "HCLK_NW6D0", - "NW6E0" - ], - [ - "HCLK_SS6END_N0_3", - "SS6END_N0_3" - ], - [ - "HCLK_SS2A2", - "SS2BEG2" - ], - [ - "HCLK_LVB1", - "LVB_L1" - ], - [ - "HCLK_NW6A0", - "NW6B0" - ], - [ - "HCLK_LV4", - "LV_L5" - ], - [ - "HCLK_LVB12", - "LVB_L12" - ], - [ - "HCLK_WL1BEG3", - "WL1BEG_N3" - ], - [ - "HCLK_ER1BEG_S0", - "ER1BEG0" - ], - [ - "HCLK_LV8", - "LV_L9" - ], - [ - "HCLK_NW6B1", - "NW6C1" - ], - [ - "HCLK_SE2A1", - "SE2BEG1" - ], - [ - "HCLK_LVB7", - "LVB_L7" - ], - [ - "HCLK_SW2END2", - "SW2BEG2" - ], - [ - "HCLK_SS2END_N0_3", - "SS2END_N0_3" - ], - [ - "HCLK_NN2BEG1", - "NN2A1" - ], - [ - "HCLK_SS6E0", - "SS6D0" - ], - [ - "HCLK_SW6END3", - "SW6END_N0_3" - ], - [ - "HCLK_NW2END_S0_0", - "NW2END0" - ], - [ - "HCLK_LV3", - "LV_L4" - ], - [ - "HCLK_SE6E0", - "SE6D0" - ], - [ - "HCLK_SE6C0", - "SE6B0" - ], - [ - "HCLK_SE6E2", - "SE6D2" - ], - [ - "HCLK_SS6D0", - "SS6C0" - ], - [ - "HCLK_LEAF_CLK_B_TOPL2", - "GCLK_L_B8" - ], - [ - "HCLK_NN6E0", - "NN6END0" - ], - [ - "HCLK_LV9", - "LV_L10" - ], - [ - "HCLK_NE6B3", - "NE6C3" - ], - [ - "HCLK_NN2A3", - "NN2END3" - ], - [ - "HCLK_NE6C2", - "NE6D2" - ], - [ - "HCLK_LV15", - "LV_L16" - ], - [ - "HCLK_SS6D1", - "SS6C1" - ], - [ - "HCLK_SS2A1", - "SS2BEG1" - ], - [ - "HCLK_SE6B2", - "SE6A2" - ], - [ - "HCLK_SS6E3", - "SS6D3" - ], - [ - "HCLK_NW2A2", - "NW2A2" - ], - [ - "HCLK_LV7", - "LV_L8" - ], - [ - "HCLK_SS2BEG3", - "SS2BEG3" - ], - [ - "HCLK_SS2END2", - "SS2A2" - ], - [ - "HCLK_LV5", - "LV_L6" - ], - [ - "HCLK_SE6B3", - "SE6A3" - ], - [ - "HCLK_SS6A2", - "SS6BEG2" - ], - [ - "HCLK_SS6A3", - "SS6BEG3" - ], - [ - "HCLK_NE6A3", - "NE6B3" - ], - [ - "HCLK_SR1END_N3_3", - "SR1END_N3_3" - ], - [ - "HCLK_NN6C0", - "NN6D0" - ], - [ - "HCLK_NN6D1", - "NN6E1" - ], - [ - "HCLK_NN6E1", - "NN6END1" - ], - [ - "HCLK_NN6BEG1", - "NN6A1" - ], - [ - "HCLK_NN6A2", - "NN6B2" - ], - [ - "HCLK_NW6D3", - "NW6E3" - ], - [ - "HCLK_NE6A2", - "NE6B2" - ], - [ - "HCLK_SW6D2", - "SW6C2" - ], - [ - "HCLK_SS6END2", - "SS6E2" - ], - [ - "HCLK_SS6C1", - "SS6B1" - ], - [ - "HCLK_LV16", - "LV_L17" - ], - [ - "HCLK_NN6C2", - "NN6D2" - ], - [ - "HCLK_SE6E3", - "SE6D3" - ], - [ - "HCLK_LVB9", - "LVB_L9" - ], - [ - "HCLK_SS6E1", - "SS6D1" - ], - [ - "HCLK_NR1BEG0", - "NR1END0" - ], - [ - "HCLK_SE2A0", - "SE2BEG0" - ], - [ - "HCLK_WW4END_S0_0", - "WW4END0" - ], - [ - "HCLK_NW6END_S0_0", - "NW6END0" - ], - [ - "HCLK_NN2BEG3", - "NN2A3" - ], - [ - "HCLK_NE2BEG2", - "NE2A2" - ], - [ - "HCLK_EL1END_S3_0", - "EL1END0" - ], - [ - "HCLK_NE6B2", - "NE6C2" - ], - [ - "HCLK_NW6B3", - "NW6C3" - ], - [ - "HCLK_NW6C3", - "NW6D3" - ], - [ - "HCLK_NW6C2", - "NW6D2" - ], - [ - "HCLK_SE2A2", - "SE2BEG2" - ], - [ - "HCLK_SL1END0", - "SL1BEG0" - ], - [ - "HCLK_LV14", - "LV_L15" - ], - [ - "HCLK_LVB11", - "LVB_L11" - ], - [ - "HCLK_SL1END1", - "SL1BEG1" - ], - [ - "HCLK_SS6E2", - "SS6D2" - ], - [ - "HCLK_NR1BEG3", - "NR1END3" - ], - [ - "HCLK_SW6E1", - "SW6D1" - ], - [ - "HCLK_NN6A0", - "NN6B0" - ], - [ - "HCLK_NN2A2", - "NN2END2" - ], - [ - "HCLK_NN6D0", - "NN6E0" - ], - [ - "HCLK_LVB4", - "LVB_L4" - ], - [ - "HCLK_WR1BEG_S0", - "WR1BEG0" - ], - [ - "HCLK_NE2BEG0", - "NE2A0" - ], - [ - "HCLK_NN6BEG3", - "NN6A3" - ], - [ - "HCLK_NN6D3", - "NN6E3" - ], - [ - "HCLK_NN2END_S2_0", - "NN2END0" - ], - [ - "HCLK_LVB6", - "LVB_L6" - ], - [ - "HCLK_BYP_BOUNCE3", - "BYP_BOUNCE_N3_3" - ], - [ - "HCLK_NN6E3", - "NN6END3" - ], - [ - "HCLK_LEAF_CLK_B_TOPL4", - "GCLK_L_B10" - ], - [ - "HCLK_SS6END1", - "SS6E1" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END_N0_3" - ], - [ - "HCLK_SR1BEG3", - "SR1BEG3" - ], - [ - "HCLK_SE6C1", - "SE6B1" - ], - [ - "HCLK_NE2BEG3", - "NE2A3" - ], - [ - "HCLK_SS2END1", - "SS2A1" - ], - [ - "HCLK_NN6BEG2", - "NN6A2" - ], - [ - "HCLK_NW2A0", - "NW2A0" - ], - [ - "HCLK_NN6B3", - "NN6C3" - ], - [ - "HCLK_SS6D2", - "SS6C2" - ], - [ - "HCLK_LV0", - "LV_L1" - ], - [ - "HCLK_SE6C2", - "SE6B2" - ], - [ - "HCLK_SW6D1", - "SW6C1" - ], - [ - "HCLK_NW6B0", - "NW6C0" - ], - [ - "HCLK_NN2BEG0", - "NN2A0" - ], - [ - "HCLK_NL1END_S3_0", - "NL1END0" - ], - [ - "HCLK_NN6D2", - "NN6E2" - ], - [ - "HCLK_SE6D1", - "SE6C1" - ], - [ - "HCLK_NN6E2", - "NN6END2" - ], - [ - "HCLK_SS6C2", - "SS6B2" - ], - [ - "HCLK_NE6D0", - "NE6E0" - ], - [ - "HCLK_NN6B1", - "NN6C1" - ], - [ - "HCLK_FAN_BOUNCE_S3_6", - "FAN_BOUNCE6" - ], - [ - "HCLK_NW6D2", - "NW6E2" - ], - [ - "HCLK_SW6C2", - "SW6B2" - ], - [ - "HCLK_LV11", - "LV_L12" - ], - [ - "HCLK_SW6E3", - "SW6D3" - ], - [ - "HCLK_LEAF_CLK_B_TOPL0", - "GCLK_L_B6" - ], - [ - "HCLK_SS6D3", - "SS6C3" - ], - [ - "HCLK_NE6C3", - "NE6D3" - ], - [ - "HCLK_NL1BEG1", - "NL1END1" - ], - [ - "HCLK_SW6C0", - "SW6B0" - ], - [ - "HCLK_NN6B0", - "NN6C0" - ], - [ - "HCLK_SE6C3", - "SE6B3" - ], - [ - "HCLK_NN6C1", - "NN6D1" - ], - [ - "HCLK_NE6D1", - "NE6E1" - ], - [ - "HCLK_SW6D3", - "SW6C3" - ], - [ - "HCLK_SE6D2", - "SE6C2" - ], - [ - "HCLK_NN6A3", - "NN6B3" - ], - [ - "HCLK_SW6E0", - "SW6D0" - ], - [ - "HCLK_NW6C0", - "NW6D0" - ], - [ - "HCLK_NN2BEG2", - "NN2A2" - ], - [ - "HCLK_NL1BEG0", - "NL1END0" - ], - [ - "HCLK_SR1END2", - "SR1BEG2" - ], - [ - "HCLK_LV2", - "LV_L3" - ], - [ - "HCLK_ER1END3", - "ER1END_N3_3" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END0" - ], - [ - "HCLK_NN6B2", - "NN6C2" - ], - [ - "HCLK_SS6A0", - "SS6BEG0" - ], - [ - "HCLK_SW2END1", - "SW2BEG1" - ], - [ - "HCLK_SW6B3", - "SW6A3" - ], - [ - "HCLK_FAN_BOUNCE_S3_4", - "FAN_BOUNCE4" - ], - [ - "HCLK_SS6C3", - "SS6B3" - ], - [ - "HCLK_SS2A0", - "SS2BEG0" - ], - [ - "HCLK_LEAF_CLK_B_TOPL1", - "GCLK_L_B7" - ], - [ - "HCLK_LEAF_CLK_B_TOPL5", - "GCLK_L_B11" - ], - [ - "HCLK_NE2END_S3_0", - "NE2END0" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "HCLK_NW2A3", - "NW2A3" - ], - [ - "HCLK_NR1BEG1", - "NR1END1" - ], - [ - "HCLK_SS2A3", - "SS2A3" - ], - [ - "HCLK_SW6B2", - "SW6A2" - ], - [ - "HCLK_SS2END0", - "SS2A0" - ], - [ - "HCLK_SL1END3", - "SL1BEG3" - ], - [ - "HCLK_NE2BEG1", - "NE2A1" - ], - [ - "HCLK_LV10", - "LV_L11" - ], - [ - "HCLK_SW2END0", - "SW2BEG0" - ], - [ - "HCLK_SW6E2", - "SW6D2" - ], - [ - "HCLK_SW6C3", - "SW6B3" - ], - [ - "HCLK_NW6A1", - "NW6B1" - ], - [ - "HCLK_SL1END2", - "SL1BEG2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 1 - ], - "tile_types": [ - "CMT_FIFO_L", - "INT_INTERFACE_L" - ], - "wire_pairs": [ - [ - "CMT_FIFO_L_FAN5_5", - "INT_INTERFACE_FAN5" - ], - [ - "CMT_FIFO_L_IMUX46_5", - "INT_INTERFACE_IMUX46" - ], - [ - "CMT_FIFO_ER1BEG1_5", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CMT_FIFO_EE2BEG0_5", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CMT_FIFO_SE4C0_5", - "INT_INTERFACE_SE4C0" - ], - [ - "CMT_FIFO_WW4C3_5", - "INT_INTERFACE_WW4C3" - ], - [ - "CMT_FIFO_L_IMUX2_5", - "INT_INTERFACE_IMUX2" - ], - [ - "CMT_FIFO_EE4B0_5", - "INT_INTERFACE_EE4B0" - ], - [ - "CMT_FIFO_L_FAN0_5", - "INT_INTERFACE_FAN0" - ], - [ - "CMT_FIFO_WW2A0_5", - "INT_INTERFACE_WW2A0" - ], - [ - "CMT_FIFO_L_IMUX21_5", - "INT_INTERFACE_IMUX21" - ], - [ - "CMT_FIFO_L_IMUX5_5", - "INT_INTERFACE_IMUX5" - ], - [ - "CMT_FIFO_L_IMUX18_5", - "INT_INTERFACE_IMUX18" - ], - [ - "CMT_FIFO_EL1BEG1_5", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS1_5", - "INT_INTERFACE_LOGIC_OUTS_L_B1" - ], - [ - "CMT_FIFO_L_IMUX47_5", - "INT_INTERFACE_IMUX47" - ], - [ - "CMT_FIFO_L_IMUX14_5", - "INT_INTERFACE_IMUX14" - ], - [ - "CMT_FIFO_SW4A3_5", - "INT_INTERFACE_SW4A3" - ], - [ - "CMT_FIFO_WW4B1_5", - "INT_INTERFACE_WW4B1" - ], - [ - "CMT_FIFO_EE4BEG2_5", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CMT_FIFO_SE4C3_5", - "INT_INTERFACE_SE4C3" - ], - [ - "CMT_FIFO_L_IMUX37_5", - "INT_INTERFACE_IMUX37" - ], - [ - "CMT_FIFO_L_IMUX13_5", - "INT_INTERFACE_IMUX13" - ], - [ - "CMT_FIFO_WW4A0_5", - "INT_INTERFACE_WW4A0" - ], - [ - "CMT_FIFO_NE2A2_5", - "INT_INTERFACE_NE2A2" - ], - [ - "CMT_FIFO_EE4C1_5", - "INT_INTERFACE_EE4C1" - ], - [ - "CMT_FIFO_WW2A1_5", - "INT_INTERFACE_WW2A1" - ], - [ - "CMT_FIFO_NE4BEG3_5", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CMT_FIFO_L_IMUX23_5", - "INT_INTERFACE_IMUX23" - ], - [ - "CMT_FIFO_NE4BEG2_5", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" - ], - [ - "CMT_FIFO_L_IMUX34_5", - "INT_INTERFACE_IMUX34" - ], - [ - "CMT_FIFO_L_BYP2_5", - "INT_INTERFACE_BYP2" - ], - [ - "CMT_FIFO_L_BYP7_5", - "INT_INTERFACE_BYP7" - ], - [ - "CMT_FIFO_L_IMUX27_5", - "INT_INTERFACE_IMUX27" - ], - [ - "CMT_FIFO_L_IMUX1_5", - "INT_INTERFACE_IMUX1" - ], - [ - "CMT_FIFO_NW4A0_5", - "INT_INTERFACE_NW4A0" - ], - [ - "CMT_FIFO_NW4END3_5", - "INT_INTERFACE_NW4END3" - ], - [ - "CMT_FIFO_SW2A0_5", - "INT_INTERFACE_SW2A0" - ], - [ - "CMT_FIFO_EE4B1_5", - "INT_INTERFACE_EE4B1" - ], - [ - "CMT_FIFO_EE2BEG1_5", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS7_5", - 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"IOI_IOCLK2", + "IOI_SING_IOCLK2" + ], + [ + "IOI_IOCLK3", + "IOI_SING_IOCLK3" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_SING_LEAF_GCLK0" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_SING_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_SING_LEAF_GCLK2" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_SING_LEAF_GCLK3" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_SING_LEAF_GCLK4" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_SING_LEAF_GCLK5" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_SING_RCLK_FORIO0" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_SING_RCLK_FORIO1" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_SING_RCLK_FORIO2" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_SING_RCLK_FORIO3" + ], + [ + "IOI_TBYTEIN", + "IOI_SING_TBYTEIN" + ] + ] + }, + { + "grid_deltas": [ + 0, + 1 + ], + "tile_types": [ + "RIOI", + "RIOI_SING" + ], + "wire_pairs": [ + [ + "IOI_IOCLK0", + "IOI_SING_IOCLK0" + ], + [ + "IOI_IOCLK1", + "IOI_SING_IOCLK1" + ], + [ + "IOI_IOCLK2", + "IOI_SING_IOCLK2" + ], + [ + "IOI_IOCLK3", + "IOI_SING_IOCLK3" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_SING_LEAF_GCLK0" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_SING_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_SING_LEAF_GCLK2" + ], + [ + "IOI_LEAF_GCLK3", + "IOI_SING_LEAF_GCLK3" + ], + [ + "IOI_LEAF_GCLK4", + "IOI_SING_LEAF_GCLK4" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_SING_LEAF_GCLK5" + ], + [ + "IOI_RCLK_FORIO0", + "IOI_SING_RCLK_FORIO0" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_SING_RCLK_FORIO1" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_SING_RCLK_FORIO2" + ], + [ + "IOI_RCLK_FORIO3", + "IOI_SING_RCLK_FORIO3" + ], + [ + "IOI_TBYTEIN", + "IOI_SING_TBYTEIN" + ] + ] + }, + { + "grid_deltas": [ + 0, + -2 + ], + "tile_types": [ + "RIOI", + "RIOI_TBYTESRC" + ], + "wire_pairs": [ + [ + "IOI_IMUX_RC2", + "IOI_IMUX_RC0" + ], + [ + "IOI_IMUX_RC3", + "IOI_IMUX_RC1" ], [ "IOI_IOCLK0", "IOI_IOCLK0" ], [ - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR0" + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" ], [ "IOI_IOCLK3", "IOI_IOCLK3" ], - [ - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1" - ], 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[ - "CMT_TOP_NE4C2_5", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_EE2BEG0_5", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_NE2A2_5", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_WW2END1_5", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_EE4C2_5", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_EE4BEG1_5", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_NW4END2_5", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_WW2A0_5", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_SE4C0_5", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_EE2BEG3_5", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_WW2END3_5", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_NE2A1_5", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_EE4B2_5", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_SE2A0_5", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_LH7_5", - "VBRK_LH7" - ], - [ - "CMT_TOP_EE4C1_5", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_LH8_5", - "VBRK_LH8" - ], - [ - "CMT_TOP_WR1END3_5", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_SW4END0_5", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_NE2A0_5", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_SW4A0_5", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_SE2A3_5", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_SW4A1_5", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_WL1END3_5", - "VBRK_WL1END3" - ] - ] - }, - { - "grid_deltas": [ - 1, - 4 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_LH10_0", - "VBRK_LH10" - ], - [ - "CLK_HROW_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NE2A1_0", - "VBRK_NE2A1" - ], - [ - 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[ - "CMT_TOP_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_LH3_1", - "VBRK_LH3" - ], - [ - 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], - [ - "CMT_TOP_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CMT_TOP_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_LH6_1", - "VBRK_LH6" - ], - [ - "CMT_TOP_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_LH9_1", - "VBRK_LH9" - ], - [ - "CMT_TOP_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_NE2A0_1", - "VBRK_NE2A0" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMVIOB" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ] - ] - }, - { - "grid_deltas": [ - -5, - 4 - ], - "tile_types": [ - "PCIE_INT_INTERFACE_L", - "PCIE_TOP" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_NW2A1", - "PCIE_NW2A1_4" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT44", - "PCIE_IMUX44_L_4" - ], - [ - "INT_INTERFACE_SE4C0", - "PCIE_SE4C0_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "PCIE_LOGIC_OUTS_B9_L_4" - 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- [ - "HCLK_INT_INTERFACE_CK_IN10", - "HCLK_VFRAME_CK_IN10" - ], - [ - "HCLK_INT_INTERFACE_CK_IN6", - "HCLK_VFRAME_CK_IN6" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK4" - ], - [ - "HCLK_INT_INTERFACE_CK_IN5", - "HCLK_VFRAME_CK_IN5" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_VFRAME_CK_BUFHCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN4", - "HCLK_VFRAME_CK_IN4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_VFRAME_CK_BUFRCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN13", - "HCLK_VFRAME_CK_IN13" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_VFRAME_CK_BUFHCLK6" - ], - [ - "HCLK_INT_INTERFACE_CK_IN7", - "HCLK_VFRAME_CK_IN7" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_VFRAME_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_VFRAME_CK_BUFHCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_VFRAME_CK_BUFRCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN11", - "HCLK_VFRAME_CK_IN11" - ], - [ - "HCLK_INT_INTERFACE_CK_IN2", - "HCLK_VFRAME_CK_IN2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_VFRAME_CK_BUFHCLK11" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_CK_IN9", - "HCLK_VFRAME_CK_IN9" - ], - [ - "HCLK_INT_INTERFACE_CK_IN1", - "HCLK_VFRAME_CK_IN1" - ] - ] - }, - { - "grid_deltas": [ - 1, - 2 - ], - "tile_types": [ - "CMT_TOP_R_UPPER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_LH1_3", - "VBRK_LH1" - ], - [ - "CMT_TOP_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_SW2A2_3", - "VBRK_SW2A2" - ], - [ - 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], - [ - "CMT_TOP_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_LH4_3", - "VBRK_LH4" - ], - [ - "CMT_TOP_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_WL1END2_3", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_WW2END3_3", - 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"CMT_TOP_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_LH3_3", - "VBRK_LH3" - ], - [ - "CMT_TOP_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_LH5_3", - "VBRK_LH5" - ], - [ - "CMT_TOP_LH7_3", - "VBRK_LH7" - ], - [ - "CMT_TOP_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_LH9_3", - "VBRK_LH9" - ], - [ - "CMT_TOP_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_SE4C0_3", - "VBRK_SE4C0" - ] - ] - }, - { - "grid_deltas": [ - 1, - -2 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_WW4C1_5", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SE4BEG2_5", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE4BEG2_5", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NW2A3_5", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4BEG1_5", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_WW2A2_5", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_LH5_5", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4END2_5", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_WW4END3_5", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE4BEG3_5", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW2A0_5", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4B1_5", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE2BEG0_5", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE2A2_5", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EE4BEG0_5", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4C3_5", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW4A2_5", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_SE4C2_5", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_WW4B2_5", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_ER1BEG0_5", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WL1END1_5", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NE4BEG3_5", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EL1BEG1_5", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE2BEG3_5", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4END1_5", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EE4B3_5", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH2_5", - "VBRK_LH2" - ], - [ - "CLK_HROW_LH4_5", - "VBRK_LH4" - ], - [ - "CLK_HROW_LH1_5", - "VBRK_LH1" - ], - [ - "CLK_HROW_ER1BEG1_5", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW2A1_5", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_NW4A0_5", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NE4C0_5", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_SW4END2_5", - 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- ], - [ - "GTXE2_LOGIC_OUTS_B9_2", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTXE2_FAN7_2", - "VBRK_EXT_FAN7" - ], - [ - "GTXE2_IMUX27_2", - "VBRK_EXT_IMUX27" - ], - [ - "GTXE2_IMUX39_2", - "VBRK_EXT_IMUX39" - ], - [ - "GTXE2_LOGIC_OUTS_B4_2", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTXE2_BYP2_2", - "VBRK_EXT_BYP2" - ], - [ - "GTXE2_IMUX43_2", - "VBRK_EXT_IMUX43" - ], - [ - "GTXE2_BYP6_2", - "VBRK_EXT_BYP6" - ], - [ - "GTXE2_BYP7_2", - "VBRK_EXT_BYP7" - ], - [ - "GTXE2_BYP0_2", - "VBRK_EXT_BYP0" - ], - [ - "GTXE2_IMUX25_2", - "VBRK_EXT_IMUX25" - ], - [ - "GTXE2_FAN0_2", - "VBRK_EXT_FAN0" - ], - [ - "GTXE2_IMUX29_2", - "VBRK_EXT_IMUX29" - ], - [ - "GTXE2_IMUX46_2", - "VBRK_EXT_IMUX46" - ], - [ - "GTXE2_IMUX38_2", - "VBRK_EXT_IMUX38" - ], - [ - "GTXE2_IMUX9_2", - "VBRK_EXT_IMUX9" - ], - [ - "GTXE2_IMUX16_2", - "VBRK_EXT_IMUX16" - ], - [ - "GTXE2_LOGIC_OUTS_B17_2", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTXE2_IMUX6_2", - "VBRK_EXT_IMUX6" - ], - [ - "GTXE2_LOGIC_OUTS_B19_2", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTXE2_FAN2_2", - "VBRK_EXT_FAN2" - ], - [ - "GTXE2_IMUX41_2", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_LOGIC_OUTS_B10_2", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTXE2_IMUX26_2", - "VBRK_EXT_IMUX26" - ], - [ - "GTXE2_LOGIC_OUTS_B5_2", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTXE2_IMUX23_2", - "VBRK_EXT_IMUX23" - ], - [ - "GTXE2_IMUX35_2", - "VBRK_EXT_IMUX35" - ], - [ - "GTXE2_LOGIC_OUTS_B23_2", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTXE2_IMUX31_2", - "VBRK_EXT_IMUX31" - ], - [ - "GTXE2_IMUX24_2", - "VBRK_EXT_IMUX24" - ], - [ - "GTXE2_IMUX14_2", - "VBRK_EXT_IMUX14" - ], - [ - "GTXE2_BYP5_2", - "VBRK_EXT_BYP5" - ], - [ - "GTXE2_IMUX30_2", - "VBRK_EXT_IMUX30" - ], - [ - "GTXE2_IMUX3_2", - "VBRK_EXT_IMUX3" - ], - [ - "GTXE2_CLK0_2", - "VBRK_EXT_CLK0" - ], - [ - "GTXE2_IMUX0_2", - "VBRK_EXT_IMUX0" - ], - [ - "GTXE2_IMUX21_2", - "VBRK_EXT_IMUX21" - ], - [ - "GTXE2_BYP4_2", - "VBRK_EXT_BYP4" - ], - [ - "GTXE2_IMUX40_2", - "VBRK_EXT_IMUX40" - ], - [ - "GTXE2_CLK1_2", - "VBRK_EXT_CLK1" - ], - [ - "GTXE2_IMUX8_2", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX36_2", - "VBRK_EXT_IMUX36" - ], - [ - "GTXE2_LOGIC_OUTS_B13_2", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_LOGIC_OUTS_B22_2", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTXE2_LOGIC_OUTS_B7_2", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTXE2_CTRL0_2", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_IMUX12_2", - "VBRK_EXT_IMUX12" - ], - [ - "GTXE2_IMUX37_2", - "VBRK_EXT_IMUX37" - ], - [ - "GTXE2_IMUX5_2", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_IMUX13_2", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_CTRL1_2", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_LOGIC_OUTS_B1_2", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_IMUX47_2", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_IMUX1_2", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_IMUX10_2", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_IMUX7_2", - "VBRK_EXT_IMUX7" - ], - [ - "GTXE2_LOGIC_OUTS_B8_2", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTXE2_FAN3_2", - "VBRK_EXT_FAN3" - ], - [ - "GTXE2_IMUX2_2", - "VBRK_EXT_IMUX2" - ], - [ - "GTXE2_IMUX15_2", - "VBRK_EXT_IMUX15" - ], - [ - "GTXE2_LOGIC_OUTS_B6_2", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTXE2_FAN1_2", - "VBRK_EXT_FAN1" - ], - [ - "GTXE2_LOGIC_OUTS_B11_2", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTXE2_LOGIC_OUTS_B16_2", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTXE2_LOGIC_OUTS_B18_2", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTXE2_IMUX20_2", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_LOGIC_OUTS_B0_2", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTXE2_FAN6_2", - "VBRK_EXT_FAN6" - ], - [ - "GTXE2_FAN4_2", - "VBRK_EXT_FAN4" - ], - [ - "GTXE2_IMUX32_2", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_LOGIC_OUTS_B20_2", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTXE2_LOGIC_OUTS_B2_2", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTXE2_IMUX33_2", - "VBRK_EXT_IMUX33" - ], - [ - "GTXE2_FAN5_2", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_BYP3_2", - "VBRK_EXT_BYP3" - ], - [ - "GTXE2_IMUX4_2", - "VBRK_EXT_IMUX4" - ], - [ - "GTXE2_IMUX17_2", - "VBRK_EXT_IMUX17" - ], - [ - "GTXE2_BYP1_2", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_IMUX34_2", - "VBRK_EXT_IMUX34" - ], - [ - "GTXE2_LOGIC_OUTS_B21_2", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTXE2_IMUX44_2", - "VBRK_EXT_IMUX44" - ], - [ - "GTXE2_IMUX18_2", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_LOGIC_OUTS_B3_2", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTXE2_IMUX28_2", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_IMUX42_2", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_IMUX19_2", - "VBRK_EXT_IMUX19" - ], - [ - "GTXE2_IMUX45_2", - "VBRK_EXT_IMUX45" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_BUFG_REBUF_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_BUFG_REBUF_SE2A0_0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_BUFG_REBUF_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_BUFG_REBUF_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - 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"INT_INTERFACE_NW2A2" - ], - [ - "CLK_BUFG_REBUF_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_BUFG_REBUF_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_BUFG_REBUF_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_BUFG_REBUF_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_BUFG_REBUF_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_REBUF_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_BUFG_REBUF_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_REBUF_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_REBUF_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_BUFG_REBUF_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_BUFG_REBUF_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_BUFG_REBUF_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_BUFG_REBUF_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_BUFG_REBUF_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_BUFG_REBUF_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_BUFG_REBUF_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_BUFG_REBUF_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_BUFG_REBUF_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_BUFG_REBUF_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_BUFG_REBUF_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_BUFG_REBUF_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_BUFG_REBUF_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_BUFG_REBUF_NE4C2_0", - "INT_INTERFACE_NE4C2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_IOB", - "HCLK_IOI3" - ], - "wire_pairs": [ - [ - "HCLK_IOB_CK_BUFHCLK6", - "HCLK_IOI_CK_BUFHCLK6" - ], - [ - "HCLK_IOB_CK_BUFRCLK3", - "HCLK_IOI_CK_BUFRCLK3" - ], - [ - "HCLK_IOB_CK_BUFRCLK0", - "HCLK_IOI_CK_BUFRCLK0" - ], - [ - "HCLK_IOB_CK_BUFRCLK1", - "HCLK_IOI_CK_BUFRCLK1" - ], - [ - "HCLK_IOB_PERFCLK2", - "HCLK_IOI_IOCLK_PLL2" - ], - [ - "HCLK_IOB_CK_BUFHCLK7", - "HCLK_IOI_CK_BUFHCLK7" - ], - [ - "HCLK_IOB_CK_BUFHCLK5", - "HCLK_IOI_CK_BUFHCLK5" - ], - [ - "HCLK_IOB_CK_BUFHCLK9", - "HCLK_IOI_CK_BUFHCLK9" - ], - [ - "HCLK_IOB_CK_BUFHCLK3", - "HCLK_IOI_CK_BUFHCLK3" - ], - [ - "HCLK_IOB_CK_BUFHCLK1", - "HCLK_IOI_CK_BUFHCLK1" - ], - [ - "HCLK_IOB_CK_BUFHCLK4", - "HCLK_IOI_CK_BUFHCLK4" - ], - [ - "HCLK_IOB_CK_BUFHCLK8", - "HCLK_IOI_CK_BUFHCLK8" - ], - [ - "HCLK_IOB_CK_BUFHCLK11", - "HCLK_IOI_CK_BUFHCLK11" - ], - [ - "HCLK_IOB_PERFCLK0", - "HCLK_IOI_IOCLK_PLL0" - ], - [ - "HCLK_IOB_PERFCLK1", - "HCLK_IOI_IOCLK_PLL1" - ], - [ - "HCLK_IOB_CK_BUFHCLK0", - "HCLK_IOI_CK_BUFHCLK0" - ], - [ - "HCLK_IOB_CK_BUFRCLK2", - "HCLK_IOI_CK_BUFRCLK2" - ], - [ - "HCLK_IOB_PERFCLK3", - "HCLK_IOI_IOCLK_PLL3" - ], - [ - "HCLK_IOB_CK_BUFHCLK2", - "HCLK_IOI_CK_BUFHCLK2" - ], - [ - "HCLK_IOB_CK_BUFHCLK10", - "HCLK_IOI_CK_BUFHCLK10" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "IO_INT_INTERFACE_L", - "L_TERM_INT" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_IMUX35", - "TERM_INT_IMUX35" - ], - [ - "INT_INTERFACE_NE2A3", - "L_TERM_INT_NW2BEG3" - ], - [ - "INT_INTERFACE_WR1END1", - "L_TERM_INT_WR1BEG1" - ], - [ - "INT_INTERFACE_SW4A3", - "L_TERM_INT_SW4BEG3" - ], - [ - "INT_INTERFACE_LH2", - "L_TERM_INT_LH1" - ], - [ - "INT_INTERFACE_WW2A1", - "L_TERM_INT_WW2BEG1" - ], - [ - "INT_INTERFACE_WW4C1", - "L_TERM_INT_WW4B1" - ], - [ - "INT_INTERFACE_IMUX6", - "TERM_INT_IMUX6" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "INT_INTERFACE_WL1END2", - "L_TERM_INT_WL1BEG2" - ], - [ - "INT_INTERFACE_IMUX12", - "TERM_INT_IMUX12" - ], - [ - "INT_INTERFACE_EE4A1", - "L_TERM_INT_WW4A1" - ], - [ - "INT_INTERFACE_IMUX33", - "TERM_INT_IMUX33" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "TERM_INT_LOGIC_OUTS_L_B13" - ], - [ - "INT_INTERFACE_NE4C2", - "L_TERM_INT_NW4C2" - ], - [ - "INT_INTERFACE_LH12", - "L_TERM_INT_LH0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "INT_INTERFACE_NE4C0", - "L_TERM_INT_NW4C0" - ], - [ - "INT_INTERFACE_SW4END0", - "L_TERM_INT_SW4C0" - ], - [ - "INT_INTERFACE_IMUX1", - "TERM_INT_IMUX1" - ], - [ - "INT_INTERFACE_IMUX16", - "TERM_INT_IMUX16" - ], - [ - "INT_INTERFACE_FAN6", - "TERM_INT_FAN6" - ], - [ - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLK" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "TERM_INT_LOGIC_OUTS_L_B0" - ], - [ - "INT_INTERFACE_EL1BEG1", - "L_TERM_INT_WL1BEG1" - ], - [ - "INT_INTERFACE_WW4B3", - "L_TERM_INT_WW4A3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "INT_INTERFACE_FAN1", - "TERM_INT_FAN1" - ], - [ - "INT_INTERFACE_IMUX44", - "TERM_INT_IMUX44" - ], - [ - "INT_INTERFACE_EE4BEG1", - "L_TERM_INT_WW4BEG1" - ], - [ - "INT_INTERFACE_SE4C2", - "L_TERM_INT_SW4C2" - ], - [ - "INT_INTERFACE_FAN5", - "TERM_INT_FAN5" - ], - [ - "INT_INTERFACE_WW4A0", - "L_TERM_INT_WW4BEG0" - ], - [ - "INT_INTERFACE_IMUX9", - "TERM_INT_IMUX9" - ], - [ - "INT_INTERFACE_SW2A0", - "L_TERM_INT_SW2BEG0" - ], - [ - "INT_INTERFACE_BYP3", - "TERM_INT_BYP3" - ], - [ - "INT_INTERFACE_BYP4", - "TERM_INT_BYP4" - ], - [ - "INT_INTERFACE_EE4B0", - "L_TERM_INT_WW4B0" - ], - [ - "INT_INTERFACE_IMUX19", - "TERM_INT_IMUX19" - ], - [ - "INT_INTERFACE_EE4C3", - "L_TERM_INT_WW4C3" - ], - [ - "INT_INTERFACE_SW4A2", - "L_TERM_INT_SW4BEG2" - ], - [ - "INT_INTERFACE_WW2A2", - "L_TERM_INT_WW2BEG2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "INT_INTERFACE_IMUX45", - "TERM_INT_IMUX45" - ], - [ - "INT_INTERFACE_MONITOR_N", - "TERM_INT_MONITOR_N" - ], - [ - "INT_INTERFACE_LH5", - "L_TERM_INT_LH4" - ], - [ - "INT_INTERFACE_WW4A3", - "L_TERM_INT_WW4BEG3" - ], - [ - "INT_INTERFACE_WW4C3", - "L_TERM_INT_WW4B3" - ], - [ - "INT_INTERFACE_IMUX40", - "TERM_INT_IMUX40" - ], - [ - "INT_INTERFACE_LH3", - "L_TERM_INT_LH2" - ], - [ - "INT_INTERFACE_SW2A1", - "L_TERM_INT_SW2BEG1" - ], - [ - "INT_INTERFACE_EE4BEG2", - "L_TERM_INT_WW4BEG2" - ], - [ - "INT_INTERFACE_BYP1", - "TERM_INT_BYP1" - ], - [ - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" - ], - [ - "INT_INTERFACE_SE2A2", - "L_TERM_INT_SW2BEG2" - ], - [ - "INT_INTERFACE_IMUX37", - "TERM_INT_IMUX37" - ], - [ - "INT_INTERFACE_BLOCK_OUTS_L_B0", - "TERM_INT_BLOCK_OUTS_L_B0" - ], - [ - "INT_INTERFACE_EE2A0", - "L_TERM_INT_WW2A0" - ], - [ - "INT_INTERFACE_FAN4", - "TERM_INT_FAN4" - ], - [ - "INT_INTERFACE_EE4A2", - "L_TERM_INT_WW4A2" - ], - [ - "INT_INTERFACE_WW4C2", - "L_TERM_INT_WW4B2" - ], - [ - "INT_INTERFACE_IMUX39", - "TERM_INT_IMUX39" - ], - [ - "INT_INTERFACE_EE4BEG3", - "L_TERM_INT_WW4BEG3" - ], - [ - "INT_INTERFACE_NW4END1", - "L_TERM_INT_NW4C1" - ], - [ - "INT_INTERFACE_EE4B1", - "L_TERM_INT_WW4B1" - ], - [ - "INT_INTERFACE_ER1BEG3", - "L_TERM_INT_WL1BEG3" - ], - [ - "INT_INTERFACE_WW2END3", - "L_TERM_INT_WW2A3" - ], - [ - "INT_INTERFACE_IMUX21", - "TERM_INT_IMUX21" - ], - [ - "INT_INTERFACE_CTRL1", - "TERM_INT_CTRL1" - ], - [ - "INT_INTERFACE_IMUX13", - "TERM_INT_IMUX13" - ], - [ - "INT_INTERFACE_IMUX10", - "TERM_INT_IMUX10" - ], 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"INT_INTERFACE_LH1", - "L_TERM_INT_LH0" - ], - [ - "INT_INTERFACE_IMUX31", - "TERM_INT_IMUX31" - ], - [ - "INT_INTERFACE_NW4A2", - "L_TERM_INT_NW4BEG2" - ], - [ - "INT_INTERFACE_EE2BEG1", - "L_TERM_INT_WW2BEG1" - ], - [ - "INT_INTERFACE_NW2A1", - "L_TERM_INT_NW2BEG1" - ], - [ - "INT_INTERFACE_EE4BEG0", - "L_TERM_INT_WW4BEG0" - ], - [ - "INT_INTERFACE_LH6", - "L_TERM_INT_LH5" - ], - [ - "INT_INTERFACE_NW4END3", - "L_TERM_INT_NW4C3" - ], - [ - "INT_INTERFACE_LH10", - "L_TERM_INT_LH2" - ], - [ - "INT_INTERFACE_WW4END0", - "L_TERM_INT_WW4C0" - ], - [ - "INT_INTERFACE_IMUX15", - "TERM_INT_IMUX15" - ], - [ - "INT_INTERFACE_FAN3", - "TERM_INT_FAN3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "INT_INTERFACE_WW2END2", - "L_TERM_INT_WW2A2" - ], - [ - "INT_INTERFACE_IMUX26", - "TERM_INT_IMUX26" - ], - [ - "INT_INTERFACE_IMUX22", - "TERM_INT_IMUX22" - ], - [ - "INT_INTERFACE_IMUX28", - "TERM_INT_IMUX28" - ], - [ - "INT_INTERFACE_EL1BEG2", - "L_TERM_INT_WL1BEG2" - ], - [ - "INT_INTERFACE_IMUX46", - "TERM_INT_IMUX46" - ], - [ - "INT_INTERFACE_CTRL0", - "TERM_INT_CTRL0" - ], - [ - "INT_INTERFACE_EE4A3", - "L_TERM_INT_WW4A3" - ], - [ - "L_INT_INTER_DQS_IOTOPHASER", - "L_TERM_INT_DQS_IOTOPHASER" - ], - [ - "INT_INTERFACE_IMUX3", - "TERM_INT_IMUX3" - ], - [ - "INT_INTERFACE_WW4B2", - "L_TERM_INT_WW4A2" - ], - [ - "INT_INTERFACE_IMUX42", - "TERM_INT_IMUX42" - ], - [ - "INT_INTERFACE_WR1END3", - "L_TERM_INT_WL1BEG3" - ], - [ - "INT_INTERFACE_WR1END2", - "L_TERM_INT_WR1BEG3" - ], - [ - "INT_INTERFACE_WW2END1", - "L_TERM_INT_WW2A1" - ], - [ - "INT_INTERFACE_IMUX32", - "TERM_INT_IMUX32" - ], - [ - "INT_INTERFACE_NW4A3", - "L_TERM_INT_NW4BEG3" - ], - [ - "INT_INTERFACE_WW4A2", - "L_TERM_INT_WW4BEG2" - ], - [ - "INT_INTERFACE_SE4BEG1", - "L_TERM_INT_SW4BEG1" - ], - [ - "INT_INTERFACE_WL1END3", - "L_TERM_INT_WR1BEG2" - ], - [ - "INT_INTERFACE_LH4", - "L_TERM_INT_LH3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "INT_INTERFACE_WL1END1", - "L_TERM_INT_WL1BEG1" - ], - [ - "INT_INTERFACE_IMUX47", - "TERM_INT_IMUX47" - ], - [ - "INT_INTERFACE_MONITOR_P", - "TERM_INT_MONITOR_P" - ], - [ - "INT_INTERFACE_NE4C1", - "L_TERM_INT_NW4C1" - ], - [ - "INT_INTERFACE_WW4END3", - "L_TERM_INT_WW4C3" - ], - [ - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" - ], - [ - "INT_INTERFACE_IMUX23", - "TERM_INT_IMUX23" - ], - [ - "INT_INTERFACE_SE4BEG0", - "L_TERM_INT_SW4BEG0" - ], - [ - "INT_INTERFACE_IMUX8", - "TERM_INT_IMUX8" - ], - [ - "INT_INTERFACE_EE2BEG2", - "L_TERM_INT_WW2BEG2" - ], - [ - "INT_INTERFACE_WW2A0", - "L_TERM_INT_WW2BEG0" - ], - [ - "INT_INTERFACE_EE2A2", - "L_TERM_INT_WW2A2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "TERM_INT_LOGIC_OUTS_L_B22" - ], - [ - "INT_INTERFACE_WL1END0", - "L_TERM_INT_WL1BEG0" - ], - [ - "INT_INTERFACE_EL1BEG0", - "L_TERM_INT_WL1BEG0" - ], - [ - "INT_INTERFACE_SE4BEG3", - "L_TERM_INT_SW4BEG3" - ], - [ - "INT_INTERFACE_NW4A1", - "L_TERM_INT_NW4BEG1" - ], - [ - "INT_INTERFACE_WW4END1", - "L_TERM_INT_WW4C1" - ], - [ - "INT_INTERFACE_IMUX4", - "TERM_INT_IMUX4" - ], - [ - "INT_INTERFACE_NE4BEG3", - "L_TERM_INT_NW4BEG3" - ], - [ - "INT_INTERFACE_EE2BEG3", - "L_TERM_INT_WW2BEG3" - ], - [ - "INT_INTERFACE_NE2A0", - "L_TERM_INT_NW2BEG0" - ], - [ - "INT_INTERFACE_IMUX34", - "TERM_INT_IMUX34" - ], - [ - "INT_INTERFACE_WR1END0", - "L_TERM_INT_WR1BEG0" - ], - [ - "INT_INTERFACE_WW4B0", - "L_TERM_INT_WW4A0" - ], - [ - "INT_INTERFACE_NW2A0", - "L_TERM_INT_NW2BEG0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "TERM_INT_LOGIC_OUTS_L_B10" - ], - [ - "INT_INTERFACE_SE4C0", - "L_TERM_INT_SW4C0" - ], - [ - "INT_INTERFACE_IMUX7", - "TERM_INT_IMUX7" - ], - [ - "INT_INTERFACE_IMUX0", - "TERM_INT_IMUX0" - ], - [ - "INT_INTERFACE_SW4A0", - "L_TERM_INT_SW4BEG0" - ], - [ - "INT_INTERFACE_IMUX41", - "TERM_INT_IMUX41" - ], - [ - "INT_INTERFACE_BYP2", - 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"VBRK_EXT_IMUX16" - ], - [ - "GTXE2_IMUX9_5", - "VBRK_EXT_IMUX9" - ], - [ - "GTXE2_IMUX47_5", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_IMUX3_5", - "VBRK_EXT_IMUX3" - ], - [ - "GTXE2_LOGIC_OUTS_B1_5", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_IMUX33_5", - "VBRK_EXT_IMUX33" - ], - [ - "GTXE2_IMUX40_5", - "VBRK_EXT_IMUX40" - ], - [ - "GTXE2_BYP7_5", - "VBRK_EXT_BYP7" - ], - [ - "GTXE2_IMUX34_5", - "VBRK_EXT_IMUX34" - ], - [ - "GTXE2_IMUX24_5", - "VBRK_EXT_IMUX24" - ], - [ - "GTXE2_FAN5_5", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_IMUX8_5", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX5_5", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_CTRL0_5", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_LOGIC_OUTS_B18_5", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTXE2_LOGIC_OUTS_B15_5", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTXE2_LOGIC_OUTS_B9_5", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTXE2_BYP2_5", - "VBRK_EXT_BYP2" - ], - [ - "GTXE2_LOGIC_OUTS_B20_5", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTXE2_LOGIC_OUTS_B6_5", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTXE2_IMUX43_5", - "VBRK_EXT_IMUX43" - ], - [ - "GTXE2_LOGIC_OUTS_B13_5", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_IMUX27_5", - "VBRK_EXT_IMUX27" - ], - [ - "GTXE2_IMUX29_5", - "VBRK_EXT_IMUX29" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_CK_BUFHCLK_R4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "CLK_HROW_CK_IN_R12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "CLK_HROW_CK_IN_R9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "CLK_HROW_CK_BUFHCLK_R7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "CLK_HROW_CK_BUFHCLK_R2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "CLK_HROW_CK_BUFHCLK_R11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "CLK_HROW_CK_IN_R11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "CLK_HROW_CK_IN_R7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "CLK_HROW_CK_BUFHCLK_R10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "CLK_HROW_CK_IN_R4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "CLK_HROW_CK_BUFHCLK_R1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "CLK_HROW_CK_IN_R8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "CLK_HROW_CK_IN_R13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "CLK_HROW_CK_BUFHCLK_R5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "CLK_HROW_CK_BUFHCLK_R6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "CLK_HROW_CK_BUFHCLK_R3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_R0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "CLK_HROW_CK_BUFHCLK_R8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "CLK_HROW_CK_IN_R10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "CLK_HROW_CK_IN_R6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "CLK_HROW_CK_IN_R5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "CLK_HROW_CK_BUFHCLK_R9", - "HCLK_VBRK_CK_BUFHCLK9" - ] - ] - }, - { - "grid_deltas": [ - -1, - 2 - ], - "tile_types": [ - "CLBLM_L", - "DSP_R" - ], - "wire_pairs": [ - [ - "CLBLM_NE2A2", - "DSP_NE2A2_2" - ], - [ - "CLBLM_ER1BEG3", - "DSP_ER1BEG3_2" - ], - [ - "CLBLM_WW4A1", - "DSP_WW4A1_2" - ], - [ - "CLBLM_WL1END0", - "DSP_WL1END0_2" - ], - [ - "CLBLM_EE4B0", - "DSP_EE4B0_2" - ], - [ - "CLBLM_MONITOR_P", - "DSP_MONITOR_P_2" - ], - [ - "CLBLM_LH5", - "DSP_LH5_2" - ], - [ - "CLBLM_WW2END0", - "DSP_WW2END0_2" - ], - [ - "CLBLM_EE4C2", - "DSP_EE4C2_2" - ], - [ - "CLBLM_NE2A1", - "DSP_NE2A1_2" - ], - [ - "CLBLM_SE4C3", - "DSP_SE4C3_2" - ], - [ - "CLBLM_EE4BEG0", - "DSP_EE4BEG0_2" - ], - [ - "CLBLM_WW4C3", - "DSP_WW4C3_2" - ], - [ - "CLBLM_NW4A0", - "DSP_NW4A0_2" - ], - [ - "CLBLM_WW4END0", - "DSP_WW4END0_2" - ], - [ - "CLBLM_EE4C3", - "DSP_EE4C3_2" - ], - [ - "CLBLM_NE4BEG3", - "DSP_NE4BEG3_2" - ], - [ - "CLBLM_WW2A3", - "DSP_WW2A3_2" - ], - [ - "CLBLM_NE4BEG0", - "DSP_NE4BEG0_2" - ], - [ - "CLBLM_WL1END3", - "DSP_WL1END3_2" - ], - [ - "CLBLM_SE4BEG1", - "DSP_SE4BEG1_2" - ], - [ - "CLBLM_NW2A3", - "DSP_NW2A3_2" - ], - [ - "CLBLM_SE4C0", - "DSP_SE4C0_2" - ], - [ - "CLBLM_EL1BEG0", - "DSP_EL1BEG0_2" - ], - [ - "CLBLM_NW4END2", - "DSP_NW4END2_2" - ], - [ - "CLBLM_WW4C0", - "DSP_WW4C0_2" - ], - [ - "CLBLM_EL1BEG2", - "DSP_EL1BEG2_2" - ], - [ - "CLBLM_WW4B1", - "DSP_WW4B1_2" - ], - [ - "CLBLM_LH1", - "DSP_LH1_2" - ], - [ - "CLBLM_LH4", - "DSP_LH4_2" - ], - [ - "CLBLM_EE4C0", - "DSP_EE4C0_2" - ], - [ - "CLBLM_LH10", - "DSP_LH10_2" - ], - [ - "CLBLM_EE2A3", - "DSP_EE2A3_2" - ], - [ - "CLBLM_WR1END2", - "DSP_WR1END2_2" - ], - [ - "CLBLM_EE4B2", - "DSP_EE4B2_2" - ], - [ - "CLBLM_WW4END3", - "DSP_WW4END3_2" - ], - [ - "CLBLM_EE2A1", - "DSP_EE2A1_2" - ], - [ - "CLBLM_WL1END2", - "DSP_WL1END2_2" - ], - [ - "CLBLM_SW2A2", - "DSP_SW2A2_2" - ], - [ - "CLBLM_NE2A0", - "DSP_NE2A0_2" - ], - [ - "CLBLM_SE2A1", - "DSP_SE2A1_2" - ], - [ - "CLBLM_NW4END3", - "DSP_NW4END3_2" - ], - [ - "CLBLM_SW4A2", - "DSP_SW4A2_2" - ], - [ - "CLBLM_SW4END1", - "DSP_SW4END1_2" - ], - [ - "CLBLM_WW2END3", - "DSP_WW2END3_2" - ], - [ - "CLBLM_EL1BEG3", - "DSP_EL1BEG3_2" - ], - [ - "CLBLM_LH6", - "DSP_LH6_2" - ], - [ - "CLBLM_WW2END1", - "DSP_WW2END1_2" - ], - [ - "CLBLM_SE4BEG0", - "DSP_SE4BEG0_2" - ], - [ - "CLBLM_WW2A1", - "DSP_WW2A1_2" - ], - [ - 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"DSP_WW2END2_2" - ], - [ - "CLBLM_EE2BEG2", - "DSP_EE2BEG2_2" - ], - [ - "CLBLM_ER1BEG0", - "DSP_ER1BEG0_2" - ], - [ - "CLBLM_SE4C2", - "DSP_SE4C2_2" - ], - [ - "CLBLM_SE2A0", - "DSP_SE2A0_2" - ], - [ - "CLBLM_EE2A0", - "DSP_EE2A0_2" - ], - [ - "CLBLM_WR1END0", - "DSP_WR1END0_2" - ] - ] - }, - { - "grid_deltas": [ - 1, - -6 - ], - "tile_types": [ - "CFG_CENTER_MID", - "VFRAME" - ], - "wire_pairs": [ - [ - "CFG_CENTER_IMUX47_16", - "VFRAME_IMUX47" - ], - [ - "CFG_CENTER_NE4BEG0_16", - "VFRAME_NE4BEG0" - ], - [ - "CFG_CENTER_FAN2_16", - "VFRAME_FAN2" - ], - [ - "CFG_CENTER_WL1END0_16", - "VFRAME_WL1END0" - ], - [ - "CFG_CENTER_ER1BEG1_16", - "VFRAME_ER1BEG1" - ], - [ - "CFG_CENTER_IMUX28_16", - "VFRAME_IMUX28" - ], - [ - "CFG_CENTER_IMUX30_16", - "VFRAME_IMUX30" - ], - [ - "CFG_CENTER_EE2BEG1_16", - "VFRAME_EE2BEG1" - ], - [ - "CFG_CENTER_NE2A3_16", - "VFRAME_NE2A3" - ], - [ - "CFG_CENTER_IMUX18_16", - "VFRAME_IMUX18" - ], - [ - "CFG_CENTER_SE4BEG1_16", - "VFRAME_SE4BEG1" - ], - [ - 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"HCLK_CMT_PHY_CONTROL_IRANKB0" - ], - [ - "CMT_PHY_CONTROL_OBURSTPENDING0", - "HCLK_CMT_OBURSTPENDING0" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL1", - "HCLK_CMT_MUX_CLK_PLL1" - ], - [ - "PLL_CLK_FREQBB_REBUFOUT3", - "HCLK_CMT_FREQ_REF_NS3" - ], - [ - "CMT_PHASER_UP_BUFMRCE_CE1", - "HCLK_CMT_BUFMR_CE1" - ], - [ - "CMT_PHASER_IN_D_RCLK3", - "HCLK_CMT_PHASERIN_RCLK3" - ], - [ - "CMT_FREQ_PHASER_REFMUX_0", - "HCLK_CMT_FREQ_PHASER_REFMUX_0" - ], - [ - "PLL_CLK_FREQBB_REBUFOUT0", - "HCLK_CMT_FREQ_REF_NS0" - ], - [ - "CMT_R_TOP_UPPER_B_CLKIN2", - "HCLK_CMT_MUX_PLLE2_CLKIN2" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL5", - "HCLK_CMT_MUX_CLK_PLL5" - ], - [ - "CMT_R_TOP_UPPER_B_CLKPLL0", - "HCLK_CMT_MUX_CLK_PLL0" - ], - [ - "CMT_PHASER_UP_PHASERREF_BELOW0", - "HCLK_CMT_PHASEREF_BELOW0" - ], - [ - "CMT_PHASER_IN_D_ICLK", - "HCLK_CMT_PHASERIND_ICLK" - ], - [ - "CMT_PHASER_TOP_SYNC_BB", - "HCLK_CMT_PHY_SYNC_BB" - ], - [ - "CMT_PHY_CONTROL_IRANKA1", - "HCLK_CMT_PHY_CONTROL_IRANKA1" - ], - [ - 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], - [ - "R_TERM_INT_GTX_LOGIC_OUTS_B18", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "R_TERM_INT_GTX_IMUX30", - "VBRK_EXT_IMUX30" - ], - [ - "R_TERM_INT_GTX_IMUX44", - "VBRK_EXT_IMUX44" - ], - [ - "R_TERM_INT_GTX_IMUX34", - "VBRK_EXT_IMUX34" - ], - [ - "R_TERM_INT_GTX_IMUX4", - "VBRK_EXT_IMUX4" - ], - [ - "R_TERM_INT_GTX_LOGIC_OUTS_B17", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "R_TERM_INT_GTX_FAN1", - "VBRK_EXT_FAN1" - ], - [ - "R_TERM_INT_GTX_CLK1", - "VBRK_EXT_CLK1" - ], - [ - "R_TERM_INT_GTX_IMUX18", - "VBRK_EXT_IMUX18" - ], - [ - "R_TERM_INT_GTX_IMUX21", - "VBRK_EXT_IMUX21" - ], - [ - "R_TERM_INT_GTX_LOGIC_OUTS_B4", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "R_TERM_INT_GTX_IMUX8", - "VBRK_EXT_IMUX8" - ], - [ - "R_TERM_INT_GTX_IMUX32", - "VBRK_EXT_IMUX32" - ], - [ - "R_TERM_INT_GTX_FAN3", - "VBRK_EXT_FAN3" - ], - [ - "R_TERM_INT_GTX_IMUX14", - "VBRK_EXT_IMUX14" - ], - [ - "R_TERM_INT_GTX_IMUX43", - "VBRK_EXT_IMUX43" - ], - [ - "R_TERM_INT_GTX_IMUX7", - "VBRK_EXT_IMUX7" - ], - [ - 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"DSP_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "DSP_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "DSP_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "DSP_SW2A0_3", - "VBRK_SW2A0" - ], - [ - "DSP_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "DSP_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "DSP_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "DSP_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "DSP_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "DSP_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "DSP_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "DSP_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "DSP_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "DSP_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "DSP_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "DSP_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "DSP_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "DSP_LH3_3", - "VBRK_LH3" - ], - [ - "DSP_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "DSP_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "DSP_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "DSP_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "DSP_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "DSP_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "DSP_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "DSP_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - "DSP_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "DSP_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "DSP_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "DSP_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "DSP_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "DSP_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "DSP_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "DSP_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "DSP_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "DSP_LH10_3", - "VBRK_LH10" - ], - [ - "DSP_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "DSP_MONITOR_N_3", - "VBRK_MONITOR_N" - ], - [ - "DSP_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "DSP_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "DSP_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "DSP_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "DSP_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "DSP_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "DSP_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "DSP_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "DSP_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "DSP_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "DSP_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "DSP_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "DSP_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "DSP_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "DSP_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "DSP_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "DSP_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "DSP_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "DSP_LH7_3", - "VBRK_LH7" - ], - [ - "DSP_LH2_3", - "VBRK_LH2" - ], - [ - "DSP_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "DSP_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "DSP_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "DSP_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "DSP_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "DSP_LH5_3", - "VBRK_LH5" - ], - [ - "DSP_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "DSP_LH4_3", - "VBRK_LH4" - ], - [ - "DSP_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "DSP_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "DSP_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "DSP_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "DSP_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "DSP_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "DSP_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "DSP_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "DSP_LH8_3", - "VBRK_LH8" - ], - [ - "DSP_LH11_3", - "VBRK_LH11" - ], - [ - "DSP_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "DSP_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "DSP_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "DSP_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "DSP_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "DSP_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "DSP_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "DSP_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "DSP_MONITOR_P_3", - "VBRK_MONITOR_P" - ], - [ - "DSP_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "DSP_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "DSP_LH12_3", - "VBRK_LH12" - ], - [ - "DSP_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "DSP_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "DSP_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "DSP_LH1_3", - "VBRK_LH1" - ], - [ - "DSP_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "DSP_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "DSP_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "DSP_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "DSP_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "DSP_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "DSP_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "DSP_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "DSP_WW4C2_3", - "VBRK_WW4C2" - ], - [ - "DSP_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "DSP_SW4A2_3", - "VBRK_SW4A2" + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" ], [ - "DSP_NE2A3_3", - "VBRK_NE2A3" + "IOI_LEAF_GCLK3", + "IOI_LEAF_GCLK3" ], [ - "DSP_EE4C3_3", - "VBRK_EE4C3" + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" ], [ - "DSP_NW4A0_3", - "VBRK_NW4A0" + "IOI_LEAF_GCLK5", + "IOI_LEAF_GCLK5" ], [ - "DSP_SE2A3_3", - "VBRK_SE2A3" + "IOI_RCLK_DIV_CE2_1", + "IOI_RCLK_DIV_CE2" ], [ - "DSP_WW4B3_3", - "VBRK_WW4B3" + "IOI_RCLK_DIV_CE3_1", + "IOI_RCLK_DIV_CE3" ], [ - "DSP_NW4END2_3", - "VBRK_NW4END2" + "IOI_RCLK_DIV_CLR0", + "IOI_RCLK_DIV_CLR0_1" ], [ - "DSP_LH9_3", - "VBRK_LH9" + "IOI_RCLK_DIV_CLR1", + "IOI_RCLK_DIV_CLR1_1" ], [ - "DSP_EE2BEG2_3", - "VBRK_EE2BEG2" + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" ], [ - "DSP_WW4C1_3", - "VBRK_WW4C1" + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" ], [ - "DSP_EE4BEG0_3", - "VBRK_EE4BEG0" + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" ], [ - "DSP_NW4END1_3", - "VBRK_NW4END1" + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" ], [ - "DSP_WW4C3_3", - "VBRK_WW4C3" + "IOI_TBYTEIN", + "IOI_TBYTEIN" ] ] }, @@ -255074,29 +473810,49 @@ "IOI_DCI_TSTRST0" ], [ - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK4" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_RCLK_FORIO3" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO2" + "IOI_IMUX_RC0", + "IOI_IMUX_RC2" ], [ "IOI_IMUX_RC1", "IOI_IMUX_RC3" ], [ - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO0" + "IOI_IOCLK0", + "IOI_IOCLK0" + ], + [ + "IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "IOI_IOCLK3", + "IOI_IOCLK3" + ], + [ + "IOI_LEAF_GCLK0", + "IOI_LEAF_GCLK0" + ], + [ + "IOI_LEAF_GCLK1", + "IOI_LEAF_GCLK1" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_LEAF_GCLK2" ], [ "IOI_LEAF_GCLK3", "IOI_LEAF_GCLK3" ], + [ + "IOI_LEAF_GCLK4", + "IOI_LEAF_GCLK4" + ], [ "IOI_LEAF_GCLK5", "IOI_LEAF_GCLK5" @@ -255106,127708 +473862,228 @@ "IOI_RCLK_DIV_CE2_1" ], [ - "IOI_IOCLK2", - "IOI_IOCLK2" - ], - [ - "IOI_IOCLK1", - "IOI_IOCLK1" - ], - [ - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR1" - ], - [ - "IOI_IOCLK0", - "IOI_IOCLK0" + "IOI_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3_1" ], [ "IOI_RCLK_DIV_CLR0_1", "IOI_RCLK_DIV_CLR0" ], [ - "IOI_IOCLK3", - "IOI_IOCLK3" - ], - [ - "IOI_TBYTEIN", - "IOI_TBYTEIN" - ], - [ - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1" - ], - [ - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK0" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO1" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK2" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK1" - ], - [ - "IOI_IMUX_RC0", - "IOI_IMUX_RC2" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH8_5", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_IMUX6_5", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_EE4A2_5", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EE2BEG1_5", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_NE4BEG0_5", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_WR1END2_5", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_LH3_5", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_IMUX33_5", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_SE4BEG1_5", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_WW4C1_5", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_WR1END0_5", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_IMUX40_5", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_LH4_5", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_IMUX41_5", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_NE2A1_5", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_WW4C0_5", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_FAN1_5", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_BYP6_5", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX8_5", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_LH6_5", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_IMUX11_5", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_IMUX23_5", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_BYP0_5", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_IMUX14_5", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_WW4END1_5", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_SW4A2_5", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_NE2A0_5", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_IMUX30_5", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_EE4B3_5", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX5_5", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_NE4C2_5", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX34_5", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_IMUX10_5", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_NW4A2_5", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_NE4C3_5", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX2_5", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_EE2A3_5", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_EL1BEG2_5", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW4B2_5", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EE2A1_5", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_EL1BEG3_5", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_NW4END2_5", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_WW4C2_5", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_EE4B2_5", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_EE4B0_5", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_ER1BEG2_5", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_LH5_5", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_FAN4_5", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_LH1_5", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_SW2A2_5", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_ER1BEG3_5", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_FAN5_5", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_LH9_5", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NE4BEG2_5", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SE4BEG3_5", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NE2A2_5", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EL1BEG0_5", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_EE4BEG3_5", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_IMUX22_5", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_WW4B1_5", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WL1END2_5", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_EE4BEG0_5", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_WL1END1_5", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_EE4A3_5", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_WW4END0_5", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_SE2A0_5", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_WW4A2_5", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_LH7_5", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_CLK0_5", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_SE2A1_5", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_SE2A2_5", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WR1END1_5", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_IMUX46_5", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_WW2END2_5", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_IMUX24_5", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_CLK1_5", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_IMUX29_5", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_WW4END3_5", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_NW2A0_5", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_SE4BEG0_5", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX19_5", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX42_5", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_NW4END3_5", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_LH2_5", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_LH10_5", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_SE4C1_5", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_EE2A2_5", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_WW4A1_5", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_NE2A3_5", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_SW2A1_5", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE4A0_5", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_BYP2_5", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_SE4C0_5", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_FAN6_5", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_EE4C2_5", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_NE4C0_5", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX45_5", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_IMUX44_5", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_SE4C2_5", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_WW2A1_5", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_NW4END1_5", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_IMUX1_5", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_EE2A0_5", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4BEG1_5", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_IMUX15_5", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_FAN7_5", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_EE4BEG2_5", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW2END1_5", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_SW4A1_5", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_BYP3_5", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX20_5", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_WL1END3_5", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_WW4B3_5", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_IMUX43_5", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_NW4END0_5", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_NE4C1_5", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_BYP5_5", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_EE2BEG0_5", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_SW4A3_5", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_EE4C3_5", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_IMUX31_5", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_BYP7_5", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_SW4A0_5", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NW4A3_5", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_IMUX17_5", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_EE4B1_5", - "INT_INTERFACE_EE4B1" - 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"VBRK_NE4BEG3" - ], - [ - "CLK_BUFG_REBUF_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CLK_BUFG_REBUF_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "CLK_BUFG_REBUF_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "CLK_BUFG_REBUF_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CLK_BUFG_REBUF_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CLK_BUFG_REBUF_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CLK_BUFG_REBUF_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CLK_BUFG_REBUF_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CLK_BUFG_REBUF_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CLK_BUFG_REBUF_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CLK_BUFG_REBUF_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CLK_BUFG_REBUF_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "CLK_BUFG_REBUF_LH12_0", - "VBRK_LH12" - ], - [ - "CLK_BUFG_REBUF_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_BUFG_REBUF_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_BUFG_REBUF_EE4A2_0", - "VBRK_EE4A2" - ], - [ - "CLK_BUFG_REBUF_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "CLK_BUFG_REBUF_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "CLK_BUFG_REBUF_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "CLK_BUFG_REBUF_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "CLK_BUFG_REBUF_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "CLK_BUFG_REBUF_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CLK_BUFG_REBUF_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CLK_BUFG_REBUF_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "CLK_BUFG_REBUF_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CLK_BUFG_REBUF_LH9_0", - "VBRK_LH9" - ], - [ - "CLK_BUFG_REBUF_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CLK_BUFG_REBUF_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CLK_BUFG_REBUF_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CLK_BUFG_REBUF_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CLK_BUFG_REBUF_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "CLK_BUFG_REBUF_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_BUFG_REBUF_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CLK_BUFG_REBUF_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CLK_BUFG_REBUF_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "CLK_BUFG_REBUF_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "CLK_BUFG_REBUF_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "CLK_BUFG_REBUF_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CLK_BUFG_REBUF_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CLK_BUFG_REBUF_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CLK_BUFG_REBUF_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CLK_BUFG_REBUF_LH7_0", - "VBRK_LH7" - ], - [ - "CLK_BUFG_REBUF_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "CLK_BUFG_REBUF_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "CLK_BUFG_REBUF_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_BUFG_REBUF_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CLK_BUFG_REBUF_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CLK_BUFG_REBUF_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "CLK_BUFG_REBUF_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CLK_BUFG_REBUF_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "CLK_BUFG_REBUF_LH1_0", - "VBRK_LH1" - ], - [ - "CLK_BUFG_REBUF_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CLK_BUFG_REBUF_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "CLK_BUFG_REBUF_LH6_0", - "VBRK_LH6" - ], - [ - "CLK_BUFG_REBUF_LH5_0", - "VBRK_LH5" - ], - [ - "CLK_BUFG_REBUF_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "CLK_BUFG_REBUF_LH10_0", - "VBRK_LH10" - ], - [ - "CLK_BUFG_REBUF_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "CLK_BUFG_REBUF_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "CLK_BUFG_REBUF_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_BUFG_REBUF_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CLK_BUFG_REBUF_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "CLK_BUFG_REBUF_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CLK_BUFG_REBUF_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CLK_BUFG_REBUF_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CLK_BUFG_REBUF_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "CLK_BUFG_REBUF_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "CLK_BUFG_REBUF_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CLK_BUFG_REBUF_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "CLK_BUFG_REBUF_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CLK_BUFG_REBUF_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CLK_BUFG_REBUF_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "CLK_BUFG_REBUF_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "CLK_BUFG_REBUF_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "CLK_BUFG_REBUF_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CLK_BUFG_REBUF_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CLK_BUFG_REBUF_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "CLK_BUFG_REBUF_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "CLK_BUFG_REBUF_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CLK_BUFG_REBUF_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "CLK_BUFG_REBUF_LH2_0", - "VBRK_LH2" - ], - [ - "CLK_BUFG_REBUF_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "CLK_BUFG_REBUF_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CLK_BUFG_REBUF_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "CLK_BUFG_REBUF_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CLK_BUFG_REBUF_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CLK_BUFG_REBUF_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "CLK_BUFG_REBUF_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "CLK_BUFG_REBUF_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CLK_BUFG_REBUF_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "CLK_BUFG_REBUF_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "CLK_BUFG_REBUF_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_BUFG_REBUF_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CLK_BUFG_REBUF_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CLK_BUFG_REBUF_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CLK_BUFG_REBUF_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CLK_BUFG_REBUF_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CLK_BUFG_REBUF_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CLK_BUFG_REBUF_LH8_0", - "VBRK_LH8" - ], - [ - "CLK_BUFG_REBUF_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CLK_BUFG_REBUF_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "CLK_BUFG_REBUF_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CLK_BUFG_REBUF_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "CLK_BUFG_REBUF_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "CLK_BUFG_REBUF_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CLK_BUFG_REBUF_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CLK_BUFG_REBUF_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_BUFG_REBUF_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CLK_BUFG_REBUF_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "CLK_BUFG_REBUF_NW4A1_0", - "VBRK_NW4A1" - ], - [ - "CLK_BUFG_REBUF_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "CLK_BUFG_REBUF_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "CLK_BUFG_REBUF_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_BUFG_REBUF_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "CLK_BUFG_REBUF_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CLK_BUFG_REBUF_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_BUFG_REBUF_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CLK_BUFG_REBUF_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CLK_BUFG_REBUF_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CLK_BUFG_REBUF_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "CLK_BUFG_REBUF_LH11_0", - "VBRK_LH11" - ], - [ - "CLK_BUFG_REBUF_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "CLK_BUFG_REBUF_NW4A2_0", - "VBRK_NW4A2" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_INT_INTERFACE", - "HCLK_R" - ], - "wire_pairs": [ - [ - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_CCIO3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_INT_PERFCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_CK_BUFRCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN2", - "HCLK_CK_IN2" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_INT_PERFCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_IN1", - "HCLK_CK_IN1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_INT_PERFCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_IN3", - "HCLK_CK_IN3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_INT_INTERFACE_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_INT_INTERFACE_CK_IN0", - "HCLK_CK_IN0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_INT_INTERFACE_CCIO0", - "HCLK_CCIO0" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_CCIO2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_INT_INTERFACE_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_INT_INTERFACE_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_CCIO1" - ] - ] - }, - { - "grid_deltas": [ - -1, - -6 - ], - "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_WW4A3_6", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_PMV_WW2A3_6", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_PMV_IMUX45_6", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_IMUX8_6", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_PMV_WW4C3_6", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_WW4END1_6", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_IMUX2_6", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_LH4_6", - "INT_INTERFACE_LH4" - ], - [ - "CLK_PMV_EE4A0_6", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_PMV_NW4END0_6", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_IMUX33_6", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_BYP5_6", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_NW4END2_6", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_IMUX29_6", - "INT_INTERFACE_IMUX29" - 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"VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_LH6_0", - "VBRK_LH6" - ], - [ - "CLK_HROW_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_NW4A1_0", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_LH8_0", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_LH1_0", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_LH5_0", - "VBRK_LH5" - ], - [ - "CLK_HROW_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_HROW_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_LH12_0", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_LH7_0", - "VBRK_LH7" - ], - [ - "CLK_HROW_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH11_0", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4A2_0", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_MONITOR_P_0", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_LH2_0", - "VBRK_LH2" - ], - [ - "CLK_HROW_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH9_0", - "VBRK_LH9" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_PMVIOB", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_LH8", - "VBRK_LH8" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_LH2", - "VBRK_LH2" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLK_FEED_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLK_FEED_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLK_FEED_EE4BEG2", - "VBRK_EE4BEG2" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLK_FEED_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLK_FEED_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLK_FEED_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLK_FEED_LH7", - "VBRK_LH7" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLK_FEED_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLK_FEED_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLK_FEED_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLK_FEED_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLK_FEED_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLK_FEED_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLK_FEED_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLK_FEED_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLK_FEED_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLK_FEED_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLK_FEED_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLK_FEED_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLK_FEED_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - 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"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" - ], - [ - "BRAM_FIFO36_CASCADEOUTA_1", - "BRKH_BRAM_CASCADEA_R" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" - ], - [ - "BRAM_FIFO36_CASCADEOUTB_1", - "BRKH_BRAM_CASCADEB_R" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" - ] - ] - }, - { - "grid_deltas": [ - -1, - 3 - ], - "tile_types": [ - "GTX_CHANNEL_2", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTXE2_IMUX11_2", - "VBRK_EXT_IMUX11" - ], - [ - "GTXE2_IMUX22_2", - "VBRK_EXT_IMUX22" - ], - [ - "GTXE2_LOGIC_OUTS_B9_2", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTXE2_FAN7_2", - "VBRK_EXT_FAN7" - ], - [ - "GTXE2_IMUX27_2", - "VBRK_EXT_IMUX27" - ], - [ - "GTXE2_IMUX39_2", - "VBRK_EXT_IMUX39" - ], - [ - "GTXE2_LOGIC_OUTS_B4_2", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTXE2_BYP2_2", - "VBRK_EXT_BYP2" - ], - [ - "GTXE2_IMUX43_2", - "VBRK_EXT_IMUX43" - ], - [ - "GTXE2_BYP6_2", - "VBRK_EXT_BYP6" - ], - [ - "GTXE2_BYP7_2", - "VBRK_EXT_BYP7" - ], - [ - "GTXE2_BYP0_2", - "VBRK_EXT_BYP0" - ], - [ - "GTXE2_IMUX25_2", - "VBRK_EXT_IMUX25" - ], - [ - "GTXE2_FAN0_2", - "VBRK_EXT_FAN0" - ], - [ - "GTXE2_IMUX29_2", - "VBRK_EXT_IMUX29" - ], - [ - "GTXE2_IMUX46_2", - "VBRK_EXT_IMUX46" - ], - [ - "GTXE2_IMUX38_2", - "VBRK_EXT_IMUX38" - ], - [ - "GTXE2_IMUX9_2", - "VBRK_EXT_IMUX9" - ], - [ - "GTXE2_IMUX16_2", - "VBRK_EXT_IMUX16" - ], - [ - "GTXE2_LOGIC_OUTS_B17_2", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTXE2_IMUX6_2", - "VBRK_EXT_IMUX6" - ], - [ - "GTXE2_LOGIC_OUTS_B19_2", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTXE2_FAN2_2", - "VBRK_EXT_FAN2" - ], - [ - "GTXE2_IMUX41_2", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_LOGIC_OUTS_B10_2", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTXE2_IMUX26_2", - "VBRK_EXT_IMUX26" - ], - [ - "GTXE2_LOGIC_OUTS_B5_2", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTXE2_IMUX23_2", - "VBRK_EXT_IMUX23" - ], - [ - "GTXE2_IMUX35_2", - "VBRK_EXT_IMUX35" - ], - [ - "GTXE2_LOGIC_OUTS_B23_2", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTXE2_IMUX31_2", - "VBRK_EXT_IMUX31" - ], - [ - "GTXE2_IMUX24_2", - "VBRK_EXT_IMUX24" - ], - [ - "GTXE2_IMUX14_2", - "VBRK_EXT_IMUX14" - ], - [ - "GTXE2_BYP5_2", - "VBRK_EXT_BYP5" - ], - [ - "GTXE2_IMUX30_2", - "VBRK_EXT_IMUX30" - ], - [ - "GTXE2_IMUX3_2", - "VBRK_EXT_IMUX3" - ], - [ - "GTXE2_CLK0_2", - "VBRK_EXT_CLK0" - ], - [ - "GTXE2_IMUX0_2", - "VBRK_EXT_IMUX0" - ], - [ - "GTXE2_IMUX21_2", - "VBRK_EXT_IMUX21" - ], - [ - "GTXE2_BYP4_2", - "VBRK_EXT_BYP4" - ], - [ - "GTXE2_IMUX40_2", - "VBRK_EXT_IMUX40" - ], - [ - "GTXE2_CLK1_2", - "VBRK_EXT_CLK1" - ], - [ - "GTXE2_IMUX8_2", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX36_2", - "VBRK_EXT_IMUX36" - ], - [ - "GTXE2_LOGIC_OUTS_B13_2", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_LOGIC_OUTS_B22_2", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTXE2_LOGIC_OUTS_B7_2", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTXE2_CTRL0_2", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_IMUX12_2", - "VBRK_EXT_IMUX12" - ], - [ - "GTXE2_IMUX37_2", - "VBRK_EXT_IMUX37" - ], - [ - "GTXE2_IMUX5_2", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_IMUX13_2", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_CTRL1_2", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_LOGIC_OUTS_B1_2", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_IMUX47_2", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_IMUX1_2", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_IMUX10_2", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_IMUX7_2", - "VBRK_EXT_IMUX7" - ], - [ - "GTXE2_LOGIC_OUTS_B8_2", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTXE2_FAN3_2", - "VBRK_EXT_FAN3" - ], - [ - "GTXE2_IMUX2_2", - "VBRK_EXT_IMUX2" - ], - [ - "GTXE2_IMUX15_2", - "VBRK_EXT_IMUX15" - ], - [ - "GTXE2_LOGIC_OUTS_B6_2", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTXE2_FAN1_2", - "VBRK_EXT_FAN1" - ], - [ - "GTXE2_LOGIC_OUTS_B11_2", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTXE2_LOGIC_OUTS_B16_2", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTXE2_LOGIC_OUTS_B18_2", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTXE2_IMUX20_2", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_LOGIC_OUTS_B0_2", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTXE2_FAN6_2", - "VBRK_EXT_FAN6" - ], - [ - "GTXE2_FAN4_2", - "VBRK_EXT_FAN4" - ], - [ - "GTXE2_IMUX32_2", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_LOGIC_OUTS_B20_2", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTXE2_LOGIC_OUTS_B2_2", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTXE2_IMUX33_2", - "VBRK_EXT_IMUX33" - ], - [ - "GTXE2_FAN5_2", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_BYP3_2", - "VBRK_EXT_BYP3" - ], - [ - "GTXE2_IMUX4_2", - "VBRK_EXT_IMUX4" - ], - [ - "GTXE2_IMUX17_2", - "VBRK_EXT_IMUX17" - ], - [ - "GTXE2_BYP1_2", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_IMUX34_2", - "VBRK_EXT_IMUX34" - ], - [ - "GTXE2_LOGIC_OUTS_B21_2", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTXE2_IMUX44_2", - "VBRK_EXT_IMUX44" - ], - [ - "GTXE2_IMUX18_2", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_LOGIC_OUTS_B3_2", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTXE2_IMUX28_2", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_IMUX42_2", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_IMUX19_2", - "VBRK_EXT_IMUX19" - ], - [ - "GTXE2_IMUX45_2", - "VBRK_EXT_IMUX45" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_L_BOT_UTURN", - "HCLK_R_BOT_UTURN" - ], - "wire_pairs": [ - [ - "HCLK_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_CK_OUTIN_L2", - "HCLK_CK_INOUT_R2" - ], - [ - "HCLK_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CK_OUTIN_L5", - "HCLK_CK_INOUT_R5" - ], - [ - "HCLK_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_CK_INOUT_L3", - "HCLK_CK_OUTIN_R7" - ], - [ - "HCLK_CK_OUTIN_L6", - "HCLK_CK_INOUT_R6" - ], - [ - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CK_OUTIN_L7", - "HCLK_CK_INOUT_R7" - ], - [ - "HCLK_CK_INOUT_L1", - "HCLK_CK_OUTIN_R5" - ], - [ - "HCLK_CK_OUTIN_L1", - "HCLK_CK_INOUT_R1" - ], - [ - "HCLK_CK_INOUT_L5", - "HCLK_CK_OUTIN_R1" - ], - [ - "HCLK_CK_INOUT_L2", - "HCLK_CK_OUTIN_R6" - ], - [ - "HCLK_CK_OUTIN_L4", - "HCLK_CK_INOUT_R4" - ], - [ - "HCLK_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CK_OUTIN_L3", - "HCLK_CK_INOUT_R3" - ], - [ - "HCLK_CK_INOUT_L6", - "HCLK_CK_OUTIN_R2" - ], - [ - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CK_INOUT_L7", - "HCLK_CK_OUTIN_R3" - ], - [ - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CK_INOUT_L0", - "HCLK_CK_OUTIN_R4" - ], - [ - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CK_OUTIN_L0", - "HCLK_CK_INOUT_R0" - ], - [ - "HCLK_CK_INOUT_L4", - "HCLK_CK_OUTIN_R0" - ], - [ - "HCLK_CK_IN6", - "HCLK_CK_IN6" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_WR1END0_7", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE4B0_7", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_WW4END1_7", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_EE2BEG0_7", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_WL1END2_7", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_NW4END3_7", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_IMUX6_7", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_LH5_7", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_FAN2_7", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_NE4C3_7", - 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"INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SW4END2_7", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_IMUX13_7", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_NE2A1_7", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_WW4A1_7", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_IMUX10_7", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_WW4B1_7", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_IMUX45_7", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_NE4BEG3_7", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE2BEG3_7", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_NW2A3_7", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WL1END1_7", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX26_7", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_EE4A0_7", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_IMUX0_7", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_CTRL1_7", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW2END3_7", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_FAN0_7", - "INT_INTERFACE_FAN0" - ], - [ - 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"INT_INTERFACE_NW2A0" - ], - [ - "CLK_BUFG_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_BUFG_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_BUFG_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_BUFG_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_IOI", - "HCLK_TERM" - ], - "wire_pairs": [ - [ - "HCLK_IOI_CK_BUFHCLK5", - "HCLK_TERM_CK_BUFHCLK5" - ], - [ - "HCLK_IOI_CK_BUFHCLK10", - "HCLK_TERM_CK_BUFHCLK10" - ], - [ - "HCLK_IOI_CK_BUFHCLK6", - "HCLK_TERM_CK_BUFHCLK6" - ], - [ - "HCLK_IOI_CK_BUFRCLK2", - "HCLK_TERM_CK_BUFRCLK2" - ], - [ - "HCLK_IOI_CK_BUFRCLK1", - "HCLK_TERM_CK_BUFRCLK1" - ], - [ - "HCLK_IOI_IOCLK_PLL0", - "HCLK_TERM_PERFCLK0" - ], - [ - "HCLK_IOI_CK_BUFHCLK11", - "HCLK_TERM_CK_BUFHCLK11" - ], - [ - "HCLK_IOI_IOCLK_PLL3", - "HCLK_TERM_PERFCLK3" - ], - [ - "HCLK_IOI_I2IOCLK_TOP1", - "HCLK_TERM_CCIO1" - ], - [ - "HCLK_IOI_CK_BUFRCLK3", - "HCLK_TERM_CK_BUFRCLK3" - ], - [ - "HCLK_IOI_I2IOCLK_BOT1", - "HCLK_TERM_CCIO3" - ], - [ - "HCLK_IOI_CK_BUFRCLK0", - "HCLK_TERM_CK_BUFRCLK0" - ], - [ - "HCLK_IOI_CK_BUFHCLK1", - "HCLK_TERM_CK_BUFHCLK1" - ], - [ - "HCLK_IOI_CK_BUFHCLK2", - "HCLK_TERM_CK_BUFHCLK2" - ], - [ - "HCLK_IOI_CK_BUFHCLK3", - "HCLK_TERM_CK_BUFHCLK3" - ], - [ - "HCLK_IOI_CK_BUFHCLK0", - "HCLK_TERM_CK_BUFHCLK0" - ], - [ - "HCLK_IOI_IOCLK_PLL2", - "HCLK_TERM_PERFCLK2" - ], - [ - "HCLK_IOI_IOCLK_PLL1", - "HCLK_TERM_PERFCLK1" - ], - [ - "HCLK_IOI_I2IOCLK_TOP0", - "HCLK_TERM_CCIO0" - ], - [ - "HCLK_IOI_CK_BUFHCLK8", - "HCLK_TERM_CK_BUFHCLK8" - ], - [ - "HCLK_IOI_CK_BUFHCLK7", - "HCLK_TERM_CK_BUFHCLK7" - ], - [ - "HCLK_IOI_I2IOCLK_BOT0", - "HCLK_TERM_CCIO2" - ], - [ - "HCLK_IOI_CK_BUFHCLK4", - "HCLK_TERM_CK_BUFHCLK4" - ], - [ - "HCLK_IOI_CK_BUFHCLK9", - "HCLK_TERM_CK_BUFHCLK9" - ] - ] - }, - { - "grid_deltas": [ - -1, - 3 - ], - "tile_types": [ - "CMT_TOP_L_LOWER_B", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_EE2A2_5", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_WL1END2_5", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_WW4END0_5", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_LH9_5", - "VBRK_LH9" - ], - [ - "CMT_TOP_WW4B2_5", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_LH3_5", - "VBRK_LH3" - ], - [ - "CMT_TOP_EE4BEG0_5", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW4C0_5", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_SE2A1_5", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_WR1END1_5", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_SW4A2_5", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_WW4END2_5", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_EE4C3_5", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_SW2A0_5", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_NW2A0_5", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_WW4A3_5", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_EE2BEG2_5", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_SE4BEG3_5", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW4C3_5", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_NW2A3_5", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_LH6_5", - "VBRK_LH6" - ], - [ - "CMT_TOP_LH10_5", - "VBRK_LH10" - ], - [ - "CMT_TOP_EE4B3_5", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_SE4BEG1_5", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_WW4END1_5", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_NE4C1_5", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_NE4BEG0_5", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_EE4B1_5", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_WR1END2_5", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_NW4END0_5", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_NE4BEG2_5", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_EE4C0_5", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_ER1BEG3_5", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_NE2A3_5", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_WW4B3_5", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WW2END0_5", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_WW2A1_5", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_SW2A1_5", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_EE4A0_5", - "VBRK_EE4A0" - ], - [ - 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"VBRK_WW4A2" - ], - [ - "CMT_TOP_SE4C2_5", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_WW2A3_5", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_SW4END3_5", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_EE2BEG1_5", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_EL1BEG2_5", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_NE4C3_5", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SE4BEG0_5", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_NW4A1_5", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WR1END0_5", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_EE2A3_5", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_LH1_5", - "VBRK_LH1" - ], - [ - "CMT_TOP_NW4END1_5", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_SW4A3_5", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_SW2A2_5", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_EE2A0_5", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_SE4C1_5", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_EL1BEG3_5", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_EE2A1_5", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_NW4A3_5", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_WW4A1_5", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_SE4BEG2_5", - "VBRK_SE4BEG2" - ], - [ - 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"VBRK_NE2A2" - ], - [ - "CMT_TOP_WW2END1_5", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_EE4C2_5", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_EE4BEG1_5", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_NW4END2_5", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_WW2A0_5", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_SE4C0_5", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_EE2BEG3_5", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_WW2END3_5", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_NE2A1_5", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_EE4B2_5", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_SE2A0_5", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_MONITOR_N_5", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_LH7_5", - "VBRK_LH7" - ], - [ - "CMT_TOP_EE4C1_5", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_LH8_5", - "VBRK_LH8" - ], - [ - "CMT_TOP_WR1END3_5", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_SW4END0_5", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_NE2A0_5", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_SW4A0_5", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_SE2A3_5", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_SW4A1_5", - "VBRK_SW4A1" - ], - [ - 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"CLK_HROW_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_LH5_2", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_LH7_2", - "VBRK_LH7" - ], - [ - "CLK_HROW_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_LH9_2", - "VBRK_LH9" - ], - [ - "CLK_HROW_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH1_2", - "VBRK_LH1" - ], - [ - "CLK_HROW_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_LH10_2", - "VBRK_LH10" - ], - [ - "CLK_HROW_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH6_2", - "VBRK_LH6" - ], - [ - "CLK_HROW_LH8_2", - "VBRK_LH8" - ], - [ - "CLK_HROW_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH11_2", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_LH12_2", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_SW4END2_2", - "VBRK_SW4END2" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_FIFO_L", - "HCLK_INT_INTERFACE" - ], - "wire_pairs": [ - [ - "HCLK_FIFO_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "HCLK_FIFO_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "HCLK_FIFO_PERFCLK3", - "HCLK_INT_INTERFACE_PERFCLK3" - ], - [ - "HCLK_FIFO_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "HCLK_FIFO_CCIO2", - "HCLK_INT_INTERFACE_CCIO2" - ], - [ - "HCLK_FIFO_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "HCLK_FIFO_CCIO1", - "HCLK_INT_INTERFACE_CCIO1" - ], - [ - "HCLK_FIFO_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "HCLK_FIFO_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "HCLK_FIFO_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "HCLK_FIFO_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "HCLK_FIFO_CCIO0", - "HCLK_INT_INTERFACE_CCIO0" - ], - [ - "HCLK_FIFO_CCIO3", - "HCLK_INT_INTERFACE_CCIO3" - ], - [ - "HCLK_FIFO_PERFCLK1", - "HCLK_INT_INTERFACE_PERFCLK1" - ], - [ - "HCLK_FIFO_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "HCLK_FIFO_PERFCLK0", - "HCLK_INT_INTERFACE_PERFCLK0" - ], - [ - "HCLK_FIFO_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ], - [ - "HCLK_FIFO_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "HCLK_FIFO_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "HCLK_FIFO_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "HCLK_FIFO_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], - [ - "HCLK_FIFO_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_FIFO_PERFCLK2", - "HCLK_INT_INTERFACE_PERFCLK2" - ], - [ - "HCLK_FIFO_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ] - ] - }, - { - "grid_deltas": [ - 0, - -10 - ], - "tile_types": [ - "MONITOR_MID_FUJI2", - "MONITOR_TOP_FUJI2" - ], - "wire_pairs": [ - [ - "MONITOR_VERT_VAUXN12", - "MONITOR_VERT_SHORT_VAUXN12" - ], - [ - "MONITOR_VERT_VAUXN11", - "MONITOR_VERT_SHORT_VAUXN11" - ], - [ - "MONITOR_VERT_VAUXN4", - "MONITOR_VERT_SHORT_VAUXN4" - ], - [ - "MONITOR_VERT_VAUXP3", - "MONITOR_VERT_SHORT_VAUXP3" - ], - [ - "MONITOR_VERT_VAUXP10", - "MONITOR_VERT_SHORT_VAUXP10" - ], - [ - "MONITOR_VERT_VAUXN1", - "MONITOR_VERT_SHORT_VAUXN1" - ], - [ - "MONITOR_VERT_VAUXN3", - "MONITOR_VERT_SHORT_VAUXN3" - ], - [ - "MONITOR_VERT_VAUXP0", - "MONITOR_VERT_SHORT_VAUXP0" - ], - [ - "MONITOR_VERT_VAUXP12", - "MONITOR_VERT_SHORT_VAUXP12" - ], - [ - "MONITOR_VERT_VAUXN0", - "MONITOR_VERT_SHORT_VAUXN0" - ], - [ - "MONITOR_VERT_VAUXN2", - "MONITOR_VERT_SHORT_VAUXN2" - ], - [ - "MONITOR_VERT_VAUXN10", - "MONITOR_VERT_SHORT_VAUXN10" - ], - [ - "MONITOR_VERT_VAUXP5", - "MONITOR_VERT_SHORT_VAUXP5" - ], - [ - "MONITOR_VERT_VAUXN9", - "MONITOR_VERT_SHORT_VAUXN9" - ], - [ - "MONITOR_VERT_VAUXP2", - "MONITOR_VERT_SHORT_VAUXP2" - ], - [ - "MONITOR_VERT_VAUXP11", - "MONITOR_VERT_SHORT_VAUXP11" - ], - [ - "MONITOR_VERT_VAUXP4", - "MONITOR_VERT_SHORT_VAUXP4" - ], - [ - "MONITOR_VERT_VAUXN8", - "MONITOR_VERT_SHORT_VAUXN8" - ], - [ - "MONITOR_VERT_VAUXN5", - "MONITOR_VERT_SHORT_VAUXN5" - ], - [ - "MONITOR_VERT_VAUXP1", - "MONITOR_VERT_SHORT_VAUXP1" - ], - [ - "MONITOR_VERT_VAUXP8", - "MONITOR_VERT_SHORT_VAUXP8" - ], - [ - "MONITOR_VERT_VAUXP9", - "MONITOR_VERT_SHORT_VAUXP9" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "BRKH_CLK", - "CLK_BUFG_TOP_R" - ], - "wire_pairs": [ - [ - "BRKH_CLK_R_CK_GCLK30", - "CLK_BUFG_CK_GCLK30" - ], - [ - "BRKH_CLK_R_CK_GCLK11", - "CLK_BUFG_CK_GCLK11" - ], - [ - "BRKH_CLK_R_CK_GCLK19", - "CLK_BUFG_CK_GCLK19" - ], - [ - "BRKH_CLK_R_CK_GCLK3", - "CLK_BUFG_CK_GCLK3" - ], - [ - "BRKH_CLK_R_CK_GCLK21", - "CLK_BUFG_CK_GCLK21" - ], - [ - "BRKH_CLK_R_CK_GCLK6", - "CLK_BUFG_CK_GCLK6" - ], - [ - "BRKH_CLK_R_CK_GCLK23", - "CLK_BUFG_CK_GCLK23" - ], - [ - "BRKH_CLK_R_CK_GCLK29", - "CLK_BUFG_CK_GCLK29" - ], - [ - "BRKH_CLK_R_CK_GCLK28", - "CLK_BUFG_CK_GCLK28" - ], - [ - "BRKH_CLK_R_CK_GCLK25", - "CLK_BUFG_CK_GCLK25" - ], - [ - "BRKH_CLK_R_CK_GCLK8", - "CLK_BUFG_CK_GCLK8" - ], - [ - "BRKH_CLK_R_CK_GCLK12", - "CLK_BUFG_CK_GCLK12" - ], - [ - "BRKH_CLK_R_CK_GCLK22", - "CLK_BUFG_CK_GCLK22" - ], - [ - "BRKH_CLK_R_CK_GCLK9", - "CLK_BUFG_CK_GCLK9" - ], - [ - "BRKH_CLK_R_CK_GCLK15", - "CLK_BUFG_CK_GCLK15" - ], - [ - "BRKH_CLK_R_CK_GCLK27", - "CLK_BUFG_CK_GCLK27" - ], - [ - "BRKH_CLK_R_CK_GCLK16", - "CLK_BUFG_CK_GCLK16" - ], - [ - "BRKH_CLK_R_CK_GCLK10", - "CLK_BUFG_CK_GCLK10" - ], - [ - "BRKH_CLK_R_CK_GCLK14", - "CLK_BUFG_CK_GCLK14" - ], - [ - "BRKH_CLK_R_CK_GCLK26", - "CLK_BUFG_CK_GCLK26" - ], - [ - "BRKH_CLK_R_CK_GCLK7", - "CLK_BUFG_CK_GCLK7" - ], - [ - "BRKH_CLK_R_CK_GCLK31", - "CLK_BUFG_CK_GCLK31" - ], - [ - "BRKH_CLK_R_CK_GCLK17", - "CLK_BUFG_CK_GCLK17" - ], - [ - "BRKH_CLK_R_CK_GCLK1", - "CLK_BUFG_CK_GCLK1" - ], - [ - "BRKH_CLK_R_CK_GCLK18", - "CLK_BUFG_CK_GCLK18" - ], - [ - "BRKH_CLK_R_CK_GCLK0", - "CLK_BUFG_CK_GCLK0" - ], - [ - "BRKH_CLK_R_CK_GCLK5", - "CLK_BUFG_CK_GCLK5" - ], - [ - "BRKH_CLK_R_CK_GCLK4", - "CLK_BUFG_CK_GCLK4" - ], - [ - "BRKH_CLK_R_CK_GCLK20", - "CLK_BUFG_CK_GCLK20" - ], - [ - "BRKH_CLK_R_CK_GCLK2", - "CLK_BUFG_CK_GCLK2" - ], - [ - "BRKH_CLK_R_CK_GCLK24", - "CLK_BUFG_CK_GCLK24" - ], - [ - "BRKH_CLK_R_CK_GCLK13", - "CLK_BUFG_CK_GCLK13" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CMT_FIFO_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CMT_FIFO_WL1END0_6", - "INT_INTERFACE_WL1END0" - ], - [ - "CMT_FIFO_NW4END1_6", - "INT_INTERFACE_NW4END1" - ], - [ - "CMT_FIFO_SE2A1_6", - "INT_INTERFACE_SE2A1" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS19_6", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "CMT_FIFO_L_IMUX19_6", - "INT_INTERFACE_IMUX19" - ], - [ - "CMT_FIFO_L_IMUX6_6", - "INT_INTERFACE_IMUX6" - ], - [ - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV" - ], - [ - "CMT_FIFO_L_IMUX39_6", - "INT_INTERFACE_IMUX39" - ], - [ - "CMT_FIFO_L_FAN4_6", - "INT_INTERFACE_FAN4" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS4_6", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CMT_FIFO_EE2A1_6", - "INT_INTERFACE_EE2A1" - ], - [ - "CMT_FIFO_SW4END2_6", - "INT_INTERFACE_SW4END2" - ], - [ - "CMT_FIFO_EL1BEG0_6", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CMT_FIFO_L_IMUX9_6", - "INT_INTERFACE_IMUX9" - ], - [ - "CMT_FIFO_EE4BEG3_6", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CMT_FIFO_L_IMUX25_6", - "INT_INTERFACE_IMUX25" - ], - [ - "CMT_FIFO_L_IMUX45_6", - "INT_INTERFACE_IMUX45" - ], - [ - "CMT_FIFO_EE4B0_6", - "INT_INTERFACE_EE4B0" - ], - [ - "CMT_FIFO_L_IMUX7_6", - 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"CLK_HROW_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_LH2_0", - "VBRK_LH2" - ], - [ - "CLK_HROW_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH9_0", - "VBRK_LH9" - ] - ] - }, - { - "grid_deltas": [ - -1, - -3 - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_BUFG_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_BUFG_IMUX33_3", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WL1END3_3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_SW2A1_3", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_FAN6_3", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4END0_3", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_NE4C1_3", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_NW2A2_3", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WW4C3_3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_BUFG_IMUX8_3", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WW4B2_3", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_SW4END0_3", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_NE2A0_3", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_LH11_3", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE4A0_3", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "CLK_BUFG_IMUX37_3", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_WW4B0_3", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_SW4A0_3", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_3", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_BUFG_IMUX36_3", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_BUFG_IMUX26_3", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_WW4A2_3", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW4END2_3", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_BUFG_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_BUFG_IMUX0_3", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_WW4C2_3", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_CLK1_3", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_SE4C1_3", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_BUFG_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_3", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_BYP7_3", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WW2END0_3", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_EE4C3_3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_BUFG_IMUX19_3", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_LH7_3", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_EE4A1_3", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_NW4END3_3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_IMUX10_3", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_IMUX40_3", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_EE4B2_3", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_BUFG_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_CLK0_3", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_FAN7_3", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW2A2_3", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_EE4B0_3", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_BUFG_IMUX7_3", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_BUFG_IMUX41_3", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_3", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_BUFG_IMUX14_3", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_EE2A1_3", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_BUFG_IMUX30_3", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_IMUX11_3", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_3", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_BUFG_IMUX45_3", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_BUFG_IMUX9_3", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_BUFG_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_3", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_EE4C0_3", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4A1_3", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_NW4END0_3", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_NE2A3_3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_SE2A1_3", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_IMUX22_3", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_BYP5_3", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_BUFG_IMUX27_3", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_3", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_HROW_WW4C1_3", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_NW4A2_3", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW2END3_3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_BUFG_IMUX43_3", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_MONITOR_N_3", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_SE4C3_3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_BYP3_3", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE2A1_3", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_NE4C3_3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_BUFG_IMUX20_3", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_MONITOR_P_3", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_NW2A1_3", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_3", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_BUFG_IMUX21_3", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_BUFG_IMUX39_3", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_WL1END0_3", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_BUFG_IMUX18_3", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_NE2A2_3", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_BUFG_IMUX4_3", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WR1END1_3", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_SE4C2_3", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW4B3_3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_BUFG_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_BUFG_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW2END2_3", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_FAN3_3", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW2A0_3", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE4B1_3", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_WW2A1_3", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_WL1END1_3", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_SW4A3_3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_BYP1_3", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_WW2A3_3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SE4C0_3", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_3", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_HROW_WW4C0_3", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_NW2A3_3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_BUFG_IMUX47_3", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_SE4BEG2_3", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_BUFG_IMUX38_3", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_BUFG_IMUX3_3", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_EE4C1_3", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_BUFG_IMUX24_3", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_BUFG_IMUX1_3", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_WW2A0_3", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_FAN0_3", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_WR1END0_3", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_NE4C0_3", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_BUFG_IMUX6_3", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_BYP0_3", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_FAN5_3", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_WW4END2_3", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_SE2A3_3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_SE2A2_3", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_SW2A2_3", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_EE4BEG0_3", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_BUFG_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_LH1_3", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_SE4BEG1_3", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_WR1END2_3", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW2END1_3", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_BUFG_IMUX5_3", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_BUFG_IMUX25_3", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_SW4END1_3", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_LH8_3", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_NE4BEG3_3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_BUFG_IMUX35_3", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_EE2A3_3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_BUFG_IMUX44_3", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_BUFG_IMUX17_3", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_EE2A0_3", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_NE4C2_3", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_EE4B3_3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_BUFG_IMUX42_3", - "INT_INTERFACE_IMUX42" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "BRKH_CLB", - "CLBLM_L" - ], - "wire_pairs": [ - [ - "BRKH_CLB_COUT1_L", - "CLBLM_L_CIN" - ], - [ - "BRKH_CLB_COUT0_L", - "CLBLM_M_CIN" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "CLK_FEED", - "CLK_HROW_TOP_R" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_HROW_TOP_R_CK_BUFG_CASCO31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_HROW_TOP_R_CK_BUFG_CASCO24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_HROW_TOP_R_CK_BUFG_CASCO8" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_HROW_TOP_R_CK_BUFG_CASCO2" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_HROW_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_HROW_TOP_R_CK_BUFG_CASCO4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_HROW_TOP_R_CK_BUFG_CASCO13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_HROW_TOP_R_CK_BUFG_CASCO22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_HROW_TOP_R_CK_BUFG_CASCO25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_HROW_TOP_R_CK_BUFG_CASCO27" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_HROW_TOP_R_CK_BUFG_CASCO15" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_HROW_TOP_R_CK_BUFG_CASCO1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_HROW_TOP_R_CK_BUFG_CASCO6" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_HROW_TOP_R_CK_BUFG_CASCO30" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_HROW_TOP_R_CK_BUFG_CASCO11" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_HROW_TOP_R_CK_BUFG_CASCO12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_HROW_TOP_R_CK_BUFG_CASCO29" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_HROW_TOP_R_CK_BUFG_CASCO16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_HROW_TOP_R_CK_BUFG_CASCO19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO7" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_HROW_TOP_R_CK_BUFG_CASCO28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_HROW_TOP_R_CK_BUFG_CASCO10" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_HROW_TOP_R_CK_BUFG_CASCO26" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_HROW_TOP_R_CK_BUFG_CASCO14" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_HROW_TOP_R_CK_BUFG_CASCO17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_HROW_TOP_R_CK_BUFG_CASCO9" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_HROW_TOP_R_CK_BUFG_CASCO21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_HROW_TOP_R_CK_BUFG_CASCO3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_HROW_TOP_R_CK_BUFG_CASCO20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO0" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_HROW_TOP_R_CK_BUFG_CASCO23" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_HROW_TOP_R_CK_BUFG_CASCO18" - ] - ] - }, - { - "grid_deltas": [ - -1, - 1 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_IMUX8_3", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WL1END3_3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_SW2A1_3", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_FAN6_3", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4END0_3", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_NE4C1_3", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_NW2A2_3", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_IMUX33_3", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX9_3", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX26_3", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WW4C3_3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WW4B2_3", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_SW4END0_3", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_NE2A0_3", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_LH11_3", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE4A0_3", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WW4B0_3", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_SW4A0_3", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_WW4A2_3", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_IMUX24_3", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW4END2_3", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_IMUX4_3", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WW4C2_3", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_CLK1_3", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_SE4C1_3", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_BYP7_3", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WW2END0_3", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_EE4C3_3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_LH7_3", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_EE4A1_3", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_IMUX30_3", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_IMUX37_3", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_NW4END3_3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_IMUX11_3", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_EE4B2_3", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_CLK0_3", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_FAN7_3", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW2A2_3", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_EE4B0_3", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_IMUX7_3", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE2A1_3", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_EE4C0_3", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4A1_3", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_NW4END0_3", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_NE2A3_3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX10_3", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_IMUX38_3", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX5_3", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX25_3", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_IMUX45_3", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SE2A1_3", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX21_3", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX27_3", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_BYP5_3", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_WW4C1_3", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_IMUX6_3", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_IMUX42_3", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_NW4A2_3", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW2END3_3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_SE4C3_3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_BYP3_3", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE2A1_3", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_NE4C3_3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX17_3", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_NW2A1_3", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_IMUX44_3", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_WL1END0_3", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_NE2A2_3", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_WR1END1_3", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_IMUX35_3", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SE4C2_3", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_IMUX18_3", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_WW2END2_3", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_FAN3_3", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_IMUX0_3", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX47_3", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW2A0_3", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE4B1_3", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_WW2A1_3", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_WL1END1_3", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_SW4A3_3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_BYP1_3", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_WW2A3_3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SE4C0_3", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_WW4C0_3", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_NW2A3_3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_SE4BEG2_3", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_EE4C1_3", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_WW2A0_3", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_FAN0_3", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX43_3", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_WR1END0_3", - "INT_INTERFACE_WR1END0" - ], - [ - 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"PCIE_INT_INTERFACE_IMUX_L_OUT34" - ], - [ - "PCIE_WW4B1_13", - "INT_INTERFACE_WW4B1" - ], - [ - "PCIE_WR1END2_13", - "INT_INTERFACE_WR1END2" - ], - [ - "PCIE_ER1BEG0_13", - "INT_INTERFACE_ER1BEG0" - ], - [ - "PCIE_NW2A0_13", - "INT_INTERFACE_NW2A0" - ], - [ - "PCIE_LOGIC_OUTS_B23_L_13", - "INT_INTERFACE_LOGIC_OUTS_L_B23" - ], - [ - "PCIE_EE2BEG3_13", - "INT_INTERFACE_EE2BEG3" - ], - [ - "PCIE_EE4BEG0_13", - "INT_INTERFACE_EE4BEG0" - ], - [ - "PCIE_MONITOR_P_13", - "INT_INTERFACE_MONITOR_P" - ], - [ - "PCIE_IMUX0_L_13", - "PCIE_INT_INTERFACE_IMUX_L_OUT0" - ], - [ - "PCIE_LOGIC_OUTS_B10_L_13", - "INT_INTERFACE_LOGIC_OUTS_L_B10" - ], - [ - "PCIE_NE2A0_13", - "INT_INTERFACE_NE2A0" - ], - [ - "PCIE_NW4END3_13", - "INT_INTERFACE_NW4END3" - ], - [ - "PCIE_NW4END2_13", - "INT_INTERFACE_NW4END2" - ], - [ - "PCIE_BYP6_L_13", - "INT_INTERFACE_BYP6" - ], - [ - "PCIE_EE4C0_13", - "INT_INTERFACE_EE4C0" - ], - [ - "PCIE_EE2A1_13", - "INT_INTERFACE_EE2A1" - ], - [ - "PCIE_WW4A3_13", - "INT_INTERFACE_WW4A3" - ], - [ - "PCIE_WL1END2_13", - "INT_INTERFACE_WL1END2" - ], - [ - "PCIE_SW4A0_13", - "INT_INTERFACE_SW4A0" - ], - [ - "PCIE_SE4C3_13", - "INT_INTERFACE_SE4C3" - ], - [ - "PCIE_NW4A1_13", - "INT_INTERFACE_NW4A1" - ], - [ - "PCIE_SE4BEG1_13", - "INT_INTERFACE_SE4BEG1" - ], - [ - "PCIE_FAN5_L_13", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_FAN2_L_13", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_IMUX19_L_13", - "PCIE_INT_INTERFACE_IMUX_L_OUT19" - ], - [ - "PCIE_WW4END0_13", - "INT_INTERFACE_WW4END0" - ], - [ - "PCIE_LOGIC_OUTS_B21_L_13", - "INT_INTERFACE_LOGIC_OUTS_L_B21" - ], - [ - "PCIE_NW4A2_13", - "INT_INTERFACE_NW4A2" - ], - [ - "PCIE_NW2A3_13", - "INT_INTERFACE_NW2A3" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "DSP_R", - "HCLK_DSP_R" - ], - "wire_pairs": [ - [ - "DSP_0_ACIN0", - "HCLK_DSP_ACIN0" - ], - [ - "DSP_0_PCIN13", - "HCLK_DSP_PCIN13" - ], - [ - "DSP_0_PCIN16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_0_BCIN4", - "HCLK_DSP_BCIN4" - ], - [ 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"HCLK_DSP_PCIN28" - ], - [ - "DSP_0_ACIN25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_0_PCIN18", - "HCLK_DSP_PCIN18" - ], - [ - "DSP_0_ACIN16", - "HCLK_DSP_ACIN16" - ], - [ - "DSP_0_PCIN31", - "HCLK_DSP_PCIN31" - ], - [ - "DSP_0_ACIN21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_0_BCIN15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_0_PCIN15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_0_ACIN19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_0_ACIN18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_0_PCIN23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_0_PCIN34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_0_ACIN3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_0_PCIN5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_0_PCIN26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_0_BCIN9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_0_ACIN28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_0_PCIN29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_0_PCIN10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_0_ACIN2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_0_PCIN40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_0_ACIN17", - "HCLK_DSP_ACIN17" - ], - [ - "DSP_0_PCIN14", - "HCLK_DSP_PCIN14" - ], - [ - "DSP_0_PCIN33", - "HCLK_DSP_PCIN33" - ], - [ - "DSP_0_PCIN35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_0_BCIN14", - "HCLK_DSP_BCIN14" - ], - [ - "DSP_0_PCIN39", - "HCLK_DSP_PCIN39" - ], - [ - "DSP_0_PCIN42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_0_PCIN1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_0_PCIN45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_0_BCIN16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_0_BCIN6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_0_ACIN26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_0_ACIN20", - "HCLK_DSP_ACIN20" - ], - [ - "DSP_0_PCIN9", - "HCLK_DSP_PCIN9" - ], - [ - "DSP_0_MULTSIGNIN", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_0_BCIN11", - "HCLK_DSP_BCIN11" - ], - [ - "DSP_0_PCIN19", - "HCLK_DSP_PCIN19" - ], - [ - "DSP_0_PCIN41", - "HCLK_DSP_PCIN41" - ], - [ - "DSP_0_PCIN21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_0_ACIN15", - "HCLK_DSP_ACIN15" - ], - [ - "DSP_0_PCIN17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_0_ACIN22", - "HCLK_DSP_ACIN22" - ], - [ - "DSP_0_ACIN11", - "HCLK_DSP_ACIN11" - ], - [ - "DSP_0_PCIN43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_0_ACIN14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_0_BCIN0", - "HCLK_DSP_BCIN0" - ], - [ - "DSP_0_BCIN7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_0_PCIN7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_0_PCIN6", - "HCLK_DSP_PCIN6" - ], - [ - "DSP_0_PCIN11", - "HCLK_DSP_PCIN11" - ], - [ - "DSP_0_BCIN3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_0_PCIN46", - "HCLK_DSP_PCIN46" - ], - [ - "DSP_0_ACIN10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_0_BCIN5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_0_ACIN12", - "HCLK_DSP_ACIN12" - ], - [ - "DSP_0_PCIN44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_0_ACIN29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_0_PCIN3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_0_PCIN47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_0_ACIN27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_0_ACIN23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_0_ACIN5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_0_PCIN32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_0_PCIN20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_0_ACIN24", - "HCLK_DSP_ACIN24" - ], - [ - "DSP_0_ACIN8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_0_BCIN8", - "HCLK_DSP_BCIN8" - ], - [ - "DSP_0_ACIN7", - "HCLK_DSP_ACIN7" - ], - [ - "DSP_0_ACIN13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_0_PCIN24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_0_PCIN30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_0_PCIN36", - "HCLK_DSP_PCIN36" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_DSP_R", - "HCLK_INT_INTERFACE" - ], - "wire_pairs": [ - [ - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], - [ - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "HCLK_DSP_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN10" - ], - [ - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "HCLK_DSP_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN9" - ], - [ - "HCLK_DSP_CK_IN3", - "HCLK_INT_INTERFACE_CK_IN3" - ], - [ - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "HCLK_DSP_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN6" - ], - [ - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "HCLK_DSP_CK_IN2", - "HCLK_INT_INTERFACE_CK_IN2" - ], - [ - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "HCLK_DSP_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN4" - ], - [ - "HCLK_DSP_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ], - [ - "HCLK_DSP_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN8" - ], - [ - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "HCLK_DSP_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "HCLK_DSP_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN0" - ], - [ - "HCLK_DSP_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN7" - ], - [ - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "HCLK_DSP_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN11" - ], - [ - "HCLK_DSP_CK_IN1", - "HCLK_INT_INTERFACE_CK_IN1" - ], - [ - "HCLK_DSP_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN5" - ] - ] - }, - { - "grid_deltas": [ - -1, - -3 - ], - "tile_types": [ - "CFG_CENTER_BOT", - "INT_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "CFG_CENTER_NW2A1_13", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_SE2A2_13", - "INT_FEEDTHRU_2_SE2A2" - ], - [ - "CFG_CENTER_EE4B2_13", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_NE4C1_13", - "INT_FEEDTHRU_2_NE4C1" - ], - [ - "CFG_CENTER_EE2BEG1_13", - "INT_FEEDTHRU_2_EE2BEG1" - ], - [ - "CFG_CENTER_WW2END2_13", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - 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"CLBLM_NE4BEG0" - ], - [ - "BRAM_SE4BEG2_4", - "CLBLM_SE4BEG2" - ], - [ - "BRAM_LH4_4", - "CLBLM_LH4" - ], - [ - "BRAM_SE4C0_4", - "CLBLM_SE4C0" - ], - [ - "BRAM_NW4END1_4", - "CLBLM_NW4END1" - ], - [ - "BRAM_SW4END3_4", - "CLBLM_SW4END3" - ], - [ - "BRAM_LH3_4", - "CLBLM_LH3" - ], - [ - "BRAM_WW4B1_4", - "CLBLM_WW4B1" - ], - [ - "BRAM_NW4END0_4", - "CLBLM_NW4END0" - ], - [ - "BRAM_WW2END0_4", - "CLBLM_WW2END0" - ], - [ - "BRAM_SE4C2_4", - "CLBLM_SE4C2" - ], - [ - "BRAM_EE4A3_4", - "CLBLM_EE4A3" - ], - [ - "BRAM_NE2A3_4", - "CLBLM_NE2A3" - ], - [ - "BRAM_SW4A3_4", - "CLBLM_SW4A3" - ], - [ - "BRAM_WW2A1_4", - "CLBLM_WW2A1" - ], - [ - "BRAM_SW4END1_4", - "CLBLM_SW4END1" - ], - [ - "BRAM_LH8_4", - "CLBLM_LH8" - ], - [ - "BRAM_WW2A0_4", - "CLBLM_WW2A0" - ], - [ - "BRAM_LH5_4", - "CLBLM_LH5" - ], - [ - "BRAM_EE4C1_4", - "CLBLM_EE4C1" - ], - [ - "BRAM_WL1END2_4", - "CLBLM_WL1END2" - ], - [ - "BRAM_WL1END0_4", - "CLBLM_WL1END0" - ], - [ - "BRAM_EL1BEG1_4", - "CLBLM_EL1BEG1" - ], - [ - "BRAM_LH2_4", - "CLBLM_LH2" - ], - [ - "BRAM_LH1_4", - "CLBLM_LH1" - ], - [ - "BRAM_NW4A3_4", - "CLBLM_NW4A3" - ], - [ - "BRAM_SW2A3_4", - "CLBLM_SW2A3" - ], - [ - "BRAM_EE2BEG3_4", - "CLBLM_EE2BEG3" - ], - [ - "BRAM_EE4A1_4", - "CLBLM_EE4A1" - ], - [ - "BRAM_SE4BEG3_4", - "CLBLM_SE4BEG3" - ], - [ - "BRAM_EE4B1_4", - "CLBLM_EE4B1" - ], - [ - "BRAM_EL1BEG2_4", - "CLBLM_EL1BEG2" - ], - [ - "BRAM_WW4A2_4", - "CLBLM_WW4A2" - ], - [ - "BRAM_WW4C2_4", - "CLBLM_WW4C2" - ], - [ - "BRAM_EE2A2_4", - "CLBLM_EE2A2" - ], - [ - "BRAM_EE4BEG0_4", - "CLBLM_EE4BEG0" - ], - [ - "BRAM_WW2END1_4", - "CLBLM_WW2END1" - ], - [ - "BRAM_ER1BEG1_4", - "CLBLM_ER1BEG1" - ], - [ - "BRAM_SE4BEG1_4", - "CLBLM_SE4BEG1" - ], - [ - "BRAM_EE2BEG2_4", - "CLBLM_EE2BEG2" - ], - [ - "BRAM_SE4C3_4", - "CLBLM_SE4C3" - ], - [ - "BRAM_SE4BEG0_4", - "CLBLM_SE4BEG0" - ], - [ - "BRAM_ER1BEG3_4", - "CLBLM_ER1BEG3" - ], - [ - "BRAM_NE4C0_4", - "CLBLM_NE4C0" - ], - [ - "BRAM_WW4B2_4", - "CLBLM_WW4B2" - ], - [ - "BRAM_LH10_4", - "CLBLM_LH10" - ], - [ - "BRAM_LH11_4", - "CLBLM_LH11" - ], - [ - "BRAM_EE4C2_4", - "CLBLM_EE4C2" - ], - [ - "BRAM_WW4C0_4", - "CLBLM_WW4C0" - ], - [ - "BRAM_WW4A1_4", - "CLBLM_WW4A1" - ], - [ - "BRAM_EE2A1_4", - "CLBLM_EE2A1" - ], - [ - "BRAM_WR1END3_4", - "CLBLM_WR1END3" - ], - [ - "BRAM_NE4BEG2_4", - "CLBLM_NE4BEG2" - ], - [ - "BRAM_SW4A2_4", - "CLBLM_SW4A2" - ], - [ - "BRAM_NE2A1_4", - "CLBLM_NE2A1" - ], - [ - "BRAM_EE2A0_4", - "CLBLM_EE2A0" - ], - [ - "BRAM_SW2A2_4", - "CLBLM_SW2A2" - ], - [ - "BRAM_EE4B2_4", - "CLBLM_EE4B2" - ], - [ - "BRAM_WR1END2_4", - "CLBLM_WR1END2" - ], - [ - "BRAM_NE4BEG1_4", - "CLBLM_NE4BEG1" - ], - [ - "BRAM_WW2END2_4", - "CLBLM_WW2END2" - ], - [ - "BRAM_WW4END3_4", - "CLBLM_WW4END3" - ], - [ - "BRAM_NW2A1_4", - "CLBLM_NW2A1" - ], - [ - "BRAM_WR1END1_4", - "CLBLM_WR1END1" - ], - [ - "BRAM_SW2A1_4", - "CLBLM_SW2A1" - ], - [ - "BRAM_NE4C2_4", - "CLBLM_NE4C2" - ], - [ - "BRAM_EE4BEG3_4", - "CLBLM_EE4BEG3" - ], - [ - "BRAM_NE2A0_4", - "CLBLM_NE2A0" - ], - [ - "BRAM_SE2A1_4", - "CLBLM_SE2A1" - ], - [ - "BRAM_ER1BEG2_4", - "CLBLM_ER1BEG2" - ], - [ - "BRAM_NW4END3_4", - "CLBLM_NW4END3" - ], - [ - "BRAM_EE4C0_4", - "CLBLM_EE4C0" - ], - [ - "BRAM_SW4A0_4", - "CLBLM_SW4A0" - ], - [ - "BRAM_NW4A0_4", - "CLBLM_NW4A0" - ], - [ - "BRAM_NW2A0_4", - "CLBLM_NW2A0" - ], - [ - "BRAM_EE4B3_4", - "CLBLM_EE4B3" - ], - [ - "BRAM_WW2A2_4", - "CLBLM_WW2A2" - ], - [ - "BRAM_EE4A0_4", - "CLBLM_EE4A0" - ], - [ - "BRAM_NE4BEG3_4", - "CLBLM_NE4BEG3" - ], - [ - "BRAM_WW4B0_4", - "CLBLM_WW4B0" - ], - [ - "BRAM_NE4C1_4", - "CLBLM_NE4C1" - ], - [ - "BRAM_EE4B0_4", - "CLBLM_EE4B0" - ], - [ - "BRAM_ER1BEG0_4", - "CLBLM_ER1BEG0" - ], - [ - "BRAM_LH12_4", - "CLBLM_LH12" - ], - [ - "BRAM_SE2A3_4", - "CLBLM_SE2A3" - ], - [ - "BRAM_EE2A3_4", - "CLBLM_EE2A3" - ], - [ - "BRAM_EE4BEG2_4", - "CLBLM_EE4BEG2" - ], - [ - "BRAM_WW4C1_4", - "CLBLM_WW4C1" - ], - [ - "BRAM_WW2END3_4", - "CLBLM_WW2END3" - ], - [ - "BRAM_EL1BEG3_4", - "CLBLM_EL1BEG3" - ], - [ - "BRAM_SE4C1_4", - "CLBLM_SE4C1" - ], - [ - "BRAM_WW2A3_4", - "CLBLM_WW2A3" - ], - [ - "BRAM_WR1END0_4", - "CLBLM_WR1END0" - ], - [ - "BRAM_SW2A0_4", - "CLBLM_SW2A0" - ], - [ - "BRAM_MONITOR_P_4", - "CLBLM_MONITOR_P" - ], - [ - "BRAM_SE2A2_4", - "CLBLM_SE2A2" - ], - [ - "BRAM_NW4A1_4", - "CLBLM_NW4A1" - ], - [ - "BRAM_WW4A0_4", - "CLBLM_WW4A0" - ], - [ - "BRAM_WW4END0_4", - "CLBLM_WW4END0" - ], - [ - "BRAM_EE4BEG1_4", - "CLBLM_EE4BEG1" - ], - [ - "BRAM_EL1BEG0_4", - "CLBLM_EL1BEG0" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "BRKH_INT", - "INT_L" - ], - "wire_pairs": [ - [ - "BRKH_INT_L_LV3", - "LV_L4" - ], - [ - "BRKH_INT_NW6A2", - "NW6B2" - ], - [ - "BRKH_INT_WR1BEG_S0", - "WR1BEG0" - ], - [ - "BRKH_INT_NE6B2", - "NE6C2" - ], - [ - "BRKH_INT_SR1END2_SLOW", - "SR1BEG2" - ], - [ - "BRKH_INT_NE6A0", - "NE6B0" - ], - [ - "BRKH_INT_NW6B3", - "NW6C3" - ], - [ - "BRKH_INT_SS2END0", - "SS2A0" - ], - [ - "BRKH_INT_SW6C2", - "SW6B2" - ], - [ - "BRKH_INT_SW6B0", - "SW6A0" - ], - [ - "BRKH_INT_NE2BEG2", - "NE2A2" - ], - [ - "BRKH_INT_LVB_L11", - "LVB_L11" - ], - [ - "BRKH_INT_BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" - ], - [ - "BRKH_INT_SS2END3", - "SS2A3" - ], - [ - "BRKH_INT_SL1END3_SLOW", - "SL1BEG3" - ], - [ - "BRKH_INT_WW4END_S0_0", - "WW4END0" - ], - [ - "BRKH_INT_BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "BRKH_INT_NW6B1", - "NW6C1" - ], - [ - "BRKH_INT_NN6D2", - "NN6E2" - ], - [ - "BRKH_INT_L_LV2", - "LV_L3" - ], - [ - "BRKH_INT_SS6D1", - "SS6C1" - ], - [ - "BRKH_INT_LVB_L9", - "LVB_L9" - ], - [ - "BRKH_INT_NN6BEG1", - "NN6A1" - ], - [ - "BRKH_INT_NE6A1", - "NE6B1" - ], - [ - "BRKH_INT_NN6A1", - "NN6B1" - ], - [ - "BRKH_INT_NW6A1", - "NW6B1" - ], - [ - "BRKH_INT_SS2A1", - "SS2BEG1" - ], - [ - "BRKH_INT_NN6E3", - "NN6END3" - ], - [ - "BRKH_INT_NN6C1", - "NN6D1" - ], - [ - "BRKH_INT_SW6D1", - "SW6C1" - ], - [ - "BRKH_INT_SW6D0", - "SW6C0" - ], - [ - "BRKH_INT_NN6B2", - "NN6C2" - ], - [ - "BRKH_INT_SE2A0", - "SE2BEG0" - ], - [ - "BRKH_INT_SS6END3", - "SS6E3" - ], - [ - "BRKH_INT_SS6D0", - "SS6C0" - ], - [ - "BRKH_INT_SW6C1", - "SW6B1" - ], - [ - "BRKH_INT_SW6B2", - "SW6A2" - ], - [ - "BRKH_INT_SE6C2", - "SE6B2" - ], - [ - "BRKH_INT_NE2BEG3", - "NE2A3" - ], - [ - "BRKH_INT_SS6A0", - "SS6BEG0" - ], - [ - "BRKH_INT_LVB_L12", - "LVB_L12" - ], - [ - "BRKH_INT_L_LV17", - "LV_L18" - ], - [ - "BRKH_INT_NN6D3", - "NN6E3" - ], - [ - "BRKH_INT_L_LV6", - "LV_L7" - ], - [ - "BRKH_INT_EL1END_S3_0", - "EL1END0" - ], - [ - "BRKH_INT_NW6C2", - "NW6D2" - ], - [ - "BRKH_INT_NN6D0", - "NN6E0" - ], - [ - "BRKH_INT_SS6END0", - "SS6E0" - ], - [ - "BRKH_INT_NW6D1", - "NW6E1" - ], - [ - "BRKH_INT_SS6E3", - "SS6D3" - ], - [ - "BRKH_INT_SW6C0", - "SW6B0" - ], - [ - "BRKH_INT_NN2A2", - "NN2END2" - ], - [ - "BRKH_INT_LVB_L4", - "LVB_L4" - ], - [ - "BRKH_INT_WL1END3", - "WL1END_N1_3" - ], - [ - "BRKH_INT_LVB_L8", - "LVB_L8" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_4", - "FAN_BOUNCE4" - ], - [ - "BRKH_INT_NL1BEG1_SLOW", - "NL1END1" - ], - [ - "BRKH_INT_NN2END_S2_0", - "NN2END0" - ], - [ - "BRKH_INT_NE6C3", - "NE6D3" - ], - [ - "BRKH_INT_NN6E0", - "NN6END0" - ], - [ - "BRKH_INT_SW2A3", - "SW2BEG3" - ], - [ - "BRKH_INT_SW6E3", - "SW6D3" - ], - [ - "BRKH_INT_NW6D0", - "NW6E0" - ], - [ - "BRKH_INT_SE6C0", - "SE6B0" - ], - [ - "BRKH_INT_SS6D2", - "SS6C2" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_2", - "FAN_BOUNCE2" - ], - [ - "BRKH_INT_NE2BEG1", - "NE2A1" - ], - [ - "BRKH_INT_L_LV7", - "LV_L8" - ], - [ - "BRKH_INT_NW6C0", - "NW6D0" - ], - [ - "BRKH_INT_L_LV13", - "LV_L14" - ], - [ - "BRKH_INT_SS2END1", - "SS2A1" - ], - [ - "BRKH_INT_SE6E1", - "SE6D1" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_6", - "FAN_BOUNCE6" - ], - [ - "BRKH_INT_NW6A0", - "NW6B0" - ], - [ - "BRKH_INT_NE2BEG0", - "NE2A0" - ], - [ - "BRKH_INT_SE6D2", - "SE6C2" - ], - [ - "BRKH_INT_SS6C0", - "SS6B0" - ], - [ - "BRKH_INT_NE6B1", - "NE6C1" - ], - [ - "BRKH_INT_NE6C2", - "NE6D2" - ], - [ - "BRKH_INT_SW6E2", - "SW6D2" - ], - [ - "BRKH_INT_NW6END_S0_0", - "NW6END0" - ], - [ - "BRKH_INT_SR1END_N3_3", - "SR1END_N3_3" - ], - [ - "BRKH_INT_LVB_L7", - "LVB_L7" - ], - [ - "BRKH_INT_SR1END3_SLOW", - "SR1BEG3" - ], - [ - "BRKH_INT_LVB_L5", - "LVB_L5" - ], - [ - "BRKH_INT_NN2BEG2", - "NN2A2" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_0", - "FAN_BOUNCE0" - ], - [ - "BRKH_INT_NN6C2", - "NN6D2" - ], - [ - "BRKH_INT_L_LV14", - "LV_L15" - ], - [ - "BRKH_INT_SS6C2", - "SS6B2" - ], - [ - "BRKH_INT_SS6D3", - "SS6C3" - ], - [ - "BRKH_INT_NW2END_S0_0", - "NW2END0" - ], - [ - "BRKH_INT_WL1BEG3", - "WL1BEG_N3" - ], - [ - "BRKH_INT_NE6C1", - "NE6D1" - ], - [ - "BRKH_INT_L_LV15", - "LV_L16" - ], - [ - "BRKH_INT_SS6B3", - "SS6A3" - ], - [ - "BRKH_INT_L_LV9", - "LV_L10" - ], - [ - "BRKH_INT_NR1BEG1_SLOW", - "NR1END1" - ], - [ - "BRKH_INT_LVB_L2", - "LVB_L2" - ], - [ - "BRKH_INT_SE2A1", - "SE2BEG1" - ], - [ - "BRKH_INT_SS2A2", - "SS2BEG2" - ], - [ - "BRKH_INT_SL1END2_SLOW", - "SL1BEG2" - ], - [ - "BRKH_INT_NW6A3", - "NW6B3" - ], - [ - "BRKH_INT_NW6C3", - "NW6D3" - ], - [ - "BRKH_INT_NN6E1", - "NN6END1" - ], - [ - "BRKH_INT_SE6B3", - "SE6A3" - ], - [ - "BRKH_INT_SR1END1_SLOW", - "SR1BEG1" - ], - [ - "BRKH_INT_L_LV16", - "LV_L17" - ], - [ - "BRKH_INT_NE6D2", - "NE6E2" - ], - [ - "BRKH_INT_NE6B3", - "NE6C3" - ], - [ - "BRKH_INT_SE6D3", - "SE6C3" - ], - [ - "BRKH_INT_NN2BEG0", - "NN2A0" - ], - [ - "BRKH_INT_SE6C1", - "SE6B1" - ], - [ - "BRKH_INT_NW2BEG1", - "NW2A1" - ], - [ - "BRKH_INT_SW2A0", - "SW2BEG0" - ], - [ - "BRKH_INT_NE6D1", - "NE6E1" - ], - [ - "BRKH_INT_EL1BEG3", - "EL1BEG_N3" - ], - [ - "BRKH_INT_L_LV0", - "LV_L1" - ], - [ - "BRKH_INT_L_LV8", - "LV_L9" - ], - [ - "BRKH_INT_WR1END_S1_0", - "WR1END0" - ], - [ - "BRKH_INT_NW6D2", - "NW6E2" - ], - [ - "BRKH_INT_NE6D0", - "NE6E0" - ], - [ - "BRKH_INT_NW2BEG0", - "NW2A0" - ], - [ - "BRKH_INT_SS6A1", - "SS6BEG1" - ], - [ - "BRKH_INT_NE6B0", - "NE6C0" - ], - [ - "BRKH_INT_SW6D2", - "SW6C2" - ], - [ - "BRKH_INT_NL1BEG2_SLOW", - "NL1END2" - ], - [ - "BRKH_INT_NN2BEG3", - "NN2A3" - ], - [ - "BRKH_INT_SW6D3", - "SW6C3" - ], - [ - "BRKH_INT_SS2A0", - "SS2BEG0" - ], - [ - "BRKH_INT_NE6D3", - "NE6E3" - ], - [ - "BRKH_INT_L_LV4", - "LV_L5" - ], - [ - "BRKH_INT_SS6END1", - "SS6E1" - ], - [ - "BRKH_INT_LVB_L1", - "LVB_L1" - ], - [ - "BRKH_INT_SW6E0", - "SW6D0" - ], - [ - "BRKH_INT_SE6B1", - "SE6A1" - ], - [ - "BRKH_INT_SE2A3", - "SE2BEG3" - ], - [ - "BRKH_INT_SE6E2", - "SE6D2" - ], - [ - "BRKH_INT_L_LV1", - "LV_L2" - ], - [ - "BRKH_INT_NR1BEG3_SLOW", - "NR1END3" - ], - [ - "BRKH_INT_L_LV10", - "LV_L11" - ], - [ - "BRKH_INT_SE6E3", - "SE6D3" - ], - [ - "BRKH_INT_NE6A3", - "NE6B3" - ], - [ - "BRKH_INT_NW6B0", - "NW6C0" - ], - [ - "BRKH_INT_NN6B3", - "NN6C3" - ], - [ - "BRKH_INT_SW6E1", - "SW6D1" - ], - [ - "BRKH_INT_SS6A2", - "SS6BEG2" - ], - [ - "BRKH_INT_NN6C3", - "NN6D3" - ], - [ - "BRKH_INT_SE6E0", - "SE6D0" - ], - [ - "BRKH_INT_L_LV5", - "LV_L6" - ], - [ - "BRKH_INT_SW6B3", - "SW6A3" - ], - [ - "BRKH_INT_SL1END0_SLOW", - "SL1BEG0" - ], - [ - "BRKH_INT_ER1BEG_S0", - "ER1BEG0" - ], - [ - "BRKH_INT_SE6B0", - "SE6A0" - ], - [ - "BRKH_INT_NL1BEG0_SLOW", - "NL1END0" - ], - [ - "BRKH_INT_NN6A2", - "NN6B2" - ], - [ - "BRKH_INT_SS6B0", - "SS6A0" - ], - [ - "BRKH_INT_SL1END1_SLOW", - "SL1BEG1" - ], - [ - "BRKH_INT_SW6B1", - "SW6A1" - ], - [ - "BRKH_INT_NE6A2", - "NE6B2" - ], - [ - "BRKH_INT_NN6A3", - "NN6B3" - ], - [ - "BRKH_INT_LVB_L6", - "LVB_L6" - ], - [ - "BRKH_INT_SS2END2", - "SS2A2" - ], - [ - "BRKH_INT_SS6END2", - "SS6E2" - ], - [ - "BRKH_INT_NR1BEG2_SLOW", - "NR1END2" - ], - [ - "BRKH_INT_NN6B0", - "NN6C0" - ], - [ - "BRKH_INT_NN2A0", - "NN2END0" - ], - [ - "BRKH_INT_SS6B2", - "SS6A2" - ], - [ - "BRKH_INT_NW6B2", - "NW6C2" - ], - [ - "BRKH_INT_SS6B1", - "SS6A1" - ], - [ - "BRKH_INT_SW2END3", - "SW2END_N0_3" - ], - [ - "BRKH_INT_NW2BEG3", - "NW2A3" - ], - [ - "BRKH_INT_ER1END3", - "ER1END_N3_3" - ], - [ - "BRKH_INT_LVB_L10", - "LVB_L10" - ], - [ - "BRKH_INT_NN2BEG1", - "NN2A1" - ], - [ - "BRKH_INT_NL1END_S3_0", - "NL1END0" - ], - [ - "BRKH_INT_SS2A3", - "SS2BEG3" - ], - [ - "BRKH_INT_SE6B2", - "SE6A2" - ], - [ - "BRKH_INT_SS6END_N0_3", - "SS6END_N0_3" - ], - [ - "BRKH_INT_SS6E0", - "SS6D0" - ], - [ - "BRKH_INT_WW2END3", - "WW2END_N0_3" - ], - [ - "BRKH_INT_NN6A0", - "NN6B0" - ], - [ - "BRKH_INT_SW6END3", - "SW6END_N0_3" - ], - [ - "BRKH_INT_SS2END_N0_3", - "SS2END_N0_3" - ], - [ - "BRKH_INT_NN6E2", - "NN6END2" - ], - [ - "BRKH_INT_NN6C0", - "NN6D0" - ], - [ - "BRKH_INT_NE6C0", - "NE6D0" - ], - [ - "BRKH_INT_NN6D1", - "NN6E1" - ], - [ - "BRKH_INT_SE6D0", - "SE6C0" - ], - [ - "BRKH_INT_NN6BEG2", - "NN6A2" - ], - [ - "BRKH_INT_NW6D3", - "NW6E3" - ], - [ - "BRKH_INT_SW2A2", - "SW2BEG2" - ], - [ - "BRKH_INT_SS6E1", - "SS6D1" - ], - [ - "BRKH_INT_SS6C1", - "SS6B1" - ], - [ - "BRKH_INT_NR1BEG0_SLOW", - "NR1END0" - ], - [ - "BRKH_INT_NN2A3", - "NN2END3" - ], - [ - "BRKH_INT_NN6B1", - "NN6C1" - ], - [ - "BRKH_INT_NN6END_S1_0", - "NN6END0" - ], - [ - "BRKH_INT_SS6C3", - "SS6B3" - ], - [ - "BRKH_INT_NN2A1", - "NN2END1" - ], - [ - "BRKH_INT_SE6C3", - "SE6B3" - ], - [ - "BRKH_INT_NW2BEG2", - "NW2A2" - ], - [ - "BRKH_INT_NN6BEG0", - "NN6A0" - ], - [ - "BRKH_INT_NN6BEG3", - "NN6A3" - ], - [ - "BRKH_INT_SE2A2", - "SE2BEG2" - ], - [ - "BRKH_INT_NE2END_S3_0", - "NE2END0" - ], - [ - "BRKH_INT_SW6C3", - "SW6B3" - ], - [ - "BRKH_INT_SS6E2", - "SS6D2" - ], - [ - "BRKH_INT_BYP_BOUNCE7", - "BYP_BOUNCE_N3_7" - ], - [ - "BRKH_INT_L_LV12", - "LV_L13" - ], - [ - "BRKH_INT_SS6A3", - "SS6BEG3" - ], - [ - "BRKH_INT_LVB_L3", - "LVB_L3" - ], - [ - "BRKH_INT_SW2A1", - "SW2BEG1" - ], - [ - "BRKH_INT_NW6C1", - "NW6D1" - ], - [ - "BRKH_INT_L_LV11", - "LV_L12" - ], - [ - "BRKH_INT_SE6D1", - "SE6C1" - ], - [ - "BRKH_INT_BYP_BOUNCE3", - "BYP_BOUNCE_N3_3" - ] - ] - }, - { - "grid_deltas": [ - -1, - -3 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_BUFG_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_BUFG_IMUX33_3", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WL1END3_3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_SW2A1_3", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_FAN6_3", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4END0_3", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_NE4C1_3", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_NW2A2_3", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WW4C3_3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_BUFG_IMUX8_3", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WW4B2_3", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_SW4END0_3", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_NE2A0_3", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_LH11_3", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE4A0_3", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "CLK_BUFG_IMUX37_3", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_WW4B0_3", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_SW4A0_3", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_3", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_BUFG_IMUX36_3", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_BUFG_IMUX26_3", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_WW4A2_3", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW4END2_3", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_BUFG_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_BUFG_IMUX0_3", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_WW4C2_3", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_CLK1_3", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_SE4C1_3", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_BUFG_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_3", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_BYP7_3", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WW2END0_3", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_EE4C3_3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_BUFG_IMUX19_3", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_LH7_3", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_EE4A1_3", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_NW4END3_3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_IMUX10_3", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_IMUX40_3", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_EE4B2_3", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_BUFG_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_CLK0_3", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_FAN7_3", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW2A2_3", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_EE4B0_3", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_BUFG_IMUX7_3", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_BUFG_IMUX41_3", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_3", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_BUFG_IMUX14_3", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_EE2A1_3", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_BUFG_IMUX30_3", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_BUFG_IMUX11_3", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_3", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_BUFG_IMUX45_3", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_BUFG_IMUX9_3", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_BUFG_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_3", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_EE4C0_3", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4A1_3", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_NW4END0_3", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_NE2A3_3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_SE2A1_3", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_IMUX22_3", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_BYP5_3", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_BUFG_IMUX27_3", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_3", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_HROW_WW4C1_3", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_NW4A2_3", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW2END3_3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_BUFG_IMUX43_3", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_SE4C3_3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_BYP3_3", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE2A1_3", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_NE4C3_3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_BUFG_IMUX20_3", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_NW2A1_3", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_3", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_BUFG_IMUX21_3", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_BUFG_IMUX39_3", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_WL1END0_3", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_BUFG_IMUX18_3", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_NE2A2_3", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_BUFG_IMUX4_3", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WR1END1_3", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_SE4C2_3", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_WW4B3_3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_BUFG_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_BUFG_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW2END2_3", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_FAN3_3", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW2A0_3", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE4B1_3", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_WW2A1_3", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_WL1END1_3", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_SW4A3_3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_BYP1_3", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_WW2A3_3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_SE4C0_3", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_3", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_HROW_WW4C0_3", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_NW2A3_3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_BUFG_IMUX47_3", - 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"CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX10_1", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_IMUX39_1", - "INT_INTERFACE_IMUX39" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_CMT", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "HCLK_CMT_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_CMT_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_CMT_MUX_CLK_7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_CMT_MUX_CLK_5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_CMT_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_CMT_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_CMT_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_CMT_MUX_CLK_13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_CMT_MUX_CLK_9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_CMT_MUX_CLK_12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_CMT_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_CMT_MUX_CLK_11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK2", - "HCLK_VBRK_PHSR_PERFCLK2" - ], - [ - "HCLK_CMT_MUX_CLK_10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_CMT_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_CMT_MUX_CLK_0", - "HCLK_VBRK_MUX_CLK0" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK3", - "HCLK_VBRK_PHSR_PERFCLK3" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK1", - "HCLK_VBRK_PHSR_PERFCLK1" - ], - [ - "HCLK_CMT_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_CMT_MUX_CLK_6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK0", - "HCLK_VBRK_PHSR_PERFCLK0" - ], - [ - "HCLK_CMT_MUX_CLK_3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_CMT_MUX_CLK_2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_CMT_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_CMT_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_CMT_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_CMT_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_CMT_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_CMT_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "HCLK_CMT_MUX_CLK_1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_CMT_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_CMT_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_CMT_MUX_CLK_4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_CMT_MUX_CLK_8", - "HCLK_VBRK_MUX_CLK8" - ] - ] - }, - { - "grid_deltas": [ - 1, - 11 - ], - "tile_types": [ - "CMT_FIFO_R", - "CMT_TOP_R_LOWER_B" - ], - "wire_pairs": [ - [ - "CMT_FIFO_ER1BEG2_2", - "CMT_TOP_ER1BEG2_15" - ], - [ - "CMT_FIFO_LH10_1", - "CMT_TOP_LH10_14" - ], - [ - "CMT_FIFO_SE4BEG3_0", - "CMT_TOP_SE4BEG3_13" - ], - [ - "CMT_FIFO_SE4C0_2", - "CMT_TOP_SE4C0_15" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_13" - ], - [ - "CMT_FIFO_WL1END2_2", - "CMT_TOP_WL1END2_15" - ], - [ - "CMT_FIFO_L_IMUX6_1", - "CMT_TOP_IMUX6_14" - ], - [ - "CMT_FIFO_L_IMUX9_0", - "CMT_TOP_IMUX9_13" - ], - [ - "CMT_FIFO_L_IMUX47_0", - "CMT_TOP_IMUX47_13" - ], - [ - "CMT_FIFO_L_IMUX15_0", - "CMT_TOP_IMUX15_13" - ], - [ - "CMT_FIFO_NE4BEG1_0", - "CMT_TOP_NE4BEG1_13" - ], - [ - "CMT_FIFO_WW4B2_0", - "CMT_TOP_WW4B2_13" - ], - [ - "CMT_FIFO_L_FAN2_0", - "CMT_TOP_FAN2_13" - ], - [ - "CMT_FIFO_L_CTRL0_2", - "CMT_TOP_CTRL0_15" - ], - [ - "CMT_FIFO_L_IMUX33_0", - "CMT_TOP_IMUX33_13" - ], - [ - "CMT_FIFO_L_IMUX18_2", - "CMT_TOP_IMUX18_15" - ], - [ - "CMT_FIFO_SE4BEG3_1", - "CMT_TOP_SE4BEG3_14" - ], - [ - "CMT_FIFO_NW4END3_2", - "CMT_TOP_NW4END3_15" - ], - [ - "CMT_FIFO_L_IMUX26_1", - "CMT_TOP_IMUX26_14" - ], - [ - "CMT_FIFO_SW2A2_1", - "CMT_TOP_SW2A2_14" - ], - [ - "CMT_FIFO_L_IMUX35_2", - "CMT_TOP_IMUX35_15" - ], - [ - "CMT_FIFO_ER1BEG3_0", - "CMT_TOP_ER1BEG3_13" - ], - [ - "CMT_FIFO_L_IMUX6_0", - "CMT_TOP_IMUX6_13" - ], - [ - "CMT_FIFO_NE4C3_1", - "CMT_TOP_NE4C3_14" - ], - [ - "CMT_FIFO_EE4B0_2", - "CMT_TOP_EE4B0_15" - ], - [ - "CMT_FIFO_LH12_2", - "CMT_TOP_LH12_15" - ], - [ - "CMT_FIFO_LH2_0", - "CMT_TOP_LH2_13" - ], - [ - "CMT_FIFO_L_FAN1_2", - "CMT_TOP_FAN1_15" - ], - [ - "CMT_FIFO_L_IMUX47_1", - "CMT_TOP_IMUX47_14" - ], - [ - "CMT_FIFO_L_IMUX26_0", - "CMT_TOP_IMUX26_13" - ], - [ - "CMT_FIFO_WW4END1_2", - "CMT_TOP_WW4END1_15" - ], - [ - "CMT_FIFO_SW4END0_2", - "CMT_TOP_SW4END0_15" - ], - [ - "CMT_FIFO_SE2A3_2", - "CMT_TOP_SE2A3_15" - ], - [ - "CMT_FIFO_SE2A1_1", - "CMT_TOP_SE2A1_14" - ], - [ - "CMT_FIFO_NE2A3_0", - "CMT_TOP_NE2A3_13" - ], - [ - "CMT_FIFO_SW4END2_0", - "CMT_TOP_SW4END2_13" - ], - [ - "CMT_FIFO_WL1END2_0", - "CMT_TOP_WL1END2_13" - ], - [ - "CMT_FIFO_L_IMUX15_1", - "CMT_TOP_IMUX15_14" - ], - [ - "CMT_FIFO_NW2A1_1", - "CMT_TOP_NW2A1_14" - ], - [ - "CMT_FIFO_NW2A0_1", - "CMT_TOP_NW2A0_14" - ], - [ - "CMT_FIFO_EE4BEG3_0", - "CMT_TOP_EE4BEG3_13" - ], - [ - "CMT_FIFO_L_IMUX1_1", - "CMT_TOP_IMUX1_14" - ], - [ - "CMT_FIFO_L_IMUX1_0", - "CMT_TOP_IMUX1_13" - ], - [ - "CMT_FIFO_WR1END0_1", - "CMT_TOP_WR1END0_14" - ], - [ - "CMT_FIFO_L_IMUX12_0", - "CMT_TOP_IMUX12_13" - ], - [ - "CMT_FIFO_L_IMUX8_2", - "CMT_TOP_IMUX8_15" - ], - [ - "CMT_FIFO_L_IMUX42_1", - "CMT_TOP_IMUX42_14" - ], - [ - "CMT_FIFO_WW4B0_0", - "CMT_TOP_WW4B0_13" - ], - [ - "CMT_FIFO_L_CLK0_1", - "CMT_TOP_CLK0_14" - ], - [ - "CMT_FIFO_NE2A1_0", - "CMT_TOP_NE2A1_13" - ], - [ - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", - "CMT_TOP_OCLKDIV_14" - ], - [ - "CMT_FIFO_L_IMUX28_1", - "CMT_TOP_IMUX28_14" - ], - [ - "CMT_FIFO_WW4C1_0", - "CMT_TOP_WW4C1_13" - ], - [ - "CMT_FIFO_SW2A2_2", - "CMT_TOP_SW2A2_15" - ], - [ - "CMT_FIFO_EE4BEG2_1", - "CMT_TOP_EE4BEG2_14" - ], - [ - "CMT_FIFO_EL1BEG3_2", - "CMT_TOP_EL1BEG3_15" - ], - [ - "CMT_FIFO_WL1END3_1", - "CMT_TOP_WL1END3_14" - ], - [ - "CMT_FIFO_NW4A0_2", - "CMT_TOP_NW4A0_15" - ], - [ - "CMT_FIFO_L_FAN5_2", - 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"PCIE_INT_INTERFACE_IMUX_L_OUT14" - ], - [ - "PCIE_EE4C3_19", - "INT_INTERFACE_EE4C3" - ], - [ - "PCIE_NW4A2_19", - "INT_INTERFACE_NW4A2" - ], - [ - "PCIE_CLK0_L_19", - "INT_INTERFACE_CLK0" - ], - [ - "PCIE_NE4C3_19", - "INT_INTERFACE_NE4C3" - ], - [ - "PCIE_EE4B0_19", - "INT_INTERFACE_EE4B0" - ], - [ - "PCIE_SE4BEG0_19", - "INT_INTERFACE_SE4BEG0" - ], - [ - "PCIE_LOGIC_OUTS_B2_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B2" - ], - [ - "PCIE_IMUX29_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT29" - ], - [ - "PCIE_WW4A0_19", - "INT_INTERFACE_WW4A0" - ], - [ - "PCIE_NE4BEG2_19", - "INT_INTERFACE_NE4BEG2" - ], - [ - "PCIE_IMUX33_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT33" - ], - [ - "PCIE_WW2A3_19", - "INT_INTERFACE_WW2A3" - ], - [ - "PCIE_BYP4_L_19", - "INT_INTERFACE_BYP4" - ], - [ - "PCIE_NE2A2_19", - "INT_INTERFACE_NE2A2" - ], - [ - "PCIE_CLK1_L_19", - "INT_INTERFACE_CLK1" - ], - [ - "PCIE_WW2END2_19", - "INT_INTERFACE_WW2END2" - ], - [ - "PCIE_IMUX9_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT9" - ], - [ - "PCIE_WR1END0_19", - "INT_INTERFACE_WR1END0" - ], - [ - "PCIE_NW4END3_19", - "INT_INTERFACE_NW4END3" - ], - [ - "PCIE_SW4A1_19", - "INT_INTERFACE_SW4A1" - ], - [ - "PCIE_LH7_19", - "INT_INTERFACE_LH7" - ], - [ - "PCIE_BYP1_L_19", - "INT_INTERFACE_BYP1" - ], - [ - "PCIE_LOGIC_OUTS_B15_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B15" - ], - [ - "PCIE_LOGIC_OUTS_B7_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B7" - ], - [ - "PCIE_LOGIC_OUTS_B4_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B4" - ], - [ - "PCIE_WW4C2_19", - "INT_INTERFACE_WW4C2" - ], - [ - "PCIE_IMUX6_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT6" - ], - [ - "PCIE_SE2A2_19", - "INT_INTERFACE_SE2A2" - ], - [ - "PCIE_SW4END3_19", - "INT_INTERFACE_SW4END3" - ], - [ - "PCIE_BYP6_L_19", - "INT_INTERFACE_BYP6" - ], - [ - "PCIE_WW4B1_19", - "INT_INTERFACE_WW4B1" - ], - [ - "PCIE_ER1BEG1_19", - "INT_INTERFACE_ER1BEG1" - ], - [ - "PCIE_IMUX24_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT24" - ], - [ - "PCIE_SE4C2_19", - "INT_INTERFACE_SE4C2" - ], - [ - "PCIE_LOGIC_OUTS_B6_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B6" - ], - [ - "PCIE_CTRL0_L_19", - "INT_INTERFACE_CTRL0" - ], - [ - "PCIE_EL1BEG3_19", - "INT_INTERFACE_EL1BEG3" - ], - [ - "PCIE_LOGIC_OUTS_B11_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "PCIE_BYP5_L_19", - "INT_INTERFACE_BYP5" - ], - [ - "PCIE_IMUX4_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT4" - ], - [ - "PCIE_EE4B3_19", - "INT_INTERFACE_EE4B3" - ], - [ - "PCIE_SW4A3_19", - "INT_INTERFACE_SW4A3" - ], - [ - "PCIE_EE2A1_19", - "INT_INTERFACE_EE2A1" - ], - [ - "PCIE_IMUX1_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT1" - ], - [ - "PCIE_NE4C1_19", - "INT_INTERFACE_NE4C1" - ], - [ - "PCIE_LOGIC_OUTS_B23_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B23" - ], - [ - "PCIE_EE4C0_19", - "INT_INTERFACE_EE4C0" - ], - [ - "PCIE_NW4A3_19", - "INT_INTERFACE_NW4A3" - ], - [ - "PCIE_IMUX5_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT5" - ], - [ - "PCIE_LOGIC_OUTS_B1_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B1" - ], - [ - "PCIE_IMUX23_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT23" - ], - [ - "PCIE_IMUX44_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT44" - ], - [ - "PCIE_LOGIC_OUTS_B18_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B18" - ], - [ - "PCIE_IMUX13_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT13" - ], - [ - "PCIE_LOGIC_OUTS_B0_L_19", - "INT_INTERFACE_LOGIC_OUTS_L_B0" - ], - [ - "PCIE_SW4END1_19", - "INT_INTERFACE_SW4END1" - ], - [ - "PCIE_EL1BEG0_19", - "INT_INTERFACE_EL1BEG0" - ], - [ - "PCIE_IMUX38_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT38" - ], - [ - "PCIE_ER1BEG2_19", - "INT_INTERFACE_ER1BEG2" - ], - [ - "PCIE_IMUX21_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT21" - ], - [ - "PCIE_LH3_19", - "INT_INTERFACE_LH3" - ], - [ - "PCIE_NE2A1_19", - "INT_INTERFACE_NE2A1" - ], - [ - "PCIE_WW4A2_19", - "INT_INTERFACE_WW4A2" - ], - [ - "PCIE_IMUX40_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT40" - ], - [ - "PCIE_IMUX43_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT43" - ], - [ - "PCIE_IMUX32_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT32" - ], - [ - "PCIE_FAN6_L_19", - "INT_INTERFACE_FAN6" - ], - [ - "PCIE_WW2END1_19", - "INT_INTERFACE_WW2END1" - ], - [ - "PCIE_WW4END0_19", - "INT_INTERFACE_WW4END0" - ], - [ - "PCIE_EE2BEG0_19", - "INT_INTERFACE_EE2BEG0" - ], - [ - "PCIE_BYP0_L_19", - "INT_INTERFACE_BYP0" - ], - [ - "PCIE_IMUX16_L_19", - "PCIE_INT_INTERFACE_IMUX_L_OUT16" - ], - [ - "PCIE_MONITOR_N_19", - "INT_INTERFACE_MONITOR_N" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "CLK_MTBF2", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_LH8", - "VBRK_LH8" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_LH2", - "VBRK_LH2" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLK_FEED_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLK_FEED_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLK_FEED_EE4BEG2", - "VBRK_EE4BEG2" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLK_FEED_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLK_FEED_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLK_FEED_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLK_FEED_LH7", - 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"CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ 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"HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_CLB_PERFCLK2", - "HCLK_VBRK_PHSR_PERFCLK2" - ], - [ - "HCLK_CLB_PERFCLK3", - "HCLK_VBRK_PHSR_PERFCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_CLB_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_CLB_CK_BUFRCLK1", - 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"INT_INTERFACE_SW4A0" - ], - [ - "PCIE_NW4END0_7", - "INT_INTERFACE_NW4END0" - ], - [ - "PCIE_IMUX43_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT43" - ], - [ - "PCIE_EE2BEG0_7", - "INT_INTERFACE_EE2BEG0" - ], - [ - "PCIE_LOGIC_OUTS_B5_R_7", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "PCIE_NW4A1_7", - "INT_INTERFACE_NW4A1" - ], - [ - "PCIE_IMUX34_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT34" - ], - [ - "PCIE_IMUX7_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT7" - ], - [ - "PCIE_LOGIC_OUTS_B10_R_7", - "INT_INTERFACE_LOGIC_OUTS_B10" - ], - [ - "PCIE_SW2A3_7", - "INT_INTERFACE_SW2A3" - ], - [ - "PCIE_IMUX31_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT31" - ], - [ - "PCIE_SE4C3_7", - "INT_INTERFACE_SE4C3" - ], - [ - "PCIE_LH11_7", - "INT_INTERFACE_LH11" - ], - [ - "PCIE_NW4A0_7", - "INT_INTERFACE_NW4A0" - ], - [ - "PCIE_EE4A3_7", - "INT_INTERFACE_EE4A3" - ], - [ - "PCIE_FAN4_R_7", - "INT_INTERFACE_FAN4" - ], - [ - "PCIE_BYP5_R_7", - "INT_INTERFACE_BYP5" - ], - [ - "PCIE_LOGIC_OUTS_B12_R_7", - "INT_INTERFACE_LOGIC_OUTS_B12" - ], - [ - "PCIE_WW4C3_7", - "INT_INTERFACE_WW4C3" - ], - [ - "PCIE_LOGIC_OUTS_B3_R_7", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "PCIE_EE4BEG0_7", - "INT_INTERFACE_EE4BEG0" - ], - [ - "PCIE_EE4B0_7", - "INT_INTERFACE_EE4B0" - ], - [ - "PCIE_LH8_7", - "INT_INTERFACE_LH8" - ], - [ - "PCIE_IMUX12_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT12" - ], - [ - "PCIE_NW2A2_7", - "INT_INTERFACE_NW2A2" - ], - [ - "PCIE_FAN5_R_7", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_LH6_7", - "INT_INTERFACE_LH6" - ], - [ - "PCIE_IMUX41_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT41" - ], - [ - "PCIE_SW4END2_7", - "INT_INTERFACE_SW4END2" - ], - [ - "PCIE_IMUX9_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT9" - ], - [ - "PCIE_LOGIC_OUTS_B22_R_7", - "INT_INTERFACE_LOGIC_OUTS_B22" - ], - [ - "PCIE_ER1BEG1_7", - "INT_INTERFACE_ER1BEG1" - ], - [ - "PCIE_SE4C0_7", - "INT_INTERFACE_SE4C0" - ], - [ - "PCIE_IMUX33_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT33" - ], - [ - "PCIE_LOGIC_OUTS_B20_R_7", - "INT_INTERFACE_LOGIC_OUTS_B20" - ], - [ - "PCIE_SE2A1_7", - "INT_INTERFACE_SE2A1" - ], - [ - "PCIE_WL1END3_7", - "INT_INTERFACE_WL1END3" - ], - [ - "PCIE_IMUX13_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT13" - ], - [ - "PCIE_IMUX35_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT35" - ], - [ - "PCIE_WW2A2_7", - "INT_INTERFACE_WW2A2" - ], - [ - "PCIE_NW4END2_7", - "INT_INTERFACE_NW4END2" - ], - [ - "PCIE_EE2BEG3_7", - "INT_INTERFACE_EE2BEG3" - ], - [ - "PCIE_LOGIC_OUTS_B6_R_7", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "PCIE_LH5_7", - "INT_INTERFACE_LH5" - ], - [ - "PCIE_EE4BEG3_7", - "INT_INTERFACE_EE4BEG3" - ], - [ - "PCIE_EL1BEG1_7", - "INT_INTERFACE_EL1BEG1" - ], - [ - "PCIE_NW4A2_7", - "INT_INTERFACE_NW4A2" - ], - [ - "PCIE_LH3_7", - "INT_INTERFACE_LH3" - ], - [ - "PCIE_LOGIC_OUTS_B2_R_7", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "PCIE_NE2A3_7", - "INT_INTERFACE_NE2A3" - ], - [ - "PCIE_BYP4_R_7", - "INT_INTERFACE_BYP4" - ], - [ - "PCIE_WW2END0_7", - "INT_INTERFACE_WW2END0" - ], - [ - "PCIE_NW2A0_7", - "INT_INTERFACE_NW2A0" - ], - [ - "PCIE_NW4END3_7", - "INT_INTERFACE_NW4END3" - ], - [ - "PCIE_IMUX39_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT39" - ], - [ - "PCIE_WR1END3_7", - "INT_INTERFACE_WR1END3" - ], - [ - "PCIE_ER1BEG2_7", - "INT_INTERFACE_ER1BEG2" - ], - [ - "PCIE_NE4BEG0_7", - "INT_INTERFACE_NE4BEG0" - ], - [ - "PCIE_EE4C2_7", - "INT_INTERFACE_EE4C2" - ], - [ - "PCIE_NW4END1_7", - "INT_INTERFACE_NW4END1" - ], - [ - "PCIE_EE2A1_7", - "INT_INTERFACE_EE2A1" - ], - [ - "PCIE_EE4BEG1_7", - "INT_INTERFACE_EE4BEG1" - ], - [ - "PCIE_IMUX1_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT1" - ], - [ - "PCIE_WW4A2_7", - "INT_INTERFACE_WW4A2" - ], - [ - "PCIE_IMUX47_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT47" - ], - [ - "PCIE_IMUX20_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT20" - ], - [ - "PCIE_NE4C1_7", - "INT_INTERFACE_NE4C1" - ], - [ - "PCIE_IMUX29_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT29" - ], - [ - "PCIE_WR1END1_7", - "INT_INTERFACE_WR1END1" - ], - [ - "PCIE_EE4B3_7", - "INT_INTERFACE_EE4B3" - ], - [ - "PCIE_EE2A2_7", - "INT_INTERFACE_EE2A2" - ], - [ - "PCIE_WW4C2_7", - "INT_INTERFACE_WW4C2" - ], - [ - "PCIE_EL1BEG2_7", - "INT_INTERFACE_EL1BEG2" - ], - [ - "PCIE_CLK1_R_7", - "INT_INTERFACE_CLK1" - ], - [ - "PCIE_NE4BEG2_7", - "INT_INTERFACE_NE4BEG2" - ], - [ - "PCIE_IMUX4_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT4" - ], - [ - "PCIE_WW4B3_7", - "INT_INTERFACE_WW4B3" - ], - [ - "PCIE_NE2A2_7", - "INT_INTERFACE_NE2A2" - ], - [ - "PCIE_WW2A3_7", - "INT_INTERFACE_WW2A3" - ], - [ - "PCIE_SW2A2_7", - "INT_INTERFACE_SW2A2" - ], - [ - "PCIE_LOGIC_OUTS_B17_R_7", - "INT_INTERFACE_LOGIC_OUTS_B17" - ] - ] - }, - { - "grid_deltas": [ - 1, - -3 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH12_3", - "VBRK_LH12" - ], - [ - "CLK_HROW_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_LH8_3", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_LH1_3", - "VBRK_LH1" - ], - [ - "CLK_HROW_WW4C1_3", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH11_3", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH10_3", - "VBRK_LH10" - ], - [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_LH9_3", - "VBRK_LH9" - ], - [ - "CLK_HROW_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_SE2A2_3", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_LH6_3", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_LH7_3", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SW2A0_3", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH2_3", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EL1BEG1_3", - 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"INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_PMV_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_FEED_ER1BEG2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_PMV_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_FEED_WW4A3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_FEED_EE4BEG2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_LOGIC_OUTS16_0", - "INT_INTERFACE_LOGIC_OUTS_B16" - ], - [ - "CLK_PMV_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_FEED_EE4A2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_EE2A0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_PMV_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_FEED_NW2A2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_FEED_WW4A2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_FEED_WW2END1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_FEED_WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_FEED_LH4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_FEED_EE2BEG1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_LOGIC_OUTS14_0", - "INT_INTERFACE_LOGIC_OUTS_B14" - ], - [ - "CLK_PMV_LOGIC_OUTS5_0", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_FEED_NE4BEG2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_FEED_EE4C0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_FEED_LH12", - "INT_INTERFACE_LH12" - ], - [ - "CLK_FEED_NE2A2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_FEED_WW4END1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_FEED_EE4BEG1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_PMV_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_FEED_LH2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_FEED_NE2A0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_FEED_NW4A0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_NW4END3", - "INT_INTERFACE_NW4END3" - ] - ] - }, - { - "grid_deltas": [ - -1, - -1 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_NE2A1_4", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_IMUX8_4", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_WL1END2_4", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WR1END2_4", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_IMUX46_4", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_IMUX15_4", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_EL1BEG0_4", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_IMUX17_4", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_WW4C2_4", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW4END1_4", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_IMUX35_4", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_LH9_4", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NW2A2_4", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_LH10_4", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_IMUX0_4", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX13_4", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_MONITOR_N_4", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_BYP6_4", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX32_4", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX47_4", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_WW2END3_4", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_IMUX31_4", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_WW4END2_4", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_WR1END0_4", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_NE2A3_4", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_EE4C3_4", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_IMUX7_4", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE2A3_4", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX29_4", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_SE4BEG2_4", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_SW4A3_4", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NW4A3_4", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_WW4B0_4", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_IMUX16_4", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4B2_4", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_SE4C0_4", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW4A0_4", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_FAN5_4", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_IMUX9_4", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_NW2A1_4", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_IMUX5_4", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_LH12_4", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_NW4END3_4", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SE2A0_4", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_NW4END2_4", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_NE4C0_4", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_NW2A3_4", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_EE4A2_4", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_NW4A0_4", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX26_4", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WW4A1_4", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW4A2_4", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_IMUX44_4", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH11_4", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE4B2_4", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_WW4B1_4", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_CTRL1_4", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX20_4", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_WL1END0_4", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_IMUX24_4", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_FAN1_4", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW4A2_4", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_EE4BEG1_4", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_BYP3_4", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_BYP7_4", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_FAN2_4", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_NE4C2_4", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_LH4_4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_IMUX2_4", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_ER1BEG1_4", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_CLK0_4", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_LH3_4", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_IMUX6_4", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_SE4BEG1_4", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NE2A2_4", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_EE4C2_4", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_SE2A1_4", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX18_4", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX39_4", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_EE2BEG1_4", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_EE4C1_4", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_EE2A2_4", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_EE2BEG0_4", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_EE4B1_4", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_EL1BEG1_4", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_SE4BEG3_4", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_EE4B3_4", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_IMUX21_4", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_SE2A3_4", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_LH5_4", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NE2A0_4", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_LH1_4", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_SW4A2_4", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_SW4END0_4", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_SW4END3_4", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_SE2A2_4", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_IMUX37_4", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_NE4BEG1_4", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_SW4END2_4", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_LH6_4", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_BYP0_4", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_IMUX28_4", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX4_4", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX19_4", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_BYP2_4", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_SE4C3_4", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_IMUX33_4", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_WR1END1_4", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_SW2A0_4", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_IMUX10_4", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_FAN0_4", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_ER1BEG0_4", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SW2A2_4", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_LH8_4", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_SW2A3_4", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SW2A1_4", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4C1_4", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_IMUX30_4", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SE4C1_4", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_WW4B3_4", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE2A0_4", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4BEG3_4", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_WR1END3_4", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_NW2A0_4", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_IMUX11_4", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_EE2BEG2_4", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_BYP1_4", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_IMUX27_4", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_EE4B0_4", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_WW4A3_4", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EE4BEG2_4", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_NW4END0_4", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_SW4A1_4", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_IMUX45_4", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_WW2A2_4", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_WW2A1_4", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_WW4C3_4", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_NW4A1_4", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_WL1END3_4", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX42_4", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_IMUX12_4", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_IMUX38_4", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_EE4A0_4", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_SE4BEG0_4", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_NE4C3_4", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_WW2END1_4", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_IMUX40_4", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_IMUX23_4", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_NE4BEG3_4", - "INT_INTERFACE_NE4BEG3" - ], - [ - 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"VBRK_WW4A3" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMV2_SVT" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - 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- ], - [ - "GTXE2_BYP2_8", - "VBRK_EXT_BYP2" - ], - [ - "GTXE2_IMUX25_8", - "VBRK_EXT_IMUX25" - ], - [ - "GTXE2_LOGIC_OUTS_B11_8", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTXE2_BYP3_8", - "VBRK_EXT_BYP3" - ], - [ - "GTXE2_IMUX5_8", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_LOGIC_OUTS_B4_8", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTXE2_LOGIC_OUTS_B16_8", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTXE2_IMUX7_8", - "VBRK_EXT_IMUX7" - ], - [ - "GTXE2_IMUX9_8", - "VBRK_EXT_IMUX9" - ], - [ - "GTXE2_FAN3_8", - "VBRK_EXT_FAN3" - ], - [ - "GTXE2_LOGIC_OUTS_B3_8", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTXE2_IMUX10_8", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_IMUX43_8", - "VBRK_EXT_IMUX43" - ], - [ - "GTXE2_BYP1_8", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_LOGIC_OUTS_B15_8", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTXE2_LOGIC_OUTS_B21_8", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTXE2_IMUX45_8", - "VBRK_EXT_IMUX45" - ], - [ - "GTXE2_IMUX3_8", - "VBRK_EXT_IMUX3" - ], - [ - "GTXE2_IMUX38_8", - "VBRK_EXT_IMUX38" - ], - [ - "GTXE2_IMUX33_8", - "VBRK_EXT_IMUX33" - ], - [ - "GTXE2_IMUX31_8", - "VBRK_EXT_IMUX31" - ], - [ - "GTXE2_IMUX23_8", - "VBRK_EXT_IMUX23" - ], - [ - "GTXE2_CLK1_8", - "VBRK_EXT_CLK1" - ], - [ - "GTXE2_CTRL1_8", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_LOGIC_OUTS_B13_8", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_IMUX16_8", - "VBRK_EXT_IMUX16" - ], - [ - "GTXE2_IMUX41_8", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_LOGIC_OUTS_B10_8", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTXE2_IMUX15_8", - "VBRK_EXT_IMUX15" - ], - [ - "GTXE2_CLK0_8", - "VBRK_EXT_CLK0" - ], - [ - "GTXE2_LOGIC_OUTS_B20_8", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTXE2_CTRL0_8", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_IMUX35_8", - "VBRK_EXT_IMUX35" - ], - [ - "GTXE2_IMUX30_8", - "VBRK_EXT_IMUX30" - ], - [ - "GTXE2_LOGIC_OUTS_B8_8", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTXE2_BYP4_8", - "VBRK_EXT_BYP4" - ], - [ - "GTXE2_IMUX44_8", - "VBRK_EXT_IMUX44" - ], - [ - "GTXE2_IMUX22_8", - "VBRK_EXT_IMUX22" - ], - [ - "GTXE2_IMUX26_8", - "VBRK_EXT_IMUX26" - ], - [ - "GTXE2_IMUX14_8", - "VBRK_EXT_IMUX14" - ], - [ - "GTXE2_IMUX39_8", - "VBRK_EXT_IMUX39" - ], - [ - "GTXE2_BYP6_8", - "VBRK_EXT_BYP6" - ], - [ - "GTXE2_IMUX13_8", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_FAN4_8", - "VBRK_EXT_FAN4" - ], - [ - "GTXE2_IMUX12_8", - "VBRK_EXT_IMUX12" - ], - [ - "GTXE2_IMUX24_8", - "VBRK_EXT_IMUX24" - ], - [ - "GTXE2_LOGIC_OUTS_B1_8", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_FAN2_8", - "VBRK_EXT_FAN2" - ], - [ - "GTXE2_LOGIC_OUTS_B14_8", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTXE2_IMUX28_8", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_IMUX34_8", - "VBRK_EXT_IMUX34" - ], - [ - "GTXE2_LOGIC_OUTS_B22_8", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTXE2_IMUX1_8", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_BYP5_8", - "VBRK_EXT_BYP5" - ], - [ - "GTXE2_IMUX19_8", - "VBRK_EXT_IMUX19" - ], - [ - "GTXE2_LOGIC_OUTS_B9_8", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTXE2_LOGIC_OUTS_B19_8", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTXE2_IMUX40_8", - "VBRK_EXT_IMUX40" - ], - [ - "GTXE2_IMUX27_8", - "VBRK_EXT_IMUX27" - ], - [ - "GTXE2_IMUX36_8", - "VBRK_EXT_IMUX36" - ], - [ - "GTXE2_IMUX6_8", - "VBRK_EXT_IMUX6" - ], - [ - "GTXE2_IMUX11_8", - "VBRK_EXT_IMUX11" - ], - [ - "GTXE2_IMUX20_8", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_LOGIC_OUTS_B7_8", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTXE2_FAN5_8", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_IMUX18_8", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_IMUX4_8", - "VBRK_EXT_IMUX4" - ], - [ - "GTXE2_LOGIC_OUTS_B5_8", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTXE2_IMUX29_8", - "VBRK_EXT_IMUX29" - ], - [ - "GTXE2_IMUX32_8", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_BYP0_8", - "VBRK_EXT_BYP0" - ], - [ - "GTXE2_BYP7_8", - "VBRK_EXT_BYP7" - ], - [ - "GTXE2_FAN1_8", - "VBRK_EXT_FAN1" - ], - [ - "GTXE2_LOGIC_OUTS_B23_8", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTXE2_LOGIC_OUTS_B2_8", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTXE2_IMUX17_8", - "VBRK_EXT_IMUX17" - ], - [ - "GTXE2_IMUX47_8", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_FAN0_8", - "VBRK_EXT_FAN0" - ], - [ - "GTXE2_IMUX42_8", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_FAN6_8", - "VBRK_EXT_FAN6" - ], - [ - "GTXE2_IMUX8_8", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX2_8", - "VBRK_EXT_IMUX2" - ], - [ - "GTXE2_LOGIC_OUTS_B12_8", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTXE2_IMUX21_8", - "VBRK_EXT_IMUX21" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "HCLK_CLB", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "HCLK_CLB_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_CLB_CK_IN9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_CLB_PERFCLK2", - "HCLK_VBRK_PHSR_PERFCLK2" - ], - [ - "HCLK_CLB_PERFCLK3", - "HCLK_VBRK_PHSR_PERFCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_CLB_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_CLB_PERFCLK0", - "HCLK_VBRK_PHSR_PERFCLK0" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_CLB_PERFCLK1", - "HCLK_VBRK_PHSR_PERFCLK1" - ], - [ - "HCLK_CLB_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_CLB_CK_IN3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_CLB_CK_IN0", - "HCLK_VBRK_MUX_CLK0" - ] - ] - }, - { - "grid_deltas": [ - 1, - 3 - ], - "tile_types": [ - "BRAM_INT_INTERFACE_R", - "BRAM_R" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX36", - "BRAM_IMUX36_UTURN_3" - ], - [ - "INT_INTERFACE_CLK0", - "BRAM_CLK0_3" - ], - [ - "INT_INTERFACE_EE4A3", - "BRAM_EE4A3_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX10", - "BRAM_IMUX10_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX10", - "BRAM_IMUX10_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX16", - "BRAM_IMUX16_3" - ], - [ - "INT_INTERFACE_NW2A2", - "BRAM_NW2A2_3" - ], - [ - "INT_INTERFACE_SW4END2", - "BRAM_SW4END2_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX40", - "BRAM_IMUX40_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_3" - ], - [ - "INT_INTERFACE_ER1BEG1", - "BRAM_ER1BEG1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_3" - ], - [ - "INT_INTERFACE_SE4C3", - "BRAM_SE4C3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX12", - "BRAM_IMUX12_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B14", - "BRAM_LOGIC_OUTS_B14_3" - ], - [ - "INT_INTERFACE_WL1END1", - "BRAM_WL1END1_3" - ], - [ - "INT_INTERFACE_EL1BEG0", - "BRAM_EL1BEG0_3" - ], - [ - "INT_INTERFACE_WW2A3", - "BRAM_WW2A3_3" - ], - [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX35", - "BRAM_IMUX35_UTURN_3" - ], - [ - "INT_INTERFACE_EE2A0", - "BRAM_EE2A0_3" - ], - [ - "INT_INTERFACE_EE2A1", - "BRAM_EE2A1_3" - ], - [ - "INT_INTERFACE_WW4C1", - "BRAM_WW4C1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B15", - "BRAM_LOGIC_OUTS_B15_3" - ], - [ - "INT_INTERFACE_EE4BEG2", - "BRAM_EE4BEG2_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_3" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX39", - "BRAM_IMUX39_UTURN_3" - ], - [ - "INT_INTERFACE_SW2A3", - "BRAM_SW2A3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX2", - "BRAM_IMUX2_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX19", - "BRAM_IMUX19_UTURN_3" - ], - [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_3" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX7", - "BRAM_IMUX7_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_3" - ], - [ - "INT_INTERFACE_NE2A3", - "BRAM_NE2A3_3" - ], - [ - "INT_INTERFACE_BYP0", - "BRAM_BYP0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX28", - "BRAM_IMUX28_UTURN_3" - ], - [ - "INT_INTERFACE_BYP6", - "BRAM_BYP6_3" - ], - [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_3" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B19", - "BRAM_LOGIC_OUTS_B19_3" - ], - [ - "INT_INTERFACE_NW2A3", - "BRAM_NW2A3_3" - ], - [ - "INT_INTERFACE_EE2A3", - "BRAM_EE2A3_3" - ], - [ - "INT_INTERFACE_EE4B3", - "BRAM_EE4B3_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "BRAM_IMUX8_3" - ], - [ - "INT_INTERFACE_WW4A3", - "BRAM_WW4A3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX27", - "BRAM_IMUX27_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B4", - "BRAM_LOGIC_OUTS_B4_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX3", - "BRAM_IMUX3_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "BRAM_IMUX5_3" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX4", - "BRAM_IMUX4_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX21", - "BRAM_IMUX21_UTURN_3" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B8", - "BRAM_LOGIC_OUTS_B8_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "BRAM_IMUX1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - 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"NN2END_S2_0" - ], - [ - "BRKH_INT_NN6E1", - "NN6E1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 0 - ], - "tile_types": [ - "CLK_PMVIOB", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_FEED_WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_FEED_NW2A0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_FEED_MONITOR_N", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_PMV_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_FEED_LH1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_FEED_WW2END2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_FEED_EE2A3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_FEED_ER1BEG1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_PMV_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_FEED_SE2A1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_FEED_WW4END3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_FEED_NW4END1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_FEED_LH10", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_FEED_WL1END1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_PMV_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_PMV_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_FEED_WR1END1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_FEED_EL1BEG1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_FEED_SE4BEG2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_PMV_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_FEED_EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_FEED_SW2A1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_FEED_EE4A3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_FEED_WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_PMV_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_FEED_NE4BEG0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_FEED_SW2A2", - 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"CLK_FEED_NW4END2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_FEED_SE4BEG3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_PMV_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_FEED_WR1END3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_PMV_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_FEED_WW4B2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_PMV_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_FEED_SW4END3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_FEED_NW4END0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_FEED_NE4BEG1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_FEED_LH8", - "INT_INTERFACE_LH8" - ], - [ - "CLK_PMV_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_FEED_EE4B3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_FEED_WW4C2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_FEED_WW2A2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_FEED_SW4A2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_FEED_LH9", - "INT_INTERFACE_LH9" - ], - [ - "CLK_PMV_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_FEED_EE4BEG0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_FEED_EE4BEG3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_PMV_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_FEED_EE2BEG0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_PMV_LOGIC_OUTS2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_FEED_EE4B0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_FEED_EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_FEED_SW4A1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_FEED_WW4A1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_FEED_SE4C1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_FEED_SE4C2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_PMV_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_FEED_SW4END0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_FEED_EE2A1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_FEED_LH6", - "INT_INTERFACE_LH6" - ], - [ - "CLK_FEED_EE4A1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_FEED_EE2BEG3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_FEED_SE4BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_FEED_LH7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_FEED_EL1BEG0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_FEED_LH11", - "INT_INTERFACE_LH11" - ], - [ - "CLK_FEED_WR1END2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_FEED_WW4END0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_FEED_WW4B3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_FEED_NW4A3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_FEED_WW2A1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_PMV_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_PMV_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_FEED_SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_FEED_ER1BEG0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_PMV_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_FEED_ER1BEG2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_PMV_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_PMV_LOGIC_OUTS0_0", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_FEED_WW4A3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_FEED_EE4BEG2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_FEED_EE4A2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_EE2A0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_PMV_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_FEED_NW2A2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_FEED_WW4A2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_FEED_WW2END1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_FEED_WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_FEED_LH4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_FEED_EE2BEG1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_FEED_NE4BEG2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_FEED_EE4C0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_FEED_LH12", - "INT_INTERFACE_LH12" - ], - [ - "CLK_FEED_NE2A2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_FEED_WW4END1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_FEED_EE4BEG1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_PMV_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_FEED_LH2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_FEED_NE2A0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_FEED_NW4A0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_NW4END3", - "INT_INTERFACE_NW4END3" - ] - ] - }, - { - "grid_deltas": [ - 1, - 4 - ], - "tile_types": [ - "BRAM_INT_INTERFACE_R", - "BRAM_R" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_WW4END2", - "BRAM_WW4END2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX30", - "BRAM_IMUX30_UTURN_4" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX26", - "BRAM_IMUX26_UTURN_4" - ], - [ - "INT_INTERFACE_SW4A0", - "BRAM_SW4A0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX18", - "BRAM_IMUX18_UTURN_4" - ], - [ - "INT_INTERFACE_WW4C3", - "BRAM_WW4C3_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B0", - "BRAM_LOGIC_OUTS_B0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX45", - "BRAM_IMUX45_UTURN_4" - ], - [ - "INT_INTERFACE_LH3", - "BRAM_LH3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX11", - "BRAM_IMUX11_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX33", - "BRAM_IMUX33_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_4" - ], - [ - "INT_INTERFACE_SE2A0", - "BRAM_SE2A0_4" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX14", - "BRAM_IMUX14_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_4" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX32", - "BRAM_IMUX32_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX3", - "BRAM_IMUX3_UTURN_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B9", - "BRAM_LOGIC_OUTS_B9_4" - ], - [ - "INT_INTERFACE_WR1END1", - "BRAM_WR1END1_4" - ], - [ - "INT_INTERFACE_WW2END2", - "BRAM_WW2END2_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B13", - "BRAM_LOGIC_OUTS_B13_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX1", - "BRAM_IMUX1_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX2", - "BRAM_IMUX2_UTURN_4" - ], - [ - "INT_INTERFACE_NW4A2", - "BRAM_NW4A2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX24", - "BRAM_IMUX24_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_4" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_4" - ], - [ - "INT_INTERFACE_NE4C3", - "BRAM_NE4C3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX34", - "BRAM_IMUX34_4" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B16", - "BRAM_LOGIC_OUTS_B16_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B10", - "BRAM_LOGIC_OUTS_B10_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B4", - "BRAM_LOGIC_OUTS_B4_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX44", - "BRAM_IMUX44_UTURN_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B21", - "BRAM_LOGIC_OUTS_B21_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B23", - "BRAM_LOGIC_OUTS_B23_4" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B15", - "BRAM_LOGIC_OUTS_B15_4" - ], - [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_4" - ], - [ - "INT_INTERFACE_CLK1", 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"VBRK_LH3" - ], - [ - "CLK_FEED_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLK_FEED_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLK_FEED_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLK_FEED_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "HCLK_R", - "INT_R" - ], - "wire_pairs": [ - [ - "HCLK_SW6E3", - "SW6E3" - ], - [ - "HCLK_NN2A1", - "NN2A1" - ], - [ - "HCLK_EL1BEG3", - "EL1BEG3" - ], - [ - "HCLK_NE2END_S3_0", - "NE2END_S3_0" - ], - [ - "HCLK_ER1BEG_S0", - "ER1BEG_S0" - ], - [ - "HCLK_NR1BEG2", - "NR1BEG2" - ], - [ - "HCLK_SS6END2", - "SS6END2" - ], - [ - "HCLK_SS2END_N0_3", - "SS2END3" - ], - [ - "HCLK_LV11", - "LV11" - ], - [ - "HCLK_SS6A2", - "SS6A2" - ], - [ - "HCLK_SE6D0", - "SE6D0" - ], - [ - "HCLK_NR1BEG1", - "NR1BEG1" - ], - [ - "HCLK_NE6B2", - "NE6B2" - ], - [ - "HCLK_NN2A0", - "NN2A0" - ], - [ - "HCLK_LV17", - "LV17" - ], - [ - "HCLK_SS6C0", - "SS6C0" - ], - [ - "HCLK_NW6C0", - "NW6C0" - ], - [ - "HCLK_NW6D2", - "NW6D2" - ], - [ - "HCLK_NN6A1", - "NN6A1" - ], - [ - "HCLK_SS6D0", - "SS6D0" - ], - [ - "HCLK_NW2A1", - "NW2BEG1" - ], - [ - "HCLK_WL1BEG3", - "WL1BEG3" - ], - [ - "HCLK_SW6D3", - "SW6D3" - ], - [ - "HCLK_NE6A2", - "NE6A2" - ], - [ - "HCLK_NE6D2", - "NE6D2" - ], - [ - "HCLK_SS6C2", - "SS6C2" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END_S1_0" - ], - [ - "HCLK_SE6C0", - "SE6C0" - ], - [ - "HCLK_LVB2", - "LVB1" - ], - [ - "HCLK_LV8", - "LV8" - ], - [ - "HCLK_SW6E0", - "SW6E0" - ], - [ - "HCLK_SW6D2", - "SW6D2" - ], - [ - "HCLK_ER1END3", - "ER1END3" - ], - [ - "HCLK_NW6A1", - "NW6A1" - ], - [ - "HCLK_SS6B0", - "SS6B0" - ], - [ - "HCLK_NN2A2", - "NN2A2" - ], - [ - "HCLK_NE6C0", - "NE6C0" - ], - [ - "HCLK_SS6A1", - "SS6A1" - ], - [ - "HCLK_LVB4", - "LVB3" - ], - [ - "HCLK_SE6E0", - "SE6E0" - ], - [ - "HCLK_NE2BEG0", - "NE2BEG0" - ], - [ - "HCLK_NE6D0", - "NE6D0" - ], - [ - "HCLK_LVB6", - "LVB5" - ], - [ - "HCLK_SW6C0", - "SW6C0" - ], - [ - "HCLK_NN6E2", - "NN6E2" - ], - [ - "HCLK_FAN_BOUNCE_S3_6", - "FAN_BOUNCE_S3_6" - ], - [ - "HCLK_NN6B3", - "NN6B3" - ], - [ - "HCLK_SR1END2", - "SR1END2" - ], - [ - "HCLK_SS6END1", - "SS6END1" - ], - [ - "HCLK_NN6D2", - "NN6D2" - ], - [ - "HCLK_LVB12", - "LVB11" - ], - [ - "HCLK_NW6C2", - "NW6C2" - ], - [ - "HCLK_SL1END3", - "SL1END3" - ], - [ - "HCLK_LV15", - "LV15" - ], - [ - "HCLK_NE6C1", - "NE6C1" - ], - [ - "HCLK_SL1END1", - "SL1END1" - ], - [ - "HCLK_NR1BEG0", - "NR1BEG0" - ], - [ - "HCLK_SW6C2", - "SW6C2" - ], - [ - "HCLK_WL1END3", - "WL1END3" - ], - [ - "HCLK_NE2BEG1", - "NE2BEG1" - ], - [ - "HCLK_SW2END2", - "SW2A2" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END3" - ], - [ - "HCLK_NN6BEG2", - "NN6BEG2" - ], - [ - "HCLK_SS6A3", - "SS6A3" - ], - [ - "HCLK_NW6A2", - "NW6A2" - ], - [ - "HCLK_NN6D3", - "NN6D3" - ], - [ - "HCLK_SS6E2", - "SS6E2" - ], - [ - "HCLK_NN6END_S1_0", - "NN6END_S1_0" - ], - [ - "HCLK_LEAF_CLK_B_BOT1", - "GCLK_B1" - ], - [ - "HCLK_NW2A2", - "NW2BEG2" - ], - [ - "HCLK_SE6E1", - "SE6E1" - ], - [ - "HCLK_SL1END0", - "SL1END0" - ], - [ - "HCLK_SW6C3", - "SW6C3" - ], - [ - "HCLK_SR1END_N3_3", - "SR1END3" - ], - [ - "HCLK_NN6D1", - "NN6D1" - ], - [ - "HCLK_LV6", - "LV6" - ], - [ - "HCLK_SS6END0", - "SS6END0" - ], - [ - "HCLK_SS6E3", - "SS6E3" - ], - [ - "HCLK_SS6D3", - "SS6D3" - ], - [ - "HCLK_SS6C1", - "SS6C1" - ], - [ - "HCLK_NW2END_S0_0", - "NW2END_S0_0" - ], - [ - "HCLK_NW6B3", - "NW6B3" - ], - [ - "HCLK_WR1BEG_S0", - "WR1BEG_S0" - ], - [ - "HCLK_NE6D1", - "NE6D1" - ], - [ - "HCLK_SS2A3", - "SS2END3" - ], - [ - "HCLK_SW6C1", - "SW6C1" - ], - [ - "HCLK_SS6A0", - "SS6A0" - ], - [ - "HCLK_NN2A3", - "NN2A3" - ], - [ - "HCLK_LV10", - "LV10" - ], - [ - "HCLK_SE6B0", - "SE6B0" - ], - [ - "HCLK_NE6D3", - "NE6D3" - ], - [ - "HCLK_NN6E1", - "NN6E1" - ], - [ - "HCLK_LVB1", - "LVB0" - ], - [ - "HCLK_NE6A3", - "NE6A3" - ], - [ - "HCLK_LV0", - "LV0" - ], - [ - "HCLK_SS6E0", - "SS6E0" - ], - [ - "HCLK_LVB11", - "LVB10" - ], - [ - "HCLK_SE6B3", - "SE6B3" - ], - [ - "HCLK_SE6B1", - "SE6B1" - ], - [ - "HCLK_LEAF_CLK_B_BOT4", - "GCLK_B4" - ], - [ - "HCLK_LEAF_CLK_B_BOT3", - "GCLK_B3" - ], - [ - "HCLK_LVB7", - "LVB6" - ], - [ - "HCLK_LEAF_CLK_B_BOT0", - "GCLK_B0" - ], - [ - "HCLK_SW6D1", - "SW6D1" - ], - [ - "HCLK_LEAF_CLK_B_BOT2", - "GCLK_B2" - ], - [ - "HCLK_BYP_BOUNCE7", - "BYP_BOUNCE7" - ], - [ - "HCLK_SS6B2", - "SS6B2" - ], - [ - "HCLK_NL1BEG1", - "NL1BEG1" - ], - [ - "HCLK_NE2BEG3", - "NE2BEG3" - ], - [ - "HCLK_NE6A0", - "NE6A0" - ], - [ - "HCLK_NE6C2", - "NE6C2" - ], - [ - "HCLK_LVB3", - "LVB2" - ], - [ - "HCLK_NW2A0", - "NW2BEG0" - ], - [ - "HCLK_NW6B0", - "NW6B0" - ], - [ - "HCLK_SS6B1", - "SS6B1" - ], - [ - "HCLK_LV9", - "LV9" - ], - [ - "HCLK_SS6E1", - "SS6E1" - ], - [ - "HCLK_SS2A0", - "SS2A0" - ], - [ - "HCLK_WW2END3", - "WW2END3" - ], - [ - "HCLK_SS6D2", - "SS6D2" - ], - [ - "HCLK_NW6END_S0_0", - "NW6END_S0_0" - ], - [ - "HCLK_FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_2" - ], - [ - "HCLK_LV12", - "LV12" - ], - [ - "HCLK_LVB10", - "LVB9" - ], - [ - "HCLK_SE2A1", - "SE2A1" - ], - [ - "HCLK_NN2BEG1", - "NN2BEG1" - ], - [ - "HCLK_NN2BEG2", - "NN2BEG2" - ], - [ - "HCLK_NE2BEG2", - "NE2BEG2" - ], - [ - "HCLK_SW6B3", - "SW6B3" - ], - [ - "HCLK_NN6BEG1", - "NN6BEG1" - ], - [ - "HCLK_SS2END0", - "SS2END0" - ], - [ - "HCLK_SS2A2", - "SS2A2" - ], - [ - "HCLK_LV4", - "LV4" - ], - [ - "HCLK_LVB5", - "LVB4" - ], - [ - "HCLK_NN6B2", - "NN6B2" - ], - [ - "HCLK_SS2END1", - "SS2END1" - ], - [ - "HCLK_NN6A3", - "NN6A3" - ], - [ - "HCLK_SW6D0", - "SW6D0" - ], - [ - "HCLK_NL1BEG2", - "NL1BEG2" - ], - [ - "HCLK_SW6E1", - "SW6E1" - ], - [ - "HCLK_LV2", - "LV2" - ], - [ - "HCLK_NN6A2", - "NN6A2" - ], - [ - "HCLK_SW6B0", - "SW6B0" - ], - [ - "HCLK_NW6D0", - "NW6D0" - ], - [ - "HCLK_SW6END3", - "SW6END3" - ], - [ - "HCLK_NW6C3", - "NW6C3" - ], - [ - "HCLK_SW2END0", - "SW2A0" - ], - [ - "HCLK_NN6A0", - "NN6A0" - ], - [ - "HCLK_SW6E2", - "SW6E2" - ], - [ - "HCLK_SS2BEG3", - "SS2A3" - ], - [ - "HCLK_NW6D3", - "NW6D3" - ], - [ - "HCLK_SE6C1", - "SE6C1" - ], - [ - "HCLK_LV7", - "LV7" - ], - [ - "HCLK_NN6C2", - "NN6C2" - ], - [ - "HCLK_SS6END3", - "SS6END3" - ], - [ - "HCLK_SE6E3", - "SE6E3" - ], - [ - "HCLK_WW4END_S0_0", - "WW4END_S0_0" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE2" - ], - [ - "HCLK_NN6C1", - "NN6C1" - ], - [ - "HCLK_NN2END_S2_0", - "NN2END_S2_0" - ], - [ - "HCLK_NW6D1", - "NW6D1" - ], - [ - "HCLK_LV3", - "LV3" - ], - [ - "HCLK_LVB9", - "LVB8" - ], - [ - "HCLK_SR1END1", - "SR1END1" - ], - [ - "HCLK_SS6B3", - "SS6B3" - ], - [ - "HCLK_EL1END_S3_0", - "EL1END_S3_0" - ], - [ - "HCLK_FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_4" - ], - [ - "HCLK_NN6E0", - "NN6E0" - ], - [ - "HCLK_SS6D1", - "SS6D1" - ], - [ - "HCLK_SS2END2", - "SS2END2" - ], - [ - "HCLK_NL1BEG0", - "NL1BEG0" - ], - [ - "HCLK_NN2BEG3", - "NN2BEG3" - ], - [ - "HCLK_NW6A3", - "NW6A3" - ], - [ - "HCLK_SE6C2", - "SE6C2" - ], - [ - "HCLK_SR1BEG3", - "SR1END3" - ], - [ - "HCLK_NW6C1", - "NW6C1" - ], - [ - "HCLK_LV1", - "LV1" - ], - [ - "HCLK_NE6A1", - "NE6A1" - ], - [ - "HCLK_SL1END2", - "SL1END2" - ], - [ - "HCLK_LV5", - "LV5" - ], - [ - "HCLK_LV14", - "LV14" - ], - [ - "HCLK_SE6E2", - "SE6E2" - ], - [ - "HCLK_NE6B1", - "NE6B1" - ], - [ - "HCLK_NE6B0", - "NE6B0" - ], - [ - "HCLK_NN6E3", - "NN6E3" - ], - [ - "HCLK_SE2A3", - "SE2A3" - ], - [ - "HCLK_SE6C3", - "SE6C3" - ], - [ - "HCLK_SS6END_N0_3", - "SS6END3" - ], - [ - "HCLK_SE2A2", - "SE2A2" - ], - [ - "HCLK_NL1END_S3_0", - "NL1END_S3_0" - ], - [ - "HCLK_SS6C3", - "SS6C3" - ], - [ - "HCLK_NN6BEG3", - "NN6BEG3" - ], - [ - "HCLK_NN6D0", - "NN6D0" - ], - [ - "HCLK_BYP_BOUNCE6", - "BYP_BOUNCE6" - ], - [ - "HCLK_LV16", - "LV16" - ], - [ - "HCLK_BYP_BOUNCE3", - "BYP_BOUNCE3" - ], - [ - "HCLK_SE6D1", - "SE6D1" - ], - [ - "HCLK_SS2A1", - "SS2A1" - ], - [ - "HCLK_LEAF_CLK_B_BOT5", - "GCLK_B5" - ], - [ - "HCLK_SW6B2", - "SW6B2" - ], - [ - "HCLK_LVB8", - "LVB7" - ], - [ - "HCLK_NW6B2", - "NW6B2" - ], - [ - "HCLK_NE6B3", - "NE6B3" - ], - [ - "HCLK_NE6C3", - "NE6C3" - ], - [ - "HCLK_SE6B2", - "SE6B2" - ], - [ - "HCLK_NN6C3", - "NN6C3" - ], - [ - "HCLK_LV13", - "LV13" - ], - [ - "HCLK_SE6D2", - "SE6D2" - ], - [ - "HCLK_SW2END1", - "SW2A1" - ], - [ - "HCLK_NN6B0", - "NN6B0" - ], - [ - "HCLK_SW6B1", - "SW6B1" - ], - [ - "HCLK_NW2A3", - "NW2BEG3" - ], - [ - "HCLK_SW2A3", - "SW2A3" - ], - [ - "HCLK_SE2A0", - "SE2A0" - ], - [ - "HCLK_FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_0" - ], - [ - "HCLK_NN2BEG0", - "NN2BEG0" - ], - [ - "HCLK_SE6D3", - "SE6D3" - ], - [ - "HCLK_NN6B1", - "NN6B1" - ], - [ - "HCLK_NN6C0", - "NN6C0" - ], - [ - "HCLK_NW6B1", - "NW6B1" - ], - [ - "HCLK_NW6A0", - "NW6A0" - ], - [ - "HCLK_NN6BEG0", - "NN6BEG0" - ], - [ - "HCLK_NR1BEG3", - "NR1BEG3" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_TERM" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_TERM_R_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_TERM_R_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_TERM_R_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_TERM_R_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_TERM_R_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_TERM_R_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_TERM_R_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_TERM_R_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_TERM_R_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_TERM_R_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_TERM_R_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_TERM_R_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_TERM_R_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_TERM_R_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_TERM_R_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_TERM_R_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_TERM_R_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_TERM_R_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_TERM_R_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_TERM_R_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_TERM_R_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_TERM_R_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_TERM_R_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_TERM_R_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_TERM_R_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_TERM_R_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_TERM_R_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_TERM_R_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_TERM_R_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_TERM_R_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_TERM_R_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_TERM_R_GCLK19" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "BRKH_CLB", - "CLBLL_L" - ], - "wire_pairs": [ - [ - "BRKH_CLB_COUT1_L", - "CLBLL_L_CIN" - ], - [ - "BRKH_CLB_COUT0_L", - "CLBLL_LL_CIN" - ] - ] - }, - { - "grid_deltas": [ - -1, - 1 - ], - "tile_types": [ - "CMT_FIFO_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CMT_FIFO_L_FAN5_5", - "INT_INTERFACE_FAN5" - ], - [ - "CMT_FIFO_L_IMUX46_5", - "INT_INTERFACE_IMUX46" - ], - [ - "CMT_FIFO_ER1BEG1_5", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CMT_FIFO_EE2BEG0_5", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CMT_FIFO_SE4C0_5", - "INT_INTERFACE_SE4C0" - ], - [ - "CMT_FIFO_WW4C3_5", - "INT_INTERFACE_WW4C3" - ], - [ - "CMT_FIFO_L_IMUX2_5", - "INT_INTERFACE_IMUX2" - ], - [ - "CMT_FIFO_EE4B0_5", - "INT_INTERFACE_EE4B0" - ], - [ - "CMT_FIFO_L_FAN0_5", - "INT_INTERFACE_FAN0" - ], - [ - "CMT_FIFO_WW2A0_5", - "INT_INTERFACE_WW2A0" - ], - [ - "CMT_FIFO_L_IMUX21_5", - "INT_INTERFACE_IMUX21" - ], - [ - "CMT_FIFO_L_IMUX5_5", - "INT_INTERFACE_IMUX5" - ], - [ - "CMT_FIFO_L_IMUX18_5", - "INT_INTERFACE_IMUX18" - ], - [ - "CMT_FIFO_EL1BEG1_5", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CMT_FIFO_L_IMUX47_5", - "INT_INTERFACE_IMUX47" - ], - [ - "CMT_FIFO_SW4A3_5", - "INT_INTERFACE_SW4A3" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS0_5", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS8_5", - "INT_INTERFACE_LOGIC_OUTS_B8" - ], - [ - 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"PCIE_IMUX41_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT41" - ], - [ - "PCIE_IMUX15_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT15" - ], - [ - "PCIE_IMUX47_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT47" - ], - [ - "PCIE_ER1BEG2_19", - "INT_INTERFACE_ER1BEG2" - ], - [ - "PCIE_LOGIC_OUTS_B5_R_19", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "PCIE_LH3_19", - "INT_INTERFACE_LH3" - ], - [ - "PCIE_NE2A1_19", - "INT_INTERFACE_NE2A1" - ], - [ - "PCIE_WW4A2_19", - "INT_INTERFACE_WW4A2" - ], - [ - "PCIE_WW4END0_19", - "INT_INTERFACE_WW4END0" - ], - [ - "PCIE_WW2END1_19", - "INT_INTERFACE_WW2END1" - ], - [ - "PCIE_IMUX2_R_19", - "PCIE_INT_INTERFACE_IMUX_OUT2" - ], - [ - "PCIE_EE2BEG0_19", - "INT_INTERFACE_EE2BEG0" - ], - [ - "PCIE_FAN5_R_19", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_NE2A2_19", - "INT_INTERFACE_NE2A2" - ], - [ - "PCIE_MONITOR_N_19", - "INT_INTERFACE_MONITOR_N" - ], - [ - "PCIE_LOGIC_OUTS_B22_R_19", - "INT_INTERFACE_LOGIC_OUTS_B22" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "LIOB33", - "LIOI3" - ], - "wire_pairs": [ - [ - "IOB_IBUF_DISABLE1", - "LIOI_IBUF_DISABLE1" - ], - [ - "IOB_PU_INT_EN_0", - "LIOI_PU_INT_EN_0" - ], - [ - "IOB_DIFF_TERM_INT_EN", - "LIOI_DIFF_TERM_INT_EN" - ], - [ - "IOB_KEEPER_INT_EN_1", - "LIOI_KEEPER_INT_EN_1" - ], - [ - "IOB_PD_INT_EN_1", - "LIOI_PD_INT_EN_1" - ], - [ - "IOB_T1", - "LIOI_T1" - ], - [ - "IOB_IBUF1", - "LIOI_IBUF1" - ], - [ - "IOB_IBUF0", - "LIOI_IBUF0" - ], - [ - "IOB_T0", - "LIOI_T0" - ], - [ - "IOB_IBUF_DISABLE0", - "LIOI_IBUF_DISABLE0" - ], - [ - "IOB_O0", - "LIOI_O0" - ], - [ - "LIOB_IN_TERM1", - "LIOI_DCI_T_TERM1" - ], - [ - "IOB_PD_INT_EN_0", - "LIOI_PD_INT_EN_0" - ], - [ - "IOB_O1", - "LIOI_O1" - ], - [ - "LIOB_MONITOR_N", - "IOI_MONITOR_N" - ], - [ - "IOB_PU_INT_EN_1", - "LIOI_PU_INT_EN_1" - ], - [ - "IOB_KEEPER_INT_EN_0", - "LIOI_KEEPER_INT_EN_0" - ], - [ - "LIOB_IN_TERM0", - "LIOI_DCI_T_TERM0" - ], - [ - "LIOB_MONITOR_P", - "IOI_MONITOR_P" - ] - ] - }, - { - "grid_deltas": [ - -1, - 2 - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_NW2A3_2", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_IMUX14_2", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_IMUX17_2", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_IMUX15_2", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_IMUX42_2", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_LH4_2", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_BYP6_2", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_SW4A2_2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE4B1_2", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_WW2END2_2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_EE4A0_2", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_NE4BEG2_2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_IMUX19_2", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_MONITOR_N_2", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_IMUX16_2", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WR1END3_2", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_WW4A0_2", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_BYP0_2", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_IMUX20_2", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_IMUX27_2", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_IMUX5_2", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_SW4END3_2", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_IMUX31_2", - "INT_INTERFACE_IMUX31" - ], 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- "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WR1END2_2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX32_2", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NE2A1_2", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_LH9_2", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_FAN3_2", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_LH2_2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_SE2A1_2", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE2A0_2", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4B3_2", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_CTRL0_2", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX23_2", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_ER1BEG2_2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX12_2", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SW2A3_2", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_EE4BEG0_2", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX37_2", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_FAN2_2", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_LH1_2", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WR1END1_2", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_NW4A3_2", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_BYP4_2", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_IMUX40_2", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_IMUX39_2", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_EE2A2_2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_WW4B0_2", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_EL1BEG2_2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX8_2", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_LH11_2", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_IMUX29_2", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX43_2", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_EE4C0_2", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_BYP5_2", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_WW2A3_2", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_WW4END2_2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_FAN6_2", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4C2_2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SE4BEG1_2", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NW4A1_2", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_EE2A1_2", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_IMUX18_2", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_WW4B2_2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_WW2A1_2", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX7_2", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_IMUX9_2", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4A3_2", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_NE2A3_2", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_FAN1_2", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_SE4BEG0_2", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_IMUX3_2", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_SE4C0_2", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_SW4END0_2", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WW4A3_2", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EE2BEG3_2", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_SE4C1_2", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX45_2", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_EE4BEG2_2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW4C3_2", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW2END3_2", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW2END0_2", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_WR1END0_2", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE2BEG0_2", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_EE4B2_2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NE4BEG0_2", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_MONITOR_P_2", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_NE4C1_2", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_IMUX22_2", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_NW4END2_2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EL1BEG0_2", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_SW2A1_2", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NE4BEG3_2", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_WW4C1_2", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_SW4A1_2", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_WW2A2_2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_WW4B3_2", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_LH12_2", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_EE2BEG1_2", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_NW4END1_2", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WL1END0_2", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NE2A2_2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_WW4END1_2", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_CTRL1_2", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW4END3_2", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_NW4END3_2", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SE2A2_2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_BYP1_2", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_FAN7_2", - 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- ] - }, - { - "grid_deltas": [ - 0, - 4 - ], - "tile_types": [ - "BRKH_CLK", - "CLK_BUFG_BOT_R" - ], - "wire_pairs": [ - [ - "BRKH_CLK_R_CK_GCLK30", - "CLK_BUFG_CK_GCLK30" - ], - [ - "BRKH_CLK_R_CK_GCLK11", - "CLK_BUFG_CK_GCLK11" - ], - [ - "BRKH_CLK_R_CK_GCLK19", - "CLK_BUFG_CK_GCLK19" - ], - [ - "BRKH_CLK_R_CK_GCLK3", - "CLK_BUFG_CK_GCLK3" - ], - [ - "BRKH_CLK_R_CK_GCLK21", - "CLK_BUFG_CK_GCLK21" - ], - [ - "BRKH_CLK_R_CK_GCLK6", - "CLK_BUFG_CK_GCLK6" - ], - [ - "BRKH_CLK_R_CK_GCLK23", - "CLK_BUFG_CK_GCLK23" - ], - [ - "BRKH_CLK_R_CK_GCLK29", - "CLK_BUFG_CK_GCLK29" - ], - [ - "BRKH_CLK_R_CK_GCLK28", - "CLK_BUFG_CK_GCLK28" - ], - [ - "BRKH_CLK_R_CK_GCLK25", - "CLK_BUFG_CK_GCLK25" - ], - [ - "BRKH_CLK_R_CK_GCLK8", - "CLK_BUFG_CK_GCLK8" - ], - [ - "BRKH_CLK_R_CK_GCLK12", - "CLK_BUFG_CK_GCLK12" - ], - [ - "BRKH_CLK_R_CK_GCLK22", - "CLK_BUFG_CK_GCLK22" - ], - [ - "BRKH_CLK_R_CK_GCLK9", - "CLK_BUFG_CK_GCLK9" - ], - [ - "BRKH_CLK_R_CK_GCLK15", - "CLK_BUFG_CK_GCLK15" - ], - [ - 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"IOI_LOGIC_OUTS6_0", - "TERM_INT_LOGIC_OUTS_L_B6" - ], - [ - "IOI_BYP3_0", - "TERM_INT_BYP3" - ], - [ - "IOI_BLOCK_OUTS1_0", - "TERM_INT_BLOCK_OUTS_L_B1" - ], - [ - "IOI_FAN4_0", - "TERM_INT_FAN4" - ], - [ - "IOI_BYP7_0", - "TERM_INT_BYP7" - ], - [ - "IOI_IMUX18_0", - "TERM_INT_IMUX18" - ], - [ - "IOI_BYP1_0", - "TERM_INT_BYP1" - ], - [ - "IOI_IMUX24_0", - "TERM_INT_IMUX24" - ], - [ - "IOI_MONITOR_P", - "TERM_INT_MONITOR_P" - ], - [ - "IOI_LOGIC_OUTS12_0", - "TERM_INT_LOGIC_OUTS_L_B12" - ], - [ - "IOI_PHASER_TO_IO_OCLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "IOI_BLOCK_OUTS0_0", - "TERM_INT_BLOCK_OUTS_L_B0" - ], - [ - "IOI_LOGIC_OUTS4_0", - "TERM_INT_LOGIC_OUTS_L_B4" - ], - [ - "IOI_LOGIC_OUTS22_0", - "TERM_INT_LOGIC_OUTS_L_B22" - ], - [ - "IOI_IMUX33_0", - "TERM_INT_IMUX33" - ], - [ - "IOI_IMUX30_0", - "TERM_INT_IMUX30" - ], - [ - "IOI_BYP5_0", - "TERM_INT_BYP5" - ], - [ - "IOI_IMUX5_0", - "TERM_INT_IMUX5" - ], - [ - "IOI_LOGIC_OUTS14_0", - "TERM_INT_LOGIC_OUTS_L_B14" - ], - [ - "IOI_FAN0_0", - "TERM_INT_FAN0" - ], - [ - "IOI_IMUX45_0", - "TERM_INT_IMUX45" - ], - [ - "IOI_LOGIC_OUTS1_0", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_LOGIC_OUTS3_0", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_IMUX32_0", - "TERM_INT_IMUX32" - ], - [ - "IOI_LOGIC_OUTS7_0", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_BYP2_0", - "TERM_INT_BYP2" - ], - [ - "IOI_IMUX46_0", - "TERM_INT_IMUX46" - ], - [ - "IOI_LOGIC_OUTS15_0", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_IMUX8_0", - "TERM_INT_IMUX8" - ], - [ - "IOI_LOGIC_OUTS5_0", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_IMUX2_0", - "TERM_INT_IMUX2" - ], - [ - "IOI_LOGIC_OUTS20_0", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_IMUX26_0", - "TERM_INT_IMUX26" - ], - [ - "IOI_IMUX28_0", - "TERM_INT_IMUX28" - ], - [ - "IOI_IMUX41_0", - "TERM_INT_IMUX41" - ], - [ - "IOI_IMUX47_0", - "TERM_INT_IMUX47" - ], - [ - "IOI_LOGIC_OUTS8_0", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_IMUX38_0", - "TERM_INT_IMUX38" - ], - [ - "IOI_IMUX0_0", - "TERM_INT_IMUX0" - ], - [ - "IOI_IMUX6_0", - "TERM_INT_IMUX6" - ], - [ - "IOI_IMUX44_0", - "TERM_INT_IMUX44" - ], - [ - "IOI_LOGIC_OUTS2_0", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "IOI_IMUX35_0", - "TERM_INT_IMUX35" - ], - [ - "IOI_FAN1_0", - "TERM_INT_FAN1" - ], - [ - "IOI_IMUX17_0", - "TERM_INT_IMUX17" - ] - ] - }, - { - "grid_deltas": [ - 1, - -1 - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_HROW_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_HROW_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_HROW_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_LH1_1", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH6_1", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_HROW_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_HROW_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NE4BEG3_1", - "VBRK_NE4BEG3" - ] - ] - }, - { - "grid_deltas": [ - 1, - -6 - ], - "tile_types": [ - "CLK_PMV", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_PMV_SW2A2_6", - "VBRK_SW2A2" - ], - [ - "CLK_PMV_NE4C0_6", - "VBRK_NE4C0" - ], - [ - "CLK_PMV_SW4A3_6", - "VBRK_SW4A3" - ], - [ - "CLK_PMV_WW4A1_6", - "VBRK_WW4A1" - ], - [ - "CLK_PMV_WL1END2_6", - "VBRK_WL1END2" - ], - [ - "CLK_PMV_NE4BEG0_6", - "VBRK_NE4BEG0" - ], - [ - "CLK_PMV_SE4C0_6", - "VBRK_SE4C0" - ], - [ - "CLK_PMV_WR1END0_6", - "VBRK_WR1END0" - ], - [ - "CLK_PMV_EE4A0_6", - "VBRK_EE4A0" - ], - [ - "CLK_PMV_SE2A3_6", - "VBRK_SE2A3" - ], - [ - "CLK_PMV_SE4BEG2_6", - "VBRK_SE4BEG2" - ], - [ - "CLK_PMV_EE2A1_6", - "VBRK_EE2A1" - ], - [ - "CLK_PMV_WW4C0_6", - "VBRK_WW4C0" - ], - [ - "CLK_PMV_LH9_6", - "VBRK_LH9" - ], - [ - "CLK_PMV_EE2A3_6", - "VBRK_EE2A3" - ], - [ - "CLK_PMV_NW4END1_6", - "VBRK_NW4END1" - ], - [ - "CLK_PMV_SE2A2_6", - "VBRK_SE2A2" - ], - [ - "CLK_PMV_EE2BEG3_6", - "VBRK_EE2BEG3" - ], - [ - "CLK_PMV_EE4C3_6", - "VBRK_EE4C3" - ], - [ - "CLK_PMV_WW4C3_6", - "VBRK_WW4C3" - ], - [ - "CLK_PMV_NW4END3_6", - "VBRK_NW4END3" - ], - [ - "CLK_PMV_WR1END1_6", - "VBRK_WR1END1" - ], - [ - "CLK_PMV_WW4C2_6", - "VBRK_WW4C2" - ], - [ - "CLK_PMV_SE2A1_6", - "VBRK_SE2A1" - ], - [ - "CLK_PMV_EE4B2_6", - "VBRK_EE4B2" - ], - [ - "CLK_PMV_LH5_6", - "VBRK_LH5" - ], - [ - "CLK_PMV_WW4END0_6", - "VBRK_WW4END0" - ], - [ - "CLK_PMV_LH4_6", - "VBRK_LH4" - ], - [ - "CLK_PMV_SE4BEG1_6", - "VBRK_SE4BEG1" - ], - [ - "CLK_PMV_EE2A2_6", - "VBRK_EE2A2" - ], - [ - "CLK_PMV_WW2END0_6", - "VBRK_WW2END0" - ], - [ - "CLK_PMV_WW4END2_6", - "VBRK_WW4END2" - ], - [ - "CLK_PMV_EL1BEG1_6", - "VBRK_EL1BEG1" - ], - [ - "CLK_PMV_EE4BEG2_6", - "VBRK_EE4BEG2" - ], - [ - "CLK_PMV_SW4A2_6", - "VBRK_SW4A2" - ], - [ - "CLK_PMV_NW4A1_6", - "VBRK_NW4A1" - ], - [ - "CLK_PMV_WW2A0_6", - "VBRK_WW2A0" - ], - [ - "CLK_PMV_WR1END2_6", - "VBRK_WR1END2" - ], - [ - "CLK_PMV_EE4A1_6", - "VBRK_EE4A1" - ], - [ - "CLK_PMV_ER1BEG1_6", - "VBRK_ER1BEG1" - ], - [ - "CLK_PMV_EE4A2_6", - "VBRK_EE4A2" - ], - [ - "CLK_PMV_WW4B0_6", - "VBRK_WW4B0" - ], - [ - "CLK_PMV_WW2END3_6", - "VBRK_WW2END3" - ], - [ - "CLK_PMV_LH3_6", - "VBRK_LH3" - ], - [ - "CLK_PMV_EE4BEG1_6", - "VBRK_EE4BEG1" - ], - [ - "CLK_PMV_NE2A1_6", - "VBRK_NE2A1" - ], - [ - "CLK_PMV_MONITOR_P_6", - "VBRK_MONITOR_P" - ], - [ - "CLK_PMV_SW4END0_6", - "VBRK_SW4END0" - ], - [ - "CLK_PMV_EE2BEG2_6", - "VBRK_EE2BEG2" - ], - [ - "CLK_PMV_LH7_6", - "VBRK_LH7" - ], - [ - "CLK_PMV_SE4BEG3_6", - "VBRK_SE4BEG3" - ], - [ - "CLK_PMV_WW2END2_6", - "VBRK_WW2END2" - ], - [ - "CLK_PMV_EL1BEG0_6", - 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"CMT_TOP_IMUX31_12" - ], - [ - "CMT_PMV_SW4A2", - "CMT_TOP_SW4A2_12" - ], - [ - "CMT_PMV_LH7", - "CMT_TOP_LH7_12" - ], - [ - "CMT_PMV_WW4END2", - "CMT_TOP_WW4END2_12" - ], - [ - "CMT_PMV_WW4A2", - "CMT_TOP_WW4A2_12" - ], - [ - "CMT_PMV_ER1BEG2", - "CMT_TOP_ER1BEG2_12" - ], - [ - "CMT_PMV_IMUX29", - "CMT_TOP_IMUX29_12" - ], - [ - "CMT_PMV_IMUX19", - "CMT_TOP_IMUX19_12" - ], - [ - "CMT_PMV_IMUX12", - "CMT_TOP_IMUX12_12" - ], - [ - "CMT_PMV_LOGIC_OUTS21", - "CMT_TOP_LOGIC_OUTS_L_B21_12" - ], - [ - "CMT_PMV_FAN1", - "CMT_TOP_FAN1_12" - ], - [ - "CMT_PMV_SE4BEG0", - "CMT_TOP_SE4BEG0_12" - ], - [ - "CMT_PMV_SE4BEG2", - "CMT_TOP_SE4BEG2_12" - ], - [ - "CMT_PMV_EE4BEG1", - "CMT_TOP_EE4BEG1_12" - ], - [ - "CMT_PMV_IMUX15", - "CMT_TOP_IMUX15_12" - ], - [ - "CMT_PMV_LH2", - "CMT_TOP_LH2_12" - ], - [ - "CMT_PMV_NE4BEG1", - "CMT_TOP_NE4BEG1_12" - ], - [ - "CMT_PMV_WW4C3", - "CMT_TOP_WW4C3_12" - ], - [ - "CMT_PMV_NE4C0", - "CMT_TOP_NE4C0_12" - ], - [ - "CMT_PMV_IMUX33", - "CMT_TOP_IMUX33_12" - ], - [ - "CMT_PMV_ER1BEG1", - "CMT_TOP_ER1BEG1_12" - ], - [ - "CMT_PMV_IMUX20", - "CMT_TOP_IMUX20_12" - ], - [ - "CMT_PMV_FAN4", - "CMT_TOP_FAN4_12" - ], - [ - "CMT_PMV_SW4A0", - "CMT_TOP_SW4A0_12" - ], - [ - "CMT_PMV_EE4B2", - "CMT_TOP_EE4B2_12" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_IOI3", - "HCLK_TERM" - ], - "wire_pairs": [ - [ - "HCLK_IOI_CK_BUFHCLK5", - "HCLK_TERM_CK_BUFHCLK5" - ], - [ - "HCLK_IOI_CK_BUFHCLK10", - "HCLK_TERM_CK_BUFHCLK10" - ], - [ - "HCLK_IOI_CK_BUFHCLK6", - "HCLK_TERM_CK_BUFHCLK6" - ], - [ - "HCLK_IOI_CK_BUFRCLK2", - "HCLK_TERM_CK_BUFRCLK2" - ], - [ - "HCLK_IOI_CK_BUFRCLK1", - "HCLK_TERM_CK_BUFRCLK1" - ], - [ - "HCLK_IOI_IOCLK_PLL0", - "HCLK_TERM_PERFCLK0" - ], - [ - "HCLK_IOI_CK_BUFHCLK11", - "HCLK_TERM_CK_BUFHCLK11" - ], - [ - "HCLK_IOI_CK_BUFRCLK3", - "HCLK_TERM_CK_BUFRCLK3" - ], - [ - "HCLK_IOI_I2IOCLK_TOP1", - "HCLK_TERM_CCIO1" - ], - [ - "HCLK_IOI_IOCLK_PLL3", - "HCLK_TERM_PERFCLK3" - ], - [ - "HCLK_IOI_I2IOCLK_BOT1", - "HCLK_TERM_CCIO3" - ], - [ - "HCLK_IOI_CK_BUFHCLK2", - "HCLK_TERM_CK_BUFHCLK2" - ], - [ - "HCLK_IOI_CK_BUFHCLK1", - "HCLK_TERM_CK_BUFHCLK1" - ], - [ - "HCLK_IOI_CK_BUFRCLK0", - "HCLK_TERM_CK_BUFRCLK0" - ], - [ - "HCLK_IOI_CK_BUFHCLK3", - "HCLK_TERM_CK_BUFHCLK3" - ], - [ - "HCLK_IOI_CK_BUFHCLK0", - "HCLK_TERM_CK_BUFHCLK0" - ], - [ - "HCLK_IOI_IOCLK_PLL2", - "HCLK_TERM_PERFCLK2" - ], - [ - "HCLK_IOI_IOCLK_PLL1", - "HCLK_TERM_PERFCLK1" - ], - [ - "HCLK_IOI_I2IOCLK_TOP0", - "HCLK_TERM_CCIO0" - ], - [ - "HCLK_IOI_CK_BUFHCLK7", - "HCLK_TERM_CK_BUFHCLK7" - ], - [ - "HCLK_IOI_CK_BUFHCLK8", - "HCLK_TERM_CK_BUFHCLK8" - ], - [ - "HCLK_IOI_I2IOCLK_BOT0", - "HCLK_TERM_CCIO2" - ], - [ - "HCLK_IOI_CK_BUFHCLK4", - "HCLK_TERM_CK_BUFHCLK4" - ], - [ - "HCLK_IOI_CK_BUFHCLK9", - "HCLK_TERM_CK_BUFHCLK9" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "BRAM_R", - "HCLK_BRAM" - ], - "wire_pairs": [ - [ - "BRAM_CASCOUT_ADDRARDADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" - ], - [ - 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], - [ - "BRAM_CASCINTOP_ADDRARDADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" - ], - [ - "BRAM_FIFO36_CASCADEOUTA_1", - "HCLK_BRAM_CASCADEA_R" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - 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"INT_INTERFACE_WW4B3" - ], - [ - "PCIE_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - "PCIE_IMUX34_L_3", - "PCIE_INT_INTERFACE_IMUX_L_OUT34" - ], - [ - "PCIE_LOGIC_OUTS_B2_L_3", - "INT_INTERFACE_LOGIC_OUTS_L_B2" - ], - [ - "PCIE_BYP4_L_3", - "INT_INTERFACE_BYP4" - ], - [ - "PCIE_IMUX19_L_3", - "PCIE_INT_INTERFACE_IMUX_L_OUT19" - ], - [ - "PCIE_LOGIC_OUTS_B4_L_3", - "INT_INTERFACE_LOGIC_OUTS_L_B4" - ], - [ - "PCIE_SW4END2_3", - "INT_INTERFACE_SW4END2" - ], - [ - "PCIE_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "PCIE_NW4A2_3", - "INT_INTERFACE_NW4A2" - ], - [ - "PCIE_IMUX27_L_3", - "PCIE_INT_INTERFACE_IMUX_L_OUT27" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_HROW_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_BUFG_IMUX33_2", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_NW2A3_2", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_2", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_BUFG_IMUX9_2", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_IMUX35_2", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_LH4_2", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_BYP6_2", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_SW4A2_2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE4B1_2", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_BUFG_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WW2END2_2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_2", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_BUFG_IMUX2_2", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_EE4A0_2", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_NE4BEG2_2", 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"CLK_HROW_NW4A0_2", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_BYP3_2", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_BUFG_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_BUFG_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_SE4BEG2_2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_NE4C3_2", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_BUFG_IMUX42_2", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_2", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_NW4END0_2", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_CLK0_2", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WR1END2_2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_BUFG_IMUX17_2", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_NE2A1_2", - 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"grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "CMT_TOP_L_LOWER_T", - "VBRK" - ], - "wire_pairs": [ - [ - "CMT_TOP_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_LH1_3", - "VBRK_LH1" - ], - [ - "CMT_TOP_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_LH11_3", - "VBRK_LH11" - ], - [ - "CMT_TOP_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_LH2_3", - "VBRK_LH2" - ], - [ - "CMT_TOP_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_MONITOR_P_3", - "VBRK_MONITOR_P" - ], - [ - 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[ - "CMT_TOP_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_LH5_3", - "VBRK_LH5" - ], - [ - "CMT_TOP_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_LH7_3", - "VBRK_LH7" - ], - [ - "CMT_TOP_LH9_3", - "VBRK_LH9" - ], - [ - "CMT_TOP_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_SE4C0_3", - "VBRK_SE4C0" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "HCLK_BRAM", - "HCLK_VBRK" - ], - "wire_pairs": [ - [ - "HCLK_BRAM_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_BRAM_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_BRAM_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_BRAM_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_BRAM_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_BRAM_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_BRAM_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_BRAM_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_BRAM_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_BRAM_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_BRAM_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_BRAM_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_BRAM_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_BRAM_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_BRAM_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - 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- [ - "BRAM_CASCINTOP_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLBLL_R", - "CLBLL_R" - ], - "wire_pairs": [ - [ - "CLBLL_L_CIN", - "CLBLL_L_COUT_N" - ], - [ - "CLBLL_LL_CIN", - "CLBLL_LL_COUT_N" - ] - ] - }, - { - "grid_deltas": [ - 1, - 8 - ], - "tile_types": [ - "CFG_CENTER_BOT", - "VFRAME" - ], - "wire_pairs": [ - [ - "CFG_CENTER_SE4BEG3_2", - "VFRAME_SE4BEG3" - ], - [ - "CFG_CENTER_NW4A3_2", - "VFRAME_NW4A3" - ], - [ - "CFG_CENTER_EE2BEG2_2", - "VFRAME_EE2BEG2" - ], - [ - "CFG_CENTER_BYP3_2", - "VFRAME_BYP3" - ], - [ - "CFG_CENTER_FAN0_2", - "VFRAME_FAN0" - ], - [ - "CFG_CENTER_IMUX15_2", - "VFRAME_IMUX15" - ], - [ - "CFG_CENTER_BYP2_2", - "VFRAME_BYP2" - ], - [ - "CFG_CENTER_NW4END0_2", - "VFRAME_NW4END0" - ], - [ - "CFG_CENTER_LH4_2", - "VFRAME_LH4" - ], - [ - "CFG_CENTER_SE4C0_2", - "VFRAME_SE4C0" - ], - [ - "CFG_CENTER_IMUX27_2", - "VFRAME_IMUX27" - ], - [ - "CFG_CENTER_FAN4_2", - "VFRAME_FAN4" - ], - [ - "CFG_CENTER_WW4A2_2", - "VFRAME_WW4A2" - ], - [ - "CFG_CENTER_FAN1_2", - "VFRAME_FAN1" - ], - [ - "CFG_CENTER_NE2A3_2", - "VFRAME_NE2A3" - ], - [ - "CFG_CENTER_NE4C2_2", - "VFRAME_NE4C2" - ], - [ - "CFG_CENTER_NW2A2_2", - "VFRAME_NW2A2" - ], - [ - "CFG_CENTER_IMUX3_2", - "VFRAME_IMUX3" - ], - [ - "CFG_CENTER_ER1BEG2_2", - "VFRAME_ER1BEG2" - ], - [ - "CFG_CENTER_LH10_2", - "VFRAME_LH10" - ], - [ - "CFG_CENTER_BYP6_2", - "VFRAME_BYP6" - ], - [ - "CFG_CENTER_EE4B3_2", - "VFRAME_EE4B3" - ], - [ - "CFG_CENTER_EE4C1_2", - "VFRAME_EE4C1" - ], - [ - "CFG_CENTER_IMUX22_2", - "VFRAME_IMUX22" - ], - [ - "CFG_CENTER_LH5_2", - "VFRAME_LH5" - ], - [ - "CFG_CENTER_WW4A1_2", - "VFRAME_WW4A1" - ], - [ - "CFG_CENTER_WL1END0_2", - "VFRAME_WL1END0" - ], - [ - "CFG_CENTER_CTRL1_2", - "VFRAME_CTRL1" - ], - [ - "CFG_CENTER_SW4END2_2", - "VFRAME_SW4END2" - ], - [ - "CFG_CENTER_IMUX25_2", - "VFRAME_IMUX25" - ], - [ - "CFG_CENTER_IMUX10_2", - "VFRAME_IMUX10" - ], - [ - "CFG_CENTER_IMUX46_2", - "VFRAME_IMUX46" - ], - [ - "CFG_CENTER_BYP7_2", - "VFRAME_BYP7" - ], - [ - "CFG_CENTER_IMUX34_2", - "VFRAME_IMUX34" - ], - [ - "CFG_CENTER_IMUX4_2", - "VFRAME_IMUX4" - ], - [ - "CFG_CENTER_SE4BEG2_2", - "VFRAME_SE4BEG2" - ], - [ - "CFG_CENTER_IMUX11_2", - "VFRAME_IMUX11" - ], - [ - "CFG_CENTER_WW4A3_2", - "VFRAME_WW4A3" - ], - [ - "CFG_CENTER_BYP0_2", - "VFRAME_BYP0" - ], - [ - "CFG_CENTER_ER1BEG0_2", - "VFRAME_ER1BEG0" - ], - [ - "CFG_CENTER_NW2A3_2", - "VFRAME_NW2A3" - ], - [ - "CFG_CENTER_FAN3_2", - "VFRAME_FAN3" - ], - [ - "CFG_CENTER_NW4END3_2", - "VFRAME_NW4END3" - ], - [ - "CFG_CENTER_LH6_2", - "VFRAME_LH6" - ], - [ - "CFG_CENTER_IMUX42_2", - "VFRAME_IMUX42" - ], - [ - "CFG_CENTER_NE2A2_2", - "VFRAME_NE2A2" - ], - [ - "CFG_CENTER_IMUX33_2", - "VFRAME_IMUX33" - ], - [ - "CFG_CENTER_EE4B0_2", - "VFRAME_EE4B0" - ], - [ - "CFG_CENTER_EE2A0_2", - "VFRAME_EE2A0" - ], - [ - "CFG_CENTER_EE4A3_2", - "VFRAME_EE4A3" - ], - [ - "CFG_CENTER_SE4C1_2", - "VFRAME_SE4C1" - ], - [ - "CFG_CENTER_IMUX18_2", - "VFRAME_IMUX18" - ], - [ - "CFG_CENTER_IMUX9_2", - "VFRAME_IMUX9" - ], - [ - "CFG_CENTER_SW4A1_2", - "VFRAME_SW4A1" - ], - [ - "CFG_CENTER_NW4END1_2", - "VFRAME_NW4END1" - ], - [ - "CFG_CENTER_IMUX30_2", - "VFRAME_IMUX30" - ], - [ - "CFG_CENTER_FAN7_2", - "VFRAME_FAN7" - ], - [ - "CFG_CENTER_IMUX17_2", - "VFRAME_IMUX17" - ], - [ - "CFG_CENTER_EE4A1_2", - "VFRAME_EE4A1" - ], - [ - "CFG_CENTER_SE4C3_2", - "VFRAME_SE4C3" - ], - [ - "CFG_CENTER_WW4END0_2", - "VFRAME_WW4END0" - ], - [ - "CFG_CENTER_WW4A0_2", - "VFRAME_WW4A0" - ], - [ - "CFG_CENTER_WW4END2_2", - "VFRAME_WW4END2" - ], - [ - "CFG_CENTER_WW4END3_2", - "VFRAME_WW4END3" - ], - [ - "CFG_CENTER_EE4C3_2", - "VFRAME_EE4C3" - ], - [ - "CFG_CENTER_WW2A2_2", - "VFRAME_WW2A2" - ], - [ - "CFG_CENTER_LH2_2", - "VFRAME_LH2" - ], - [ - "CFG_CENTER_EE2A3_2", - "VFRAME_EE2A3" - ], - [ - "CFG_CENTER_IMUX16_2", - "VFRAME_IMUX16" - ], - [ - "CFG_CENTER_WL1END3_2", - "VFRAME_WL1END3" - ], - [ - "CFG_CENTER_EE2BEG1_2", - "VFRAME_EE2BEG1" - ], - [ - "CFG_CENTER_IMUX31_2", - "VFRAME_IMUX31" - ], - [ - "CFG_CENTER_WW2END0_2", - "VFRAME_WW2END0" - ], - [ - "CFG_CENTER_EL1BEG3_2", - "VFRAME_EL1BEG3" - ], - [ - "CFG_CENTER_EE4BEG2_2", - "VFRAME_EE4BEG2" - ], - [ - "CFG_CENTER_SE2A0_2", - "VFRAME_SE2A0" - ], - [ - "CFG_CENTER_IMUX23_2", - "VFRAME_IMUX23" - ], - [ - "CFG_CENTER_NW4END2_2", - "VFRAME_NW4END2" - ], - [ - "CFG_CENTER_WL1END1_2", - "VFRAME_WL1END1" - ], - [ - "CFG_CENTER_SW4END0_2", - "VFRAME_SW4END0" - ], - [ - "CFG_CENTER_LH8_2", - "VFRAME_LH8" - ], - [ - "CFG_CENTER_NW4A2_2", - "VFRAME_NW4A2" - ], - [ - "CFG_CENTER_WW4B1_2", - "VFRAME_WW4B1" - ], - [ - "CFG_CENTER_WW2END1_2", - "VFRAME_WW2END1" - ], - [ - "CFG_CENTER_IMUX8_2", - "VFRAME_IMUX8" - ], - [ - "CFG_CENTER_IMUX40_2", - "VFRAME_IMUX40" - ], - [ - "CFG_CENTER_EE4C0_2", - "VFRAME_EE4C0" - ], - [ - "CFG_CENTER_IMUX26_2", - "VFRAME_IMUX26" - ], - [ - "CFG_CENTER_IMUX13_2", - "VFRAME_IMUX13" - ], - [ - "CFG_CENTER_SW4END1_2", - "VFRAME_SW4END1" - ], - [ - "CFG_CENTER_EE4BEG0_2", - "VFRAME_EE4BEG0" - ], - [ - "CFG_CENTER_WW2A1_2", - "VFRAME_WW2A1" - ], - [ - "CFG_CENTER_IMUX0_2", - "VFRAME_IMUX0" - ], - [ - "CFG_CENTER_SE2A2_2", - "VFRAME_SE2A2" - ], - [ - "CFG_CENTER_SE4C2_2", - "VFRAME_SE4C2" - ], - [ - "CFG_CENTER_IMUX41_2", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_NE2A1_2", - "VFRAME_NE2A1" - ], - [ - "CFG_CENTER_EE4BEG1_2", - "VFRAME_EE4BEG1" - ], - [ - "CFG_CENTER_BYP5_2", - "VFRAME_BYP5" - ], - [ - "CFG_CENTER_WW2A0_2", - "VFRAME_WW2A0" - ], - [ - "CFG_CENTER_IMUX6_2", - "VFRAME_IMUX6" - ], - [ - "CFG_CENTER_EE2BEG0_2", - "VFRAME_EE2BEG0" - ], - [ - "CFG_CENTER_EE4A2_2", - "VFRAME_EE4A2" - ], - [ - "CFG_CENTER_NE2A0_2", - "VFRAME_NE2A0" - ], - [ - "CFG_CENTER_NE4BEG2_2", - "VFRAME_NE4BEG2" - ], - [ - "CFG_CENTER_NE4C3_2", - "VFRAME_NE4C3" - ], - [ - "CFG_CENTER_WW4END1_2", - "VFRAME_WW4END1" - ], - [ - "CFG_CENTER_LH7_2", - "VFRAME_LH7" - ], - [ - "CFG_CENTER_IMUX44_2", - "VFRAME_IMUX44" - ], - [ - "CFG_CENTER_SW4A0_2", - "VFRAME_SW4A0" - ], - [ - "CFG_CENTER_LH9_2", - "VFRAME_LH9" - ], - [ - "CFG_CENTER_IMUX45_2", - "VFRAME_IMUX45" - ], - [ - "CFG_CENTER_BYP1_2", - "VFRAME_BYP1" - ], - [ - "CFG_CENTER_EE4BEG3_2", - "VFRAME_EE4BEG3" - ], - [ - "CFG_CENTER_NE4C0_2", - "VFRAME_NE4C0" - ], - [ - "CFG_CENTER_IMUX24_2", - "VFRAME_IMUX24" - ], - [ - "CFG_CENTER_SW4A2_2", - "VFRAME_SW4A2" - ], - [ - "CFG_CENTER_WW4B2_2", - "VFRAME_WW4B2" - ], - [ - "CFG_CENTER_WL1END2_2", - "VFRAME_WL1END2" - ], - [ - "CFG_CENTER_IMUX47_2", - "VFRAME_IMUX47" - ], - [ - "CFG_CENTER_WR1END2_2", - "VFRAME_WR1END2" - ], - [ - "CFG_CENTER_WW4C2_2", - "VFRAME_WW4C2" - ], - [ - "CFG_CENTER_NE4C1_2", - "VFRAME_NE4C1" - ], - [ - "CFG_CENTER_WW2END3_2", - "VFRAME_WW2END3" - ], - [ - "CFG_CENTER_IMUX28_2", - "VFRAME_IMUX28" - ], - [ - "CFG_CENTER_EE2BEG3_2", - "VFRAME_EE2BEG3" - ], - [ - "CFG_CENTER_IMUX1_2", - "VFRAME_IMUX1" - ], - [ - "CFG_CENTER_NW2A1_2", - "VFRAME_NW2A1" - ], - [ - "CFG_CENTER_IMUX21_2", - "VFRAME_IMUX21" - ], - [ - "CFG_CENTER_IMUX37_2", - "VFRAME_IMUX37" - ], - [ - "CFG_CENTER_FAN2_2", - "VFRAME_FAN2" - ], - [ - "CFG_CENTER_EE2A1_2", - "VFRAME_EE2A1" - ], - [ - "CFG_CENTER_IMUX14_2", - "VFRAME_IMUX14" - ], - [ - "CFG_CENTER_WW2A3_2", - "VFRAME_WW2A3" - ], - [ - "CFG_CENTER_SW4END3_2", - "VFRAME_SW4END3" - ], - [ - "CFG_CENTER_IMUX38_2", - "VFRAME_IMUX38" - ], - [ - "CFG_CENTER_EE4A0_2", - "VFRAME_EE4A0" - ], - [ - "CFG_CENTER_IMUX5_2", - "VFRAME_IMUX5" - ], - [ - "CFG_CENTER_IMUX43_2", - "VFRAME_IMUX43" - ], - [ - "CFG_CENTER_CLK0_2", - "VFRAME_CLK0" - ], - [ - "CFG_CENTER_WW4B0_2", - "VFRAME_WW4B0" - ], - [ - "CFG_CENTER_IMUX2_2", - "VFRAME_IMUX2" - ], - [ - "CFG_CENTER_SE4BEG1_2", - "VFRAME_SE4BEG1" - ], - [ - "CFG_CENTER_SE2A1_2", - "VFRAME_SE2A1" - ], - [ - "CFG_CENTER_IMUX12_2", - "VFRAME_IMUX12" - ], - [ - "CFG_CENTER_WW4B3_2", - "VFRAME_WW4B3" - ], - [ - "CFG_CENTER_EL1BEG0_2", - "VFRAME_EL1BEG0" - ], - [ - "CFG_CENTER_BYP4_2", - "VFRAME_BYP4" - ], - [ - "CFG_CENTER_EE4B2_2", - "VFRAME_EE4B2" - ], - [ - "CFG_CENTER_SE2A3_2", - "VFRAME_SE2A3" - ], - [ - "CFG_CENTER_SW2A1_2", - "VFRAME_SW2A1" - ], - [ - "CFG_CENTER_CLK1_2", - "VFRAME_CLK1" - ], - [ - "CFG_CENTER_EL1BEG1_2", - "VFRAME_EL1BEG1" - ], - [ - "CFG_CENTER_WR1END3_2", - "VFRAME_WR1END3" - ], - [ - "CFG_CENTER_WW2END2_2", - "VFRAME_WW2END2" - ], - [ - "CFG_CENTER_WR1END1_2", - "VFRAME_WR1END1" - ], - [ - "CFG_CENTER_IMUX39_2", - "VFRAME_IMUX39" - ], - [ - "CFG_CENTER_WW4C1_2", - "VFRAME_WW4C1" - ], - [ - "CFG_CENTER_EE4B1_2", - "VFRAME_EE4B1" - ], - [ - "CFG_CENTER_NE4BEG1_2", - "VFRAME_NE4BEG1" - ], - [ - "CFG_CENTER_IMUX19_2", - "VFRAME_IMUX19" - ], - [ - "CFG_CENTER_IMUX36_2", - "VFRAME_IMUX36" - ], - [ - "CFG_CENTER_LH11_2", - "VFRAME_LH11" - ], - [ - "CFG_CENTER_FAN6_2", - "VFRAME_FAN6" - ], - [ - "CFG_CENTER_WW4C3_2", - "VFRAME_WW4C3" - ], - [ - "CFG_CENTER_IMUX32_2", - "VFRAME_IMUX32" - ], - [ - "CFG_CENTER_NW4A1_2", - "VFRAME_NW4A1" - ], - [ - "CFG_CENTER_NW4A0_2", - "VFRAME_NW4A0" - ], - [ - "CFG_CENTER_CTRL0_2", - "VFRAME_CTRL0" - ], - [ - "CFG_CENTER_SE4BEG0_2", - "VFRAME_SE4BEG0" - ], - [ - "CFG_CENTER_SW2A2_2", - "VFRAME_SW2A2" - ], - [ - "CFG_CENTER_IMUX29_2", - "VFRAME_IMUX29" - ], - [ - "CFG_CENTER_EE2A2_2", - "VFRAME_EE2A2" - ], - [ - "CFG_CENTER_LH3_2", - "VFRAME_LH3" - ], - [ - "CFG_CENTER_IMUX7_2", - "VFRAME_IMUX7" - ], - [ - "CFG_CENTER_SW2A0_2", - "VFRAME_SW2A0" - ], - [ - "CFG_CENTER_NW2A0_2", - "VFRAME_NW2A0" - ], - [ - "CFG_CENTER_LH1_2", - "VFRAME_LH1" - ], - [ - "CFG_CENTER_NE4BEG3_2", - "VFRAME_NE4BEG3" - ], - [ - "CFG_CENTER_SW4A3_2", - "VFRAME_SW4A3" - ], - [ - "CFG_CENTER_WR1END0_2", - "VFRAME_WR1END0" - ], - [ - "CFG_CENTER_FAN5_2", - "VFRAME_FAN5" - ], - [ - "CFG_CENTER_IMUX35_2", - "VFRAME_IMUX35" - ], - [ - "CFG_CENTER_SW2A3_2", - "VFRAME_SW2A3" - ], - [ - "CFG_CENTER_EL1BEG2_2", - "VFRAME_EL1BEG2" ], [ - "CFG_CENTER_IMUX20_2", - "VFRAME_IMUX20" + "IOI_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3_1" ], [ - "CFG_CENTER_WW4C0_2", - "VFRAME_WW4C0" + "IOI_RCLK_DIV_CLR0_1", + "IOI_RCLK_DIV_CLR0" ], [ - "CFG_CENTER_EE4C2_2", - "VFRAME_EE4C2" + "IOI_RCLK_DIV_CLR1_1", + "IOI_RCLK_DIV_CLR1" ], [ - "CFG_CENTER_NE4BEG0_2", - "VFRAME_NE4BEG0" + "IOI_RCLK_FORIO0", + "IOI_RCLK_FORIO0" ], [ - "CFG_CENTER_LH12_2", - "VFRAME_LH12" + "IOI_RCLK_FORIO1", + "IOI_RCLK_FORIO1" ], [ - "CFG_CENTER_ER1BEG3_2", - "VFRAME_ER1BEG3" + "IOI_RCLK_FORIO2", + "IOI_RCLK_FORIO2" ], [ - "CFG_CENTER_ER1BEG1_2", - "VFRAME_ER1BEG1" - ] - ] - }, - { - "grid_deltas": [ - 0, - -2 - ], - "tile_types": [ - "LIOI3", - "LIOI3" - ], - "wire_pairs": [ - [ - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1" + "IOI_RCLK_FORIO3", + "IOI_RCLK_FORIO3" ], [ - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1" + "IOI_TBYTEIN", + "IOI_TBYTEIN_TERM" ] ] }, @@ -382817,3858 +474093,374 @@ -1 ], "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "CLK_PMV_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_PMV_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_PMV_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_PMV_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_PMV_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_PMV_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_PMV_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_PMV_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_PMV_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_PMV_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_PMV_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_PMV_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_PMV_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_PMV_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "CLK_PMV_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_PMV_NW4END3_1", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_PMV_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_PMV_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_PMV_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_PMV_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_PMV_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_PMV_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_PMV_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_PMV_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - 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"CLK_PMV_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_PMV_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_PMV_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_PMV_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_PMV_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_PMV_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_PMV_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_PMV_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_PMV_WW2A3_1", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_PMV_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_PMV_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_PMV_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_PMV_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_PMV_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_PMV_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_PMV_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_PMV_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_PMV_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_PMV_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_PMV_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_PMV_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_PMV_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_PMV_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_PMV_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_PMV_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_PMV_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_PMV_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_PMV_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_PMV_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_PMV_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_PMV_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_PMV_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_PMV_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_PMV_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_PMV_BYP4_1", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_PMV_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_PMV_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_PMV_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_PMV_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_PMV_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_PMV_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_PMV_SW2A0_1", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_PMV_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_PMV_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_PMV_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_PMV_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_PMV_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_IMUX28_1", - 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"INT_INTERFACE_IMUX10" - ], - [ - "CLK_PMV_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_PMV_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_PMV_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_PMV_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_PMV_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_PMV_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_PMV_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_PMV_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_PMV_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_PMV_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_PMV_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_PMV_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_PMV_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_PMV_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_PMV_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_PMV_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_PMV_IMUX3_1", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_PMV_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "CLK_PMV_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_PMV_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_PMV_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_PMV_ER1BEG1_1", - "INT_INTERFACE_ER1BEG1" - ], - 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"VFRAME_WW4C2" - ], - [ - "CFG_CENTER_SE4BEG3_6", - "VFRAME_SE4BEG3" - ], - [ - "CFG_CENTER_SE4C2_6", - "VFRAME_SE4C2" - ], - [ - "CFG_CENTER_IMUX22_6", - "VFRAME_IMUX22" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "DSP_L", - "HCLK_DSP_L" - ], - "wire_pairs": [ - [ - "DSP_PCOUT25", - "HCLK_DSP_PCIN25" - ], - [ - "DSP_MULTSIGNOUT", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_BCOUT17", - "HCLK_DSP_BCIN17" - ], - [ - "DSP_ACOUT20", - "HCLK_DSP_ACIN20" - ], - [ - "DSP_PCOUT18", - "HCLK_DSP_PCIN18" - ], - [ - "DSP_ACOUT2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_PCOUT19", - "HCLK_DSP_PCIN19" - ], - [ - "DSP_PCOUT7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_ACOUT4", - "HCLK_DSP_ACIN4" - ], - [ - "DSP_ACOUT15", - "HCLK_DSP_ACIN15" - ], - [ - "DSP_ACOUT24", - "HCLK_DSP_ACIN24" - ], - [ - "DSP_BCOUT10", - "HCLK_DSP_BCIN10" - ], - [ - "DSP_PCOUT40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_BCOUT11", - "HCLK_DSP_BCIN11" - ], - [ - "DSP_PCOUT36", - "HCLK_DSP_PCIN36" - ], - [ - "DSP_PCOUT27", - "HCLK_DSP_PCIN27" - ], - [ - "DSP_BCOUT0", - "HCLK_DSP_BCIN0" - ], - [ - "DSP_PCOUT4", - "HCLK_DSP_PCIN4" - ], - [ - "DSP_ACOUT27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_BCOUT8", - "HCLK_DSP_BCIN8" - ], - [ - "DSP_ACOUT8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_ACOUT19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_BCOUT5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_PCOUT5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_ACOUT5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_ACOUT17", - "HCLK_DSP_ACIN17" - ], - [ - "DSP_PCOUT30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_PCOUT31", - "HCLK_DSP_PCIN31" - ], - [ - "DSP_PCOUT14", - "HCLK_DSP_PCIN14" - ], - [ - "DSP_PCOUT46", - "HCLK_DSP_PCIN46" - ], - [ - "DSP_PCOUT24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_PCOUT15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_ACOUT3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_PCOUT43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_ACOUT10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_BCOUT2", - "HCLK_DSP_BCIN2" - ], - [ - "DSP_ACOUT28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_PCOUT3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_CARRYCASCOUT", - "HCLK_DSP_CARRYCASCIN" - ], - [ - "DSP_PCOUT45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_PCOUT17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_ACOUT23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_PCOUT2", - "HCLK_DSP_PCIN2" - ], - [ - "DSP_PCOUT26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_PCOUT33", - "HCLK_DSP_PCIN33" - ], - [ - "DSP_PCOUT8", - "HCLK_DSP_PCIN8" - ], - [ - "DSP_ACOUT1", - "HCLK_DSP_ACIN1" - ], - [ - "DSP_PCOUT28", - "HCLK_DSP_PCIN28" - ], - [ - "DSP_BCOUT16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_PCOUT16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_PCOUT34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_PCOUT35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_PCOUT41", - "HCLK_DSP_PCIN41" - ], - [ - "DSP_ACOUT0", - "HCLK_DSP_ACIN0" - ], - [ - "DSP_ACOUT6", - "HCLK_DSP_ACIN6" - ], - [ - "DSP_ACOUT13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_ACOUT16", - "HCLK_DSP_ACIN16" - ], - [ - "DSP_ACOUT21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_PCOUT12", - "HCLK_DSP_PCIN12" - ], - [ - "DSP_PCOUT47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_PCOUT1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_PCOUT37", - "HCLK_DSP_PCIN37" - ], - [ - "DSP_ACOUT26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_PCOUT39", - "HCLK_DSP_PCIN39" - ], - [ - "DSP_PCOUT6", - "HCLK_DSP_PCIN6" - ], - [ - "DSP_ACOUT9", - "HCLK_DSP_ACIN9" - ], - [ - "DSP_PCOUT20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_PCOUT32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_BCOUT15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_PCOUT44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_BCOUT7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_PCOUT0", - "HCLK_DSP_PCIN0" - ], - [ - "DSP_PCOUT13", - "HCLK_DSP_PCIN13" - ], - [ - "DSP_BCOUT13", - "HCLK_DSP_BCIN13" - ], - [ - "DSP_BCOUT12", - "HCLK_DSP_BCIN12" - ], - [ - "DSP_PCOUT22", - "HCLK_DSP_PCIN22" - ], - [ - "DSP_PCOUT10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_ACOUT25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_ACOUT12", - "HCLK_DSP_ACIN12" - ], - [ - "DSP_BCOUT9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_ACOUT14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_ACOUT22", - "HCLK_DSP_ACIN22" - ], - [ - "DSP_ACOUT11", - "HCLK_DSP_ACIN11" - ], - [ - "DSP_ACOUT7", - "HCLK_DSP_ACIN7" - ], - [ - "DSP_BCOUT3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_BCOUT14", - "HCLK_DSP_BCIN14" - ], - [ - "DSP_ACOUT18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_PCOUT29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_BCOUT1", - "HCLK_DSP_BCIN1" - ], - [ - "DSP_BCOUT4", - "HCLK_DSP_BCIN4" - ], - [ - "DSP_PCOUT9", - "HCLK_DSP_PCIN9" - ], - [ - "DSP_BCOUT6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_PCOUT23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_PCOUT11", - "HCLK_DSP_PCIN11" - ], - [ - "DSP_ACOUT29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_PCOUT42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_PCOUT21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_PCOUT38", - "HCLK_DSP_PCIN38" - ] - ] - }, - { - "grid_deltas": [ - 1, 0 ], "tile_types": [ - "INT_FEEDTHRU_2", - "INT_FEEDTHRU_2" + "RIOI_TBYTESRC", + "R_TERM_INT" ], "wire_pairs": [ [ - "INT_FEEDTHRU_2_WL1END2", - "INT_FEEDTHRU_2_WL1END2" + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" ], [ - "INT_FEEDTHRU_2_NW4A0", - "INT_FEEDTHRU_2_NW4A0" + "IOI_BLOCK_OUTS1_0", + "TERM_INT_BLOCK_OUTS_L_B1" ], [ - "INT_FEEDTHRU_2_WL1END0", - "INT_FEEDTHRU_2_WL1END0" + "IOI_BLOCK_OUTS2_0", + "TERM_INT_BLOCK_OUTS_L_B2" ], [ - "INT_FEEDTHRU_2_WW2A2", - "INT_FEEDTHRU_2_WW2A2" + "IOI_BYP0_0", + "TERM_INT_BYP0" ], [ - "INT_FEEDTHRU_2_WW4B3", - "INT_FEEDTHRU_2_WW4B3" + "IOI_BYP1_0", + "TERM_INT_BYP1" ], [ - "INT_FEEDTHRU_2_NE4C3", - "INT_FEEDTHRU_2_NE4C3" + "IOI_BYP2_0", + "TERM_INT_BYP2" ], [ - "INT_FEEDTHRU_2_EE2BEG0", - "INT_FEEDTHRU_2_EE2BEG0" + "IOI_BYP3_0", + "TERM_INT_BYP3" ], [ - "INT_FEEDTHRU_2_WW4B0", - "INT_FEEDTHRU_2_WW4B0" + "IOI_BYP4_0", + "TERM_INT_BYP4" ], [ - "INT_FEEDTHRU_2_SW4END1", - "INT_FEEDTHRU_2_SW4END1" + "IOI_BYP5_0", + "TERM_INT_BYP5" ], [ - "INT_FEEDTHRU_2_EE2A2", - "INT_FEEDTHRU_2_EE2A2" + "IOI_BYP6_0", + "TERM_INT_BYP6" ], [ - "INT_FEEDTHRU_2_WW2END2", - "INT_FEEDTHRU_2_WW2END2" + "IOI_BYP7_0", + "TERM_INT_BYP7" ], [ - "INT_FEEDTHRU_2_WW4C0", - "INT_FEEDTHRU_2_WW4C0" + "IOI_CLK0_0", + "TERM_INT_CLK0" ], [ - "INT_FEEDTHRU_2_LH1", - "INT_FEEDTHRU_2_LH1" + "IOI_CLK1_0", + "TERM_INT_CLK1" ], [ - "INT_FEEDTHRU_2_NW4A3", - "INT_FEEDTHRU_2_NW4A3" + "IOI_CTRL0_0", + "TERM_INT_CTRL0" ], [ - "INT_FEEDTHRU_2_SW4END3", - "INT_FEEDTHRU_2_SW4END3" + "IOI_CTRL1_0", + "TERM_INT_CTRL1" ], [ - "INT_FEEDTHRU_2_EE2A3", - "INT_FEEDTHRU_2_EE2A3" + "IOI_FAN0_0", + "TERM_INT_FAN0" ], [ - "INT_FEEDTHRU_2_WW4A1", - "INT_FEEDTHRU_2_WW4A1" + "IOI_FAN1_0", + "TERM_INT_FAN1" ], [ - "INT_FEEDTHRU_2_SE4C3", - "INT_FEEDTHRU_2_SE4C3" + "IOI_FAN2_0", + "TERM_INT_FAN2" ], [ - "INT_FEEDTHRU_2_EE4C0", - "INT_FEEDTHRU_2_EE4C0" + "IOI_FAN3_0", + "TERM_INT_FAN3" ], [ - "INT_FEEDTHRU_2_EE4B0", - "INT_FEEDTHRU_2_EE4B0" + "IOI_FAN4_0", + "TERM_INT_FAN4" ], [ - "INT_FEEDTHRU_2_EE2A1", - "INT_FEEDTHRU_2_EE2A1" + "IOI_FAN5_0", + "TERM_INT_FAN5" ], [ - "INT_FEEDTHRU_2_EE4A3", - "INT_FEEDTHRU_2_EE4A3" + "IOI_FAN6_0", + "TERM_INT_FAN6" ], [ - "INT_FEEDTHRU_2_EE2BEG1", - "INT_FEEDTHRU_2_EE2BEG1" + "IOI_FAN7_0", + "TERM_INT_FAN7" ], [ - "INT_FEEDTHRU_2_LH5", - "INT_FEEDTHRU_2_LH5" + "IOI_IMUX0_0", + "TERM_INT_IMUX0" ], [ - "INT_FEEDTHRU_2_WR1END1", - "INT_FEEDTHRU_2_WR1END1" + "IOI_IMUX1_0", + "TERM_INT_IMUX1" ], [ - "INT_FEEDTHRU_2_WR1END3", - "INT_FEEDTHRU_2_WR1END3" + "IOI_IMUX2_0", + "TERM_INT_IMUX2" ], [ - "INT_FEEDTHRU_2_WW4C2", - "INT_FEEDTHRU_2_WW4C2" + "IOI_IMUX3_0", + "TERM_INT_IMUX3" ], [ - "INT_FEEDTHRU_2_NE4C2", - "INT_FEEDTHRU_2_NE4C2" + "IOI_IMUX4_0", + "TERM_INT_IMUX4" ], [ - "INT_FEEDTHRU_2_WW2A3", - "INT_FEEDTHRU_2_WW2A3" + "IOI_IMUX5_0", + "TERM_INT_IMUX5" ], [ - "INT_FEEDTHRU_2_SE4BEG3", - "INT_FEEDTHRU_2_SE4BEG3" + "IOI_IMUX6_0", + "TERM_INT_IMUX6" ], [ - "INT_FEEDTHRU_2_EE4C2", - "INT_FEEDTHRU_2_EE4C2" + "IOI_IMUX7_0", + "TERM_INT_IMUX7" ], [ - "INT_FEEDTHRU_2_SE2A3", - "INT_FEEDTHRU_2_SE2A3" + "IOI_IMUX8_0", + "TERM_INT_IMUX8" ], [ - "INT_FEEDTHRU_2_SE4C2", - "INT_FEEDTHRU_2_SE4C2" + "IOI_IMUX9_0", + "TERM_INT_IMUX9" ], [ - "INT_FEEDTHRU_2_MONITOR_P", - "INT_FEEDTHRU_2_MONITOR_P" + "IOI_IMUX10_0", + "TERM_INT_IMUX10" ], [ - "INT_FEEDTHRU_2_WL1END1", - "INT_FEEDTHRU_2_WL1END1" + "IOI_IMUX11_0", + "TERM_INT_IMUX11" ], [ - "INT_FEEDTHRU_2_EE4BEG3", - "INT_FEEDTHRU_2_EE4BEG3" + "IOI_IMUX12_0", + "TERM_INT_IMUX12" ], [ - "INT_FEEDTHRU_2_LH7", - "INT_FEEDTHRU_2_LH7" + "IOI_IMUX13_0", + "TERM_INT_IMUX13" ], [ - "INT_FEEDTHRU_2_NE2A3", - "INT_FEEDTHRU_2_NE2A3" + "IOI_IMUX14_0", + "TERM_INT_IMUX14" ], [ - "INT_FEEDTHRU_2_WW2A0", - "INT_FEEDTHRU_2_WW2A0" + "IOI_IMUX15_0", + "TERM_INT_IMUX15" ], [ - "INT_FEEDTHRU_2_LH8", - "INT_FEEDTHRU_2_LH8" + "IOI_IMUX16_0", + "TERM_INT_IMUX16" ], [ - "INT_FEEDTHRU_2_EE4B2", - "INT_FEEDTHRU_2_EE4B2" + "IOI_IMUX17_0", + "TERM_INT_IMUX17" ], [ - "INT_FEEDTHRU_2_LH11", - "INT_FEEDTHRU_2_LH11" + "IOI_IMUX18_0", + "TERM_INT_IMUX18" ], [ - "INT_FEEDTHRU_2_NW2A0", - "INT_FEEDTHRU_2_NW2A0" + "IOI_IMUX19_0", + "TERM_INT_IMUX19" ], [ - "INT_FEEDTHRU_2_SW2A3", - "INT_FEEDTHRU_2_SW2A3" + "IOI_IMUX20_0", + "TERM_INT_IMUX20" ], [ - "INT_FEEDTHRU_2_LH4", - "INT_FEEDTHRU_2_LH4" + "IOI_IMUX21_0", + "TERM_INT_IMUX21" ], [ - "INT_FEEDTHRU_2_LH2", - "INT_FEEDTHRU_2_LH2" + "IOI_IMUX22_0", + "TERM_INT_IMUX22" ], [ - "INT_FEEDTHRU_2_NE4C0", - "INT_FEEDTHRU_2_NE4C0" + "IOI_IMUX23_0", + "TERM_INT_IMUX23" ], [ - "INT_FEEDTHRU_2_WW4A0", - "INT_FEEDTHRU_2_WW4A0" + "IOI_IMUX24_0", + "TERM_INT_IMUX24" ], [ - "INT_FEEDTHRU_2_NE4BEG3", - "INT_FEEDTHRU_2_NE4BEG3" + "IOI_IMUX25_0", + "TERM_INT_IMUX25" ], [ - "INT_FEEDTHRU_2_WW2END3", - "INT_FEEDTHRU_2_WW2END3" + "IOI_IMUX26_0", + "TERM_INT_IMUX26" ], [ - "INT_FEEDTHRU_2_SW4A0", - "INT_FEEDTHRU_2_SW4A0" + "IOI_IMUX27_0", + "TERM_INT_IMUX27" ], [ - "INT_FEEDTHRU_2_LH3", - "INT_FEEDTHRU_2_LH3" + "IOI_IMUX28_0", + "TERM_INT_IMUX28" ], [ - "INT_FEEDTHRU_2_EE4A2", - "INT_FEEDTHRU_2_EE4A2" + "IOI_IMUX29_0", + "TERM_INT_IMUX29" ], [ - "INT_FEEDTHRU_2_WW2END1", - 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"INT_FEEDTHRU_2_SE2A1" - ], - [ - "CFG_CENTER_SE4C1_14", - "INT_FEEDTHRU_2_SE4C1" - ], - [ - "CFG_CENTER_NW4END2_14", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_LH2_14", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_EE4C0_14", - "INT_FEEDTHRU_2_EE4C0" - ], - [ - "CFG_CENTER_NE4C1_14", - "INT_FEEDTHRU_2_NE4C1" + "RIOI_I2GCLK_TOP0", + "L_TERM_INT_DQS_IOTOPHASER" ] ] }, @@ -392777,18197 +476125,393 @@ -1 ], "tile_types": [ - "GTX_CHANNEL_1", - "VBRK_EXT" + "RIOI_TBYTETERM", + "R_TERM_INT" ], "wire_pairs": [ [ - "GTXE2_LOGIC_OUTS_B19_6", - "VBRK_EXT_LOGIC_OUTS_B19" + "IOI_BLOCK_OUTS0_1", + "TERM_INT_BLOCK_OUTS_L_B0" ], [ - "GTXE2_BYP1_6", - "VBRK_EXT_BYP1" + "IOI_BLOCK_OUTS1_1", + "TERM_INT_BLOCK_OUTS_L_B1" ], [ - "GTXE2_IMUX18_6", - "VBRK_EXT_IMUX18" + "IOI_BLOCK_OUTS2_1", + "TERM_INT_BLOCK_OUTS_L_B2" ], [ - "GTXE2_LOGIC_OUTS_B5_6", - "VBRK_EXT_LOGIC_OUTS_B5" + "IOI_BYP0_1", + "TERM_INT_BYP0" ], [ - "GTXE2_IMUX22_6", - "VBRK_EXT_IMUX22" + "IOI_BYP1_1", + "TERM_INT_BYP1" ], [ - "GTXE2_IMUX21_6", - "VBRK_EXT_IMUX21" + "IOI_BYP2_1", + "TERM_INT_BYP2" ], [ - "GTXE2_IMUX32_6", - "VBRK_EXT_IMUX32" + "IOI_BYP3_1", + "TERM_INT_BYP3" ], [ - "GTXE2_FAN5_6", - "VBRK_EXT_FAN5" + "IOI_BYP4_1", + "TERM_INT_BYP4" ], [ - "GTXE2_LOGIC_OUTS_B15_6", - "VBRK_EXT_LOGIC_OUTS_B15" + "IOI_BYP5_1", + "TERM_INT_BYP5" ], [ - "GTXE2_IMUX16_6", - "VBRK_EXT_IMUX16" + "IOI_BYP6_1", + "TERM_INT_BYP6" ], [ - "GTXE2_IMUX14_6", - "VBRK_EXT_IMUX14" + "IOI_BYP7_1", + "TERM_INT_BYP7" ], [ - "GTXE2_FAN7_6", - "VBRK_EXT_FAN7" + "IOI_CLK0_1", + "TERM_INT_CLK0" ], [ - "GTXE2_LOGIC_OUTS_B7_6", - "VBRK_EXT_LOGIC_OUTS_B7" + "IOI_CLK1_1", + "TERM_INT_CLK1" ], [ - "GTXE2_IMUX19_6", - "VBRK_EXT_IMUX19" + "IOI_CTRL0_1", + "TERM_INT_CTRL0" ], [ - "GTXE2_FAN0_6", - "VBRK_EXT_FAN0" + "IOI_CTRL1_1", + "TERM_INT_CTRL1" ], [ - "GTXE2_IMUX4_6", - "VBRK_EXT_IMUX4" + "IOI_FAN0_1", + "TERM_INT_FAN0" ], [ - "GTXE2_IMUX39_6", - "VBRK_EXT_IMUX39" + "IOI_FAN1_1", + "TERM_INT_FAN1" ], [ - "GTXE2_LOGIC_OUTS_B6_6", - "VBRK_EXT_LOGIC_OUTS_B6" + "IOI_FAN2_1", + "TERM_INT_FAN2" ], [ - "GTXE2_IMUX44_6", - "VBRK_EXT_IMUX44" + "IOI_FAN3_1", + "TERM_INT_FAN3" ], [ - "GTXE2_IMUX27_6", - "VBRK_EXT_IMUX27" + "IOI_FAN4_1", + "TERM_INT_FAN4" ], [ - "GTXE2_IMUX20_6", - "VBRK_EXT_IMUX20" + "IOI_FAN5_1", + "TERM_INT_FAN5" ], [ - "GTXE2_IMUX12_6", - "VBRK_EXT_IMUX12" + "IOI_FAN6_1", + "TERM_INT_FAN6" ], [ - "GTXE2_IMUX34_6", - "VBRK_EXT_IMUX34" + "IOI_FAN7_1", + "TERM_INT_FAN7" ], [ - "GTXE2_IMUX13_6", - "VBRK_EXT_IMUX13" + "IOI_IMUX0_1", + "TERM_INT_IMUX0" ], [ - "GTXE2_LOGIC_OUTS_B12_6", - "VBRK_EXT_LOGIC_OUTS_B12" + "IOI_IMUX1_1", + "TERM_INT_IMUX1" ], [ - "GTXE2_IMUX46_6", - "VBRK_EXT_IMUX46" + "IOI_IMUX2_1", + "TERM_INT_IMUX2" ], [ - "GTXE2_FAN6_6", - "VBRK_EXT_FAN6" + "IOI_IMUX3_1", + "TERM_INT_IMUX3" ], [ - "GTXE2_IMUX33_6", - "VBRK_EXT_IMUX33" + "IOI_IMUX4_1", + "TERM_INT_IMUX4" ], [ - "GTXE2_LOGIC_OUTS_B14_6", - "VBRK_EXT_LOGIC_OUTS_B14" + "IOI_IMUX5_1", + "TERM_INT_IMUX5" ], [ - "GTXE2_IMUX29_6", - "VBRK_EXT_IMUX29" + "IOI_IMUX6_1", + "TERM_INT_IMUX6" ], [ - "GTXE2_LOGIC_OUTS_B0_6", - "VBRK_EXT_LOGIC_OUTS_B0" + "IOI_IMUX7_1", + "TERM_INT_IMUX7" ], [ - "GTXE2_IMUX1_6", - "VBRK_EXT_IMUX1" + "IOI_IMUX8_1", + "TERM_INT_IMUX8" ], [ - "GTXE2_IMUX47_6", - "VBRK_EXT_IMUX47" + "IOI_IMUX9_1", + "TERM_INT_IMUX9" ], [ - "GTXE2_IMUX15_6", - "VBRK_EXT_IMUX15" + "IOI_IMUX10_1", + "TERM_INT_IMUX10" ], [ - "GTXE2_IMUX25_6", - "VBRK_EXT_IMUX25" + "IOI_IMUX11_1", + "TERM_INT_IMUX11" ], [ - "GTXE2_IMUX42_6", - "VBRK_EXT_IMUX42" + "IOI_IMUX12_1", + "TERM_INT_IMUX12" ], [ - "GTXE2_IMUX23_6", - "VBRK_EXT_IMUX23" + "IOI_IMUX13_1", + "TERM_INT_IMUX13" ], [ - "GTXE2_FAN3_6", - "VBRK_EXT_FAN3" + "IOI_IMUX14_1", + "TERM_INT_IMUX14" ], [ - "GTXE2_LOGIC_OUTS_B10_6", - "VBRK_EXT_LOGIC_OUTS_B10" + "IOI_IMUX15_1", + "TERM_INT_IMUX15" ], [ - "GTXE2_BYP3_6", - "VBRK_EXT_BYP3" + "IOI_IMUX16_1", + "TERM_INT_IMUX16" ], [ - "GTXE2_IMUX24_6", - "VBRK_EXT_IMUX24" + "IOI_IMUX17_1", + "TERM_INT_IMUX17" ], [ - "GTXE2_BYP4_6", - "VBRK_EXT_BYP4" + "IOI_IMUX18_1", + "TERM_INT_IMUX18" ], [ - "GTXE2_IMUX5_6", - "VBRK_EXT_IMUX5" + "IOI_IMUX19_1", + "TERM_INT_IMUX19" ], [ - "GTXE2_FAN1_6", - "VBRK_EXT_FAN1" + "IOI_IMUX20_1", + "TERM_INT_IMUX20" ], [ - "GTXE2_IMUX40_6", - "VBRK_EXT_IMUX40" + "IOI_IMUX21_1", + "TERM_INT_IMUX21" ], [ - "GTXE2_IMUX28_6", - "VBRK_EXT_IMUX28" + "IOI_IMUX22_1", + "TERM_INT_IMUX22" ], [ - "GTXE2_FAN4_6", - "VBRK_EXT_FAN4" + "IOI_IMUX23_1", + "TERM_INT_IMUX23" ], [ - "GTXE2_IMUX6_6", - "VBRK_EXT_IMUX6" + "IOI_IMUX24_1", + "TERM_INT_IMUX24" ], [ - "GTXE2_LOGIC_OUTS_B13_6", - "VBRK_EXT_LOGIC_OUTS_B13" + "IOI_IMUX25_1", + "TERM_INT_IMUX25" ], [ - "GTXE2_IMUX38_6", - "VBRK_EXT_IMUX38" + "IOI_IMUX26_1", + "TERM_INT_IMUX26" ], [ - "GTXE2_LOGIC_OUTS_B11_6", - "VBRK_EXT_LOGIC_OUTS_B11" + "IOI_IMUX27_1", + "TERM_INT_IMUX27" ], [ - "GTXE2_IMUX8_6", - "VBRK_EXT_IMUX8" + "IOI_IMUX28_1", + "TERM_INT_IMUX28" ], [ - "GTXE2_IMUX11_6", - "VBRK_EXT_IMUX11" + "IOI_IMUX29_1", + "TERM_INT_IMUX29" ], [ - "GTXE2_LOGIC_OUTS_B9_6", - "VBRK_EXT_LOGIC_OUTS_B9" + "IOI_IMUX30_1", + "TERM_INT_IMUX30" ], [ - "GTXE2_IMUX36_6", - "VBRK_EXT_IMUX36" + "IOI_IMUX31_1", + "TERM_INT_IMUX31" ], [ - "GTXE2_IMUX30_6", - "VBRK_EXT_IMUX30" + "IOI_IMUX32_1", + "TERM_INT_IMUX32" ], [ - "GTXE2_IMUX41_6", - "VBRK_EXT_IMUX41" + "IOI_IMUX33_1", + "TERM_INT_IMUX33" ], [ - "GTXE2_LOGIC_OUTS_B4_6", - "VBRK_EXT_LOGIC_OUTS_B4" + "IOI_IMUX34_1", + "TERM_INT_IMUX34" ], [ - "GTXE2_LOGIC_OUTS_B3_6", - "VBRK_EXT_LOGIC_OUTS_B3" + "IOI_IMUX35_1", + "TERM_INT_IMUX35" ], [ - "GTXE2_IMUX17_6", - "VBRK_EXT_IMUX17" + "IOI_IMUX36_1", + "TERM_INT_IMUX36" ], [ - "GTXE2_IMUX2_6", - "VBRK_EXT_IMUX2" + "IOI_IMUX37_1", + "TERM_INT_IMUX37" ], [ - "GTXE2_BYP2_6", - "VBRK_EXT_BYP2" + "IOI_IMUX38_1", + "TERM_INT_IMUX38" ], [ - "GTXE2_IMUX31_6", - "VBRK_EXT_IMUX31" + "IOI_IMUX39_1", + "TERM_INT_IMUX39" ], [ - "GTXE2_LOGIC_OUTS_B2_6", - "VBRK_EXT_LOGIC_OUTS_B2" + "IOI_IMUX40_1", + "TERM_INT_IMUX40" ], [ - "GTXE2_BYP6_6", - "VBRK_EXT_BYP6" + "IOI_IMUX41_1", + "TERM_INT_IMUX41" ], [ - "GTXE2_LOGIC_OUTS_B1_6", - "VBRK_EXT_LOGIC_OUTS_B1" + "IOI_IMUX42_1", + "TERM_INT_IMUX42" ], [ - "GTXE2_IMUX3_6", - "VBRK_EXT_IMUX3" + "IOI_IMUX43_1", + "TERM_INT_IMUX43" ], [ - "GTXE2_LOGIC_OUTS_B16_6", - "VBRK_EXT_LOGIC_OUTS_B16" + "IOI_IMUX44_1", + "TERM_INT_IMUX44" ], [ - "GTXE2_IMUX10_6", - "VBRK_EXT_IMUX10" + "IOI_IMUX45_1", + "TERM_INT_IMUX45" ], [ - "GTXE2_LOGIC_OUTS_B8_6", - "VBRK_EXT_LOGIC_OUTS_B8" + "IOI_IMUX46_1", + "TERM_INT_IMUX46" ], [ - "GTXE2_LOGIC_OUTS_B20_6", - "VBRK_EXT_LOGIC_OUTS_B20" + "IOI_IMUX47_1", + "TERM_INT_IMUX47" ], [ - "GTXE2_IMUX43_6", - "VBRK_EXT_IMUX43" + "IOI_LOGIC_OUTS0_1", + "TERM_INT_LOGIC_OUTS_L_B0" ], [ - "GTXE2_IMUX7_6", - "VBRK_EXT_IMUX7" + "IOI_LOGIC_OUTS1_1", + "TERM_INT_LOGIC_OUTS_L_B1" ], [ - "GTXE2_IMUX9_6", - "VBRK_EXT_IMUX9" + "IOI_LOGIC_OUTS2_1", + "TERM_INT_LOGIC_OUTS_L_B2" ], [ - "GTXE2_BYP7_6", - "VBRK_EXT_BYP7" + "IOI_LOGIC_OUTS3_1", + "TERM_INT_LOGIC_OUTS_L_B3" ], [ - "GTXE2_IMUX0_6", - "VBRK_EXT_IMUX0" + "IOI_LOGIC_OUTS4_1", + "TERM_INT_LOGIC_OUTS_L_B4" ], [ - "GTXE2_LOGIC_OUTS_B23_6", - "VBRK_EXT_LOGIC_OUTS_B23" + "IOI_LOGIC_OUTS5_1", + "TERM_INT_LOGIC_OUTS_L_B5" ], [ - "GTXE2_IMUX26_6", - "VBRK_EXT_IMUX26" + "IOI_LOGIC_OUTS6_1", + "TERM_INT_LOGIC_OUTS_L_B6" ], [ - "GTXE2_IMUX35_6", - "VBRK_EXT_IMUX35" + "IOI_LOGIC_OUTS7_1", + "TERM_INT_LOGIC_OUTS_L_B7" ], [ - "GTXE2_BYP0_6", - "VBRK_EXT_BYP0" + "IOI_LOGIC_OUTS8_1", + "TERM_INT_LOGIC_OUTS_L_B8" ], [ - "GTXE2_IMUX45_6", - "VBRK_EXT_IMUX45" + "IOI_LOGIC_OUTS9_1", + "TERM_INT_LOGIC_OUTS_L_B9" ], [ - "GTXE2_LOGIC_OUTS_B17_6", - "VBRK_EXT_LOGIC_OUTS_B17" + "IOI_LOGIC_OUTS10_1", + "TERM_INT_LOGIC_OUTS_L_B10" ], [ - "GTXE2_FAN2_6", - "VBRK_EXT_FAN2" + "IOI_LOGIC_OUTS11_1", + "TERM_INT_LOGIC_OUTS_L_B11" ], [ - "GTXE2_BYP5_6", - "VBRK_EXT_BYP5" + "IOI_LOGIC_OUTS12_1", + "TERM_INT_LOGIC_OUTS_L_B12" ], [ - "GTXE2_CTRL0_6", - "VBRK_EXT_CTRL0" + "IOI_LOGIC_OUTS14_1", + "TERM_INT_LOGIC_OUTS_L_B14" ], [ - "GTXE2_IMUX37_6", - "VBRK_EXT_IMUX37" + "IOI_LOGIC_OUTS15_1", + "TERM_INT_LOGIC_OUTS_L_B15" ], [ - "GTXE2_CLK0_6", - "VBRK_EXT_CLK0" + "IOI_LOGIC_OUTS17_1", + "TERM_INT_LOGIC_OUTS_L_B17" ], [ - "GTXE2_CTRL1_6", - "VBRK_EXT_CTRL1" + "IOI_LOGIC_OUTS18_1", + "TERM_INT_LOGIC_OUTS_L_B18" ], [ - "GTXE2_CLK1_6", - "VBRK_EXT_CLK1" + "IOI_LOGIC_OUTS19_1", + "TERM_INT_LOGIC_OUTS_L_B19" ], [ - "GTXE2_LOGIC_OUTS_B22_6", - "VBRK_EXT_LOGIC_OUTS_B22" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "DSP_L", - "VBRK" - ], - "wire_pairs": [ - [ - "DSP_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "DSP_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "DSP_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "DSP_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "DSP_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "DSP_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "DSP_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "DSP_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "DSP_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "DSP_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "DSP_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "DSP_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "DSP_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "DSP_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "DSP_LH6_4", - "VBRK_LH6" - ], - [ - "DSP_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "DSP_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "DSP_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "DSP_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "DSP_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "DSP_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "DSP_LH1_4", - "VBRK_LH1" - ], - [ - "DSP_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "DSP_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "DSP_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "DSP_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "DSP_LH2_4", - "VBRK_LH2" - ], - [ - "DSP_LH9_4", - "VBRK_LH9" - ], - [ - "DSP_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "DSP_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "DSP_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "DSP_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "DSP_LH5_4", - "VBRK_LH5" - ], - [ - "DSP_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "DSP_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "DSP_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "DSP_LH7_4", - "VBRK_LH7" - ], - [ - "DSP_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "DSP_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "DSP_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "DSP_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "DSP_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "DSP_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "DSP_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "DSP_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "DSP_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "DSP_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "DSP_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "DSP_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "DSP_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "DSP_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "DSP_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "DSP_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "DSP_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "DSP_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "DSP_LH12_4", - "VBRK_LH12" - ], - [ - "DSP_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "DSP_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "DSP_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "DSP_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "DSP_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "DSP_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "DSP_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "DSP_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "DSP_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "DSP_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "DSP_EE4C0_4", - "VBRK_EE4C0" - ], - [ - "DSP_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "DSP_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "DSP_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "DSP_LH4_4", - "VBRK_LH4" - ], - [ - "DSP_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "DSP_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "DSP_LH11_4", - "VBRK_LH11" - ], - [ - "DSP_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "DSP_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "DSP_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "DSP_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "DSP_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "DSP_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "DSP_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "DSP_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "DSP_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "DSP_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "DSP_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "DSP_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "DSP_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "DSP_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "DSP_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "DSP_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "DSP_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "DSP_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "DSP_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "DSP_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "DSP_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "DSP_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "DSP_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "DSP_LH3_4", - "VBRK_LH3" - ], - [ - "DSP_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "DSP_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "DSP_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "DSP_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "DSP_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "DSP_SE2A1_4", - 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"CMT_FIFO_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CMT_FIFO_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CMT_FIFO_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CMT_FIFO_L_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "CMT_FIFO_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CMT_FIFO_L_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CMT_FIFO_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CMT_FIFO_L_IMUX36_1", - "INT_INTERFACE_IMUX36" - ] - ] - }, - { - "grid_deltas": [ - 0, - -5 - ], - "tile_types": [ - "CLK_FEED", - "CLK_HROW_BOT_R" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN25" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN4" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN31" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN1" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN7" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_HROW_R_CK_GCLK9" - ], - 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], - [ - "HCLK_SW6E0", - "SW6E0" - ], - [ - "HCLK_ER1END3", - "ER1END3" - ], - [ - "HCLK_SW6D2", - "SW6D2" - ], - [ - "HCLK_LV6", - "LV_L6" - ], - [ - "HCLK_NW6A1", - "NW6A1" - ], - [ - "HCLK_SS6B0", - "SS6B0" - ], - [ - "HCLK_NN2A2", - "NN2A2" - ], - [ - "HCLK_NE6C0", - "NE6C0" - ], - [ - "HCLK_LEAF_CLK_B_BOTL2", - "GCLK_L_B8" - ], - [ - "HCLK_SS6A1", - "SS6A1" - ], - [ - "HCLK_NE2BEG0", - "NE2BEG0" - ], - [ - "HCLK_SE6E0", - "SE6E0" - ], - [ - "HCLK_NE6D0", - "NE6D0" - ], - [ - "HCLK_SW6C0", - "SW6C0" - ], - [ - "HCLK_NN6E2", - "NN6E2" - ], - [ - "HCLK_FAN_BOUNCE_S3_6", - "FAN_BOUNCE_S3_6" - ], - [ - "HCLK_NN6B3", - "NN6B3" - ], - [ - "HCLK_LV8", - "LV_L8" - ], - [ - "HCLK_SR1END2", - "SR1END2" - ], - [ - "HCLK_SS6END1", - "SS6END1" - ], - [ - "HCLK_NN6D2", - "NN6D2" - ], - [ - "HCLK_NW6C2", - "NW6C2" - ], - [ - "HCLK_SL1END3", - "SL1END3" - ], - [ - "HCLK_LV7", - "LV_L7" - ], - [ - "HCLK_NE6C1", - "NE6C1" - ], - [ - "HCLK_SL1END1", - "SL1END1" - ], - [ - "HCLK_NR1BEG0", - "NR1BEG0" - ], - [ - "HCLK_SW6C2", - "SW6C2" - ], - [ - "HCLK_LEAF_CLK_B_BOTL0", - "GCLK_L_B6" - ], - [ - "HCLK_WL1END3", - "WL1END3" - ], - [ - "HCLK_LV9", - "LV_L9" - ], - [ - "HCLK_NE2BEG1", - "NE2BEG1" - ], - [ - "HCLK_SW2END2", - "SW2A2" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END3" - ], - [ - "HCLK_NN6BEG2", - "NN6BEG2" - ], - [ - "HCLK_LVB3", - "LVB_L2" - ], - [ - "HCLK_SS6A3", - "SS6A3" - ], - [ - "HCLK_NW6A2", - "NW6A2" - ], - [ - "HCLK_NN6D3", - "NN6D3" - ], - [ - "HCLK_SS6E2", - "SS6E2" - ], - [ - "HCLK_LEAF_CLK_B_BOTL4", - "GCLK_L_B10" - ], - [ - "HCLK_NN6END_S1_0", - "NN6END_S1_0" - ], - [ - "HCLK_LV15", - "LV_L15" - ], - [ - "HCLK_LV10", - "LV_L10" - ], - [ - "HCLK_NW2A2", - "NW2BEG2" - ], - [ - "HCLK_SE6E1", - "SE6E1" - ], - [ - "HCLK_SL1END0", - "SL1END0" - ], - [ - "HCLK_SW6C3", - "SW6C3" - ], - [ - "HCLK_SR1END_N3_3", - "SR1END3" - ], - [ - "HCLK_NN6D1", - "NN6D1" - ], - [ - "HCLK_SS6E3", - "SS6E3" - ], - [ - "HCLK_SS6END0", - "SS6END0" - ], - [ - "HCLK_LVB2", - "LVB_L1" - ], - [ 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"VBRK_WR1END3" - ], - [ - "CMT_TOP_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_LH12_4", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_LH11_4", - "VBRK_LH11" - ], - [ - "CMT_TOP_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_LH3_4", - "VBRK_LH3" - ], - [ - "CMT_TOP_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_LH7_4", - "VBRK_LH7" - ], - [ - "CMT_TOP_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_LH10_4", - "VBRK_LH10" - ], - [ - "CMT_TOP_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_EE4C0_4", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_LH8_4", - "VBRK_LH8" - ], - [ - "CMT_TOP_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_EE4C3_4", - "VBRK_EE4C3" - ] - ] - }, - { - "grid_deltas": [ - 1, - -1 - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_BUFG_REBUF_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_BUFG_REBUF_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CLK_BUFG_REBUF_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_BUFG_REBUF_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_BUFG_REBUF_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_BUFG_REBUF_LH1_1", - "VBRK_LH1" - ], - [ - "CLK_BUFG_REBUF_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_BUFG_REBUF_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_BUFG_REBUF_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_BUFG_REBUF_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_BUFG_REBUF_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_BUFG_REBUF_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_BUFG_REBUF_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_BUFG_REBUF_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_BUFG_REBUF_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_BUFG_REBUF_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_BUFG_REBUF_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_BUFG_REBUF_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_BUFG_REBUF_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_BUFG_REBUF_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_BUFG_REBUF_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_BUFG_REBUF_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_BUFG_REBUF_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_BUFG_REBUF_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_BUFG_REBUF_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_BUFG_REBUF_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_BUFG_REBUF_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_BUFG_REBUF_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_BUFG_REBUF_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_BUFG_REBUF_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_BUFG_REBUF_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_BUFG_REBUF_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_BUFG_REBUF_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CLK_BUFG_REBUF_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_BUFG_REBUF_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_BUFG_REBUF_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_BUFG_REBUF_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_BUFG_REBUF_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_BUFG_REBUF_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_BUFG_REBUF_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_BUFG_REBUF_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_BUFG_REBUF_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_BUFG_REBUF_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_BUFG_REBUF_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_BUFG_REBUF_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CLK_BUFG_REBUF_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_BUFG_REBUF_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_BUFG_REBUF_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_BUFG_REBUF_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_BUFG_REBUF_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_BUFG_REBUF_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_BUFG_REBUF_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_BUFG_REBUF_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CLK_BUFG_REBUF_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_BUFG_REBUF_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_BUFG_REBUF_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_BUFG_REBUF_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_BUFG_REBUF_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CLK_BUFG_REBUF_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_BUFG_REBUF_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_BUFG_REBUF_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_BUFG_REBUF_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_BUFG_REBUF_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_BUFG_REBUF_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_BUFG_REBUF_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_BUFG_REBUF_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_BUFG_REBUF_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CLK_BUFG_REBUF_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_BUFG_REBUF_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_BUFG_REBUF_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_BUFG_REBUF_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_BUFG_REBUF_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_BUFG_REBUF_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_BUFG_REBUF_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_BUFG_REBUF_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_BUFG_REBUF_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_BUFG_REBUF_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_BUFG_REBUF_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_BUFG_REBUF_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_BUFG_REBUF_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CLK_BUFG_REBUF_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CLK_BUFG_REBUF_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_BUFG_REBUF_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_BUFG_REBUF_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_BUFG_REBUF_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_BUFG_REBUF_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_BUFG_REBUF_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_BUFG_REBUF_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_BUFG_REBUF_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_BUFG_REBUF_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_BUFG_REBUF_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_BUFG_REBUF_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_BUFG_REBUF_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_BUFG_REBUF_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_BUFG_REBUF_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - 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-1, - 0 - ], - "tile_types": [ - "HCLK_IOB", - "HCLK_IOI" - ], - "wire_pairs": [ - [ - "HCLK_IOB_CK_BUFHCLK6", - "HCLK_IOI_CK_BUFHCLK6" - ], - [ - "HCLK_IOB_CK_BUFRCLK3", - "HCLK_IOI_CK_BUFRCLK3" - ], - [ - "HCLK_IOB_PERFCLK2", - "HCLK_IOI_IOCLK_PLL2" - ], - [ - "HCLK_IOB_CK_BUFRCLK0", - "HCLK_IOI_CK_BUFRCLK0" - ], - [ - "HCLK_IOB_CK_BUFRCLK1", - "HCLK_IOI_CK_BUFRCLK1" - ], - [ - "HCLK_IOB_CK_BUFHCLK5", - "HCLK_IOI_CK_BUFHCLK5" - ], - [ - "HCLK_IOB_CK_BUFHCLK9", - "HCLK_IOI_CK_BUFHCLK9" - ], - [ - "HCLK_IOB_PERFCLK3", - "HCLK_IOI_IOCLK_PLL3" - ], - [ - "HCLK_IOB_CK_BUFHCLK3", - "HCLK_IOI_CK_BUFHCLK3" - ], - [ - "HCLK_IOB_CK_BUFHCLK4", - "HCLK_IOI_CK_BUFHCLK4" - ], - [ - "HCLK_IOB_CK_BUFHCLK1", - "HCLK_IOI_CK_BUFHCLK1" - ], - [ - "HCLK_IOB_CK_BUFHCLK8", - "HCLK_IOI_CK_BUFHCLK8" - ], - [ - "HCLK_IOB_CK_BUFHCLK11", - "HCLK_IOI_CK_BUFHCLK11" - ], - [ - "HCLK_IOB_PERFCLK0", - "HCLK_IOI_IOCLK_PLL0" - ], - [ - "HCLK_IOB_PERFCLK1", - "HCLK_IOI_IOCLK_PLL1" - ], - [ - "HCLK_IOB_CK_BUFHCLK0", - "HCLK_IOI_CK_BUFHCLK0" - ], - [ - "HCLK_IOB_CK_BUFRCLK2", - "HCLK_IOI_CK_BUFRCLK2" - ], - [ - "HCLK_IOB_CK_BUFHCLK7", - "HCLK_IOI_CK_BUFHCLK7" - ], - [ - "HCLK_IOB_CK_BUFHCLK2", - "HCLK_IOI_CK_BUFHCLK2" - ], - [ - "HCLK_IOB_CK_BUFHCLK10", - "HCLK_IOI_CK_BUFHCLK10" - ] - ] - }, - { - "grid_deltas": [ - 0, - 2 - ], - "tile_types": [ - "HCLK_IOI", - "RIOI" - ], - "wire_pairs": [ - [ - "HCLK_IOI_IOCLK1", - "IOI_IOCLK1" - ], - [ - "HCLK_IOI_IOCLK3", - "IOI_IOCLK3" - ], - [ - "HCLK_IOI_RCLK_IMUX2", - "IOI_IMUX_RC2" - ], - [ - "HCLK_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3" - ], - [ - "HCLK_IOI_IOCLK2", - "IOI_IOCLK2" - ], - [ - "HCLK_IOI_RCLK2IO2", - "IOI_RCLK_FORIO2" - ], - [ - "HCLK_IOI_LEAF_GCLK_BOT3", - "IOI_LEAF_GCLK3" - ], - [ - "HCLK_IOI_RCLK2IO1", - "IOI_RCLK_FORIO1" - ], - [ - "HCLK_IOI_DCI_TSTCLK", - "IOI_DCI_TSTCLK" - ], - [ - "HCLK_IOI_I2IOCLK_BOT0", - "RIOI_I2GCLK_BOT1" - ], - [ - "HCLK_IOI_IOCLK0", - "IOI_IOCLK0" - ], - [ - "HCLK_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR2" - ], - [ - "HCLK_IOI_LEAF_GCLK_BOT1", - "IOI_LEAF_GCLK1" - ], - [ - "HCLK_IOI_RCLK2IO3", - "IOI_RCLK_FORIO3" - ], - [ - "HCLK_IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_OUTN65" - ], - [ - "HCLK_IOI_LEAF_GCLK_BOT4", - "IOI_LEAF_GCLK4" - ], - [ - "HCLK_IOI_LEAF_GCLK_BOT0", - "IOI_LEAF_GCLK0" - ], - [ - "HCLK_RCLK_DIV_CLR3", - "IOI_RCLK_DIV_CLR3" - ], - [ - "HCLK_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2" - ], - [ - "HCLK_IOI_LEAF_GCLK_BOT5", - "IOI_LEAF_GCLK5" - ], - [ - "HCLK_IOI_RCLK_IMUX3", - "IOI_IMUX_RC3" - ], - [ - "HCLK_IOI_RCLK2IO0", - "IOI_RCLK_FORIO0" - ], - [ - "HCLK_IOI_I2IOCLK_BOT1", - "RIOI_I2GCLK_TOP0" - ], - [ - "HCLK_IOI_LEAF_GCLK_BOT2", - "IOI_LEAF_GCLK2" - ], - [ - "HCLK_IOI_INT_DCI_EN", - "IOI_INT_DCI_EN" - ], - [ - "HCLK_IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RDY" - ], - [ - "HCLK_IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN1" - ] - ] - }, - { - "grid_deltas": [ - -1, - 9 - ], - "tile_types": [ - "CFG_CENTER_BOT", - "INT_FEEDTHRU_2" - ], - "wire_pairs": [ - [ - "CFG_CENTER_SW2A3_1", - "INT_FEEDTHRU_2_SW2A3" - ], - [ - "CFG_CENTER_WW2END1_1", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_NE4C1_1", - "INT_FEEDTHRU_2_NE4C1" - ], - [ - "CFG_CENTER_EE4A3_1", - "INT_FEEDTHRU_2_EE4A3" - ], - [ - "CFG_CENTER_EE4C1_1", - "INT_FEEDTHRU_2_EE4C1" - ], - [ - "CFG_CENTER_SW4END3_1", - "INT_FEEDTHRU_2_SW4END3" - ], - [ - "CFG_CENTER_SE4BEG3_1", - "INT_FEEDTHRU_2_SE4BEG3" - ], - [ - "CFG_CENTER_WW4A1_1", - "INT_FEEDTHRU_2_WW4A1" - ], - [ - "CFG_CENTER_WW2END0_1", - "INT_FEEDTHRU_2_WW2END0" - ], - [ - "CFG_CENTER_EE2A1_1", - "INT_FEEDTHRU_2_EE2A1" - ], - [ - "CFG_CENTER_WW4B1_1", - "INT_FEEDTHRU_2_WW4B1" - ], - [ - "CFG_CENTER_EE2A0_1", - "INT_FEEDTHRU_2_EE2A0" - ], - [ - "CFG_CENTER_EE4C3_1", - "INT_FEEDTHRU_2_EE4C3" - ], - [ - "CFG_CENTER_SW4A0_1", - "INT_FEEDTHRU_2_SW4A0" - ], - [ - "CFG_CENTER_EE4BEG0_1", - "INT_FEEDTHRU_2_EE4BEG0" - ], - [ - "CFG_CENTER_EE2BEG1_1", - "INT_FEEDTHRU_2_EE2BEG1" - ], - [ - "CFG_CENTER_EE2BEG2_1", - "INT_FEEDTHRU_2_EE2BEG2" - ], - [ - "CFG_CENTER_LH9_1", - "INT_FEEDTHRU_2_LH9" - ], - [ - "CFG_CENTER_NW4A1_1", - "INT_FEEDTHRU_2_NW4A1" - ], - [ - "CFG_CENTER_NW4END2_1", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_SW4END2_1", - "INT_FEEDTHRU_2_SW4END2" - ], - [ - "CFG_CENTER_WW4B3_1", - "INT_FEEDTHRU_2_WW4B3" - ], - [ - "CFG_CENTER_WW4END3_1", - "INT_FEEDTHRU_2_WW4END3" - ], - [ - "CFG_CENTER_EE2A2_1", - "INT_FEEDTHRU_2_EE2A2" - ], - [ - "CFG_CENTER_EL1BEG0_1", - "INT_FEEDTHRU_2_EL1BEG0" - ], - [ - "CFG_CENTER_WR1END0_1", - "INT_FEEDTHRU_2_WR1END0" - ], - [ - "CFG_CENTER_SE4C3_1", - "INT_FEEDTHRU_2_SE4C3" - ], - [ - "CFG_CENTER_SW4END1_1", - "INT_FEEDTHRU_2_SW4END1" - ], - [ - "CFG_CENTER_EL1BEG2_1", - "INT_FEEDTHRU_2_EL1BEG2" - ], - [ - "CFG_CENTER_NE2A2_1", - "INT_FEEDTHRU_2_NE2A2" - ], - [ - "CFG_CENTER_WL1END0_1", - "INT_FEEDTHRU_2_WL1END0" - ], - [ - "CFG_CENTER_LH1_1", - "INT_FEEDTHRU_2_LH1" - ], - [ - "CFG_CENTER_LH5_1", - "INT_FEEDTHRU_2_LH5" - ], - [ - "CFG_CENTER_WW2A0_1", - "INT_FEEDTHRU_2_WW2A0" - ], - [ - "CFG_CENTER_WW4END1_1", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_NW2A0_1", - "INT_FEEDTHRU_2_NW2A0" - ], - [ - "CFG_CENTER_NW4END3_1", - "INT_FEEDTHRU_2_NW4END3" - ], - [ - "CFG_CENTER_WW4A0_1", - "INT_FEEDTHRU_2_WW4A0" - ], - [ - "CFG_CENTER_WW2A3_1", - "INT_FEEDTHRU_2_WW2A3" - ], - [ - "CFG_CENTER_SW4A2_1", - "INT_FEEDTHRU_2_SW4A2" - ], - [ - "CFG_CENTER_SW2A0_1", - "INT_FEEDTHRU_2_SW2A0" - ], - [ - "CFG_CENTER_SE4C1_1", - "INT_FEEDTHRU_2_SE4C1" - ], - [ - "CFG_CENTER_WL1END2_1", - "INT_FEEDTHRU_2_WL1END2" - ], - [ - "CFG_CENTER_NE4BEG3_1", - "INT_FEEDTHRU_2_NE4BEG3" - ], - [ - "CFG_CENTER_NE4C0_1", - "INT_FEEDTHRU_2_NE4C0" - ], - [ - "CFG_CENTER_SE4C2_1", - "INT_FEEDTHRU_2_SE4C2" - ], - [ - "CFG_CENTER_EE4BEG3_1", - "INT_FEEDTHRU_2_EE4BEG3" - ], - [ - "CFG_CENTER_WW4C3_1", - "INT_FEEDTHRU_2_WW4C3" - ], - [ - "CFG_CENTER_SE4BEG2_1", - "INT_FEEDTHRU_2_SE4BEG2" - ], - [ - "CFG_CENTER_WW2A1_1", - "INT_FEEDTHRU_2_WW2A1" - ], - [ - "CFG_CENTER_WW2END2_1", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_WW4END2_1", - "INT_FEEDTHRU_2_WW4END2" - ], - [ - "CFG_CENTER_NE4BEG0_1", - "INT_FEEDTHRU_2_NE4BEG0" - ], - [ - "CFG_CENTER_EE4B3_1", - "INT_FEEDTHRU_2_EE4B3" - ], - [ - "CFG_CENTER_EE2BEG3_1", - "INT_FEEDTHRU_2_EE2BEG3" - ], - [ - "CFG_CENTER_NE2A1_1", - "INT_FEEDTHRU_2_NE2A1" - ], - [ - "CFG_CENTER_EE4BEG2_1", - "INT_FEEDTHRU_2_EE4BEG2" - ], - [ - "CFG_CENTER_WW2A2_1", - "INT_FEEDTHRU_2_WW2A2" - ], - [ - "CFG_CENTER_NW4END1_1", - "INT_FEEDTHRU_2_NW4END1" - ], - [ - "CFG_CENTER_EE4A0_1", - "INT_FEEDTHRU_2_EE4A0" - ], - [ - "CFG_CENTER_NW4A3_1", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_LH7_1", - "INT_FEEDTHRU_2_LH7" - ], - [ - "CFG_CENTER_NE4C3_1", - "INT_FEEDTHRU_2_NE4C3" - ], - [ - "CFG_CENTER_WW4A2_1", - "INT_FEEDTHRU_2_WW4A2" - ], - [ - "CFG_CENTER_WR1END1_1", - "INT_FEEDTHRU_2_WR1END1" - ], - [ - "CFG_CENTER_SE2A1_1", - "INT_FEEDTHRU_2_SE2A1" - ], - [ - "CFG_CENTER_SE2A2_1", - "INT_FEEDTHRU_2_SE2A2" - ], - [ - "CFG_CENTER_ER1BEG2_1", - "INT_FEEDTHRU_2_ER1BEG2" - ], - [ - "CFG_CENTER_ER1BEG0_1", - "INT_FEEDTHRU_2_ER1BEG0" - ], - [ - "CFG_CENTER_NW2A2_1", - "INT_FEEDTHRU_2_NW2A2" - ], - [ - "CFG_CENTER_SW4A1_1", - "INT_FEEDTHRU_2_SW4A1" - ], - [ - "CFG_CENTER_WW2END3_1", - "INT_FEEDTHRU_2_WW2END3" - ], - [ - "CFG_CENTER_NW4END0_1", - "INT_FEEDTHRU_2_NW4END0" - ], - [ - "CFG_CENTER_EE4BEG1_1", - "INT_FEEDTHRU_2_EE4BEG1" - ], - [ - "CFG_CENTER_WW4A3_1", - "INT_FEEDTHRU_2_WW4A3" - ], - [ - "CFG_CENTER_SW2A1_1", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_WW4C0_1", - "INT_FEEDTHRU_2_WW4C0" - ], - [ - "CFG_CENTER_WR1END3_1", - "INT_FEEDTHRU_2_WR1END3" - ], - [ - "CFG_CENTER_WW4END0_1", - "INT_FEEDTHRU_2_WW4END0" - ], - [ - "CFG_CENTER_SW4A3_1", - "INT_FEEDTHRU_2_SW4A3" - ], - [ - "CFG_CENTER_NE4C2_1", - "INT_FEEDTHRU_2_NE4C2" - ], - [ - "CFG_CENTER_LH4_1", - "INT_FEEDTHRU_2_LH4" - ], - [ - "CFG_CENTER_EE4A1_1", - "INT_FEEDTHRU_2_EE4A1" - ], - [ - "CFG_CENTER_SE4BEG1_1", - "INT_FEEDTHRU_2_SE4BEG1" - ], - [ - "CFG_CENTER_EE2A3_1", - "INT_FEEDTHRU_2_EE2A3" - ], - [ - "CFG_CENTER_LH6_1", - "INT_FEEDTHRU_2_LH6" - ], - [ - "CFG_CENTER_WL1END1_1", - "INT_FEEDTHRU_2_WL1END1" - ], - [ - "CFG_CENTER_EL1BEG1_1", - "INT_FEEDTHRU_2_EL1BEG1" - ], - [ - "CFG_CENTER_LH2_1", - "INT_FEEDTHRU_2_LH2" - ], - [ - "CFG_CENTER_NE2A3_1", - "INT_FEEDTHRU_2_NE2A3" - ], - [ - "CFG_CENTER_LH3_1", - "INT_FEEDTHRU_2_LH3" - ], - [ - "CFG_CENTER_SE4BEG0_1", - "INT_FEEDTHRU_2_SE4BEG0" - ], - [ - "CFG_CENTER_EE2BEG0_1", - "INT_FEEDTHRU_2_EE2BEG0" - ], - [ - "CFG_CENTER_LH11_1", - "INT_FEEDTHRU_2_LH11" - ], - [ - "CFG_CENTER_EE4B1_1", - "INT_FEEDTHRU_2_EE4B1" - ], - [ - "CFG_CENTER_WW4B2_1", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_EE4B0_1", - "INT_FEEDTHRU_2_EE4B0" - ], - [ - "CFG_CENTER_NE2A0_1", - "INT_FEEDTHRU_2_NE2A0" - ], - [ - "CFG_CENTER_WL1END3_1", - "INT_FEEDTHRU_2_WL1END3" - ], - [ - "CFG_CENTER_NW4A0_1", - "INT_FEEDTHRU_2_NW4A0" - ], - [ - "CFG_CENTER_NW2A1_1", - "INT_FEEDTHRU_2_NW2A1" - ], - [ - "CFG_CENTER_WW4B0_1", - "INT_FEEDTHRU_2_WW4B0" - ], - [ - "CFG_CENTER_SW4END0_1", - "INT_FEEDTHRU_2_SW4END0" - ], - [ - "CFG_CENTER_EE4A2_1", - "INT_FEEDTHRU_2_EE4A2" - ], - [ - "CFG_CENTER_WR1END2_1", - "INT_FEEDTHRU_2_WR1END2" - ], - [ - "CFG_CENTER_NE4BEG1_1", - "INT_FEEDTHRU_2_NE4BEG1" - ], - [ - "CFG_CENTER_LH8_1", - "INT_FEEDTHRU_2_LH8" - ], - [ - "CFG_CENTER_SE2A3_1", - "INT_FEEDTHRU_2_SE2A3" - ], - [ - "CFG_CENTER_SE4C0_1", - "INT_FEEDTHRU_2_SE4C0" - ], - [ - "CFG_CENTER_EL1BEG3_1", - "INT_FEEDTHRU_2_EL1BEG3" - ], - [ - "CFG_CENTER_WW4C2_1", - "INT_FEEDTHRU_2_WW4C2" - ], - [ - "CFG_CENTER_NE4BEG2_1", - "INT_FEEDTHRU_2_NE4BEG2" - ], - [ - "CFG_CENTER_EE4C2_1", - "INT_FEEDTHRU_2_EE4C2" - ], - [ - "CFG_CENTER_ER1BEG3_1", - "INT_FEEDTHRU_2_ER1BEG3" - ], - [ - "CFG_CENTER_NW2A3_1", - "INT_FEEDTHRU_2_NW2A3" - ], - [ - "CFG_CENTER_NW4A2_1", - "INT_FEEDTHRU_2_NW4A2" - ], - [ - "CFG_CENTER_WW4C1_1", - "INT_FEEDTHRU_2_WW4C1" - ], - [ - "CFG_CENTER_SE2A0_1", - "INT_FEEDTHRU_2_SE2A0" + "IOI_LOGIC_OUTS20_1", + "TERM_INT_LOGIC_OUTS_L_B20" ], [ - "CFG_CENTER_EE4B2_1", - "INT_FEEDTHRU_2_EE4B2" + "IOI_LOGIC_OUTS21_1", + "TERM_INT_LOGIC_OUTS_L_B21" ], [ - "CFG_CENTER_LH10_1", - "INT_FEEDTHRU_2_LH10" + "IOI_LOGIC_OUTS23_1", + "TERM_INT_LOGIC_OUTS_L_B23" ], [ - "CFG_CENTER_SW2A2_1", - "INT_FEEDTHRU_2_SW2A2" + "IOI_PHASER_TO_IO_ICLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV" ], [ - "CFG_CENTER_ER1BEG1_1", - "INT_FEEDTHRU_2_ER1BEG1" + "IOI_PHASER_TO_IO_ICLK_0", + "L_TERM_INT_PHASER_TO_IO_ICLK" ], [ - "CFG_CENTER_EE4C0_1", - "INT_FEEDTHRU_2_EE4C0" + "IOI_PHASER_TO_IO_OCLKDIV_0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV" ], [ - "CFG_CENTER_LH12_1", - "INT_FEEDTHRU_2_LH12" + "IOI_PHASER_TO_IO_OCLK_0", + "L_TERM_INT_PHASER_TO_IO_OCLK" ] ] }, @@ -410982,45 +476526,89 @@ ], "wire_pairs": [ [ - "IOI_IMUX20_0", - "TERM_INT_IMUX20" + "IOI_BLOCK_OUTS0_0", + "TERM_INT_BLOCK_OUTS_L_B0" ], [ - "IOI_IMUX13_0", - "TERM_INT_IMUX13" - ], - [ - "IOI_LOGIC_OUTS9_0", - "TERM_INT_LOGIC_OUTS_L_B9" - ], - [ - "IOI_IMUX11_0", - "TERM_INT_IMUX11" - ], - [ - "IOI_CTRL1_0", - "TERM_INT_CTRL1" - ], - [ - "IOI_CLK0_0", - "TERM_INT_CLK0" - ], - [ - "IOI_BYP0_0", - "TERM_INT_BYP0" - ], - [ - "IOI_IMUX36_0", - "TERM_INT_IMUX36" + "IOI_BLOCK_OUTS1_0", + "TERM_INT_BLOCK_OUTS_L_B1" ], [ "IOI_BLOCK_OUTS2_0", "TERM_INT_BLOCK_OUTS_L_B2" ], + [ + "IOI_BYP0_0", + "TERM_INT_BYP0" + ], + [ + "IOI_BYP1_0", + "TERM_INT_BYP1" + ], + [ + "IOI_BYP2_0", + "TERM_INT_BYP2" + ], + [ + "IOI_BYP3_0", + "TERM_INT_BYP3" + ], + [ + "IOI_BYP4_0", + "TERM_INT_BYP4" + ], + [ + "IOI_BYP5_0", + "TERM_INT_BYP5" + ], + [ + "IOI_BYP6_0", + "TERM_INT_BYP6" + ], + [ + "IOI_BYP7_0", + "TERM_INT_BYP7" + ], + [ + "IOI_CLK0_0", + "TERM_INT_CLK0" + ], + [ + "IOI_CLK1_0", + "TERM_INT_CLK1" + ], [ "IOI_CTRL0_0", "TERM_INT_CTRL0" ], + [ + "IOI_CTRL1_0", + "TERM_INT_CTRL1" + ], + [ + "IOI_FAN0_0", + "TERM_INT_FAN0" + ], + [ + "IOI_FAN1_0", + "TERM_INT_FAN1" + ], + [ + "IOI_FAN2_0", + "TERM_INT_FAN2" + ], + [ + "IOI_FAN3_0", + "TERM_INT_FAN3" + ], + [ + "IOI_FAN4_0", + "TERM_INT_FAN4" + ], + [ + "IOI_FAN5_0", + "TERM_INT_FAN5" + ], [ "IOI_FAN6_0", "TERM_INT_FAN6" @@ -411030,66272 +476618,684 @@ "TERM_INT_FAN7" ], [ - "IOI_IMUX25_0", - "TERM_INT_IMUX25" - ], - [ - "IOI_IMUX19_0", - "TERM_INT_IMUX19" - ], - [ - "IOI_IMUX16_0", - "TERM_INT_IMUX16" - ], - [ - "IOI_FAN5_0", - "TERM_INT_FAN5" - ], - [ - "IOI_IMUX12_0", - "TERM_INT_IMUX12" - ], - [ - "IOI_BYP6_0", - "TERM_INT_BYP6" - ], - [ - "IOI_IMUX3_0", - "TERM_INT_IMUX3" - ], - [ - "IOI_IMUX31_0", - "TERM_INT_IMUX31" - ], - [ - "IOI_IMUX43_0", - "TERM_INT_IMUX43" + "IOI_IMUX0_0", + "TERM_INT_IMUX0" ], [ "IOI_IMUX1_0", "TERM_INT_IMUX1" ], [ - "IOI_LOGIC_OUTS21_0", - "TERM_INT_LOGIC_OUTS_L_B21" + "IOI_IMUX2_0", + "TERM_INT_IMUX2" ], [ - "IOI_IMUX37_0", - "TERM_INT_IMUX37" - ], - [ - "IOI_IMUX42_0", - "TERM_INT_IMUX42" - ], - [ - "IOI_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_IMUX22_0", - "TERM_INT_IMUX22" - ], - [ - "IOI_IMUX40_0", - "TERM_INT_IMUX40" - ], - [ - "IOI_IMUX34_0", - "TERM_INT_IMUX34" - ], - [ - "IOI_LOGIC_OUTS17_0", - "TERM_INT_LOGIC_OUTS_L_B17" - ], - [ - "IOI_IMUX14_0", - "TERM_INT_IMUX14" - ], - [ - "IOI_BYP4_0", - "TERM_INT_BYP4" - ], - [ - "IOI_IMUX39_0", - "TERM_INT_IMUX39" - ], - [ - "IOI_IMUX7_0", - "TERM_INT_IMUX7" - ], - [ - "IOI_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" - ], - [ - "IOI_IMUX23_0", - "TERM_INT_IMUX23" - ], - [ - "IOI_IMUX21_0", - "TERM_INT_IMUX21" - ], - [ - "IOI_IMUX9_0", - "TERM_INT_IMUX9" - ], - [ - "IOI_LOGIC_OUTS11_0", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "IOI_FAN2_0", - "TERM_INT_FAN2" - ], - [ - "IOI_LOGIC_OUTS0_0", - "TERM_INT_LOGIC_OUTS_L_B0" - ], - [ - "IOI_IMUX10_0", - "TERM_INT_IMUX10" - ], - [ - "IOI_IMUX15_0", - "TERM_INT_IMUX15" - ], - [ - "IOI_LOGIC_OUTS18_0", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "IOI_IMUX29_0", - "TERM_INT_IMUX29" - ], - [ - "IOI_CLK1_0", - "TERM_INT_CLK1" - ], - [ - "IOI_IMUX27_0", - "TERM_INT_IMUX27" - ], - [ - "IOI_MONITOR_N", - "TERM_INT_MONITOR_N" - ], - [ - "IOI_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLK" + "IOI_IMUX3_0", + "TERM_INT_IMUX3" ], [ "IOI_IMUX4_0", "TERM_INT_IMUX4" ], - [ - "IOI_LOGIC_OUTS23_0", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "IOI_LOGIC_OUTS19_0", - "TERM_INT_LOGIC_OUTS_L_B19" - ], - [ - "IOI_LOGIC_OUTS10_0", - "TERM_INT_LOGIC_OUTS_L_B10" - ], - [ - "IOI_FAN3_0", - "TERM_INT_FAN3" - ], - [ - "IOI_LOGIC_OUTS6_0", - "TERM_INT_LOGIC_OUTS_L_B6" - ], - [ - "IOI_BYP3_0", - "TERM_INT_BYP3" - ], - [ - "IOI_BLOCK_OUTS1_0", - "TERM_INT_BLOCK_OUTS_L_B1" - ], - [ - "IOI_FAN4_0", - "TERM_INT_FAN4" - ], - [ - "IOI_BYP7_0", - "TERM_INT_BYP7" - ], - [ - "IOI_IMUX18_0", - "TERM_INT_IMUX18" - ], - [ - "IOI_BYP1_0", - "TERM_INT_BYP1" - ], - [ - "IOI_IMUX24_0", - "TERM_INT_IMUX24" - ], - [ - "IOI_MONITOR_P", - "TERM_INT_MONITOR_P" - ], - [ - "IOI_PHASER_TO_IO_OCLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "IOI_LOGIC_OUTS12_0", - "TERM_INT_LOGIC_OUTS_L_B12" - ], - [ - "IOI_BLOCK_OUTS0_0", - "TERM_INT_BLOCK_OUTS_L_B0" - ], - [ - "IOI_LOGIC_OUTS4_0", - "TERM_INT_LOGIC_OUTS_L_B4" - ], - [ - "IOI_IMUX33_0", - "TERM_INT_IMUX33" - ], - [ - "IOI_IMUX30_0", - "TERM_INT_IMUX30" - ], - [ - "IOI_BYP5_0", - "TERM_INT_BYP5" - ], [ "IOI_IMUX5_0", "TERM_INT_IMUX5" ], - [ - "IOI_LOGIC_OUTS14_0", - "TERM_INT_LOGIC_OUTS_L_B14" - ], - [ - "IOI_FAN0_0", - "TERM_INT_FAN0" - ], - [ - "IOI_IMUX45_0", - "TERM_INT_IMUX45" - ], - [ - "IOI_LOGIC_OUTS1_0", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_LOGIC_OUTS3_0", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_IMUX32_0", - "TERM_INT_IMUX32" - ], - [ - "IOI_LOGIC_OUTS7_0", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_BYP2_0", - "TERM_INT_BYP2" - ], - [ - "IOI_IMUX46_0", - "TERM_INT_IMUX46" - ], - [ - "IOI_LOGIC_OUTS15_0", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_IMUX8_0", - "TERM_INT_IMUX8" - ], - [ - "IOI_LOGIC_OUTS5_0", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_IMUX2_0", - "TERM_INT_IMUX2" - ], - [ - "IOI_LOGIC_OUTS20_0", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_IMUX26_0", - "TERM_INT_IMUX26" - ], - [ - "IOI_IMUX28_0", - "TERM_INT_IMUX28" - ], - [ - "IOI_IMUX41_0", - "TERM_INT_IMUX41" - ], - [ - "IOI_IMUX47_0", - "TERM_INT_IMUX47" - ], - [ - "IOI_LOGIC_OUTS8_0", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_IMUX38_0", - "TERM_INT_IMUX38" - ], - [ - "IOI_IMUX0_0", - "TERM_INT_IMUX0" - ], [ "IOI_IMUX6_0", "TERM_INT_IMUX6" ], [ - "IOI_IMUX44_0", - "TERM_INT_IMUX44" + "IOI_IMUX7_0", + "TERM_INT_IMUX7" ], [ - "IOI_LOGIC_OUTS2_0", - "TERM_INT_LOGIC_OUTS_L_B2" + "IOI_IMUX8_0", + "TERM_INT_IMUX8" + ], + [ + "IOI_IMUX9_0", + "TERM_INT_IMUX9" + ], + [ + "IOI_IMUX10_0", + "TERM_INT_IMUX10" + ], + [ + "IOI_IMUX11_0", + "TERM_INT_IMUX11" + ], + [ + "IOI_IMUX12_0", + "TERM_INT_IMUX12" + ], + [ + "IOI_IMUX13_0", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX14_0", + "TERM_INT_IMUX14" + ], + [ + "IOI_IMUX15_0", + "TERM_INT_IMUX15" + ], + [ + "IOI_IMUX16_0", + "TERM_INT_IMUX16" + ], + [ + "IOI_IMUX17_0", + "TERM_INT_IMUX17" + ], + [ + "IOI_IMUX18_0", + "TERM_INT_IMUX18" + ], + [ + "IOI_IMUX19_0", + "TERM_INT_IMUX19" + ], + [ + "IOI_IMUX20_0", + "TERM_INT_IMUX20" + ], + [ + "IOI_IMUX21_0", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX22_0", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX23_0", + "TERM_INT_IMUX23" + ], + [ + "IOI_IMUX24_0", + "TERM_INT_IMUX24" + ], + [ + "IOI_IMUX25_0", + "TERM_INT_IMUX25" + ], + [ + "IOI_IMUX26_0", + "TERM_INT_IMUX26" + ], + [ + "IOI_IMUX27_0", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX28_0", + "TERM_INT_IMUX28" + ], + [ + "IOI_IMUX29_0", + "TERM_INT_IMUX29" + ], + [ + "IOI_IMUX30_0", + "TERM_INT_IMUX30" + ], + [ + "IOI_IMUX31_0", + "TERM_INT_IMUX31" + ], + [ + "IOI_IMUX32_0", + "TERM_INT_IMUX32" + ], + [ + "IOI_IMUX33_0", + "TERM_INT_IMUX33" + ], + [ + "IOI_IMUX34_0", + "TERM_INT_IMUX34" ], [ "IOI_IMUX35_0", "TERM_INT_IMUX35" ], [ - "IOI_FAN1_0", - "TERM_INT_FAN1" - ], - [ - "IOI_IMUX17_0", - "TERM_INT_IMUX17" - ] - ] - }, - { - "grid_deltas": [ - 1, - 6 - ], - "tile_types": [ - "INT_FEEDTHRU_2", - "MONITOR_BOT_FUJI2" - ], - "wire_pairs": [ - [ - "INT_FEEDTHRU_2_WW4B0", - "MONITOR_WW4B0_6" - ], - [ - "INT_FEEDTHRU_2_WL1END3", - "MONITOR_WL1END3_6" - ], - [ - "INT_FEEDTHRU_2_WR1END0", - "MONITOR_WR1END0_6" - ], - [ - "INT_FEEDTHRU_2_EL1BEG3", - "MONITOR_EL1BEG3_6" - ], - [ - "INT_FEEDTHRU_2_WW2END2", - "MONITOR_WW2END2_6" - ], - [ - "INT_FEEDTHRU_2_EE4A2", - "MONITOR_EE4A2_6" - ], - [ - "INT_FEEDTHRU_2_EL1BEG1", - "MONITOR_EL1BEG1_6" - ], - [ - "INT_FEEDTHRU_2_NE2A2", - "MONITOR_NE2A2_6" - ], - [ - "INT_FEEDTHRU_2_ER1BEG2", - "MONITOR_ER1BEG2_6" - ], - [ - "INT_FEEDTHRU_2_WW4END3", - "MONITOR_WW4END3_6" - ], - [ - "INT_FEEDTHRU_2_NW4END2", - "MONITOR_NW4END2_6" - ], - [ - "INT_FEEDTHRU_2_LH11", - "MONITOR_LH11_6" - ], - [ - "INT_FEEDTHRU_2_WW4A3", - "MONITOR_WW4A3_6" - ], - [ - "INT_FEEDTHRU_2_WW4C2", - "MONITOR_WW4C2_6" - ], - [ - "INT_FEEDTHRU_2_SW4A3", - "MONITOR_SW4A3_6" - ], - [ - "INT_FEEDTHRU_2_WW2A0", - "MONITOR_WW2A0_6" - ], - [ - "INT_FEEDTHRU_2_WW4C3", - "MONITOR_WW4C3_6" - ], - [ - "INT_FEEDTHRU_2_SE4BEG3", - "MONITOR_SE4BEG3_6" - ], - [ - "INT_FEEDTHRU_2_EE4BEG1", - "MONITOR_EE4BEG1_6" - ], - [ - "INT_FEEDTHRU_2_SW4END1", - "MONITOR_SW4END1_6" - ], - [ - "INT_FEEDTHRU_2_SE2A3", - "MONITOR_SE2A3_6" - ], - [ - "INT_FEEDTHRU_2_WW4B3", - "MONITOR_WW4B3_6" - ], - [ - "INT_FEEDTHRU_2_SE4BEG0", - "MONITOR_SE4BEG0_6" - ], - [ - "INT_FEEDTHRU_2_SE2A0", - "MONITOR_SE2A0_6" - ], - [ - "INT_FEEDTHRU_2_SW4END2", - "MONITOR_SW4END2_6" - ], - [ - "INT_FEEDTHRU_2_EL1BEG0", - "MONITOR_EL1BEG0_6" - ], - [ - "INT_FEEDTHRU_2_SW4A2", - "MONITOR_SW4A2_6" - ], - [ - "INT_FEEDTHRU_2_LH8", - "MONITOR_LH8_6" - ], - [ - "INT_FEEDTHRU_2_EE4B0", - "MONITOR_EE4B0_6" - ], - [ - "INT_FEEDTHRU_2_NE4C3", - "MONITOR_NE4C3_6" - ], - [ - "INT_FEEDTHRU_2_LH12", - "MONITOR_LH12_6" - ], - [ - "INT_FEEDTHRU_2_NE4BEG0", - "MONITOR_NE4BEG0_6" - ], - [ - "INT_FEEDTHRU_2_WW4A1", - "MONITOR_WW4A1_6" - ], - [ - "INT_FEEDTHRU_2_WR1END3", - "MONITOR_WR1END3_6" - ], - [ - "INT_FEEDTHRU_2_SW4A1", - "MONITOR_SW4A1_6" - ], - [ - "INT_FEEDTHRU_2_EE2BEG1", - "MONITOR_EE2BEG1_6" - ], - [ - "INT_FEEDTHRU_2_LH5", - "MONITOR_LH5_6" - ], - [ - "INT_FEEDTHRU_2_EE4BEG2", - "MONITOR_EE4BEG2_6" - ], - [ - "INT_FEEDTHRU_2_WW4A2", - "MONITOR_WW4A2_6" - ], - [ - "INT_FEEDTHRU_2_EE4B3", - "MONITOR_EE4B3_6" - ], - [ - "INT_FEEDTHRU_2_LH3", - "MONITOR_LH3_6" - ], - [ - "INT_FEEDTHRU_2_SW2A1", - "MONITOR_SW2A1_6" - ], - [ - "INT_FEEDTHRU_2_ER1BEG0", - "MONITOR_ER1BEG0_6" - ], - [ - "INT_FEEDTHRU_2_EE2A0", - "MONITOR_EE2A0_6" - ], - [ - "INT_FEEDTHRU_2_EE2BEG0", - "MONITOR_EE2BEG0_6" - ], - [ - "INT_FEEDTHRU_2_MONITOR_N", - "MONITOR_HORIZ_VAUXN11" - ], - [ - "INT_FEEDTHRU_2_WW4C1", - "MONITOR_WW4C1_6" - ], - [ - "INT_FEEDTHRU_2_SW4END0", - "MONITOR_SW4END0_6" - ], - [ - "INT_FEEDTHRU_2_WW4END0", - "MONITOR_WW4END0_6" - ], - [ - "INT_FEEDTHRU_2_NE2A3", - "MONITOR_NE2A3_6" - ], - [ - "INT_FEEDTHRU_2_WR1END1", - "MONITOR_WR1END1_6" - ], - [ - "INT_FEEDTHRU_2_NE2A0", - "MONITOR_NE2A0_6" - ], - [ - "INT_FEEDTHRU_2_SE4C3", - "MONITOR_SE4C3_6" - ], - [ - "INT_FEEDTHRU_2_LH1", - "MONITOR_LH1_6" - ], - [ - "INT_FEEDTHRU_2_NE2A1", - "MONITOR_NE2A1_6" - ], - [ - "INT_FEEDTHRU_2_LH7", - "MONITOR_LH7_6" - ], - [ - "INT_FEEDTHRU_2_WW4C0", - "MONITOR_WW4C0_6" - ], - [ - "INT_FEEDTHRU_2_NW4END0", - "MONITOR_NW4END0_6" - ], - [ - "INT_FEEDTHRU_2_NW4A2", - "MONITOR_NW4A2_6" - ], - [ - "INT_FEEDTHRU_2_SW2A3", - "MONITOR_SW2A3_6" - ], - [ - "INT_FEEDTHRU_2_EE4C1", - "MONITOR_EE4C1_6" - ], - [ - "INT_FEEDTHRU_2_NW4END3", - "MONITOR_NW4END3_6" - ], - [ - "INT_FEEDTHRU_2_ER1BEG3", - "MONITOR_ER1BEG3_6" - ], - [ - "INT_FEEDTHRU_2_NE4BEG3", - "MONITOR_NE4BEG3_6" - ], - [ - "INT_FEEDTHRU_2_MONITOR_P", - "MONITOR_HORIZ_VAUXP11" - ], - [ - "INT_FEEDTHRU_2_EE4BEG3", - "MONITOR_EE4BEG3_6" - ], - [ - "INT_FEEDTHRU_2_EE2A2", - "MONITOR_EE2A2_6" - ], - [ - "INT_FEEDTHRU_2_EE2BEG2", - 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- [ - "CLK_HROW_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_LH7_4", - "VBRK_LH7" - ], - [ - "CLK_HROW_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_LH10_4", - "VBRK_LH10" - ], - [ - "CLK_HROW_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_LH9_4", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH3_4", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_LH4_4", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_LH8_4", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_LH2_4", - "VBRK_LH2" - ], - [ - "CLK_HROW_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH5_4", - "VBRK_LH5" - ], - [ - "CLK_HROW_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_LH1_4", - "VBRK_LH1" - ], - [ - "CLK_HROW_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_LH11_4", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE2BEG0_4", - "VBRK_EE2BEG0" - ] - ] - }, - { - "grid_deltas": [ - 1, - -3 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_LH7_6", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE4BEG2_6", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_SE2A2_6", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_WW2END1_6", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EL1BEG3_6", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE4C3_6", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_SW2A3_6", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_SE4BEG3_6", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_NE2A0_6", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_ER1BEG0_6", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WL1END0_6", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4A3_6", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_NE4C3_6", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_SW2A2_6", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_NE4BEG3_6", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE4A1_6", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_WW4A2_6", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE2BEG0_6", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_ER1BEG3_6", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE2BEG2_6", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_NE2A2_6", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_LH8_6", - "VBRK_LH8" - ], - [ - "CLK_HROW_LH12_6", - "VBRK_LH12" - ], - [ - "CLK_HROW_EL1BEG0_6", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE2A2_6", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW2A0_6", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE2BEG3_6", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW4C3_6", - "VBRK_WW4C3" - ], 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"CLK_HROW_WR1END1_6", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW4END1_6", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW4END0_6", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_SW4END3_6", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_EE4A2_6", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_NE4BEG1_6", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_NW4END0_6", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_LH1_6", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW4END2_6", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WL1END3_6", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_ER1BEG1_6", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SE4C3_6", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WW4END3_6", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE2A1_6", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_SW2A1_6", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_EE4BEG3_6", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW4A1_6", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_EE4B0_6", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_LH9_6", - "VBRK_LH9" - ], - [ - "CLK_HROW_EE4BEG0_6", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4BEG1_6", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_WR1END2_6", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_NE4C1_6", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_SW4A1_6", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_MONITOR_N_6", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_LH4_6", - "VBRK_LH4" - ], - [ - "CLK_HROW_WW2A2_6", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WW4END0_6", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NW2A0_6", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_NE4C2_6", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW2END3_6", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_WW4C1_6", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SW4A2_6", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_EE4B1_6", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_NW2A2_6", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WW2A1_6", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_SE2A3_6", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_EE2A3_6", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_WW4C0_6", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_LH11_6", - "VBRK_LH11" - ], - [ - "CLK_HROW_SE2A0_6", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_LH3_6", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE2BEG1_6", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_LH6_6", - "VBRK_LH6" - ], - [ - "CLK_HROW_NW4END2_6", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_NW4END1_6", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_WR1END3_6", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_LH10_6", - "VBRK_LH10" - ], - [ - "CLK_HROW_WW4A0_6", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_NW4A1_6", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW4END2_6", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NE4BEG0_6", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_EE4C0_6", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_SE4BEG2_6", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE4BEG2_6", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_SE4BEG0_6", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_WL1END1_6", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_SW4END1_6", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NW4A2_6", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_ER1BEG2_6", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_SE2A1_6", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_WW2A3_6", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SE4BEG1_6", - "VBRK_SE4BEG1" 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"HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_TERM_CK_BUFHCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_TERM_CK_BUFRCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_TERM_CK_BUFHCLK5" - ], - [ - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_TERM_CCIO3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_TERM_CK_BUFHCLK6" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_TERM_CK_BUFHCLK4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_TERM_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_TERM_CCIO1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_TERM_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_TERM_CK_BUFHCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_TERM_CK_BUFHCLK10" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_TERM_CK_BUFHCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_TERM_CK_BUFHCLK9" - ], - [ - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_TERM_CCIO2" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_TERM_PERFCLK3" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_TERM_PERFCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_TERM_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_TERM_CK_BUFRCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_TERM_CK_BUFHCLK1" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_TERM_PERFCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_TERM_CK_BUFHCLK11" - ] - ] - }, - { - "grid_deltas": [ - 1, - 0 - ], - "tile_types": [ - "LIOB33", - "LIOI3_TBYTESRC" - ], - "wire_pairs": [ - [ - "IOB_IBUF_DISABLE1", - "LIOI_IBUF_DISABLE1" - ], - [ - "IOB_PU_INT_EN_0", - "LIOI_PU_INT_EN_0" - ], - [ - "IOB_DIFF_TERM_INT_EN", - "LIOI_DIFF_TERM_INT_EN" - ], - [ - "IOB_PD_INT_EN_1", - "LIOI_PD_INT_EN_1" - ], - [ - "IOB_T1", - "LIOI_T1" - ], - [ - "IOB_T0", - "LIOI_T0" - ], - [ - "IOB_IBUF0", - "LIOI_IBUF0" - ], - [ - "IOB_IBUF1", - "LIOI_IBUF1" - ], - [ - "IOB_IBUF_DISABLE0", - "LIOI_IBUF_DISABLE0" - ], - [ - "IOB_O0", - "LIOI_O0" - ], - [ - "LIOB_IN_TERM1", - "LIOI_DCI_T_TERM1" - ], - [ - "IOB_PD_INT_EN_0", - "LIOI_PD_INT_EN_0" - ], - [ - "LIOB_MONITOR_N", - "IOI_MONITOR_N" - ], - [ - "IOB_O1", - "LIOI_O1" - ], - [ - "IOB_KEEPER_INT_EN_1", - "LIOI_KEEPER_INT_EN_1" - ], - [ - "IOB_PU_INT_EN_1", - "LIOI_PU_INT_EN_1" - ], - [ - "IOB_KEEPER_INT_EN_0", - "LIOI_KEEPER_INT_EN_0" - ], - [ - "LIOB_IN_TERM0", - "LIOI_DCI_T_TERM0" - ], - [ - "LIOB_MONITOR_P", - "IOI_MONITOR_P" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMVIOB" - ], - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ] - ] - }, - { - "grid_deltas": [ - 0, - 5 - ], - "tile_types": [ - "BRKH_DSP_L", - "DSP_L" - ], - "wire_pairs": [ - [ - "BRKH_DSP_PCIN19", - "DSP_PCOUT19" - ], - [ - "BRKH_DSP_PCIN23", - "DSP_PCOUT23" - ], - [ - "BRKH_DSP_PCIN21", - "DSP_PCOUT21" - ], - [ - "BRKH_DSP_BCIN12", - "DSP_BCOUT12" - ], - [ - "BRKH_DSP_ACIN17", - "DSP_ACOUT17" - ], - [ - "BRKH_DSP_ACIN26", - "DSP_ACOUT26" - ], - [ - "BRKH_DSP_ACIN6", - "DSP_ACOUT6" - ], - [ - "BRKH_DSP_ACIN19", - "DSP_ACOUT19" - ], - [ - "BRKH_DSP_PCIN44", - "DSP_PCOUT44" - ], - [ - "BRKH_DSP_PCIN10", - "DSP_PCOUT10" - ], - [ - "BRKH_DSP_PCIN18", - "DSP_PCOUT18" - ], - [ - "BRKH_DSP_PCIN3", - "DSP_PCOUT3" - ], - [ - "BRKH_DSP_PCIN33", - "DSP_PCOUT33" - ], - [ - "BRKH_DSP_PCIN22", - "DSP_PCOUT22" - ], - [ - "BRKH_DSP_PCIN1", - "DSP_PCOUT1" - ], - [ - "BRKH_DSP_PCIN28", - "DSP_PCOUT28" - ], - [ - "BRKH_DSP_PCIN2", - "DSP_PCOUT2" - ], - [ - "BRKH_DSP_PCIN46", - "DSP_PCOUT46" - ], - [ - "BRKH_DSP_PCIN13", - "DSP_PCOUT13" - ], - [ - "BRKH_DSP_PCIN38", - "DSP_PCOUT38" - ], - [ - "BRKH_DSP_ACIN8", - "DSP_ACOUT8" - ], - [ - "BRKH_DSP_PCIN0", - "DSP_PCOUT0" - ], - [ - "BRKH_DSP_PCIN29", - "DSP_PCOUT29" - ], - [ - "BRKH_DSP_PCIN9", - "DSP_PCOUT9" - ], - [ - "BRKH_DSP_BCIN4", - "DSP_BCOUT4" - ], - [ - "BRKH_DSP_ACIN7", - "DSP_ACOUT7" - ], - [ - "BRKH_DSP_ACIN28", - "DSP_ACOUT28" - ], - [ - "BRKH_DSP_PCIN31", - "DSP_PCOUT31" - ], - [ - "BRKH_DSP_ACIN14", - "DSP_ACOUT14" - ], - [ - "BRKH_DSP_PCIN47", - "DSP_PCOUT47" - ], - [ - "BRKH_DSP_BCIN3", - "DSP_BCOUT3" - ], - [ - "BRKH_DSP_BCIN0", - "DSP_BCOUT0" - ], - [ - "BRKH_DSP_PCIN7", - "DSP_PCOUT7" - ], - [ - "BRKH_DSP_BCIN14", - "DSP_BCOUT14" - ], - [ - "BRKH_DSP_BCIN1", - "DSP_BCOUT1" - ], - [ - "BRKH_DSP_PCIN4", - "DSP_PCOUT4" - ], - [ - "BRKH_DSP_ACIN2", - "DSP_ACOUT2" - ], - [ - "BRKH_DSP_ACIN15", - "DSP_ACOUT15" - ], - [ - "BRKH_DSP_BCIN16", - "DSP_BCOUT16" - ], - [ - "BRKH_DSP_BCIN10", - "DSP_BCOUT10" - ], - [ - "BRKH_DSP_ACIN27", - "DSP_ACOUT27" - ], - [ - "BRKH_DSP_BCIN2", - "DSP_BCOUT2" - ], - [ - "BRKH_DSP_ACIN16", - "DSP_ACOUT16" - ], - [ - "BRKH_DSP_PCIN30", - "DSP_PCOUT30" - ], - [ - "BRKH_DSP_ACIN1", - "DSP_ACOUT1" - ], - [ - "BRKH_DSP_PCIN11", - "DSP_PCOUT11" - ], - [ - "BRKH_DSP_BCIN17", - "DSP_BCOUT17" - ], - [ - "BRKH_DSP_ACIN0", - "DSP_ACOUT0" - ], - [ - "BRKH_DSP_BCIN15", - "DSP_BCOUT15" - ], - [ - "BRKH_DSP_ACIN22", - "DSP_ACOUT22" - ], - [ - "BRKH_DSP_BCIN6", - "DSP_BCOUT6" - ], - [ - "BRKH_DSP_BCIN5", - "DSP_BCOUT5" - ], - [ - "BRKH_DSP_PCIN20", - "DSP_PCOUT20" - ], - [ - "BRKH_DSP_ACIN25", - "DSP_ACOUT25" - ], - [ - "BRKH_DSP_ACIN12", - "DSP_ACOUT12" - ], - [ - "BRKH_DSP_BCIN9", - "DSP_BCOUT9" - ], - [ - "BRKH_DSP_ACIN3", - "DSP_ACOUT3" - ], - [ - "BRKH_DSP_ACIN5", - "DSP_ACOUT5" - ], - [ - "BRKH_DSP_ACIN24", - "DSP_ACOUT24" - ], - [ - "BRKH_DSP_ACIN4", - "DSP_ACOUT4" - ], - [ - "BRKH_DSP_PCIN32", - "DSP_PCOUT32" - ], - [ - "BRKH_DSP_MULTSIGNIN", - "DSP_MULTSIGNOUT" - ], - [ - "BRKH_DSP_PCIN5", - "DSP_PCOUT5" - ], - [ - "BRKH_DSP_PCIN16", - "DSP_PCOUT16" - ], - [ - "BRKH_DSP_PCIN40", - "DSP_PCOUT40" - ], - [ - "BRKH_DSP_ACIN9", - "DSP_ACOUT9" - ], - [ - "BRKH_DSP_PCIN15", - "DSP_PCOUT15" - ], - [ - "BRKH_DSP_ACIN21", - "DSP_ACOUT21" - ], - [ - "BRKH_DSP_PCIN27", - "DSP_PCOUT27" - ], - [ - "BRKH_DSP_PCIN6", - "DSP_PCOUT6" - ], - [ - "BRKH_DSP_PCIN39", - "DSP_PCOUT39" - ], - [ - "BRKH_DSP_ACIN10", - "DSP_ACOUT10" - ], - [ - "BRKH_DSP_ACIN23", - "DSP_ACOUT23" - ], - [ - "BRKH_DSP_PCIN45", - "DSP_PCOUT45" - ], - [ - "BRKH_DSP_PCIN34", - "DSP_PCOUT34" - ], - [ - "BRKH_DSP_PCIN37", - "DSP_PCOUT37" - ], - [ - "BRKH_DSP_ACIN20", - "DSP_ACOUT20" - ], - [ - "BRKH_DSP_PCIN12", - "DSP_PCOUT12" - ], - [ - "BRKH_DSP_PCIN8", - "DSP_PCOUT8" - ], - [ - "BRKH_DSP_BCIN8", - "DSP_BCOUT8" - ], - [ - "BRKH_DSP_BCIN13", - "DSP_BCOUT13" - ], - [ - "BRKH_DSP_PCIN42", - "DSP_PCOUT42" - ], - [ - "BRKH_DSP_PCIN26", - "DSP_PCOUT26" - ], - [ - "BRKH_DSP_ACIN18", - "DSP_ACOUT18" - ], - [ - "BRKH_DSP_PCIN36", - "DSP_PCOUT36" - ], - [ - "BRKH_DSP_CARRYCASCIN", - "DSP_CARRYCASCOUT" - ], - [ - "BRKH_DSP_PCIN41", - "DSP_PCOUT41" - ], - [ - "BRKH_DSP_ACIN29", - "DSP_ACOUT29" - ], - [ - "BRKH_DSP_PCIN35", - "DSP_PCOUT35" - ], - [ - "BRKH_DSP_BCIN7", - "DSP_BCOUT7" - ], - [ - "BRKH_DSP_BCIN11", - "DSP_BCOUT11" - ], - [ - "BRKH_DSP_ACIN13", - "DSP_ACOUT13" - ], - [ - "BRKH_DSP_PCIN24", - "DSP_PCOUT24" - ], - [ - "BRKH_DSP_ACIN11", - "DSP_ACOUT11" - ], - [ - "BRKH_DSP_PCIN25", - "DSP_PCOUT25" - ], - [ - "BRKH_DSP_PCIN14", - "DSP_PCOUT14" - ], - [ - "BRKH_DSP_PCIN17", - "DSP_PCOUT17" - ], - [ - "BRKH_DSP_PCIN43", - "DSP_PCOUT43" - ] - ] - }, - { - "grid_deltas": [ - 1, - -1 - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_HROW_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_HROW_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_HROW_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_LH1_1", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH6_1", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_HROW_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_HROW_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NE4BEG3_1", - "VBRK_NE4BEG3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 10 - ], - "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_R" - ], - "wire_pairs": [ - [ - "PCIE_LOGIC_OUTS_B0_R_0", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "PCIE_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "PCIE_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "PCIE_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "PCIE_LOGIC_OUTS_B22_R_0", - "INT_INTERFACE_LOGIC_OUTS_B22" - ], - [ - "PCIE_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "PCIE_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "PCIE_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "PCIE_FAN3_R_0", - "INT_INTERFACE_FAN3" - ], - [ - "PCIE_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "PCIE_LOGIC_OUTS_B7_R_0", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "PCIE_IMUX31_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT31" - ], - [ - "PCIE_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "PCIE_IMUX27_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT27" - ], - [ - "PCIE_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "PCIE_LOGIC_OUTS_B4_R_0", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "PCIE_LOGIC_OUTS_B17_R_0", - "INT_INTERFACE_LOGIC_OUTS_B17" - ], - [ - "PCIE_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "PCIE_BYP3_R_0", - "INT_INTERFACE_BYP3" - ], - [ - "PCIE_IMUX35_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT35" - ], - [ - "PCIE_IMUX44_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT44" - ], - [ - "PCIE_IMUX0_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT0" - ], - [ - "PCIE_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "PCIE_FAN6_R_0", - "INT_INTERFACE_FAN6" - ], - [ - "PCIE_IMUX28_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT28" - ], - [ - "PCIE_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "PCIE_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "PCIE_LOGIC_OUTS_B21_R_0", - "INT_INTERFACE_LOGIC_OUTS_B21" - ], - [ - "PCIE_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "PCIE_FAN2_R_0", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_SE4C0_0", - "INT_INTERFACE_SE4C0" - ], - [ - "PCIE_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "PCIE_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "PCIE_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "PCIE_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "PCIE_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "PCIE_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "PCIE_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "PCIE_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "PCIE_IMUX42_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT42" - ], - [ - "PCIE_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "PCIE_LOGIC_OUTS_B14_R_0", - "INT_INTERFACE_LOGIC_OUTS_B14" - ], - [ - "PCIE_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "PCIE_IMUX46_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT46" - ], - [ - "PCIE_FAN5_R_0", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_IMUX13_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT13" - ], - [ - "PCIE_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "PCIE_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "PCIE_IMUX15_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT15" - ], - [ - "PCIE_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "PCIE_IMUX45_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT45" - ], - [ - "PCIE_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "PCIE_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "PCIE_IMUX23_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT23" - ], - [ - "PCIE_IMUX8_R_0", - "PCIE_INT_INTERFACE_IMUX_OUT8" - ], - [ - "PCIE_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "PCIE_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "PCIE_FAN0_R_0", - "INT_INTERFACE_FAN0" - ], - [ - "PCIE_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "PCIE_CTRL0_R_0", - "INT_INTERFACE_CTRL0" - ], - [ - "PCIE_LH1_0", - "INT_INTERFACE_LH1" - ], - [ - "PCIE_FAN7_R_0", - "INT_INTERFACE_FAN7" - ], - [ - "PCIE_CLK0_R_0", - "INT_INTERFACE_CLK0" - ], - [ - "PCIE_LOGIC_OUTS_B1_R_0", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "PCIE_LOGIC_OUTS_B23_R_0", - "INT_INTERFACE_LOGIC_OUTS_B23" - ], - [ - "PCIE_LOGIC_OUTS_B6_R_0", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "PCIE_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "PCIE_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "PCIE_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "PCIE_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "PCIE_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "PCIE_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "PCIE_LOGIC_OUTS_B19_R_0", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "PCIE_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "PCIE_LOGIC_OUTS_B18_R_0", - "INT_INTERFACE_LOGIC_OUTS_B18" - ], - [ - "PCIE_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "PCIE_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - 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"CFG_CENTER_WW4C2_8", - "VFRAME_WW4C2" - ], - [ - "CFG_CENTER_IMUX44_8", - "VFRAME_IMUX44" - ], - [ - "CFG_CENTER_FAN4_8", - "VFRAME_FAN4" - ], - [ - "CFG_CENTER_ER1BEG2_8", - "VFRAME_ER1BEG2" - ], - [ - "CFG_CENTER_SW2A2_8", - "VFRAME_SW2A2" - ], - [ - "CFG_CENTER_BYP7_8", - "VFRAME_BYP7" - ], - [ - "CFG_CENTER_WW4C0_8", - "VFRAME_WW4C0" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "BRKH_CLK", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "BRKH_CLK_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "BRKH_CLK_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "BRKH_CLK_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "BRKH_CLK_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "BRKH_CLK_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - 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"DSP_0_PCIN38" - ], - [ - "BRKH_DSP_PCIN8", - "DSP_0_PCIN8" - ] - ] - }, - { - "grid_deltas": [ - -1, - 2 - ], - "tile_types": [ - "GTX_CHANNEL_2", - "VBRK_EXT" - ], - "wire_pairs": [ - [ - "GTXE2_IMUX39_3", - "VBRK_EXT_IMUX39" - ], - [ - "GTXE2_IMUX37_3", - "VBRK_EXT_IMUX37" - ], - [ - "GTXE2_BYP6_3", - "VBRK_EXT_BYP6" - ], - [ - "GTXE2_LOGIC_OUTS_B20_3", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTXE2_IMUX23_3", - "VBRK_EXT_IMUX23" - ], - [ - "GTXE2_LOGIC_OUTS_B11_3", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTXE2_FAN4_3", - "VBRK_EXT_FAN4" - ], - [ - "GTXE2_IMUX9_3", - "VBRK_EXT_IMUX9" - ], - [ - "GTXE2_IMUX17_3", - "VBRK_EXT_IMUX17" - ], - [ - "GTXE2_IMUX21_3", - "VBRK_EXT_IMUX21" - ], - [ - "GTXE2_BYP3_3", - "VBRK_EXT_BYP3" - ], - [ - "GTXE2_IMUX11_3", - "VBRK_EXT_IMUX11" - ], - [ - "GTXE2_IMUX44_3", - "VBRK_EXT_IMUX44" - ], - [ - "GTXE2_BYP4_3", - "VBRK_EXT_BYP4" - ], - [ - "GTXE2_IMUX0_3", - "VBRK_EXT_IMUX0" - ], - [ - "GTXE2_IMUX33_3", - "VBRK_EXT_IMUX33" - ], - [ - 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"VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTXE2_LOGIC_OUTS_B23_3", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTXE2_LOGIC_OUTS_B14_3", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTXE2_LOGIC_OUTS_B3_3", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTXE2_IMUX26_3", - "VBRK_EXT_IMUX26" - ], - [ - "GTXE2_CLK0_3", - "VBRK_EXT_CLK0" - ], - [ - "GTXE2_BYP1_3", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_IMUX12_3", - "VBRK_EXT_IMUX12" - ], - [ - "GTXE2_FAN7_3", - "VBRK_EXT_FAN7" - ], - [ - "GTXE2_IMUX27_3", - "VBRK_EXT_IMUX27" - ], - [ - "GTXE2_IMUX8_3", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX16_3", - "VBRK_EXT_IMUX16" - ], - [ - "GTXE2_IMUX46_3", - "VBRK_EXT_IMUX46" - ], - [ - "GTXE2_LOGIC_OUTS_B16_3", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTXE2_IMUX20_3", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_LOGIC_OUTS_B5_3", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTXE2_IMUX42_3", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_IMUX18_3", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_CLK1_3", - "VBRK_EXT_CLK1" - ], - [ - "GTXE2_LOGIC_OUTS_B8_3", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTXE2_IMUX43_3", - "VBRK_EXT_IMUX43" - ], - [ - "GTXE2_LOGIC_OUTS_B13_3", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_IMUX32_3", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_IMUX40_3", - "VBRK_EXT_IMUX40" - ], - [ - "GTXE2_IMUX29_3", - "VBRK_EXT_IMUX29" - ], - [ - "GTXE2_LOGIC_OUTS_B9_3", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTXE2_IMUX25_3", - "VBRK_EXT_IMUX25" - ], - [ - "GTXE2_IMUX10_3", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_CTRL1_3", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_LOGIC_OUTS_B4_3", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTXE2_FAN0_3", - "VBRK_EXT_FAN0" - ], - [ - "GTXE2_BYP2_3", - "VBRK_EXT_BYP2" - ], - [ - "GTXE2_LOGIC_OUTS_B2_3", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTXE2_IMUX1_3", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_IMUX28_3", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_IMUX38_3", - "VBRK_EXT_IMUX38" - ], - [ - "GTXE2_LOGIC_OUTS_B7_3", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTXE2_CTRL0_3", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_IMUX41_3", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_IMUX13_3", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_LOGIC_OUTS_B1_3", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_IMUX14_3", - "VBRK_EXT_IMUX14" - ], - [ - "GTXE2_BYP7_3", - "VBRK_EXT_BYP7" - ], - [ - "GTXE2_FAN3_3", - "VBRK_EXT_FAN3" - ], - [ - "GTXE2_LOGIC_OUTS_B6_3", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTXE2_LOGIC_OUTS_B10_3", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTXE2_IMUX2_3", - "VBRK_EXT_IMUX2" - ], - [ - "GTXE2_BYP0_3", - "VBRK_EXT_BYP0" - ], - [ - "GTXE2_IMUX6_3", - "VBRK_EXT_IMUX6" - ], - [ - "GTXE2_IMUX34_3", - "VBRK_EXT_IMUX34" - ], - [ - "GTXE2_IMUX5_3", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_IMUX47_3", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_IMUX36_3", - "VBRK_EXT_IMUX36" - ], - [ - "GTXE2_IMUX22_3", - "VBRK_EXT_IMUX22" - ], - [ - "GTXE2_IMUX35_3", - "VBRK_EXT_IMUX35" - ], - [ - "GTXE2_IMUX15_3", - "VBRK_EXT_IMUX15" - ], - [ - "GTXE2_IMUX24_3", - "VBRK_EXT_IMUX24" - ], - [ - "GTXE2_LOGIC_OUTS_B18_3", - "VBRK_EXT_LOGIC_OUTS_B18" - ] - ] - }, - { - "grid_deltas": [ - 0, - -2 - ], - "tile_types": [ - "RIOI", - "RIOI_SING" - ], - "wire_pairs": [ - [ - "IOI_LEAF_GCLK0", - "IOI_SING_LEAF_GCLK0" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_SING_RCLK_FORIO3" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_SING_LEAF_GCLK2" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_SING_LEAF_GCLK4" - ], - [ - "IOI_IOCLK3", - "IOI_SING_IOCLK3" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_SING_LEAF_GCLK5" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_SING_RCLK_FORIO1" - ], - [ - "IOI_IOCLK2", - "IOI_SING_IOCLK2" - ], - [ - "IOI_TBYTEIN", - "IOI_SING_TBYTEIN" - ], - [ - "IOI_IOCLK1", - "IOI_SING_IOCLK1" - ], - [ - "IOI_RCLK_FORIO0", - "IOI_SING_RCLK_FORIO0" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_SING_LEAF_GCLK1" - ], - [ - "IOI_IOCLK0", - "IOI_SING_IOCLK0" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_SING_RCLK_FORIO2" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_SING_LEAF_GCLK3" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - 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- "IOI_IMUX11_1", - "TERM_INT_IMUX11" - ], - [ - "IOI_IMUX7_1", - "TERM_INT_IMUX7" - ], - [ - "IOI_FAN1_1", - "TERM_INT_FAN1" - ], - [ - "IOI_LOGIC_OUTS18_1", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "IOI_IMUX19_1", - "TERM_INT_IMUX19" - ], - [ - "IOI_IMUX0_1", - "TERM_INT_IMUX0" - ], - [ - "IOI_IMUX39_1", + "IOI_IMUX39_0", "TERM_INT_IMUX39" ], [ - "IOI_IMUX9_1", - "TERM_INT_IMUX9" + "IOI_IMUX40_0", + "TERM_INT_IMUX40" ], [ - "IOI_IMUX41_1", + "IOI_IMUX41_0", "TERM_INT_IMUX41" ], [ - "IOI_PHASER_TO_IO_OCLK_0", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_LOGIC_OUTS5_1", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_IMUX43_1", - "TERM_INT_IMUX43" - ], - [ - "IOI_FAN7_1", - "TERM_INT_FAN7" - ], - [ - "IOI_IMUX1_1", - "TERM_INT_IMUX1" - ], - [ - "IOI_IMUX47_1", - "TERM_INT_IMUX47" - ], - [ - "IOI_IMUX22_1", - "TERM_INT_IMUX22" - ], - [ - "IOI_CTRL1_1", - "TERM_INT_CTRL1" - ], - [ - "IOI_PHASER_TO_IO_OCLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "IOI_IMUX14_1", - "TERM_INT_IMUX14" - ], - [ - "IOI_IMUX42_1", + "IOI_IMUX42_0", "TERM_INT_IMUX42" ], [ - "IOI_FAN0_1", - "TERM_INT_FAN0" + "IOI_IMUX43_0", + "TERM_INT_IMUX43" ], [ - "IOI_IMUX35_1", - "TERM_INT_IMUX35" - ], - [ - "IOI_IMUX6_1", - "TERM_INT_IMUX6" - ], - [ - "IOI_IMUX20_1", - "TERM_INT_IMUX20" - ], - [ - "IOI_IMUX3_1", - "TERM_INT_IMUX3" - ], - [ - "IOI_PHASER_TO_IO_ICLK_0", - "L_TERM_INT_PHASER_TO_IO_ICLK" - ], - [ - "IOI_IMUX25_1", - "TERM_INT_IMUX25" - ], - [ - "IOI_CTRL0_1", - "TERM_INT_CTRL0" - ], - [ - "IOI_BYP4_1", - "TERM_INT_BYP4" - ], - [ - "IOI_IMUX30_1", - "TERM_INT_IMUX30" - ], - [ - "IOI_LOGIC_OUTS16_1", - "TERM_INT_LOGIC_OUTS_L_B16" - ], - [ - "IOI_LOGIC_OUTS23_1", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "IOI_BYP5_1", - "TERM_INT_BYP5" - ], - [ - "IOI_CLK1_1", - "TERM_INT_CLK1" - ], - [ - "IOI_IMUX15_1", - "TERM_INT_IMUX15" - ], - [ - "IOI_IMUX16_1", - "TERM_INT_IMUX16" - ], - [ - "IOI_IMUX13_1", - "TERM_INT_IMUX13" - ], - [ - "IOI_IMUX33_1", - "TERM_INT_IMUX33" - ], - [ - "IOI_IMUX29_1", - "TERM_INT_IMUX29" - ], - [ - "IOI_BYP1_1", - "TERM_INT_BYP1" - ], - [ - "IOI_LOGIC_OUTS3_1", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_BYP0_1", - "TERM_INT_BYP0" - ], - [ - "IOI_IMUX8_1", - "TERM_INT_IMUX8" - ], - [ - "IOI_LOGIC_OUTS1_1", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_IMUX44_1", + "IOI_IMUX44_0", "TERM_INT_IMUX44" ], [ - "IOI_LOGIC_OUTS10_1", - "TERM_INT_LOGIC_OUTS_L_B10" - ] - ] - }, - { - "grid_deltas": [ - 0, - -1 - ], - "tile_types": [ - "INT_R", - "T_TERM_INT" - ], - "wire_pairs": [ - [ - "SE6E3", - "T_TERM_UTURN_INT_SE6E3" - ], - [ - "SS6D0", - "T_TERM_UTURN_INT_SS6D0" - ], - [ - "SE2A0", - "T_TERM_UTURN_INT_SE2A0" - ], - [ - "NN6D1", - "T_TERM_UTURN_INT_SS6E2" - ], - [ - "SS6A0", - "T_TERM_UTURN_INT_SS6A0" - ], - [ - "NE6B0", - "T_TERM_UTURN_INT_SE6C3" - ], - [ - "SE6C3", - "T_TERM_UTURN_INT_SE6C3" - ], - [ - "NE6B1", - "T_TERM_UTURN_INT_SE6C2" - ], - [ - "LV5", - "T_TERM_INT_UTURN_LV_R5" - ], - [ - "SE6E2", - "T_TERM_UTURN_INT_SE6E2" - ], - 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"SL1END1", - "T_TERM_UTURN_INT_SL1END1" - ], - [ - "NE2BEG2", - "T_TERM_UTURN_INT_SE2A1" - ], - [ - "SE6B1", - "T_TERM_UTURN_INT_SE6B1" - ], - [ - "NE6A3", - "T_TERM_UTURN_INT_SE6B0" - ], - [ - "SE6D2", - "T_TERM_UTURN_INT_SE6D2" - ], - [ - "LVB6", - "T_TERM_UTURN_INT_LVB5" - ], - [ - "NW6A0", - "T_TERM_UTURN_INT_SW6B3" - ], - [ - "SS6C2", - "T_TERM_UTURN_INT_SS6C2" - ], - [ - "WL1END3", - "T_TERM_UTURN_INT_WR1END_S1_0" - ], - [ - "EL1END_S3_0", - "T_TERM_UTURN_INT_ER1END3" - ], - [ - "LV17", - "T_TERM_INT_UTURN_LV_R17" - ], - [ - "SS6C1", - "T_TERM_UTURN_INT_SS6C1" - ], - [ - "NE6C1", - "T_TERM_UTURN_INT_SE6D2" - ], - [ - "NN6B0", - "T_TERM_UTURN_INT_SS6C3" - ], - [ - "NN6D2", - "T_TERM_UTURN_INT_SS6E1" - ], - [ - "NN6BEG2", - "T_TERM_UTURN_INT_SS6A1" - ], - [ - "NW6D1", - "T_TERM_UTURN_INT_SW6E2" - ], - [ - "SS6A1", - "T_TERM_UTURN_INT_SS6A1" - ], - [ - "SS2END3", - "T_TERM_UTURN_INT_SS2END3" - ], - [ - "SL1END3", - "T_TERM_UTURN_INT_SL1END3" - ], - [ - "NN6BEG0", - "T_TERM_UTURN_INT_SS6A3" - ], - [ - "SS6A3", - "T_TERM_UTURN_INT_SS6A3" - ], - [ - "FAN_BOUNCE_S3_6", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6" - ], - [ - "NN6A3", - "T_TERM_UTURN_INT_SS6B0" - ], - [ - "NR1BEG2", - "T_TERM_UTURN_INT_SL1END1" - ], - [ - "SW2A3", - "T_TERM_UTURN_INT_SW2A3" - ], - [ - "NL1BEG0", - "T_TERM_UTURN_INT_SR1END3" - ], - [ - "SW6D0", - "T_TERM_UTURN_INT_SW6D0" - ], - [ - "SE6D0", - "T_TERM_UTURN_INT_SE6D0" - ], - [ - "LV3", - "T_TERM_INT_UTURN_LV_R3" - ], - [ - "NN6B1", - "T_TERM_UTURN_INT_SS6C2" - ], - [ - "SW6B2", - "T_TERM_UTURN_INT_SW6B2" - ], - [ - "SE6C2", - "T_TERM_UTURN_INT_SE6C2" - ], - [ - "NN6C3", - "T_TERM_UTURN_INT_SS6D0" - ], - [ - "NW6C2", - "T_TERM_UTURN_INT_SW6D1" - ], - [ - "LVB1", - "T_TERM_UTURN_INT_LVB1" - ], - [ - "NE2BEG3", - "T_TERM_UTURN_INT_SE2A0" - ], - [ - "SE6E0", - "T_TERM_UTURN_INT_SE6E0" - ], - [ - "BYP_BOUNCE3", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2" - ], - [ - "NW6D2", - "T_TERM_UTURN_INT_SW6E1" - ], - [ - "SS6E1", - "T_TERM_UTURN_INT_SS6E1" - ], - [ - "LV13", - "T_TERM_INT_UTURN_LV_R4" - ], - [ - "ER1END3", - "T_TERM_UTURN_INT_ER1END3" - ], - [ - "SW2A2", - "T_TERM_UTURN_INT_SW2A2" - ], - [ - "SS6END1", - "T_TERM_UTURN_INT_SS6END1" - ], - [ - "NW6A1", - "T_TERM_UTURN_INT_SW6B2" - ], - [ - "SS2END0", - "T_TERM_UTURN_INT_SS2END0" - ], - [ - "FAN_BOUNCE_S3_4", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4" - ], - [ - "NN6D0", - "T_TERM_UTURN_INT_SS6E3" - ], - [ - "SE2A3", - "T_TERM_UTURN_INT_SE2A3" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "CLBLM_R", - "CLBLM_R" - ], - "wire_pairs": [ - [ - "CLBLM_L_CIN", - "CLBLM_L_COUT_N" - ], - [ - "CLBLM_M_CIN", - "CLBLM_M_COUT_N" - ] - ] - }, - { - "grid_deltas": [ - -1, - -4 - ], - "tile_types": [ - "BRAM_L", - "VBRK" - ], - "wire_pairs": [ - [ - "BRAM_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "BRAM_EE4C0_4", - "VBRK_EE4C0" - ], - [ - "BRAM_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "BRAM_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "BRAM_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "BRAM_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "BRAM_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "BRAM_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "BRAM_LH1_4", - "VBRK_LH1" - ], - [ - "BRAM_LH8_4", - "VBRK_LH8" - ], - [ - "BRAM_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "BRAM_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "BRAM_LH12_4", - "VBRK_LH12" - ], - [ - "BRAM_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "BRAM_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "BRAM_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "BRAM_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "BRAM_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "BRAM_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "BRAM_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "BRAM_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "BRAM_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "BRAM_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "BRAM_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "BRAM_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "BRAM_LH9_4", - "VBRK_LH9" - ], - [ - "BRAM_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "BRAM_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "BRAM_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "BRAM_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "BRAM_LH7_4", - "VBRK_LH7" - ], - [ - "BRAM_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "BRAM_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "BRAM_LH5_4", - "VBRK_LH5" - ], - [ - "BRAM_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "BRAM_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "BRAM_LH3_4", - "VBRK_LH3" - ], - [ - "BRAM_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "BRAM_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "BRAM_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "BRAM_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "BRAM_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "BRAM_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "BRAM_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "BRAM_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "BRAM_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "BRAM_LH10_4", - "VBRK_LH10" - ], - [ - "BRAM_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "BRAM_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "BRAM_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "BRAM_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "BRAM_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "BRAM_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "BRAM_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "BRAM_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "BRAM_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "BRAM_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "BRAM_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "BRAM_SE2A1_4", - "VBRK_SE2A1" - ], - [ - "BRAM_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "BRAM_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "BRAM_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "BRAM_LH11_4", - "VBRK_LH11" - ], - [ - "BRAM_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "BRAM_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "BRAM_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "BRAM_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "BRAM_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "BRAM_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "BRAM_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "BRAM_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "BRAM_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "BRAM_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "BRAM_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "BRAM_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "BRAM_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "BRAM_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "BRAM_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "BRAM_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "BRAM_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "BRAM_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "BRAM_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "BRAM_LH2_4", - "VBRK_LH2" - ], - [ - "BRAM_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "BRAM_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "BRAM_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "BRAM_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "BRAM_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "BRAM_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "BRAM_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "BRAM_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "BRAM_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "BRAM_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "BRAM_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "BRAM_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "BRAM_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "BRAM_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "BRAM_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "BRAM_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "BRAM_LH6_4", - "VBRK_LH6" - ], - [ - "BRAM_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "BRAM_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "BRAM_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "BRAM_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "BRAM_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "BRAM_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "BRAM_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "BRAM_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "BRAM_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "BRAM_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "BRAM_LH4_4", - "VBRK_LH4" - ], - [ - "BRAM_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "BRAM_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "BRAM_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "BRAM_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "BRAM_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "BRAM_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "BRAM_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "BRAM_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "BRAM_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "BRAM_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "BRAM_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "BRAM_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "BRAM_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "BRAM_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "BRAM_EE4C1_4", - "VBRK_EE4C1" - ] - ] - }, - { - "grid_deltas": [ - 0, - 1 - ], - "tile_types": [ - "DSP_L", - "HCLK_DSP_L" - ], - "wire_pairs": [ - [ - "DSP_0_ACIN0", - "HCLK_DSP_ACIN0" - ], - [ - "DSP_0_PCIN13", - "HCLK_DSP_PCIN13" - ], - [ - "DSP_0_PCIN16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_0_BCIN4", - "HCLK_DSP_BCIN4" - ], - [ - "DSP_0_PCIN27", - "HCLK_DSP_PCIN27" - ], - [ - "DSP_0_BCIN1", - "HCLK_DSP_BCIN1" - ], - [ - "DSP_0_PCIN2", - "HCLK_DSP_PCIN2" - ], - [ - "DSP_0_ACIN1", - "HCLK_DSP_ACIN1" - ], - [ - "DSP_0_CARRYCASCIN", - "HCLK_DSP_CARRYCASCIN" - ], - [ - "DSP_0_BCIN10", - "HCLK_DSP_BCIN10" - ], - [ - "DSP_0_ACIN4", - "HCLK_DSP_ACIN4" - ], - [ - "DSP_0_PCIN37", - "HCLK_DSP_PCIN37" - ], - [ - "DSP_0_PCIN22", - "HCLK_DSP_PCIN22" - ], - [ - "DSP_0_PCIN12", - "HCLK_DSP_PCIN12" - ], - [ - "DSP_0_BCIN2", - "HCLK_DSP_BCIN2" - ], - [ - "DSP_0_ACIN9", - "HCLK_DSP_ACIN9" - ], - [ - "DSP_0_BCIN12", - "HCLK_DSP_BCIN12" - ], - [ - "DSP_0_PCIN0", - "HCLK_DSP_PCIN0" - ], - [ - "DSP_0_BCIN17", - "HCLK_DSP_BCIN17" - ], - [ - "DSP_0_PCIN4", - "HCLK_DSP_PCIN4" - ], - [ - "DSP_0_PCIN8", - "HCLK_DSP_PCIN8" - ], - [ - "DSP_0_PCIN38", - "HCLK_DSP_PCIN38" - ], - [ - "DSP_0_PCIN25", - "HCLK_DSP_PCIN25" - ], - [ - "DSP_0_BCIN13", - "HCLK_DSP_BCIN13" - ], - [ - "DSP_0_ACIN6", - "HCLK_DSP_ACIN6" - ], - [ - "DSP_0_PCIN28", - "HCLK_DSP_PCIN28" - ], - [ - "DSP_0_ACIN25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_0_PCIN18", - "HCLK_DSP_PCIN18" - ], - [ - "DSP_0_ACIN16", - "HCLK_DSP_ACIN16" - ], - [ - "DSP_0_PCIN31", - "HCLK_DSP_PCIN31" - ], - [ - "DSP_0_ACIN21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_0_BCIN15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_0_PCIN15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_0_ACIN19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_0_ACIN18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_0_PCIN23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_0_PCIN34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_0_ACIN3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_0_PCIN5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_0_PCIN26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_0_BCIN9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_0_ACIN28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_0_PCIN29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_0_PCIN10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_0_ACIN2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_0_PCIN40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_0_ACIN17", - "HCLK_DSP_ACIN17" - ], - [ - "DSP_0_PCIN14", - "HCLK_DSP_PCIN14" - ], - [ - "DSP_0_PCIN33", - "HCLK_DSP_PCIN33" - ], - [ - "DSP_0_PCIN35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_0_BCIN14", - "HCLK_DSP_BCIN14" - ], - [ - "DSP_0_PCIN39", - "HCLK_DSP_PCIN39" - ], - [ - "DSP_0_PCIN42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_0_PCIN1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_0_PCIN45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_0_BCIN6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_0_BCIN16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_0_ACIN26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_0_ACIN20", - "HCLK_DSP_ACIN20" - ], - [ - "DSP_0_PCIN9", - "HCLK_DSP_PCIN9" - ], - [ - "DSP_0_MULTSIGNIN", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_0_BCIN11", - "HCLK_DSP_BCIN11" - ], - [ - "DSP_0_PCIN19", - "HCLK_DSP_PCIN19" - ], - [ - "DSP_0_PCIN41", - "HCLK_DSP_PCIN41" - ], - [ - "DSP_0_PCIN21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_0_ACIN15", - "HCLK_DSP_ACIN15" - ], - [ - "DSP_0_PCIN17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_0_ACIN22", - "HCLK_DSP_ACIN22" - ], - [ - "DSP_0_ACIN11", - "HCLK_DSP_ACIN11" - ], - [ - "DSP_0_PCIN43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_0_ACIN14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_0_BCIN0", - "HCLK_DSP_BCIN0" - ], - [ - "DSP_0_BCIN7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_0_PCIN7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_0_PCIN6", - "HCLK_DSP_PCIN6" - ], - [ - "DSP_0_PCIN11", - "HCLK_DSP_PCIN11" - ], - [ - "DSP_0_BCIN3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_0_PCIN46", - "HCLK_DSP_PCIN46" - ], - [ - "DSP_0_ACIN10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_0_BCIN5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_0_ACIN12", - "HCLK_DSP_ACIN12" - ], - [ - "DSP_0_PCIN44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_0_ACIN29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_0_PCIN3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_0_PCIN47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_0_ACIN27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_0_ACIN23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_0_ACIN5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_0_PCIN32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_0_PCIN20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_0_ACIN24", - "HCLK_DSP_ACIN24" - ], - [ - "DSP_0_ACIN8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_0_BCIN8", - "HCLK_DSP_BCIN8" - ], - [ - "DSP_0_ACIN7", - "HCLK_DSP_ACIN7" - ], - [ - "DSP_0_ACIN13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_0_PCIN24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_0_PCIN30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_0_PCIN36", - "HCLK_DSP_PCIN36" - ] - ] - }, - { - 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"INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "INT_INTERFACE_IMUX5", - "TERM_INT_IMUX5" - ], - [ - "INT_INTERFACE_IMUX11", - "TERM_INT_IMUX11" - ], - [ - "INT_INTERFACE_LH5", - "R_TERM_INT_LH4" - ], - [ - "INT_INTERFACE_SE2A1", - "R_TERM_INT_SW2A1" - ], - [ - "INT_INTERFACE_LH9", - "R_TERM_INT_LH3" - ], - [ - "INT_INTERFACE_IMUX29", - "TERM_INT_IMUX29" - ], - [ - "INT_INTERFACE_SE4C3", - "R_TERM_INT_SW4END3" - ], - [ - "INT_INTERFACE_IMUX2", - "TERM_INT_IMUX2" - ], - [ - "INT_INTERFACE_LH4", - "R_TERM_INT_LH3" - ], - [ - "INT_INTERFACE_WW4A1", - "R_TERM_INT_WW4A1" - ], - [ - "INT_INTERFACE_IMUX14", - "TERM_INT_IMUX14" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B23", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "INT_INTERFACE_EE4C0", - "R_TERM_INT_WW4END0" - ], - [ - "INT_INTERFACE_ER1BEG1", - "R_TERM_INT_WR1END1" - ], - [ - "INT_INTERFACE_IMUX38", - "TERM_INT_IMUX38" - ], - [ - "INT_INTERFACE_IMUX31", - "TERM_INT_IMUX31" - ], - [ - "INT_INTERFACE_SW4A0", - "R_TERM_INT_SW4A0" - ], - [ - "INT_INTERFACE_NW2A1", - "R_TERM_INT_NW2A1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B5", + "IOI_LOGIC_OUTS5_0", "TERM_INT_LOGIC_OUTS_L_B5" ], [ - "INT_INTERFACE_WL1END3", - "R_TERM_INT_WL1END3" + "IOI_LOGIC_OUTS6_0", + "TERM_INT_LOGIC_OUTS_L_B6" ], [ - "INT_INTERFACE_LOGIC_OUTS_B13", - "TERM_INT_LOGIC_OUTS_L_B13" + "IOI_LOGIC_OUTS7_0", + "TERM_INT_LOGIC_OUTS_L_B7" ], [ - "INT_INTERFACE_WW2A1", - "R_TERM_INT_WW2A1" - ], - [ - "INT_INTERFACE_NW4END2", - "R_TERM_INT_NW4END2" - ], - [ - "INT_INTERFACE_IMUX15", - "TERM_INT_IMUX15" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B8", + "IOI_LOGIC_OUTS8_0", "TERM_INT_LOGIC_OUTS_L_B8" ], [ - "INT_INTERFACE_FAN3", - "TERM_INT_FAN3" + "IOI_LOGIC_OUTS9_0", + "TERM_INT_LOGIC_OUTS_L_B9" ], [ - "INT_INTERFACE_BLOCK_OUTS_B0", - "TERM_INT_BLOCK_OUTS_L_B0" + "IOI_LOGIC_OUTS10_0", + "TERM_INT_LOGIC_OUTS_L_B10" ], [ - "INT_INTERFACE_IMUX26", - "TERM_INT_IMUX26" - ], - [ - "INT_INTERFACE_SE2A2", - "R_TERM_INT_SW2A2" - ], - [ - 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], - [ - "INT_INTERFACE_LOGIC_OUTS_B2", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "INT_INTERFACE_BLOCK_OUTS_B2", - "TERM_INT_BLOCK_OUTS_L_B2" - ], - [ - "INT_INTERFACE_SE4C0", - "R_TERM_INT_SW4END0" - ], - [ - "INT_INTERFACE_IMUX8", - "TERM_INT_IMUX8" - ], - [ - "INT_INTERFACE_SE4BEG1", - "R_TERM_INT_SW4A1" - ], - [ - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90" - ], - [ - "INT_INTERFACE_WW4B1", - "R_TERM_INT_WW4B1" - ], - [ - "INT_INTERFACE_WW4B3", - "R_TERM_INT_WW4B3" - ], - [ - "INT_INTERFACE_EE2BEG0", - "R_TERM_INT_WW2A0" - ], - [ - "INT_INTERFACE_NE4BEG3", - "R_TERM_INT_NW4A3" - ], - [ - "INT_INTERFACE_IMUX4", - "TERM_INT_IMUX4" - ], - [ - "INT_INTERFACE_EE2A0", - "R_TERM_INT_WW2END0" - ], - [ - "INT_INTERFACE_IMUX34", - "TERM_INT_IMUX34" - ], - [ - "INT_INTERFACE_NW4A0", - "R_TERM_INT_NW4A0" - ], - [ - "INT_INTERFACE_EE4BEG1", - "R_TERM_INT_WW4A1" - ], - [ - "INT_INTERFACE_WW4A0", - "R_TERM_INT_WW4A0" - ], - [ - "INT_INTERFACE_NE2A1", - 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- [ - "IOI_IOCLK2", - "IOI_IOCLK2" - ], - [ - "IOI_IOCLK3", - "IOI_IOCLK3" - ], - [ - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE2" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_RCLK_FORIO3" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK3" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK2" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_LEAF_GCLK5" - ], - [ - "IOI_IMUX_RC3", - "IOI_IMUX_RC1" - ], - [ - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CE3" - ], - [ - "IOI_IOCLK1", - "IOI_IOCLK1" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO1" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO2" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK1" - ], - [ - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO0" - ], - [ - "IOI_IOCLK0", - "IOI_IOCLK0" - ], - [ - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1" - ], - [ - "IOI_TBYTEIN", - "IOI_TBYTEIN" - ] - ] - }, - { - "grid_deltas": [ - -1, - 4 - ], - "tile_types": [ - "GTX_CHANNEL_3", + "R_TERM_INT_GTX", "VBRK_EXT" ], "wire_pairs": [ [ - "GTXE2_CTRL0_1", - "VBRK_EXT_CTRL0" - ], - [ - "GTXE2_IMUX45_1", - "VBRK_EXT_IMUX45" - ], - [ - "GTXE2_CTRL1_1", - "VBRK_EXT_CTRL1" - ], - [ - "GTXE2_IMUX17_1", - "VBRK_EXT_IMUX17" - ], - [ - "GTXE2_LOGIC_OUTS_B1_1", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTXE2_LOGIC_OUTS_B0_1", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTXE2_FAN3_1", - "VBRK_EXT_FAN3" - ], - [ - "GTXE2_IMUX34_1", - "VBRK_EXT_IMUX34" - ], - [ - "GTXE2_LOGIC_OUTS_B15_1", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTXE2_IMUX29_1", - "VBRK_EXT_IMUX29" - ], - [ - "GTXE2_IMUX42_1", - "VBRK_EXT_IMUX42" - ], - [ - "GTXE2_IMUX19_1", - "VBRK_EXT_IMUX19" - ], - [ - "GTXE2_BYP1_1", - "VBRK_EXT_BYP1" - ], - [ - "GTXE2_LOGIC_OUTS_B22_1", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTXE2_IMUX20_1", - "VBRK_EXT_IMUX20" - ], - [ - "GTXE2_IMUX36_1", - "VBRK_EXT_IMUX36" - ], - [ - "GTXE2_IMUX16_1", - "VBRK_EXT_IMUX16" - ], - [ - "GTXE2_LOGIC_OUTS_B13_1", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTXE2_FAN7_1", - "VBRK_EXT_FAN7" - ], - [ - "GTXE2_IMUX0_1", - "VBRK_EXT_IMUX0" - ], - [ - "GTXE2_IMUX32_1", - "VBRK_EXT_IMUX32" - ], - [ - "GTXE2_LOGIC_OUTS_B20_1", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTXE2_LOGIC_OUTS_B14_1", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTXE2_IMUX35_1", - "VBRK_EXT_IMUX35" - ], - [ - "GTXE2_CLK1_1", - "VBRK_EXT_CLK1" - ], - [ - "GTXE2_IMUX1_1", - "VBRK_EXT_IMUX1" - ], - [ - "GTXE2_LOGIC_OUTS_B5_1", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTXE2_FAN0_1", - "VBRK_EXT_FAN0" - ], - [ - "GTXE2_IMUX8_1", - "VBRK_EXT_IMUX8" - ], - [ - "GTXE2_IMUX21_1", - "VBRK_EXT_IMUX21" - ], - [ - "GTXE2_LOGIC_OUTS_B11_1", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTXE2_IMUX7_1", - "VBRK_EXT_IMUX7" - ], - [ - "GTXE2_IMUX2_1", - "VBRK_EXT_IMUX2" - ], - [ - "GTXE2_IMUX46_1", - "VBRK_EXT_IMUX46" - ], - [ - "GTXE2_BYP5_1", - "VBRK_EXT_BYP5" - ], - [ - "GTXE2_IMUX18_1", - "VBRK_EXT_IMUX18" - ], - [ - "GTXE2_IMUX14_1", - "VBRK_EXT_IMUX14" - ], - [ - "GTXE2_IMUX41_1", - "VBRK_EXT_IMUX41" - ], - [ - "GTXE2_IMUX13_1", - "VBRK_EXT_IMUX13" - ], - [ - "GTXE2_IMUX5_1", - "VBRK_EXT_IMUX5" - ], - [ - "GTXE2_LOGIC_OUTS_B17_1", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTXE2_BYP3_1", - "VBRK_EXT_BYP3" - ], - [ - "GTXE2_IMUX6_1", - "VBRK_EXT_IMUX6" - ], - [ - "GTXE2_LOGIC_OUTS_B6_1", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTXE2_BYP4_1", - "VBRK_EXT_BYP4" - ], - [ - "GTXE2_LOGIC_OUTS_B7_1", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTXE2_IMUX26_1", - "VBRK_EXT_IMUX26" - ], - [ - "GTXE2_IMUX40_1", - "VBRK_EXT_IMUX40" - ], - [ - "GTXE2_IMUX28_1", - "VBRK_EXT_IMUX28" - ], - [ - "GTXE2_IMUX25_1", - "VBRK_EXT_IMUX25" - ], - [ - "GTXE2_LOGIC_OUTS_B16_1", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTXE2_IMUX38_1", - "VBRK_EXT_IMUX38" - ], - [ - "GTXE2_IMUX37_1", - "VBRK_EXT_IMUX37" - ], - [ - "GTXE2_BYP6_1", - "VBRK_EXT_BYP6" - ], - [ - "GTXE2_IMUX3_1", - "VBRK_EXT_IMUX3" - ], - [ - "GTXE2_FAN4_1", - "VBRK_EXT_FAN4" - ], - [ - "GTXE2_IMUX43_1", - "VBRK_EXT_IMUX43" - ], - [ - "GTXE2_IMUX4_1", - "VBRK_EXT_IMUX4" - ], - [ - "GTXE2_LOGIC_OUTS_B8_1", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTXE2_IMUX10_1", - "VBRK_EXT_IMUX10" - ], - [ - "GTXE2_LOGIC_OUTS_B4_1", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTXE2_FAN5_1", - "VBRK_EXT_FAN5" - ], - [ - "GTXE2_LOGIC_OUTS_B18_1", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTXE2_IMUX24_1", - "VBRK_EXT_IMUX24" - ], - [ - "GTXE2_IMUX15_1", - "VBRK_EXT_IMUX15" - ], - [ - "GTXE2_CLK0_1", - "VBRK_EXT_CLK0" - ], - [ - "GTXE2_LOGIC_OUTS_B9_1", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTXE2_IMUX30_1", - "VBRK_EXT_IMUX30" - ], - [ - "GTXE2_LOGIC_OUTS_B19_1", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTXE2_FAN6_1", - "VBRK_EXT_FAN6" - ], - [ - "GTXE2_IMUX33_1", - "VBRK_EXT_IMUX33" - ], - [ - "GTXE2_IMUX39_1", - "VBRK_EXT_IMUX39" - ], - [ - "GTXE2_LOGIC_OUTS_B3_1", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTXE2_BYP7_1", - "VBRK_EXT_BYP7" - ], - [ - "GTXE2_FAN2_1", - "VBRK_EXT_FAN2" - ], - [ - "GTXE2_FAN1_1", - "VBRK_EXT_FAN1" - ], - [ - "GTXE2_IMUX22_1", - "VBRK_EXT_IMUX22" - ], - [ - "GTXE2_IMUX23_1", - "VBRK_EXT_IMUX23" - ], - [ - "GTXE2_IMUX47_1", - "VBRK_EXT_IMUX47" - ], - [ - "GTXE2_BYP2_1", - "VBRK_EXT_BYP2" - ], - [ - "GTXE2_LOGIC_OUTS_B10_1", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTXE2_IMUX31_1", - "VBRK_EXT_IMUX31" - ], - [ - "GTXE2_LOGIC_OUTS_B2_1", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTXE2_BYP0_1", + "R_TERM_INT_GTX_BYP0", "VBRK_EXT_BYP0" ], [ - "GTXE2_IMUX27_1", - "VBRK_EXT_IMUX27" + "R_TERM_INT_GTX_BYP1", + "VBRK_EXT_BYP1" ], [ - "GTXE2_IMUX11_1", + "R_TERM_INT_GTX_BYP2", + "VBRK_EXT_BYP2" + ], + [ + "R_TERM_INT_GTX_BYP3", + "VBRK_EXT_BYP3" + ], + [ + "R_TERM_INT_GTX_BYP4", + "VBRK_EXT_BYP4" + ], + [ + "R_TERM_INT_GTX_BYP5", + "VBRK_EXT_BYP5" + ], + [ + "R_TERM_INT_GTX_BYP6", + "VBRK_EXT_BYP6" + ], + [ + "R_TERM_INT_GTX_BYP7", + "VBRK_EXT_BYP7" + ], + [ + "R_TERM_INT_GTX_CLK0", + "VBRK_EXT_CLK0" + ], + [ + "R_TERM_INT_GTX_CLK1", + "VBRK_EXT_CLK1" + ], + [ + "R_TERM_INT_GTX_CTRL0", + "VBRK_EXT_CTRL0" + ], + [ + "R_TERM_INT_GTX_CTRL1", + "VBRK_EXT_CTRL1" + ], + [ + "R_TERM_INT_GTX_FAN0", + "VBRK_EXT_FAN0" + ], + [ + "R_TERM_INT_GTX_FAN1", + "VBRK_EXT_FAN1" + ], + [ + "R_TERM_INT_GTX_FAN2", + "VBRK_EXT_FAN2" + ], + [ + "R_TERM_INT_GTX_FAN3", + "VBRK_EXT_FAN3" + ], + [ + "R_TERM_INT_GTX_FAN4", + "VBRK_EXT_FAN4" + ], + [ + "R_TERM_INT_GTX_FAN5", + "VBRK_EXT_FAN5" + ], + [ + "R_TERM_INT_GTX_FAN6", + "VBRK_EXT_FAN6" + ], + [ + "R_TERM_INT_GTX_FAN7", + "VBRK_EXT_FAN7" + ], + [ + "R_TERM_INT_GTX_IMUX0", + "VBRK_EXT_IMUX0" + ], + [ + "R_TERM_INT_GTX_IMUX1", + "VBRK_EXT_IMUX1" + ], + [ + "R_TERM_INT_GTX_IMUX2", + "VBRK_EXT_IMUX2" + ], + [ + "R_TERM_INT_GTX_IMUX3", + "VBRK_EXT_IMUX3" + ], + [ + "R_TERM_INT_GTX_IMUX4", + "VBRK_EXT_IMUX4" + ], + [ + "R_TERM_INT_GTX_IMUX5", + "VBRK_EXT_IMUX5" + ], + [ + "R_TERM_INT_GTX_IMUX6", + "VBRK_EXT_IMUX6" + ], + [ + "R_TERM_INT_GTX_IMUX7", + "VBRK_EXT_IMUX7" + ], + [ + "R_TERM_INT_GTX_IMUX8", + "VBRK_EXT_IMUX8" + ], + [ + "R_TERM_INT_GTX_IMUX9", + "VBRK_EXT_IMUX9" + ], + [ + "R_TERM_INT_GTX_IMUX10", + "VBRK_EXT_IMUX10" + ], + [ + "R_TERM_INT_GTX_IMUX11", "VBRK_EXT_IMUX11" ], [ - "GTXE2_IMUX12_1", + "R_TERM_INT_GTX_IMUX12", "VBRK_EXT_IMUX12" ], [ - "GTXE2_IMUX44_1", + "R_TERM_INT_GTX_IMUX13", + "VBRK_EXT_IMUX13" + ], + [ + "R_TERM_INT_GTX_IMUX14", + "VBRK_EXT_IMUX14" + ], + [ + "R_TERM_INT_GTX_IMUX15", + "VBRK_EXT_IMUX15" + ], + [ + "R_TERM_INT_GTX_IMUX16", + "VBRK_EXT_IMUX16" + ], + [ + "R_TERM_INT_GTX_IMUX17", + "VBRK_EXT_IMUX17" + ], + [ + "R_TERM_INT_GTX_IMUX18", + "VBRK_EXT_IMUX18" + ], + [ + "R_TERM_INT_GTX_IMUX19", + "VBRK_EXT_IMUX19" + ], + [ + "R_TERM_INT_GTX_IMUX20", + "VBRK_EXT_IMUX20" + ], + [ + "R_TERM_INT_GTX_IMUX21", + "VBRK_EXT_IMUX21" + ], + [ + "R_TERM_INT_GTX_IMUX22", + "VBRK_EXT_IMUX22" + ], + [ + "R_TERM_INT_GTX_IMUX23", + "VBRK_EXT_IMUX23" + ], + [ + "R_TERM_INT_GTX_IMUX24", + "VBRK_EXT_IMUX24" + ], + [ + "R_TERM_INT_GTX_IMUX25", + "VBRK_EXT_IMUX25" + ], + [ + "R_TERM_INT_GTX_IMUX26", + "VBRK_EXT_IMUX26" + ], + [ + "R_TERM_INT_GTX_IMUX27", + "VBRK_EXT_IMUX27" + ], + [ + "R_TERM_INT_GTX_IMUX28", + "VBRK_EXT_IMUX28" + ], + [ + "R_TERM_INT_GTX_IMUX29", + "VBRK_EXT_IMUX29" + ], + [ + "R_TERM_INT_GTX_IMUX30", + "VBRK_EXT_IMUX30" + ], + [ + "R_TERM_INT_GTX_IMUX31", + "VBRK_EXT_IMUX31" + ], + [ + "R_TERM_INT_GTX_IMUX32", + "VBRK_EXT_IMUX32" + ], + [ + "R_TERM_INT_GTX_IMUX33", + "VBRK_EXT_IMUX33" + ], + [ + "R_TERM_INT_GTX_IMUX34", + "VBRK_EXT_IMUX34" + ], + [ + "R_TERM_INT_GTX_IMUX35", + "VBRK_EXT_IMUX35" + ], + [ + "R_TERM_INT_GTX_IMUX36", + "VBRK_EXT_IMUX36" + ], + [ + "R_TERM_INT_GTX_IMUX37", + "VBRK_EXT_IMUX37" + ], + [ + "R_TERM_INT_GTX_IMUX38", + "VBRK_EXT_IMUX38" + ], + [ + "R_TERM_INT_GTX_IMUX39", + "VBRK_EXT_IMUX39" + ], + [ + "R_TERM_INT_GTX_IMUX40", + "VBRK_EXT_IMUX40" + ], + [ + "R_TERM_INT_GTX_IMUX41", + "VBRK_EXT_IMUX41" + ], + [ + "R_TERM_INT_GTX_IMUX42", + "VBRK_EXT_IMUX42" + ], + [ + "R_TERM_INT_GTX_IMUX43", + "VBRK_EXT_IMUX43" + ], + [ + "R_TERM_INT_GTX_IMUX44", "VBRK_EXT_IMUX44" ], [ - "GTXE2_IMUX9_1", - "VBRK_EXT_IMUX9" - ] - ] - }, - { - "grid_deltas": [ - -1, - -2 - ], - "tile_types": [ - "DSP_L", - "VBRK" - ], - "wire_pairs": [ - [ - "DSP_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "DSP_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "DSP_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "DSP_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "DSP_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "DSP_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "DSP_LH7_2", - "VBRK_LH7" - ], - [ - "DSP_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "DSP_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "DSP_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "DSP_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "DSP_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "DSP_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "DSP_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "DSP_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "DSP_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "DSP_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "DSP_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "DSP_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "DSP_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "DSP_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "DSP_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "DSP_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "DSP_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "DSP_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "DSP_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "DSP_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "DSP_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "DSP_LH6_2", - "VBRK_LH6" - ], - [ - "DSP_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "DSP_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "DSP_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "DSP_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "DSP_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "DSP_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "DSP_LH5_2", - "VBRK_LH5" - ], - [ - "DSP_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "DSP_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "DSP_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "DSP_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "DSP_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "DSP_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "DSP_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "DSP_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "DSP_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "DSP_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "DSP_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "DSP_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "DSP_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "DSP_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "DSP_LH11_2", - "VBRK_LH11" - ], - [ - "DSP_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "DSP_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "DSP_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "DSP_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "DSP_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "DSP_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "DSP_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "DSP_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "DSP_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "DSP_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "DSP_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "DSP_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "DSP_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "DSP_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "DSP_LH3_2", - "VBRK_LH3" - ], - [ - "DSP_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "DSP_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "DSP_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "DSP_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "DSP_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "DSP_LH2_2", - "VBRK_LH2" - ], - [ - "DSP_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "DSP_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "DSP_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "DSP_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "DSP_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "DSP_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "DSP_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "DSP_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "DSP_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "DSP_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "DSP_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "DSP_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "DSP_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "DSP_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "DSP_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "DSP_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "DSP_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "DSP_LH12_2", - "VBRK_LH12" - ], - [ - "DSP_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "DSP_LH10_2", - "VBRK_LH10" - ], - [ - "DSP_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "DSP_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "DSP_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "DSP_LH4_2", - "VBRK_LH4" - ], - [ - "DSP_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "DSP_LH1_2", - "VBRK_LH1" - ], - [ - "DSP_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "DSP_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "DSP_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "DSP_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "DSP_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "DSP_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "DSP_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "DSP_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "DSP_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "DSP_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "DSP_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "DSP_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "DSP_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "DSP_LH9_2", - "VBRK_LH9" - ], - [ - "DSP_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "DSP_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "DSP_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "DSP_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "DSP_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "DSP_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "DSP_LH8_2", - "VBRK_LH8" - ], - [ - "DSP_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "DSP_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "DSP_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "DSP_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "DSP_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "DSP_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "DSP_SE4C2_2", - "VBRK_SE4C2" - ] - ] - }, - { - "grid_deltas": [ - 0, - -4 - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "CLK_FEED" - ], - "wire_pairs": [ - [ - "CLK_BUFG_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_BUFG_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_BUFG_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_BUFG_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_BUFG_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_BUFG_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_BUFG_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_BUFG_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_BUFG_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_BUFG_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_BUFG_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_BUFG_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_BUFG_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_BUFG_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_BUFG_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_BUFG_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_BUFG_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_BUFG_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_BUFG_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_BUFG_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_BUFG_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_BUFG_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_BUFG_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_BUFG_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_BUFG_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_BUFG_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_BUFG_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_BUFG_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_BUFG_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_BUFG_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_BUFG_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_BUFG_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_BUFG_TOP_R_CK_MUXED28", - "CLK_FEED_R_CK_BUFG_CASC28" - ] - ] - }, - { - "grid_deltas": [ - 1, - 3 - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "wire_pairs": [ - [ - "CLK_HROW_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - 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"VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_HROW_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_HROW_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_HROW_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_LH1_1", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_HROW_LH6_1", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_HROW_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_HROW_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NE4BEG3_1", - "VBRK_NE4BEG3" - ] - ] - }, - { - "grid_deltas": [ - -1, - 2 - ], - "tile_types": [ - "BRAM_INT_INTERFACE_L", - "BRAM_L" - ], - "wire_pairs": [ - [ - "INT_INTERFACE_BYP6", - "BRAM_BYP6_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "BRAM_LOGIC_OUTS_B18_2" - ], - [ - "INT_INTERFACE_SE4BEG0", - "BRAM_SE4BEG0_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX26", - "BRAM_IMUX26_UTURN_2" - ], - [ - "INT_INTERFACE_WR1END1", - "BRAM_WR1END1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "BRAM_IMUX10_UTURN_2" - ], - [ - "INT_INTERFACE_SE4C1", - "BRAM_SE4C1_2" - ], - [ - "INT_INTERFACE_EE4BEG3", - "BRAM_EE4BEG3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX42", - "BRAM_IMUX42_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX29", - "BRAM_IMUX29_2" - ], - [ - "INT_INTERFACE_SE4C3", - "BRAM_SE4C3_2" - ], - [ - "INT_INTERFACE_SE4BEG1", - "BRAM_SE4BEG1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX23", - "BRAM_IMUX23_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX6", - "BRAM_IMUX6_UTURN_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "BRAM_LOGIC_OUTS_B19_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX9", - "BRAM_IMUX9_UTURN_2" - ], - [ - "INT_INTERFACE_LH12", - "BRAM_LH12_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX16", - "BRAM_IMUX16_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "BRAM_IMUX32_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "BRAM_LOGIC_OUTS_B17_2" - ], - [ - "INT_INTERFACE_ER1BEG0", - "BRAM_ER1BEG0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "BRAM_LOGIC_OUTS_B13_2" - ], - [ - "INT_INTERFACE_FAN4", - "BRAM_FAN4_2" - ], - [ - "INT_INTERFACE_EE4B1", - "BRAM_EE4B1_2" - ], - [ - "INT_INTERFACE_LH3", - "BRAM_LH3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX41", - "BRAM_IMUX41_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_2" - ], - [ - "INT_INTERFACE_NE2A3", - "BRAM_NE2A3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "BRAM_IMUX1_2" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_2" - ], - [ - "INT_INTERFACE_EE4A2", - "BRAM_EE4A2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_2" - ], - [ - "INT_INTERFACE_WW4END3", - "BRAM_WW4END3_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "BRAM_LOGIC_OUTS_B1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX9", - "BRAM_IMUX9_2" - ], - [ - "INT_INTERFACE_WW4END2", - "BRAM_WW4END2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - "BRAM_IMUX47_2" - ], - [ - "INT_INTERFACE_FAN2", - "BRAM_FAN2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "BRAM_LOGIC_OUTS_B11_2" - ], - [ - "INT_INTERFACE_NW2A1", - "BRAM_NW2A1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "BRAM_IMUX25_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX0", - "BRAM_IMUX0_UTURN_2" - ], - [ - "INT_INTERFACE_SW4A2", - "BRAM_SW4A2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX11", - "BRAM_IMUX11_2" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_2" - ], - [ - "INT_INTERFACE_SE2A3", - "BRAM_SE2A3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "BRAM_IMUX38_2" - ], - [ - "INT_INTERFACE_BYP5", - "BRAM_BYP5_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_2" - ], - [ - "INT_INTERFACE_EE2BEG2", - "BRAM_EE2BEG2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "BRAM_LOGIC_OUTS_B22_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX13", - "BRAM_IMUX13_UTURN_2" - ], - [ - "INT_INTERFACE_SE4BEG3", - "BRAM_SE4BEG3_2" - ], - [ - "INT_INTERFACE_EE2A3", - "BRAM_EE2A3_2" - ], - [ - "INT_INTERFACE_ER1BEG1", - "BRAM_ER1BEG1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX23", - "BRAM_IMUX23_UTURN_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "BRAM_LOGIC_OUTS_B9_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "BRAM_LOGIC_OUTS_B20_2" - ], - [ - "INT_INTERFACE_SW4A3", - "BRAM_SW4A3_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX0", - "BRAM_IMUX0_2" - ], - [ - "INT_INTERFACE_EE2A1", - "BRAM_EE2A1_2" - ], - [ - "INT_INTERFACE_SW4A1", - "BRAM_SW4A1_2" - ], - [ - "INT_INTERFACE_EL1BEG1", - "BRAM_EL1BEG1_2" - ], - [ - "INT_INTERFACE_LH1", - "BRAM_LH1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX34", - "BRAM_IMUX34_UTURN_2" - ], - [ - "INT_INTERFACE_SE2A1", - "BRAM_SE2A1_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "BRAM_LOGIC_OUTS_B23_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "BRAM_LOGIC_OUTS_B7_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX16", - "BRAM_IMUX16_UTURN_2" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_2" - ], - [ - "INT_INTERFACE_NE4BEG1", - "BRAM_NE4BEG1_2" - ], - [ - "INT_INTERFACE_EE4BEG1", - "BRAM_EE4BEG1_2" - ], - [ - "INT_INTERFACE_LH7", - "BRAM_LH7_2" - ], - [ - "INT_INTERFACE_FAN6", - "BRAM_FAN6_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX46", - "BRAM_IMUX46_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX45", - "BRAM_IMUX45_2" - ], - [ - "INT_INTERFACE_LH2", - "BRAM_LH2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "BRAM_LOGIC_OUTS_B12_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "BRAM_LOGIC_OUTS_B3_2" - ], - [ - "INT_INTERFACE_SW2A2", - "BRAM_SW2A2_2" - ], - [ - "INT_INTERFACE_EL1BEG2", - "BRAM_EL1BEG2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "BRAM_LOGIC_OUTS_B6_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX33", - "BRAM_IMUX33_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "BRAM_IMUX17_2" - ], - [ - "INT_INTERFACE_NW4END2", - "BRAM_NW4END2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX14", - "BRAM_IMUX14_UTURN_2" - ], - [ - "INT_INTERFACE_WW4A1", - "BRAM_WW4A1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX8", - "BRAM_IMUX8_UTURN_2" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_2" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_2" - ], - [ - "INT_INTERFACE_SE2A0", - "BRAM_SE2A0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "BRAM_IMUX31_2" - ], - [ - "INT_INTERFACE_SE4C0", - "BRAM_SE4C0_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX29", - "BRAM_IMUX29_UTURN_2" - ], - [ - "INT_INTERFACE_WR1END3", - "BRAM_WR1END3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX5", - "BRAM_IMUX5_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX15", - "BRAM_IMUX15_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX7", - "BRAM_IMUX7_2" - ], - [ - "INT_INTERFACE_FAN0", - "BRAM_FAN0_2" - ], - [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_2" - ], - [ - "INT_INTERFACE_SW4END1", - "BRAM_SW4END1_2" - ], - [ - "INT_INTERFACE_EE2A0", - "BRAM_EE2A0_2" - ], - [ - "INT_INTERFACE_WW4C1", - "BRAM_WW4C1_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "BRAM_LOGIC_OUTS_B15_2" - ], - [ - "INT_INTERFACE_EE2A2", - "BRAM_EE2A2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "BRAM_IMUX8_2" - ], - [ - "INT_INTERFACE_EE4BEG0", - "BRAM_EE4BEG0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_2" - ], - [ - "INT_INTERFACE_WL1END0", - "BRAM_WL1END0_2" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_2" - ], - [ - "INT_INTERFACE_NW2A3", - "BRAM_NW2A3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX22", - "BRAM_IMUX22_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX17", - "BRAM_IMUX17_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX30", - 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"CFG_CENTER_NW2A2_16", - "INT_FEEDTHRU_2_NW2A2" - ], - [ - "CFG_CENTER_WW4A2_16", - "INT_FEEDTHRU_2_WW4A2" - ], - [ - "CFG_CENTER_NE2A2_16", - "INT_FEEDTHRU_2_NE2A2" + "R_TERM_INT_GTX_IMUX45", + "VBRK_EXT_IMUX45" ], [ - "CFG_CENTER_LH8_16", - "INT_FEEDTHRU_2_LH8" + "R_TERM_INT_GTX_IMUX46", + "VBRK_EXT_IMUX46" ], [ - "CFG_CENTER_SW4END1_16", - "INT_FEEDTHRU_2_SW4END1" + "R_TERM_INT_GTX_IMUX47", + "VBRK_EXT_IMUX47" ], [ - "CFG_CENTER_SW2A0_16", - "INT_FEEDTHRU_2_SW2A0" + "R_TERM_INT_GTX_LOGIC_OUTS_B0", + "VBRK_EXT_LOGIC_OUTS_B0" ], [ - "CFG_CENTER_WW2END3_16", - "INT_FEEDTHRU_2_WW2END3" + "R_TERM_INT_GTX_LOGIC_OUTS_B1", + "VBRK_EXT_LOGIC_OUTS_B1" ], [ - "CFG_CENTER_WR1END1_16", - "INT_FEEDTHRU_2_WR1END1" + "R_TERM_INT_GTX_LOGIC_OUTS_B2", + "VBRK_EXT_LOGIC_OUTS_B2" ], [ - "CFG_CENTER_NE4BEG1_16", - "INT_FEEDTHRU_2_NE4BEG1" + "R_TERM_INT_GTX_LOGIC_OUTS_B3", + "VBRK_EXT_LOGIC_OUTS_B3" ], [ - "CFG_CENTER_LH2_16", - "INT_FEEDTHRU_2_LH2" + "R_TERM_INT_GTX_LOGIC_OUTS_B4", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "CFG_CENTER_WR1END3_16", - "INT_FEEDTHRU_2_WR1END3" + "R_TERM_INT_GTX_LOGIC_OUTS_B5", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "CFG_CENTER_NE4C2_16", - "INT_FEEDTHRU_2_NE4C2" + "R_TERM_INT_GTX_LOGIC_OUTS_B6", + "VBRK_EXT_LOGIC_OUTS_B6" ], [ - "CFG_CENTER_WW4A1_16", - "INT_FEEDTHRU_2_WW4A1" + "R_TERM_INT_GTX_LOGIC_OUTS_B7", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "CFG_CENTER_SE2A0_16", - "INT_FEEDTHRU_2_SE2A0" + "R_TERM_INT_GTX_LOGIC_OUTS_B8", + "VBRK_EXT_LOGIC_OUTS_B8" ], [ - "CFG_CENTER_EE4BEG2_16", - "INT_FEEDTHRU_2_EE4BEG2" + "R_TERM_INT_GTX_LOGIC_OUTS_B9", + "VBRK_EXT_LOGIC_OUTS_B9" ], [ - "CFG_CENTER_NW4A0_16", - "INT_FEEDTHRU_2_NW4A0" + "R_TERM_INT_GTX_LOGIC_OUTS_B10", + "VBRK_EXT_LOGIC_OUTS_B10" ], [ - "CFG_CENTER_WW4B3_16", - "INT_FEEDTHRU_2_WW4B3" + "R_TERM_INT_GTX_LOGIC_OUTS_B11", + "VBRK_EXT_LOGIC_OUTS_B11" ], [ - "CFG_CENTER_ER1BEG0_16", - "INT_FEEDTHRU_2_ER1BEG0" + "R_TERM_INT_GTX_LOGIC_OUTS_B12", + "VBRK_EXT_LOGIC_OUTS_B12" ], [ - "CFG_CENTER_SW4A3_16", - "INT_FEEDTHRU_2_SW4A3" + "R_TERM_INT_GTX_LOGIC_OUTS_B13", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "CFG_CENTER_NE4C1_16", - "INT_FEEDTHRU_2_NE4C1" + "R_TERM_INT_GTX_LOGIC_OUTS_B14", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ - "CFG_CENTER_NE4BEG2_16", - "INT_FEEDTHRU_2_NE4BEG2" + "R_TERM_INT_GTX_LOGIC_OUTS_B15", + "VBRK_EXT_LOGIC_OUTS_B15" ], [ - "CFG_CENTER_LH6_16", - "INT_FEEDTHRU_2_LH6" + "R_TERM_INT_GTX_LOGIC_OUTS_B16", + "VBRK_EXT_LOGIC_OUTS_B16" ], [ - "CFG_CENTER_WW2A1_16", - "INT_FEEDTHRU_2_WW2A1" + "R_TERM_INT_GTX_LOGIC_OUTS_B17", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "CFG_CENTER_EL1BEG2_16", - "INT_FEEDTHRU_2_EL1BEG2" + "R_TERM_INT_GTX_LOGIC_OUTS_B18", + "VBRK_EXT_LOGIC_OUTS_B18" ], [ - "CFG_CENTER_SE4C3_16", - "INT_FEEDTHRU_2_SE4C3" + "R_TERM_INT_GTX_LOGIC_OUTS_B19", + "VBRK_EXT_LOGIC_OUTS_B19" ], [ - "CFG_CENTER_EE4C0_16", - "INT_FEEDTHRU_2_EE4C0" + "R_TERM_INT_GTX_LOGIC_OUTS_B20", + "VBRK_EXT_LOGIC_OUTS_B20" ], [ - "CFG_CENTER_ER1BEG2_16", - "INT_FEEDTHRU_2_ER1BEG2" + "R_TERM_INT_GTX_LOGIC_OUTS_B21", + "VBRK_EXT_LOGIC_OUTS_B21" ], [ - "CFG_CENTER_WL1END2_16", - "INT_FEEDTHRU_2_WL1END2" + "R_TERM_INT_GTX_LOGIC_OUTS_B22", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "CFG_CENTER_WR1END2_16", - "INT_FEEDTHRU_2_WR1END2" + "R_TERM_INT_GTX_LOGIC_OUTS_B23", + "VBRK_EXT_LOGIC_OUTS_B23" ] ] }