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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY2"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY20"
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                "res": "0.000"
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                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY23"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT24",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY24"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY25->PCIE_INT_INTERFACE_IMUX_OUT25": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT25",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY25"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY26->PCIE_INT_INTERFACE_IMUX_OUT26": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT26",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY26"
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        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY27->PCIE_INT_INTERFACE_IMUX_OUT27": {
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            "dst_to_src": {
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                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT27",
            "is_directional": "1",
            "is_pass_transistor": 1,
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            "src_to_dst": {
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                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY27"
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        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY28->PCIE_INT_INTERFACE_IMUX_OUT28": {
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            "dst_to_src": {
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                "res": "0.000"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT28",
            "is_directional": "1",
            "is_pass_transistor": 1,
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                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY28"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY29->PCIE_INT_INTERFACE_IMUX_OUT29": {
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            "dst_to_src": {
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                "res": "0.000"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT29",
            "is_directional": "1",
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            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY29"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY3->PCIE_INT_INTERFACE_IMUX_OUT3": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY3"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY30->PCIE_INT_INTERFACE_IMUX_OUT30": {
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            "dst_to_src": {
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                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT30",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY30"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY31->PCIE_INT_INTERFACE_IMUX_OUT31": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT31",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY31"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY32->PCIE_INT_INTERFACE_IMUX_OUT32": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT32",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY32"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY33->PCIE_INT_INTERFACE_IMUX_OUT33": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT33",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY33"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY34->PCIE_INT_INTERFACE_IMUX_OUT34": {
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            "dst_to_src": {
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                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT34",
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            "is_pass_transistor": 1,
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            "src_to_dst": {
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY34"
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                "res": "0.000"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT35",
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            "src_to_dst": {
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY35"
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        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY36->PCIE_INT_INTERFACE_IMUX_OUT36": {
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                "res": "0.000"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT36",
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            "is_pass_transistor": 1,
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            "src_to_dst": {
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY36"
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        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY37->PCIE_INT_INTERFACE_IMUX_OUT37": {
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            "dst_to_src": {
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                "res": "0.000"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT37",
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            "is_pass_transistor": 1,
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            "src_to_dst": {
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY37"
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        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY38->PCIE_INT_INTERFACE_IMUX_OUT38": {
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            "dst_to_src": {
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            "src_to_dst": {
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY38"
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        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY39->PCIE_INT_INTERFACE_IMUX_OUT39": {
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            "dst_to_src": {
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT39",
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                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY39"
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            "dst_to_src": {
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                "res": "0.000"
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT4",
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                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY4"
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            "dst_to_src": {
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            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT40",
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY40"
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            "dst_to_src": {
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                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT41",
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                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY41"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY42->PCIE_INT_INTERFACE_IMUX_OUT42": {
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            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT42",
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                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY42"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY43->PCIE_INT_INTERFACE_IMUX_OUT43": {
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            "dst_to_src": {
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                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT43",
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            "is_pass_transistor": 1,
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            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY43"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY44->PCIE_INT_INTERFACE_IMUX_OUT44": {
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            "dst_to_src": {
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                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT44",
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            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY44"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY45->PCIE_INT_INTERFACE_IMUX_OUT45": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT45",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY45"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY46->PCIE_INT_INTERFACE_IMUX_OUT46": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT46",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY46"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY47->PCIE_INT_INTERFACE_IMUX_OUT47": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT47",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY47"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY5->PCIE_INT_INTERFACE_IMUX_OUT5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY5"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY6->PCIE_INT_INTERFACE_IMUX_OUT6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY6"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY7->PCIE_INT_INTERFACE_IMUX_OUT7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY7"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY8->PCIE_INT_INTERFACE_IMUX_OUT8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY8"
        },
        "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY9->PCIE_INT_INTERFACE_IMUX_OUT9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY9"
        }
    },
    "sites": [],
    "tile_type": "PCIE_INT_INTERFACE_R",
    "wires": {
        "INT_INTERFACE_BLOCK_OUTS_B0": null,
        "INT_INTERFACE_BLOCK_OUTS_B1": null,
        "INT_INTERFACE_BLOCK_OUTS_B2": null,
        "INT_INTERFACE_BLOCK_OUTS_B3": null,
        "INT_INTERFACE_BYP0": null,
        "INT_INTERFACE_BYP1": null,
        "INT_INTERFACE_BYP2": null,
        "INT_INTERFACE_BYP3": null,
        "INT_INTERFACE_BYP4": null,
        "INT_INTERFACE_BYP5": null,
        "INT_INTERFACE_BYP6": null,
        "INT_INTERFACE_BYP7": null,
        "INT_INTERFACE_CLK0": null,
        "INT_INTERFACE_CLK1": null,
        "INT_INTERFACE_CTRL0": null,
        "INT_INTERFACE_CTRL1": null,
        "INT_INTERFACE_EE2A0": null,
        "INT_INTERFACE_EE2A1": null,
        "INT_INTERFACE_EE2A2": null,
        "INT_INTERFACE_EE2A3": null,
        "INT_INTERFACE_EE2BEG0": null,
        "INT_INTERFACE_EE2BEG1": null,
        "INT_INTERFACE_EE2BEG2": null,
        "INT_INTERFACE_EE2BEG3": null,
        "INT_INTERFACE_EE4A0": null,
        "INT_INTERFACE_EE4A1": null,
        "INT_INTERFACE_EE4A2": null,
        "INT_INTERFACE_EE4A3": null,
        "INT_INTERFACE_EE4B0": null,
        "INT_INTERFACE_EE4B1": null,
        "INT_INTERFACE_EE4B2": null,
        "INT_INTERFACE_EE4B3": null,
        "INT_INTERFACE_EE4BEG0": null,
        "INT_INTERFACE_EE4BEG1": null,
        "INT_INTERFACE_EE4BEG2": null,
        "INT_INTERFACE_EE4BEG3": null,
        "INT_INTERFACE_EE4C0": null,
        "INT_INTERFACE_EE4C1": null,
        "INT_INTERFACE_EE4C2": null,
        "INT_INTERFACE_EE4C3": null,
        "INT_INTERFACE_EL1BEG0": null,
        "INT_INTERFACE_EL1BEG1": null,
        "INT_INTERFACE_EL1BEG2": null,
        "INT_INTERFACE_EL1BEG3": null,
        "INT_INTERFACE_ER1BEG0": null,
        "INT_INTERFACE_ER1BEG1": null,
        "INT_INTERFACE_ER1BEG2": null,
        "INT_INTERFACE_ER1BEG3": null,
        "INT_INTERFACE_FAN0": null,
        "INT_INTERFACE_FAN1": null,
        "INT_INTERFACE_FAN2": null,
        "INT_INTERFACE_FAN3": null,
        "INT_INTERFACE_FAN4": null,
        "INT_INTERFACE_FAN5": null,
        "INT_INTERFACE_FAN6": null,
        "INT_INTERFACE_FAN7": null,
        "INT_INTERFACE_LH1": null,
        "INT_INTERFACE_LH10": null,
        "INT_INTERFACE_LH11": null,
        "INT_INTERFACE_LH12": null,
        "INT_INTERFACE_LH2": null,
        "INT_INTERFACE_LH3": null,
        "INT_INTERFACE_LH4": null,
        "INT_INTERFACE_LH5": null,
        "INT_INTERFACE_LH6": null,
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}
