{
    "pips": {
        "GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B8_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B8_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_CPLLFBCLKLOST"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLLOCK->GTXE2_LOGIC_OUTS_B14_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B14_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_CPLLLOCK"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B18_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B18_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_CPLLREFCLKLOST"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT0->GTXE2_LOGIC_OUTS_B9_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DMONITOROUT0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT1->GTXE2_LOGIC_OUTS_B9_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DMONITOROUT1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT2->GTXE2_LOGIC_OUTS_B9_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DMONITOROUT2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT3->GTXE2_LOGIC_OUTS_B9_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DMONITOROUT3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT4->GTXE2_LOGIC_OUTS_B9_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DMONITOROUT4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT5->GTXE2_LOGIC_OUTS_B9_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DMONITOROUT5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT6->GTXE2_LOGIC_OUTS_B9_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DMONITOROUT6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT7->GTXE2_LOGIC_OUTS_B9_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DMONITOROUT7"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO0->GTXE2_LOGIC_OUTS_B0_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO1->GTXE2_LOGIC_OUTS_B4_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO10->GTXE2_LOGIC_OUTS_B2_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO10"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO11->GTXE2_LOGIC_OUTS_B6_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO11"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO12->GTXE2_LOGIC_OUTS_B5_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO12"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO13->GTXE2_LOGIC_OUTS_B1_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO13"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO14->GTXE2_LOGIC_OUTS_B7_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO14"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO15->GTXE2_LOGIC_OUTS_B3_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO15"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO2->GTXE2_LOGIC_OUTS_B2_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO3->GTXE2_LOGIC_OUTS_B6_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO4->GTXE2_LOGIC_OUTS_B5_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO5->GTXE2_LOGIC_OUTS_B1_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO6->GTXE2_LOGIC_OUTS_B7_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO7->GTXE2_LOGIC_OUTS_B3_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO7"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO8->GTXE2_LOGIC_OUTS_B0_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO8"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO9->GTXE2_LOGIC_OUTS_B4_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPDO9"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPRDY->GTXE2_LOGIC_OUTS_B20_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B20_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_DRPRDY"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_EYESCANDATAERROR->GTXE2_LOGIC_OUTS_B20_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B20_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_EYESCANDATAERROR"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_GTREFCLKMONITOR->GTXE2_LOGIC_OUTS_B23_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B23_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_GTREFCLKMONITOR"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_GTRXOUTCLK_0->GTXE2_CHANNEL_RXOUTCLK_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXOUTCLK_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_GTRXOUTCLK_0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_GTTXOUTCLK_0->GTXE2_CHANNEL_TXOUTCLK_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXOUTCLK_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_GTTXOUTCLK_0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_NORTHREFCLK0->GTXE2_CHANNEL_GTNORTHREFCLK0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_NORTHREFCLK0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_NORTHREFCLK1->GTXE2_CHANNEL_GTNORTHREFCLK1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_NORTHREFCLK1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT0->GTXE2_LOGIC_OUTS_B13_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT1->GTXE2_LOGIC_OUTS_B13_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT10->GTXE2_LOGIC_OUTS_B13_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT10"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT11->GTXE2_LOGIC_OUTS_B9_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT11"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT12->GTXE2_LOGIC_OUTS_B9_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT12"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT13->GTXE2_LOGIC_OUTS_B9_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B9_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT13"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT14->GTXE2_LOGIC_OUTS_B16_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT14"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT15->GTXE2_LOGIC_OUTS_B16_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT15"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT2->GTXE2_LOGIC_OUTS_B13_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT3->GTXE2_LOGIC_OUTS_B13_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT4->GTXE2_LOGIC_OUTS_B13_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT5->GTXE2_LOGIC_OUTS_B13_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT6->GTXE2_LOGIC_OUTS_B13_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT7->GTXE2_LOGIC_OUTS_B13_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT7"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT8->GTXE2_LOGIC_OUTS_B13_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT8"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT9->GTXE2_LOGIC_OUTS_B13_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B13_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT9"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_PHYSTATUS->GTXE2_LOGIC_OUTS_B10_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B10_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_PHYSTATUS"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_QPLLCLK->GTXE2_CHANNEL_GTQPLLCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTQPLLCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_QPLLCLK"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_QPLLREFCLK->GTXE2_CHANNEL_GTQPLLREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTQPLLREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_QPLLREFCLK"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_REFCLK0->GTXE2_CHANNEL_GTREFCLK0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTREFCLK0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_REFCLK0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_REFCLK1->GTXE2_CHANNEL_GTREFCLK1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTREFCLK1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_REFCLK1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFSTATUS0->GTXE2_LOGIC_OUTS_B23_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B23_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFSTATUS1->GTXE2_LOGIC_OUTS_B19_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B19_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFSTATUS2->GTXE2_LOGIC_OUTS_B17_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBYTEISALIGNED->GTXE2_LOGIC_OUTS_B18_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B18_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXBYTEISALIGNED"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBYTEREALIGN->GTXE2_LOGIC_OUTS_B10_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B10_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXBYTEREALIGN"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCDRLOCK->GTXE2_LOGIC_OUTS_B17_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCDRLOCK"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHANBONDSEQ->GTXE2_LOGIC_OUTS_B10_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B10_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHANBONDSEQ"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHANISALIGNED->GTXE2_LOGIC_OUTS_B18_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B18_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHANISALIGNED"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHANREALIGN->GTXE2_LOGIC_OUTS_B23_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B23_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHANREALIGN"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA0->GTXE2_LOGIC_OUTS_B15_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B15_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA1->GTXE2_LOGIC_OUTS_B15_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B15_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA2->GTXE2_LOGIC_OUTS_B15_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B15_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA3->GTXE2_LOGIC_OUTS_B15_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B15_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA4->GTXE2_LOGIC_OUTS_B15_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B15_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA5->GTXE2_LOGIC_OUTS_B15_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B15_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA6->GTXE2_LOGIC_OUTS_B15_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B15_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA7->GTXE2_LOGIC_OUTS_B15_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B15_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA7"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK0->GTXE2_LOGIC_OUTS_B12_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B12_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISK0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK1->GTXE2_LOGIC_OUTS_B12_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B12_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISK1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK2->GTXE2_LOGIC_OUTS_B12_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B12_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISK2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK3->GTXE2_LOGIC_OUTS_B12_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B12_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISK3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK4->GTXE2_LOGIC_OUTS_B12_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B12_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISK4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK5->GTXE2_LOGIC_OUTS_B12_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B12_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISK5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK6->GTXE2_LOGIC_OUTS_B12_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B12_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISK6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK7->GTXE2_LOGIC_OUTS_B12_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B12_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHARISK7"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO0->GTXE2_LOGIC_OUTS_B16_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHBONDO0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO1->GTXE2_LOGIC_OUTS_B16_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHBONDO1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO2->GTXE2_LOGIC_OUTS_B16_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHBONDO2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO3->GTXE2_LOGIC_OUTS_B16_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHBONDO3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO4->GTXE2_LOGIC_OUTS_B16_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCHBONDO4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCLKCORCNT0->GTXE2_LOGIC_OUTS_B18_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B18_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCLKCORCNT1->GTXE2_LOGIC_OUTS_B20_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B20_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMINITDET->GTXE2_LOGIC_OUTS_B20_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B20_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCOMINITDET"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMMADET->GTXE2_LOGIC_OUTS_B19_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B19_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCOMMADET"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMSASDET->GTXE2_LOGIC_OUTS_B18_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B18_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCOMSASDET"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMWAKEDET->GTXE2_LOGIC_OUTS_B19_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B19_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXCOMWAKEDET"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA0->GTXE2_LOGIC_OUTS_B6_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA1->GTXE2_LOGIC_OUTS_B2_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA10->GTXE2_LOGIC_OUTS_B4_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA10"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA11->GTXE2_LOGIC_OUTS_B0_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA11"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA12->GTXE2_LOGIC_OUTS_B3_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA12"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA13->GTXE2_LOGIC_OUTS_B7_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA13"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA14->GTXE2_LOGIC_OUTS_B1_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA14"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA15->GTXE2_LOGIC_OUTS_B5_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA15"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA16->GTXE2_LOGIC_OUTS_B6_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA16"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA17->GTXE2_LOGIC_OUTS_B2_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA17"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA18->GTXE2_LOGIC_OUTS_B4_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA18"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA19->GTXE2_LOGIC_OUTS_B0_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA19"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA2->GTXE2_LOGIC_OUTS_B4_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA20->GTXE2_LOGIC_OUTS_B3_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA20"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA21->GTXE2_LOGIC_OUTS_B7_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA21"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA22->GTXE2_LOGIC_OUTS_B1_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA22"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA23->GTXE2_LOGIC_OUTS_B5_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA23"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA24->GTXE2_LOGIC_OUTS_B6_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA24"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA25->GTXE2_LOGIC_OUTS_B2_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA25"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA26->GTXE2_LOGIC_OUTS_B4_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA26"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA27->GTXE2_LOGIC_OUTS_B0_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA27"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA28->GTXE2_LOGIC_OUTS_B3_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA28"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA29->GTXE2_LOGIC_OUTS_B7_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA29"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA3->GTXE2_LOGIC_OUTS_B0_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA30->GTXE2_LOGIC_OUTS_B1_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA30"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA31->GTXE2_LOGIC_OUTS_B5_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA31"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA32->GTXE2_LOGIC_OUTS_B3_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA32"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA33->GTXE2_LOGIC_OUTS_B7_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA33"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA34->GTXE2_LOGIC_OUTS_B1_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA34"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA35->GTXE2_LOGIC_OUTS_B5_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA35"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA36->GTXE2_LOGIC_OUTS_B6_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA36"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA37->GTXE2_LOGIC_OUTS_B2_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA37"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA38->GTXE2_LOGIC_OUTS_B4_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA38"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA39->GTXE2_LOGIC_OUTS_B0_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA39"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA4->GTXE2_LOGIC_OUTS_B3_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA40->GTXE2_LOGIC_OUTS_B3_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA40"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA41->GTXE2_LOGIC_OUTS_B7_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA41"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA42->GTXE2_LOGIC_OUTS_B1_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA42"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA43->GTXE2_LOGIC_OUTS_B5_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA43"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA44->GTXE2_LOGIC_OUTS_B6_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA44"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA45->GTXE2_LOGIC_OUTS_B2_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA45"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA46->GTXE2_LOGIC_OUTS_B4_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA46"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA47->GTXE2_LOGIC_OUTS_B0_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA47"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA48->GTXE2_LOGIC_OUTS_B3_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA48"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA49->GTXE2_LOGIC_OUTS_B7_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA49"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA5->GTXE2_LOGIC_OUTS_B7_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA50->GTXE2_LOGIC_OUTS_B1_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA50"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA51->GTXE2_LOGIC_OUTS_B5_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA51"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA52->GTXE2_LOGIC_OUTS_B6_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA52"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA53->GTXE2_LOGIC_OUTS_B2_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA53"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA54->GTXE2_LOGIC_OUTS_B4_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA54"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA55->GTXE2_LOGIC_OUTS_B0_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA55"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA56->GTXE2_LOGIC_OUTS_B3_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA56"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA57->GTXE2_LOGIC_OUTS_B7_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA57"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA58->GTXE2_LOGIC_OUTS_B1_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA58"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA59->GTXE2_LOGIC_OUTS_B5_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA59"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA6->GTXE2_LOGIC_OUTS_B1_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA60->GTXE2_LOGIC_OUTS_B6_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA60"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA61->GTXE2_LOGIC_OUTS_B2_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA61"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA62->GTXE2_LOGIC_OUTS_B4_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA62"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA63->GTXE2_LOGIC_OUTS_B0_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA63"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA7->GTXE2_LOGIC_OUTS_B5_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA7"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA8->GTXE2_LOGIC_OUTS_B6_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA8"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA9->GTXE2_LOGIC_OUTS_B2_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATA9"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATAVALID->GTXE2_LOGIC_OUTS_B19_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B19_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDATAVALID"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR0->GTXE2_LOGIC_OUTS_B22_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B22_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDISPERR0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR1->GTXE2_LOGIC_OUTS_B22_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B22_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDISPERR1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR2->GTXE2_LOGIC_OUTS_B22_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B22_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDISPERR2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR3->GTXE2_LOGIC_OUTS_B22_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B22_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDISPERR3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR4->GTXE2_LOGIC_OUTS_B22_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B22_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDISPERR4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR5->GTXE2_LOGIC_OUTS_B22_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B22_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDISPERR5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR6->GTXE2_LOGIC_OUTS_B22_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B22_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDISPERR6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR7->GTXE2_LOGIC_OUTS_B22_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B22_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDISPERR7"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B22_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B22_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXDLYSRESETDONE"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXELECIDLE->GTXE2_LOGIC_OUTS_B19_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B19_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXELECIDLE"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADER0->GTXE2_LOGIC_OUTS_B19_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B19_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXHEADER0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADER1->GTXE2_LOGIC_OUTS_B23_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B23_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXHEADER1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADER2->GTXE2_LOGIC_OUTS_B17_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXHEADER2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADERVALID->GTXE2_LOGIC_OUTS_B23_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B23_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXHEADERVALID"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT0->GTXE2_LOGIC_OUTS_B8_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B8_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXMONITOROUT0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT1->GTXE2_LOGIC_OUTS_B8_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B8_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXMONITOROUT1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT2->GTXE2_LOGIC_OUTS_B8_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B8_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXMONITOROUT2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT3->GTXE2_LOGIC_OUTS_B8_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B8_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXMONITOROUT3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT4->GTXE2_LOGIC_OUTS_B8_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B8_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXMONITOROUT4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT5->GTXE2_LOGIC_OUTS_B8_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B8_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXMONITOROUT5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT6->GTXE2_LOGIC_OUTS_B8_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B8_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXMONITOROUT6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE0->GTXE2_LOGIC_OUTS_B14_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B14_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE1->GTXE2_LOGIC_OUTS_B14_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B14_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE2->GTXE2_LOGIC_OUTS_B14_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B14_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE3->GTXE2_LOGIC_OUTS_B14_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B14_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE4->GTXE2_LOGIC_OUTS_B14_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B14_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE5->GTXE2_LOGIC_OUTS_B14_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B14_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE6->GTXE2_LOGIC_OUTS_B14_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B14_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE7->GTXE2_LOGIC_OUTS_B14_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B14_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE7"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXN_PAD->GTXE2_CHANNEL_RXN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXN_PAD"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B17_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLKPCS->GTXE2_LOGIC_OUTS_B21_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B21_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXOUTCLKPCS"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B18_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHALIGNDONE"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR0->GTXE2_LOGIC_OUTS_B5_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B5_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHMONITOR0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR1->GTXE2_LOGIC_OUTS_B1_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B1_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHMONITOR1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR2->GTXE2_LOGIC_OUTS_B7_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B7_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHMONITOR2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR3->GTXE2_LOGIC_OUTS_B3_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B3_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHMONITOR3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR4->GTXE2_LOGIC_OUTS_B21_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B21_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHMONITOR4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR0->GTXE2_LOGIC_OUTS_B0_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B0_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR1->GTXE2_LOGIC_OUTS_B4_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B4_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR2->GTXE2_LOGIC_OUTS_B2_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B2_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR3->GTXE2_LOGIC_OUTS_B6_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B6_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR4->GTXE2_LOGIC_OUTS_B16_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPRBSERR->GTXE2_LOGIC_OUTS_B20_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B20_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXPRBSERR"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXP_PAD->GTXE2_CHANNEL_RXP": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXP",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXP_PAD"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXQPISENN->GTXE2_LOGIC_OUTS_B17_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXQPISENN"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXQPISENP->GTXE2_LOGIC_OUTS_B15_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B15_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXQPISENP"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXRATEDONE->GTXE2_LOGIC_OUTS_B23_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B23_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXRATEDONE"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXRESETDONE->GTXE2_LOGIC_OUTS_B20_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B20_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXRESETDONE"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTARTOFSEQ->GTXE2_LOGIC_OUTS_B18_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B18_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXSTARTOFSEQ"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTATUS0->GTXE2_LOGIC_OUTS_B21_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B21_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXSTATUS0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTATUS1->GTXE2_LOGIC_OUTS_B17_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXSTATUS1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTATUS2->GTXE2_LOGIC_OUTS_B23_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B23_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXSTATUS2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_RXVALID->GTXE2_LOGIC_OUTS_B20_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B20_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_RXVALID"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_SOUTHREFCLK0->GTXE2_CHANNEL_GTSOUTHREFCLK0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_SOUTHREFCLK1->GTXE2_CHANNEL_GTSOUTHREFCLK1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT0->GTXE2_LOGIC_OUTS_B11_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT1->GTXE2_LOGIC_OUTS_B11_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT2->GTXE2_LOGIC_OUTS_B11_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT2"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT3->GTXE2_LOGIC_OUTS_B11_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT3"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT4->GTXE2_LOGIC_OUTS_B11_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT4"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT5->GTXE2_LOGIC_OUTS_B11_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT5"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT6->GTXE2_LOGIC_OUTS_B11_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT6"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT7->GTXE2_LOGIC_OUTS_B11_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT7"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT8->GTXE2_LOGIC_OUTS_B11_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT8"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT9->GTXE2_LOGIC_OUTS_B11_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B11_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TSTOUT9"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXBUFSTATUS0->GTXE2_LOGIC_OUTS_B17_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS0"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXBUFSTATUS1->GTXE2_LOGIC_OUTS_B21_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B21_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS1"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXCOMFINISH->GTXE2_LOGIC_OUTS_B16_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXCOMFINISH"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B17_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXDLYSRESETDONE"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXGEARBOXREADY->GTXE2_LOGIC_OUTS_B23_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B23_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXGEARBOXREADY"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXN->GTXE2_CHANNEL_TXN_PAD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXN_PAD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXN"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B23_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B23_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLKPCS->GTXE2_LOGIC_OUTS_B17_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXOUTCLKPCS"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXP->GTXE2_CHANNEL_TXP_PAD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXP_PAD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXP"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B18_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXPHALIGNDONE"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHINITDONE->GTXE2_LOGIC_OUTS_B17_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B17_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXPHINITDONE"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXQPISENN->GTXE2_LOGIC_OUTS_B20_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B20_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXQPISENN"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXQPISENP->GTXE2_LOGIC_OUTS_B8_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B8_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXQPISENP"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXRATEDONE->GTXE2_LOGIC_OUTS_B20_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B20_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXRATEDONE"
        },
        "GTX_CHANNEL_0.GTXE2_CHANNEL_TXRESETDONE->GTXE2_LOGIC_OUTS_B16_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_LOGIC_OUTS_B16_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CHANNEL_TXRESETDONE"
        },
        "GTX_CHANNEL_0.GTXE2_CLK0_2->GTXE2_CHANNEL_CPLLLOCKDETCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK0_2"
        },
        "GTX_CHANNEL_0.GTXE2_CLK0_4->GTXE2_CHANNEL_TXUSRCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXUSRCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK0_4"
        },
        "GTX_CHANNEL_0.GTXE2_CLK0_5->GTXE2_CHANNEL_TXUSRCLK2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXUSRCLK2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK0_5"
        },
        "GTX_CHANNEL_0.GTXE2_CLK0_6->GTXE2_CHANNEL_RXUSRCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXUSRCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK0_6"
        },
        "GTX_CHANNEL_0.GTXE2_CLK0_7->GTXE2_CHANNEL_RXUSRCLK2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXUSRCLK2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK0_7"
        },
        "GTX_CHANNEL_0.GTXE2_CLK1_1->GTXE2_CHANNEL_DRPCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK1_1"
        },
        "GTX_CHANNEL_0.GTXE2_CLK1_2->GTXE2_CHANNEL_TXPHDLYTSTCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK1_2"
        },
        "GTX_CHANNEL_0.GTXE2_CLK1_4->GTXE2_CHANNEL_CLKRSVD0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CLKRSVD0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK1_4"
        },
        "GTX_CHANNEL_0.GTXE2_CLK1_5->GTXE2_CHANNEL_CLKRSVD1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CLKRSVD1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK1_5"
        },
        "GTX_CHANNEL_0.GTXE2_CLK1_6->GTXE2_CHANNEL_GTGREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTGREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK1_6"
        },
        "GTX_CHANNEL_0.GTXE2_CLK1_7->GTXE2_CHANNEL_CLKRSVD2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CLKRSVD2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK1_7"
        },
        "GTX_CHANNEL_0.GTXE2_CLK1_8->GTXE2_CHANNEL_CLKRSVD3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CLKRSVD3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CLK1_8"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL0_10->GTXE2_CHANNEL_GTRESETSEL": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRESETSEL",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL0_10"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL0_3->GTXE2_CHANNEL_CPLLRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CPLLRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL0_3"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL0_5->GTXE2_CHANNEL_GTTXRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTTXRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL0_5"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL0_6->GTXE2_CHANNEL_RXDLYSRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDLYSRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL0_6"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL0_7->GTXE2_CHANNEL_RXCDRFREQRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCDRFREQRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL0_7"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL0_8->GTXE2_CHANNEL_GTRXRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRXRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL0_8"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL0_9->GTXE2_CHANNEL_RXDFELPMRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFELPMRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL0_9"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL1_1->GTXE2_CHANNEL_RXPHDLYRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPHDLYRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL1_1"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL1_10->GTXE2_CHANNEL_RXOOBRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXOOBRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL1_10"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL1_3->GTXE2_CHANNEL_TXPMARESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPMARESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL1_3"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL1_5->GTXE2_CHANNEL_CFGRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CFGRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL1_5"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL1_6->GTXE2_CHANNEL_RXBUFRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXBUFRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL1_6"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL1_7->GTXE2_CHANNEL_RXPMARESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPMARESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL1_7"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL1_8->GTXE2_CHANNEL_RXCDRRESETRSV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCDRRESETRSV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL1_8"
        },
        "GTX_CHANNEL_0.GTXE2_CTRL1_9->GTXE2_CHANNEL_RXCDRRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCDRRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_CTRL1_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX0_10->GTXE2_CHANNEL_RXELECIDLEMODE0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX0_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX0_2->GTXE2_CHANNEL_TX8B10BEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TX8B10BEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX0_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX0_3->GTXE2_CHANNEL_TXMAINCURSOR3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX0_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX0_5->GTXE2_CHANNEL_TXSEQUENCE3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX0_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX0_6->GTXE2_CHANNEL_PMARSVDIN24": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN24",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX0_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX0_7->GTXE2_CHANNEL_PMARSVDIN23": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN23",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX0_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX0_8->GTXE2_CHANNEL_PMARSVDIN4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX0_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX0_9->GTXE2_CHANNEL_PMARSVDIN3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX0_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX10_0->GTXE2_CHANNEL_TXCHARDISPVAL7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX10_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX10_1->GTXE2_CHANNEL_TXPDELECIDLEMODE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX10_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX10_2->GTXE2_CHANNEL_TXCHARDISPVAL6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX10_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX10_4->GTXE2_CHANNEL_TXCHARDISPVAL5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX10_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX10_5->GTXE2_CHANNEL_TXUSERRDY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXUSERRDY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX10_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX10_6->GTXE2_CHANNEL_TXCHARDISPVAL4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX10_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX10_7->GTXE2_CHANNEL_TXBUFDIFFCTRL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX10_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX10_9->GTXE2_CHANNEL_RXQPIEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXQPIEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX10_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX11_10->GTXE2_CHANNEL_RXLPMLFHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXLPMLFHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX11_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX11_2->GTXE2_CHANNEL_CPLLREFCLKSEL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX11_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX11_5->GTXE2_CHANNEL_TXDLYHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDLYHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX11_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX11_6->GTXE2_CHANNEL_RXRATE2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXRATE2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX11_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX11_8->GTXE2_CHANNEL_RXDFEVSEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEVSEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX11_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX12_1->GTXE2_CHANNEL_TXCOMWAKE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCOMWAKE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX12_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX12_10->GTXE2_CHANNEL_RXDFETAP3OVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX12_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX12_2->GTXE2_CHANNEL_TXHEADER1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXHEADER1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX12_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX12_4->GTXE2_CHANNEL_TXPHOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPHOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX12_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX12_5->GTXE2_CHANNEL_TXDLYOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDLYOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX12_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX12_7->GTXE2_CHANNEL_TXBUFDIFFCTRL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX12_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX12_8->GTXE2_CHANNEL_RXSLIDE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXSLIDE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX12_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX12_9->GTXE2_CHANNEL_RX8B10BEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RX8B10BEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX12_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX13_1->GTXE2_CHANNEL_TXQPISTRONGPDOWN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX13_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX13_10->GTXE2_CHANNEL_RXPRBSCNTRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPRBSCNTRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX13_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX13_2->GTXE2_CHANNEL_TXHEADER0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXHEADER0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX13_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX13_7->GTXE2_CHANNEL_TXBUFDIFFCTRL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX13_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX13_8->GTXE2_CHANNEL_RXOSOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXOSOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX13_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX13_9->GTXE2_CHANNEL_RXDFETAP5OVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX13_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX14_10->GTXE2_CHANNEL_RXPHOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPHOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX14_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX14_2->GTXE2_CHANNEL_CPLLREFCLKSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX14_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX14_5->GTXE2_CHANNEL_TXDLYEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDLYEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX14_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX14_6->GTXE2_CHANNEL_RXRATE1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXRATE1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX14_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX14_7->GTXE2_CHANNEL_RXPCSRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPCSRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX14_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX14_8->GTXE2_CHANNEL_RXCDROVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCDROVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX14_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX14_9->GTXE2_CHANNEL_RXPHALIGN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPHALIGN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX14_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX15_1->GTXE2_CHANNEL_TX8B10BBYPASS3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX15_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX15_2->GTXE2_CHANNEL_CPLLREFCLKSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX15_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX15_3->GTXE2_CHANNEL_TX8B10BBYPASS2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX15_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX15_4->GTXE2_CHANNEL_TXPRBSFORCEERR": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRBSFORCEERR",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX15_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX15_5->GTXE2_CHANNEL_TX8B10BBYPASS1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX15_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX15_6->GTXE2_CHANNEL_RXRATE0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXRATE0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX15_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX15_7->GTXE2_CHANNEL_TX8B10BBYPASS0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX15_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX16_0->GTXE2_CHANNEL_TXDATA28": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA28",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX16_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX16_1->GTXE2_CHANNEL_TXDATA56": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA56",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX16_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX16_10->GTXE2_CHANNEL_RXDFECM1EN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFECM1EN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX16_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX16_2->GTXE2_CHANNEL_TXDATA20": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA20",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX16_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX16_3->GTXE2_CHANNEL_TXDATA48": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA48",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX16_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX16_4->GTXE2_CHANNEL_TXDATA12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX16_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX16_5->GTXE2_CHANNEL_TXDATA40": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA40",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX16_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX16_6->GTXE2_CHANNEL_TXDATA4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX16_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX16_7->GTXE2_CHANNEL_TXDATA35": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA35",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX16_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX17_0->GTXE2_CHANNEL_TXDATA29": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA29",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX17_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX17_1->GTXE2_CHANNEL_TXDATA57": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA57",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX17_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX17_2->GTXE2_CHANNEL_TXDATA21": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA21",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX17_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX17_3->GTXE2_CHANNEL_TXDATA49": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA49",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX17_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX17_4->GTXE2_CHANNEL_TXDATA13": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA13",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX17_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX17_5->GTXE2_CHANNEL_TXDATA41": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA41",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX17_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX17_6->GTXE2_CHANNEL_TXDATA5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX17_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX17_7->GTXE2_CHANNEL_TXDATA34": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA34",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX17_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX17_9->GTXE2_CHANNEL_RXCHBONDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX17_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_0->GTXE2_CHANNEL_TXDATA60": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA60",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_1->GTXE2_CHANNEL_TXDATA24": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA24",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_10->GTXE2_CHANNEL_RXCHBONDLEVEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_2->GTXE2_CHANNEL_TXDATA52": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA52",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_3->GTXE2_CHANNEL_TXDATA16": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA16",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_4->GTXE2_CHANNEL_TXDATA44": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA44",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_5->GTXE2_CHANNEL_TXDATA8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_6->GTXE2_CHANNEL_TXDATA36": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA36",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_7->GTXE2_CHANNEL_TXDATA0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX18_9->GTXE2_CHANNEL_RXCHBONDI0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDI0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX18_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_0->GTXE2_CHANNEL_TXDATA61": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA61",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_1->GTXE2_CHANNEL_TXDATA25": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA25",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_10->GTXE2_CHANNEL_RXCHBONDLEVEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_2->GTXE2_CHANNEL_TXDATA53": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA53",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_3->GTXE2_CHANNEL_TXDATA17": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA17",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_4->GTXE2_CHANNEL_TXDATA45": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA45",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_5->GTXE2_CHANNEL_TXDATA9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_6->GTXE2_CHANNEL_TXDATA37": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA37",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_7->GTXE2_CHANNEL_TXDATA1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_8->GTXE2_CHANNEL_RXDFEVPHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEVPHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX19_9->GTXE2_CHANNEL_RXCHBONDI1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDI1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX19_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX1_10->GTXE2_CHANNEL_RXELECIDLEMODE1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX1_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX1_2->GTXE2_CHANNEL_RXMONITORSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX1_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX1_3->GTXE2_CHANNEL_TXMAINCURSOR2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX1_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX1_4->GTXE2_CHANNEL_TXMAINCURSOR6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX1_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX1_5->GTXE2_CHANNEL_TXSEQUENCE2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX1_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX1_6->GTXE2_CHANNEL_TXSEQUENCE6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX1_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX1_7->GTXE2_CHANNEL_PMARSVDIN22": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN22",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX1_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX1_8->GTXE2_CHANNEL_TXOUTCLKSEL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX1_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX1_9->GTXE2_CHANNEL_PMARSVDIN2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX1_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX20_0->GTXE2_CHANNEL_TXDATA30": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA30",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX20_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX20_1->GTXE2_CHANNEL_TXDATA58": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA58",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX20_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX20_2->GTXE2_CHANNEL_TXDATA22": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA22",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX20_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX20_3->GTXE2_CHANNEL_TXDATA50": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA50",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX20_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX20_4->GTXE2_CHANNEL_TXDATA14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX20_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX20_5->GTXE2_CHANNEL_TXDATA42": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA42",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX20_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX20_6->GTXE2_CHANNEL_TXDATA6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX20_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX20_7->GTXE2_CHANNEL_TXDATA33": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA33",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX20_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_0->GTXE2_CHANNEL_TXDATA31": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA31",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_1->GTXE2_CHANNEL_TXDATA59": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA59",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_10->GTXE2_CHANNEL_RXDFEAGCOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_2->GTXE2_CHANNEL_TXDATA23": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA23",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_3->GTXE2_CHANNEL_TXDATA51": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA51",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_4->GTXE2_CHANNEL_TXDATA15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_5->GTXE2_CHANNEL_TXDATA43": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA43",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_6->GTXE2_CHANNEL_TXDATA7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_7->GTXE2_CHANNEL_TXDATA32": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA32",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_8->GTXE2_CHANNEL_RXDFEXYDOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX21_9->GTXE2_CHANNEL_RXDFETAP4OVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX21_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_0->GTXE2_CHANNEL_TXDATA62": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA62",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_1->GTXE2_CHANNEL_TXDATA26": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA26",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_10->GTXE2_CHANNEL_RXCHBONDLEVEL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_2->GTXE2_CHANNEL_TXDATA54": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA54",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_3->GTXE2_CHANNEL_TXDATA18": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA18",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_4->GTXE2_CHANNEL_TXDATA46": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA46",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_5->GTXE2_CHANNEL_TXDATA10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_6->GTXE2_CHANNEL_TXDATA38": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA38",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_7->GTXE2_CHANNEL_TXDATA2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_8->GTXE2_CHANNEL_RXPRBSSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX22_9->GTXE2_CHANNEL_RXCHBONDI2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDI2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX22_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_0->GTXE2_CHANNEL_TXDATA63": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA63",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_1->GTXE2_CHANNEL_TXDATA27": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA27",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_10->GTXE2_CHANNEL_RXCHBONDI4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDI4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_2->GTXE2_CHANNEL_TXDATA55": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA55",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_3->GTXE2_CHANNEL_TXDATA19": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA19",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_4->GTXE2_CHANNEL_TXDATA47": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA47",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_5->GTXE2_CHANNEL_TXDATA11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_6->GTXE2_CHANNEL_TXDATA39": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA39",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_7->GTXE2_CHANNEL_TXDATA3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDATA3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_8->GTXE2_CHANNEL_RXPRBSSEL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX23_9->GTXE2_CHANNEL_RXCHBONDI3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDI3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX23_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_1->GTXE2_CHANNEL_TSTIN10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_10->GTXE2_CHANNEL_TSTIN19": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN19",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_2->GTXE2_CHANNEL_TSTIN11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_3->GTXE2_CHANNEL_TSTIN12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_4->GTXE2_CHANNEL_TSTIN13": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN13",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_5->GTXE2_CHANNEL_TSTIN14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_6->GTXE2_CHANNEL_TSTIN15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_7->GTXE2_CHANNEL_TSTIN16": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN16",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_8->GTXE2_CHANNEL_TSTIN17": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN17",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX24_9->GTXE2_CHANNEL_TSTIN18": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN18",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX24_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX25_10->GTXE2_CHANNEL_PCSRSVDIN7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX25_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX25_2->GTXE2_CHANNEL_TXPHALIGN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPHALIGN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX25_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX25_3->GTXE2_CHANNEL_PCSRSVDIN0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX25_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX25_4->GTXE2_CHANNEL_PCSRSVDIN1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX25_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX25_5->GTXE2_CHANNEL_PCSRSVDIN2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX25_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX25_6->GTXE2_CHANNEL_PCSRSVDIN3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX25_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX25_7->GTXE2_CHANNEL_PCSRSVDIN4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX25_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX25_8->GTXE2_CHANNEL_PCSRSVDIN5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX25_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX25_9->GTXE2_CHANNEL_PCSRSVDIN6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX25_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX26_10->GTXE2_CHANNEL_GTRSVD15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX26_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX26_3->GTXE2_CHANNEL_GTRSVD8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX26_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX26_4->GTXE2_CHANNEL_GTRSVD9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX26_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX26_5->GTXE2_CHANNEL_GTRSVD10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX26_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX26_6->GTXE2_CHANNEL_GTRSVD11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX26_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX26_7->GTXE2_CHANNEL_GTRSVD12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX26_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX26_8->GTXE2_CHANNEL_GTRSVD13": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD13",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX26_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX26_9->GTXE2_CHANNEL_GTRSVD14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX26_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX27_10->GTXE2_CHANNEL_RXLPMHFOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX27_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX27_5->GTXE2_CHANNEL_TXPHINIT": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPHINIT",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX27_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX27_7->GTXE2_CHANNEL_RXPOLARITY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPOLARITY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX27_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX27_8->GTXE2_CHANNEL_RXDFEVPOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX27_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX27_9->GTXE2_CHANNEL_RXDFELFOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFELFOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX27_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX28_1->GTXE2_CHANNEL_TXCOMSAS": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCOMSAS",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX28_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX28_10->GTXE2_CHANNEL_RXDFETAP2OVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX28_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX28_2->GTXE2_CHANNEL_CPLLLOCKEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CPLLLOCKEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX28_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX28_3->GTXE2_CHANNEL_DRPWE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPWE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX28_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX28_4->GTXE2_CHANNEL_TXSYSCLKSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX28_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX28_5->GTXE2_CHANNEL_TXSYSCLKSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX28_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX28_6->GTXE2_CHANNEL_RXDLYEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDLYEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX28_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX28_8->GTXE2_CHANNEL_RXPD1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPD1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX28_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_0->GTXE2_CHANNEL_TXCHARDISPMODE3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_1->GTXE2_CHANNEL_TXCHARISK7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARISK7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_10->GTXE2_CHANNEL_RXDFEAGCHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEAGCHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_2->GTXE2_CHANNEL_TXCHARDISPMODE2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_3->GTXE2_CHANNEL_TXCHARISK6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARISK6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_4->GTXE2_CHANNEL_TXCHARDISPMODE1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_5->GTXE2_CHANNEL_TXCHARISK5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARISK5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_6->GTXE2_CHANNEL_TXCHARDISPMODE0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_7->GTXE2_CHANNEL_TXCHARISK4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARISK4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_8->GTXE2_CHANNEL_RXOSHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXOSHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX29_9->GTXE2_CHANNEL_RXDFETAP5HOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFETAP5HOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX29_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX2_10->GTXE2_CHANNEL_RXOUTCLKSEL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX2_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX2_3->GTXE2_CHANNEL_DRPADDR8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPADDR8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX2_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX2_4->GTXE2_CHANNEL_TXPOSTCURSOR3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX2_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX2_5->GTXE2_CHANNEL_TXDIFFCTRL3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX2_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX2_6->GTXE2_CHANNEL_TXPRECURSOR3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX2_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX2_8->GTXE2_CHANNEL_RXGEARBOXSLIP": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXGEARBOXSLIP",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX2_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX2_9->GTXE2_CHANNEL_RXMCOMMAALIGNEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX2_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX30_10->GTXE2_CHANNEL_RXCHBONDSLAVE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDSLAVE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX30_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX30_3->GTXE2_CHANNEL_TXPOLARITY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPOLARITY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX30_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX30_7->GTXE2_CHANNEL_TXPCSRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPCSRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX30_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX30_8->GTXE2_CHANNEL_RXCDRHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCDRHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX30_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX30_9->GTXE2_CHANNEL_RXCHBONDMASTER": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCHBONDMASTER",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX30_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX31_0->GTXE2_CHANNEL_TXCHARDISPMODE7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX31_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX31_1->GTXE2_CHANNEL_TXCHARISK3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARISK3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX31_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX31_2->GTXE2_CHANNEL_TXCHARDISPMODE6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX31_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX31_3->GTXE2_CHANNEL_TXCHARISK2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARISK2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX31_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX31_4->GTXE2_CHANNEL_TXCHARDISPMODE5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX31_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX31_5->GTXE2_CHANNEL_TXCHARISK1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARISK1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX31_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX31_6->GTXE2_CHANNEL_TXCHARDISPMODE4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX31_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX31_7->GTXE2_CHANNEL_TXCHARISK0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARISK0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX31_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX31_8->GTXE2_CHANNEL_EYESCANTRIGGER": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_EYESCANTRIGGER",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX31_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX32_0->GTXE2_CHANNEL_DRPDI11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX32_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX32_1->GTXE2_CHANNEL_DRPDI15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX32_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX32_2->GTXE2_CHANNEL_TXINHIBIT": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXINHIBIT",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX32_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX32_8->GTXE2_CHANNEL_RXDLYBYPASS": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDLYBYPASS",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX32_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX33_0->GTXE2_CHANNEL_DRPDI10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX33_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX33_1->GTXE2_CHANNEL_DRPDI14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX33_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX33_2->GTXE2_CHANNEL_TXPHALIGNEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPHALIGNEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX33_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX34_0->GTXE2_CHANNEL_DRPDI3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX34_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX34_1->GTXE2_CHANNEL_DRPDI7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX34_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX34_10->GTXE2_CHANNEL_PCSRSVDIN20": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN20",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX34_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX34_2->GTXE2_CHANNEL_DRPADDR3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPADDR3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX34_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX34_3->GTXE2_CHANNEL_DRPADDR7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPADDR7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX34_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX34_4->GTXE2_CHANNEL_SETERRSTATUS": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_SETERRSTATUS",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX34_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX34_8->GTXE2_CHANNEL_RXLPMEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXLPMEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX34_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX34_9->GTXE2_CHANNEL_RXPCOMMAALIGNEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX34_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_0->GTXE2_CHANNEL_DRPDI2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_1->GTXE2_CHANNEL_DRPDI6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_10->GTXE2_CHANNEL_PCSRSVDIN21": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN21",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_2->GTXE2_CHANNEL_DRPADDR2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPADDR2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_3->GTXE2_CHANNEL_DRPADDR6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPADDR6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_4->GTXE2_CHANNEL_TXMARGIN2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMARGIN2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_5->GTXE2_CHANNEL_TXDEEMPH": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDEEMPH",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_6->GTXE2_CHANNEL_TXPD1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPD1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_8->GTXE2_CHANNEL_RXDFEUTOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX35_9->GTXE2_CHANNEL_RXDFELFHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFELFHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX35_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX36_0->GTXE2_CHANNEL_DRPDI9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX36_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX36_1->GTXE2_CHANNEL_DRPDI13": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI13",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX36_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX36_10->GTXE2_CHANNEL_RXDFETAP3HOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFETAP3HOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX36_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX36_2->GTXE2_CHANNEL_CPLLPD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_CPLLPD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX36_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX36_5->GTXE2_CHANNEL_TXPHDLYRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPHDLYRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX36_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX37_0->GTXE2_CHANNEL_DRPDI8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX37_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX37_1->GTXE2_CHANNEL_DRPDI12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX37_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX37_3->GTXE2_CHANNEL_TXPHDLYPD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPHDLYPD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX37_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX37_4->GTXE2_CHANNEL_TXDIFFPD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDIFFPD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX37_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX37_8->GTXE2_CHANNEL_RXDFEXYDHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEXYDHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX37_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX37_9->GTXE2_CHANNEL_RXDFETAP4HOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFETAP4HOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX37_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_0->GTXE2_CHANNEL_DRPDI1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_1->GTXE2_CHANNEL_DRPDI5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_10->GTXE2_CHANNEL_PCSRSVDIN22": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN22",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_2->GTXE2_CHANNEL_DRPADDR1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPADDR1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_3->GTXE2_CHANNEL_DRPADDR5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPADDR5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_4->GTXE2_CHANNEL_TXMARGIN1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMARGIN1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_5->GTXE2_CHANNEL_TXSWING": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSWING",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_6->GTXE2_CHANNEL_TXPD0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPD0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_7->GTXE2_CHANNEL_RXDLYOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDLYOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX38_8->GTXE2_CHANNEL_RXPRBSSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX38_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX39_0->GTXE2_CHANNEL_DRPDI0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX39_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX39_1->GTXE2_CHANNEL_DRPDI4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPDI4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX39_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX39_10->GTXE2_CHANNEL_PCSRSVDIN23": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN23",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX39_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX39_2->GTXE2_CHANNEL_DRPADDR0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPADDR0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX39_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX39_3->GTXE2_CHANNEL_DRPADDR4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPADDR4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX39_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX39_4->GTXE2_CHANNEL_TXMARGIN0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMARGIN0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX39_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX39_5->GTXE2_CHANNEL_TXDETECTRX": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDETECTRX",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX39_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX39_6->GTXE2_CHANNEL_TXELECIDLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXELECIDLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX39_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX39_9->GTXE2_CHANNEL_PCSRSVDIN24": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN24",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX39_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX3_10->GTXE2_CHANNEL_RXLPMLFKLOVRDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX3_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX3_3->GTXE2_CHANNEL_TXSTARTSEQ": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSTARTSEQ",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX3_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX3_4->GTXE2_CHANNEL_TXPOSTCURSOR2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX3_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX3_5->GTXE2_CHANNEL_TXDIFFCTRL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX3_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX3_6->GTXE2_CHANNEL_TXPRECURSOR2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX3_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX3_7->GTXE2_CHANNEL_RXPD0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPD0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX3_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX3_8->GTXE2_CHANNEL_TXPRBSSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX3_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX3_9->GTXE2_CHANNEL_RXDFEUTHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEUTHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX3_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_1->GTXE2_CHANNEL_TSTIN0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_10->GTXE2_CHANNEL_TSTIN9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_2->GTXE2_CHANNEL_TSTIN1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_3->GTXE2_CHANNEL_TSTIN2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_4->GTXE2_CHANNEL_TSTIN3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_5->GTXE2_CHANNEL_TSTIN4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_6->GTXE2_CHANNEL_TSTIN5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_7->GTXE2_CHANNEL_TSTIN6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_8->GTXE2_CHANNEL_TSTIN7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX40_9->GTXE2_CHANNEL_TSTIN8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TSTIN8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX40_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX41_0->GTXE2_CHANNEL_EYESCANMODE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_EYESCANMODE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX41_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX41_1->GTXE2_CHANNEL_TXPOSTCURSORINV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSORINV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX41_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX41_5->GTXE2_CHANNEL_RESETOVRD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RESETOVRD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX41_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX41_6->GTXE2_CHANNEL_RXPHALIGNEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPHALIGNEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX41_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX42_10->GTXE2_CHANNEL_GTRSVD7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX42_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX42_2->GTXE2_CHANNEL_RXSYSCLKSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX42_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX42_3->GTXE2_CHANNEL_GTRSVD0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX42_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX42_4->GTXE2_CHANNEL_GTRSVD1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX42_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX42_5->GTXE2_CHANNEL_GTRSVD2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX42_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX42_6->GTXE2_CHANNEL_GTRSVD3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX42_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX42_7->GTXE2_CHANNEL_GTRSVD4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX42_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX42_8->GTXE2_CHANNEL_GTRSVD5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX42_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX42_9->GTXE2_CHANNEL_GTRSVD6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_GTRSVD6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX42_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX43_10->GTXE2_CHANNEL_RXLPMHFHOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXLPMHFHOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX43_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX43_5->GTXE2_CHANNEL_TXDLYUPDOWN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDLYUPDOWN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX43_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX43_6->GTXE2_CHANNEL_TXRATE2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXRATE2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX43_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX43_9->GTXE2_CHANNEL_LOOPBACK0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_LOOPBACK0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX43_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX44_1->GTXE2_CHANNEL_TXCOMINIT": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCOMINIT",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX44_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX44_10->GTXE2_CHANNEL_RXDFETAP2HOLD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFETAP2HOLD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX44_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX44_3->GTXE2_CHANNEL_DRPEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_DRPEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX44_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX44_5->GTXE2_CHANNEL_TXDLYBYPASS": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDLYBYPASS",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX44_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX44_8->GTXE2_CHANNEL_RXUSERRDY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXUSERRDY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX44_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX44_9->GTXE2_CHANNEL_RXCOMMADETEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXCOMMADETEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX44_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX45_1->GTXE2_CHANNEL_TXQPIWEAKPUP": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXQPIWEAKPUP",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX45_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX45_10->GTXE2_CHANNEL_RXMONITORSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX45_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX45_2->GTXE2_CHANNEL_RXSYSCLKSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX45_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX45_3->GTXE2_CHANNEL_TXDLYSRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDLYSRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX45_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX45_8->GTXE2_CHANNEL_EYESCANRESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_EYESCANRESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX45_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX45_9->GTXE2_CHANNEL_RXDFEXYDEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDFEXYDEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX45_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX46_6->GTXE2_CHANNEL_TXRATE1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXRATE1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX46_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX46_9->GTXE2_CHANNEL_LOOPBACK1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_LOOPBACK1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX46_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX47_6->GTXE2_CHANNEL_TXRATE0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXRATE0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX47_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX47_9->GTXE2_CHANNEL_LOOPBACK2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_LOOPBACK2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX47_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX4_1->GTXE2_CHANNEL_TXPRECURSORINV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRECURSORINV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX4_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX4_10->GTXE2_CHANNEL_RXOUTCLKSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX4_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX4_3->GTXE2_CHANNEL_TXMAINCURSOR1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX4_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX4_4->GTXE2_CHANNEL_TXMAINCURSOR5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX4_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX4_5->GTXE2_CHANNEL_TXSEQUENCE1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX4_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX4_6->GTXE2_CHANNEL_TXSEQUENCE5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX4_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX4_7->GTXE2_CHANNEL_PMARSVDIN21": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN21",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX4_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX4_8->GTXE2_CHANNEL_TXOUTCLKSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX4_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX4_9->GTXE2_CHANNEL_PMARSVDIN1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX4_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX5_1->GTXE2_CHANNEL_TXQPIBIASEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXQPIBIASEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX5_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX5_10->GTXE2_CHANNEL_RXOUTCLKSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX5_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX5_3->GTXE2_CHANNEL_TXMAINCURSOR0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX5_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX5_4->GTXE2_CHANNEL_TXMAINCURSOR4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX5_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX5_5->GTXE2_CHANNEL_TXSEQUENCE0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX5_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX5_6->GTXE2_CHANNEL_TXSEQUENCE4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX5_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX5_7->GTXE2_CHANNEL_PMARSVDIN20": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN20",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX5_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX5_8->GTXE2_CHANNEL_TXOUTCLKSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX5_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX5_9->GTXE2_CHANNEL_PMARSVDIN0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PMARSVDIN0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX5_9"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX6_4->GTXE2_CHANNEL_TXPOSTCURSOR1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX6_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX6_5->GTXE2_CHANNEL_TXDIFFCTRL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX6_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX6_6->GTXE2_CHANNEL_TXPRECURSOR1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX6_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX6_8->GTXE2_CHANNEL_TXPRBSSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX6_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX7_0->GTXE2_CHANNEL_TXPISOPD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPISOPD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX7_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX7_3->GTXE2_CHANNEL_TXPOSTCURSOR4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX7_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX7_4->GTXE2_CHANNEL_TXPOSTCURSOR0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX7_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX7_5->GTXE2_CHANNEL_TXDIFFCTRL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX7_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX7_6->GTXE2_CHANNEL_TXPRECURSOR0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX7_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX7_7->GTXE2_CHANNEL_TXPRECURSOR4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX7_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX7_8->GTXE2_CHANNEL_TXPRBSSEL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX7_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX8_0->GTXE2_CHANNEL_TXCHARDISPVAL3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX8_0"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX8_1->GTXE2_CHANNEL_TX8B10BBYPASS7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX8_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX8_2->GTXE2_CHANNEL_TXCHARDISPVAL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX8_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX8_3->GTXE2_CHANNEL_TX8B10BBYPASS6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX8_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX8_4->GTXE2_CHANNEL_TXCHARDISPVAL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX8_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX8_5->GTXE2_CHANNEL_TX8B10BBYPASS5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX8_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX8_6->GTXE2_CHANNEL_TXCHARDISPVAL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX8_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX8_7->GTXE2_CHANNEL_TX8B10BBYPASS4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX8_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX8_8->GTXE2_CHANNEL_RXDDIEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXDDIEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX8_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_1->GTXE2_CHANNEL_RXPHDLYPD": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_RXPHDLYPD",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_1"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_10->GTXE2_CHANNEL_PCSRSVDIN15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_10"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_2->GTXE2_CHANNEL_TXHEADER2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_TXHEADER2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_2"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_3->GTXE2_CHANNEL_PCSRSVDIN8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_3"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_4->GTXE2_CHANNEL_PCSRSVDIN9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_4"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_5->GTXE2_CHANNEL_PCSRSVDIN10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_5"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_6->GTXE2_CHANNEL_PCSRSVDIN11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_6"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_7->GTXE2_CHANNEL_PCSRSVDIN12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_7"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_8->GTXE2_CHANNEL_PCSRSVDIN13": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN13",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_8"
        },
        "GTX_CHANNEL_0.GTXE2_IMUX9_9->GTXE2_CHANNEL_PCSRSVDIN14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "GTXE2_IMUX9_9"
        }
    },
    "sites": [
        {
            "name": "X0Y0",
            "prefix": "GTXE2_CHANNEL",
            "site_pins": {
                "CFGRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CFGRESET"
                },
                "CLKRSVD0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CLKRSVD0"
                },
                "CLKRSVD1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CLKRSVD1"
                },
                "CLKRSVD2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CLKRSVD2"
                },
                "CLKRSVD3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CLKRSVD3"
                },
                "CPLLFBCLKLOST": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_CPLLFBCLKLOST"
                },
                "CPLLLOCK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_CPLLLOCK"
                },
                "CPLLLOCKDETCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK"
                },
                "CPLLLOCKEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CPLLLOCKEN"
                },
                "CPLLPD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CPLLPD"
                },
                "CPLLREFCLKLOST": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_CPLLREFCLKLOST"
                },
                "CPLLREFCLKSEL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0"
                },
                "CPLLREFCLKSEL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1"
                },
                "CPLLREFCLKSEL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2"
                },
                "CPLLRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_CPLLRESET"
                },
                "DMONITOROUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DMONITOROUT0"
                },
                "DMONITOROUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DMONITOROUT1"
                },
                "DMONITOROUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DMONITOROUT2"
                },
                "DMONITOROUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DMONITOROUT3"
                },
                "DMONITOROUT4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DMONITOROUT4"
                },
                "DMONITOROUT5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DMONITOROUT5"
                },
                "DMONITOROUT6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DMONITOROUT6"
                },
                "DMONITOROUT7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DMONITOROUT7"
                },
                "DRPADDR0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPADDR0"
                },
                "DRPADDR1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPADDR1"
                },
                "DRPADDR2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPADDR2"
                },
                "DRPADDR3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPADDR3"
                },
                "DRPADDR4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPADDR4"
                },
                "DRPADDR5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPADDR5"
                },
                "DRPADDR6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPADDR6"
                },
                "DRPADDR7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPADDR7"
                },
                "DRPADDR8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPADDR8"
                },
                "DRPCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPCLK"
                },
                "DRPDI0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI0"
                },
                "DRPDI1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI1"
                },
                "DRPDI10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI10"
                },
                "DRPDI11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI11"
                },
                "DRPDI12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI12"
                },
                "DRPDI13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI13"
                },
                "DRPDI14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI14"
                },
                "DRPDI15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI15"
                },
                "DRPDI2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI2"
                },
                "DRPDI3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI3"
                },
                "DRPDI4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI4"
                },
                "DRPDI5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI5"
                },
                "DRPDI6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI6"
                },
                "DRPDI7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI7"
                },
                "DRPDI8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI8"
                },
                "DRPDI9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPDI9"
                },
                "DRPDO0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO0"
                },
                "DRPDO1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO1"
                },
                "DRPDO10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO10"
                },
                "DRPDO11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO11"
                },
                "DRPDO12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO12"
                },
                "DRPDO13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO13"
                },
                "DRPDO14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO14"
                },
                "DRPDO15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO15"
                },
                "DRPDO2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO2"
                },
                "DRPDO3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO3"
                },
                "DRPDO4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO4"
                },
                "DRPDO5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO5"
                },
                "DRPDO6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO6"
                },
                "DRPDO7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO7"
                },
                "DRPDO8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO8"
                },
                "DRPDO9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPDO9"
                },
                "DRPEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPEN"
                },
                "DRPRDY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_DRPRDY"
                },
                "DRPWE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_DRPWE"
                },
                "EDTBYPASS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_EDTBYPASS"
                },
                "EDTCLOCK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_EDTCLOCK"
                },
                "EDTCONFIGURATION": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_EDTCONFIGURATION"
                },
                "EDTSINGLEBYPASSCHAIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN"
                },
                "EDTUPDATE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_EDTUPDATE"
                },
                "EYESCANDATAERROR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_EYESCANDATAERROR"
                },
                "EYESCANMODE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_EYESCANMODE"
                },
                "EYESCANRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_EYESCANRESET"
                },
                "EYESCANTRIGGER": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_EYESCANTRIGGER"
                },
                "GTGREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTGREFCLK"
                },
                "GTNORTHREFCLK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTNORTHREFCLK0"
                },
                "GTNORTHREFCLK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTNORTHREFCLK1"
                },
                "GTREFCLK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTREFCLK0"
                },
                "GTREFCLK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTREFCLK1"
                },
                "GTREFCLKMONITOR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_GTREFCLKMONITOR"
                },
                "GTRESETSEL": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRESETSEL"
                },
                "GTRSVD0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD0"
                },
                "GTRSVD1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD1"
                },
                "GTRSVD10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD10"
                },
                "GTRSVD11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD11"
                },
                "GTRSVD12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD12"
                },
                "GTRSVD13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD13"
                },
                "GTRSVD14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD14"
                },
                "GTRSVD15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD15"
                },
                "GTRSVD2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD2"
                },
                "GTRSVD3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD3"
                },
                "GTRSVD4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD4"
                },
                "GTRSVD5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD5"
                },
                "GTRSVD6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD6"
                },
                "GTRSVD7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD7"
                },
                "GTRSVD8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD8"
                },
                "GTRSVD9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRSVD9"
                },
                "GTRXRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTRXRESET"
                },
                "GTSOUTHREFCLK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0"
                },
                "GTSOUTHREFCLK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1"
                },
                "GTTXRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTTXRESET"
                },
                "GTXRXN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXN"
                },
                "GTXRXP": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXP"
                },
                "GTXTXN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXN"
                },
                "GTXTXP": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXP"
                },
                "LOOPBACK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_LOOPBACK0"
                },
                "LOOPBACK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_LOOPBACK1"
                },
                "LOOPBACK2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_LOOPBACK2"
                },
                "PCSRSVDIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN0"
                },
                "PCSRSVDIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN1"
                },
                "PCSRSVDIN10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN10"
                },
                "PCSRSVDIN11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN11"
                },
                "PCSRSVDIN12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN12"
                },
                "PCSRSVDIN13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN13"
                },
                "PCSRSVDIN14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN14"
                },
                "PCSRSVDIN15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN15"
                },
                "PCSRSVDIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN2"
                },
                "PCSRSVDIN20": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN20"
                },
                "PCSRSVDIN21": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN21"
                },
                "PCSRSVDIN22": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN22"
                },
                "PCSRSVDIN23": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN23"
                },
                "PCSRSVDIN24": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN24"
                },
                "PCSRSVDIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN3"
                },
                "PCSRSVDIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN4"
                },
                "PCSRSVDIN5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN5"
                },
                "PCSRSVDIN6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN6"
                },
                "PCSRSVDIN7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN7"
                },
                "PCSRSVDIN8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN8"
                },
                "PCSRSVDIN9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PCSRSVDIN9"
                },
                "PCSRSVDOUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT0"
                },
                "PCSRSVDOUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT1"
                },
                "PCSRSVDOUT10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT10"
                },
                "PCSRSVDOUT11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT11"
                },
                "PCSRSVDOUT12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT12"
                },
                "PCSRSVDOUT13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT13"
                },
                "PCSRSVDOUT14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT14"
                },
                "PCSRSVDOUT15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT15"
                },
                "PCSRSVDOUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT2"
                },
                "PCSRSVDOUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT3"
                },
                "PCSRSVDOUT4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT4"
                },
                "PCSRSVDOUT5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT5"
                },
                "PCSRSVDOUT6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT6"
                },
                "PCSRSVDOUT7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT7"
                },
                "PCSRSVDOUT8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT8"
                },
                "PCSRSVDOUT9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PCSRSVDOUT9"
                },
                "PHYSTATUS": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PHYSTATUS"
                },
                "PMARSVDIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN0"
                },
                "PMARSVDIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN1"
                },
                "PMARSVDIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN2"
                },
                "PMARSVDIN20": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN20"
                },
                "PMARSVDIN21": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN21"
                },
                "PMARSVDIN22": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN22"
                },
                "PMARSVDIN23": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN23"
                },
                "PMARSVDIN24": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN24"
                },
                "PMARSVDIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN3"
                },
                "PMARSVDIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMARSVDIN4"
                },
                "PMASCANCLK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANCLK0"
                },
                "PMASCANCLK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANCLK1"
                },
                "PMASCANCLK2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANCLK2"
                },
                "PMASCANCLK3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANCLK3"
                },
                "PMASCANCLK4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANCLK4"
                },
                "PMASCANENB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANENB"
                },
                "PMASCANIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANIN0"
                },
                "PMASCANIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANIN1"
                },
                "PMASCANIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANIN2"
                },
                "PMASCANIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANIN3"
                },
                "PMASCANIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANIN4"
                },
                "PMASCANMODEB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANMODEB"
                },
                "PMASCANOUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PMASCANOUT0"
                },
                "PMASCANOUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PMASCANOUT1"
                },
                "PMASCANOUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PMASCANOUT2"
                },
                "PMASCANOUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PMASCANOUT3"
                },
                "PMASCANOUT4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_PMASCANOUT4"
                },
                "PMASCANRSTEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_PMASCANRSTEN"
                },
                "QPLLCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTQPLLCLK"
                },
                "QPLLREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_GTQPLLREFCLK"
                },
                "RESETOVRD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RESETOVRD"
                },
                "RX8B10BEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RX8B10BEN"
                },
                "RXBUFRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXBUFRESET"
                },
                "RXBUFSTATUS0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXBUFSTATUS0"
                },
                "RXBUFSTATUS1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXBUFSTATUS1"
                },
                "RXBUFSTATUS2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXBUFSTATUS2"
                },
                "RXBYTEISALIGNED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXBYTEISALIGNED"
                },
                "RXBYTEREALIGN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXBYTEREALIGN"
                },
                "RXCDRFREQRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCDRFREQRESET"
                },
                "RXCDRHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCDRHOLD"
                },
                "RXCDRLOCK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCDRLOCK"
                },
                "RXCDROVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCDROVRDEN"
                },
                "RXCDRRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCDRRESET"
                },
                "RXCDRRESETRSV": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCDRRESETRSV"
                },
                "RXCHANBONDSEQ": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHANBONDSEQ"
                },
                "RXCHANISALIGNED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHANISALIGNED"
                },
                "RXCHANREALIGN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHANREALIGN"
                },
                "RXCHARISCOMMA0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISCOMMA0"
                },
                "RXCHARISCOMMA1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISCOMMA1"
                },
                "RXCHARISCOMMA2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISCOMMA2"
                },
                "RXCHARISCOMMA3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISCOMMA3"
                },
                "RXCHARISCOMMA4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISCOMMA4"
                },
                "RXCHARISCOMMA5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISCOMMA5"
                },
                "RXCHARISCOMMA6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISCOMMA6"
                },
                "RXCHARISCOMMA7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISCOMMA7"
                },
                "RXCHARISK0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISK0"
                },
                "RXCHARISK1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISK1"
                },
                "RXCHARISK2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISK2"
                },
                "RXCHARISK3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISK3"
                },
                "RXCHARISK4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISK4"
                },
                "RXCHARISK5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISK5"
                },
                "RXCHARISK6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISK6"
                },
                "RXCHARISK7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHARISK7"
                },
                "RXCHBONDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDEN"
                },
                "RXCHBONDI0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDI0"
                },
                "RXCHBONDI1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDI1"
                },
                "RXCHBONDI2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDI2"
                },
                "RXCHBONDI3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDI3"
                },
                "RXCHBONDI4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDI4"
                },
                "RXCHBONDLEVEL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0"
                },
                "RXCHBONDLEVEL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1"
                },
                "RXCHBONDLEVEL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2"
                },
                "RXCHBONDMASTER": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDMASTER"
                },
                "RXCHBONDO0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHBONDO0"
                },
                "RXCHBONDO1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHBONDO1"
                },
                "RXCHBONDO2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHBONDO2"
                },
                "RXCHBONDO3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHBONDO3"
                },
                "RXCHBONDO4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCHBONDO4"
                },
                "RXCHBONDSLAVE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCHBONDSLAVE"
                },
                "RXCLKCORCNT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCLKCORCNT0"
                },
                "RXCLKCORCNT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCLKCORCNT1"
                },
                "RXCOMINITDET": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCOMINITDET"
                },
                "RXCOMMADET": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCOMMADET"
                },
                "RXCOMMADETEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXCOMMADETEN"
                },
                "RXCOMSASDET": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCOMSASDET"
                },
                "RXCOMWAKEDET": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXCOMWAKEDET"
                },
                "RXDATA0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA0"
                },
                "RXDATA1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA1"
                },
                "RXDATA10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA10"
                },
                "RXDATA11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA11"
                },
                "RXDATA12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA12"
                },
                "RXDATA13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA13"
                },
                "RXDATA14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA14"
                },
                "RXDATA15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA15"
                },
                "RXDATA16": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA16"
                },
                "RXDATA17": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA17"
                },
                "RXDATA18": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA18"
                },
                "RXDATA19": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA19"
                },
                "RXDATA2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA2"
                },
                "RXDATA20": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA20"
                },
                "RXDATA21": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA21"
                },
                "RXDATA22": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA22"
                },
                "RXDATA23": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA23"
                },
                "RXDATA24": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA24"
                },
                "RXDATA25": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA25"
                },
                "RXDATA26": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA26"
                },
                "RXDATA27": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA27"
                },
                "RXDATA28": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA28"
                },
                "RXDATA29": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA29"
                },
                "RXDATA3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA3"
                },
                "RXDATA30": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA30"
                },
                "RXDATA31": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA31"
                },
                "RXDATA32": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA32"
                },
                "RXDATA33": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA33"
                },
                "RXDATA34": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA34"
                },
                "RXDATA35": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA35"
                },
                "RXDATA36": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA36"
                },
                "RXDATA37": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA37"
                },
                "RXDATA38": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA38"
                },
                "RXDATA39": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA39"
                },
                "RXDATA4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA4"
                },
                "RXDATA40": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA40"
                },
                "RXDATA41": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA41"
                },
                "RXDATA42": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA42"
                },
                "RXDATA43": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA43"
                },
                "RXDATA44": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA44"
                },
                "RXDATA45": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA45"
                },
                "RXDATA46": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA46"
                },
                "RXDATA47": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA47"
                },
                "RXDATA48": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA48"
                },
                "RXDATA49": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA49"
                },
                "RXDATA5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA5"
                },
                "RXDATA50": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA50"
                },
                "RXDATA51": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA51"
                },
                "RXDATA52": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA52"
                },
                "RXDATA53": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA53"
                },
                "RXDATA54": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA54"
                },
                "RXDATA55": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA55"
                },
                "RXDATA56": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA56"
                },
                "RXDATA57": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA57"
                },
                "RXDATA58": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA58"
                },
                "RXDATA59": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA59"
                },
                "RXDATA6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA6"
                },
                "RXDATA60": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA60"
                },
                "RXDATA61": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA61"
                },
                "RXDATA62": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA62"
                },
                "RXDATA63": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA63"
                },
                "RXDATA7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA7"
                },
                "RXDATA8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA8"
                },
                "RXDATA9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATA9"
                },
                "RXDATAVALID": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDATAVALID"
                },
                "RXDDIEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDDIEN"
                },
                "RXDEBUGPULSE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDEBUGPULSE"
                },
                "RXDFEAGCHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEAGCHOLD"
                },
                "RXDFEAGCOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN"
                },
                "RXDFECM1EN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFECM1EN"
                },
                "RXDFELFHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFELFHOLD"
                },
                "RXDFELFOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFELFOVRDEN"
                },
                "RXDFELPMRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFELPMRESET"
                },
                "RXDFETAP2HOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFETAP2HOLD"
                },
                "RXDFETAP2OVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN"
                },
                "RXDFETAP3HOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFETAP3HOLD"
                },
                "RXDFETAP3OVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN"
                },
                "RXDFETAP4HOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFETAP4HOLD"
                },
                "RXDFETAP4OVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN"
                },
                "RXDFETAP5HOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFETAP5HOLD"
                },
                "RXDFETAP5OVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN"
                },
                "RXDFEUTHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEUTHOLD"
                },
                "RXDFEUTOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN"
                },
                "RXDFEVPHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEVPHOLD"
                },
                "RXDFEVPOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN"
                },
                "RXDFEVSEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEVSEN"
                },
                "RXDFEXYDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEXYDEN"
                },
                "RXDFEXYDHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEXYDHOLD"
                },
                "RXDFEXYDOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN"
                },
                "RXDISPERR0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDISPERR0"
                },
                "RXDISPERR1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDISPERR1"
                },
                "RXDISPERR2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDISPERR2"
                },
                "RXDISPERR3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDISPERR3"
                },
                "RXDISPERR4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDISPERR4"
                },
                "RXDISPERR5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDISPERR5"
                },
                "RXDISPERR6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDISPERR6"
                },
                "RXDISPERR7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDISPERR7"
                },
                "RXDLYBYPASS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDLYBYPASS"
                },
                "RXDLYEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDLYEN"
                },
                "RXDLYOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDLYOVRDEN"
                },
                "RXDLYSRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDLYSRESET"
                },
                "RXDLYSRESETDONE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXDLYSRESETDONE"
                },
                "RXDLYTESTENB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXDLYTESTENB"
                },
                "RXELECIDLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXELECIDLE"
                },
                "RXELECIDLEMODE0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXELECIDLEMODE0"
                },
                "RXELECIDLEMODE1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXELECIDLEMODE1"
                },
                "RXGEARBOXSLIP": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXGEARBOXSLIP"
                },
                "RXHEADER0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXHEADER0"
                },
                "RXHEADER1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXHEADER1"
                },
                "RXHEADER2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXHEADER2"
                },
                "RXHEADERVALID": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXHEADERVALID"
                },
                "RXLPMEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXLPMEN"
                },
                "RXLPMHFHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXLPMHFHOLD"
                },
                "RXLPMHFOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN"
                },
                "RXLPMLFHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXLPMLFHOLD"
                },
                "RXLPMLFKLOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN"
                },
                "RXMCOMMAALIGNEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN"
                },
                "RXMONITOROUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXMONITOROUT0"
                },
                "RXMONITOROUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXMONITOROUT1"
                },
                "RXMONITOROUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXMONITOROUT2"
                },
                "RXMONITOROUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXMONITOROUT3"
                },
                "RXMONITOROUT4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXMONITOROUT4"
                },
                "RXMONITOROUT5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXMONITOROUT5"
                },
                "RXMONITOROUT6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXMONITOROUT6"
                },
                "RXMONITORSEL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXMONITORSEL0"
                },
                "RXMONITORSEL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXMONITORSEL1"
                },
                "RXNOTINTABLE0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXNOTINTABLE0"
                },
                "RXNOTINTABLE1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXNOTINTABLE1"
                },
                "RXNOTINTABLE2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXNOTINTABLE2"
                },
                "RXNOTINTABLE3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXNOTINTABLE3"
                },
                "RXNOTINTABLE4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXNOTINTABLE4"
                },
                "RXNOTINTABLE5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXNOTINTABLE5"
                },
                "RXNOTINTABLE6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXNOTINTABLE6"
                },
                "RXNOTINTABLE7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXNOTINTABLE7"
                },
                "RXOOBRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXOOBRESET"
                },
                "RXOSHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXOSHOLD"
                },
                "RXOSOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXOSOVRDEN"
                },
                "RXOUTCLK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_GTRXOUTCLK_0"
                },
                "RXOUTCLKFABRIC": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC"
                },
                "RXOUTCLKPCS": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXOUTCLKPCS"
                },
                "RXOUTCLKSEL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXOUTCLKSEL0"
                },
                "RXOUTCLKSEL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXOUTCLKSEL1"
                },
                "RXOUTCLKSEL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXOUTCLKSEL2"
                },
                "RXPCD1DONE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPCD1DONE"
                },
                "RXPCOMMAALIGNEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN"
                },
                "RXPCSRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPCSRESET"
                },
                "RXPD0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPD0"
                },
                "RXPD1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPD1"
                },
                "RXPHALIGN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPHALIGN"
                },
                "RXPHALIGNDONE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHALIGNDONE"
                },
                "RXPHALIGNEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPHALIGNEN"
                },
                "RXPHDLYPD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPHDLYPD"
                },
                "RXPHDLYRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPHDLYRESET"
                },
                "RXPHMONITOR0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHMONITOR0"
                },
                "RXPHMONITOR1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHMONITOR1"
                },
                "RXPHMONITOR2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHMONITOR2"
                },
                "RXPHMONITOR3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHMONITOR3"
                },
                "RXPHMONITOR4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHMONITOR4"
                },
                "RXPHOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPHOVRDEN"
                },
                "RXPHSLIPMONITOR0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0"
                },
                "RXPHSLIPMONITOR1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1"
                },
                "RXPHSLIPMONITOR2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2"
                },
                "RXPHSLIPMONITOR3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3"
                },
                "RXPHSLIPMONITOR4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4"
                },
                "RXPMARESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPMARESET"
                },
                "RXPOLARITY": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPOLARITY"
                },
                "RXPRBSCNTRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPRBSCNTRESET"
                },
                "RXPRBSERR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXPRBSERR"
                },
                "RXPRBSSEL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPRBSSEL0"
                },
                "RXPRBSSEL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPRBSSEL1"
                },
                "RXPRBSSEL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXPRBSSEL2"
                },
                "RXQPIEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXQPIEN"
                },
                "RXQPISENN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXQPISENN"
                },
                "RXQPISENP": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXQPISENP"
                },
                "RXRATE0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXRATE0"
                },
                "RXRATE1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXRATE1"
                },
                "RXRATE2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXRATE2"
                },
                "RXRATEDONE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXRATEDONE"
                },
                "RXRESETDONE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXRESETDONE"
                },
                "RXSLIDE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXSLIDE"
                },
                "RXSTARTOFSEQ": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXSTARTOFSEQ"
                },
                "RXSTATUS0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXSTATUS0"
                },
                "RXSTATUS1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXSTATUS1"
                },
                "RXSTATUS2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXSTATUS2"
                },
                "RXSYSCLKSEL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXSYSCLKSEL0"
                },
                "RXSYSCLKSEL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXSYSCLKSEL1"
                },
                "RXUSERRDY": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXUSERRDY"
                },
                "RXUSRCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXUSRCLK"
                },
                "RXUSRCLK2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_RXUSRCLK2"
                },
                "RXVALID": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_RXVALID"
                },
                "SCANCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_SCANCLK"
                },
                "SCANENB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_SCANENB"
                },
                "SCANIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_SCANIN0"
                },
                "SCANIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_SCANIN1"
                },
                "SCANIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_SCANIN2"
                },
                "SCANIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_SCANIN3"
                },
                "SCANIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_SCANIN4"
                },
                "SCANMODEB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_SCANMODEB"
                },
                "SCANOUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_SCANOUT0"
                },
                "SCANOUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_SCANOUT1"
                },
                "SCANOUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_SCANOUT2"
                },
                "SCANOUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_SCANOUT3"
                },
                "SCANOUT4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_SCANOUT4"
                },
                "SETERRSTATUS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_SETERRSTATUS"
                },
                "TSTCLK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTCLK0"
                },
                "TSTCLK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTCLK1"
                },
                "TSTIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN0"
                },
                "TSTIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN1"
                },
                "TSTIN10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN10"
                },
                "TSTIN11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN11"
                },
                "TSTIN12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN12"
                },
                "TSTIN13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN13"
                },
                "TSTIN14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN14"
                },
                "TSTIN15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN15"
                },
                "TSTIN16": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN16"
                },
                "TSTIN17": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN17"
                },
                "TSTIN18": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN18"
                },
                "TSTIN19": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN19"
                },
                "TSTIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN2"
                },
                "TSTIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN3"
                },
                "TSTIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN4"
                },
                "TSTIN5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN5"
                },
                "TSTIN6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN6"
                },
                "TSTIN7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN7"
                },
                "TSTIN8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN8"
                },
                "TSTIN9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTIN9"
                },
                "TSTOUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT0"
                },
                "TSTOUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT1"
                },
                "TSTOUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT2"
                },
                "TSTOUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT3"
                },
                "TSTOUT4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT4"
                },
                "TSTOUT5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT5"
                },
                "TSTOUT6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT6"
                },
                "TSTOUT7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT7"
                },
                "TSTOUT8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT8"
                },
                "TSTOUT9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TSTOUT9"
                },
                "TSTPD0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTPD0"
                },
                "TSTPD1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTPD1"
                },
                "TSTPD2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTPD2"
                },
                "TSTPD3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTPD3"
                },
                "TSTPD4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTPD4"
                },
                "TSTPDOVRDB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TSTPDOVRDB"
                },
                "TX8B10BBYPASS0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TX8B10BBYPASS0"
                },
                "TX8B10BBYPASS1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TX8B10BBYPASS1"
                },
                "TX8B10BBYPASS2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TX8B10BBYPASS2"
                },
                "TX8B10BBYPASS3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TX8B10BBYPASS3"
                },
                "TX8B10BBYPASS4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TX8B10BBYPASS4"
                },
                "TX8B10BBYPASS5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TX8B10BBYPASS5"
                },
                "TX8B10BBYPASS6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TX8B10BBYPASS6"
                },
                "TX8B10BBYPASS7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TX8B10BBYPASS7"
                },
                "TX8B10BEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TX8B10BEN"
                },
                "TXBUFDIFFCTRL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0"
                },
                "TXBUFDIFFCTRL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1"
                },
                "TXBUFDIFFCTRL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2"
                },
                "TXBUFSTATUS0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXBUFSTATUS0"
                },
                "TXBUFSTATUS1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXBUFSTATUS1"
                },
                "TXCHARDISPMODE0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPMODE0"
                },
                "TXCHARDISPMODE1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPMODE1"
                },
                "TXCHARDISPMODE2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPMODE2"
                },
                "TXCHARDISPMODE3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPMODE3"
                },
                "TXCHARDISPMODE4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPMODE4"
                },
                "TXCHARDISPMODE5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPMODE5"
                },
                "TXCHARDISPMODE6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPMODE6"
                },
                "TXCHARDISPMODE7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPMODE7"
                },
                "TXCHARDISPVAL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPVAL0"
                },
                "TXCHARDISPVAL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPVAL1"
                },
                "TXCHARDISPVAL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPVAL2"
                },
                "TXCHARDISPVAL3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPVAL3"
                },
                "TXCHARDISPVAL4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPVAL4"
                },
                "TXCHARDISPVAL5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPVAL5"
                },
                "TXCHARDISPVAL6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPVAL6"
                },
                "TXCHARDISPVAL7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARDISPVAL7"
                },
                "TXCHARISK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARISK0"
                },
                "TXCHARISK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARISK1"
                },
                "TXCHARISK2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARISK2"
                },
                "TXCHARISK3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARISK3"
                },
                "TXCHARISK4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARISK4"
                },
                "TXCHARISK5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARISK5"
                },
                "TXCHARISK6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARISK6"
                },
                "TXCHARISK7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCHARISK7"
                },
                "TXCOMFINISH": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXCOMFINISH"
                },
                "TXCOMINIT": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCOMINIT"
                },
                "TXCOMSAS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCOMSAS"
                },
                "TXCOMWAKE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXCOMWAKE"
                },
                "TXDATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA0"
                },
                "TXDATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA1"
                },
                "TXDATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA10"
                },
                "TXDATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA11"
                },
                "TXDATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA12"
                },
                "TXDATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA13"
                },
                "TXDATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA14"
                },
                "TXDATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA15"
                },
                "TXDATA16": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA16"
                },
                "TXDATA17": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA17"
                },
                "TXDATA18": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA18"
                },
                "TXDATA19": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA19"
                },
                "TXDATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA2"
                },
                "TXDATA20": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA20"
                },
                "TXDATA21": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA21"
                },
                "TXDATA22": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA22"
                },
                "TXDATA23": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA23"
                },
                "TXDATA24": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA24"
                },
                "TXDATA25": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA25"
                },
                "TXDATA26": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA26"
                },
                "TXDATA27": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA27"
                },
                "TXDATA28": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA28"
                },
                "TXDATA29": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA29"
                },
                "TXDATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA3"
                },
                "TXDATA30": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA30"
                },
                "TXDATA31": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA31"
                },
                "TXDATA32": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA32"
                },
                "TXDATA33": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA33"
                },
                "TXDATA34": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA34"
                },
                "TXDATA35": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA35"
                },
                "TXDATA36": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA36"
                },
                "TXDATA37": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA37"
                },
                "TXDATA38": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA38"
                },
                "TXDATA39": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA39"
                },
                "TXDATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA4"
                },
                "TXDATA40": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA40"
                },
                "TXDATA41": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA41"
                },
                "TXDATA42": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA42"
                },
                "TXDATA43": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA43"
                },
                "TXDATA44": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA44"
                },
                "TXDATA45": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA45"
                },
                "TXDATA46": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA46"
                },
                "TXDATA47": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA47"
                },
                "TXDATA48": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA48"
                },
                "TXDATA49": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA49"
                },
                "TXDATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA5"
                },
                "TXDATA50": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA50"
                },
                "TXDATA51": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA51"
                },
                "TXDATA52": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA52"
                },
                "TXDATA53": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA53"
                },
                "TXDATA54": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA54"
                },
                "TXDATA55": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA55"
                },
                "TXDATA56": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA56"
                },
                "TXDATA57": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA57"
                },
                "TXDATA58": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA58"
                },
                "TXDATA59": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA59"
                },
                "TXDATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA6"
                },
                "TXDATA60": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA60"
                },
                "TXDATA61": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA61"
                },
                "TXDATA62": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA62"
                },
                "TXDATA63": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA63"
                },
                "TXDATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA7"
                },
                "TXDATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA8"
                },
                "TXDATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDATA9"
                },
                "TXDEEMPH": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDEEMPH"
                },
                "TXDETECTRX": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDETECTRX"
                },
                "TXDIFFCTRL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDIFFCTRL0"
                },
                "TXDIFFCTRL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDIFFCTRL1"
                },
                "TXDIFFCTRL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDIFFCTRL2"
                },
                "TXDIFFCTRL3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDIFFCTRL3"
                },
                "TXDIFFPD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDIFFPD"
                },
                "TXDLYBYPASS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDLYBYPASS"
                },
                "TXDLYEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDLYEN"
                },
                "TXDLYHOLD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDLYHOLD"
                },
                "TXDLYOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDLYOVRDEN"
                },
                "TXDLYSRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDLYSRESET"
                },
                "TXDLYSRESETDONE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXDLYSRESETDONE"
                },
                "TXDLYTESTENB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDLYTESTENB"
                },
                "TXDLYUPDOWN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXDLYUPDOWN"
                },
                "TXELECIDLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXELECIDLE"
                },
                "TXGEARBOXREADY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXGEARBOXREADY"
                },
                "TXHEADER0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXHEADER0"
                },
                "TXHEADER1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXHEADER1"
                },
                "TXHEADER2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXHEADER2"
                },
                "TXINHIBIT": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXINHIBIT"
                },
                "TXMAINCURSOR0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMAINCURSOR0"
                },
                "TXMAINCURSOR1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMAINCURSOR1"
                },
                "TXMAINCURSOR2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMAINCURSOR2"
                },
                "TXMAINCURSOR3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMAINCURSOR3"
                },
                "TXMAINCURSOR4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMAINCURSOR4"
                },
                "TXMAINCURSOR5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMAINCURSOR5"
                },
                "TXMAINCURSOR6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMAINCURSOR6"
                },
                "TXMARGIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMARGIN0"
                },
                "TXMARGIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMARGIN1"
                },
                "TXMARGIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXMARGIN2"
                },
                "TXOUTCLK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_GTTXOUTCLK_0"
                },
                "TXOUTCLKFABRIC": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC"
                },
                "TXOUTCLKPCS": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXOUTCLKPCS"
                },
                "TXOUTCLKSEL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXOUTCLKSEL0"
                },
                "TXOUTCLKSEL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXOUTCLKSEL1"
                },
                "TXOUTCLKSEL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXOUTCLKSEL2"
                },
                "TXPCSRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPCSRESET"
                },
                "TXPD0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPD0"
                },
                "TXPD1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPD1"
                },
                "TXPDELECIDLEMODE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE"
                },
                "TXPHALIGN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPHALIGN"
                },
                "TXPHALIGNDONE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXPHALIGNDONE"
                },
                "TXPHALIGNEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPHALIGNEN"
                },
                "TXPHDLYPD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPHDLYPD"
                },
                "TXPHDLYRESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPHDLYRESET"
                },
                "TXPHDLYTSTCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK"
                },
                "TXPHINIT": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPHINIT"
                },
                "TXPHINITDONE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "GTXE2_CHANNEL_TXPHINITDONE"
                },
                "TXPHOVRDEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPHOVRDEN"
                },
                "TXPISOPD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPISOPD"
                },
                "TXPMARESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPMARESET"
                },
                "TXPOLARITY": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPOLARITY"
                },
                "TXPOSTCURSOR0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPOSTCURSOR0"
                },
                "TXPOSTCURSOR1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPOSTCURSOR1"
                },
                "TXPOSTCURSOR2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPOSTCURSOR2"
                },
                "TXPOSTCURSOR3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "GTXE2_CHANNEL_TXPOSTCURSOR3"
                },
                "TXPOSTCURSOR4": {
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                        "0.000",
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                        "0.000"
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            "name": "X0Y0",
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        {
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        {
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        {
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