{
    "pips": {
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B19"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B20"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B21"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B22"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B3"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B4"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B5"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B6"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B7"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8"
        },
        "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_B9"
        }
    },
    "sites": [],
    "tile_type": "BRAM_INT_INTERFACE_R",
    "wires": [
        "INT_INTERFACE_BLOCK_OUTS_B0",
        "INT_INTERFACE_BLOCK_OUTS_B1",
        "INT_INTERFACE_BLOCK_OUTS_B2",
        "INT_INTERFACE_BLOCK_OUTS_B3",
        "INT_INTERFACE_BRAM_IMUX0",
        "INT_INTERFACE_BRAM_IMUX1",
        "INT_INTERFACE_BRAM_IMUX10",
        "INT_INTERFACE_BRAM_IMUX11",
        "INT_INTERFACE_BRAM_IMUX12",
        "INT_INTERFACE_BRAM_IMUX13",
        "INT_INTERFACE_BRAM_IMUX14",
        "INT_INTERFACE_BRAM_IMUX15",
        "INT_INTERFACE_BRAM_IMUX16",
        "INT_INTERFACE_BRAM_IMUX17",
        "INT_INTERFACE_BRAM_IMUX18",
        "INT_INTERFACE_BRAM_IMUX19",
        "INT_INTERFACE_BRAM_IMUX2",
        "INT_INTERFACE_BRAM_IMUX20",
        "INT_INTERFACE_BRAM_IMUX21",
        "INT_INTERFACE_BRAM_IMUX22",
        "INT_INTERFACE_BRAM_IMUX23",
        "INT_INTERFACE_BRAM_IMUX24",
        "INT_INTERFACE_BRAM_IMUX25",
        "INT_INTERFACE_BRAM_IMUX26",
        "INT_INTERFACE_BRAM_IMUX27",
        "INT_INTERFACE_BRAM_IMUX28",
        "INT_INTERFACE_BRAM_IMUX29",
        "INT_INTERFACE_BRAM_IMUX3",
        "INT_INTERFACE_BRAM_IMUX30",
        "INT_INTERFACE_BRAM_IMUX31",
        "INT_INTERFACE_BRAM_IMUX32",
        "INT_INTERFACE_BRAM_IMUX33",
        "INT_INTERFACE_BRAM_IMUX34",
        "INT_INTERFACE_BRAM_IMUX35",
        "INT_INTERFACE_BRAM_IMUX36",
        "INT_INTERFACE_BRAM_IMUX37",
        "INT_INTERFACE_BRAM_IMUX38",
        "INT_INTERFACE_BRAM_IMUX39",
        "INT_INTERFACE_BRAM_IMUX4",
        "INT_INTERFACE_BRAM_IMUX40",
        "INT_INTERFACE_BRAM_IMUX41",
        "INT_INTERFACE_BRAM_IMUX42",
        "INT_INTERFACE_BRAM_IMUX43",
        "INT_INTERFACE_BRAM_IMUX44",
        "INT_INTERFACE_BRAM_IMUX45",
        "INT_INTERFACE_BRAM_IMUX46",
        "INT_INTERFACE_BRAM_IMUX47",
        "INT_INTERFACE_BRAM_IMUX5",
        "INT_INTERFACE_BRAM_IMUX6",
        "INT_INTERFACE_BRAM_IMUX7",
        "INT_INTERFACE_BRAM_IMUX8",
        "INT_INTERFACE_BRAM_IMUX9",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX0",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX1",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX10",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX11",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX12",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX13",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX14",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX15",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX16",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX17",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX18",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX19",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX2",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX20",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX21",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX22",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX23",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX24",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX25",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX26",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX27",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX28",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX29",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX3",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX30",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX31",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX32",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX33",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX34",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX35",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX36",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX37",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX38",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX39",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX4",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX40",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX41",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX42",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX43",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX44",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX45",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX46",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX47",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX5",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX6",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX7",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX8",
        "INT_INTERFACE_BRAM_UTURN_R_IMUX9",
        "INT_INTERFACE_BYP0",
        "INT_INTERFACE_BYP1",
        "INT_INTERFACE_BYP2",
        "INT_INTERFACE_BYP3",
        "INT_INTERFACE_BYP4",
        "INT_INTERFACE_BYP5",
        "INT_INTERFACE_BYP6",
        "INT_INTERFACE_BYP7",
        "INT_INTERFACE_CLK0",
        "INT_INTERFACE_CLK1",
        "INT_INTERFACE_CTRL0",
        "INT_INTERFACE_CTRL1",
        "INT_INTERFACE_EE2A0",
        "INT_INTERFACE_EE2A1",
        "INT_INTERFACE_EE2A2",
        "INT_INTERFACE_EE2A3",
        "INT_INTERFACE_EE2BEG0",
        "INT_INTERFACE_EE2BEG1",
        "INT_INTERFACE_EE2BEG2",
        "INT_INTERFACE_EE2BEG3",
        "INT_INTERFACE_EE4A0",
        "INT_INTERFACE_EE4A1",
        "INT_INTERFACE_EE4A2",
        "INT_INTERFACE_EE4A3",
        "INT_INTERFACE_EE4B0",
        "INT_INTERFACE_EE4B1",
        "INT_INTERFACE_EE4B2",
        "INT_INTERFACE_EE4B3",
        "INT_INTERFACE_EE4BEG0",
        "INT_INTERFACE_EE4BEG1",
        "INT_INTERFACE_EE4BEG2",
        "INT_INTERFACE_EE4BEG3",
        "INT_INTERFACE_EE4C0",
        "INT_INTERFACE_EE4C1",
        "INT_INTERFACE_EE4C2",
        "INT_INTERFACE_EE4C3",
        "INT_INTERFACE_EL1BEG0",
        "INT_INTERFACE_EL1BEG1",
        "INT_INTERFACE_EL1BEG2",
        "INT_INTERFACE_EL1BEG3",
        "INT_INTERFACE_ER1BEG0",
        "INT_INTERFACE_ER1BEG1",
        "INT_INTERFACE_ER1BEG2",
        "INT_INTERFACE_ER1BEG3",
        "INT_INTERFACE_FAN0",
        "INT_INTERFACE_FAN1",
        "INT_INTERFACE_FAN2",
        "INT_INTERFACE_FAN3",
        "INT_INTERFACE_FAN4",
        "INT_INTERFACE_FAN5",
        "INT_INTERFACE_FAN6",
        "INT_INTERFACE_FAN7",
        "INT_INTERFACE_LH1",
        "INT_INTERFACE_LH10",
        "INT_INTERFACE_LH11",
        "INT_INTERFACE_LH12",
        "INT_INTERFACE_LH2",
        "INT_INTERFACE_LH3",
        "INT_INTERFACE_LH4",
        "INT_INTERFACE_LH5",
        "INT_INTERFACE_LH6",
        "INT_INTERFACE_LH7",
        "INT_INTERFACE_LH8",
        "INT_INTERFACE_LH9",
        "INT_INTERFACE_LOGIC_OUTS0",
        "INT_INTERFACE_LOGIC_OUTS1",
        "INT_INTERFACE_LOGIC_OUTS10",
        "INT_INTERFACE_LOGIC_OUTS11",
        "INT_INTERFACE_LOGIC_OUTS12",
        "INT_INTERFACE_LOGIC_OUTS13",
        "INT_INTERFACE_LOGIC_OUTS14",
        "INT_INTERFACE_LOGIC_OUTS15",
        "INT_INTERFACE_LOGIC_OUTS16",
        "INT_INTERFACE_LOGIC_OUTS17",
        "INT_INTERFACE_LOGIC_OUTS18",
        "INT_INTERFACE_LOGIC_OUTS19",
        "INT_INTERFACE_LOGIC_OUTS2",
        "INT_INTERFACE_LOGIC_OUTS20",
        "INT_INTERFACE_LOGIC_OUTS21",
        "INT_INTERFACE_LOGIC_OUTS22",
        "INT_INTERFACE_LOGIC_OUTS23",
        "INT_INTERFACE_LOGIC_OUTS3",
        "INT_INTERFACE_LOGIC_OUTS4",
        "INT_INTERFACE_LOGIC_OUTS5",
        "INT_INTERFACE_LOGIC_OUTS6",
        "INT_INTERFACE_LOGIC_OUTS7",
        "INT_INTERFACE_LOGIC_OUTS8",
        "INT_INTERFACE_LOGIC_OUTS9",
        "INT_INTERFACE_LOGIC_OUTS_B0",
        "INT_INTERFACE_LOGIC_OUTS_B1",
        "INT_INTERFACE_LOGIC_OUTS_B10",
        "INT_INTERFACE_LOGIC_OUTS_B11",
        "INT_INTERFACE_LOGIC_OUTS_B12",
        "INT_INTERFACE_LOGIC_OUTS_B13",
        "INT_INTERFACE_LOGIC_OUTS_B14",
        "INT_INTERFACE_LOGIC_OUTS_B15",
        "INT_INTERFACE_LOGIC_OUTS_B16",
        "INT_INTERFACE_LOGIC_OUTS_B17",
        "INT_INTERFACE_LOGIC_OUTS_B18",
        "INT_INTERFACE_LOGIC_OUTS_B19",
        "INT_INTERFACE_LOGIC_OUTS_B2",
        "INT_INTERFACE_LOGIC_OUTS_B20",
        "INT_INTERFACE_LOGIC_OUTS_B21",
        "INT_INTERFACE_LOGIC_OUTS_B22",
        "INT_INTERFACE_LOGIC_OUTS_B23",
        "INT_INTERFACE_LOGIC_OUTS_B3",
        "INT_INTERFACE_LOGIC_OUTS_B4",
        "INT_INTERFACE_LOGIC_OUTS_B5",
        "INT_INTERFACE_LOGIC_OUTS_B6",
        "INT_INTERFACE_LOGIC_OUTS_B7",
        "INT_INTERFACE_LOGIC_OUTS_B8",
        "INT_INTERFACE_LOGIC_OUTS_B9",
        "INT_INTERFACE_MONITOR_N",
        "INT_INTERFACE_MONITOR_P",
        "INT_INTERFACE_NE2A0",
        "INT_INTERFACE_NE2A1",
        "INT_INTERFACE_NE2A2",
        "INT_INTERFACE_NE2A3",
        "INT_INTERFACE_NE4BEG0",
        "INT_INTERFACE_NE4BEG1",
        "INT_INTERFACE_NE4BEG2",
        "INT_INTERFACE_NE4BEG3",
        "INT_INTERFACE_NE4C0",
        "INT_INTERFACE_NE4C1",
        "INT_INTERFACE_NE4C2",
        "INT_INTERFACE_NE4C3",
        "INT_INTERFACE_NW2A0",
        "INT_INTERFACE_NW2A1",
        "INT_INTERFACE_NW2A2",
        "INT_INTERFACE_NW2A3",
        "INT_INTERFACE_NW4A0",
        "INT_INTERFACE_NW4A1",
        "INT_INTERFACE_NW4A2",
        "INT_INTERFACE_NW4A3",
        "INT_INTERFACE_NW4END0",
        "INT_INTERFACE_NW4END1",
        "INT_INTERFACE_NW4END2",
        "INT_INTERFACE_NW4END3",
        "INT_INTERFACE_PHASER_TO_IO_ICLK",
        "INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
        "INT_INTERFACE_PHASER_TO_IO_OCLK",
        "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
        "INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
        "INT_INTERFACE_SE2A0",
        "INT_INTERFACE_SE2A1",
        "INT_INTERFACE_SE2A2",
        "INT_INTERFACE_SE2A3",
        "INT_INTERFACE_SE4BEG0",
        "INT_INTERFACE_SE4BEG1",
        "INT_INTERFACE_SE4BEG2",
        "INT_INTERFACE_SE4BEG3",
        "INT_INTERFACE_SE4C0",
        "INT_INTERFACE_SE4C1",
        "INT_INTERFACE_SE4C2",
        "INT_INTERFACE_SE4C3",
        "INT_INTERFACE_SW2A0",
        "INT_INTERFACE_SW2A1",
        "INT_INTERFACE_SW2A2",
        "INT_INTERFACE_SW2A3",
        "INT_INTERFACE_SW4A0",
        "INT_INTERFACE_SW4A1",
        "INT_INTERFACE_SW4A2",
        "INT_INTERFACE_SW4A3",
        "INT_INTERFACE_SW4END0",
        "INT_INTERFACE_SW4END1",
        "INT_INTERFACE_SW4END2",
        "INT_INTERFACE_SW4END3",
        "INT_INTERFACE_WL1END0",
        "INT_INTERFACE_WL1END1",
        "INT_INTERFACE_WL1END2",
        "INT_INTERFACE_WL1END3",
        "INT_INTERFACE_WR1END0",
        "INT_INTERFACE_WR1END1",
        "INT_INTERFACE_WR1END2",
        "INT_INTERFACE_WR1END3",
        "INT_INTERFACE_WW2A0",
        "INT_INTERFACE_WW2A1",
        "INT_INTERFACE_WW2A2",
        "INT_INTERFACE_WW2A3",
        "INT_INTERFACE_WW2END0",
        "INT_INTERFACE_WW2END1",
        "INT_INTERFACE_WW2END2",
        "INT_INTERFACE_WW2END3",
        "INT_INTERFACE_WW4A0",
        "INT_INTERFACE_WW4A1",
        "INT_INTERFACE_WW4A2",
        "INT_INTERFACE_WW4A3",
        "INT_INTERFACE_WW4B0",
        "INT_INTERFACE_WW4B1",
        "INT_INTERFACE_WW4B2",
        "INT_INTERFACE_WW4B3",
        "INT_INTERFACE_WW4C0",
        "INT_INTERFACE_WW4C1",
        "INT_INTERFACE_WW4C2",
        "INT_INTERFACE_WW4C3",
        "INT_INTERFACE_WW4END0",
        "INT_INTERFACE_WW4END1",
        "INT_INTERFACE_WW4END2",
        "INT_INTERFACE_WW4END3",
        "L_INT_INTER_DQS_IOTOPHASER"
    ]
}