{
    "pips": {},
    "sites": [],
    "tile_type": "HCLK_CLB",
    "wires": [
        "HCLK_CLB_CK_BUFHCLK0",
        "HCLK_CLB_CK_BUFHCLK1",
        "HCLK_CLB_CK_BUFHCLK10",
        "HCLK_CLB_CK_BUFHCLK11",
        "HCLK_CLB_CK_BUFHCLK2",
        "HCLK_CLB_CK_BUFHCLK3",
        "HCLK_CLB_CK_BUFHCLK4",
        "HCLK_CLB_CK_BUFHCLK5",
        "HCLK_CLB_CK_BUFHCLK6",
        "HCLK_CLB_CK_BUFHCLK7",
        "HCLK_CLB_CK_BUFHCLK8",
        "HCLK_CLB_CK_BUFHCLK9",
        "HCLK_CLB_CK_BUFRCLK0",
        "HCLK_CLB_CK_BUFRCLK1",
        "HCLK_CLB_CK_BUFRCLK2",
        "HCLK_CLB_CK_BUFRCLK3",
        "HCLK_CLB_CK_IN0",
        "HCLK_CLB_CK_IN1",
        "HCLK_CLB_CK_IN10",
        "HCLK_CLB_CK_IN11",
        "HCLK_CLB_CK_IN12",
        "HCLK_CLB_CK_IN13",
        "HCLK_CLB_CK_IN2",
        "HCLK_CLB_CK_IN3",
        "HCLK_CLB_CK_IN4",
        "HCLK_CLB_CK_IN5",
        "HCLK_CLB_CK_IN6",
        "HCLK_CLB_CK_IN7",
        "HCLK_CLB_CK_IN8",
        "HCLK_CLB_CK_IN9",
        "HCLK_CLB_COUT0_L",
        "HCLK_CLB_COUT0_R",
        "HCLK_CLB_COUT1_L",
        "HCLK_CLB_COUT1_R",
        "HCLK_CLB_PERFCLK0",
        "HCLK_CLB_PERFCLK1",
        "HCLK_CLB_PERFCLK2",
        "HCLK_CLB_PERFCLK3",
        "HCLK_CLB_REFCK_EASTCLK0",
        "HCLK_CLB_REFCK_EASTCLK1",
        "HCLK_CLB_REFCK_WESTCLK0",
        "HCLK_CLB_REFCK_WESTCLK1"
    ]
}