{
    "pips": {},
    "sites": [],
    "tile_type": "HCLK_BRAM",
    "wires": [
        "HCLK_BRAM_CASCADEA_L",
        "HCLK_BRAM_CASCADEA_R",
        "HCLK_BRAM_CASCADEB_L",
        "HCLK_BRAM_CASCADEB_R",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8",
        "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8",
        "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8",
        "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8",
        "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9",
        "HCLK_BRAM_CK_BUFHCLK0",
        "HCLK_BRAM_CK_BUFHCLK1",
        "HCLK_BRAM_CK_BUFHCLK10",
        "HCLK_BRAM_CK_BUFHCLK11",
        "HCLK_BRAM_CK_BUFHCLK2",
        "HCLK_BRAM_CK_BUFHCLK3",
        "HCLK_BRAM_CK_BUFHCLK4",
        "HCLK_BRAM_CK_BUFHCLK5",
        "HCLK_BRAM_CK_BUFHCLK6",
        "HCLK_BRAM_CK_BUFHCLK7",
        "HCLK_BRAM_CK_BUFHCLK8",
        "HCLK_BRAM_CK_BUFHCLK9",
        "HCLK_BRAM_CK_BUFRCLK0",
        "HCLK_BRAM_CK_BUFRCLK1",
        "HCLK_BRAM_CK_BUFRCLK2",
        "HCLK_BRAM_CK_BUFRCLK3",
        "HCLK_BRAM_CK_IN0",
        "HCLK_BRAM_CK_IN1",
        "HCLK_BRAM_CK_IN10",
        "HCLK_BRAM_CK_IN11",
        "HCLK_BRAM_CK_IN12",
        "HCLK_BRAM_CK_IN13",
        "HCLK_BRAM_CK_IN2",
        "HCLK_BRAM_CK_IN3",
        "HCLK_BRAM_CK_IN4",
        "HCLK_BRAM_CK_IN5",
        "HCLK_BRAM_CK_IN6",
        "HCLK_BRAM_CK_IN7",
        "HCLK_BRAM_CK_IN8",
        "HCLK_BRAM_CK_IN9",
        "HCLK_BRAM_PMVBRAM_O",
        "HCLK_BRAM_PMVBRAM_ODIV2",
        "HCLK_BRAM_PMVBRAM_ODIV4",
        "HCLK_BRAM_PMVBRAM_SELECT1",
        "HCLK_BRAM_PMVBRAM_SELECT2",
        "HCLK_BRAM_PMVBRAM_SELECT3",
        "HCLK_BRAM_PMVBRAM_SELECT4"
    ]
}