{
    "pips": {
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8"
        },
        "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
            "can_invert": "0",
            "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
            "is_directional": "1",
            "is_pseudo": "0",
            "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9"
        }
    },
    "sites": [],
    "tile_type": "IO_INT_INTERFACE_L",
    "wires": [
        "INT_INTERFACE_BLOCK_OUTS_L_B0",
        "INT_INTERFACE_BLOCK_OUTS_L_B1",
        "INT_INTERFACE_BLOCK_OUTS_L_B2",
        "INT_INTERFACE_BLOCK_OUTS_L_B3",
        "INT_INTERFACE_BYP0",
        "INT_INTERFACE_BYP1",
        "INT_INTERFACE_BYP2",
        "INT_INTERFACE_BYP3",
        "INT_INTERFACE_BYP4",
        "INT_INTERFACE_BYP5",
        "INT_INTERFACE_BYP6",
        "INT_INTERFACE_BYP7",
        "INT_INTERFACE_CLK0",
        "INT_INTERFACE_CLK1",
        "INT_INTERFACE_CTRL0",
        "INT_INTERFACE_CTRL1",
        "INT_INTERFACE_EE2A0",
        "INT_INTERFACE_EE2A1",
        "INT_INTERFACE_EE2A2",
        "INT_INTERFACE_EE2A3",
        "INT_INTERFACE_EE2BEG0",
        "INT_INTERFACE_EE2BEG1",
        "INT_INTERFACE_EE2BEG2",
        "INT_INTERFACE_EE2BEG3",
        "INT_INTERFACE_EE4A0",
        "INT_INTERFACE_EE4A1",
        "INT_INTERFACE_EE4A2",
        "INT_INTERFACE_EE4A3",
        "INT_INTERFACE_EE4B0",
        "INT_INTERFACE_EE4B1",
        "INT_INTERFACE_EE4B2",
        "INT_INTERFACE_EE4B3",
        "INT_INTERFACE_EE4BEG0",
        "INT_INTERFACE_EE4BEG1",
        "INT_INTERFACE_EE4BEG2",
        "INT_INTERFACE_EE4BEG3",
        "INT_INTERFACE_EE4C0",
        "INT_INTERFACE_EE4C1",
        "INT_INTERFACE_EE4C2",
        "INT_INTERFACE_EE4C3",
        "INT_INTERFACE_EL1BEG0",
        "INT_INTERFACE_EL1BEG1",
        "INT_INTERFACE_EL1BEG2",
        "INT_INTERFACE_EL1BEG3",
        "INT_INTERFACE_ER1BEG0",
        "INT_INTERFACE_ER1BEG1",
        "INT_INTERFACE_ER1BEG2",
        "INT_INTERFACE_ER1BEG3",
        "INT_INTERFACE_FAN0",
        "INT_INTERFACE_FAN1",
        "INT_INTERFACE_FAN2",
        "INT_INTERFACE_FAN3",
        "INT_INTERFACE_FAN4",
        "INT_INTERFACE_FAN5",
        "INT_INTERFACE_FAN6",
        "INT_INTERFACE_FAN7",
        "INT_INTERFACE_IMUX0",
        "INT_INTERFACE_IMUX1",
        "INT_INTERFACE_IMUX10",
        "INT_INTERFACE_IMUX11",
        "INT_INTERFACE_IMUX12",
        "INT_INTERFACE_IMUX13",
        "INT_INTERFACE_IMUX14",
        "INT_INTERFACE_IMUX15",
        "INT_INTERFACE_IMUX16",
        "INT_INTERFACE_IMUX17",
        "INT_INTERFACE_IMUX18",
        "INT_INTERFACE_IMUX19",
        "INT_INTERFACE_IMUX2",
        "INT_INTERFACE_IMUX20",
        "INT_INTERFACE_IMUX21",
        "INT_INTERFACE_IMUX22",
        "INT_INTERFACE_IMUX23",
        "INT_INTERFACE_IMUX24",
        "INT_INTERFACE_IMUX25",
        "INT_INTERFACE_IMUX26",
        "INT_INTERFACE_IMUX27",
        "INT_INTERFACE_IMUX28",
        "INT_INTERFACE_IMUX29",
        "INT_INTERFACE_IMUX3",
        "INT_INTERFACE_IMUX30",
        "INT_INTERFACE_IMUX31",
        "INT_INTERFACE_IMUX32",
        "INT_INTERFACE_IMUX33",
        "INT_INTERFACE_IMUX34",
        "INT_INTERFACE_IMUX35",
        "INT_INTERFACE_IMUX36",
        "INT_INTERFACE_IMUX37",
        "INT_INTERFACE_IMUX38",
        "INT_INTERFACE_IMUX39",
        "INT_INTERFACE_IMUX4",
        "INT_INTERFACE_IMUX40",
        "INT_INTERFACE_IMUX41",
        "INT_INTERFACE_IMUX42",
        "INT_INTERFACE_IMUX43",
        "INT_INTERFACE_IMUX44",
        "INT_INTERFACE_IMUX45",
        "INT_INTERFACE_IMUX46",
        "INT_INTERFACE_IMUX47",
        "INT_INTERFACE_IMUX5",
        "INT_INTERFACE_IMUX6",
        "INT_INTERFACE_IMUX7",
        "INT_INTERFACE_IMUX8",
        "INT_INTERFACE_IMUX9",
        "INT_INTERFACE_LH1",
        "INT_INTERFACE_LH10",
        "INT_INTERFACE_LH11",
        "INT_INTERFACE_LH12",
        "INT_INTERFACE_LH2",
        "INT_INTERFACE_LH3",
        "INT_INTERFACE_LH4",
        "INT_INTERFACE_LH5",
        "INT_INTERFACE_LH6",
        "INT_INTERFACE_LH7",
        "INT_INTERFACE_LH8",
        "INT_INTERFACE_LH9",
        "INT_INTERFACE_LOGIC_OUTS_L0",
        "INT_INTERFACE_LOGIC_OUTS_L1",
        "INT_INTERFACE_LOGIC_OUTS_L10",
        "INT_INTERFACE_LOGIC_OUTS_L11",
        "INT_INTERFACE_LOGIC_OUTS_L12",
        "INT_INTERFACE_LOGIC_OUTS_L13",
        "INT_INTERFACE_LOGIC_OUTS_L14",
        "INT_INTERFACE_LOGIC_OUTS_L15",
        "INT_INTERFACE_LOGIC_OUTS_L16",
        "INT_INTERFACE_LOGIC_OUTS_L17",
        "INT_INTERFACE_LOGIC_OUTS_L18",
        "INT_INTERFACE_LOGIC_OUTS_L19",
        "INT_INTERFACE_LOGIC_OUTS_L2",
        "INT_INTERFACE_LOGIC_OUTS_L20",
        "INT_INTERFACE_LOGIC_OUTS_L21",
        "INT_INTERFACE_LOGIC_OUTS_L22",
        "INT_INTERFACE_LOGIC_OUTS_L23",
        "INT_INTERFACE_LOGIC_OUTS_L3",
        "INT_INTERFACE_LOGIC_OUTS_L4",
        "INT_INTERFACE_LOGIC_OUTS_L5",
        "INT_INTERFACE_LOGIC_OUTS_L6",
        "INT_INTERFACE_LOGIC_OUTS_L7",
        "INT_INTERFACE_LOGIC_OUTS_L8",
        "INT_INTERFACE_LOGIC_OUTS_L9",
        "INT_INTERFACE_LOGIC_OUTS_L_B0",
        "INT_INTERFACE_LOGIC_OUTS_L_B1",
        "INT_INTERFACE_LOGIC_OUTS_L_B10",
        "INT_INTERFACE_LOGIC_OUTS_L_B11",
        "INT_INTERFACE_LOGIC_OUTS_L_B12",
        "INT_INTERFACE_LOGIC_OUTS_L_B13",
        "INT_INTERFACE_LOGIC_OUTS_L_B14",
        "INT_INTERFACE_LOGIC_OUTS_L_B15",
        "INT_INTERFACE_LOGIC_OUTS_L_B16",
        "INT_INTERFACE_LOGIC_OUTS_L_B17",
        "INT_INTERFACE_LOGIC_OUTS_L_B18",
        "INT_INTERFACE_LOGIC_OUTS_L_B19",
        "INT_INTERFACE_LOGIC_OUTS_L_B2",
        "INT_INTERFACE_LOGIC_OUTS_L_B20",
        "INT_INTERFACE_LOGIC_OUTS_L_B21",
        "INT_INTERFACE_LOGIC_OUTS_L_B22",
        "INT_INTERFACE_LOGIC_OUTS_L_B23",
        "INT_INTERFACE_LOGIC_OUTS_L_B3",
        "INT_INTERFACE_LOGIC_OUTS_L_B4",
        "INT_INTERFACE_LOGIC_OUTS_L_B5",
        "INT_INTERFACE_LOGIC_OUTS_L_B6",
        "INT_INTERFACE_LOGIC_OUTS_L_B7",
        "INT_INTERFACE_LOGIC_OUTS_L_B8",
        "INT_INTERFACE_LOGIC_OUTS_L_B9",
        "INT_INTERFACE_MONITOR_N",
        "INT_INTERFACE_MONITOR_P",
        "INT_INTERFACE_NE2A0",
        "INT_INTERFACE_NE2A1",
        "INT_INTERFACE_NE2A2",
        "INT_INTERFACE_NE2A3",
        "INT_INTERFACE_NE4BEG0",
        "INT_INTERFACE_NE4BEG1",
        "INT_INTERFACE_NE4BEG2",
        "INT_INTERFACE_NE4BEG3",
        "INT_INTERFACE_NE4C0",
        "INT_INTERFACE_NE4C1",
        "INT_INTERFACE_NE4C2",
        "INT_INTERFACE_NE4C3",
        "INT_INTERFACE_NW2A0",
        "INT_INTERFACE_NW2A1",
        "INT_INTERFACE_NW2A2",
        "INT_INTERFACE_NW2A3",
        "INT_INTERFACE_NW4A0",
        "INT_INTERFACE_NW4A1",
        "INT_INTERFACE_NW4A2",
        "INT_INTERFACE_NW4A3",
        "INT_INTERFACE_NW4END0",
        "INT_INTERFACE_NW4END1",
        "INT_INTERFACE_NW4END2",
        "INT_INTERFACE_NW4END3",
        "INT_INTERFACE_PHASER_TO_IO_ICLK",
        "INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
        "INT_INTERFACE_PHASER_TO_IO_OCLK",
        "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
        "INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
        "INT_INTERFACE_SE2A0",
        "INT_INTERFACE_SE2A1",
        "INT_INTERFACE_SE2A2",
        "INT_INTERFACE_SE2A3",
        "INT_INTERFACE_SE4BEG0",
        "INT_INTERFACE_SE4BEG1",
        "INT_INTERFACE_SE4BEG2",
        "INT_INTERFACE_SE4BEG3",
        "INT_INTERFACE_SE4C0",
        "INT_INTERFACE_SE4C1",
        "INT_INTERFACE_SE4C2",
        "INT_INTERFACE_SE4C3",
        "INT_INTERFACE_SW2A0",
        "INT_INTERFACE_SW2A1",
        "INT_INTERFACE_SW2A2",
        "INT_INTERFACE_SW2A3",
        "INT_INTERFACE_SW4A0",
        "INT_INTERFACE_SW4A1",
        "INT_INTERFACE_SW4A2",
        "INT_INTERFACE_SW4A3",
        "INT_INTERFACE_SW4END0",
        "INT_INTERFACE_SW4END1",
        "INT_INTERFACE_SW4END2",
        "INT_INTERFACE_SW4END3",
        "INT_INTERFACE_WL1END0",
        "INT_INTERFACE_WL1END1",
        "INT_INTERFACE_WL1END2",
        "INT_INTERFACE_WL1END3",
        "INT_INTERFACE_WR1END0",
        "INT_INTERFACE_WR1END1",
        "INT_INTERFACE_WR1END2",
        "INT_INTERFACE_WR1END3",
        "INT_INTERFACE_WW2A0",
        "INT_INTERFACE_WW2A1",
        "INT_INTERFACE_WW2A2",
        "INT_INTERFACE_WW2A3",
        "INT_INTERFACE_WW2END0",
        "INT_INTERFACE_WW2END1",
        "INT_INTERFACE_WW2END2",
        "INT_INTERFACE_WW2END3",
        "INT_INTERFACE_WW4A0",
        "INT_INTERFACE_WW4A1",
        "INT_INTERFACE_WW4A2",
        "INT_INTERFACE_WW4A3",
        "INT_INTERFACE_WW4B0",
        "INT_INTERFACE_WW4B1",
        "INT_INTERFACE_WW4B2",
        "INT_INTERFACE_WW4B3",
        "INT_INTERFACE_WW4C0",
        "INT_INTERFACE_WW4C1",
        "INT_INTERFACE_WW4C2",
        "INT_INTERFACE_WW4C3",
        "INT_INTERFACE_WW4END0",
        "INT_INTERFACE_WW4END1",
        "INT_INTERFACE_WW4END2",
        "INT_INTERFACE_WW4END3",
        "L_INT_INTER_DQS_IOTOPHASER"
    ]
}