{
    "pips": {},
    "sites": [],
    "tile_type": "R_TERM_INT",
    "wires": [
        "L_TERM_INT_DQS_IOTOPHASER",
        "L_TERM_INT_PHASER_TO_IO_ICLK",
        "L_TERM_INT_PHASER_TO_IO_ICLKDIV",
        "L_TERM_INT_PHASER_TO_IO_OCLK",
        "L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
        "L_TERM_INT_PHASER_TO_IO_OCLKDIV",
        "R_TERM_INT_LH0",
        "R_TERM_INT_LH1",
        "R_TERM_INT_LH2",
        "R_TERM_INT_LH3",
        "R_TERM_INT_LH4",
        "R_TERM_INT_LH5",
        "R_TERM_INT_NW2A0",
        "R_TERM_INT_NW2A1",
        "R_TERM_INT_NW2A2",
        "R_TERM_INT_NW2A3",
        "R_TERM_INT_NW4A0",
        "R_TERM_INT_NW4A1",
        "R_TERM_INT_NW4A2",
        "R_TERM_INT_NW4A3",
        "R_TERM_INT_NW4END0",
        "R_TERM_INT_NW4END1",
        "R_TERM_INT_NW4END2",
        "R_TERM_INT_NW4END3",
        "R_TERM_INT_SW2A0",
        "R_TERM_INT_SW2A1",
        "R_TERM_INT_SW2A2",
        "R_TERM_INT_SW2A3",
        "R_TERM_INT_SW4A0",
        "R_TERM_INT_SW4A1",
        "R_TERM_INT_SW4A2",
        "R_TERM_INT_SW4A3",
        "R_TERM_INT_SW4END0",
        "R_TERM_INT_SW4END1",
        "R_TERM_INT_SW4END2",
        "R_TERM_INT_SW4END3",
        "R_TERM_INT_WL1END0",
        "R_TERM_INT_WL1END1",
        "R_TERM_INT_WL1END2",
        "R_TERM_INT_WL1END3",
        "R_TERM_INT_WR1END0",
        "R_TERM_INT_WR1END1",
        "R_TERM_INT_WR1END2",
        "R_TERM_INT_WR1END3",
        "R_TERM_INT_WW2A0",
        "R_TERM_INT_WW2A1",
        "R_TERM_INT_WW2A2",
        "R_TERM_INT_WW2A3",
        "R_TERM_INT_WW2END0",
        "R_TERM_INT_WW2END1",
        "R_TERM_INT_WW2END2",
        "R_TERM_INT_WW2END3",
        "R_TERM_INT_WW4A0",
        "R_TERM_INT_WW4A1",
        "R_TERM_INT_WW4A2",
        "R_TERM_INT_WW4A3",
        "R_TERM_INT_WW4B0",
        "R_TERM_INT_WW4B1",
        "R_TERM_INT_WW4B2",
        "R_TERM_INT_WW4B3",
        "R_TERM_INT_WW4C0",
        "R_TERM_INT_WW4C1",
        "R_TERM_INT_WW4C2",
        "R_TERM_INT_WW4C3",
        "R_TERM_INT_WW4END0",
        "R_TERM_INT_WW4END1",
        "R_TERM_INT_WW4END2",
        "R_TERM_INT_WW4END3",
        "TERM_INT_BLOCK_OUTS_L_B0",
        "TERM_INT_BLOCK_OUTS_L_B1",
        "TERM_INT_BLOCK_OUTS_L_B2",
        "TERM_INT_BLOCK_OUTS_L_B3",
        "TERM_INT_BYP0",
        "TERM_INT_BYP1",
        "TERM_INT_BYP2",
        "TERM_INT_BYP3",
        "TERM_INT_BYP4",
        "TERM_INT_BYP5",
        "TERM_INT_BYP6",
        "TERM_INT_BYP7",
        "TERM_INT_CLK0",
        "TERM_INT_CLK1",
        "TERM_INT_CTRL0",
        "TERM_INT_CTRL1",
        "TERM_INT_FAN0",
        "TERM_INT_FAN1",
        "TERM_INT_FAN2",
        "TERM_INT_FAN3",
        "TERM_INT_FAN4",
        "TERM_INT_FAN5",
        "TERM_INT_FAN6",
        "TERM_INT_FAN7",
        "TERM_INT_IMUX0",
        "TERM_INT_IMUX1",
        "TERM_INT_IMUX10",
        "TERM_INT_IMUX11",
        "TERM_INT_IMUX12",
        "TERM_INT_IMUX13",
        "TERM_INT_IMUX14",
        "TERM_INT_IMUX15",
        "TERM_INT_IMUX16",
        "TERM_INT_IMUX17",
        "TERM_INT_IMUX18",
        "TERM_INT_IMUX19",
        "TERM_INT_IMUX2",
        "TERM_INT_IMUX20",
        "TERM_INT_IMUX21",
        "TERM_INT_IMUX22",
        "TERM_INT_IMUX23",
        "TERM_INT_IMUX24",
        "TERM_INT_IMUX25",
        "TERM_INT_IMUX26",
        "TERM_INT_IMUX27",
        "TERM_INT_IMUX28",
        "TERM_INT_IMUX29",
        "TERM_INT_IMUX3",
        "TERM_INT_IMUX30",
        "TERM_INT_IMUX31",
        "TERM_INT_IMUX32",
        "TERM_INT_IMUX33",
        "TERM_INT_IMUX34",
        "TERM_INT_IMUX35",
        "TERM_INT_IMUX36",
        "TERM_INT_IMUX37",
        "TERM_INT_IMUX38",
        "TERM_INT_IMUX39",
        "TERM_INT_IMUX4",
        "TERM_INT_IMUX40",
        "TERM_INT_IMUX41",
        "TERM_INT_IMUX42",
        "TERM_INT_IMUX43",
        "TERM_INT_IMUX44",
        "TERM_INT_IMUX45",
        "TERM_INT_IMUX46",
        "TERM_INT_IMUX47",
        "TERM_INT_IMUX5",
        "TERM_INT_IMUX6",
        "TERM_INT_IMUX7",
        "TERM_INT_IMUX8",
        "TERM_INT_IMUX9",
        "TERM_INT_LOGIC_OUTS_L_B0",
        "TERM_INT_LOGIC_OUTS_L_B1",
        "TERM_INT_LOGIC_OUTS_L_B10",
        "TERM_INT_LOGIC_OUTS_L_B11",
        "TERM_INT_LOGIC_OUTS_L_B12",
        "TERM_INT_LOGIC_OUTS_L_B13",
        "TERM_INT_LOGIC_OUTS_L_B14",
        "TERM_INT_LOGIC_OUTS_L_B15",
        "TERM_INT_LOGIC_OUTS_L_B16",
        "TERM_INT_LOGIC_OUTS_L_B17",
        "TERM_INT_LOGIC_OUTS_L_B18",
        "TERM_INT_LOGIC_OUTS_L_B19",
        "TERM_INT_LOGIC_OUTS_L_B2",
        "TERM_INT_LOGIC_OUTS_L_B20",
        "TERM_INT_LOGIC_OUTS_L_B21",
        "TERM_INT_LOGIC_OUTS_L_B22",
        "TERM_INT_LOGIC_OUTS_L_B23",
        "TERM_INT_LOGIC_OUTS_L_B3",
        "TERM_INT_LOGIC_OUTS_L_B4",
        "TERM_INT_LOGIC_OUTS_L_B5",
        "TERM_INT_LOGIC_OUTS_L_B6",
        "TERM_INT_LOGIC_OUTS_L_B7",
        "TERM_INT_LOGIC_OUTS_L_B8",
        "TERM_INT_LOGIC_OUTS_L_B9",
        "TERM_INT_MONITOR_N",
        "TERM_INT_MONITOR_P"
    ]
}