{
    "pips": {},
    "sites": [],
    "tile_type": "HCLK_VBRK",
    "wires": [
        "HCLK_VBRK_CK_BUFHCLK0",
        "HCLK_VBRK_CK_BUFHCLK1",
        "HCLK_VBRK_CK_BUFHCLK10",
        "HCLK_VBRK_CK_BUFHCLK11",
        "HCLK_VBRK_CK_BUFHCLK2",
        "HCLK_VBRK_CK_BUFHCLK3",
        "HCLK_VBRK_CK_BUFHCLK4",
        "HCLK_VBRK_CK_BUFHCLK5",
        "HCLK_VBRK_CK_BUFHCLK6",
        "HCLK_VBRK_CK_BUFHCLK7",
        "HCLK_VBRK_CK_BUFHCLK8",
        "HCLK_VBRK_CK_BUFHCLK9",
        "HCLK_VBRK_CK_BUFRCLK0",
        "HCLK_VBRK_CK_BUFRCLK1",
        "HCLK_VBRK_CK_BUFRCLK2",
        "HCLK_VBRK_CK_BUFRCLK3",
        "HCLK_VBRK_MUX_CLK0",
        "HCLK_VBRK_MUX_CLK1",
        "HCLK_VBRK_MUX_CLK10",
        "HCLK_VBRK_MUX_CLK11",
        "HCLK_VBRK_MUX_CLK12",
        "HCLK_VBRK_MUX_CLK13",
        "HCLK_VBRK_MUX_CLK2",
        "HCLK_VBRK_MUX_CLK3",
        "HCLK_VBRK_MUX_CLK4",
        "HCLK_VBRK_MUX_CLK5",
        "HCLK_VBRK_MUX_CLK6",
        "HCLK_VBRK_MUX_CLK7",
        "HCLK_VBRK_MUX_CLK8",
        "HCLK_VBRK_MUX_CLK9",
        "HCLK_VBRK_PHSR_PERFCLK0",
        "HCLK_VBRK_PHSR_PERFCLK1",
        "HCLK_VBRK_PHSR_PERFCLK2",
        "HCLK_VBRK_PHSR_PERFCLK3",
        "HCLK_VBRK_REFCK_EASTCLK0",
        "HCLK_VBRK_REFCK_EASTCLK1",
        "HCLK_VBRK_REFCK_WESTCLK0",
        "HCLK_VBRK_REFCK_WESTCLK1"
    ]
}