diff --git a/gatemate/die.py b/gatemate/die.py index fbcd538..7828196 100644 --- a/gatemate/die.py +++ b/gatemate/die.py @@ -98,6 +98,9 @@ def is_edge_io(x,y): if (y==max_row() and x>=101 and x<=136): # IO Bank N2/EB return True +def is_ram(x,y): + return x in [33,65,97,129] and y in [1,17,33,49,65,81,97,113] + @dataclass class IOName: bank : str @@ -285,6 +288,789 @@ PRIMITIVES_PINS = { "USR_RSTN" : [ Pin("USR_RSTN", PinType.OUTPUT,"USR_RSTN_WIRE"), ], + "RAM" : [ + Pin("C_ADDRA_0", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA_1", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA_2", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA_3", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA_4", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA_5", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA_6", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA_7", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB_0", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB_1", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB_2", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB_3", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB_4", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB_5", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB_6", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB_7", PinType.INPUT,"RAM_WIRE"), + Pin("CLKA_0", PinType.INPUT,"RAM_WIRE"), + Pin("CLKA_1", PinType.INPUT,"RAM_WIRE"), + Pin("ENA_0", PinType.INPUT,"RAM_WIRE"), + Pin("ENA_1", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEA_0", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEA_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_0", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_2", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_4", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_5", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_6", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_7", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_8", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_9", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_10", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_11", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_12", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_13", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_14", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0_15", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_0", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_2", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_4", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_5", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_6", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_7", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_8", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_9", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_10", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_11", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_12", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_13", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_14", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X_15", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_0", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_1", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_2", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_3", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_4", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_5", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_6", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_7", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_8", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_9", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_10", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_11", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_12", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_13", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_14", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_15", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_16", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_17", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_18", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_19", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_0", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_1", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_2", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_3", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_4", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_5", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_6", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_7", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_8", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_9", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_10", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_11", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_12", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_13", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_14", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_15", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_16", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_17", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_18", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_19", PinType.INPUT,"RAM_WIRE"), + Pin("CLKA_2", PinType.INPUT,"RAM_WIRE"), + Pin("CLKA_3", PinType.INPUT,"RAM_WIRE"), + Pin("ENA_2", PinType.INPUT,"RAM_WIRE"), + Pin("ENA_3", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEA_2", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEA_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_0", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_2", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_4", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_5", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_6", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_7", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_8", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_9", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_10", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_11", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_12", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_13", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_14", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1_15", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_0", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_2", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_4", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_5", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_6", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_7", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_8", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_9", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_10", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_11", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_12", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_13", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_14", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X_15", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_20", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_21", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_22", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_23", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_24", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_25", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_26", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_27", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_28", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_29", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_30", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_31", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_32", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_33", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_34", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_35", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_36", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_37", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_38", PinType.INPUT,"RAM_WIRE"), + Pin("DIA_39", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_20", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_21", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_22", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_23", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_24", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_25", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_26", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_27", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_28", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_29", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_30", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_31", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_32", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_33", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_34", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_35", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_36", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_37", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_38", PinType.INPUT,"RAM_WIRE"), + Pin("WEA_39", PinType.INPUT,"RAM_WIRE"), + Pin("CLKB_0", PinType.INPUT,"RAM_WIRE"), + Pin("CLKB_1", PinType.INPUT,"RAM_WIRE"), + Pin("ENB_0", PinType.INPUT,"RAM_WIRE"), + Pin("ENB_1", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEB_0", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEB_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_0", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_2", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_4", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_5", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_6", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_7", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_8", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_9", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_10", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_11", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_12", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_13", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_14", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0_15", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_0", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_2", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_4", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_5", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_6", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_7", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_8", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_9", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_10", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_11", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_12", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_13", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_14", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X_15", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_0", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_1", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_2", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_3", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_4", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_5", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_6", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_7", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_8", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_9", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_10", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_11", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_12", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_13", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_14", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_15", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_16", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_17", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_18", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_19", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_0", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_1", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_2", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_3", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_4", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_5", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_6", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_7", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_8", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_9", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_10", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_11", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_12", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_13", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_14", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_15", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_16", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_17", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_18", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_19", PinType.INPUT,"RAM_WIRE"), + Pin("CLKB_2", PinType.INPUT,"RAM_WIRE"), + Pin("CLKB_3", PinType.INPUT,"RAM_WIRE"), + Pin("ENB_2", PinType.INPUT,"RAM_WIRE"), + Pin("ENB_3", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEB_2", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEB_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_0", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_2", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_4", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_5", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_6", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_7", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_8", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_9", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_10", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_11", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_12", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_13", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_14", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1_15", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_0", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_1", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_2", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_3", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_4", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_5", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_6", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_7", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_8", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_9", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_10", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_11", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_12", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_13", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_14", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X_15", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_20", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_21", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_22", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_23", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_24", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_25", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_26", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_27", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_28", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_29", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_30", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_31", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_32", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_33", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_34", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_35", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_36", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_37", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_38", PinType.INPUT,"RAM_WIRE"), + Pin("DIB_39", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_20", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_21", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_22", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_23", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_24", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_25", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_26", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_27", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_28", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_29", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_30", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_31", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_32", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_33", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_34", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_35", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_36", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_37", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_38", PinType.INPUT,"RAM_WIRE"), + Pin("WEB_39", PinType.INPUT,"RAM_WIRE"), + Pin("F_RSTN", PinType.INPUT,"RAM_WIRE"), + Pin("DOA_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_16", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_16", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_17", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_17", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_18", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_18", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_19", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_19", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_20", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_20", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_21", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_21", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_22", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_22", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_23", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_23", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_24", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_24", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_25", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_25", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_26", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_26", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_27", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_27", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_28", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_28", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_29", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_29", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_30", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_30", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_31", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_31", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_32", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_32", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_33", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_33", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_34", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_34", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_35", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_35", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_36", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_36", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_37", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_37", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_38", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_38", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA_39", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX_39", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKA_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKA_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKA_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKA_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_16", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_16", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_17", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_17", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_18", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_18", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_19", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_19", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_20", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_20", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_21", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_21", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_22", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_22", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_23", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_23", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_24", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_24", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_25", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_25", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_26", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_26", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_27", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_27", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_28", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_28", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_29", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_29", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_30", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_30", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_31", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_31", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_32", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_32", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_33", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_33", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_34", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_34", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_35", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_35", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_36", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_36", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_37", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_37", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_38", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_38", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB_39", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX_39", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKB_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKB_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKB_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKB_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRA_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRA_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRA_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRA_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRB_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRB_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRB_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRB_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRA_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRA_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRA_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRA_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRB_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRB_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRB_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRB_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_FULL_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_FULL_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_EMPTY_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_EMPTY_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_AL_FULL_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_AL_FULL_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_AL_EMPTY_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_AL_EMPTY_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ERR_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ERR_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ERR_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ERR_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_CAS_WRAO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_CAS_WRAI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_CAS_WRBO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_CAS_WRBI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_CAS_BMAO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_CAS_BMAI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_CAS_BMBO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_CAS_BMBI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_CAS_RDAO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_CAS_RDAI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_CAS_RDBO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_CAS_RDBI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_0", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_1", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_2", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_3", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_4", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_5", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_6", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_7", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_8", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_9", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_10", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_11", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_12", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_13", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_14", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI_15", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_0", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_1", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_2", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_3", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_4", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_5", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_6", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_7", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_8", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_9", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_10", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_11", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_12", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_13", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_14", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI_15", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_0", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_1", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_2", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_3", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_4", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_5", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_6", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_7", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_8", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_9", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_10", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_11", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_12", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_13", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_14", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI_15", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_0", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_1", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_2", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_3", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_4", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_5", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_6", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_7", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_8", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_9", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_10", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_11", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_12", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_13", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_14", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_0", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_1", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_2", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_3", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_4", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_5", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_6", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_7", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_8", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_9", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_10", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_11", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_12", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_13", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_14", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI_15", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UA0CLKO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LA0CLKI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UA0ENO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LA0ENI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UA0WEO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LA0WEI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LA0CLKO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UA0CLKI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LA0ENO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UA0ENI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LA0WEO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UA0WEI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UA1CLKO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LA1CLKI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UA1ENO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LA1ENI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UA1WEO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LA1WEI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LA1CLKO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UA1CLKI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LA1ENO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UA1ENI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LA1WEO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UA1WEI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UB0CLKO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LB0CLKI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UB0ENO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LB0ENI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UB0WEO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LB0WEI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LB0CLKO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UB0CLKI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LB0ENO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UB0ENI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LB0WEO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UB0WEI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UB1CLKO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LB1CLKI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UB1ENO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LB1ENI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UB1WEO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LB1WEI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LB1CLKO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UB1CLKI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LB1ENO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UB1ENI", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LB1WEO", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UB1WEI", PinType.INPUT,"RAM_WIRE"), + Pin("CLOCK1", PinType.INPUT,"RAM_WIRE"), + Pin("CLOCK2", PinType.INPUT,"RAM_WIRE"), + Pin("CLOCK3", PinType.INPUT,"RAM_WIRE"), + Pin("CLOCK4", PinType.INPUT,"RAM_WIRE"), + ], } def get_groups_for_type(type): @@ -330,6 +1116,8 @@ def get_primitives_for_type(type): if "CPE" in type: primitives.append(Primitive("CPE_HALF_U","CPE_HALF_U",0)) primitives.append(Primitive("CPE_HALF_L","CPE_HALF_L",1)) + if "RAM" in type: + primitives.append(Primitive("RAM","RAM",4)) if "GPIO" in type: primitives.append(Primitive("GPIO","GPIO",0)) if "PLL" in type: @@ -1008,6 +1796,8 @@ def get_tile_types(x,y): val.append("SERDES") if x==1 and y==66: val.append("USR_RSTN") + if is_ram(x,y): + val.append("RAM") return val def get_tile_type(x,y): @@ -1503,6 +2293,696 @@ class Die: self.connect_ddr_i(96,1,2,'S2') self.connect_ddr_i(48,1,1,'S3') + def create_ram(self, x, y): + self.create_conn(x-3,y+2,"CPE.RAM_O1", x,y,"RAM.C_ADDRA_0") + self.create_conn(x-3,y+2,"CPE.RAM_O2", x,y,"RAM.C_ADDRA_1") + self.create_conn(x-3,y+3,"CPE.RAM_O1", x,y,"RAM.C_ADDRA_2") + self.create_conn(x-3,y+3,"CPE.RAM_O2", x,y,"RAM.C_ADDRA_3") + self.create_conn(x-3,y+4,"CPE.RAM_O1", x,y,"RAM.C_ADDRA_4") + self.create_conn(x-3,y+4,"CPE.RAM_O2", x,y,"RAM.C_ADDRA_5") + self.create_conn(x-3,y+5,"CPE.RAM_O1", x,y,"RAM.C_ADDRA_6") + self.create_conn(x-3,y+5,"CPE.RAM_O2", x,y,"RAM.C_ADDRA_7") + self.create_conn(x+2,y+2,"CPE.RAM_O1", x,y,"RAM.C_ADDRB_0") + self.create_conn(x+2,y+2,"CPE.RAM_O2", x,y,"RAM.C_ADDRB_1") + self.create_conn(x+2,y+3,"CPE.RAM_O1", x,y,"RAM.C_ADDRB_2") + self.create_conn(x+2,y+3,"CPE.RAM_O2", x,y,"RAM.C_ADDRB_3") + self.create_conn(x+2,y+4,"CPE.RAM_O1", x,y,"RAM.C_ADDRB_4") + self.create_conn(x+2,y+4,"CPE.RAM_O2", x,y,"RAM.C_ADDRB_5") + self.create_conn(x+2,y+5,"CPE.RAM_O1", x,y,"RAM.C_ADDRB_6") + self.create_conn(x+2,y+5,"CPE.RAM_O2", x,y,"RAM.C_ADDRB_7") + self.create_conn(x-6,y+0,"CPE.RAM_O1", x,y,"RAM.CLKA_0") + self.create_conn(x-3,y+0,"CPE.RAM_O1", x,y,"RAM.CLKA_1") + self.create_conn(x-6,y+1,"CPE.RAM_O1", x,y,"RAM.ENA_0") + self.create_conn(x-3,y+1,"CPE.RAM_O1", x,y,"RAM.ENA_1") + self.create_conn(x-6,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEA_0") + self.create_conn(x-3,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEA_1") + self.create_conn(x-5,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0_0") + self.create_conn(x-5,y+0,"CPE.RAM_O2", x,y,"RAM.ADDRA0_1") + self.create_conn(x-5,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0_2") + self.create_conn(x-5,y+1,"CPE.RAM_O2", x,y,"RAM.ADDRA0_3") + self.create_conn(x-5,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0_4") + self.create_conn(x-5,y+2,"CPE.RAM_O2", x,y,"RAM.ADDRA0_5") + self.create_conn(x-5,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0_6") + self.create_conn(x-5,y+3,"CPE.RAM_O2", x,y,"RAM.ADDRA0_7") + self.create_conn(x-5,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0_8") + self.create_conn(x-5,y+4,"CPE.RAM_O2", x,y,"RAM.ADDRA0_9") + self.create_conn(x-5,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0_10") + self.create_conn(x-5,y+5,"CPE.RAM_O2", x,y,"RAM.ADDRA0_11") + self.create_conn(x-5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0_12") + self.create_conn(x-5,y+6,"CPE.RAM_O2", x,y,"RAM.ADDRA0_13") + self.create_conn(x-5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0_14") + self.create_conn(x-5,y+7,"CPE.RAM_O2", x,y,"RAM.ADDRA0_15") + self.create_conn(x-5,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_0") + self.create_conn(x-4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_1") + self.create_conn(x-5,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_2") + self.create_conn(x-4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_3") + self.create_conn(x-5,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_4") + self.create_conn(x-4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_5") + self.create_conn(x-5,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_6") + self.create_conn(x-4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_7") + self.create_conn(x-5,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_8") + self.create_conn(x-4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_9") + self.create_conn(x-5,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_10") + self.create_conn(x-4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_11") + self.create_conn(x-6,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_12") + self.create_conn(x-5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_13") + self.create_conn(x-6,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_14") + self.create_conn(x-5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_15") + self.create_conn(x-1,y+0,"CPE.RAM_O1", x,y,"RAM.DIA_0") + self.create_conn(x-1,y+0,"CPE.RAM_O2", x,y,"RAM.DIA_1") + self.create_conn(x-1,y+1,"CPE.RAM_O1", x,y,"RAM.DIA_2") + self.create_conn(x-1,y+1,"CPE.RAM_O2", x,y,"RAM.DIA_3") + self.create_conn(x-1,y+2,"CPE.RAM_O1", x,y,"RAM.DIA_4") + self.create_conn(x-1,y+2,"CPE.RAM_O2", x,y,"RAM.DIA_5") + self.create_conn(x-1,y+3,"CPE.RAM_O1", x,y,"RAM.DIA_6") + self.create_conn(x-1,y+3,"CPE.RAM_O2", x,y,"RAM.DIA_7") + self.create_conn(x-1,y+4,"CPE.RAM_O1", x,y,"RAM.DIA_8") + self.create_conn(x-1,y+4,"CPE.RAM_O2", x,y,"RAM.DIA_9") + self.create_conn(x-1,y+5,"CPE.RAM_O1", x,y,"RAM.DIA_10") + self.create_conn(x-1,y+5,"CPE.RAM_O2", x,y,"RAM.DIA_11") + self.create_conn(x-1,y+6,"CPE.RAM_O1", x,y,"RAM.DIA_12") + self.create_conn(x-1,y+6,"CPE.RAM_O2", x,y,"RAM.DIA_13") + self.create_conn(x-1,y+7,"CPE.RAM_O1", x,y,"RAM.DIA_14") + self.create_conn(x-1,y+7,"CPE.RAM_O2", x,y,"RAM.DIA_15") + self.create_conn(x-3,y+6,"CPE.RAM_O1", x,y,"RAM.DIA_16") + self.create_conn(x-3,y+6,"CPE.RAM_O2", x,y,"RAM.DIA_17") + self.create_conn(x-3,y+7,"CPE.RAM_O1", x,y,"RAM.DIA_18") + self.create_conn(x-3,y+7,"CPE.RAM_O2", x,y,"RAM.DIA_19") + self.create_conn(x-2,y+0,"CPE.RAM_O1", x,y,"RAM.WEA_0") + self.create_conn(x-2,y+0,"CPE.RAM_O2", x,y,"RAM.WEA_1") + self.create_conn(x-2,y+1,"CPE.RAM_O1", x,y,"RAM.WEA_2") + self.create_conn(x-2,y+1,"CPE.RAM_O2", x,y,"RAM.WEA_3") + self.create_conn(x-2,y+2,"CPE.RAM_O1", x,y,"RAM.WEA_4") + self.create_conn(x-2,y+2,"CPE.RAM_O2", x,y,"RAM.WEA_5") + self.create_conn(x-2,y+3,"CPE.RAM_O1", x,y,"RAM.WEA_6") + self.create_conn(x-2,y+3,"CPE.RAM_O2", x,y,"RAM.WEA_7") + self.create_conn(x-2,y+4,"CPE.RAM_O1", x,y,"RAM.WEA_8") + self.create_conn(x-2,y+4,"CPE.RAM_O2", x,y,"RAM.WEA_9") + self.create_conn(x-2,y+5,"CPE.RAM_O1", x,y,"RAM.WEA_10") + self.create_conn(x-2,y+5,"CPE.RAM_O2", x,y,"RAM.WEA_11") + self.create_conn(x-2,y+6,"CPE.RAM_O1", x,y,"RAM.WEA_12") + self.create_conn(x-2,y+6,"CPE.RAM_O2", x,y,"RAM.WEA_13") + self.create_conn(x-2,y+7,"CPE.RAM_O1", x,y,"RAM.WEA_14") + self.create_conn(x-2,y+7,"CPE.RAM_O2", x,y,"RAM.WEA_15") + self.create_conn(x-4,y+6,"CPE.RAM_O1", x,y,"RAM.WEA_16") + self.create_conn(x-4,y+6,"CPE.RAM_O2", x,y,"RAM.WEA_17") + self.create_conn(x-4,y+7,"CPE.RAM_O1", x,y,"RAM.WEA_18") + self.create_conn(x-4,y+7,"CPE.RAM_O2", x,y,"RAM.WEA_19") + self.create_conn(x-6,y+8,"CPE.RAM_O1", x,y,"RAM.CLKA_2") + self.create_conn(x-3,y+8,"CPE.RAM_O1", x,y,"RAM.CLKA_3") + self.create_conn(x-6,y+9,"CPE.RAM_O1", x,y,"RAM.ENA_2") + self.create_conn(x-3,y+9,"CPE.RAM_O1", x,y,"RAM.ENA_3") + self.create_conn(x-6,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEA_2") + self.create_conn(x-3,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEA_3") + self.create_conn(x-5,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1_0") + self.create_conn(x-5,y+8,"CPE.RAM_O2", x,y,"RAM.ADDRA1_1") + self.create_conn(x-5,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1_2") + self.create_conn(x-5,y+9,"CPE.RAM_O2", x,y,"RAM.ADDRA1_3") + self.create_conn(x-5,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1_4") + self.create_conn(x-5,y+10,"CPE.RAM_O2", x,y,"RAM.ADDRA1_5") + self.create_conn(x-5,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1_6") + self.create_conn(x-5,y+11,"CPE.RAM_O2", x,y,"RAM.ADDRA1_7") + self.create_conn(x-5,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1_8") + self.create_conn(x-5,y+12,"CPE.RAM_O2", x,y,"RAM.ADDRA1_9") + self.create_conn(x-5,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1_10") + self.create_conn(x-5,y+13,"CPE.RAM_O2", x,y,"RAM.ADDRA1_11") + self.create_conn(x-5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1_12") + self.create_conn(x-5,y+14,"CPE.RAM_O2", x,y,"RAM.ADDRA1_13") + self.create_conn(x-5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1_14") + self.create_conn(x-5,y+15,"CPE.RAM_O2", x,y,"RAM.ADDRA1_15") + self.create_conn(x-5,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_0") + self.create_conn(x-4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_1") + self.create_conn(x-5,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_2") + self.create_conn(x-4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_3") + self.create_conn(x-5,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_4") + self.create_conn(x-4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_5") + self.create_conn(x-5,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_6") + self.create_conn(x-4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_7") + self.create_conn(x-5,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_8") + self.create_conn(x-4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_9") + self.create_conn(x-5,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_10") + self.create_conn(x-4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_11") + self.create_conn(x-6,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_12") + self.create_conn(x-5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_13") + self.create_conn(x-6,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_14") + self.create_conn(x-5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_15") + self.create_conn(x-1,y+8,"CPE.RAM_O1", x,y,"RAM.DIA_20") + self.create_conn(x-1,y+8,"CPE.RAM_O2", x,y,"RAM.DIA_21") + self.create_conn(x-1,y+9,"CPE.RAM_O1", x,y,"RAM.DIA_22") + self.create_conn(x-1,y+9,"CPE.RAM_O2", x,y,"RAM.DIA_23") + self.create_conn(x-1,y+10,"CPE.RAM_O1", x,y,"RAM.DIA_24") + self.create_conn(x-1,y+10,"CPE.RAM_O2", x,y,"RAM.DIA_25") + self.create_conn(x-1,y+11,"CPE.RAM_O1", x,y,"RAM.DIA_26") + self.create_conn(x-1,y+11,"CPE.RAM_O2", x,y,"RAM.DIA_27") + self.create_conn(x-1,y+12,"CPE.RAM_O1", x,y,"RAM.DIA_28") + self.create_conn(x-1,y+12,"CPE.RAM_O2", x,y,"RAM.DIA_29") + self.create_conn(x-1,y+13,"CPE.RAM_O1", x,y,"RAM.DIA_30") + self.create_conn(x-1,y+13,"CPE.RAM_O2", x,y,"RAM.DIA_31") + self.create_conn(x-1,y+14,"CPE.RAM_O1", x,y,"RAM.DIA_32") + self.create_conn(x-1,y+14,"CPE.RAM_O2", x,y,"RAM.DIA_33") + self.create_conn(x-1,y+15,"CPE.RAM_O1", x,y,"RAM.DIA_34") + self.create_conn(x-1,y+15,"CPE.RAM_O2", x,y,"RAM.DIA_35") + self.create_conn(x-3,y+14,"CPE.RAM_O1", x,y,"RAM.DIA_36") + self.create_conn(x-3,y+14,"CPE.RAM_O2", x,y,"RAM.DIA_37") + self.create_conn(x-3,y+15,"CPE.RAM_O1", x,y,"RAM.DIA_38") + self.create_conn(x-3,y+15,"CPE.RAM_O2", x,y,"RAM.DIA_39") + self.create_conn(x-2,y+8,"CPE.RAM_O1", x,y,"RAM.WEA_20") + self.create_conn(x-2,y+8,"CPE.RAM_O2", x,y,"RAM.WEA_21") + self.create_conn(x-2,y+9,"CPE.RAM_O1", x,y,"RAM.WEA_22") + self.create_conn(x-2,y+9,"CPE.RAM_O2", x,y,"RAM.WEA_23") + self.create_conn(x-2,y+10,"CPE.RAM_O1", x,y,"RAM.WEA_24") + self.create_conn(x-2,y+10,"CPE.RAM_O2", x,y,"RAM.WEA_25") + self.create_conn(x-2,y+11,"CPE.RAM_O1", x,y,"RAM.WEA_26") + self.create_conn(x-2,y+11,"CPE.RAM_O2", x,y,"RAM.WEA_27") + self.create_conn(x-2,y+12,"CPE.RAM_O1", x,y,"RAM.WEA_28") + self.create_conn(x-2,y+12,"CPE.RAM_O2", x,y,"RAM.WEA_29") + self.create_conn(x-2,y+13,"CPE.RAM_O1", x,y,"RAM.WEA_30") + self.create_conn(x-2,y+13,"CPE.RAM_O2", x,y,"RAM.WEA_31") + self.create_conn(x-2,y+14,"CPE.RAM_O1", x,y,"RAM.WEA_32") + self.create_conn(x-2,y+14,"CPE.RAM_O2", x,y,"RAM.WEA_33") + self.create_conn(x-2,y+15,"CPE.RAM_O1", x,y,"RAM.WEA_34") + self.create_conn(x-2,y+15,"CPE.RAM_O2", x,y,"RAM.WEA_35") + self.create_conn(x-4,y+14,"CPE.RAM_O1", x,y,"RAM.WEA_36") + self.create_conn(x-4,y+14,"CPE.RAM_O2", x,y,"RAM.WEA_37") + self.create_conn(x-4,y+15,"CPE.RAM_O1", x,y,"RAM.WEA_38") + self.create_conn(x-4,y+15,"CPE.RAM_O2", x,y,"RAM.WEA_39") + self.create_conn(x+2,y+0,"CPE.RAM_O1", x,y,"RAM.CLKB_0") + self.create_conn(x+5,y+0,"CPE.RAM_O1", x,y,"RAM.CLKB_1") + self.create_conn(x+2,y+1,"CPE.RAM_O1", x,y,"RAM.ENB_0") + self.create_conn(x+5,y+1,"CPE.RAM_O1", x,y,"RAM.ENB_1") + self.create_conn(x+2,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEB_0") + self.create_conn(x+5,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEB_1") + self.create_conn(x+4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0_0") + self.create_conn(x+4,y+0,"CPE.RAM_O2", x,y,"RAM.ADDRB0_1") + self.create_conn(x+4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0_2") + self.create_conn(x+4,y+1,"CPE.RAM_O2", x,y,"RAM.ADDRB0_3") + self.create_conn(x+4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0_4") + self.create_conn(x+4,y+2,"CPE.RAM_O2", x,y,"RAM.ADDRB0_5") + self.create_conn(x+4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0_6") + self.create_conn(x+4,y+3,"CPE.RAM_O2", x,y,"RAM.ADDRB0_7") + self.create_conn(x+4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0_8") + self.create_conn(x+4,y+4,"CPE.RAM_O2", x,y,"RAM.ADDRB0_9") + self.create_conn(x+4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0_10") + self.create_conn(x+4,y+5,"CPE.RAM_O2", x,y,"RAM.ADDRB0_11") + self.create_conn(x+4,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0_12") + self.create_conn(x+4,y+6,"CPE.RAM_O2", x,y,"RAM.ADDRB0_13") + self.create_conn(x+4,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0_14") + self.create_conn(x+4,y+7,"CPE.RAM_O2", x,y,"RAM.ADDRB0_15") + self.create_conn(x+3,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_0") + self.create_conn(x+4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_1") + self.create_conn(x+3,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_2") + self.create_conn(x+4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_3") + self.create_conn(x+3,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_4") + self.create_conn(x+4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_5") + self.create_conn(x+3,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_6") + self.create_conn(x+4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_7") + self.create_conn(x+3,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_8") + self.create_conn(x+4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_9") + self.create_conn(x+3,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_10") + self.create_conn(x+4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_11") + self.create_conn(x+4,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_12") + self.create_conn(x+5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_13") + self.create_conn(x+4,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_14") + self.create_conn(x+5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_15") + self.create_conn(x+1,y+0,"CPE.RAM_O1", x,y,"RAM.DIB_0") + self.create_conn(x+1,y+0,"CPE.RAM_O2", x,y,"RAM.DIB_1") + self.create_conn(x+1,y+1,"CPE.RAM_O1", x,y,"RAM.DIB_2") + self.create_conn(x+1,y+1,"CPE.RAM_O2", x,y,"RAM.DIB_3") + self.create_conn(x+1,y+2,"CPE.RAM_O1", x,y,"RAM.DIB_4") + self.create_conn(x+1,y+2,"CPE.RAM_O2", x,y,"RAM.DIB_5") + self.create_conn(x+1,y+3,"CPE.RAM_O1", x,y,"RAM.DIB_6") + self.create_conn(x+1,y+3,"CPE.RAM_O2", x,y,"RAM.DIB_7") + self.create_conn(x+1,y+4,"CPE.RAM_O1", x,y,"RAM.DIB_8") + self.create_conn(x+1,y+4,"CPE.RAM_O2", x,y,"RAM.DIB_9") + self.create_conn(x+1,y+5,"CPE.RAM_O1", x,y,"RAM.DIB_10") + self.create_conn(x+1,y+5,"CPE.RAM_O2", x,y,"RAM.DIB_11") + self.create_conn(x+1,y+6,"CPE.RAM_O1", x,y,"RAM.DIB_12") + self.create_conn(x+1,y+6,"CPE.RAM_O2", x,y,"RAM.DIB_13") + self.create_conn(x+1,y+7,"CPE.RAM_O1", x,y,"RAM.DIB_14") + self.create_conn(x+1,y+7,"CPE.RAM_O2", x,y,"RAM.DIB_15") + self.create_conn(x+3,y+6,"CPE.RAM_O1", x,y,"RAM.DIB_16") + self.create_conn(x+3,y+6,"CPE.RAM_O2", x,y,"RAM.DIB_17") + self.create_conn(x+3,y+7,"CPE.RAM_O1", x,y,"RAM.DIB_18") + self.create_conn(x+3,y+7,"CPE.RAM_O2", x,y,"RAM.DIB_19") + self.create_conn(x+0,y+0,"CPE.RAM_O1", x,y,"RAM.WEB_0") + self.create_conn(x+0,y+0,"CPE.RAM_O2", x,y,"RAM.WEB_1") + self.create_conn(x+0,y+1,"CPE.RAM_O1", x,y,"RAM.WEB_2") + self.create_conn(x+0,y+1,"CPE.RAM_O2", x,y,"RAM.WEB_3") + self.create_conn(x+0,y+2,"CPE.RAM_O1", x,y,"RAM.WEB_4") + self.create_conn(x+0,y+2,"CPE.RAM_O2", x,y,"RAM.WEB_5") + self.create_conn(x+0,y+3,"CPE.RAM_O1", x,y,"RAM.WEB_6") + self.create_conn(x+0,y+3,"CPE.RAM_O2", x,y,"RAM.WEB_7") + self.create_conn(x+0,y+4,"CPE.RAM_O1", x,y,"RAM.WEB_8") + self.create_conn(x+0,y+4,"CPE.RAM_O2", x,y,"RAM.WEB_9") + self.create_conn(x+0,y+5,"CPE.RAM_O1", x,y,"RAM.WEB_10") + self.create_conn(x+0,y+5,"CPE.RAM_O2", x,y,"RAM.WEB_11") + self.create_conn(x+0,y+6,"CPE.RAM_O1", x,y,"RAM.WEB_12") + self.create_conn(x+0,y+6,"CPE.RAM_O2", x,y,"RAM.WEB_13") + self.create_conn(x+0,y+7,"CPE.RAM_O1", x,y,"RAM.WEB_14") + self.create_conn(x+0,y+7,"CPE.RAM_O2", x,y,"RAM.WEB_15") + self.create_conn(x+2,y+6,"CPE.RAM_O1", x,y,"RAM.WEB_16") + self.create_conn(x+2,y+6,"CPE.RAM_O2", x,y,"RAM.WEB_17") + self.create_conn(x+2,y+7,"CPE.RAM_O1", x,y,"RAM.WEB_18") + self.create_conn(x+2,y+7,"CPE.RAM_O2", x,y,"RAM.WEB_19") + self.create_conn(x+2,y+8,"CPE.RAM_O1", x,y,"RAM.CLKB_2") + self.create_conn(x+5,y+8,"CPE.RAM_O1", x,y,"RAM.CLKB_3") + self.create_conn(x+2,y+9,"CPE.RAM_O1", x,y,"RAM.ENB_2") + self.create_conn(x+5,y+9,"CPE.RAM_O1", x,y,"RAM.ENB_3") + self.create_conn(x+2,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEB_2") + self.create_conn(x+5,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEB_3") + self.create_conn(x+4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1_0") + self.create_conn(x+4,y+8,"CPE.RAM_O2", x,y,"RAM.ADDRB1_1") + self.create_conn(x+4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1_2") + self.create_conn(x+4,y+9,"CPE.RAM_O2", x,y,"RAM.ADDRB1_3") + self.create_conn(x+4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1_4") + self.create_conn(x+4,y+10,"CPE.RAM_O2", x,y,"RAM.ADDRB1_5") + self.create_conn(x+4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1_6") + self.create_conn(x+4,y+11,"CPE.RAM_O2", x,y,"RAM.ADDRB1_7") + self.create_conn(x+4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1_8") + self.create_conn(x+4,y+12,"CPE.RAM_O2", x,y,"RAM.ADDRB1_9") + self.create_conn(x+4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1_10") + self.create_conn(x+4,y+13,"CPE.RAM_O2", x,y,"RAM.ADDRB1_11") + self.create_conn(x+4,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1_12") + self.create_conn(x+4,y+14,"CPE.RAM_O2", x,y,"RAM.ADDRB1_13") + self.create_conn(x+4,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1_14") + self.create_conn(x+4,y+15,"CPE.RAM_O2", x,y,"RAM.ADDRB1_15") + self.create_conn(x+3,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_0") + self.create_conn(x+4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_1") + self.create_conn(x+3,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_2") + self.create_conn(x+4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_3") + self.create_conn(x+3,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_4") + self.create_conn(x+4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_5") + self.create_conn(x+3,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_6") + self.create_conn(x+4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_7") + self.create_conn(x+3,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_8") + self.create_conn(x+4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_9") + self.create_conn(x+3,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_10") + self.create_conn(x+4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_11") + self.create_conn(x+4,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_12") + self.create_conn(x+5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_13") + self.create_conn(x+4,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_14") + self.create_conn(x+5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_15") + self.create_conn(x+1,y+8,"CPE.RAM_O1", x,y,"RAM.DIB_20") + self.create_conn(x+1,y+8,"CPE.RAM_O2", x,y,"RAM.DIB_21") + self.create_conn(x+1,y+9,"CPE.RAM_O1", x,y,"RAM.DIB_22") + self.create_conn(x+1,y+9,"CPE.RAM_O2", x,y,"RAM.DIB_23") + self.create_conn(x+1,y+10,"CPE.RAM_O1", x,y,"RAM.DIB_24") + self.create_conn(x+1,y+10,"CPE.RAM_O2", x,y,"RAM.DIB_25") + self.create_conn(x+1,y+11,"CPE.RAM_O1", x,y,"RAM.DIB_26") + self.create_conn(x+1,y+11,"CPE.RAM_O2", x,y,"RAM.DIB_27") + self.create_conn(x+1,y+12,"CPE.RAM_O1", x,y,"RAM.DIB_28") + self.create_conn(x+1,y+12,"CPE.RAM_O2", x,y,"RAM.DIB_29") + self.create_conn(x+1,y+13,"CPE.RAM_O1", x,y,"RAM.DIB_30") + self.create_conn(x+1,y+13,"CPE.RAM_O2", x,y,"RAM.DIB_31") + self.create_conn(x+1,y+14,"CPE.RAM_O1", x,y,"RAM.DIB_32") + self.create_conn(x+1,y+14,"CPE.RAM_O2", x,y,"RAM.DIB_33") + self.create_conn(x+1,y+15,"CPE.RAM_O1", x,y,"RAM.DIB_34") + self.create_conn(x+1,y+15,"CPE.RAM_O2", x,y,"RAM.DIB_35") + self.create_conn(x+3,y+14,"CPE.RAM_O1", x,y,"RAM.DIB_36") + self.create_conn(x+3,y+14,"CPE.RAM_O2", x,y,"RAM.DIB_37") + self.create_conn(x+3,y+15,"CPE.RAM_O1", x,y,"RAM.DIB_38") + self.create_conn(x+3,y+15,"CPE.RAM_O2", x,y,"RAM.DIB_39") + self.create_conn(x+0,y+8,"CPE.RAM_O1", x,y,"RAM.WEB_20") + self.create_conn(x+0,y+8,"CPE.RAM_O2", x,y,"RAM.WEB_21") + self.create_conn(x+0,y+9,"CPE.RAM_O1", x,y,"RAM.WEB_22") + self.create_conn(x+0,y+9,"CPE.RAM_O2", x,y,"RAM.WEB_23") + self.create_conn(x+0,y+10,"CPE.RAM_O1", x,y,"RAM.WEB_24") + self.create_conn(x+0,y+10,"CPE.RAM_O2", x,y,"RAM.WEB_25") + self.create_conn(x+0,y+11,"CPE.RAM_O1", x,y,"RAM.WEB_26") + self.create_conn(x+0,y+11,"CPE.RAM_O2", x,y,"RAM.WEB_27") + self.create_conn(x+0,y+12,"CPE.RAM_O1", x,y,"RAM.WEB_28") + self.create_conn(x+0,y+12,"CPE.RAM_O2", x,y,"RAM.WEB_29") + self.create_conn(x+0,y+13,"CPE.RAM_O1", x,y,"RAM.WEB_30") + self.create_conn(x+0,y+13,"CPE.RAM_O2", x,y,"RAM.WEB_31") + self.create_conn(x+0,y+14,"CPE.RAM_O1", x,y,"RAM.WEB_32") + self.create_conn(x+0,y+14,"CPE.RAM_O2", x,y,"RAM.WEB_33") + self.create_conn(x+0,y+15,"CPE.RAM_O1", x,y,"RAM.WEB_34") + self.create_conn(x+0,y+15,"CPE.RAM_O2", x,y,"RAM.WEB_35") + self.create_conn(x+2,y+14,"CPE.RAM_O1", x,y,"RAM.WEB_36") + self.create_conn(x+2,y+14,"CPE.RAM_O2", x,y,"RAM.WEB_37") + self.create_conn(x+2,y+15,"CPE.RAM_O1", x,y,"RAM.WEB_38") + self.create_conn(x+2,y+15,"CPE.RAM_O2", x,y,"RAM.WEB_39") + self.create_conn(x-6,y+2,"CPE.RAM_O2", x,y,"RAM.F_RSTN") + self.create_conn(x,y,"RAM.DOA_0", x-1,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_0", x-2,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_1", x-1,y+0,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_1", x-1,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_2", x-1,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_2", x-2,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_3", x-1,y+1,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_3", x-1,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_4", x-1,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_4", x-2,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_5", x-1,y+2,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_5", x-1,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_6", x-1,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_6", x-2,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_7", x-1,y+3,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_7", x-1,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_8", x-1,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_8", x-2,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_9", x-1,y+4,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_9", x-1,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_10", x-1,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_10", x-2,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_11", x-1,y+5,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_11", x-1,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_12", x-1,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_12", x-2,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_13", x-1,y+6,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_13", x-1,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_14", x-1,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_14", x-2,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_15", x-1,y+7,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_15", x-1,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_16", x-3,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_16", x-4,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_17", x-3,y+6,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_17", x-3,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_18", x-3,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_18", x-4,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_19", x-3,y+7,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_19", x-3,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_20", x-1,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_20", x-2,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_21", x-1,y+8,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_21", x-1,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_22", x-1,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_22", x-2,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_23", x-1,y+9,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_23", x-1,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_24", x-1,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_24", x-2,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_25", x-1,y+10,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_25", x-1,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_26", x-1,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_26", x-2,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_27", x-1,y+11,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_27", x-1,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_28", x-1,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_28", x-2,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_29", x-1,y+12,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_29", x-1,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_30", x-1,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_30", x-2,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_31", x-1,y+13,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_31", x-1,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_32", x-1,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_32", x-2,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_33", x-1,y+14,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_33", x-1,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_34", x-1,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_34", x-2,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_35", x-1,y+15,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_35", x-1,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_36", x-3,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_36", x-4,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_37", x-3,y+14,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_37", x-3,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_38", x-3,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX_38", x-4,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA_39", x-3,y+15,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX_39", x-3,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKA_1", x-3,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.CLOCKA_2", x-3,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.CLOCKA_3", x-3,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.CLOCKA_4", x-3,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOB_0", x+1,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_0", x+0,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_1", x+1,y+0,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_1", x+1,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_2", x+1,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_2", x+0,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_3", x+1,y+1,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_3", x+1,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_4", x+1,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_4", x+0,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_5", x+1,y+2,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_5", x+1,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_6", x+1,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_6", x+0,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_7", x+1,y+3,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_7", x+1,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_8", x+1,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_8", x+0,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_9", x+1,y+4,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_9", x+1,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_10", x+1,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_10", x+0,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_11", x+1,y+5,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_11", x+1,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_12", x+1,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_12", x+0,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_13", x+1,y+6,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_13", x+1,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_14", x+1,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_14", x+0,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_15", x+1,y+7,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_15", x+1,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_16", x+3,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_16", x+2,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_17", x+3,y+6,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_17", x+3,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_18", x+3,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_18", x+2,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_19", x+3,y+7,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_19", x+3,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_20", x+1,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_20", x+0,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_21", x+1,y+8,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_21", x+1,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_22", x+1,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_22", x+0,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_23", x+1,y+9,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_23", x+1,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_24", x+1,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_24", x+0,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_25", x+1,y+10,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_25", x+1,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_26", x+1,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_26", x+0,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_27", x+1,y+11,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_27", x+1,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_28", x+1,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_28", x+0,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_29", x+1,y+12,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_29", x+1,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_30", x+1,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_30", x+0,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_31", x+1,y+13,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_31", x+1,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_32", x+1,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_32", x+0,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_33", x+1,y+14,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_33", x+1,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_34", x+1,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_34", x+0,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_35", x+1,y+15,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_35", x+1,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_36", x+3,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_36", x+2,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_37", x+3,y+14,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_37", x+3,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_38", x+3,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX_38", x+2,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB_39", x+3,y+15,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX_39", x+3,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKB_1", x+2,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKB_2", x+2,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKB_3", x+2,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKB_4", x+2,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC1B_ERRA_0", x-4,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRA_1", x-4,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRA_2", x+5,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRA_3", x+5,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRB_0", x-4,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRB_1", x-4,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRB_2", x+5,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRB_3", x+5,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC2B_ERRA_0", x-4,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRA_1", x-4,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRA_2", x+5,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRA_3", x+5,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRB_0", x-4,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRB_1", x-4,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRB_2", x+5,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRB_3", x+5,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_FULL_0", x-4,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_FULL_1", x-4,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_EMPTY_0", x-4,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.F_EMPTY_1", x-4,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_AL_FULL_0", x-4,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_AL_FULL_1", x-4,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.F_AL_EMPTY_0", x-4,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.F_AL_EMPTY_1", x-4,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ERR_0", x-4,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ERR_1", x-4,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ERR_0", x-4,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ERR_1", x-4,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR_0", x-6,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX_0", x-5,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR_1", x-6,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX_1", x-5,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR_2", x-6,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX_2", x-5,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR_3", x-6,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX_3", x-5,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR_4", x-6,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX_4", x-5,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR_5", x-6,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX_5", x-5,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR_6", x-6,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX_6", x-5,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR_7", x-6,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX_7", x-5,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR_8", x-6,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX_8", x-5,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR_9", x-6,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX_9", x-5,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR_10", x-6,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX_10", x-5,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR_11", x-6,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX_11", x-5,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR_12", x-6,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX_12", x-5,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR_13", x-6,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX_13", x-5,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR_14", x-6,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX_14", x-5,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR_15", x-6,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX_15", x-5,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR_0", x-6,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX_0", x-5,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR_1", x-6,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX_1", x-5,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR_2", x-6,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX_2", x-5,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR_3", x-6,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX_3", x-5,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR_4", x-6,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX_4", x-5,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR_5", x-6,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX_5", x-5,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR_6", x-6,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX_6", x-5,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR_7", x-6,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX_7", x-5,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR_8", x-6,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX_8", x-5,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR_9", x-6,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX_9", x-5,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR_10", x-6,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX_10", x-5,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR_11", x-6,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX_11", x-5,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR_12", x-6,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX_12", x-5,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR_13", x-6,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX_13", x-5,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR_14", x-6,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX_14", x-5,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR_15", x-6,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX_15", x-5,y+7,"CPE.RAM_I2") + if is_ram(x,y-16): + self.create_conn(x,y,"RAM.FORW_CAS_WRAO", x,y-16,"RAM.FORW_CAS_WRAI") + self.create_conn(x,y,"RAM.FORW_CAS_WRBO", x,y-16,"RAM.FORW_CAS_WRBI") + self.create_conn(x,y,"RAM.FORW_CAS_BMAO", x,y-16,"RAM.FORW_CAS_BMAI") + self.create_conn(x,y,"RAM.FORW_CAS_BMBO", x,y-16,"RAM.FORW_CAS_BMBI") + self.create_conn(x,y,"RAM.FORW_CAS_RDAO", x,y-16,"RAM.FORW_CAS_RDAI") + self.create_conn(x,y,"RAM.FORW_CAS_RDBO", x,y-16,"RAM.FORW_CAS_RDBI") + self.create_conn(x,y,"RAM.FORW_UADDRAO_0", x,y-16,"RAM.FORW_UADDRAI_0") + self.create_conn(x,y,"RAM.FORW_UADDRAO_1", x,y-16,"RAM.FORW_UADDRAI_1") + self.create_conn(x,y,"RAM.FORW_UADDRAO_2", x,y-16,"RAM.FORW_UADDRAI_2") + self.create_conn(x,y,"RAM.FORW_UADDRAO_3", x,y-16,"RAM.FORW_UADDRAI_3") + self.create_conn(x,y,"RAM.FORW_UADDRAO_4", x,y-16,"RAM.FORW_UADDRAI_4") + self.create_conn(x,y,"RAM.FORW_UADDRAO_5", x,y-16,"RAM.FORW_UADDRAI_5") + self.create_conn(x,y,"RAM.FORW_UADDRAO_6", x,y-16,"RAM.FORW_UADDRAI_6") + self.create_conn(x,y,"RAM.FORW_UADDRAO_7", x,y-16,"RAM.FORW_UADDRAI_7") + self.create_conn(x,y,"RAM.FORW_UADDRAO_8", x,y-16,"RAM.FORW_UADDRAI_8") + self.create_conn(x,y,"RAM.FORW_UADDRAO_9", x,y-16,"RAM.FORW_UADDRAI_9") + self.create_conn(x,y,"RAM.FORW_UADDRAO_10", x,y-16,"RAM.FORW_UADDRAI_10") + self.create_conn(x,y,"RAM.FORW_UADDRAO_11", x,y-16,"RAM.FORW_UADDRAI_11") + self.create_conn(x,y,"RAM.FORW_UADDRAO_12", x,y-16,"RAM.FORW_UADDRAI_12") + self.create_conn(x,y,"RAM.FORW_UADDRAO_13", x,y-16,"RAM.FORW_UADDRAI_13") + self.create_conn(x,y,"RAM.FORW_UADDRAO_14", x,y-16,"RAM.FORW_UADDRAI_14") + self.create_conn(x,y,"RAM.FORW_UADDRAO_15", x,y-16,"RAM.FORW_UADDRAI_15") + self.create_conn(x,y,"RAM.FORW_LADDRAO_0", x,y-16,"RAM.FORW_LADDRAI_0") + self.create_conn(x,y,"RAM.FORW_LADDRAO_1", x,y-16,"RAM.FORW_LADDRAI_1") + self.create_conn(x,y,"RAM.FORW_LADDRAO_2", x,y-16,"RAM.FORW_LADDRAI_2") + self.create_conn(x,y,"RAM.FORW_LADDRAO_3", x,y-16,"RAM.FORW_LADDRAI_3") + self.create_conn(x,y,"RAM.FORW_LADDRAO_4", x,y-16,"RAM.FORW_LADDRAI_4") + self.create_conn(x,y,"RAM.FORW_LADDRAO_5", x,y-16,"RAM.FORW_LADDRAI_5") + self.create_conn(x,y,"RAM.FORW_LADDRAO_6", x,y-16,"RAM.FORW_LADDRAI_6") + self.create_conn(x,y,"RAM.FORW_LADDRAO_7", x,y-16,"RAM.FORW_LADDRAI_7") + self.create_conn(x,y,"RAM.FORW_LADDRAO_8", x,y-16,"RAM.FORW_LADDRAI_8") + self.create_conn(x,y,"RAM.FORW_LADDRAO_9", x,y-16,"RAM.FORW_LADDRAI_9") + self.create_conn(x,y,"RAM.FORW_LADDRAO_10", x,y-16,"RAM.FORW_LADDRAI_10") + self.create_conn(x,y,"RAM.FORW_LADDRAO_11", x,y-16,"RAM.FORW_LADDRAI_11") + self.create_conn(x,y,"RAM.FORW_LADDRAO_12", x,y-16,"RAM.FORW_LADDRAI_12") + self.create_conn(x,y,"RAM.FORW_LADDRAO_13", x,y-16,"RAM.FORW_LADDRAI_13") + self.create_conn(x,y,"RAM.FORW_LADDRAO_14", x,y-16,"RAM.FORW_LADDRAI_14") + self.create_conn(x,y,"RAM.FORW_LADDRAO_15", x,y-16,"RAM.FORW_LADDRAI_15") + self.create_conn(x,y,"RAM.FORW_UADDRBO_0", x,y-16,"RAM.FORW_UADDRBI_0") + self.create_conn(x,y,"RAM.FORW_UADDRBO_1", x,y-16,"RAM.FORW_UADDRBI_1") + self.create_conn(x,y,"RAM.FORW_UADDRBO_2", x,y-16,"RAM.FORW_UADDRBI_2") + self.create_conn(x,y,"RAM.FORW_UADDRBO_3", x,y-16,"RAM.FORW_UADDRBI_3") + self.create_conn(x,y,"RAM.FORW_UADDRBO_4", x,y-16,"RAM.FORW_UADDRBI_4") + self.create_conn(x,y,"RAM.FORW_UADDRBO_5", x,y-16,"RAM.FORW_UADDRBI_5") + self.create_conn(x,y,"RAM.FORW_UADDRBO_6", x,y-16,"RAM.FORW_UADDRBI_6") + self.create_conn(x,y,"RAM.FORW_UADDRBO_7", x,y-16,"RAM.FORW_UADDRBI_7") + self.create_conn(x,y,"RAM.FORW_UADDRBO_8", x,y-16,"RAM.FORW_UADDRBI_8") + self.create_conn(x,y,"RAM.FORW_UADDRBO_9", x,y-16,"RAM.FORW_UADDRBI_9") + self.create_conn(x,y,"RAM.FORW_UADDRBO_10", x,y-16,"RAM.FORW_UADDRBI_10") + self.create_conn(x,y,"RAM.FORW_UADDRBO_11", x,y-16,"RAM.FORW_UADDRBI_11") + self.create_conn(x,y,"RAM.FORW_UADDRBO_12", x,y-16,"RAM.FORW_UADDRBI_12") + self.create_conn(x,y,"RAM.FORW_UADDRBO_13", x,y-16,"RAM.FORW_UADDRBI_13") + self.create_conn(x,y,"RAM.FORW_UADDRBO_14", x,y-16,"RAM.FORW_UADDRBI_14") + self.create_conn(x,y,"RAM.FORW_UADDRBO_15", x,y-16,"RAM.FORW_UADDRBI_15") + self.create_conn(x,y,"RAM.FORW_LADDRBO_0", x,y-16,"RAM.FORW_LADDRBI_0") + self.create_conn(x,y,"RAM.FORW_LADDRBO_1", x,y-16,"RAM.FORW_LADDRBI_1") + self.create_conn(x,y,"RAM.FORW_LADDRBO_2", x,y-16,"RAM.FORW_LADDRBI_2") + self.create_conn(x,y,"RAM.FORW_LADDRBO_3", x,y-16,"RAM.FORW_LADDRBI_3") + self.create_conn(x,y,"RAM.FORW_LADDRBO_4", x,y-16,"RAM.FORW_LADDRBI_4") + self.create_conn(x,y,"RAM.FORW_LADDRBO_5", x,y-16,"RAM.FORW_LADDRBI_5") + self.create_conn(x,y,"RAM.FORW_LADDRBO_6", x,y-16,"RAM.FORW_LADDRBI_6") + self.create_conn(x,y,"RAM.FORW_LADDRBO_7", x,y-16,"RAM.FORW_LADDRBI_7") + self.create_conn(x,y,"RAM.FORW_LADDRBO_8", x,y-16,"RAM.FORW_LADDRBI_8") + self.create_conn(x,y,"RAM.FORW_LADDRBO_9", x,y-16,"RAM.FORW_LADDRBI_9") + self.create_conn(x,y,"RAM.FORW_LADDRBO_10", x,y-16,"RAM.FORW_LADDRBI_10") + self.create_conn(x,y,"RAM.FORW_LADDRBO_11", x,y-16,"RAM.FORW_LADDRBI_11") + self.create_conn(x,y,"RAM.FORW_LADDRBO_12", x,y-16,"RAM.FORW_LADDRBI_12") + self.create_conn(x,y,"RAM.FORW_LADDRBO_13", x,y-16,"RAM.FORW_LADDRBI_13") + self.create_conn(x,y,"RAM.FORW_LADDRBO_14", x,y-16,"RAM.FORW_LADDRBI_14") + self.create_conn(x,y,"RAM.FORW_LADDRBO_15", x,y-16,"RAM.FORW_LADDRBI_15") + self.create_conn(x,y,"RAM.FORW_UA0CLKO", x,y-16,"RAM.FORW_UA0CLKI") + self.create_conn(x,y,"RAM.FORW_UA0ENO", x,y-16,"RAM.FORW_UA0ENI") + self.create_conn(x,y,"RAM.FORW_UA0WEO", x,y-16,"RAM.FORW_UA0WEI") + self.create_conn(x,y,"RAM.FORW_LA0CLKO", x,y-16,"RAM.FORW_LA0CLKI") + self.create_conn(x,y,"RAM.FORW_LA0ENO", x,y-16,"RAM.FORW_LA0ENI") + self.create_conn(x,y,"RAM.FORW_LA0WEO", x,y-16,"RAM.FORW_LA0WEI") + self.create_conn(x,y,"RAM.FORW_UA1CLKO", x,y-16,"RAM.FORW_UA1CLKI") + self.create_conn(x,y,"RAM.FORW_UA1ENO", x,y-16,"RAM.FORW_UA1ENI") + self.create_conn(x,y,"RAM.FORW_UA1WEO", x,y-16,"RAM.FORW_UA1WEI") + self.create_conn(x,y,"RAM.FORW_LA1CLKO", x,y-16,"RAM.FORW_LA1CLKI") + self.create_conn(x,y,"RAM.FORW_LA1ENO", x,y-16,"RAM.FORW_LA1ENI") + self.create_conn(x,y,"RAM.FORW_LA1WEO", x,y-16,"RAM.FORW_LA1WEI") + self.create_conn(x,y,"RAM.FORW_UB0CLKO", x,y-16,"RAM.FORW_UB0CLKI") + self.create_conn(x,y,"RAM.FORW_UB0ENO", x,y-16,"RAM.FORW_UB0ENI") + self.create_conn(x,y,"RAM.FORW_UB0WEO", x,y-16,"RAM.FORW_UB0WEI") + self.create_conn(x,y,"RAM.FORW_LB0CLKO", x,y-16,"RAM.FORW_LB0CLKI") + self.create_conn(x,y,"RAM.FORW_LB0ENO", x,y-16,"RAM.FORW_LB0ENI") + self.create_conn(x,y,"RAM.FORW_LB0WEO", x,y-16,"RAM.FORW_LB0WEI") + self.create_conn(x,y,"RAM.FORW_UB1CLKO", x,y-16,"RAM.FORW_UB1CLKI") + self.create_conn(x,y,"RAM.FORW_UB1ENO", x,y-16,"RAM.FORW_UB1ENI") + self.create_conn(x,y,"RAM.FORW_UB1WEO", x,y-16,"RAM.FORW_UB1WEI") + self.create_conn(x,y,"RAM.FORW_LB1CLKO", x,y-16,"RAM.FORW_LB1CLKI") + self.create_conn(x,y,"RAM.FORW_LB1ENO", x,y-16,"RAM.FORW_LB1ENI") + self.create_conn(x,y,"RAM.FORW_LB1WEO", x,y-16,"RAM.FORW_LB1WEI") + self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", x, y, "RAM.CLOCK1") + self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", x, y, "RAM.CLOCK2") + self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", x, y, "RAM.CLOCK3") + self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", x, y, "RAM.CLOCK4") + def create_in_die_connections(self, conn): self.conn = conn for y in range(-2, max_row()+1): @@ -1516,6 +2996,8 @@ class Die: self.create_sb(x,y) if is_edge_io(x,y): self.create_io(x,y) + if is_ram(x,y): + self.create_ram(x,y) self.create_pll() self.global_mesh() self.edge_select()