From cd9c9b3e3b65ca471eca1afaa9c8d06171e79532 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 4 Mar 2025 13:10:40 +0100 Subject: [PATCH] Added serdes and use real ram port names --- gatemate/die.py | 3362 ++++++++++++++++++++++--------------- tools/extract_constids.py | 2 +- 2 files changed, 1994 insertions(+), 1370 deletions(-) diff --git a/gatemate/die.py b/gatemate/die.py index 31a2500..c0d4fa7 100644 --- a/gatemate/die.py +++ b/gatemate/die.py @@ -22,7 +22,7 @@ from dataclasses import dataclass PLL_X_POS = 33 PLL_Y_POS = 131 SERDES_X_POS = 1 -SERDES_Y_POS = 131 +SERDES_Y_POS = 121 def max_row(): return 131 @@ -289,595 +289,595 @@ PRIMITIVES_PINS = { Pin("USR_RSTN", PinType.OUTPUT,"USR_RSTN_WIRE"), ], "RAM" : [ - Pin("C_ADDRA_0", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRA_1", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRA_2", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRA_3", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRA_4", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRA_5", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRA_6", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRA_7", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRB_0", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRB_1", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRB_2", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRB_3", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRB_4", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRB_5", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRB_6", PinType.INPUT,"RAM_WIRE"), - Pin("C_ADDRB_7", PinType.INPUT,"RAM_WIRE"), - Pin("CLKA_0", PinType.INPUT,"RAM_WIRE"), - Pin("CLKA_1", PinType.INPUT,"RAM_WIRE"), - Pin("ENA_0", PinType.INPUT,"RAM_WIRE"), - Pin("ENA_1", PinType.INPUT,"RAM_WIRE"), - Pin("GLWEA_0", PinType.INPUT,"RAM_WIRE"), - Pin("GLWEA_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_0", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_2", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_4", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_5", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_6", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_7", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_8", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_9", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_10", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_11", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_12", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_13", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_14", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0_15", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_0", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_2", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_4", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_5", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_6", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_7", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_8", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_9", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_10", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_11", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_12", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_13", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_14", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA0X_15", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_0", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_1", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_2", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_3", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_4", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_5", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_6", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_7", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_8", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_9", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_10", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_11", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_12", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_13", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_14", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_15", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_16", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_17", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_18", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_19", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_0", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_1", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_2", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_3", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_4", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_5", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_6", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_7", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_8", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_9", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_10", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_11", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_12", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_13", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_14", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_15", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_16", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_17", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_18", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_19", PinType.INPUT,"RAM_WIRE"), - Pin("CLKA_2", PinType.INPUT,"RAM_WIRE"), - Pin("CLKA_3", PinType.INPUT,"RAM_WIRE"), - Pin("ENA_2", PinType.INPUT,"RAM_WIRE"), - Pin("ENA_3", PinType.INPUT,"RAM_WIRE"), - Pin("GLWEA_2", PinType.INPUT,"RAM_WIRE"), - Pin("GLWEA_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_0", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_2", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_4", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_5", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_6", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_7", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_8", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_9", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_10", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_11", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_12", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_13", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_14", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1_15", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_0", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_2", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_4", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_5", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_6", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_7", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_8", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_9", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_10", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_11", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_12", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_13", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_14", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRA1X_15", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_20", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_21", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_22", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_23", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_24", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_25", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_26", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_27", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_28", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_29", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_30", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_31", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_32", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_33", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_34", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_35", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_36", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_37", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_38", PinType.INPUT,"RAM_WIRE"), - Pin("DIA_39", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_20", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_21", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_22", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_23", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_24", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_25", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_26", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_27", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_28", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_29", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_30", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_31", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_32", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_33", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_34", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_35", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_36", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_37", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_38", PinType.INPUT,"RAM_WIRE"), - Pin("WEA_39", PinType.INPUT,"RAM_WIRE"), - Pin("CLKB_0", PinType.INPUT,"RAM_WIRE"), - Pin("CLKB_1", PinType.INPUT,"RAM_WIRE"), - Pin("ENB_0", PinType.INPUT,"RAM_WIRE"), - Pin("ENB_1", PinType.INPUT,"RAM_WIRE"), - Pin("GLWEB_0", PinType.INPUT,"RAM_WIRE"), - Pin("GLWEB_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_0", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_2", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_4", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_5", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_6", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_7", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_8", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_9", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_10", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_11", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_12", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_13", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_14", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0_15", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_0", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_2", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_4", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_5", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_6", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_7", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_8", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_9", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_10", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_11", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_12", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_13", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_14", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB0X_15", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_0", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_1", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_2", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_3", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_4", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_5", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_6", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_7", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_8", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_9", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_10", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_11", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_12", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_13", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_14", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_15", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_16", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_17", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_18", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_19", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_0", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_1", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_2", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_3", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_4", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_5", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_6", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_7", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_8", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_9", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_10", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_11", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_12", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_13", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_14", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_15", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_16", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_17", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_18", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_19", PinType.INPUT,"RAM_WIRE"), - Pin("CLKB_2", PinType.INPUT,"RAM_WIRE"), - Pin("CLKB_3", PinType.INPUT,"RAM_WIRE"), - Pin("ENB_2", PinType.INPUT,"RAM_WIRE"), - Pin("ENB_3", PinType.INPUT,"RAM_WIRE"), - Pin("GLWEB_2", PinType.INPUT,"RAM_WIRE"), - Pin("GLWEB_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_0", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_2", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_4", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_5", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_6", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_7", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_8", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_9", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_10", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_11", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_12", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_13", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_14", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1_15", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_0", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_1", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_2", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_3", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_4", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_5", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_6", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_7", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_8", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_9", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_10", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_11", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_12", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_13", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_14", PinType.INPUT,"RAM_WIRE"), - Pin("ADDRB1X_15", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_20", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_21", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_22", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_23", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_24", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_25", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_26", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_27", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_28", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_29", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_30", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_31", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_32", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_33", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_34", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_35", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_36", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_37", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_38", PinType.INPUT,"RAM_WIRE"), - Pin("DIB_39", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_20", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_21", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_22", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_23", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_24", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_25", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_26", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_27", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_28", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_29", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_30", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_31", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_32", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_33", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_34", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_35", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_36", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_37", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_38", PinType.INPUT,"RAM_WIRE"), - Pin("WEB_39", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA[0]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA[1]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA[2]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA[3]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA[4]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA[5]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA[6]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRA[7]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB[0]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB[1]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB[2]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB[3]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB[4]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB[5]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB[6]", PinType.INPUT,"RAM_WIRE"), + Pin("C_ADDRB[7]", PinType.INPUT,"RAM_WIRE"), + Pin("CLKA[0]", PinType.INPUT,"RAM_WIRE"), + Pin("CLKA[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ENA[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ENA[1]", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEA[0]", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEA[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[4]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[5]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[6]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[7]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[8]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[9]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[10]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[11]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[12]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[13]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[14]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0[15]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[4]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[5]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[6]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[7]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[8]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[9]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[10]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[11]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[12]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[13]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[14]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA0X[15]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[0]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[1]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[2]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[3]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[4]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[5]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[6]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[7]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[8]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[9]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[10]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[11]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[12]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[13]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[14]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[15]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[16]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[17]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[18]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[19]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[0]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[1]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[2]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[3]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[4]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[5]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[6]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[7]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[8]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[9]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[10]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[11]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[12]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[13]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[14]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[15]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[16]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[17]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[18]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[19]", PinType.INPUT,"RAM_WIRE"), + Pin("CLKA[2]", PinType.INPUT,"RAM_WIRE"), + Pin("CLKA[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ENA[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ENA[3]", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEA[2]", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEA[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[4]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[5]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[6]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[7]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[8]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[9]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[10]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[11]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[12]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[13]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[14]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1[15]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[4]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[5]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[6]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[7]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[8]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[9]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[10]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[11]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[12]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[13]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[14]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRA1X[15]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[20]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[21]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[22]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[23]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[24]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[25]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[26]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[27]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[28]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[29]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[30]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[31]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[32]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[33]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[34]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[35]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[36]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[37]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[38]", PinType.INPUT,"RAM_WIRE"), + Pin("DIA[39]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[20]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[21]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[22]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[23]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[24]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[25]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[26]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[27]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[28]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[29]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[30]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[31]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[32]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[33]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[34]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[35]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[36]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[37]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[38]", PinType.INPUT,"RAM_WIRE"), + Pin("WEA[39]", PinType.INPUT,"RAM_WIRE"), + Pin("CLKB[0]", PinType.INPUT,"RAM_WIRE"), + Pin("CLKB[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ENB[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ENB[1]", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEB[0]", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEB[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[4]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[5]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[6]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[7]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[8]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[9]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[10]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[11]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[12]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[13]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[14]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0[15]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[4]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[5]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[6]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[7]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[8]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[9]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[10]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[11]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[12]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[13]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[14]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB0X[15]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[0]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[1]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[2]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[3]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[4]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[5]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[6]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[7]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[8]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[9]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[10]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[11]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[12]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[13]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[14]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[15]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[16]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[17]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[18]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[19]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[0]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[1]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[2]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[3]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[4]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[5]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[6]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[7]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[8]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[9]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[10]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[11]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[12]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[13]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[14]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[15]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[16]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[17]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[18]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[19]", PinType.INPUT,"RAM_WIRE"), + Pin("CLKB[2]", PinType.INPUT,"RAM_WIRE"), + Pin("CLKB[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ENB[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ENB[3]", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEB[2]", PinType.INPUT,"RAM_WIRE"), + Pin("GLWEB[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[4]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[5]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[6]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[7]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[8]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[9]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[10]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[11]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[12]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[13]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[14]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1[15]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[0]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[1]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[2]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[3]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[4]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[5]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[6]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[7]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[8]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[9]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[10]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[11]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[12]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[13]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[14]", PinType.INPUT,"RAM_WIRE"), + Pin("ADDRB1X[15]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[20]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[21]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[22]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[23]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[24]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[25]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[26]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[27]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[28]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[29]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[30]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[31]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[32]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[33]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[34]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[35]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[36]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[37]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[38]", PinType.INPUT,"RAM_WIRE"), + Pin("DIB[39]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[20]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[21]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[22]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[23]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[24]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[25]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[26]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[27]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[28]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[29]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[30]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[31]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[32]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[33]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[34]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[35]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[36]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[37]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[38]", PinType.INPUT,"RAM_WIRE"), + Pin("WEB[39]", PinType.INPUT,"RAM_WIRE"), Pin("F_RSTN", PinType.INPUT,"RAM_WIRE"), - Pin("DOA_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_16", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_16", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_17", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_17", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_18", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_18", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_19", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_19", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_20", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_20", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_21", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_21", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_22", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_22", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_23", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_23", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_24", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_24", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_25", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_25", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_26", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_26", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_27", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_27", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_28", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_28", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_29", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_29", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_30", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_30", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_31", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_31", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_32", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_32", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_33", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_33", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_34", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_34", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_35", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_35", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_36", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_36", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_37", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_37", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_38", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_38", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOA_39", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOAX_39", PinType.OUTPUT,"RAM_WIRE"), - Pin("CLOCKA_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("CLOCKA_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("CLOCKA_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("CLOCKA_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_16", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_16", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_17", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_17", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_18", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_18", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_19", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_19", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_20", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_20", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_21", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_21", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_22", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_22", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_23", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_23", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_24", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_24", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_25", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_25", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_26", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_26", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_27", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_27", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_28", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_28", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_29", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_29", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_30", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_30", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_31", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_31", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_32", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_32", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_33", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_33", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_34", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_34", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_35", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_35", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_36", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_36", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_37", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_37", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_38", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_38", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOB_39", PinType.OUTPUT,"RAM_WIRE"), - Pin("DOBX_39", PinType.OUTPUT,"RAM_WIRE"), - Pin("CLOCKB_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("CLOCKB_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("CLOCKB_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("CLOCKB_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC1B_ERRA_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC1B_ERRA_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC1B_ERRA_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC1B_ERRA_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC1B_ERRB_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC1B_ERRB_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC1B_ERRB_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC1B_ERRB_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC2B_ERRA_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC2B_ERRA_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC2B_ERRA_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC2B_ERRA_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC2B_ERRB_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC2B_ERRB_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC2B_ERRB_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("ECC2B_ERRB_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("F_FULL_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("F_FULL_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("F_EMPTY_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("F_EMPTY_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("F_AL_FULL_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("F_AL_FULL_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("F_AL_EMPTY_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("F_AL_EMPTY_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ERR_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ERR_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ERR_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ERR_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDR_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("FWR_ADDRX_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDR_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("FRD_ADDRX_15", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[16]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[16]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[17]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[17]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[18]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[18]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[19]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[19]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[20]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[20]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[21]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[21]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[22]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[22]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[23]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[23]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[24]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[24]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[25]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[25]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[26]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[26]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[27]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[27]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[28]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[28]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[29]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[29]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[30]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[30]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[31]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[31]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[32]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[32]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[33]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[33]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[34]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[34]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[35]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[35]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[36]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[36]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[37]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[37]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[38]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[38]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOA[39]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOAX[39]", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKA[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKA[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKA[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKA[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[16]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[16]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[17]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[17]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[18]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[18]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[19]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[19]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[20]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[20]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[21]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[21]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[22]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[22]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[23]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[23]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[24]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[24]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[25]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[25]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[26]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[26]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[27]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[27]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[28]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[28]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[29]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[29]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[30]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[30]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[31]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[31]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[32]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[32]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[33]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[33]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[34]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[34]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[35]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[35]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[36]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[36]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[37]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[37]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[38]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[38]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOB[39]", PinType.OUTPUT,"RAM_WIRE"), + Pin("DOBX[39]", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKB[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKB[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKB[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("CLOCKB[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRA[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRA[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRB[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC1B_ERRB[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRA[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRA[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRB[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("ECC2B_ERRB[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_FULL[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_FULL[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_EMPTY[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_EMPTY[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_AL_FULL[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_AL_FULL[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_AL_EMPTY[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("F_AL_EMPTY[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ERR[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ERR[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ERR[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ERR[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDR[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FWR_ADDRX[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDR[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FRD_ADDRX[15]", PinType.OUTPUT,"RAM_WIRE"), Pin("FORW_CAS_WRAO", PinType.OUTPUT,"RAM_WIRE"), Pin("FORW_CAS_WRAI", PinType.INPUT,"RAM_WIRE"), Pin("FORW_CAS_WRBO", PinType.OUTPUT,"RAM_WIRE"), @@ -890,134 +890,134 @@ PRIMITIVES_PINS = { Pin("FORW_CAS_RDAI", PinType.INPUT,"RAM_WIRE"), Pin("FORW_CAS_RDBO", PinType.OUTPUT,"RAM_WIRE"), Pin("FORW_CAS_RDBI", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAO_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_0", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_1", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_2", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_3", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_4", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_5", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_6", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_7", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_8", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_9", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_10", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_11", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_12", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_13", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_14", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAI_15", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRAO_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_0", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_1", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_2", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_3", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_4", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_5", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_6", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_7", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_8", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_9", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_10", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_11", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_12", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_13", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_14", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRAI_15", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBO_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_0", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_1", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_2", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_3", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_4", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_5", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_6", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_7", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_8", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_9", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_10", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_11", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_12", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_13", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_14", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBI_15", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_0", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_1", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_2", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_3", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_4", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_5", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_6", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_7", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_8", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_9", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_10", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_11", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_12", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_13", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_14", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_LADDRBO_15", PinType.OUTPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_0", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_1", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_2", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_3", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_4", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_5", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_6", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_7", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_8", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_9", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_10", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_11", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_12", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_13", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_14", PinType.INPUT,"RAM_WIRE"), - Pin("FORW_UADDRBI_15", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAO[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[0]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[1]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[2]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[3]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[4]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[5]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[6]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[7]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[8]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[9]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[10]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[11]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[12]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[13]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[14]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAI[15]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRAO[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[0]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[1]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[2]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[3]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[4]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[5]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[6]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[7]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[8]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[9]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[10]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[11]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[12]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[13]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[14]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRAI[15]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBO[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[0]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[1]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[2]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[3]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[4]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[5]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[6]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[7]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[8]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[9]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[10]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[11]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[12]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[13]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[14]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBI[15]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[0]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[1]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[2]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[3]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[4]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[5]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[6]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[7]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[8]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[9]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[10]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[11]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[12]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[13]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[14]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_LADDRBO[15]", PinType.OUTPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[0]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[1]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[2]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[3]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[4]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[5]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[6]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[7]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[8]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[9]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[10]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[11]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[12]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[13]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[14]", PinType.INPUT,"RAM_WIRE"), + Pin("FORW_UADDRBI[15]", PinType.INPUT,"RAM_WIRE"), Pin("FORW_UA0CLKO", PinType.OUTPUT,"RAM_WIRE"), Pin("FORW_LA0CLKI", PinType.INPUT,"RAM_WIRE"), Pin("FORW_UA0ENO", PinType.OUTPUT,"RAM_WIRE"), @@ -1071,6 +1071,316 @@ PRIMITIVES_PINS = { Pin("CLOCK3", PinType.INPUT,"RAM_WIRE"), Pin("CLOCK4", PinType.INPUT,"RAM_WIRE"), ], + "SERDES" : [ + Pin("TX_DETECT_RX_I", PinType.INPUT,"SERDES_WIRE"), + Pin("PLL_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("CLK_REG_I", PinType.INPUT,"SERDES_WIRE"), + Pin("CLK_CORE_TX_I", PinType.INPUT,"SERDES_WIRE"), + Pin("CLK_CORE_RX_I", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_WE_I", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_EN_I", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_PCS_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_PMA_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_PRBS_FORCE_ERR_I", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_POLARITY_I", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_8B10B_EN_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_PMA_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_EQA_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_CDR_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_PCS_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_BUF_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_PRBS_CNT_RESET_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_EN_EI_DETECTOR_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_COMMA_DETECT_EN_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_SLIDE_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_POLARITY_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_8B10B_EN_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_MCOMMA_ALIGN_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_PCOMMA_ALIGN_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_NOT_IN_TABLE_O[7]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_NOT_IN_TABLE_O[6]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_NOT_IN_TABLE_O[5]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_NOT_IN_TABLE_O[4]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_NOT_IN_TABLE_O[3]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_NOT_IN_TABLE_O[2]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_NOT_IN_TABLE_O[1]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_NOT_IN_TABLE_O[0]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_COMMA_O[7]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_COMMA_O[6]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_COMMA_O[5]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_COMMA_O[4]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_COMMA_O[3]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_COMMA_O[2]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_COMMA_O[1]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_COMMA_O[0]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_ADDR_I[7]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_ADDR_I[6]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_ADDR_I[5]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_ADDR_I[4]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_ADDR_I[3]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_ADDR_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_ADDR_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_ADDR_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_IS_K_I[7]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_IS_K_I[6]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_IS_K_I[5]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_IS_K_I[4]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_IS_K_I[3]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_IS_K_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_IS_K_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_IS_K_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_8B10B_BYPASS_I[7]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_8B10B_BYPASS_I[6]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_8B10B_BYPASS_I[5]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_8B10B_BYPASS_I[4]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_8B10B_BYPASS_I[3]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_8B10B_BYPASS_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_8B10B_BYPASS_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_8B10B_BYPASS_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_8B10B_BYPASS_I[7]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_8B10B_BYPASS_I[6]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_8B10B_BYPASS_I[5]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_8B10B_BYPASS_I[4]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_8B10B_BYPASS_I[3]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_8B10B_BYPASS_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_8B10B_BYPASS_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_8B10B_BYPASS_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPMODE_I[7]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPMODE_I[6]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPMODE_I[5]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPMODE_I[4]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPMODE_I[3]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPMODE_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPMODE_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPMODE_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPVAL_I[7]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPVAL_I[6]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPVAL_I[5]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPVAL_I[4]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPVAL_I[3]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPVAL_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPVAL_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_CHAR_DISPVAL_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[63]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[62]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[61]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[60]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[59]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[58]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[57]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[56]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[55]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[54]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[53]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[52]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[51]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[50]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[49]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[48]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[47]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[46]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[45]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[44]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[43]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[42]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[41]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[40]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[39]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[38]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[37]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[36]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[35]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[34]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[33]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[32]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[31]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[30]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[29]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[28]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[27]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[26]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[25]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[24]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[23]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[22]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[21]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[20]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[19]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[18]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[17]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[16]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[15]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[14]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[13]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[12]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[11]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[10]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[9]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[8]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[7]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[6]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[5]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[4]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[3]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_DATA_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[15]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[14]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[13]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[12]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[11]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[10]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[9]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[8]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[7]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[6]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[5]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[4]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[3]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[2]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[1]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DO_O[0]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[15]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[14]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[13]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[12]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[11]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[10]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[9]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[8]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[7]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[6]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[5]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[4]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[3]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_DI_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[15]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[14]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[13]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[12]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[11]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[10]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[9]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[8]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[7]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[6]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[5]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[4]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[3]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("REGFILE_MASK_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_K_O[7]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_K_O[6]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_K_O[5]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_K_O[4]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_K_O[3]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_K_O[2]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_K_O[1]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_CHAR_IS_K_O[0]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DISP_ERR_O[7]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DISP_ERR_O[6]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DISP_ERR_O[5]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DISP_ERR_O[4]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DISP_ERR_O[3]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DISP_ERR_O[2]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DISP_ERR_O[1]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DISP_ERR_O[0]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[63]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[62]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[61]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[60]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[59]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[58]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[57]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[56]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[55]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[54]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[53]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[52]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[51]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[50]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[49]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[48]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[47]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[46]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[45]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[44]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[43]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[42]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[41]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[40]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[39]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[38]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[37]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[36]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[35]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[34]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[33]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[32]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[31]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[30]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[29]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[28]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[27]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[26]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[25]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[24]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[23]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[22]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[21]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[20]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[19]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[18]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[17]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[16]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[15]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[14]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[13]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[12]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[11]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[10]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[9]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[8]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[7]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[6]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[5]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[4]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[3]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[2]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[1]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_DATA_O[0]", PinType.OUTPUT,"SERDES_WIRE"), + Pin("TX_DETECT_RX_DONE_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("TX_DETECT_RX_PRESENT_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("CLK_CORE_RX_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("CLK_CORE_PLL_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("TX_BUF_ERR_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("TX_RESETDONE_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("REGFILE_RDY_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_PRBS_ERR_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_BUF_ERR_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_BYTE_IS_ALIGNED_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_BYTE_REALIGN_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_RESETDONE_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("RX_EI_EN_O", PinType.OUTPUT,"SERDES_WIRE"), + Pin("LOOPBACK_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("LOOPBACK_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("LOOPBACK_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_PRBS_SEL_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_PRBS_SEL_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_PRBS_SEL_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_PRBS_SEL_I[2]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_PRBS_SEL_I[1]", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_PRBS_SEL_I[0]", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_POWERDOWN_N_I", PinType.INPUT,"SERDES_WIRE"), + Pin("RX_POWERDOWN_N_I", PinType.INPUT,"SERDES_WIRE"), + Pin("TX_ELEC_IDLE_I", PinType.INPUT,"SERDES_WIRE"), + ], } def get_groups_for_type(type): @@ -1118,6 +1428,8 @@ def get_primitives_for_type(type): primitives.append(Primitive("CPE_HALF_L","CPE_HALF_L",1)) if "RAM" in type: primitives.append(Primitive("RAM","RAM",4)) + if "SERDES" in type: + primitives.append(Primitive("SERDES","SERDES",4)) if "GPIO" in type: primitives.append(Primitive("GPIO","GPIO",0)) if "PLL" in type: @@ -2297,596 +2609,906 @@ class Die: self.connect_ddr_i(96,1,2,'S2') self.connect_ddr_i(48,1,1,'S3') + def create_serdes(self, x, y): + self.create_conn(x+6,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_DETECT_RX_I") + self.create_conn(x+6,y+5,"CPE.RAM_O2", x,y,"SERDES.PLL_RESET_I") + self.create_conn(x+6,y+5,"CPE.RAM_O1", x,y,"SERDES.CLK_REG_I") + self.create_conn(x+6,y+4,"CPE.RAM_O2", x,y,"SERDES.CLK_CORE_TX_I") + self.create_conn(x+6,y+4,"CPE.RAM_O1", x,y,"SERDES.CLK_CORE_RX_I") + self.create_conn(x+6,y+3,"CPE.RAM_O2", x,y,"SERDES.REGFILE_WE_I") + self.create_conn(x+6,y+3,"CPE.RAM_O1", x,y,"SERDES.REGFILE_EN_I") + self.create_conn(x+6,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_RESET_I") + self.create_conn(x+6,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_PCS_RESET_I") + self.create_conn(x+6,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_PMA_RESET_I") + self.create_conn(x+6,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_PRBS_FORCE_ERR_I") + self.create_conn(x+6,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_POLARITY_I") + self.create_conn(x+6,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_EN_I") + self.create_conn(x+7,y+6,"CPE.RAM_O2", x,y,"SERDES.RX_RESET_I") + self.create_conn(x+7,y+6,"CPE.RAM_O1", x,y,"SERDES.RX_PMA_RESET_I") + self.create_conn(x+7,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_EQA_RESET_I") + self.create_conn(x+7,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_CDR_RESET_I") + self.create_conn(x+7,y+4,"CPE.RAM_O2", x,y,"SERDES.RX_PCS_RESET_I") + self.create_conn(x+7,y+4,"CPE.RAM_O1", x,y,"SERDES.RX_BUF_RESET_I") + self.create_conn(x+7,y+3,"CPE.RAM_O2", x,y,"SERDES.RX_PRBS_CNT_RESET_I") + self.create_conn(x+7,y+3,"CPE.RAM_O1", x,y,"SERDES.RX_EN_EI_DETECTOR_I") + self.create_conn(x+7,y+2,"CPE.RAM_O2", x,y,"SERDES.RX_COMMA_DETECT_EN_I") + self.create_conn(x+7,y+2,"CPE.RAM_O1", x,y,"SERDES.RX_SLIDE_I") + self.create_conn(x+7,y+1,"CPE.RAM_O2", x,y,"SERDES.RX_POLARITY_I") + self.create_conn(x+7,y+1,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_EN_I") + self.create_conn(x+7,y+0,"CPE.RAM_O2", x,y,"SERDES.RX_MCOMMA_ALIGN_I") + self.create_conn(x+7,y+0,"CPE.RAM_O1", x,y,"SERDES.RX_PCOMMA_ALIGN_I") + self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[7]", x+8,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[6]", x+8,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[5]", x+9,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[4]", x+9,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[3]", x+10,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[2]", x+10,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[1]", x+11,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[0]", x+11,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[7]", x+12,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[6]", x+12,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[5]", x+13,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[4]", x+13,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[3]", x+14,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[2]", x+14,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[1]", x+15,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[0]", x+15,y+7,"CPE.RAM_I2") + self.create_conn(x+8,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_ADDR_I[7]") + self.create_conn(x+8,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_ADDR_I[6]") + self.create_conn(x+9,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_ADDR_I[5]") + self.create_conn(x+9,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_ADDR_I[4]") + self.create_conn(x+10,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_ADDR_I[3]") + self.create_conn(x+10,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_ADDR_I[2]") + self.create_conn(x+11,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_ADDR_I[1]") + self.create_conn(x+11,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_ADDR_I[0]") + self.create_conn(x+12,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_IS_K_I[7]") + self.create_conn(x+12,y+6,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_IS_K_I[6]") + self.create_conn(x+13,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_IS_K_I[5]") + self.create_conn(x+13,y+6,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_IS_K_I[4]") + self.create_conn(x+14,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_IS_K_I[3]") + self.create_conn(x+14,y+6,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_IS_K_I[2]") + self.create_conn(x+15,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_IS_K_I[1]") + self.create_conn(x+15,y+6,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_IS_K_I[0]") + self.create_conn(x+8,y+5,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_BYPASS_I[7]") + self.create_conn(x+8,y+5,"CPE.RAM_O2", x,y,"SERDES.TX_8B10B_BYPASS_I[6]") + self.create_conn(x+9,y+5,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_BYPASS_I[5]") + self.create_conn(x+9,y+5,"CPE.RAM_O2", x,y,"SERDES.TX_8B10B_BYPASS_I[4]") + self.create_conn(x+10,y+5,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_BYPASS_I[3]") + self.create_conn(x+10,y+5,"CPE.RAM_O2", x,y,"SERDES.TX_8B10B_BYPASS_I[2]") + self.create_conn(x+11,y+5,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_BYPASS_I[1]") + self.create_conn(x+11,y+5,"CPE.RAM_O2", x,y,"SERDES.TX_8B10B_BYPASS_I[0]") + self.create_conn(x+12,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_BYPASS_I[7]") + self.create_conn(x+12,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_8B10B_BYPASS_I[6]") + self.create_conn(x+13,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_BYPASS_I[5]") + self.create_conn(x+13,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_8B10B_BYPASS_I[4]") + self.create_conn(x+14,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_BYPASS_I[3]") + self.create_conn(x+14,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_8B10B_BYPASS_I[2]") + self.create_conn(x+15,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_BYPASS_I[1]") + self.create_conn(x+15,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_8B10B_BYPASS_I[0]") + self.create_conn(x+8,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPMODE_I[7]") + self.create_conn(x+8,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPMODE_I[6]") + self.create_conn(x+9,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPMODE_I[5]") + self.create_conn(x+9,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPMODE_I[4]") + self.create_conn(x+10,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPMODE_I[3]") + self.create_conn(x+10,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPMODE_I[2]") + self.create_conn(x+11,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPMODE_I[1]") + self.create_conn(x+11,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPMODE_I[0]") + self.create_conn(x+12,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPVAL_I[7]") + self.create_conn(x+12,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPVAL_I[6]") + self.create_conn(x+13,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPVAL_I[5]") + self.create_conn(x+13,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPVAL_I[4]") + self.create_conn(x+14,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPVAL_I[3]") + self.create_conn(x+14,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPVAL_I[2]") + self.create_conn(x+15,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPVAL_I[1]") + self.create_conn(x+15,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPVAL_I[0]") + self.create_conn(x+8,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[63]") + self.create_conn(x+8,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[62]") + self.create_conn(x+9,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[61]") + self.create_conn(x+9,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[60]") + self.create_conn(x+10,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[59]") + self.create_conn(x+10,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[58]") + self.create_conn(x+11,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[57]") + self.create_conn(x+11,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[56]") + self.create_conn(x+12,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[55]") + self.create_conn(x+12,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[54]") + self.create_conn(x+13,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[53]") + self.create_conn(x+13,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[52]") + self.create_conn(x+14,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[51]") + self.create_conn(x+14,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[50]") + self.create_conn(x+15,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[49]") + self.create_conn(x+15,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[48]") + self.create_conn(x+8,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[47]") + self.create_conn(x+8,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[46]") + self.create_conn(x+9,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[45]") + self.create_conn(x+9,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[44]") + self.create_conn(x+10,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[43]") + self.create_conn(x+10,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[42]") + self.create_conn(x+11,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[41]") + self.create_conn(x+11,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[40]") + self.create_conn(x+12,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[39]") + self.create_conn(x+12,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[38]") + self.create_conn(x+13,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[37]") + self.create_conn(x+13,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[36]") + self.create_conn(x+14,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[35]") + self.create_conn(x+14,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[34]") + self.create_conn(x+15,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[33]") + self.create_conn(x+15,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[32]") + self.create_conn(x+8,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[31]") + self.create_conn(x+8,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[30]") + self.create_conn(x+9,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[29]") + self.create_conn(x+9,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[28]") + self.create_conn(x+10,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[27]") + self.create_conn(x+10,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[26]") + self.create_conn(x+11,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[25]") + self.create_conn(x+11,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[24]") + self.create_conn(x+12,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[23]") + self.create_conn(x+12,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[22]") + self.create_conn(x+13,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[21]") + self.create_conn(x+13,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[20]") + self.create_conn(x+14,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[19]") + self.create_conn(x+14,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[18]") + self.create_conn(x+15,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[17]") + self.create_conn(x+15,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[16]") + self.create_conn(x+8,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[15]") + self.create_conn(x+8,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[14]") + self.create_conn(x+9,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[13]") + self.create_conn(x+9,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[12]") + self.create_conn(x+10,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[11]") + self.create_conn(x+10,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[10]") + self.create_conn(x+11,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[9]") + self.create_conn(x+11,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[8]") + self.create_conn(x+12,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[7]") + self.create_conn(x+12,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[6]") + self.create_conn(x+13,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[5]") + self.create_conn(x+13,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[4]") + self.create_conn(x+14,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[3]") + self.create_conn(x+14,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[2]") + self.create_conn(x+15,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[1]") + self.create_conn(x+15,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[0]") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[15]", x+16,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[14]", x+16,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[13]", x+17,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[12]", x+17,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[11]", x+18,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[10]", x+18,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[9]", x+19,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[8]", x+19,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[7]", x+20,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[6]", x+20,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[5]", x+21,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[4]", x+21,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[3]", x+22,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[2]", x+22,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[1]", x+23,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.REGFILE_DO_O[0]", x+23,y+7,"CPE.RAM_I2") + self.create_conn(x+16,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[15]") + self.create_conn(x+16,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[14]") + self.create_conn(x+17,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[13]") + self.create_conn(x+17,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[12]") + self.create_conn(x+18,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[11]") + self.create_conn(x+18,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[10]") + self.create_conn(x+19,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[9]") + self.create_conn(x+19,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[8]") + self.create_conn(x+20,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[7]") + self.create_conn(x+20,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[6]") + self.create_conn(x+21,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[5]") + self.create_conn(x+21,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[4]") + self.create_conn(x+22,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[3]") + self.create_conn(x+22,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[2]") + self.create_conn(x+23,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[1]") + self.create_conn(x+23,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[0]") + self.create_conn(x+16,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[15]") + self.create_conn(x+16,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[14]") + self.create_conn(x+17,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[13]") + self.create_conn(x+17,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[12]") + self.create_conn(x+18,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[11]") + self.create_conn(x+18,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[10]") + self.create_conn(x+19,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[9]") + self.create_conn(x+19,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[8]") + self.create_conn(x+20,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[7]") + self.create_conn(x+20,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[6]") + self.create_conn(x+21,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[5]") + self.create_conn(x+21,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[4]") + self.create_conn(x+22,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[3]") + self.create_conn(x+22,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[2]") + self.create_conn(x+23,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[1]") + self.create_conn(x+23,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[0]") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[7]", x+16,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[6]", x+16,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[5]", x+17,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[4]", x+17,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[3]", x+18,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[2]", x+18,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[1]", x+19,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[0]", x+19,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[7]", x+20,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[6]", x+20,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[5]", x+21,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[4]", x+21,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[3]", x+22,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[2]", x+22,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[1]", x+23,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[0]", x+23,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[63]", x+16,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[62]", x+16,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[61]", x+17,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[60]", x+17,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[59]", x+18,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[58]", x+18,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[57]", x+19,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[56]", x+19,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[55]", x+20,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[54]", x+20,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[53]", x+21,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[52]", x+21,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[51]", x+22,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[50]", x+22,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[49]", x+23,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[48]", x+23,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[47]", x+16,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[46]", x+16,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[45]", x+17,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[44]", x+17,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[43]", x+18,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[42]", x+18,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[41]", x+19,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[40]", x+19,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[39]", x+20,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[38]", x+20,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[37]", x+21,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[36]", x+21,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[35]", x+22,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[34]", x+22,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[33]", x+23,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[32]", x+23,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[31]", x+16,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[30]", x+16,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[29]", x+17,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[28]", x+17,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[27]", x+18,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[26]", x+18,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[25]", x+19,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[24]", x+19,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[23]", x+20,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[22]", x+20,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[21]", x+21,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[20]", x+21,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[19]", x+22,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[18]", x+22,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[17]", x+23,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[16]", x+23,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[15]", x+16,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[14]", x+16,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[13]", x+17,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[12]", x+17,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[11]", x+18,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[10]", x+18,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[9]", x+19,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[8]", x+19,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[7]", x+20,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[6]", x+20,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[5]", x+21,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[4]", x+21,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[3]", x+22,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[2]", x+22,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_DATA_O[1]", x+23,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_DATA_O[0]", x+23,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.TX_DETECT_RX_DONE_O", x+24,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.TX_DETECT_RX_PRESENT_O", x+24,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.CLK_CORE_RX_O", x+24,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.CLK_CORE_PLL_O", x+24,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.TX_BUF_ERR_O", x+24,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.TX_RESETDONE_O", x+24,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.REGFILE_RDY_O", x+24,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_PRBS_ERR_O", x+24,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_BUF_ERR_O", x+24,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_BYTE_IS_ALIGNED_O", x+24,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_BYTE_REALIGN_O", x+24,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"SERDES.RX_RESETDONE_O", x+24,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"SERDES.RX_EI_EN_O", x+24,y+0,"CPE.RAM_I2") + self.create_conn(x+25,y+5,"CPE.RAM_O1", x,y,"SERDES.LOOPBACK_I[2]") + self.create_conn(x+25,y+5,"CPE.RAM_O2", x,y,"SERDES.LOOPBACK_I[1]") + self.create_conn(x+25,y+4,"CPE.RAM_O2", x,y,"SERDES.LOOPBACK_I[0]") + self.create_conn(x+25,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_PRBS_SEL_I[2]") + self.create_conn(x+25,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_PRBS_SEL_I[1]") + self.create_conn(x+25,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_PRBS_SEL_I[0]") + self.create_conn(x+25,y+1,"CPE.RAM_O1", x,y,"SERDES.RX_PRBS_SEL_I[2]") + self.create_conn(x+25,y+1,"CPE.RAM_O2", x,y,"SERDES.RX_PRBS_SEL_I[1]") + self.create_conn(x+25,y+0,"CPE.RAM_O2", x,y,"SERDES.RX_PRBS_SEL_I[0]") + self.create_conn(x+25,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_POWERDOWN_N_I") + self.create_conn(x+25,y+2,"CPE.RAM_O1", x,y,"SERDES.RX_POWERDOWN_N_I") + self.create_conn(x+25,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_ELEC_IDLE_I") + def create_ram(self, x, y): - self.create_conn(x-3,y+2,"CPE.RAM_O1", x,y,"RAM.C_ADDRA_0") - self.create_conn(x-3,y+2,"CPE.RAM_O2", x,y,"RAM.C_ADDRA_1") - self.create_conn(x-3,y+3,"CPE.RAM_O1", x,y,"RAM.C_ADDRA_2") - self.create_conn(x-3,y+3,"CPE.RAM_O2", x,y,"RAM.C_ADDRA_3") - self.create_conn(x-3,y+4,"CPE.RAM_O1", x,y,"RAM.C_ADDRA_4") - self.create_conn(x-3,y+4,"CPE.RAM_O2", x,y,"RAM.C_ADDRA_5") - self.create_conn(x-3,y+5,"CPE.RAM_O1", x,y,"RAM.C_ADDRA_6") - self.create_conn(x-3,y+5,"CPE.RAM_O2", x,y,"RAM.C_ADDRA_7") - self.create_conn(x+2,y+2,"CPE.RAM_O1", x,y,"RAM.C_ADDRB_0") - self.create_conn(x+2,y+2,"CPE.RAM_O2", x,y,"RAM.C_ADDRB_1") - self.create_conn(x+2,y+3,"CPE.RAM_O1", x,y,"RAM.C_ADDRB_2") - self.create_conn(x+2,y+3,"CPE.RAM_O2", x,y,"RAM.C_ADDRB_3") - self.create_conn(x+2,y+4,"CPE.RAM_O1", x,y,"RAM.C_ADDRB_4") - self.create_conn(x+2,y+4,"CPE.RAM_O2", x,y,"RAM.C_ADDRB_5") - self.create_conn(x+2,y+5,"CPE.RAM_O1", x,y,"RAM.C_ADDRB_6") - self.create_conn(x+2,y+5,"CPE.RAM_O2", x,y,"RAM.C_ADDRB_7") - self.create_conn(x-6,y+0,"CPE.RAM_O1", x,y,"RAM.CLKA_0") - self.create_conn(x-3,y+0,"CPE.RAM_O1", x,y,"RAM.CLKA_1") - self.create_conn(x-6,y+1,"CPE.RAM_O1", x,y,"RAM.ENA_0") - self.create_conn(x-3,y+1,"CPE.RAM_O1", x,y,"RAM.ENA_1") - self.create_conn(x-6,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEA_0") - self.create_conn(x-3,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEA_1") - self.create_conn(x-5,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0_0") - self.create_conn(x-5,y+0,"CPE.RAM_O2", x,y,"RAM.ADDRA0_1") - self.create_conn(x-5,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0_2") - self.create_conn(x-5,y+1,"CPE.RAM_O2", x,y,"RAM.ADDRA0_3") - self.create_conn(x-5,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0_4") - self.create_conn(x-5,y+2,"CPE.RAM_O2", x,y,"RAM.ADDRA0_5") - self.create_conn(x-5,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0_6") - self.create_conn(x-5,y+3,"CPE.RAM_O2", x,y,"RAM.ADDRA0_7") - self.create_conn(x-5,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0_8") - self.create_conn(x-5,y+4,"CPE.RAM_O2", x,y,"RAM.ADDRA0_9") - self.create_conn(x-5,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0_10") - self.create_conn(x-5,y+5,"CPE.RAM_O2", x,y,"RAM.ADDRA0_11") - self.create_conn(x-5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0_12") - self.create_conn(x-5,y+6,"CPE.RAM_O2", x,y,"RAM.ADDRA0_13") - self.create_conn(x-5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0_14") - self.create_conn(x-5,y+7,"CPE.RAM_O2", x,y,"RAM.ADDRA0_15") - self.create_conn(x-5,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_0") - self.create_conn(x-4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_1") - self.create_conn(x-5,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_2") - self.create_conn(x-4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_3") - self.create_conn(x-5,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_4") - self.create_conn(x-4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_5") - self.create_conn(x-5,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_6") - self.create_conn(x-4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_7") - self.create_conn(x-5,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_8") - self.create_conn(x-4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_9") - self.create_conn(x-5,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_10") - self.create_conn(x-4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_11") - self.create_conn(x-6,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_12") - self.create_conn(x-5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_13") - self.create_conn(x-6,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_14") - self.create_conn(x-5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0X_15") - self.create_conn(x-1,y+0,"CPE.RAM_O1", x,y,"RAM.DIA_0") - self.create_conn(x-1,y+0,"CPE.RAM_O2", x,y,"RAM.DIA_1") - self.create_conn(x-1,y+1,"CPE.RAM_O1", x,y,"RAM.DIA_2") - self.create_conn(x-1,y+1,"CPE.RAM_O2", x,y,"RAM.DIA_3") - self.create_conn(x-1,y+2,"CPE.RAM_O1", x,y,"RAM.DIA_4") - self.create_conn(x-1,y+2,"CPE.RAM_O2", x,y,"RAM.DIA_5") - self.create_conn(x-1,y+3,"CPE.RAM_O1", x,y,"RAM.DIA_6") - self.create_conn(x-1,y+3,"CPE.RAM_O2", x,y,"RAM.DIA_7") - self.create_conn(x-1,y+4,"CPE.RAM_O1", x,y,"RAM.DIA_8") - self.create_conn(x-1,y+4,"CPE.RAM_O2", x,y,"RAM.DIA_9") - self.create_conn(x-1,y+5,"CPE.RAM_O1", x,y,"RAM.DIA_10") - self.create_conn(x-1,y+5,"CPE.RAM_O2", x,y,"RAM.DIA_11") - self.create_conn(x-1,y+6,"CPE.RAM_O1", x,y,"RAM.DIA_12") - self.create_conn(x-1,y+6,"CPE.RAM_O2", x,y,"RAM.DIA_13") - self.create_conn(x-1,y+7,"CPE.RAM_O1", x,y,"RAM.DIA_14") - self.create_conn(x-1,y+7,"CPE.RAM_O2", x,y,"RAM.DIA_15") - self.create_conn(x-3,y+6,"CPE.RAM_O1", x,y,"RAM.DIA_16") - self.create_conn(x-3,y+6,"CPE.RAM_O2", x,y,"RAM.DIA_17") - self.create_conn(x-3,y+7,"CPE.RAM_O1", x,y,"RAM.DIA_18") - self.create_conn(x-3,y+7,"CPE.RAM_O2", x,y,"RAM.DIA_19") - self.create_conn(x-2,y+0,"CPE.RAM_O1", x,y,"RAM.WEA_0") - self.create_conn(x-2,y+0,"CPE.RAM_O2", x,y,"RAM.WEA_1") - self.create_conn(x-2,y+1,"CPE.RAM_O1", x,y,"RAM.WEA_2") - self.create_conn(x-2,y+1,"CPE.RAM_O2", x,y,"RAM.WEA_3") - self.create_conn(x-2,y+2,"CPE.RAM_O1", x,y,"RAM.WEA_4") - self.create_conn(x-2,y+2,"CPE.RAM_O2", x,y,"RAM.WEA_5") - self.create_conn(x-2,y+3,"CPE.RAM_O1", x,y,"RAM.WEA_6") - self.create_conn(x-2,y+3,"CPE.RAM_O2", x,y,"RAM.WEA_7") - self.create_conn(x-2,y+4,"CPE.RAM_O1", x,y,"RAM.WEA_8") - self.create_conn(x-2,y+4,"CPE.RAM_O2", x,y,"RAM.WEA_9") - self.create_conn(x-2,y+5,"CPE.RAM_O1", x,y,"RAM.WEA_10") - self.create_conn(x-2,y+5,"CPE.RAM_O2", x,y,"RAM.WEA_11") - self.create_conn(x-2,y+6,"CPE.RAM_O1", x,y,"RAM.WEA_12") - self.create_conn(x-2,y+6,"CPE.RAM_O2", x,y,"RAM.WEA_13") - self.create_conn(x-2,y+7,"CPE.RAM_O1", x,y,"RAM.WEA_14") - self.create_conn(x-2,y+7,"CPE.RAM_O2", x,y,"RAM.WEA_15") - self.create_conn(x-4,y+6,"CPE.RAM_O1", x,y,"RAM.WEA_16") - self.create_conn(x-4,y+6,"CPE.RAM_O2", x,y,"RAM.WEA_17") - self.create_conn(x-4,y+7,"CPE.RAM_O1", x,y,"RAM.WEA_18") - self.create_conn(x-4,y+7,"CPE.RAM_O2", x,y,"RAM.WEA_19") - self.create_conn(x-6,y+8,"CPE.RAM_O1", x,y,"RAM.CLKA_2") - self.create_conn(x-3,y+8,"CPE.RAM_O1", x,y,"RAM.CLKA_3") - self.create_conn(x-6,y+9,"CPE.RAM_O1", x,y,"RAM.ENA_2") - self.create_conn(x-3,y+9,"CPE.RAM_O1", x,y,"RAM.ENA_3") - self.create_conn(x-6,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEA_2") - self.create_conn(x-3,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEA_3") - self.create_conn(x-5,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1_0") - self.create_conn(x-5,y+8,"CPE.RAM_O2", x,y,"RAM.ADDRA1_1") - self.create_conn(x-5,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1_2") - self.create_conn(x-5,y+9,"CPE.RAM_O2", x,y,"RAM.ADDRA1_3") - self.create_conn(x-5,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1_4") - self.create_conn(x-5,y+10,"CPE.RAM_O2", x,y,"RAM.ADDRA1_5") - self.create_conn(x-5,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1_6") - self.create_conn(x-5,y+11,"CPE.RAM_O2", x,y,"RAM.ADDRA1_7") - self.create_conn(x-5,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1_8") - self.create_conn(x-5,y+12,"CPE.RAM_O2", x,y,"RAM.ADDRA1_9") - self.create_conn(x-5,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1_10") - self.create_conn(x-5,y+13,"CPE.RAM_O2", x,y,"RAM.ADDRA1_11") - self.create_conn(x-5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1_12") - self.create_conn(x-5,y+14,"CPE.RAM_O2", x,y,"RAM.ADDRA1_13") - self.create_conn(x-5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1_14") - self.create_conn(x-5,y+15,"CPE.RAM_O2", x,y,"RAM.ADDRA1_15") - self.create_conn(x-5,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_0") - self.create_conn(x-4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_1") - self.create_conn(x-5,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_2") - self.create_conn(x-4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_3") - self.create_conn(x-5,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_4") - self.create_conn(x-4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_5") - self.create_conn(x-5,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_6") - self.create_conn(x-4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_7") - self.create_conn(x-5,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_8") - self.create_conn(x-4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_9") - self.create_conn(x-5,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_10") - self.create_conn(x-4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_11") - self.create_conn(x-6,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_12") - self.create_conn(x-5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_13") - self.create_conn(x-6,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_14") - self.create_conn(x-5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1X_15") - self.create_conn(x-1,y+8,"CPE.RAM_O1", x,y,"RAM.DIA_20") - self.create_conn(x-1,y+8,"CPE.RAM_O2", x,y,"RAM.DIA_21") - self.create_conn(x-1,y+9,"CPE.RAM_O1", x,y,"RAM.DIA_22") - self.create_conn(x-1,y+9,"CPE.RAM_O2", x,y,"RAM.DIA_23") - self.create_conn(x-1,y+10,"CPE.RAM_O1", x,y,"RAM.DIA_24") - self.create_conn(x-1,y+10,"CPE.RAM_O2", x,y,"RAM.DIA_25") - self.create_conn(x-1,y+11,"CPE.RAM_O1", x,y,"RAM.DIA_26") - self.create_conn(x-1,y+11,"CPE.RAM_O2", x,y,"RAM.DIA_27") - self.create_conn(x-1,y+12,"CPE.RAM_O1", x,y,"RAM.DIA_28") - self.create_conn(x-1,y+12,"CPE.RAM_O2", x,y,"RAM.DIA_29") - self.create_conn(x-1,y+13,"CPE.RAM_O1", x,y,"RAM.DIA_30") - self.create_conn(x-1,y+13,"CPE.RAM_O2", x,y,"RAM.DIA_31") - self.create_conn(x-1,y+14,"CPE.RAM_O1", x,y,"RAM.DIA_32") - self.create_conn(x-1,y+14,"CPE.RAM_O2", x,y,"RAM.DIA_33") - self.create_conn(x-1,y+15,"CPE.RAM_O1", x,y,"RAM.DIA_34") - self.create_conn(x-1,y+15,"CPE.RAM_O2", x,y,"RAM.DIA_35") - self.create_conn(x-3,y+14,"CPE.RAM_O1", x,y,"RAM.DIA_36") - self.create_conn(x-3,y+14,"CPE.RAM_O2", x,y,"RAM.DIA_37") - self.create_conn(x-3,y+15,"CPE.RAM_O1", x,y,"RAM.DIA_38") - self.create_conn(x-3,y+15,"CPE.RAM_O2", x,y,"RAM.DIA_39") - self.create_conn(x-2,y+8,"CPE.RAM_O1", x,y,"RAM.WEA_20") - self.create_conn(x-2,y+8,"CPE.RAM_O2", x,y,"RAM.WEA_21") - self.create_conn(x-2,y+9,"CPE.RAM_O1", x,y,"RAM.WEA_22") - self.create_conn(x-2,y+9,"CPE.RAM_O2", x,y,"RAM.WEA_23") - self.create_conn(x-2,y+10,"CPE.RAM_O1", x,y,"RAM.WEA_24") - self.create_conn(x-2,y+10,"CPE.RAM_O2", x,y,"RAM.WEA_25") - self.create_conn(x-2,y+11,"CPE.RAM_O1", x,y,"RAM.WEA_26") - self.create_conn(x-2,y+11,"CPE.RAM_O2", x,y,"RAM.WEA_27") - self.create_conn(x-2,y+12,"CPE.RAM_O1", x,y,"RAM.WEA_28") - self.create_conn(x-2,y+12,"CPE.RAM_O2", x,y,"RAM.WEA_29") - self.create_conn(x-2,y+13,"CPE.RAM_O1", x,y,"RAM.WEA_30") - self.create_conn(x-2,y+13,"CPE.RAM_O2", x,y,"RAM.WEA_31") - self.create_conn(x-2,y+14,"CPE.RAM_O1", x,y,"RAM.WEA_32") - self.create_conn(x-2,y+14,"CPE.RAM_O2", x,y,"RAM.WEA_33") - self.create_conn(x-2,y+15,"CPE.RAM_O1", x,y,"RAM.WEA_34") - self.create_conn(x-2,y+15,"CPE.RAM_O2", x,y,"RAM.WEA_35") - self.create_conn(x-4,y+14,"CPE.RAM_O1", x,y,"RAM.WEA_36") - self.create_conn(x-4,y+14,"CPE.RAM_O2", x,y,"RAM.WEA_37") - self.create_conn(x-4,y+15,"CPE.RAM_O1", x,y,"RAM.WEA_38") - self.create_conn(x-4,y+15,"CPE.RAM_O2", x,y,"RAM.WEA_39") - self.create_conn(x+2,y+0,"CPE.RAM_O1", x,y,"RAM.CLKB_0") - self.create_conn(x+5,y+0,"CPE.RAM_O1", x,y,"RAM.CLKB_1") - self.create_conn(x+2,y+1,"CPE.RAM_O1", x,y,"RAM.ENB_0") - self.create_conn(x+5,y+1,"CPE.RAM_O1", x,y,"RAM.ENB_1") - self.create_conn(x+2,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEB_0") - self.create_conn(x+5,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEB_1") - self.create_conn(x+4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0_0") - self.create_conn(x+4,y+0,"CPE.RAM_O2", x,y,"RAM.ADDRB0_1") - self.create_conn(x+4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0_2") - self.create_conn(x+4,y+1,"CPE.RAM_O2", x,y,"RAM.ADDRB0_3") - self.create_conn(x+4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0_4") - self.create_conn(x+4,y+2,"CPE.RAM_O2", x,y,"RAM.ADDRB0_5") - self.create_conn(x+4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0_6") - self.create_conn(x+4,y+3,"CPE.RAM_O2", x,y,"RAM.ADDRB0_7") - self.create_conn(x+4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0_8") - self.create_conn(x+4,y+4,"CPE.RAM_O2", x,y,"RAM.ADDRB0_9") - self.create_conn(x+4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0_10") - self.create_conn(x+4,y+5,"CPE.RAM_O2", x,y,"RAM.ADDRB0_11") - self.create_conn(x+4,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0_12") - self.create_conn(x+4,y+6,"CPE.RAM_O2", x,y,"RAM.ADDRB0_13") - self.create_conn(x+4,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0_14") - self.create_conn(x+4,y+7,"CPE.RAM_O2", x,y,"RAM.ADDRB0_15") - self.create_conn(x+3,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_0") - self.create_conn(x+4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_1") - self.create_conn(x+3,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_2") - self.create_conn(x+4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_3") - self.create_conn(x+3,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_4") - self.create_conn(x+4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_5") - self.create_conn(x+3,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_6") - self.create_conn(x+4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_7") - self.create_conn(x+3,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_8") - self.create_conn(x+4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_9") - self.create_conn(x+3,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_10") - self.create_conn(x+4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_11") - self.create_conn(x+4,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_12") - self.create_conn(x+5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_13") - self.create_conn(x+4,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_14") - self.create_conn(x+5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0X_15") - self.create_conn(x+1,y+0,"CPE.RAM_O1", x,y,"RAM.DIB_0") - self.create_conn(x+1,y+0,"CPE.RAM_O2", x,y,"RAM.DIB_1") - self.create_conn(x+1,y+1,"CPE.RAM_O1", x,y,"RAM.DIB_2") - self.create_conn(x+1,y+1,"CPE.RAM_O2", x,y,"RAM.DIB_3") - self.create_conn(x+1,y+2,"CPE.RAM_O1", x,y,"RAM.DIB_4") - self.create_conn(x+1,y+2,"CPE.RAM_O2", x,y,"RAM.DIB_5") - self.create_conn(x+1,y+3,"CPE.RAM_O1", x,y,"RAM.DIB_6") - self.create_conn(x+1,y+3,"CPE.RAM_O2", x,y,"RAM.DIB_7") - self.create_conn(x+1,y+4,"CPE.RAM_O1", x,y,"RAM.DIB_8") - self.create_conn(x+1,y+4,"CPE.RAM_O2", x,y,"RAM.DIB_9") - self.create_conn(x+1,y+5,"CPE.RAM_O1", x,y,"RAM.DIB_10") - self.create_conn(x+1,y+5,"CPE.RAM_O2", x,y,"RAM.DIB_11") - self.create_conn(x+1,y+6,"CPE.RAM_O1", x,y,"RAM.DIB_12") - self.create_conn(x+1,y+6,"CPE.RAM_O2", x,y,"RAM.DIB_13") - self.create_conn(x+1,y+7,"CPE.RAM_O1", x,y,"RAM.DIB_14") - self.create_conn(x+1,y+7,"CPE.RAM_O2", x,y,"RAM.DIB_15") - self.create_conn(x+3,y+6,"CPE.RAM_O1", x,y,"RAM.DIB_16") - self.create_conn(x+3,y+6,"CPE.RAM_O2", x,y,"RAM.DIB_17") - self.create_conn(x+3,y+7,"CPE.RAM_O1", x,y,"RAM.DIB_18") - self.create_conn(x+3,y+7,"CPE.RAM_O2", x,y,"RAM.DIB_19") - self.create_conn(x+0,y+0,"CPE.RAM_O1", x,y,"RAM.WEB_0") - self.create_conn(x+0,y+0,"CPE.RAM_O2", x,y,"RAM.WEB_1") - self.create_conn(x+0,y+1,"CPE.RAM_O1", x,y,"RAM.WEB_2") - self.create_conn(x+0,y+1,"CPE.RAM_O2", x,y,"RAM.WEB_3") - self.create_conn(x+0,y+2,"CPE.RAM_O1", x,y,"RAM.WEB_4") - self.create_conn(x+0,y+2,"CPE.RAM_O2", x,y,"RAM.WEB_5") - self.create_conn(x+0,y+3,"CPE.RAM_O1", x,y,"RAM.WEB_6") - self.create_conn(x+0,y+3,"CPE.RAM_O2", x,y,"RAM.WEB_7") - self.create_conn(x+0,y+4,"CPE.RAM_O1", x,y,"RAM.WEB_8") - self.create_conn(x+0,y+4,"CPE.RAM_O2", x,y,"RAM.WEB_9") - self.create_conn(x+0,y+5,"CPE.RAM_O1", x,y,"RAM.WEB_10") - self.create_conn(x+0,y+5,"CPE.RAM_O2", x,y,"RAM.WEB_11") - self.create_conn(x+0,y+6,"CPE.RAM_O1", x,y,"RAM.WEB_12") - self.create_conn(x+0,y+6,"CPE.RAM_O2", x,y,"RAM.WEB_13") - self.create_conn(x+0,y+7,"CPE.RAM_O1", x,y,"RAM.WEB_14") - self.create_conn(x+0,y+7,"CPE.RAM_O2", x,y,"RAM.WEB_15") - self.create_conn(x+2,y+6,"CPE.RAM_O1", x,y,"RAM.WEB_16") - self.create_conn(x+2,y+6,"CPE.RAM_O2", x,y,"RAM.WEB_17") - self.create_conn(x+2,y+7,"CPE.RAM_O1", x,y,"RAM.WEB_18") - self.create_conn(x+2,y+7,"CPE.RAM_O2", x,y,"RAM.WEB_19") - self.create_conn(x+2,y+8,"CPE.RAM_O1", x,y,"RAM.CLKB_2") - self.create_conn(x+5,y+8,"CPE.RAM_O1", x,y,"RAM.CLKB_3") - self.create_conn(x+2,y+9,"CPE.RAM_O1", x,y,"RAM.ENB_2") - self.create_conn(x+5,y+9,"CPE.RAM_O1", x,y,"RAM.ENB_3") - self.create_conn(x+2,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEB_2") - self.create_conn(x+5,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEB_3") - self.create_conn(x+4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1_0") - self.create_conn(x+4,y+8,"CPE.RAM_O2", x,y,"RAM.ADDRB1_1") - self.create_conn(x+4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1_2") - self.create_conn(x+4,y+9,"CPE.RAM_O2", x,y,"RAM.ADDRB1_3") - self.create_conn(x+4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1_4") - self.create_conn(x+4,y+10,"CPE.RAM_O2", x,y,"RAM.ADDRB1_5") - self.create_conn(x+4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1_6") - self.create_conn(x+4,y+11,"CPE.RAM_O2", x,y,"RAM.ADDRB1_7") - self.create_conn(x+4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1_8") - self.create_conn(x+4,y+12,"CPE.RAM_O2", x,y,"RAM.ADDRB1_9") - self.create_conn(x+4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1_10") - self.create_conn(x+4,y+13,"CPE.RAM_O2", x,y,"RAM.ADDRB1_11") - self.create_conn(x+4,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1_12") - self.create_conn(x+4,y+14,"CPE.RAM_O2", x,y,"RAM.ADDRB1_13") - self.create_conn(x+4,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1_14") - self.create_conn(x+4,y+15,"CPE.RAM_O2", x,y,"RAM.ADDRB1_15") - self.create_conn(x+3,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_0") - self.create_conn(x+4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_1") - self.create_conn(x+3,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_2") - self.create_conn(x+4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_3") - self.create_conn(x+3,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_4") - self.create_conn(x+4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_5") - self.create_conn(x+3,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_6") - self.create_conn(x+4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_7") - self.create_conn(x+3,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_8") - self.create_conn(x+4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_9") - self.create_conn(x+3,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_10") - self.create_conn(x+4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_11") - self.create_conn(x+4,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_12") - self.create_conn(x+5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_13") - self.create_conn(x+4,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_14") - self.create_conn(x+5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1X_15") - self.create_conn(x+1,y+8,"CPE.RAM_O1", x,y,"RAM.DIB_20") - self.create_conn(x+1,y+8,"CPE.RAM_O2", x,y,"RAM.DIB_21") - self.create_conn(x+1,y+9,"CPE.RAM_O1", x,y,"RAM.DIB_22") - self.create_conn(x+1,y+9,"CPE.RAM_O2", x,y,"RAM.DIB_23") - self.create_conn(x+1,y+10,"CPE.RAM_O1", x,y,"RAM.DIB_24") - self.create_conn(x+1,y+10,"CPE.RAM_O2", x,y,"RAM.DIB_25") - self.create_conn(x+1,y+11,"CPE.RAM_O1", x,y,"RAM.DIB_26") - self.create_conn(x+1,y+11,"CPE.RAM_O2", x,y,"RAM.DIB_27") - self.create_conn(x+1,y+12,"CPE.RAM_O1", x,y,"RAM.DIB_28") - self.create_conn(x+1,y+12,"CPE.RAM_O2", x,y,"RAM.DIB_29") - self.create_conn(x+1,y+13,"CPE.RAM_O1", x,y,"RAM.DIB_30") - self.create_conn(x+1,y+13,"CPE.RAM_O2", x,y,"RAM.DIB_31") - self.create_conn(x+1,y+14,"CPE.RAM_O1", x,y,"RAM.DIB_32") - self.create_conn(x+1,y+14,"CPE.RAM_O2", x,y,"RAM.DIB_33") - self.create_conn(x+1,y+15,"CPE.RAM_O1", x,y,"RAM.DIB_34") - self.create_conn(x+1,y+15,"CPE.RAM_O2", x,y,"RAM.DIB_35") - self.create_conn(x+3,y+14,"CPE.RAM_O1", x,y,"RAM.DIB_36") - self.create_conn(x+3,y+14,"CPE.RAM_O2", x,y,"RAM.DIB_37") - self.create_conn(x+3,y+15,"CPE.RAM_O1", x,y,"RAM.DIB_38") - self.create_conn(x+3,y+15,"CPE.RAM_O2", x,y,"RAM.DIB_39") - self.create_conn(x+0,y+8,"CPE.RAM_O1", x,y,"RAM.WEB_20") - self.create_conn(x+0,y+8,"CPE.RAM_O2", x,y,"RAM.WEB_21") - self.create_conn(x+0,y+9,"CPE.RAM_O1", x,y,"RAM.WEB_22") - self.create_conn(x+0,y+9,"CPE.RAM_O2", x,y,"RAM.WEB_23") - self.create_conn(x+0,y+10,"CPE.RAM_O1", x,y,"RAM.WEB_24") - self.create_conn(x+0,y+10,"CPE.RAM_O2", x,y,"RAM.WEB_25") - self.create_conn(x+0,y+11,"CPE.RAM_O1", x,y,"RAM.WEB_26") - self.create_conn(x+0,y+11,"CPE.RAM_O2", x,y,"RAM.WEB_27") - self.create_conn(x+0,y+12,"CPE.RAM_O1", x,y,"RAM.WEB_28") - self.create_conn(x+0,y+12,"CPE.RAM_O2", x,y,"RAM.WEB_29") - self.create_conn(x+0,y+13,"CPE.RAM_O1", x,y,"RAM.WEB_30") - self.create_conn(x+0,y+13,"CPE.RAM_O2", x,y,"RAM.WEB_31") - self.create_conn(x+0,y+14,"CPE.RAM_O1", x,y,"RAM.WEB_32") - self.create_conn(x+0,y+14,"CPE.RAM_O2", x,y,"RAM.WEB_33") - self.create_conn(x+0,y+15,"CPE.RAM_O1", x,y,"RAM.WEB_34") - self.create_conn(x+0,y+15,"CPE.RAM_O2", x,y,"RAM.WEB_35") - self.create_conn(x+2,y+14,"CPE.RAM_O1", x,y,"RAM.WEB_36") - self.create_conn(x+2,y+14,"CPE.RAM_O2", x,y,"RAM.WEB_37") - self.create_conn(x+2,y+15,"CPE.RAM_O1", x,y,"RAM.WEB_38") - self.create_conn(x+2,y+15,"CPE.RAM_O2", x,y,"RAM.WEB_39") + self.create_conn(x-3,y+2,"CPE.RAM_O1", x,y,"RAM.C_ADDRA[0]") + self.create_conn(x-3,y+2,"CPE.RAM_O2", x,y,"RAM.C_ADDRA[1]") + self.create_conn(x-3,y+3,"CPE.RAM_O1", x,y,"RAM.C_ADDRA[2]") + self.create_conn(x-3,y+3,"CPE.RAM_O2", x,y,"RAM.C_ADDRA[3]") + self.create_conn(x-3,y+4,"CPE.RAM_O1", x,y,"RAM.C_ADDRA[4]") + self.create_conn(x-3,y+4,"CPE.RAM_O2", x,y,"RAM.C_ADDRA[5]") + self.create_conn(x-3,y+5,"CPE.RAM_O1", x,y,"RAM.C_ADDRA[6]") + self.create_conn(x-3,y+5,"CPE.RAM_O2", x,y,"RAM.C_ADDRA[7]") + self.create_conn(x+2,y+2,"CPE.RAM_O1", x,y,"RAM.C_ADDRB[0]") + self.create_conn(x+2,y+2,"CPE.RAM_O2", x,y,"RAM.C_ADDRB[1]") + self.create_conn(x+2,y+3,"CPE.RAM_O1", x,y,"RAM.C_ADDRB[2]") + self.create_conn(x+2,y+3,"CPE.RAM_O2", x,y,"RAM.C_ADDRB[3]") + self.create_conn(x+2,y+4,"CPE.RAM_O1", x,y,"RAM.C_ADDRB[4]") + self.create_conn(x+2,y+4,"CPE.RAM_O2", x,y,"RAM.C_ADDRB[5]") + self.create_conn(x+2,y+5,"CPE.RAM_O1", x,y,"RAM.C_ADDRB[6]") + self.create_conn(x+2,y+5,"CPE.RAM_O2", x,y,"RAM.C_ADDRB[7]") + self.create_conn(x-6,y+0,"CPE.RAM_O1", x,y,"RAM.CLKA[0]") + self.create_conn(x-3,y+0,"CPE.RAM_O1", x,y,"RAM.CLKA[1]") + self.create_conn(x-6,y+1,"CPE.RAM_O1", x,y,"RAM.ENA[0]") + self.create_conn(x-3,y+1,"CPE.RAM_O1", x,y,"RAM.ENA[1]") + self.create_conn(x-6,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEA[0]") + self.create_conn(x-3,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEA[1]") + self.create_conn(x-5,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0[0]") + self.create_conn(x-5,y+0,"CPE.RAM_O2", x,y,"RAM.ADDRA0[1]") + self.create_conn(x-5,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0[2]") + self.create_conn(x-5,y+1,"CPE.RAM_O2", x,y,"RAM.ADDRA0[3]") + self.create_conn(x-5,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0[4]") + self.create_conn(x-5,y+2,"CPE.RAM_O2", x,y,"RAM.ADDRA0[5]") + self.create_conn(x-5,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0[6]") + self.create_conn(x-5,y+3,"CPE.RAM_O2", x,y,"RAM.ADDRA0[7]") + self.create_conn(x-5,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0[8]") + self.create_conn(x-5,y+4,"CPE.RAM_O2", x,y,"RAM.ADDRA0[9]") + self.create_conn(x-5,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0[10]") + self.create_conn(x-5,y+5,"CPE.RAM_O2", x,y,"RAM.ADDRA0[11]") + self.create_conn(x-5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0[12]") + self.create_conn(x-5,y+6,"CPE.RAM_O2", x,y,"RAM.ADDRA0[13]") + self.create_conn(x-5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0[14]") + self.create_conn(x-5,y+7,"CPE.RAM_O2", x,y,"RAM.ADDRA0[15]") + self.create_conn(x-5,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[0]") + self.create_conn(x-4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[1]") + self.create_conn(x-5,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[2]") + self.create_conn(x-4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[3]") + self.create_conn(x-5,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[4]") + self.create_conn(x-4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[5]") + self.create_conn(x-5,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[6]") + self.create_conn(x-4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[7]") + self.create_conn(x-5,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[8]") + self.create_conn(x-4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[9]") + self.create_conn(x-5,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[10]") + self.create_conn(x-4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[11]") + self.create_conn(x-6,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[12]") + self.create_conn(x-5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[13]") + self.create_conn(x-6,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[14]") + self.create_conn(x-5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[15]") + self.create_conn(x-1,y+0,"CPE.RAM_O1", x,y,"RAM.DIA[0]") + self.create_conn(x-1,y+0,"CPE.RAM_O2", x,y,"RAM.DIA[1]") + self.create_conn(x-1,y+1,"CPE.RAM_O1", x,y,"RAM.DIA[2]") + self.create_conn(x-1,y+1,"CPE.RAM_O2", x,y,"RAM.DIA[3]") + self.create_conn(x-1,y+2,"CPE.RAM_O1", x,y,"RAM.DIA[4]") + self.create_conn(x-1,y+2,"CPE.RAM_O2", x,y,"RAM.DIA[5]") + self.create_conn(x-1,y+3,"CPE.RAM_O1", x,y,"RAM.DIA[6]") + self.create_conn(x-1,y+3,"CPE.RAM_O2", x,y,"RAM.DIA[7]") + self.create_conn(x-1,y+4,"CPE.RAM_O1", x,y,"RAM.DIA[8]") + self.create_conn(x-1,y+4,"CPE.RAM_O2", x,y,"RAM.DIA[9]") + self.create_conn(x-1,y+5,"CPE.RAM_O1", x,y,"RAM.DIA[10]") + self.create_conn(x-1,y+5,"CPE.RAM_O2", x,y,"RAM.DIA[11]") + self.create_conn(x-1,y+6,"CPE.RAM_O1", x,y,"RAM.DIA[12]") + self.create_conn(x-1,y+6,"CPE.RAM_O2", x,y,"RAM.DIA[13]") + self.create_conn(x-1,y+7,"CPE.RAM_O1", x,y,"RAM.DIA[14]") + self.create_conn(x-1,y+7,"CPE.RAM_O2", x,y,"RAM.DIA[15]") + self.create_conn(x-3,y+6,"CPE.RAM_O1", x,y,"RAM.DIA[16]") + self.create_conn(x-3,y+6,"CPE.RAM_O2", x,y,"RAM.DIA[17]") + self.create_conn(x-3,y+7,"CPE.RAM_O1", x,y,"RAM.DIA[18]") + self.create_conn(x-3,y+7,"CPE.RAM_O2", x,y,"RAM.DIA[19]") + self.create_conn(x-2,y+0,"CPE.RAM_O1", x,y,"RAM.WEA[0]") + self.create_conn(x-2,y+0,"CPE.RAM_O2", x,y,"RAM.WEA[1]") + self.create_conn(x-2,y+1,"CPE.RAM_O1", x,y,"RAM.WEA[2]") + self.create_conn(x-2,y+1,"CPE.RAM_O2", x,y,"RAM.WEA[3]") + self.create_conn(x-2,y+2,"CPE.RAM_O1", x,y,"RAM.WEA[4]") + self.create_conn(x-2,y+2,"CPE.RAM_O2", x,y,"RAM.WEA[5]") + self.create_conn(x-2,y+3,"CPE.RAM_O1", x,y,"RAM.WEA[6]") + self.create_conn(x-2,y+3,"CPE.RAM_O2", x,y,"RAM.WEA[7]") + self.create_conn(x-2,y+4,"CPE.RAM_O1", x,y,"RAM.WEA[8]") + self.create_conn(x-2,y+4,"CPE.RAM_O2", x,y,"RAM.WEA[9]") + self.create_conn(x-2,y+5,"CPE.RAM_O1", x,y,"RAM.WEA[10]") + self.create_conn(x-2,y+5,"CPE.RAM_O2", x,y,"RAM.WEA[11]") + self.create_conn(x-2,y+6,"CPE.RAM_O1", x,y,"RAM.WEA[12]") + self.create_conn(x-2,y+6,"CPE.RAM_O2", x,y,"RAM.WEA[13]") + self.create_conn(x-2,y+7,"CPE.RAM_O1", x,y,"RAM.WEA[14]") + self.create_conn(x-2,y+7,"CPE.RAM_O2", x,y,"RAM.WEA[15]") + self.create_conn(x-4,y+6,"CPE.RAM_O1", x,y,"RAM.WEA[16]") + self.create_conn(x-4,y+6,"CPE.RAM_O2", x,y,"RAM.WEA[17]") + self.create_conn(x-4,y+7,"CPE.RAM_O1", x,y,"RAM.WEA[18]") + self.create_conn(x-4,y+7,"CPE.RAM_O2", x,y,"RAM.WEA[19]") + self.create_conn(x-6,y+8,"CPE.RAM_O1", x,y,"RAM.CLKA[2]") + self.create_conn(x-3,y+8,"CPE.RAM_O1", x,y,"RAM.CLKA[3]") + self.create_conn(x-6,y+9,"CPE.RAM_O1", x,y,"RAM.ENA[2]") + self.create_conn(x-3,y+9,"CPE.RAM_O1", x,y,"RAM.ENA[3]") + self.create_conn(x-6,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEA[2]") + self.create_conn(x-3,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEA[3]") + self.create_conn(x-5,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1[0]") + self.create_conn(x-5,y+8,"CPE.RAM_O2", x,y,"RAM.ADDRA1[1]") + self.create_conn(x-5,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1[2]") + self.create_conn(x-5,y+9,"CPE.RAM_O2", x,y,"RAM.ADDRA1[3]") + self.create_conn(x-5,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1[4]") + self.create_conn(x-5,y+10,"CPE.RAM_O2", x,y,"RAM.ADDRA1[5]") + self.create_conn(x-5,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1[6]") + self.create_conn(x-5,y+11,"CPE.RAM_O2", x,y,"RAM.ADDRA1[7]") + self.create_conn(x-5,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1[8]") + self.create_conn(x-5,y+12,"CPE.RAM_O2", x,y,"RAM.ADDRA1[9]") + self.create_conn(x-5,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1[10]") + self.create_conn(x-5,y+13,"CPE.RAM_O2", x,y,"RAM.ADDRA1[11]") + self.create_conn(x-5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1[12]") + self.create_conn(x-5,y+14,"CPE.RAM_O2", x,y,"RAM.ADDRA1[13]") + self.create_conn(x-5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1[14]") + self.create_conn(x-5,y+15,"CPE.RAM_O2", x,y,"RAM.ADDRA1[15]") + self.create_conn(x-5,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[0]") + self.create_conn(x-4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[1]") + self.create_conn(x-5,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[2]") + self.create_conn(x-4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[3]") + self.create_conn(x-5,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[4]") + self.create_conn(x-4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[5]") + self.create_conn(x-5,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[6]") + self.create_conn(x-4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[7]") + self.create_conn(x-5,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[8]") + self.create_conn(x-4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[9]") + self.create_conn(x-5,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[10]") + self.create_conn(x-4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[11]") + self.create_conn(x-6,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[12]") + self.create_conn(x-5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[13]") + self.create_conn(x-6,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[14]") + self.create_conn(x-5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[15]") + self.create_conn(x-1,y+8,"CPE.RAM_O1", x,y,"RAM.DIA[20]") + self.create_conn(x-1,y+8,"CPE.RAM_O2", x,y,"RAM.DIA[21]") + self.create_conn(x-1,y+9,"CPE.RAM_O1", x,y,"RAM.DIA[22]") + self.create_conn(x-1,y+9,"CPE.RAM_O2", x,y,"RAM.DIA[23]") + self.create_conn(x-1,y+10,"CPE.RAM_O1", x,y,"RAM.DIA[24]") + self.create_conn(x-1,y+10,"CPE.RAM_O2", x,y,"RAM.DIA[25]") + self.create_conn(x-1,y+11,"CPE.RAM_O1", x,y,"RAM.DIA[26]") + self.create_conn(x-1,y+11,"CPE.RAM_O2", x,y,"RAM.DIA[27]") + self.create_conn(x-1,y+12,"CPE.RAM_O1", x,y,"RAM.DIA[28]") + self.create_conn(x-1,y+12,"CPE.RAM_O2", x,y,"RAM.DIA[29]") + self.create_conn(x-1,y+13,"CPE.RAM_O1", x,y,"RAM.DIA[30]") + self.create_conn(x-1,y+13,"CPE.RAM_O2", x,y,"RAM.DIA[31]") + self.create_conn(x-1,y+14,"CPE.RAM_O1", x,y,"RAM.DIA[32]") + self.create_conn(x-1,y+14,"CPE.RAM_O2", x,y,"RAM.DIA[33]") + self.create_conn(x-1,y+15,"CPE.RAM_O1", x,y,"RAM.DIA[34]") + self.create_conn(x-1,y+15,"CPE.RAM_O2", x,y,"RAM.DIA[35]") + self.create_conn(x-3,y+14,"CPE.RAM_O1", x,y,"RAM.DIA[36]") + self.create_conn(x-3,y+14,"CPE.RAM_O2", x,y,"RAM.DIA[37]") + self.create_conn(x-3,y+15,"CPE.RAM_O1", x,y,"RAM.DIA[38]") + self.create_conn(x-3,y+15,"CPE.RAM_O2", x,y,"RAM.DIA[39]") + self.create_conn(x-2,y+8,"CPE.RAM_O1", x,y,"RAM.WEA[20]") + self.create_conn(x-2,y+8,"CPE.RAM_O2", x,y,"RAM.WEA[21]") + self.create_conn(x-2,y+9,"CPE.RAM_O1", x,y,"RAM.WEA[22]") + self.create_conn(x-2,y+9,"CPE.RAM_O2", x,y,"RAM.WEA[23]") + self.create_conn(x-2,y+10,"CPE.RAM_O1", x,y,"RAM.WEA[24]") + self.create_conn(x-2,y+10,"CPE.RAM_O2", x,y,"RAM.WEA[25]") + self.create_conn(x-2,y+11,"CPE.RAM_O1", x,y,"RAM.WEA[26]") + self.create_conn(x-2,y+11,"CPE.RAM_O2", x,y,"RAM.WEA[27]") + self.create_conn(x-2,y+12,"CPE.RAM_O1", x,y,"RAM.WEA[28]") + self.create_conn(x-2,y+12,"CPE.RAM_O2", x,y,"RAM.WEA[29]") + self.create_conn(x-2,y+13,"CPE.RAM_O1", x,y,"RAM.WEA[30]") + self.create_conn(x-2,y+13,"CPE.RAM_O2", x,y,"RAM.WEA[31]") + self.create_conn(x-2,y+14,"CPE.RAM_O1", x,y,"RAM.WEA[32]") + self.create_conn(x-2,y+14,"CPE.RAM_O2", x,y,"RAM.WEA[33]") + self.create_conn(x-2,y+15,"CPE.RAM_O1", x,y,"RAM.WEA[34]") + self.create_conn(x-2,y+15,"CPE.RAM_O2", x,y,"RAM.WEA[35]") + self.create_conn(x-4,y+14,"CPE.RAM_O1", x,y,"RAM.WEA[36]") + self.create_conn(x-4,y+14,"CPE.RAM_O2", x,y,"RAM.WEA[37]") + self.create_conn(x-4,y+15,"CPE.RAM_O1", x,y,"RAM.WEA[38]") + self.create_conn(x-4,y+15,"CPE.RAM_O2", x,y,"RAM.WEA[39]") + self.create_conn(x+2,y+0,"CPE.RAM_O1", x,y,"RAM.CLKB[0]") + self.create_conn(x+5,y+0,"CPE.RAM_O1", x,y,"RAM.CLKB[1]") + self.create_conn(x+2,y+1,"CPE.RAM_O1", x,y,"RAM.ENB[0]") + self.create_conn(x+5,y+1,"CPE.RAM_O1", x,y,"RAM.ENB[1]") + self.create_conn(x+2,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEB[0]") + self.create_conn(x+5,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEB[1]") + self.create_conn(x+4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0[0]") + self.create_conn(x+4,y+0,"CPE.RAM_O2", x,y,"RAM.ADDRB0[1]") + self.create_conn(x+4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0[2]") + self.create_conn(x+4,y+1,"CPE.RAM_O2", x,y,"RAM.ADDRB0[3]") + self.create_conn(x+4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0[4]") + self.create_conn(x+4,y+2,"CPE.RAM_O2", x,y,"RAM.ADDRB0[5]") + self.create_conn(x+4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0[6]") + self.create_conn(x+4,y+3,"CPE.RAM_O2", x,y,"RAM.ADDRB0[7]") + self.create_conn(x+4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0[8]") + self.create_conn(x+4,y+4,"CPE.RAM_O2", x,y,"RAM.ADDRB0[9]") + self.create_conn(x+4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0[10]") + self.create_conn(x+4,y+5,"CPE.RAM_O2", x,y,"RAM.ADDRB0[11]") + self.create_conn(x+4,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0[12]") + self.create_conn(x+4,y+6,"CPE.RAM_O2", x,y,"RAM.ADDRB0[13]") + self.create_conn(x+4,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0[14]") + self.create_conn(x+4,y+7,"CPE.RAM_O2", x,y,"RAM.ADDRB0[15]") + self.create_conn(x+3,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[0]") + self.create_conn(x+4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[1]") + self.create_conn(x+3,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[2]") + self.create_conn(x+4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[3]") + self.create_conn(x+3,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[4]") + self.create_conn(x+4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[5]") + self.create_conn(x+3,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[6]") + self.create_conn(x+4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[7]") + self.create_conn(x+3,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[8]") + self.create_conn(x+4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[9]") + self.create_conn(x+3,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[10]") + self.create_conn(x+4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[11]") + self.create_conn(x+4,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[12]") + self.create_conn(x+5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[13]") + self.create_conn(x+4,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[14]") + self.create_conn(x+5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[15]") + self.create_conn(x+1,y+0,"CPE.RAM_O1", x,y,"RAM.DIB[0]") + self.create_conn(x+1,y+0,"CPE.RAM_O2", x,y,"RAM.DIB[1]") + self.create_conn(x+1,y+1,"CPE.RAM_O1", x,y,"RAM.DIB[2]") + self.create_conn(x+1,y+1,"CPE.RAM_O2", x,y,"RAM.DIB[3]") + self.create_conn(x+1,y+2,"CPE.RAM_O1", x,y,"RAM.DIB[4]") + self.create_conn(x+1,y+2,"CPE.RAM_O2", x,y,"RAM.DIB[5]") + self.create_conn(x+1,y+3,"CPE.RAM_O1", x,y,"RAM.DIB[6]") + self.create_conn(x+1,y+3,"CPE.RAM_O2", x,y,"RAM.DIB[7]") + self.create_conn(x+1,y+4,"CPE.RAM_O1", x,y,"RAM.DIB[8]") + self.create_conn(x+1,y+4,"CPE.RAM_O2", x,y,"RAM.DIB[9]") + self.create_conn(x+1,y+5,"CPE.RAM_O1", x,y,"RAM.DIB[10]") + self.create_conn(x+1,y+5,"CPE.RAM_O2", x,y,"RAM.DIB[11]") + self.create_conn(x+1,y+6,"CPE.RAM_O1", x,y,"RAM.DIB[12]") + self.create_conn(x+1,y+6,"CPE.RAM_O2", x,y,"RAM.DIB[13]") + self.create_conn(x+1,y+7,"CPE.RAM_O1", x,y,"RAM.DIB[14]") + self.create_conn(x+1,y+7,"CPE.RAM_O2", x,y,"RAM.DIB[15]") + self.create_conn(x+3,y+6,"CPE.RAM_O1", x,y,"RAM.DIB[16]") + self.create_conn(x+3,y+6,"CPE.RAM_O2", x,y,"RAM.DIB[17]") + self.create_conn(x+3,y+7,"CPE.RAM_O1", x,y,"RAM.DIB[18]") + self.create_conn(x+3,y+7,"CPE.RAM_O2", x,y,"RAM.DIB[19]") + self.create_conn(x+0,y+0,"CPE.RAM_O1", x,y,"RAM.WEB[0]") + self.create_conn(x+0,y+0,"CPE.RAM_O2", x,y,"RAM.WEB[1]") + self.create_conn(x+0,y+1,"CPE.RAM_O1", x,y,"RAM.WEB[2]") + self.create_conn(x+0,y+1,"CPE.RAM_O2", x,y,"RAM.WEB[3]") + self.create_conn(x+0,y+2,"CPE.RAM_O1", x,y,"RAM.WEB[4]") + self.create_conn(x+0,y+2,"CPE.RAM_O2", x,y,"RAM.WEB[5]") + self.create_conn(x+0,y+3,"CPE.RAM_O1", x,y,"RAM.WEB[6]") + self.create_conn(x+0,y+3,"CPE.RAM_O2", x,y,"RAM.WEB[7]") + self.create_conn(x+0,y+4,"CPE.RAM_O1", x,y,"RAM.WEB[8]") + self.create_conn(x+0,y+4,"CPE.RAM_O2", x,y,"RAM.WEB[9]") + self.create_conn(x+0,y+5,"CPE.RAM_O1", x,y,"RAM.WEB[10]") + self.create_conn(x+0,y+5,"CPE.RAM_O2", x,y,"RAM.WEB[11]") + self.create_conn(x+0,y+6,"CPE.RAM_O1", x,y,"RAM.WEB[12]") + self.create_conn(x+0,y+6,"CPE.RAM_O2", x,y,"RAM.WEB[13]") + self.create_conn(x+0,y+7,"CPE.RAM_O1", x,y,"RAM.WEB[14]") + self.create_conn(x+0,y+7,"CPE.RAM_O2", x,y,"RAM.WEB[15]") + self.create_conn(x+2,y+6,"CPE.RAM_O1", x,y,"RAM.WEB[16]") + self.create_conn(x+2,y+6,"CPE.RAM_O2", x,y,"RAM.WEB[17]") + self.create_conn(x+2,y+7,"CPE.RAM_O1", x,y,"RAM.WEB[18]") + self.create_conn(x+2,y+7,"CPE.RAM_O2", x,y,"RAM.WEB[19]") + self.create_conn(x+2,y+8,"CPE.RAM_O1", x,y,"RAM.CLKB[2]") + self.create_conn(x+5,y+8,"CPE.RAM_O1", x,y,"RAM.CLKB[3]") + self.create_conn(x+2,y+9,"CPE.RAM_O1", x,y,"RAM.ENB[2]") + self.create_conn(x+5,y+9,"CPE.RAM_O1", x,y,"RAM.ENB[3]") + self.create_conn(x+2,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEB[2]") + self.create_conn(x+5,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEB[3]") + self.create_conn(x+4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1[0]") + self.create_conn(x+4,y+8,"CPE.RAM_O2", x,y,"RAM.ADDRB1[1]") + self.create_conn(x+4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1[2]") + self.create_conn(x+4,y+9,"CPE.RAM_O2", x,y,"RAM.ADDRB1[3]") + self.create_conn(x+4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1[4]") + self.create_conn(x+4,y+10,"CPE.RAM_O2", x,y,"RAM.ADDRB1[5]") + self.create_conn(x+4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1[6]") + self.create_conn(x+4,y+11,"CPE.RAM_O2", x,y,"RAM.ADDRB1[7]") + self.create_conn(x+4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1[8]") + self.create_conn(x+4,y+12,"CPE.RAM_O2", x,y,"RAM.ADDRB1[9]") + self.create_conn(x+4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1[10]") + self.create_conn(x+4,y+13,"CPE.RAM_O2", x,y,"RAM.ADDRB1[11]") + self.create_conn(x+4,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1[12]") + self.create_conn(x+4,y+14,"CPE.RAM_O2", x,y,"RAM.ADDRB1[13]") + self.create_conn(x+4,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1[14]") + self.create_conn(x+4,y+15,"CPE.RAM_O2", x,y,"RAM.ADDRB1[15]") + self.create_conn(x+3,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[0]") + self.create_conn(x+4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[1]") + self.create_conn(x+3,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[2]") + self.create_conn(x+4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[3]") + self.create_conn(x+3,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[4]") + self.create_conn(x+4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[5]") + self.create_conn(x+3,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[6]") + self.create_conn(x+4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[7]") + self.create_conn(x+3,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[8]") + self.create_conn(x+4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[9]") + self.create_conn(x+3,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[10]") + self.create_conn(x+4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[11]") + self.create_conn(x+4,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[12]") + self.create_conn(x+5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[13]") + self.create_conn(x+4,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[14]") + self.create_conn(x+5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[15]") + self.create_conn(x+1,y+8,"CPE.RAM_O1", x,y,"RAM.DIB[20]") + self.create_conn(x+1,y+8,"CPE.RAM_O2", x,y,"RAM.DIB[21]") + self.create_conn(x+1,y+9,"CPE.RAM_O1", x,y,"RAM.DIB[22]") + self.create_conn(x+1,y+9,"CPE.RAM_O2", x,y,"RAM.DIB[23]") + self.create_conn(x+1,y+10,"CPE.RAM_O1", x,y,"RAM.DIB[24]") + self.create_conn(x+1,y+10,"CPE.RAM_O2", x,y,"RAM.DIB[25]") + self.create_conn(x+1,y+11,"CPE.RAM_O1", x,y,"RAM.DIB[26]") + self.create_conn(x+1,y+11,"CPE.RAM_O2", x,y,"RAM.DIB[27]") + self.create_conn(x+1,y+12,"CPE.RAM_O1", x,y,"RAM.DIB[28]") + self.create_conn(x+1,y+12,"CPE.RAM_O2", x,y,"RAM.DIB[29]") + self.create_conn(x+1,y+13,"CPE.RAM_O1", x,y,"RAM.DIB[30]") + self.create_conn(x+1,y+13,"CPE.RAM_O2", x,y,"RAM.DIB[31]") + self.create_conn(x+1,y+14,"CPE.RAM_O1", x,y,"RAM.DIB[32]") + self.create_conn(x+1,y+14,"CPE.RAM_O2", x,y,"RAM.DIB[33]") + self.create_conn(x+1,y+15,"CPE.RAM_O1", x,y,"RAM.DIB[34]") + self.create_conn(x+1,y+15,"CPE.RAM_O2", x,y,"RAM.DIB[35]") + self.create_conn(x+3,y+14,"CPE.RAM_O1", x,y,"RAM.DIB[36]") + self.create_conn(x+3,y+14,"CPE.RAM_O2", x,y,"RAM.DIB[37]") + self.create_conn(x+3,y+15,"CPE.RAM_O1", x,y,"RAM.DIB[38]") + self.create_conn(x+3,y+15,"CPE.RAM_O2", x,y,"RAM.DIB[39]") + self.create_conn(x+0,y+8,"CPE.RAM_O1", x,y,"RAM.WEB[20]") + self.create_conn(x+0,y+8,"CPE.RAM_O2", x,y,"RAM.WEB[21]") + self.create_conn(x+0,y+9,"CPE.RAM_O1", x,y,"RAM.WEB[22]") + self.create_conn(x+0,y+9,"CPE.RAM_O2", x,y,"RAM.WEB[23]") + self.create_conn(x+0,y+10,"CPE.RAM_O1", x,y,"RAM.WEB[24]") + self.create_conn(x+0,y+10,"CPE.RAM_O2", x,y,"RAM.WEB[25]") + self.create_conn(x+0,y+11,"CPE.RAM_O1", x,y,"RAM.WEB[26]") + self.create_conn(x+0,y+11,"CPE.RAM_O2", x,y,"RAM.WEB[27]") + self.create_conn(x+0,y+12,"CPE.RAM_O1", x,y,"RAM.WEB[28]") + self.create_conn(x+0,y+12,"CPE.RAM_O2", x,y,"RAM.WEB[29]") + self.create_conn(x+0,y+13,"CPE.RAM_O1", x,y,"RAM.WEB[30]") + self.create_conn(x+0,y+13,"CPE.RAM_O2", x,y,"RAM.WEB[31]") + self.create_conn(x+0,y+14,"CPE.RAM_O1", x,y,"RAM.WEB[32]") + self.create_conn(x+0,y+14,"CPE.RAM_O2", x,y,"RAM.WEB[33]") + self.create_conn(x+0,y+15,"CPE.RAM_O1", x,y,"RAM.WEB[34]") + self.create_conn(x+0,y+15,"CPE.RAM_O2", x,y,"RAM.WEB[35]") + self.create_conn(x+2,y+14,"CPE.RAM_O1", x,y,"RAM.WEB[36]") + self.create_conn(x+2,y+14,"CPE.RAM_O2", x,y,"RAM.WEB[37]") + self.create_conn(x+2,y+15,"CPE.RAM_O1", x,y,"RAM.WEB[38]") + self.create_conn(x+2,y+15,"CPE.RAM_O2", x,y,"RAM.WEB[39]") self.create_conn(x-6,y+2,"CPE.RAM_O2", x,y,"RAM.F_RSTN") - self.create_conn(x,y,"RAM.DOA_0", x-1,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_0", x-2,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_1", x-1,y+0,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_1", x-1,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_2", x-1,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_2", x-2,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_3", x-1,y+1,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_3", x-1,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_4", x-1,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_4", x-2,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_5", x-1,y+2,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_5", x-1,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_6", x-1,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_6", x-2,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_7", x-1,y+3,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_7", x-1,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_8", x-1,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_8", x-2,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_9", x-1,y+4,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_9", x-1,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_10", x-1,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_10", x-2,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_11", x-1,y+5,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_11", x-1,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_12", x-1,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_12", x-2,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_13", x-1,y+6,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_13", x-1,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_14", x-1,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_14", x-2,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_15", x-1,y+7,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_15", x-1,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_16", x-3,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_16", x-4,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_17", x-3,y+6,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_17", x-3,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_18", x-3,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_18", x-4,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_19", x-3,y+7,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_19", x-3,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_20", x-1,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_20", x-2,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_21", x-1,y+8,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_21", x-1,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_22", x-1,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_22", x-2,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_23", x-1,y+9,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_23", x-1,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_24", x-1,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_24", x-2,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_25", x-1,y+10,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_25", x-1,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_26", x-1,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_26", x-2,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_27", x-1,y+11,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_27", x-1,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_28", x-1,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_28", x-2,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_29", x-1,y+12,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_29", x-1,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_30", x-1,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_30", x-2,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_31", x-1,y+13,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_31", x-1,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_32", x-1,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_32", x-2,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_33", x-1,y+14,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_33", x-1,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_34", x-1,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_34", x-2,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_35", x-1,y+15,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_35", x-1,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_36", x-3,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_36", x-4,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_37", x-3,y+14,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_37", x-3,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_38", x-3,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX_38", x-4,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA_39", x-3,y+15,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX_39", x-3,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKA_1", x-3,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.CLOCKA_2", x-3,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.CLOCKA_3", x-3,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.CLOCKA_4", x-3,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOB_0", x+1,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_0", x+0,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_1", x+1,y+0,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_1", x+1,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_2", x+1,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_2", x+0,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_3", x+1,y+1,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_3", x+1,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_4", x+1,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_4", x+0,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_5", x+1,y+2,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_5", x+1,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_6", x+1,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_6", x+0,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_7", x+1,y+3,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_7", x+1,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_8", x+1,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_8", x+0,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_9", x+1,y+4,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_9", x+1,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_10", x+1,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_10", x+0,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_11", x+1,y+5,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_11", x+1,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_12", x+1,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_12", x+0,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_13", x+1,y+6,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_13", x+1,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_14", x+1,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_14", x+0,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_15", x+1,y+7,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_15", x+1,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_16", x+3,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_16", x+2,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_17", x+3,y+6,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_17", x+3,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_18", x+3,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_18", x+2,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_19", x+3,y+7,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_19", x+3,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_20", x+1,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_20", x+0,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_21", x+1,y+8,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_21", x+1,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_22", x+1,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_22", x+0,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_23", x+1,y+9,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_23", x+1,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_24", x+1,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_24", x+0,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_25", x+1,y+10,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_25", x+1,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_26", x+1,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_26", x+0,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_27", x+1,y+11,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_27", x+1,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_28", x+1,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_28", x+0,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_29", x+1,y+12,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_29", x+1,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_30", x+1,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_30", x+0,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_31", x+1,y+13,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_31", x+1,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_32", x+1,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_32", x+0,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_33", x+1,y+14,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_33", x+1,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_34", x+1,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_34", x+0,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_35", x+1,y+15,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_35", x+1,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_36", x+3,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_36", x+2,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_37", x+3,y+14,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_37", x+3,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_38", x+3,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX_38", x+2,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB_39", x+3,y+15,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX_39", x+3,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKB_1", x+2,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKB_2", x+2,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKB_3", x+2,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKB_4", x+2,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC1B_ERRA_0", x-4,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRA_1", x-4,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRA_2", x+5,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRA_3", x+5,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRB_0", x-4,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRB_1", x-4,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRB_2", x+5,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRB_3", x+5,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC2B_ERRA_0", x-4,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRA_1", x-4,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRA_2", x+5,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRA_3", x+5,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRB_0", x-4,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRB_1", x-4,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRB_2", x+5,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRB_3", x+5,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_FULL_0", x-4,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_FULL_1", x-4,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_EMPTY_0", x-4,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.F_EMPTY_1", x-4,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_AL_FULL_0", x-4,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_AL_FULL_1", x-4,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.F_AL_EMPTY_0", x-4,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.F_AL_EMPTY_1", x-4,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ERR_0", x-4,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ERR_1", x-4,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ERR_0", x-4,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ERR_1", x-4,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR_0", x-6,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX_0", x-5,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR_1", x-6,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX_1", x-5,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR_2", x-6,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX_2", x-5,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR_3", x-6,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX_3", x-5,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR_4", x-6,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX_4", x-5,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR_5", x-6,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX_5", x-5,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR_6", x-6,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX_6", x-5,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR_7", x-6,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX_7", x-5,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR_8", x-6,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX_8", x-5,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR_9", x-6,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX_9", x-5,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR_10", x-6,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX_10", x-5,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR_11", x-6,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX_11", x-5,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR_12", x-6,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX_12", x-5,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR_13", x-6,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX_13", x-5,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR_14", x-6,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX_14", x-5,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR_15", x-6,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX_15", x-5,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR_0", x-6,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX_0", x-5,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR_1", x-6,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX_1", x-5,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR_2", x-6,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX_2", x-5,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR_3", x-6,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX_3", x-5,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR_4", x-6,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX_4", x-5,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR_5", x-6,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX_5", x-5,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR_6", x-6,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX_6", x-5,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR_7", x-6,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX_7", x-5,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR_8", x-6,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX_8", x-5,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR_9", x-6,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX_9", x-5,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR_10", x-6,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX_10", x-5,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR_11", x-6,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX_11", x-5,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR_12", x-6,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX_12", x-5,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR_13", x-6,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX_13", x-5,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR_14", x-6,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX_14", x-5,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR_15", x-6,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX_15", x-5,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[0]", x-1,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[0]", x-2,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[1]", x-1,y+0,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[1]", x-1,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[2]", x-1,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[2]", x-2,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[3]", x-1,y+1,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[3]", x-1,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[4]", x-1,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[4]", x-2,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[5]", x-1,y+2,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[5]", x-1,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[6]", x-1,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[6]", x-2,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[7]", x-1,y+3,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[7]", x-1,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[8]", x-1,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[8]", x-2,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[9]", x-1,y+4,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[9]", x-1,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[10]", x-1,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[10]", x-2,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[11]", x-1,y+5,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[11]", x-1,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[12]", x-1,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[12]", x-2,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[13]", x-1,y+6,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[13]", x-1,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[14]", x-1,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[14]", x-2,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[15]", x-1,y+7,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[15]", x-1,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[16]", x-3,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[16]", x-4,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[17]", x-3,y+6,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[17]", x-3,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[18]", x-3,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[18]", x-4,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[19]", x-3,y+7,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[19]", x-3,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[20]", x-1,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[20]", x-2,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[21]", x-1,y+8,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[21]", x-1,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[22]", x-1,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[22]", x-2,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[23]", x-1,y+9,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[23]", x-1,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[24]", x-1,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[24]", x-2,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[25]", x-1,y+10,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[25]", x-1,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[26]", x-1,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[26]", x-2,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[27]", x-1,y+11,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[27]", x-1,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[28]", x-1,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[28]", x-2,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[29]", x-1,y+12,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[29]", x-1,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[30]", x-1,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[30]", x-2,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[31]", x-1,y+13,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[31]", x-1,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[32]", x-1,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[32]", x-2,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[33]", x-1,y+14,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[33]", x-1,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[34]", x-1,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[34]", x-2,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[35]", x-1,y+15,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[35]", x-1,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[36]", x-3,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[36]", x-4,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[37]", x-3,y+14,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[37]", x-3,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[38]", x-3,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOAX[38]", x-4,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOA[39]", x-3,y+15,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOAX[39]", x-3,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKA[1]", x-3,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.CLOCKA[2]", x-3,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.CLOCKA[3]", x-3,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.CLOCKA[4]", x-3,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOB[0]", x+1,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[0]", x+0,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[1]", x+1,y+0,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[1]", x+1,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[2]", x+1,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[2]", x+0,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[3]", x+1,y+1,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[3]", x+1,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[4]", x+1,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[4]", x+0,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[5]", x+1,y+2,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[5]", x+1,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[6]", x+1,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[6]", x+0,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[7]", x+1,y+3,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[7]", x+1,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[8]", x+1,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[8]", x+0,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[9]", x+1,y+4,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[9]", x+1,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[10]", x+1,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[10]", x+0,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[11]", x+1,y+5,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[11]", x+1,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[12]", x+1,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[12]", x+0,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[13]", x+1,y+6,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[13]", x+1,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[14]", x+1,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[14]", x+0,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[15]", x+1,y+7,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[15]", x+1,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[16]", x+3,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[16]", x+2,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[17]", x+3,y+6,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[17]", x+3,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[18]", x+3,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[18]", x+2,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[19]", x+3,y+7,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[19]", x+3,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[20]", x+1,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[20]", x+0,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[21]", x+1,y+8,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[21]", x+1,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[22]", x+1,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[22]", x+0,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[23]", x+1,y+9,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[23]", x+1,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[24]", x+1,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[24]", x+0,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[25]", x+1,y+10,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[25]", x+1,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[26]", x+1,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[26]", x+0,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[27]", x+1,y+11,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[27]", x+1,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[28]", x+1,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[28]", x+0,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[29]", x+1,y+12,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[29]", x+1,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[30]", x+1,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[30]", x+0,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[31]", x+1,y+13,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[31]", x+1,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[32]", x+1,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[32]", x+0,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[33]", x+1,y+14,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[33]", x+1,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[34]", x+1,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[34]", x+0,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[35]", x+1,y+15,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[35]", x+1,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[36]", x+3,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[36]", x+2,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[37]", x+3,y+14,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[37]", x+3,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[38]", x+3,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.DOBX[38]", x+2,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.DOB[39]", x+3,y+15,"CPE.RAM_I2") +# self.create_conn(x,y,"RAM.DOBX[39]", x+3,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKB[1]", x+2,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKB[2]", x+2,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKB[3]", x+2,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.CLOCKB[4]", x+2,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC1B_ERRA[0]", x-4,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRA[1]", x-4,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRA[2]", x+5,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRA[3]", x+5,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRB[0]", x-4,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRB[1]", x-4,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRB[2]", x+5,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC1B_ERRB[3]", x+5,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.ECC2B_ERRA[0]", x-4,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRA[1]", x-4,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRA[2]", x+5,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRA[3]", x+5,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRB[0]", x-4,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRB[1]", x-4,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRB[2]", x+5,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.ECC2B_ERRB[3]", x+5,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_FULL[0]", x-4,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_FULL[1]", x-4,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_EMPTY[0]", x-4,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.F_EMPTY[1]", x-4,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_AL_FULL[0]", x-4,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.F_AL_FULL[1]", x-4,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.F_AL_EMPTY[0]", x-4,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.F_AL_EMPTY[1]", x-4,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ERR[0]", x-4,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ERR[1]", x-4,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ERR[0]", x-4,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ERR[1]", x-4,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR[0]", x-6,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX[0]", x-5,y+8,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR[1]", x-6,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX[1]", x-5,y+8,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR[2]", x-6,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX[2]", x-5,y+9,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR[3]", x-6,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX[3]", x-5,y+9,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR[4]", x-6,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX[4]", x-5,y+10,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR[5]", x-6,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX[5]", x-5,y+10,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR[6]", x-6,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX[6]", x-5,y+11,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR[7]", x-6,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX[7]", x-5,y+11,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR[8]", x-6,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX[8]", x-5,y+12,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR[9]", x-6,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX[9]", x-5,y+12,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR[10]", x-6,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX[10]", x-5,y+13,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR[11]", x-6,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX[11]", x-5,y+13,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR[12]", x-6,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX[12]", x-5,y+14,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR[13]", x-6,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX[13]", x-5,y+14,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDR[14]", x-6,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDRX[14]", x-5,y+15,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FWR_ADDR[15]", x-6,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FWR_ADDRX[15]", x-5,y+15,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR[0]", x-6,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX[0]", x-5,y+0,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR[1]", x-6,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX[1]", x-5,y+0,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR[2]", x-6,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX[2]", x-5,y+1,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR[3]", x-6,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX[3]", x-5,y+1,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR[4]", x-6,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX[4]", x-5,y+2,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR[5]", x-6,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX[5]", x-5,y+2,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR[6]", x-6,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX[6]", x-5,y+3,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR[7]", x-6,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX[7]", x-5,y+3,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR[8]", x-6,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX[8]", x-5,y+4,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR[9]", x-6,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX[9]", x-5,y+4,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR[10]", x-6,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX[10]", x-5,y+5,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR[11]", x-6,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX[11]", x-5,y+5,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR[12]", x-6,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX[12]", x-5,y+6,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR[13]", x-6,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX[13]", x-5,y+6,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDR[14]", x-6,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDRX[14]", x-5,y+7,"CPE.RAM_I1") + self.create_conn(x,y,"RAM.FRD_ADDR[15]", x-6,y+7,"CPE.RAM_I2") + self.create_conn(x,y,"RAM.FRD_ADDRX[15]", x-5,y+7,"CPE.RAM_I2") if is_ram(x,y-16): self.create_conn(x,y,"RAM.FORW_CAS_WRAO", x,y-16,"RAM.FORW_CAS_WRAI") self.create_conn(x,y,"RAM.FORW_CAS_WRBO", x,y-16,"RAM.FORW_CAS_WRBI") @@ -2894,70 +3516,70 @@ class Die: self.create_conn(x,y,"RAM.FORW_CAS_BMBO", x,y-16,"RAM.FORW_CAS_BMBI") self.create_conn(x,y,"RAM.FORW_CAS_RDAO", x,y-16,"RAM.FORW_CAS_RDAI") self.create_conn(x,y,"RAM.FORW_CAS_RDBO", x,y-16,"RAM.FORW_CAS_RDBI") - self.create_conn(x,y,"RAM.FORW_UADDRAO_0", x,y-16,"RAM.FORW_UADDRAI_0") - self.create_conn(x,y,"RAM.FORW_UADDRAO_1", x,y-16,"RAM.FORW_UADDRAI_1") - self.create_conn(x,y,"RAM.FORW_UADDRAO_2", x,y-16,"RAM.FORW_UADDRAI_2") - self.create_conn(x,y,"RAM.FORW_UADDRAO_3", x,y-16,"RAM.FORW_UADDRAI_3") - self.create_conn(x,y,"RAM.FORW_UADDRAO_4", x,y-16,"RAM.FORW_UADDRAI_4") - self.create_conn(x,y,"RAM.FORW_UADDRAO_5", x,y-16,"RAM.FORW_UADDRAI_5") - self.create_conn(x,y,"RAM.FORW_UADDRAO_6", x,y-16,"RAM.FORW_UADDRAI_6") - self.create_conn(x,y,"RAM.FORW_UADDRAO_7", x,y-16,"RAM.FORW_UADDRAI_7") - self.create_conn(x,y,"RAM.FORW_UADDRAO_8", x,y-16,"RAM.FORW_UADDRAI_8") - self.create_conn(x,y,"RAM.FORW_UADDRAO_9", x,y-16,"RAM.FORW_UADDRAI_9") - self.create_conn(x,y,"RAM.FORW_UADDRAO_10", x,y-16,"RAM.FORW_UADDRAI_10") - self.create_conn(x,y,"RAM.FORW_UADDRAO_11", x,y-16,"RAM.FORW_UADDRAI_11") - self.create_conn(x,y,"RAM.FORW_UADDRAO_12", x,y-16,"RAM.FORW_UADDRAI_12") - self.create_conn(x,y,"RAM.FORW_UADDRAO_13", x,y-16,"RAM.FORW_UADDRAI_13") - self.create_conn(x,y,"RAM.FORW_UADDRAO_14", x,y-16,"RAM.FORW_UADDRAI_14") - self.create_conn(x,y,"RAM.FORW_UADDRAO_15", x,y-16,"RAM.FORW_UADDRAI_15") - self.create_conn(x,y,"RAM.FORW_LADDRAO_0", x,y-16,"RAM.FORW_LADDRAI_0") - self.create_conn(x,y,"RAM.FORW_LADDRAO_1", x,y-16,"RAM.FORW_LADDRAI_1") - self.create_conn(x,y,"RAM.FORW_LADDRAO_2", x,y-16,"RAM.FORW_LADDRAI_2") - self.create_conn(x,y,"RAM.FORW_LADDRAO_3", x,y-16,"RAM.FORW_LADDRAI_3") - self.create_conn(x,y,"RAM.FORW_LADDRAO_4", x,y-16,"RAM.FORW_LADDRAI_4") - self.create_conn(x,y,"RAM.FORW_LADDRAO_5", x,y-16,"RAM.FORW_LADDRAI_5") - self.create_conn(x,y,"RAM.FORW_LADDRAO_6", x,y-16,"RAM.FORW_LADDRAI_6") - self.create_conn(x,y,"RAM.FORW_LADDRAO_7", x,y-16,"RAM.FORW_LADDRAI_7") - self.create_conn(x,y,"RAM.FORW_LADDRAO_8", x,y-16,"RAM.FORW_LADDRAI_8") - self.create_conn(x,y,"RAM.FORW_LADDRAO_9", x,y-16,"RAM.FORW_LADDRAI_9") - self.create_conn(x,y,"RAM.FORW_LADDRAO_10", x,y-16,"RAM.FORW_LADDRAI_10") - self.create_conn(x,y,"RAM.FORW_LADDRAO_11", x,y-16,"RAM.FORW_LADDRAI_11") - self.create_conn(x,y,"RAM.FORW_LADDRAO_12", x,y-16,"RAM.FORW_LADDRAI_12") - self.create_conn(x,y,"RAM.FORW_LADDRAO_13", x,y-16,"RAM.FORW_LADDRAI_13") - self.create_conn(x,y,"RAM.FORW_LADDRAO_14", x,y-16,"RAM.FORW_LADDRAI_14") - self.create_conn(x,y,"RAM.FORW_LADDRAO_15", x,y-16,"RAM.FORW_LADDRAI_15") - self.create_conn(x,y,"RAM.FORW_UADDRBO_0", x,y-16,"RAM.FORW_UADDRBI_0") - self.create_conn(x,y,"RAM.FORW_UADDRBO_1", x,y-16,"RAM.FORW_UADDRBI_1") - self.create_conn(x,y,"RAM.FORW_UADDRBO_2", x,y-16,"RAM.FORW_UADDRBI_2") - self.create_conn(x,y,"RAM.FORW_UADDRBO_3", x,y-16,"RAM.FORW_UADDRBI_3") - self.create_conn(x,y,"RAM.FORW_UADDRBO_4", x,y-16,"RAM.FORW_UADDRBI_4") - self.create_conn(x,y,"RAM.FORW_UADDRBO_5", x,y-16,"RAM.FORW_UADDRBI_5") - self.create_conn(x,y,"RAM.FORW_UADDRBO_6", x,y-16,"RAM.FORW_UADDRBI_6") - self.create_conn(x,y,"RAM.FORW_UADDRBO_7", x,y-16,"RAM.FORW_UADDRBI_7") - self.create_conn(x,y,"RAM.FORW_UADDRBO_8", x,y-16,"RAM.FORW_UADDRBI_8") - self.create_conn(x,y,"RAM.FORW_UADDRBO_9", x,y-16,"RAM.FORW_UADDRBI_9") - self.create_conn(x,y,"RAM.FORW_UADDRBO_10", x,y-16,"RAM.FORW_UADDRBI_10") - self.create_conn(x,y,"RAM.FORW_UADDRBO_11", x,y-16,"RAM.FORW_UADDRBI_11") - self.create_conn(x,y,"RAM.FORW_UADDRBO_12", x,y-16,"RAM.FORW_UADDRBI_12") - self.create_conn(x,y,"RAM.FORW_UADDRBO_13", x,y-16,"RAM.FORW_UADDRBI_13") - self.create_conn(x,y,"RAM.FORW_UADDRBO_14", x,y-16,"RAM.FORW_UADDRBI_14") - self.create_conn(x,y,"RAM.FORW_UADDRBO_15", x,y-16,"RAM.FORW_UADDRBI_15") - self.create_conn(x,y,"RAM.FORW_LADDRBO_0", x,y-16,"RAM.FORW_LADDRBI_0") - self.create_conn(x,y,"RAM.FORW_LADDRBO_1", x,y-16,"RAM.FORW_LADDRBI_1") - self.create_conn(x,y,"RAM.FORW_LADDRBO_2", x,y-16,"RAM.FORW_LADDRBI_2") - self.create_conn(x,y,"RAM.FORW_LADDRBO_3", x,y-16,"RAM.FORW_LADDRBI_3") - self.create_conn(x,y,"RAM.FORW_LADDRBO_4", x,y-16,"RAM.FORW_LADDRBI_4") - self.create_conn(x,y,"RAM.FORW_LADDRBO_5", x,y-16,"RAM.FORW_LADDRBI_5") - self.create_conn(x,y,"RAM.FORW_LADDRBO_6", x,y-16,"RAM.FORW_LADDRBI_6") - self.create_conn(x,y,"RAM.FORW_LADDRBO_7", x,y-16,"RAM.FORW_LADDRBI_7") - self.create_conn(x,y,"RAM.FORW_LADDRBO_8", x,y-16,"RAM.FORW_LADDRBI_8") - self.create_conn(x,y,"RAM.FORW_LADDRBO_9", x,y-16,"RAM.FORW_LADDRBI_9") - self.create_conn(x,y,"RAM.FORW_LADDRBO_10", x,y-16,"RAM.FORW_LADDRBI_10") - self.create_conn(x,y,"RAM.FORW_LADDRBO_11", x,y-16,"RAM.FORW_LADDRBI_11") - self.create_conn(x,y,"RAM.FORW_LADDRBO_12", x,y-16,"RAM.FORW_LADDRBI_12") - self.create_conn(x,y,"RAM.FORW_LADDRBO_13", x,y-16,"RAM.FORW_LADDRBI_13") - self.create_conn(x,y,"RAM.FORW_LADDRBO_14", x,y-16,"RAM.FORW_LADDRBI_14") - self.create_conn(x,y,"RAM.FORW_LADDRBO_15", x,y-16,"RAM.FORW_LADDRBI_15") + self.create_conn(x,y,"RAM.FORW_UADDRAO[0]", x,y-16,"RAM.FORW_UADDRAI[0]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[1]", x,y-16,"RAM.FORW_UADDRAI[1]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[2]", x,y-16,"RAM.FORW_UADDRAI[2]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[3]", x,y-16,"RAM.FORW_UADDRAI[3]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[4]", x,y-16,"RAM.FORW_UADDRAI[4]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[5]", x,y-16,"RAM.FORW_UADDRAI[5]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[6]", x,y-16,"RAM.FORW_UADDRAI[6]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[7]", x,y-16,"RAM.FORW_UADDRAI[7]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[8]", x,y-16,"RAM.FORW_UADDRAI[8]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[9]", x,y-16,"RAM.FORW_UADDRAI[9]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[10]", x,y-16,"RAM.FORW_UADDRAI[10]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[11]", x,y-16,"RAM.FORW_UADDRAI[11]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[12]", x,y-16,"RAM.FORW_UADDRAI[12]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[13]", x,y-16,"RAM.FORW_UADDRAI[13]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[14]", x,y-16,"RAM.FORW_UADDRAI[14]") + self.create_conn(x,y,"RAM.FORW_UADDRAO[15]", x,y-16,"RAM.FORW_UADDRAI[15]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[0]", x,y-16,"RAM.FORW_LADDRAI[0]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[1]", x,y-16,"RAM.FORW_LADDRAI[1]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[2]", x,y-16,"RAM.FORW_LADDRAI[2]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[3]", x,y-16,"RAM.FORW_LADDRAI[3]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[4]", x,y-16,"RAM.FORW_LADDRAI[4]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[5]", x,y-16,"RAM.FORW_LADDRAI[5]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[6]", x,y-16,"RAM.FORW_LADDRAI[6]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[7]", x,y-16,"RAM.FORW_LADDRAI[7]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[8]", x,y-16,"RAM.FORW_LADDRAI[8]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[9]", x,y-16,"RAM.FORW_LADDRAI[9]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[10]", x,y-16,"RAM.FORW_LADDRAI[10]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[11]", x,y-16,"RAM.FORW_LADDRAI[11]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[12]", x,y-16,"RAM.FORW_LADDRAI[12]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[13]", x,y-16,"RAM.FORW_LADDRAI[13]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[14]", x,y-16,"RAM.FORW_LADDRAI[14]") + self.create_conn(x,y,"RAM.FORW_LADDRAO[15]", x,y-16,"RAM.FORW_LADDRAI[15]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[0]", x,y-16,"RAM.FORW_UADDRBI[0]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[1]", x,y-16,"RAM.FORW_UADDRBI[1]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[2]", x,y-16,"RAM.FORW_UADDRBI[2]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[3]", x,y-16,"RAM.FORW_UADDRBI[3]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[4]", x,y-16,"RAM.FORW_UADDRBI[4]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[5]", x,y-16,"RAM.FORW_UADDRBI[5]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[6]", x,y-16,"RAM.FORW_UADDRBI[6]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[7]", x,y-16,"RAM.FORW_UADDRBI[7]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[8]", x,y-16,"RAM.FORW_UADDRBI[8]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[9]", x,y-16,"RAM.FORW_UADDRBI[9]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[10]", x,y-16,"RAM.FORW_UADDRBI[10]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[11]", x,y-16,"RAM.FORW_UADDRBI[11]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[12]", x,y-16,"RAM.FORW_UADDRBI[12]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[13]", x,y-16,"RAM.FORW_UADDRBI[13]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[14]", x,y-16,"RAM.FORW_UADDRBI[14]") + self.create_conn(x,y,"RAM.FORW_UADDRBO[15]", x,y-16,"RAM.FORW_UADDRBI[15]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[0]", x,y-16,"RAM.FORW_LADDRBI[0]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[1]", x,y-16,"RAM.FORW_LADDRBI[1]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[2]", x,y-16,"RAM.FORW_LADDRBI[2]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[3]", x,y-16,"RAM.FORW_LADDRBI[3]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[4]", x,y-16,"RAM.FORW_LADDRBI[4]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[5]", x,y-16,"RAM.FORW_LADDRBI[5]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[6]", x,y-16,"RAM.FORW_LADDRBI[6]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[7]", x,y-16,"RAM.FORW_LADDRBI[7]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[8]", x,y-16,"RAM.FORW_LADDRBI[8]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[9]", x,y-16,"RAM.FORW_LADDRBI[9]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[10]", x,y-16,"RAM.FORW_LADDRBI[10]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[11]", x,y-16,"RAM.FORW_LADDRBI[11]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[12]", x,y-16,"RAM.FORW_LADDRBI[12]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[13]", x,y-16,"RAM.FORW_LADDRBI[13]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[14]", x,y-16,"RAM.FORW_LADDRBI[14]") + self.create_conn(x,y,"RAM.FORW_LADDRBO[15]", x,y-16,"RAM.FORW_LADDRBI[15]") self.create_conn(x,y,"RAM.FORW_UA0CLKO", x,y-16,"RAM.FORW_UA0CLKI") self.create_conn(x,y,"RAM.FORW_UA0ENO", x,y-16,"RAM.FORW_UA0ENI") self.create_conn(x,y,"RAM.FORW_UA0WEO", x,y-16,"RAM.FORW_UA0WEI") @@ -3002,6 +3624,8 @@ class Die: self.create_io(x,y) if is_ram(x,y): self.create_ram(x,y) + if is_serdes(x,y): + self.create_serdes(x,y) self.create_pll() self.global_mesh() self.edge_select() diff --git a/tools/extract_constids.py b/tools/extract_constids.py index 9c89e85..c96f098 100644 --- a/tools/extract_constids.py +++ b/tools/extract_constids.py @@ -12,7 +12,7 @@ parser.add_argument('-o', '--outfile', dest='outfile', type=argparse.FileType('w help="output HTML file") def export_name(name,fout): - if name not in consts: + if name not in consts and "[" not in name: print(f"X({name})", file=fout) consts.add(name) else: