From 9ccc8588c0c99d7cf9f8db3448171f8144da81d8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 21 Mar 2025 10:01:41 +0100 Subject: [PATCH] RAM configuration bits --- libgm/src/TileBitDatabase.cpp | 43 ++++++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/libgm/src/TileBitDatabase.cpp b/libgm/src/TileBitDatabase.cpp index 158444d..a5e0701 100644 --- a/libgm/src/TileBitDatabase.cpp +++ b/libgm/src/TileBitDatabase.cpp @@ -440,19 +440,36 @@ RamBitDatabase::RamBitDatabase() : BaseBitDatabase(Die::RAM_BLOCK_SIZE * 8) add_word_settings("RAM_cfg_forward_b1_clk", 11 * 8, 8); add_word_settings("RAM_cfg_forward_b1_en", 12 * 8, 8); add_word_settings("RAM_cfg_forward_b1_we", 13 * 8, 8); - add_word_settings("RAM_cfg_sram_mode_i_cfg", 14 * 8, 8); - add_word_settings("RAM_cfg_in_out_cfg", 15 * 8, 8); - add_word_settings("RAM_cfg_out_cfg", 16 * 8, 8); - add_word_settings("RAM_cfg_out_b1_cfg", 17 * 8, 8); - add_word_settings("RAM_cfg_wrmode_outreg", 18 * 8, 8); - add_word_settings("RAM_cfg_inversion", 19 * 8, 8); - add_word_settings("RAM_cfg_inv_ecc_dyn", 20 * 8, 8); - add_word_settings("RAM_cfg_fifo_sync_empty", 21 * 8, 8); - add_word_settings("RAM_cfg_fifo_empty", 22 * 8, 8); - add_word_settings("RAM_cfg_fifo_aync_full", 23 * 8, 8); - add_word_settings("RAM_cfg_fifo_full", 24 * 8, 8); - add_word_settings("RAM_cfg_sram_delay", 25 * 8, 8); - add_word_settings("RAM_cfg_datbm_cascade", 26 * 8, 8); + add_word_settings("RAM_cfg_sram_mode", 14 * 8, 2); + add_word_settings("RAM_cfg_input_config_a0", 14 * 8 + 2, 3); + add_word_settings("RAM_cfg_input_config_a1", 14 * 8 + 5, 3); + add_word_settings("RAM_cfg_input_config_b0", 15 * 8 + 1, 3); + add_word_settings("RAM_cfg_input_config_b1", 15 * 8 + 4, 3); + add_word_settings("RAM_cfg_output_config_a0", 15 * 8 + 7, 3); + add_word_settings("RAM_cfg_output_config_a1", 16 * 8 + 2, 3); + add_word_settings("RAM_cfg_output_config_b0", 16 * 8 + 5, 3); + add_word_settings("RAM_cfg_output_config_b1", 17 * 8, 3); + add_word_settings("RAM_cfg_a0_writemode", 18 * 8 + 0, 1); + add_word_settings("RAM_cfg_a1_writemode", 18 * 8 + 1, 1); + add_word_settings("RAM_cfg_b0_writemode", 18 * 8 + 2, 1); + add_word_settings("RAM_cfg_b1_writemode", 18 * 8 + 3, 1); + add_word_settings("RAM_cfg_a0_set_outputreg", 18 * 8 + 4, 1); + add_word_settings("RAM_cfg_a1_set_outputreg", 18 * 8 + 5, 1); + add_word_settings("RAM_cfg_b0_set_outputreg", 18 * 8 + 6, 1); + add_word_settings("RAM_cfg_b1_set_outputreg", 18 * 8 + 7, 1); + add_word_settings("RAM_cfg_inversion_a0", 19 * 8, 3); + add_word_settings("RAM_cfg_inversion_a1", 19 * 8 + 3, 3); + add_word_settings("RAM_cfg_inversion_b0", 19 * 8 + 6, 3); + add_word_settings("RAM_cfg_inversion_b1", 20 * 8 + 1, 3); + add_word_settings("RAM_cfg_ecc_enable", 20 * 8 + 4, 2); + add_word_settings("RAM_cfg_dyn_stat_select", 20 * 8 + 6, 2); + add_word_settings("RAM_cfg_fifo_sync_enable", 21 * 8, 1); + add_word_settings("RAM_cfg_almost_empty_offset", 21 * 8 + 1, 15); + add_word_settings("RAM_cfg_fifo_async_enable", 23 * 8, 1); + add_word_settings("RAM_cfg_almost_full_offset", 23 * 8 + 1, 15); + add_word_settings("RAM_cfg_sram_delay", 25 * 8, 6); + add_word_settings("RAM_cfg_datbm_sel", 26 * 8, 4); + add_word_settings("RAM_cfg_cascade_enable", 26 * 8 + 4, 2); add_unknowns(); }