From 97cb94755f5d3be08030184e2feaeeb259903c3f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 4 Dec 2024 17:56:16 +0100 Subject: [PATCH] Add detection of unknown bits and conflicts --- libgm/include/TileBitDatabase.hpp | 16 +++--- libgm/src/ChipConfig.cpp | 8 +-- libgm/src/TileBitDatabase.cpp | 89 ++++++++++++++----------------- 3 files changed, 54 insertions(+), 59 deletions(-) diff --git a/libgm/include/TileBitDatabase.hpp b/libgm/include/TileBitDatabase.hpp index c5e9278..13f0850 100644 --- a/libgm/include/TileBitDatabase.hpp +++ b/libgm/include/TileBitDatabase.hpp @@ -42,22 +42,26 @@ struct WordSettingBits class BaseBitDatabase { public: - BaseBitDatabase(); + BaseBitDatabase(int num_bits); virtual ~BaseBitDatabase(); + TileConfig data_to_config(const vector &data); + std::vector config_to_data(const TileConfig &cfg); + protected: void add_word_settings(const std::string &name, int start, int end); + void add_unknowns(); std::vector bits_to_bytes(std::vector &bits); + int num_bits; map words; + std::vector known_bits; }; -class TileBitDatabase : BaseBitDatabase +class TileBitDatabase : public BaseBitDatabase { public: TileBitDatabase(const int x, const int y); - TileConfig tile_data_to_config(const vector &data); - std::vector config_to_tile_data(const TileConfig &cfg); private: void add_sb_big(int index, int start); @@ -76,12 +80,10 @@ class TileBitDatabase : BaseBitDatabase void add_bottom_edge(int index, int start); }; -class RamBitDatabase : BaseBitDatabase +class RamBitDatabase : public BaseBitDatabase { public: RamBitDatabase(); - TileConfig ram_data_to_config(const vector &data); - std::vector config_to_ram_data(const TileConfig &cfg); }; class DatabaseConflictError : public runtime_error diff --git a/libgm/src/ChipConfig.cpp b/libgm/src/ChipConfig.cpp index d1405f7..c0caddc 100644 --- a/libgm/src/ChipConfig.cpp +++ b/libgm/src/ChipConfig.cpp @@ -121,7 +121,7 @@ Chip ChipConfig::to_chip() const if (tiles.count(loc)) { TileBitDatabase db(x, y); const TileConfig &cfg = tiles.at(loc); - die.write_latch(x, y, db.config_to_tile_data(cfg)); + die.write_latch(x, y, db.config_to_data(cfg)); } } } @@ -132,7 +132,7 @@ Chip ChipConfig::to_chip() const loc.x = x; if (brams.count(loc)) { const TileConfig &cfg = brams.at(loc); - die.write_ram(x, y, ram_db.config_to_ram_data(cfg)); + die.write_ram(x, y, ram_db.config_to_data(cfg)); } if (bram_data.count(loc)) die.write_ram_data(x, y, bram_data.at(loc), 0); @@ -157,7 +157,7 @@ ChipConfig ChipConfig::from_chip(const Chip &chip) loc.x = x; TileBitDatabase db(x, y); if (!die.is_latch_empty(x, y)) - cc.tiles.emplace(loc, db.tile_data_to_config(die.get_latch_config(x, y))); + cc.tiles.emplace(loc, db.data_to_config(die.get_latch_config(x, y))); } } RamBitDatabase ram_db; @@ -166,7 +166,7 @@ ChipConfig ChipConfig::from_chip(const Chip &chip) for (int x = 0; x < die.get_max_ram_col(); x++) { loc.x = x; if (!die.is_ram_empty(x, y)) { - cc.brams.emplace(loc, ram_db.ram_data_to_config(die.get_ram_config(x, y))); + cc.brams.emplace(loc, ram_db.data_to_config(die.get_ram_config(x, y))); if (!die.is_ram_data_empty(x, y)) { cc.bram_data.emplace(loc, die.get_ram_data(x, y)); } diff --git a/libgm/src/TileBitDatabase.cpp b/libgm/src/TileBitDatabase.cpp index bd76568..d5f8e22 100644 --- a/libgm/src/TileBitDatabase.cpp +++ b/libgm/src/TileBitDatabase.cpp @@ -51,7 +51,7 @@ bool is_array_empty(std::vector &array) return true; } -BaseBitDatabase::BaseBitDatabase() {} +BaseBitDatabase::BaseBitDatabase(int num_bits) : num_bits(num_bits), known_bits(num_bits, false) {} BaseBitDatabase::~BaseBitDatabase() {} void BaseBitDatabase::add_word_settings(const std::string &name, int start, int end) @@ -59,9 +59,22 @@ void BaseBitDatabase::add_word_settings(const std::string &name, int start, int if (words.find(name) != words.end()) throw DatabaseConflictError(fmt("word " << name << " already exists in DB")); + for (int i = start; i < start + end; i++) { + if (known_bits[i]) + throw DatabaseConflictError(fmt("bit " << i << " for word " << name << " already mapped")); + known_bits[i] = true; + } words[name] = {start, start + end}; } +void BaseBitDatabase::add_unknowns() +{ + for (int i = 0; i < num_bits; i++) { + if (!known_bits[i]) + words[stringf("UNKNOWN_%03d", i)] = {i, i + 1}; + } +} + std::vector BaseBitDatabase::bits_to_bytes(std::vector &bits) { std::vector val; @@ -78,6 +91,28 @@ std::vector BaseBitDatabase::bits_to_bytes(std::vector &bits) return val; } +std::vector BaseBitDatabase::config_to_data(const TileConfig &cfg) +{ + std::vector tile(num_bits, false); + for (auto &w : cfg.cwords) { + words[w.name].set_value(tile, w.value); + } + return bits_to_bytes(tile); +} + +TileConfig BaseBitDatabase::data_to_config(const vector &data) +{ + TileConfig cfg; + std::vector d = data_bytes_to_array(data, num_bits * 8); + for (auto &w : words) { + auto val = w.second.get_value(d); + if (is_array_empty(val)) + continue; + cfg.add_word(w.first, val); + } + return cfg; +} + void TileBitDatabase::add_sb_big(int index, int start) { add_word_settings(stringf("SB_BIG_%02d", index), start, 15); } void TileBitDatabase::add_sb_sml(int index, int start) { add_word_settings(stringf("SB_SML_%02d", index), start, 12); } @@ -118,7 +153,7 @@ void TileBitDatabase::add_bottom_edge(int index, int start) add_word_settings(stringf("BOTTOM_EDGE_%d", index), start, 48); } -TileBitDatabase::TileBitDatabase(const int x, const int y) : BaseBitDatabase() +TileBitDatabase::TileBitDatabase(const int x, const int y) : BaseBitDatabase(Die::LATCH_BLOCK_SIZE * 8) { bool is_core = false; if (y == 0) { @@ -150,7 +185,7 @@ TileBitDatabase::TileBitDatabase(const int x, const int y) : BaseBitDatabase() if (!is_core) { add_gpio(0); add_edge_io(1, 9 * 8); - add_edge_io(2, 10 * 8); + add_edge_io(2, 11 * 8); } int pos = 64; @@ -179,31 +214,10 @@ TileBitDatabase::TileBitDatabase(const int x, const int y) : BaseBitDatabase() add_sb_sml(i * 2 + 2, (pos + 1) * 8 + 4); pos += 3; } + add_unknowns(); } -std::vector TileBitDatabase::config_to_tile_data(const TileConfig &cfg) -{ - std::vector tile(Die::LATCH_BLOCK_SIZE * 8, false); - for (auto &w : cfg.cwords) { - words[w.name].set_value(tile, w.value); - } - return bits_to_bytes(tile); -} - -TileConfig TileBitDatabase::tile_data_to_config(const vector &data) -{ - TileConfig cfg; - std::vector d = data_bytes_to_array(data, Die::LATCH_BLOCK_SIZE); - for (auto &w : words) { - auto val = w.second.get_value(d); - if (is_array_empty(val)) - continue; - cfg.add_word(w.first, val); - } - return cfg; -} - -RamBitDatabase::RamBitDatabase() : BaseBitDatabase() +RamBitDatabase::RamBitDatabase() : BaseBitDatabase(Die::RAM_BLOCK_SIZE * 8) { add_word_settings("RAM_cfg_forward_a_addr", 0 * 8, 8); add_word_settings("RAM_cfg_forward_b_addr", 1 * 8, 8); @@ -232,28 +246,7 @@ RamBitDatabase::RamBitDatabase() : BaseBitDatabase() add_word_settings("RAM_cfg_fifo_full", 24 * 8, 8); add_word_settings("RAM_cfg_sram_delay", 25 * 8, 8); add_word_settings("RAM_cfg_datbm_cascade", 26 * 8, 8); -} - -std::vector RamBitDatabase::config_to_ram_data(const TileConfig &cfg) -{ - std::vector tile(Die::RAM_BLOCK_SIZE * 8, false); - for (auto &w : cfg.cwords) { - words[w.name].set_value(tile, w.value); - } - return bits_to_bytes(tile); -} - -TileConfig RamBitDatabase::ram_data_to_config(const vector &data) -{ - TileConfig cfg; - std::vector d = data_bytes_to_array(data, Die::RAM_BLOCK_SIZE); - for (auto &w : words) { - auto val = w.second.get_value(d); - if (is_array_empty(val)) - continue; - cfg.add_word(w.first, val); - } - return cfg; + add_unknowns(); } vector WordSettingBits::get_value(const vector &tile) const