diff --git a/gatemate/die.py b/gatemate/die.py index b3a5096..ec2cac2 100644 --- a/gatemate/die.py +++ b/gatemate/die.py @@ -25,6 +25,8 @@ SERDES_X_POS = 1 SERDES_Y_POS = 121 CTRL_X_POS = -2 CTRL_Y_POS = -2 +RAM_INPUT = 0 +RAM_OUTPUT = 1 def max_row(): return 131 @@ -176,6 +178,15 @@ class Pin: wire_type : str use_alias_conn: bool = False +@dataclass(eq=True, order=True) +class PinConstr: + name : str + rel_x : int + rel_y : int + output: int + pin_num : int + skip: bool = False + @dataclass(eq=True, order=True) class Group: name : str @@ -1466,6 +1477,966 @@ def get_primitives_for_type(type): def get_primitive_pins(bel): return PRIMITIVES_PINS[bel] +def get_pins_constraint(type_name, prim_name, prim_type): + val = [] + if prim_type=="USR_RSTN": + val.append(PinConstr("USR_RSTN", -CTRL_X_POS+1, -CTRL_Y_POS+66, RAM_INPUT, 2)) + elif prim_type=="CFG_CTRL": + val.append(PinConstr("DATA[7]", -CTRL_X_POS+1, -CTRL_Y_POS+16, RAM_OUTPUT, 1)) + val.append(PinConstr("DATA[6]", -CTRL_X_POS+1, -CTRL_Y_POS+15, RAM_OUTPUT, 1)) + val.append(PinConstr("DATA[5]", -CTRL_X_POS+1, -CTRL_Y_POS+14, RAM_OUTPUT, 1)) + val.append(PinConstr("DATA[4]", -CTRL_X_POS+1, -CTRL_Y_POS+13, RAM_OUTPUT, 1)) + val.append(PinConstr("DATA[3]", -CTRL_X_POS+1, -CTRL_Y_POS+12, RAM_OUTPUT, 1)) + val.append(PinConstr("DATA[2]", -CTRL_X_POS+1, -CTRL_Y_POS+11, RAM_OUTPUT, 1)) + val.append(PinConstr("DATA[1]", -CTRL_X_POS+1, -CTRL_Y_POS+10, RAM_OUTPUT, 1)) + val.append(PinConstr("DATA[0]", -CTRL_X_POS+1, -CTRL_Y_POS+ 9, RAM_OUTPUT, 1)) + val.append(PinConstr("CLK",-CTRL_X_POS+1, -CTRL_Y_POS+6, RAM_OUTPUT, 1)) + val.append(PinConstr("EN",-CTRL_X_POS+1, -CTRL_Y_POS+7, RAM_OUTPUT, 1)) + val.append(PinConstr("VALID",-CTRL_X_POS+1, -CTRL_Y_POS+8, RAM_OUTPUT, 1)) + val.append(PinConstr("RECFG",-CTRL_X_POS+1, -CTRL_Y_POS+5, RAM_OUTPUT, 1)) + elif prim_type=="RAM": + val.append(PinConstr("C_ADDRA[0]", -3, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("C_ADDRA[1]", -3, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("C_ADDRA[2]", -3, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("C_ADDRA[3]", -3, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("C_ADDRA[4]", -3, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("C_ADDRA[5]", -3, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("C_ADDRA[6]", -3, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("C_ADDRA[7]", -3, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("C_ADDRB[0]", 2, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("C_ADDRB[1]", 2, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("C_ADDRB[2]", 2, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("C_ADDRB[3]", 2, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("C_ADDRB[4]", 2, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("C_ADDRB[5]", 2, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("C_ADDRB[6]", 2, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("C_ADDRB[7]", 2, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("CLKA[0]", -6, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("CLKA[1]", -3, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("ENA[0]", -6, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("ENA[1]", -3, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("GLWEA[0]", -6, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("GLWEA[1]", -3, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA0[0]", -5, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0[1]", -5, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA0[2]", -5, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0[3]", -5, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA0[4]", -5, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0[5]", -5, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA0[6]", -5, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0[7]", -5, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA0[8]", -5, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0[9]", -5, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA0[10]", -5, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0[11]", -5, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA0[12]", -5, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0[13]", -5, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA0[14]", -5, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0[15]", -5, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA0X[0]", -5, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[1]", -4, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[2]", -5, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[3]", -4, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[4]", -5, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[5]", -4, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[6]", -5, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[7]", -4, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[8]", -5, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[9]", -4, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[10]", -5, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[11]", -4, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[12]", -6, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[13]", -5, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[14]", -6, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA0X[15]", -5, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[0]", -1, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[1]", -1, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[2]", -1, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[3]", -1, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[4]", -1, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[5]", -1, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[6]", -1, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[7]", -1, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[8]", -1, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[9]", -1, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[10]", -1, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[11]", -1, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[12]", -1, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[13]", -1, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[14]", -1, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[15]", -1, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[16]", -3, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[17]", -3, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[18]", -3, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[19]", -3, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[0]", -2, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[1]", -2, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[2]", -2, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[3]", -2, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[4]", -2, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[5]", -2, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[6]", -2, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[7]", -2, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[8]", -2, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[9]", -2, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[10]", -2, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[11]", -2, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[12]", -2, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[13]", -2, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[14]", -2, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[15]", -2, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[16]", -4, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[17]", -4, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[18]", -4, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[19]", -4, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("CLKA[2]", -6, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("CLKA[3]", -3, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("ENA[2]", -6, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("ENA[3]", -3, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("GLWEA[2]", -6, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("GLWEA[3]", -3, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA1[0]", -5, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1[1]", -5, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA1[2]", -5, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1[3]", -5, 9, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA1[4]", -5, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1[5]", -5, 10, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA1[6]", -5, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1[7]", -5, 11, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA1[8]", -5, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1[9]", -5, 12, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA1[10]", -5, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1[11]", -5, 13, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA1[12]", -5, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1[13]", -5, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA1[14]", -5, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1[15]", -5, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRA1X[0]", -5, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[1]", -4, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[2]", -5, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[3]", -4, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[4]", -5, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[5]", -4, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[6]", -5, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[7]", -4, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[8]", -5, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[9]", -4, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[10]", -5, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[11]", -4, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[12]", -6, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[13]", -5, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[14]", -6, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRA1X[15]", -5, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[20]", -1, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[21]", -1, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[22]", -1, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[23]", -1, 9, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[24]", -1, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[25]", -1, 10, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[26]", -1, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[27]", -1, 11, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[28]", -1, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[29]", -1, 12, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[30]", -1, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[31]", -1, 13, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[32]", -1, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[33]", -1, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[34]", -1, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[35]", -1, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[36]", -3, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[37]", -3, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("DIA[38]", -3, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("DIA[39]", -3, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[20]", -2, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[21]", -2, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[22]", -2, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[23]", -2, 9, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[24]", -2, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[25]", -2, 10, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[26]", -2, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[27]", -2, 11, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[28]", -2, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[29]", -2, 12, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[30]", -2, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[31]", -2, 13, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[32]", -2, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[33]", -2, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[34]", -2, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[35]", -2, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[36]", -4, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[37]", -4, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("WEA[38]", -4, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("WEA[39]", -4, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("CLKB[0]", 2, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("CLKB[1]", 5, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("ENB[0]", 2, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("ENB[1]", 5, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("GLWEB[0]", 2, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("GLWEB[1]", 5, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB0[0]", 4, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0[1]", 4, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB0[2]", 4, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0[3]", 4, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB0[4]", 4, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0[5]", 4, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB0[6]", 4, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0[7]", 4, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB0[8]", 4, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0[9]", 4, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB0[10]", 4, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0[11]", 4, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB0[12]", 4, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0[13]", 4, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB0[14]", 4, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0[15]", 4, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB0X[0]", 3, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[1]", 4, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[2]", 3, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[3]", 4, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[4]", 3, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[5]", 4, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[6]", 3, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[7]", 4, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[8]", 3, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[9]", 4, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[10]", 3, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[11]", 4, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[12]", 4, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[13]", 5, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[14]", 4, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB0X[15]", 5, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[0]", 1, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[1]", 1, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[2]", 1, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[3]", 1, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[4]", 1, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[5]", 1, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[6]", 1, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[7]", 1, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[8]", 1, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[9]", 1, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[10]", 1, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[11]", 1, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[12]", 1, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[13]", 1, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[14]", 1, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[15]", 1, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[16]", 3, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[17]", 3, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[18]", 3, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[19]", 3, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[0]", 0, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[1]", 0, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[2]", 0, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[3]", 0, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[4]", 0, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[5]", 0, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[6]", 0, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[7]", 0, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[8]", 0, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[9]", 0, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[10]", 0, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[11]", 0, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[12]", 0, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[13]", 0, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[14]", 0, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[15]", 0, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[16]", 2, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[17]", 2, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[18]", 2, 7, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[19]", 2, 7, RAM_OUTPUT, 2)) + val.append(PinConstr("CLKB[2]", 2, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("CLKB[3]", 5, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("ENB[2]", 2, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("ENB[3]", 5, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("GLWEB[2]", 2, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("GLWEB[3]", 5, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB1[0]", 4, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1[1]", 4, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB1[2]", 4, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1[3]", 4, 9, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB1[4]", 4, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1[5]", 4, 10, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB1[6]", 4, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1[7]", 4, 11, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB1[8]", 4, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1[9]", 4, 12, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB1[10]", 4, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1[11]", 4, 13, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB1[12]", 4, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1[13]", 4, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB1[14]", 4, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1[15]", 4, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("ADDRB1X[0]", 3, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[1]", 4, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[2]", 3, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[3]", 4, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[4]", 3, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[5]", 4, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[6]", 3, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[7]", 4, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[8]", 3, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[9]", 4, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[10]", 3, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[11]", 4, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[12]", 4, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[13]", 5, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[14]", 4, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("ADDRB1X[15]", 5, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[20]", 1, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[21]", 1, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[22]", 1, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[23]", 1, 9, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[24]", 1, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[25]", 1, 10, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[26]", 1, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[27]", 1, 11, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[28]", 1, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[29]", 1, 12, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[30]", 1, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[31]", 1, 13, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[32]", 1, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[33]", 1, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[34]", 1, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[35]", 1, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[36]", 3, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[37]", 3, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("DIB[38]", 3, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("DIB[39]", 3, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[20]", 0, 8, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[21]", 0, 8, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[22]", 0, 9, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[23]", 0, 9, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[24]", 0, 10, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[25]", 0, 10, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[26]", 0, 11, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[27]", 0, 11, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[28]", 0, 12, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[29]", 0, 12, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[30]", 0, 13, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[31]", 0, 13, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[32]", 0, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[33]", 0, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[34]", 0, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[35]", 0, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[36]", 2, 14, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[37]", 2, 14, RAM_OUTPUT, 2)) + val.append(PinConstr("WEB[38]", 2, 15, RAM_OUTPUT, 1)) + val.append(PinConstr("WEB[39]", 2, 15, RAM_OUTPUT, 2)) + val.append(PinConstr("F_RSTN", -6, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("DOA[0]", -1, 0, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[0]", -2, 0, RAM_INPUT, 2)) + val.append(PinConstr("DOA[1]", -1, 0, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[1]", -1, 0, RAM_INPUT, 2)) + val.append(PinConstr("DOA[2]", -1, 1, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[2]", -2, 1, RAM_INPUT, 2)) + val.append(PinConstr("DOA[3]", -1, 1, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[3]", -1, 1, RAM_INPUT, 2)) + val.append(PinConstr("DOA[4]", -1, 2, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[4]", -2, 2, RAM_INPUT, 2)) + val.append(PinConstr("DOA[5]", -1, 2, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[5]", -1, 2, RAM_INPUT, 2)) + val.append(PinConstr("DOA[6]", -1, 3, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[6]", -2, 3, RAM_INPUT, 2)) + val.append(PinConstr("DOA[7]", -1, 3, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[7]", -1, 3, RAM_INPUT, 2)) + val.append(PinConstr("DOA[8]", -1, 4, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[8]", -2, 4, RAM_INPUT, 2)) + val.append(PinConstr("DOA[9]", -1, 4, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[9]", -1, 4, RAM_INPUT, 2)) + val.append(PinConstr("DOA[10]", -1, 5, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[10]", -2, 5, RAM_INPUT, 2)) + val.append(PinConstr("DOA[11]", -1, 5, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[11]", -1, 5, RAM_INPUT, 2)) + val.append(PinConstr("DOA[12]", -1, 6, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[12]", -2, 6, RAM_INPUT, 2)) + val.append(PinConstr("DOA[13]", -1, 6, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[13]", -1, 6, RAM_INPUT, 2)) + val.append(PinConstr("DOA[14]", -1, 7, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[14]", -2, 7, RAM_INPUT, 2)) + val.append(PinConstr("DOA[15]", -1, 7, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[15]", -1, 7, RAM_INPUT, 2)) + val.append(PinConstr("DOA[16]", -3, 6, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[16]", -4, 6, RAM_INPUT, 2)) + val.append(PinConstr("DOA[17]", -3, 6, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[17]", -3, 6, RAM_INPUT, 2)) + val.append(PinConstr("DOA[18]", -3, 7, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[18]", -4, 7, RAM_INPUT, 2)) + val.append(PinConstr("DOA[19]", -3, 7, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[19]", -3, 7, RAM_INPUT, 2)) + val.append(PinConstr("DOA[20]", -1, 8, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[20]", -2, 8, RAM_INPUT, 2)) + val.append(PinConstr("DOA[21]", -1, 8, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[21]", -1, 8, RAM_INPUT, 2)) + val.append(PinConstr("DOA[22]", -1, 9, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[22]", -2, 9, RAM_INPUT, 2)) + val.append(PinConstr("DOA[23]", -1, 9, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[23]", -1, 9, RAM_INPUT, 2)) + val.append(PinConstr("DOA[24]", -1, 10, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[24]", -2, 10, RAM_INPUT, 2)) + val.append(PinConstr("DOA[25]", -1, 10, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[25]", -1, 10, RAM_INPUT, 2)) + val.append(PinConstr("DOA[26]", -1, 11, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[26]", -2, 11, RAM_INPUT, 2)) + val.append(PinConstr("DOA[27]", -1, 11, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[27]", -1, 11, RAM_INPUT, 2)) + val.append(PinConstr("DOA[28]", -1, 12, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[28]", -2, 12, RAM_INPUT, 2)) + val.append(PinConstr("DOA[29]", -1, 12, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[29]", -1, 12, RAM_INPUT, 2)) + val.append(PinConstr("DOA[30]", -1, 13, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[30]", -2, 13, RAM_INPUT, 2)) + val.append(PinConstr("DOA[31]", -1, 13, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[31]", -1, 13, RAM_INPUT, 2)) + val.append(PinConstr("DOA[32]", -1, 14, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[32]", -2, 14, RAM_INPUT, 2)) + val.append(PinConstr("DOA[33]", -1, 14, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[33]", -1, 14, RAM_INPUT, 2)) + val.append(PinConstr("DOA[34]", -1, 15, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[34]", -2, 15, RAM_INPUT, 2)) + val.append(PinConstr("DOA[35]", -1, 15, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[35]", -1, 15, RAM_INPUT, 2)) + val.append(PinConstr("DOA[36]", -3, 14, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[36]", -4, 14, RAM_INPUT, 2)) + val.append(PinConstr("DOA[37]", -3, 14, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[37]", -3, 14, RAM_INPUT, 2)) + val.append(PinConstr("DOA[38]", -3, 15, RAM_INPUT, 1)) + val.append(PinConstr("DOAX[38]", -4, 15, RAM_INPUT, 2)) + val.append(PinConstr("DOA[39]", -3, 15, RAM_INPUT, 2)) +# val.append(PinConstr("DOAX[39]", -3, 15, RAM_INPUT, 2)) + val.append(PinConstr("CLOCKA[1]", -3, 10, RAM_INPUT, 1)) + val.append(PinConstr("CLOCKA[2]", -3, 11, RAM_INPUT, 1)) + val.append(PinConstr("CLOCKA[3]", -3, 12, RAM_INPUT, 1)) + val.append(PinConstr("CLOCKA[4]", -3, 13, RAM_INPUT, 1)) + val.append(PinConstr("DOB[0]", 1, 0, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[0]", 0, 0, RAM_INPUT, 2)) + val.append(PinConstr("DOB[1]", 1, 0, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[1]", 1, 0, RAM_INPUT, 2)) + val.append(PinConstr("DOB[2]", 1, 1, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[2]", 0, 1, RAM_INPUT, 2)) + val.append(PinConstr("DOB[3]", 1, 1, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[3]", 1, 1, RAM_INPUT, 2)) + val.append(PinConstr("DOB[4]", 1, 2, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[4]", 0, 2, RAM_INPUT, 2)) + val.append(PinConstr("DOB[5]", 1, 2, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[5]", 1, 2, RAM_INPUT, 2)) + val.append(PinConstr("DOB[6]", 1, 3, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[6]", 0, 3, RAM_INPUT, 2)) + val.append(PinConstr("DOB[7]", 1, 3, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[7]", 1, 3, RAM_INPUT, 2)) + val.append(PinConstr("DOB[8]", 1, 4, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[8]", 0, 4, RAM_INPUT, 2)) + val.append(PinConstr("DOB[9]", 1, 4, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[9]", 1, 4, RAM_INPUT, 2)) + val.append(PinConstr("DOB[10]", 1, 5, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[10]", 0, 5, RAM_INPUT, 2)) + val.append(PinConstr("DOB[11]", 1, 5, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[11]", 1, 5, RAM_INPUT, 2)) + val.append(PinConstr("DOB[12]", 1, 6, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[12]", 0, 6, RAM_INPUT, 2)) + val.append(PinConstr("DOB[13]", 1, 6, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[13]", 1, 6, RAM_INPUT, 2)) + val.append(PinConstr("DOB[14]", 1, 7, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[14]", 0, 7, RAM_INPUT, 2)) + val.append(PinConstr("DOB[15]", 1, 7, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[15]", 1, 7, RAM_INPUT, 2)) + val.append(PinConstr("DOB[16]", 3, 6, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[16]", 2, 6, RAM_INPUT, 2)) + val.append(PinConstr("DOB[17]", 3, 6, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[17]", 3, 6, RAM_INPUT, 2)) + val.append(PinConstr("DOB[18]", 3, 7, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[18]", 2, 7, RAM_INPUT, 2)) + val.append(PinConstr("DOB[19]", 3, 7, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[19]", 3, 7, RAM_INPUT, 2)) + val.append(PinConstr("DOB[20]", 1, 8, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[20]", 0, 8, RAM_INPUT, 2)) + val.append(PinConstr("DOB[21]", 1, 8, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[21]", 1, 8, RAM_INPUT, 2)) + val.append(PinConstr("DOB[22]", 1, 9, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[22]", 0, 9, RAM_INPUT, 2)) + val.append(PinConstr("DOB[23]", 1, 9, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[23]", 1, 9, RAM_INPUT, 2)) + val.append(PinConstr("DOB[24]", 1, 10, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[24]", 0, 10, RAM_INPUT, 2)) + val.append(PinConstr("DOB[25]", 1, 10, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[25]", 1, 10, RAM_INPUT, 2)) + val.append(PinConstr("DOB[26]", 1, 11, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[26]", 0, 11, RAM_INPUT, 2)) + val.append(PinConstr("DOB[27]", 1, 11, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[27]", 1, 11, RAM_INPUT, 2)) + val.append(PinConstr("DOB[28]", 1, 12, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[28]", 0, 12, RAM_INPUT, 2)) + val.append(PinConstr("DOB[29]", 1, 12, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[29]", 1, 12, RAM_INPUT, 2)) + val.append(PinConstr("DOB[30]", 1, 13, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[30]", 0, 13, RAM_INPUT, 2)) + val.append(PinConstr("DOB[31]", 1, 13, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[31]", 1, 13, RAM_INPUT, 2)) + val.append(PinConstr("DOB[32]", 1, 14, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[32]", 0, 14, RAM_INPUT, 2)) + val.append(PinConstr("DOB[33]", 1, 14, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[33]", 1, 14, RAM_INPUT, 2)) + val.append(PinConstr("DOB[34]", 1, 15, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[34]", 0, 15, RAM_INPUT, 2)) + val.append(PinConstr("DOB[35]", 1, 15, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[35]", 1, 15, RAM_INPUT, 2)) + val.append(PinConstr("DOB[36]", 3, 14, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[36]", 2, 14, RAM_INPUT, 2)) + val.append(PinConstr("DOB[37]", 3, 14, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[37]", 3, 14, RAM_INPUT, 2)) + val.append(PinConstr("DOB[38]", 3, 15, RAM_INPUT, 1)) + val.append(PinConstr("DOBX[38]", 2, 15, RAM_INPUT, 2)) + val.append(PinConstr("DOB[39]", 3, 15, RAM_INPUT, 2)) +# val.append(PinConstr("DOBX[39]", 3, 15, RAM_INPUT, 2)) + val.append(PinConstr("CLOCKB[1]", 2, 10, RAM_INPUT, 2)) + val.append(PinConstr("CLOCKB[2]", 2, 11, RAM_INPUT, 2)) + val.append(PinConstr("CLOCKB[3]", 2, 12, RAM_INPUT, 2)) + val.append(PinConstr("CLOCKB[4]", 2, 13, RAM_INPUT, 2)) + val.append(PinConstr("ECC1B_ERRA[0]", -4, 0, RAM_INPUT, 1)) + val.append(PinConstr("ECC1B_ERRA[1]", -4, 8, RAM_INPUT, 1)) + val.append(PinConstr("ECC1B_ERRA[2]", 5, 0, RAM_INPUT, 1)) + val.append(PinConstr("ECC1B_ERRA[3]", 5, 8, RAM_INPUT, 1)) + val.append(PinConstr("ECC1B_ERRB[0]", -4, 1, RAM_INPUT, 1)) + val.append(PinConstr("ECC1B_ERRB[1]", -4, 9, RAM_INPUT, 1)) + val.append(PinConstr("ECC1B_ERRB[2]", 5, 1, RAM_INPUT, 1)) + val.append(PinConstr("ECC1B_ERRB[3]", 5, 9, RAM_INPUT, 1)) + val.append(PinConstr("ECC2B_ERRA[0]", -4, 0, RAM_INPUT, 2)) + val.append(PinConstr("ECC2B_ERRA[1]", -4, 8, RAM_INPUT, 2)) + val.append(PinConstr("ECC2B_ERRA[2]", 5, 0, RAM_INPUT, 2)) + val.append(PinConstr("ECC2B_ERRA[3]", 5, 8, RAM_INPUT, 2)) + val.append(PinConstr("ECC2B_ERRB[0]", -4, 1, RAM_INPUT, 2)) + val.append(PinConstr("ECC2B_ERRB[1]", -4, 9, RAM_INPUT, 2)) + val.append(PinConstr("ECC2B_ERRB[2]", 5, 1, RAM_INPUT, 2)) + val.append(PinConstr("ECC2B_ERRB[3]", 5, 9, RAM_INPUT, 2)) + val.append(PinConstr("F_FULL[0]", -4, 10, RAM_INPUT, 2)) + val.append(PinConstr("F_FULL[1]", -4, 12, RAM_INPUT, 2)) + val.append(PinConstr("F_EMPTY[0]", -4, 10, RAM_INPUT, 1)) + val.append(PinConstr("F_EMPTY[1]", -4, 13, RAM_INPUT, 2)) + val.append(PinConstr("F_AL_FULL[0]", -4, 11, RAM_INPUT, 2)) + val.append(PinConstr("F_AL_FULL[1]", -4, 12, RAM_INPUT, 1)) + val.append(PinConstr("F_AL_EMPTY[0]", -4, 11, RAM_INPUT, 1)) + val.append(PinConstr("F_AL_EMPTY[1]", -4, 13, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ERR[0]", -4, 4, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ERR[1]", -4, 5, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ERR[0]", -4, 4, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ERR[1]", -4, 5, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDR[0]", -6, 8, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDRX[0]", -5, 8, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDR[1]", -6, 8, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDRX[1]", -5, 8, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDR[2]", -6, 9, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDRX[2]", -5, 9, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDR[3]", -6, 9, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDRX[3]", -5, 9, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDR[4]", -6, 10, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDRX[4]", -5, 10, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDR[5]", -6, 10, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDRX[5]", -5, 10, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDR[6]", -6, 11, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDRX[6]", -5, 11, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDR[7]", -6, 11, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDRX[7]", -5, 11, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDR[8]", -6, 12, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDRX[8]", -5, 12, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDR[9]", -6, 12, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDRX[9]", -5, 12, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDR[10]", -6, 13, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDRX[10]", -5, 13, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDR[11]", -6, 13, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDRX[11]", -5, 13, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDR[12]", -6, 14, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDRX[12]", -5, 14, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDR[13]", -6, 14, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDRX[13]", -5, 14, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDR[14]", -6, 15, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDRX[14]", -5, 15, RAM_INPUT, 1)) + val.append(PinConstr("FWR_ADDR[15]", -6, 15, RAM_INPUT, 2)) + val.append(PinConstr("FWR_ADDRX[15]", -5, 15, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDR[0]", -6, 0, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDRX[0]", -5, 0, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDR[1]", -6, 0, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDRX[1]", -5, 0, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDR[2]", -6, 1, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDRX[2]", -5, 1, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDR[3]", -6, 1, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDRX[3]", -5, 1, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDR[4]", -6, 2, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDRX[4]", -5, 2, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDR[5]", -6, 2, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDRX[5]", -5, 2, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDR[6]", -6, 3, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDRX[6]", -5, 3, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDR[7]", -6, 3, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDRX[7]", -5, 3, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDR[8]", -6, 4, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDRX[8]", -5, 4, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDR[9]", -6, 4, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDRX[9]", -5, 4, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDR[10]", -6, 5, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDRX[10]", -5, 5, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDR[11]", -6, 5, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDRX[11]", -5, 5, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDR[12]", -6, 6, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDRX[12]", -5, 6, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDR[13]", -6, 6, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDRX[13]", -5, 6, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDR[14]", -6, 7, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDRX[14]", -5, 7, RAM_INPUT, 1)) + val.append(PinConstr("FRD_ADDR[15]", -6, 7, RAM_INPUT, 2)) + val.append(PinConstr("FRD_ADDRX[15]", -5, 7, RAM_INPUT, 2)) + elif prim_type=="SERDES": + val.append(PinConstr("TX_DETECT_RX_I", 6, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("PLL_RESET_I", 6, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_CLK_I", 6, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CLK_I", 6, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_CLK_I", 6, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_WE_I", 6, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_EN_I", 6, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_RESET_I", 6, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_PCS_RESET_I", 6, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_PMA_RESET_I", 6, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_PRBS_FORCE_ERR_I", 6, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_POLARITY_I", 6, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_8B10B_EN_I", 6, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_RESET_I", 7, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_PMA_RESET_I", 7, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_EQA_RESET_I", 7, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_CDR_RESET_I", 7, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_PCS_RESET_I", 7, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_BUF_RESET_I", 7, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_PRBS_CNT_RESET_I", 7, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_EN_EI_DETECTOR_I", 7, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_COMMA_DETECT_EN_I", 7, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_SLIDE_I", 7, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_POLARITY_I", 7, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_8B10B_EN_I", 7, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_MCOMMA_ALIGN_I", 7, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_PCOMMA_ALIGN_I", 7, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_NOT_IN_TABLE_O[7]", 8, 7, RAM_INPUT, 1)) + val.append(PinConstr("RX_NOT_IN_TABLE_O[6]", 8, 7, RAM_INPUT, 2)) + val.append(PinConstr("RX_NOT_IN_TABLE_O[5]", 9, 7, RAM_INPUT, 1)) + val.append(PinConstr("RX_NOT_IN_TABLE_O[4]", 9, 7, RAM_INPUT, 2)) + val.append(PinConstr("RX_NOT_IN_TABLE_O[3]", 10, 7, RAM_INPUT, 1)) + val.append(PinConstr("RX_NOT_IN_TABLE_O[2]", 10, 7, RAM_INPUT, 2)) + val.append(PinConstr("RX_NOT_IN_TABLE_O[1]", 11, 7, RAM_INPUT, 1)) + val.append(PinConstr("RX_NOT_IN_TABLE_O[0]", 11, 7, RAM_INPUT, 2)) + val.append(PinConstr("RX_CHAR_IS_COMMA_O[7]", 12, 7, RAM_INPUT, 1)) + val.append(PinConstr("RX_CHAR_IS_COMMA_O[6]", 12, 7, RAM_INPUT, 2)) + val.append(PinConstr("RX_CHAR_IS_COMMA_O[5]", 13, 7, RAM_INPUT, 1)) + val.append(PinConstr("RX_CHAR_IS_COMMA_O[4]", 13, 7, RAM_INPUT, 2)) + val.append(PinConstr("RX_CHAR_IS_COMMA_O[3]", 14, 7, RAM_INPUT, 1)) + val.append(PinConstr("RX_CHAR_IS_COMMA_O[2]", 14, 7, RAM_INPUT, 2)) + val.append(PinConstr("RX_CHAR_IS_COMMA_O[1]", 15, 7, RAM_INPUT, 1)) + val.append(PinConstr("RX_CHAR_IS_COMMA_O[0]", 15, 7, RAM_INPUT, 2)) + val.append(PinConstr("REGFILE_ADDR_I[7]", 8, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_ADDR_I[6]", 8, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_ADDR_I[5]", 9, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_ADDR_I[4]", 9, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_ADDR_I[3]", 10, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_ADDR_I[2]", 10, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_ADDR_I[1]", 11, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_ADDR_I[0]", 11, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_IS_K_I[7]", 12, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_IS_K_I[6]", 12, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_IS_K_I[5]", 13, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_IS_K_I[4]", 13, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_IS_K_I[3]", 14, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_IS_K_I[2]", 14, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_IS_K_I[1]", 15, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_IS_K_I[0]", 15, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_8B10B_BYPASS_I[7]", 8, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_8B10B_BYPASS_I[6]", 8, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_8B10B_BYPASS_I[5]", 9, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_8B10B_BYPASS_I[4]", 9, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_8B10B_BYPASS_I[3]", 10, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_8B10B_BYPASS_I[2]", 10, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_8B10B_BYPASS_I[1]", 11, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_8B10B_BYPASS_I[0]", 11, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_8B10B_BYPASS_I[7]", 12, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_8B10B_BYPASS_I[6]", 12, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_8B10B_BYPASS_I[5]", 13, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_8B10B_BYPASS_I[4]", 13, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_8B10B_BYPASS_I[3]", 14, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_8B10B_BYPASS_I[2]", 14, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_8B10B_BYPASS_I[1]", 15, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_8B10B_BYPASS_I[0]", 15, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_DISPMODE_I[7]", 8, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_DISPMODE_I[6]", 8, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_DISPMODE_I[5]", 9, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_DISPMODE_I[4]", 9, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_DISPMODE_I[3]", 10, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_DISPMODE_I[2]", 10, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_DISPMODE_I[1]", 11, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_DISPMODE_I[0]", 11, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_DISPVAL_I[7]", 12, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_DISPVAL_I[6]", 12, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_DISPVAL_I[5]", 13, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_DISPVAL_I[4]", 13, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_DISPVAL_I[3]", 14, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_DISPVAL_I[2]", 14, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_CHAR_DISPVAL_I[1]", 15, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_CHAR_DISPVAL_I[0]", 15, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[63]", 8, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[62]", 8, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[61]", 9, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[60]", 9, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[59]", 10, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[58]", 10, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[57]", 11, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[56]", 11, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[55]", 12, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[54]", 12, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[53]", 13, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[52]", 13, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[51]", 14, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[50]", 14, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[49]", 15, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[48]", 15, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[47]", 8, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[46]", 8, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[45]", 9, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[44]", 9, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[43]", 10, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[42]", 10, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[41]", 11, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[40]", 11, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[39]", 12, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[38]", 12, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[37]", 13, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[36]", 13, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[35]", 14, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[34]", 14, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[33]", 15, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[32]", 15, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[31]", 8, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[30]", 8, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[29]", 9, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[28]", 9, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[27]", 10, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[26]", 10, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[25]", 11, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[24]", 11, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[23]", 12, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[22]", 12, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[21]", 13, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[20]", 13, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[19]", 14, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[18]", 14, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[17]", 15, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[16]", 15, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[15]", 8, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[14]", 8, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[13]", 9, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[12]", 9, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[11]", 10, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[10]", 10, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[9]", 11, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[8]", 11, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[7]", 12, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[6]", 12, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[5]", 13, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[4]", 13, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[3]", 14, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[2]", 14, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_DATA_I[1]", 15, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_DATA_I[0]", 15, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_DO_O[15]", 16, 7, RAM_INPUT, 1)) + val.append(PinConstr("REGFILE_DO_O[14]", 16, 7, RAM_INPUT, 2)) + val.append(PinConstr("REGFILE_DO_O[13]", 17, 7, RAM_INPUT, 1)) + val.append(PinConstr("REGFILE_DO_O[12]", 17, 7, RAM_INPUT, 2)) + val.append(PinConstr("REGFILE_DO_O[11]", 18, 7, RAM_INPUT, 1)) + val.append(PinConstr("REGFILE_DO_O[10]", 18, 7, RAM_INPUT, 2)) + val.append(PinConstr("REGFILE_DO_O[9]", 19, 7, RAM_INPUT, 1)) + val.append(PinConstr("REGFILE_DO_O[8]", 19, 7, RAM_INPUT, 2)) + val.append(PinConstr("REGFILE_DO_O[7]", 20, 7, RAM_INPUT, 1)) + val.append(PinConstr("REGFILE_DO_O[6]", 20, 7, RAM_INPUT, 2)) + val.append(PinConstr("REGFILE_DO_O[5]", 21, 7, RAM_INPUT, 1)) + val.append(PinConstr("REGFILE_DO_O[4]", 21, 7, RAM_INPUT, 2)) + val.append(PinConstr("REGFILE_DO_O[3]", 22, 7, RAM_INPUT, 1)) + val.append(PinConstr("REGFILE_DO_O[2]", 22, 7, RAM_INPUT, 2)) + val.append(PinConstr("REGFILE_DO_O[1]", 23, 7, RAM_INPUT, 1)) + val.append(PinConstr("REGFILE_DO_O[0]", 23, 7, RAM_INPUT, 2)) + val.append(PinConstr("REGFILE_DI_I[15]", 16, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_DI_I[14]", 16, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_DI_I[13]", 17, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_DI_I[12]", 17, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_DI_I[11]", 18, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_DI_I[10]", 18, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_DI_I[9]", 19, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_DI_I[8]", 19, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_DI_I[7]", 20, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_DI_I[6]", 20, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_DI_I[5]", 21, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_DI_I[4]", 21, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_DI_I[3]", 22, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_DI_I[2]", 22, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_DI_I[1]", 23, 6, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_DI_I[0]", 23, 6, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_MASK_I[15]", 16, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_MASK_I[14]", 16, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_MASK_I[13]", 17, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_MASK_I[12]", 17, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_MASK_I[11]", 18, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_MASK_I[10]", 18, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_MASK_I[9]", 19, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_MASK_I[8]", 19, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_MASK_I[7]", 20, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_MASK_I[6]", 20, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_MASK_I[5]", 21, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_MASK_I[4]", 21, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_MASK_I[3]", 22, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_MASK_I[2]", 22, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("REGFILE_MASK_I[1]", 23, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("REGFILE_MASK_I[0]", 23, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_CHAR_IS_K_O[7]", 16, 4, RAM_INPUT, 1)) + val.append(PinConstr("RX_CHAR_IS_K_O[6]", 16, 4, RAM_INPUT, 2)) + val.append(PinConstr("RX_CHAR_IS_K_O[5]", 17, 4, RAM_INPUT, 1)) + val.append(PinConstr("RX_CHAR_IS_K_O[4]", 17, 4, RAM_INPUT, 2)) + val.append(PinConstr("RX_CHAR_IS_K_O[3]", 18, 4, RAM_INPUT, 1)) + val.append(PinConstr("RX_CHAR_IS_K_O[2]", 18, 4, RAM_INPUT, 2)) + val.append(PinConstr("RX_CHAR_IS_K_O[1]", 19, 4, RAM_INPUT, 1)) + val.append(PinConstr("RX_CHAR_IS_K_O[0]", 19, 4, RAM_INPUT, 2)) + val.append(PinConstr("RX_DISP_ERR_O[7]", 20, 4, RAM_INPUT, 1)) + val.append(PinConstr("RX_DISP_ERR_O[6]", 20, 4, RAM_INPUT, 2)) + val.append(PinConstr("RX_DISP_ERR_O[5]", 21, 4, RAM_INPUT, 1)) + val.append(PinConstr("RX_DISP_ERR_O[4]", 21, 4, RAM_INPUT, 2)) + val.append(PinConstr("RX_DISP_ERR_O[3]", 22, 4, RAM_INPUT, 1)) + val.append(PinConstr("RX_DISP_ERR_O[2]", 22, 4, RAM_INPUT, 2)) + val.append(PinConstr("RX_DISP_ERR_O[1]", 23, 4, RAM_INPUT, 1)) + val.append(PinConstr("RX_DISP_ERR_O[0]", 23, 4, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[63]", 16, 3, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[62]", 16, 3, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[61]", 17, 3, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[60]", 17, 3, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[59]", 18, 3, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[58]", 18, 3, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[57]", 19, 3, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[56]", 19, 3, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[55]", 20, 3, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[54]", 20, 3, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[53]", 21, 3, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[52]", 21, 3, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[51]", 22, 3, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[50]", 22, 3, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[49]", 23, 3, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[48]", 23, 3, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[47]", 16, 2, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[46]", 16, 2, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[45]", 17, 2, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[44]", 17, 2, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[43]", 18, 2, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[42]", 18, 2, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[41]", 19, 2, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[40]", 19, 2, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[39]", 20, 2, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[38]", 20, 2, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[37]", 21, 2, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[36]", 21, 2, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[35]", 22, 2, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[34]", 22, 2, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[33]", 23, 2, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[32]", 23, 2, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[31]", 16, 1, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[30]", 16, 1, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[29]", 17, 1, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[28]", 17, 1, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[27]", 18, 1, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[26]", 18, 1, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[25]", 19, 1, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[24]", 19, 1, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[23]", 20, 1, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[22]", 20, 1, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[21]", 21, 1, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[20]", 21, 1, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[19]", 22, 1, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[18]", 22, 1, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[17]", 23, 1, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[16]", 23, 1, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[15]", 16, 0, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[14]", 16, 0, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[13]", 17, 0, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[12]", 17, 0, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[11]", 18, 0, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[10]", 18, 0, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[9]", 19, 0, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[8]", 19, 0, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[7]", 20, 0, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[6]", 20, 0, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[5]", 21, 0, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[4]", 21, 0, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[3]", 22, 0, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[2]", 22, 0, RAM_INPUT, 2)) + val.append(PinConstr("RX_DATA_O[1]", 23, 0, RAM_INPUT, 1)) + val.append(PinConstr("RX_DATA_O[0]", 23, 0, RAM_INPUT, 2)) + val.append(PinConstr("TX_DETECT_RX_DONE_O", 24, 6, RAM_INPUT, 2)) + val.append(PinConstr("TX_DETECT_RX_PRESENT_O", 24, 6, RAM_INPUT, 1)) + val.append(PinConstr("RX_CLK_O", 24, 5, RAM_INPUT, 2)) + val.append(PinConstr("PLL_CLK_O", 24, 5, RAM_INPUT, 1)) + val.append(PinConstr("TX_BUF_ERR_O", 24, 4, RAM_INPUT, 2)) + val.append(PinConstr("TX_RESET_DONE_O", 24, 4, RAM_INPUT, 1)) + val.append(PinConstr("REGFILE_RDY_O", 24, 3, RAM_INPUT, 2)) + val.append(PinConstr("RX_PRBS_ERR_O", 24, 3, RAM_INPUT, 1)) + val.append(PinConstr("RX_BUF_ERR_O", 24, 2, RAM_INPUT, 2)) + val.append(PinConstr("RX_BYTE_IS_ALIGNED_O", 24, 2, RAM_INPUT, 1)) + val.append(PinConstr("RX_BYTE_REALIGN_O", 24, 1, RAM_INPUT, 2)) + val.append(PinConstr("RX_RESET_DONE_O", 24, 1, RAM_INPUT, 1)) + val.append(PinConstr("RX_EI_EN_O", 24, 0, RAM_INPUT, 2)) + val.append(PinConstr("LOOPBACK_I[2]", 25, 5, RAM_OUTPUT, 1)) + val.append(PinConstr("LOOPBACK_I[1]", 25, 5, RAM_OUTPUT, 2)) + val.append(PinConstr("LOOPBACK_I[0]", 25, 4, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_PRBS_SEL_I[2]", 25, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_PRBS_SEL_I[1]", 25, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_PRBS_SEL_I[0]", 25, 2, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_PRBS_SEL_I[2]", 25, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_PRBS_SEL_I[1]", 25, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("RX_PRBS_SEL_I[0]", 25, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("TX_POWER_DOWN_N_I", 25, 4, RAM_OUTPUT, 1)) + val.append(PinConstr("RX_POWER_DOWN_N_I", 25, 2, RAM_OUTPUT, 1)) + val.append(PinConstr("TX_ELEC_IDLE_I", 25, 0, RAM_OUTPUT, 1)) + elif prim_type=="GPIO": + if "LES" in type_name: + val.append(PinConstr("OUT4", 3, 1, RAM_OUTPUT, 2)) + val.append(PinConstr("OUT3", 3, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("OUT2", 3, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("OUT1", 3, 0, RAM_OUTPUT, 1)) + if "RES" in type_name: + val.append(PinConstr("OUT1", -3, 0, RAM_OUTPUT, 1)) + val.append(PinConstr("OUT2", -3, 0, RAM_OUTPUT, 2)) + val.append(PinConstr("OUT3", -3, 1, RAM_OUTPUT, 1)) + val.append(PinConstr("OUT4", -3, 1, RAM_OUTPUT, 2)) + if "TES" in type_name: + val.append(PinConstr("OUT1", 0, -3, RAM_OUTPUT, 1)) + val.append(PinConstr("OUT2", 0, -3, RAM_OUTPUT, 2)) + val.append(PinConstr("OUT3", 1, -3, RAM_OUTPUT, 1)) + val.append(PinConstr("OUT4", 1, -3, RAM_OUTPUT, 2)) + if "BES" in type_name: + val.append(PinConstr("OUT4", 1, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("OUT3", 1, 3, RAM_OUTPUT, 1)) + val.append(PinConstr("OUT2", 0, 3, RAM_OUTPUT, 2)) + val.append(PinConstr("OUT1", 0, 3, RAM_OUTPUT, 1)) + elif prim_type=="PLL": + pll_num = int(prim_name[3]) + + val.append(PinConstr("USR_CLK_REF", -PLL_X_POS+1, -PLL_Y_POS+124 - pll_num, RAM_OUTPUT, 1)) + val.append(PinConstr("USR_LOCKED_STDY_RST", -PLL_X_POS+1, -PLL_Y_POS+120 - pll_num, RAM_OUTPUT, 1)) + val.append(PinConstr("USR_SEL_A_B", -PLL_X_POS+1, -PLL_Y_POS+116 - pll_num, RAM_OUTPUT, 1)) + + val.append(PinConstr("USR_PLL_LOCKED", -PLL_X_POS+1, -PLL_Y_POS+128 - pll_num, RAM_INPUT, 2)) + val.append(PinConstr("USR_PLL_LOCKED_STDY", -PLL_X_POS+1, -PLL_Y_POS+124 - pll_num, RAM_INPUT, 2)) + + val.append(PinConstr("CLK0", -PLL_X_POS+39 + pll_num * 4, -PLL_Y_POS+128, RAM_INPUT, 1)) + val.append(PinConstr("CLK90", -PLL_X_POS+40 + pll_num * 4, -PLL_Y_POS+128, RAM_INPUT, 1)) + val.append(PinConstr("CLK180", -PLL_X_POS+41 + pll_num * 4, -PLL_Y_POS+128, RAM_INPUT, 1)) + val.append(PinConstr("CLK270", -PLL_X_POS+42 + pll_num * 4, -PLL_Y_POS+128, RAM_INPUT, 1)) + # not connected directly + val.append(PinConstr("CLK_FEEDBACK", -PLL_X_POS+1, -PLL_Y_POS+128 - pll_num, RAM_OUTPUT, 2, skip=True)) + elif prim_type=="BUFG": + bufg_num = int(prim_name[4]) + # not connected directly + val.append(PinConstr("I", -PLL_X_POS+1, -PLL_Y_POS+128 - bufg_num, RAM_OUTPUT, 1, skip=True)) + + return val + def get_pin_connection_name(prim, pin): if prim.type == "BUFG": if pin.dir == PinType.INPUT: @@ -2353,6 +3324,25 @@ class Die: self.create_conn(x_0+1, y_0, f"CPE.OUT{outputs[2]}", x,y, f"OM.P{plane}.D2") self.create_conn(x_0+1, y_0+1, f"CPE.OUT{outputs[3]}", x,y, f"OM.P{plane}.D3") + def get_pin_real_name(self, prim_name, pin): + prim_type = prim_name + num = 0 + if prim_name.startswith("PLL"): + num = int(prim_name[3]) + 4 + prim_type = "PLL" + prim = Primitive(prim_name, prim_type, num) + return get_pin_connection_name(prim, Pin(pin,PinType.INPUT,"",False)) + + def create_ram_io_conn(self, prim_name, prim_type, loc_x, loc_y): + for c in get_pins_constraint(get_tile_type(loc_x,loc_y),prim_name, prim_type): + if c.skip: + continue + name = self.get_pin_real_name(prim_name, c.name) + if c.output == RAM_OUTPUT: + self.create_conn(loc_x + c.rel_x, loc_y + c.rel_y, f"CPE.RAM_O{c.pin_num}", loc_x, loc_y, f"{name}") + else: + self.create_conn(loc_x, loc_y, f"{name}", loc_x + c.rel_x, loc_y + c.rel_y, f"CPE.RAM_I{c.pin_num}") + def create_io(self, x,y): cpe_x, cpe_y = gpio_x, gpio_y = sb_x, sb_y = x, y alt = False @@ -2400,12 +3390,8 @@ class Die: self.create_conn(gpio_x,gpio_y,"GPIO.IN1", x,y, "IOES.IO_IN1") self.create_conn(gpio_x,gpio_y,"GPIO.IN2", x,y, "IOES.IO_IN2") - if alt: - self.create_conn(cpe_x, cpe_y, "CPE.RAM_O1", gpio_x,gpio_y,"GPIO.OUT3") - self.create_conn(cpe_x, cpe_y, "CPE.RAM_O2", gpio_x,gpio_y,"GPIO.OUT4") - else: - self.create_conn(cpe_x, cpe_y, "CPE.RAM_O1", gpio_x,gpio_y,"GPIO.OUT1") - self.create_conn(cpe_x, cpe_y, "CPE.RAM_O2", gpio_x,gpio_y,"GPIO.OUT2") + if not alt: + self.create_ram_io_conn("GPIO", "GPIO", x, y) self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", gpio_x, gpio_y, "GPIO.CLOCK1") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", gpio_x, gpio_y, "GPIO.CLOCK2") self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", gpio_x, gpio_y, "GPIO.CLOCK3") @@ -2428,6 +3414,8 @@ class Die: loc = self.gpio_to_loc["GPIO_W2_A[5]"] self.create_conn(loc.x, loc.y, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK3") + # Next two groups are not directly connected to primitive inputs + # so we need to create connections manually self.create_conn(1, 128, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "GLBOUT.USR_GLB0") self.create_conn(1, 127, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "GLBOUT.USR_GLB1") self.create_conn(1, 126, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "GLBOUT.USR_GLB2") @@ -2438,51 +3426,10 @@ class Die: self.create_conn(1, 126, "CPE.RAM_O2", PLL_X_POS, PLL_Y_POS, "GLBOUT.USR_FB2") self.create_conn(1, 125, "CPE.RAM_O2", PLL_X_POS, PLL_Y_POS, "GLBOUT.USR_FB3") - self.create_conn(1, 124, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL0.USR_CLK_REF") - self.create_conn(1, 123, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL1.USR_CLK_REF") - self.create_conn(1, 122, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL2.USR_CLK_REF") - self.create_conn(1, 121, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL3.USR_CLK_REF") - - self.create_conn(1, 120, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL0.USR_LOCKED_STDY_RST") - self.create_conn(1, 119, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL1.USR_LOCKED_STDY_RST") - self.create_conn(1, 118, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL2.USR_LOCKED_STDY_RST") - self.create_conn(1, 117, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL3.USR_LOCKED_STDY_RST") - - self.create_conn(1, 116, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL0.USR_SEL_A_B") - self.create_conn(1, 115, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL1.USR_SEL_A_B") - self.create_conn(1, 114, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL2.USR_SEL_A_B") - self.create_conn(1, 113, "CPE.RAM_O1", PLL_X_POS, PLL_Y_POS, "PLL3.USR_SEL_A_B") - - self.create_conn(PLL_X_POS, PLL_Y_POS, "PLL0.USR_PLL_LOCKED", 1, 128, "CPE.RAM_I2") - self.create_conn(PLL_X_POS, PLL_Y_POS, "PLL1.USR_PLL_LOCKED", 1, 127, "CPE.RAM_I2") - self.create_conn(PLL_X_POS, PLL_Y_POS, "PLL2.USR_PLL_LOCKED", 1, 126, "CPE.RAM_I2") - self.create_conn(PLL_X_POS, PLL_Y_POS, "PLL3.USR_PLL_LOCKED", 1, 125, "CPE.RAM_I2") - - self.create_conn(PLL_X_POS, PLL_Y_POS, "PLL0.USR_PLL_LOCKED_STDY", 1, 124, "CPE.RAM_I2") - self.create_conn(PLL_X_POS, PLL_Y_POS, "PLL1.USR_PLL_LOCKED_STDY", 1, 123, "CPE.RAM_I2") - self.create_conn(PLL_X_POS, PLL_Y_POS, "PLL2.USR_PLL_LOCKED_STDY", 1, 122, "CPE.RAM_I2") - self.create_conn(PLL_X_POS, PLL_Y_POS, "PLL3.USR_PLL_LOCKED_STDY", 1, 121, "CPE.RAM_I2") - - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK0_0", 39, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK90_0", 40, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK180_0", 41, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK270_0", 42, 128, "CPE.RAM_I1") - - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK0_1", 43, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK90_1", 44, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK180_1", 45, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK270_1", 46, 128, "CPE.RAM_I1") - - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK0_2", 47, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK90_2", 48, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK180_2", 49, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK270_2", 50, 128, "CPE.RAM_I1") - - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK0_3", 51, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK90_3", 52, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK180_3", 53, 128, "CPE.RAM_I1") - self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.CLK270_3", 54, 128, "CPE.RAM_I1") - + self.create_ram_io_conn("PLL0", "PLL", PLL_X_POS, PLL_Y_POS) + self.create_ram_io_conn("PLL1", "PLL", PLL_X_POS, PLL_Y_POS) + self.create_ram_io_conn("PLL2", "PLL", PLL_X_POS, PLL_Y_POS) + self.create_ram_io_conn("PLL3", "PLL", PLL_X_POS, PLL_Y_POS) def global_mesh(self): def global_mesh_conn(x,y,inp): @@ -2616,22 +3563,8 @@ class Die: self.create_conn(x, y , f"CPE.RAM_O{out}", loc.x, loc.y, "GPIO.DDR") def misc_connections(self): - self.create_conn(1, 16, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.DATA[7]") - self.create_conn(1, 15, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.DATA[6]") - self.create_conn(1, 14, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.DATA[5]") - self.create_conn(1, 13, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.DATA[4]") - self.create_conn(1, 12, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.DATA[3]") - self.create_conn(1, 11, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.DATA[2]") - self.create_conn(1, 10, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.DATA[1]") - self.create_conn(1, 9, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.DATA[0]") - - self.create_conn(1, 6, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.CLK") - self.create_conn(1, 7, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.EN") - self.create_conn(1, 8, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.VALID") - - self.create_conn(1, 5, "CPE.RAM_O1", CTRL_X_POS, CTRL_Y_POS, "CFG_CTRL.RECFG") - - self.create_conn(CTRL_X_POS, CTRL_Y_POS ,"USR_RSTN.USR_RSTN", 1, 66, "CPE.RAM_I2") + self.create_ram_io_conn("CFG_CTRL", "CFG_CTRL", CTRL_X_POS, CTRL_Y_POS) + self.create_ram_io_conn("USR_RSTN", "USR_RSTN", CTRL_X_POS, CTRL_Y_POS) self.connect_ddr_i(97,128,1,'N1') self.connect_ddr_i(97,128,2,'N2') @@ -2644,905 +3577,10 @@ class Die: self.connect_ddr_i(49,1,1,'S3') def create_serdes(self, x, y): - self.create_conn(x+6,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_DETECT_RX_I") - self.create_conn(x+6,y+5,"CPE.RAM_O2", x,y,"SERDES.PLL_RESET_I") - self.create_conn(x+6,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_CLK_I") - self.create_conn(x+6,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CLK_I") - self.create_conn(x+6,y+4,"CPE.RAM_O1", x,y,"SERDES.RX_CLK_I") - self.create_conn(x+6,y+3,"CPE.RAM_O2", x,y,"SERDES.REGFILE_WE_I") - self.create_conn(x+6,y+3,"CPE.RAM_O1", x,y,"SERDES.REGFILE_EN_I") - self.create_conn(x+6,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_RESET_I") - self.create_conn(x+6,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_PCS_RESET_I") - self.create_conn(x+6,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_PMA_RESET_I") - self.create_conn(x+6,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_PRBS_FORCE_ERR_I") - self.create_conn(x+6,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_POLARITY_I") - self.create_conn(x+6,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_EN_I") - self.create_conn(x+7,y+6,"CPE.RAM_O2", x,y,"SERDES.RX_RESET_I") - self.create_conn(x+7,y+6,"CPE.RAM_O1", x,y,"SERDES.RX_PMA_RESET_I") - self.create_conn(x+7,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_EQA_RESET_I") - self.create_conn(x+7,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_CDR_RESET_I") - self.create_conn(x+7,y+4,"CPE.RAM_O2", x,y,"SERDES.RX_PCS_RESET_I") - self.create_conn(x+7,y+4,"CPE.RAM_O1", x,y,"SERDES.RX_BUF_RESET_I") - self.create_conn(x+7,y+3,"CPE.RAM_O2", x,y,"SERDES.RX_PRBS_CNT_RESET_I") - self.create_conn(x+7,y+3,"CPE.RAM_O1", x,y,"SERDES.RX_EN_EI_DETECTOR_I") - self.create_conn(x+7,y+2,"CPE.RAM_O2", x,y,"SERDES.RX_COMMA_DETECT_EN_I") - self.create_conn(x+7,y+2,"CPE.RAM_O1", x,y,"SERDES.RX_SLIDE_I") - self.create_conn(x+7,y+1,"CPE.RAM_O2", x,y,"SERDES.RX_POLARITY_I") - self.create_conn(x+7,y+1,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_EN_I") - self.create_conn(x+7,y+0,"CPE.RAM_O2", x,y,"SERDES.RX_MCOMMA_ALIGN_I") - self.create_conn(x+7,y+0,"CPE.RAM_O1", x,y,"SERDES.RX_PCOMMA_ALIGN_I") - self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[7]", x+8,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[6]", x+8,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[5]", x+9,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[4]", x+9,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[3]", x+10,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[2]", x+10,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[1]", x+11,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_NOT_IN_TABLE_O[0]", x+11,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[7]", x+12,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[6]", x+12,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[5]", x+13,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[4]", x+13,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[3]", x+14,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[2]", x+14,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[1]", x+15,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_COMMA_O[0]", x+15,y+7,"CPE.RAM_I2") - self.create_conn(x+8,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_ADDR_I[7]") - self.create_conn(x+8,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_ADDR_I[6]") - self.create_conn(x+9,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_ADDR_I[5]") - self.create_conn(x+9,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_ADDR_I[4]") - self.create_conn(x+10,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_ADDR_I[3]") - self.create_conn(x+10,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_ADDR_I[2]") - self.create_conn(x+11,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_ADDR_I[1]") - self.create_conn(x+11,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_ADDR_I[0]") - self.create_conn(x+12,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_IS_K_I[7]") - self.create_conn(x+12,y+6,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_IS_K_I[6]") - self.create_conn(x+13,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_IS_K_I[5]") - self.create_conn(x+13,y+6,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_IS_K_I[4]") - self.create_conn(x+14,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_IS_K_I[3]") - self.create_conn(x+14,y+6,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_IS_K_I[2]") - self.create_conn(x+15,y+6,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_IS_K_I[1]") - self.create_conn(x+15,y+6,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_IS_K_I[0]") - self.create_conn(x+8,y+5,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_BYPASS_I[7]") - self.create_conn(x+8,y+5,"CPE.RAM_O2", x,y,"SERDES.TX_8B10B_BYPASS_I[6]") - self.create_conn(x+9,y+5,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_BYPASS_I[5]") - self.create_conn(x+9,y+5,"CPE.RAM_O2", x,y,"SERDES.TX_8B10B_BYPASS_I[4]") - self.create_conn(x+10,y+5,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_BYPASS_I[3]") - self.create_conn(x+10,y+5,"CPE.RAM_O2", x,y,"SERDES.TX_8B10B_BYPASS_I[2]") - self.create_conn(x+11,y+5,"CPE.RAM_O1", x,y,"SERDES.TX_8B10B_BYPASS_I[1]") - self.create_conn(x+11,y+5,"CPE.RAM_O2", x,y,"SERDES.TX_8B10B_BYPASS_I[0]") - self.create_conn(x+12,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_BYPASS_I[7]") - self.create_conn(x+12,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_8B10B_BYPASS_I[6]") - self.create_conn(x+13,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_BYPASS_I[5]") - self.create_conn(x+13,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_8B10B_BYPASS_I[4]") - self.create_conn(x+14,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_BYPASS_I[3]") - self.create_conn(x+14,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_8B10B_BYPASS_I[2]") - self.create_conn(x+15,y+5,"CPE.RAM_O1", x,y,"SERDES.RX_8B10B_BYPASS_I[1]") - self.create_conn(x+15,y+5,"CPE.RAM_O2", x,y,"SERDES.RX_8B10B_BYPASS_I[0]") - self.create_conn(x+8,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPMODE_I[7]") - self.create_conn(x+8,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPMODE_I[6]") - self.create_conn(x+9,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPMODE_I[5]") - self.create_conn(x+9,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPMODE_I[4]") - self.create_conn(x+10,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPMODE_I[3]") - self.create_conn(x+10,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPMODE_I[2]") - self.create_conn(x+11,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPMODE_I[1]") - self.create_conn(x+11,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPMODE_I[0]") - self.create_conn(x+12,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPVAL_I[7]") - self.create_conn(x+12,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPVAL_I[6]") - self.create_conn(x+13,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPVAL_I[5]") - self.create_conn(x+13,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPVAL_I[4]") - self.create_conn(x+14,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPVAL_I[3]") - self.create_conn(x+14,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPVAL_I[2]") - self.create_conn(x+15,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_CHAR_DISPVAL_I[1]") - self.create_conn(x+15,y+4,"CPE.RAM_O2", x,y,"SERDES.TX_CHAR_DISPVAL_I[0]") - self.create_conn(x+8,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[63]") - self.create_conn(x+8,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[62]") - self.create_conn(x+9,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[61]") - self.create_conn(x+9,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[60]") - self.create_conn(x+10,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[59]") - self.create_conn(x+10,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[58]") - self.create_conn(x+11,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[57]") - self.create_conn(x+11,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[56]") - self.create_conn(x+12,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[55]") - self.create_conn(x+12,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[54]") - self.create_conn(x+13,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[53]") - self.create_conn(x+13,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[52]") - self.create_conn(x+14,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[51]") - self.create_conn(x+14,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[50]") - self.create_conn(x+15,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[49]") - self.create_conn(x+15,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[48]") - self.create_conn(x+8,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[47]") - self.create_conn(x+8,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[46]") - self.create_conn(x+9,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[45]") - self.create_conn(x+9,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[44]") - self.create_conn(x+10,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[43]") - self.create_conn(x+10,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[42]") - self.create_conn(x+11,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[41]") - self.create_conn(x+11,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[40]") - self.create_conn(x+12,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[39]") - self.create_conn(x+12,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[38]") - self.create_conn(x+13,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[37]") - self.create_conn(x+13,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[36]") - self.create_conn(x+14,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[35]") - self.create_conn(x+14,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[34]") - self.create_conn(x+15,y+2,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[33]") - self.create_conn(x+15,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[32]") - self.create_conn(x+8,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[31]") - self.create_conn(x+8,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[30]") - self.create_conn(x+9,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[29]") - self.create_conn(x+9,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[28]") - self.create_conn(x+10,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[27]") - self.create_conn(x+10,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[26]") - self.create_conn(x+11,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[25]") - self.create_conn(x+11,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[24]") - self.create_conn(x+12,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[23]") - self.create_conn(x+12,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[22]") - self.create_conn(x+13,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[21]") - self.create_conn(x+13,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[20]") - self.create_conn(x+14,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[19]") - self.create_conn(x+14,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[18]") - self.create_conn(x+15,y+1,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[17]") - self.create_conn(x+15,y+1,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[16]") - self.create_conn(x+8,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[15]") - self.create_conn(x+8,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[14]") - self.create_conn(x+9,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[13]") - self.create_conn(x+9,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[12]") - self.create_conn(x+10,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[11]") - self.create_conn(x+10,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[10]") - self.create_conn(x+11,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[9]") - self.create_conn(x+11,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[8]") - self.create_conn(x+12,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[7]") - self.create_conn(x+12,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[6]") - self.create_conn(x+13,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[5]") - self.create_conn(x+13,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[4]") - self.create_conn(x+14,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[3]") - self.create_conn(x+14,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[2]") - self.create_conn(x+15,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_DATA_I[1]") - self.create_conn(x+15,y+0,"CPE.RAM_O2", x,y,"SERDES.TX_DATA_I[0]") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[15]", x+16,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[14]", x+16,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[13]", x+17,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[12]", x+17,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[11]", x+18,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[10]", x+18,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[9]", x+19,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[8]", x+19,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[7]", x+20,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[6]", x+20,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[5]", x+21,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[4]", x+21,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[3]", x+22,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[2]", x+22,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[1]", x+23,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.REGFILE_DO_O[0]", x+23,y+7,"CPE.RAM_I2") - self.create_conn(x+16,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[15]") - self.create_conn(x+16,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[14]") - self.create_conn(x+17,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[13]") - self.create_conn(x+17,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[12]") - self.create_conn(x+18,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[11]") - self.create_conn(x+18,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[10]") - self.create_conn(x+19,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[9]") - self.create_conn(x+19,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[8]") - self.create_conn(x+20,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[7]") - self.create_conn(x+20,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[6]") - self.create_conn(x+21,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[5]") - self.create_conn(x+21,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[4]") - self.create_conn(x+22,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[3]") - self.create_conn(x+22,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[2]") - self.create_conn(x+23,y+6,"CPE.RAM_O1", x,y,"SERDES.REGFILE_DI_I[1]") - self.create_conn(x+23,y+6,"CPE.RAM_O2", x,y,"SERDES.REGFILE_DI_I[0]") - self.create_conn(x+16,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[15]") - self.create_conn(x+16,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[14]") - self.create_conn(x+17,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[13]") - self.create_conn(x+17,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[12]") - self.create_conn(x+18,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[11]") - self.create_conn(x+18,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[10]") - self.create_conn(x+19,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[9]") - self.create_conn(x+19,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[8]") - self.create_conn(x+20,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[7]") - self.create_conn(x+20,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[6]") - self.create_conn(x+21,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[5]") - self.create_conn(x+21,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[4]") - self.create_conn(x+22,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[3]") - self.create_conn(x+22,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[2]") - self.create_conn(x+23,y+5,"CPE.RAM_O1", x,y,"SERDES.REGFILE_MASK_I[1]") - self.create_conn(x+23,y+5,"CPE.RAM_O2", x,y,"SERDES.REGFILE_MASK_I[0]") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[7]", x+16,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[6]", x+16,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[5]", x+17,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[4]", x+17,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[3]", x+18,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[2]", x+18,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[1]", x+19,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_CHAR_IS_K_O[0]", x+19,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[7]", x+20,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[6]", x+20,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[5]", x+21,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[4]", x+21,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[3]", x+22,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[2]", x+22,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[1]", x+23,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DISP_ERR_O[0]", x+23,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[63]", x+16,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[62]", x+16,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[61]", x+17,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[60]", x+17,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[59]", x+18,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[58]", x+18,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[57]", x+19,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[56]", x+19,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[55]", x+20,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[54]", x+20,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[53]", x+21,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[52]", x+21,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[51]", x+22,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[50]", x+22,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[49]", x+23,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[48]", x+23,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[47]", x+16,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[46]", x+16,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[45]", x+17,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[44]", x+17,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[43]", x+18,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[42]", x+18,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[41]", x+19,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[40]", x+19,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[39]", x+20,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[38]", x+20,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[37]", x+21,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[36]", x+21,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[35]", x+22,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[34]", x+22,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[33]", x+23,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[32]", x+23,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[31]", x+16,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[30]", x+16,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[29]", x+17,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[28]", x+17,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[27]", x+18,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[26]", x+18,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[25]", x+19,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[24]", x+19,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[23]", x+20,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[22]", x+20,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[21]", x+21,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[20]", x+21,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[19]", x+22,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[18]", x+22,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[17]", x+23,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[16]", x+23,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[15]", x+16,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[14]", x+16,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[13]", x+17,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[12]", x+17,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[11]", x+18,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[10]", x+18,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[9]", x+19,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[8]", x+19,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[7]", x+20,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[6]", x+20,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[5]", x+21,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[4]", x+21,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[3]", x+22,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[2]", x+22,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_DATA_O[1]", x+23,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_DATA_O[0]", x+23,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.TX_DETECT_RX_DONE_O", x+24,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.TX_DETECT_RX_PRESENT_O", x+24,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_CLK_O", x+24,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.PLL_CLK_O", x+24,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.TX_BUF_ERR_O", x+24,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.TX_RESET_DONE_O", x+24,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.REGFILE_RDY_O", x+24,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_PRBS_ERR_O", x+24,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_BUF_ERR_O", x+24,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_BYTE_IS_ALIGNED_O", x+24,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_BYTE_REALIGN_O", x+24,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"SERDES.RX_RESET_DONE_O", x+24,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"SERDES.RX_EI_EN_O", x+24,y+0,"CPE.RAM_I2") - self.create_conn(x+25,y+5,"CPE.RAM_O1", x,y,"SERDES.LOOPBACK_I[2]") - self.create_conn(x+25,y+5,"CPE.RAM_O2", x,y,"SERDES.LOOPBACK_I[1]") - self.create_conn(x+25,y+4,"CPE.RAM_O2", x,y,"SERDES.LOOPBACK_I[0]") - self.create_conn(x+25,y+3,"CPE.RAM_O1", x,y,"SERDES.TX_PRBS_SEL_I[2]") - self.create_conn(x+25,y+3,"CPE.RAM_O2", x,y,"SERDES.TX_PRBS_SEL_I[1]") - self.create_conn(x+25,y+2,"CPE.RAM_O2", x,y,"SERDES.TX_PRBS_SEL_I[0]") - self.create_conn(x+25,y+1,"CPE.RAM_O1", x,y,"SERDES.RX_PRBS_SEL_I[2]") - self.create_conn(x+25,y+1,"CPE.RAM_O2", x,y,"SERDES.RX_PRBS_SEL_I[1]") - self.create_conn(x+25,y+0,"CPE.RAM_O2", x,y,"SERDES.RX_PRBS_SEL_I[0]") - self.create_conn(x+25,y+4,"CPE.RAM_O1", x,y,"SERDES.TX_POWER_DOWN_N_I") - self.create_conn(x+25,y+2,"CPE.RAM_O1", x,y,"SERDES.RX_POWER_DOWN_N_I") - self.create_conn(x+25,y+0,"CPE.RAM_O1", x,y,"SERDES.TX_ELEC_IDLE_I") + self.create_ram_io_conn("SERDES", "SERDES", x, y) def create_ram(self, x, y): - self.create_conn(x-3,y+2,"CPE.RAM_O1", x,y,"RAM.C_ADDRA[0]") - self.create_conn(x-3,y+2,"CPE.RAM_O2", x,y,"RAM.C_ADDRA[1]") - self.create_conn(x-3,y+3,"CPE.RAM_O1", x,y,"RAM.C_ADDRA[2]") - self.create_conn(x-3,y+3,"CPE.RAM_O2", x,y,"RAM.C_ADDRA[3]") - self.create_conn(x-3,y+4,"CPE.RAM_O1", x,y,"RAM.C_ADDRA[4]") - self.create_conn(x-3,y+4,"CPE.RAM_O2", x,y,"RAM.C_ADDRA[5]") - self.create_conn(x-3,y+5,"CPE.RAM_O1", x,y,"RAM.C_ADDRA[6]") - self.create_conn(x-3,y+5,"CPE.RAM_O2", x,y,"RAM.C_ADDRA[7]") - self.create_conn(x+2,y+2,"CPE.RAM_O1", x,y,"RAM.C_ADDRB[0]") - self.create_conn(x+2,y+2,"CPE.RAM_O2", x,y,"RAM.C_ADDRB[1]") - self.create_conn(x+2,y+3,"CPE.RAM_O1", x,y,"RAM.C_ADDRB[2]") - self.create_conn(x+2,y+3,"CPE.RAM_O2", x,y,"RAM.C_ADDRB[3]") - self.create_conn(x+2,y+4,"CPE.RAM_O1", x,y,"RAM.C_ADDRB[4]") - self.create_conn(x+2,y+4,"CPE.RAM_O2", x,y,"RAM.C_ADDRB[5]") - self.create_conn(x+2,y+5,"CPE.RAM_O1", x,y,"RAM.C_ADDRB[6]") - self.create_conn(x+2,y+5,"CPE.RAM_O2", x,y,"RAM.C_ADDRB[7]") - self.create_conn(x-6,y+0,"CPE.RAM_O1", x,y,"RAM.CLKA[0]") - self.create_conn(x-3,y+0,"CPE.RAM_O1", x,y,"RAM.CLKA[1]") - self.create_conn(x-6,y+1,"CPE.RAM_O1", x,y,"RAM.ENA[0]") - self.create_conn(x-3,y+1,"CPE.RAM_O1", x,y,"RAM.ENA[1]") - self.create_conn(x-6,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEA[0]") - self.create_conn(x-3,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEA[1]") - self.create_conn(x-5,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0[0]") - self.create_conn(x-5,y+0,"CPE.RAM_O2", x,y,"RAM.ADDRA0[1]") - self.create_conn(x-5,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0[2]") - self.create_conn(x-5,y+1,"CPE.RAM_O2", x,y,"RAM.ADDRA0[3]") - self.create_conn(x-5,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0[4]") - self.create_conn(x-5,y+2,"CPE.RAM_O2", x,y,"RAM.ADDRA0[5]") - self.create_conn(x-5,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0[6]") - self.create_conn(x-5,y+3,"CPE.RAM_O2", x,y,"RAM.ADDRA0[7]") - self.create_conn(x-5,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0[8]") - self.create_conn(x-5,y+4,"CPE.RAM_O2", x,y,"RAM.ADDRA0[9]") - self.create_conn(x-5,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0[10]") - self.create_conn(x-5,y+5,"CPE.RAM_O2", x,y,"RAM.ADDRA0[11]") - self.create_conn(x-5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0[12]") - self.create_conn(x-5,y+6,"CPE.RAM_O2", x,y,"RAM.ADDRA0[13]") - self.create_conn(x-5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0[14]") - self.create_conn(x-5,y+7,"CPE.RAM_O2", x,y,"RAM.ADDRA0[15]") - self.create_conn(x-5,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[0]") - self.create_conn(x-4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[1]") - self.create_conn(x-5,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[2]") - self.create_conn(x-4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[3]") - self.create_conn(x-5,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[4]") - self.create_conn(x-4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[5]") - self.create_conn(x-5,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[6]") - self.create_conn(x-4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[7]") - self.create_conn(x-5,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[8]") - self.create_conn(x-4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[9]") - self.create_conn(x-5,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[10]") - self.create_conn(x-4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[11]") - self.create_conn(x-6,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[12]") - self.create_conn(x-5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[13]") - self.create_conn(x-6,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[14]") - self.create_conn(x-5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRA0X[15]") - self.create_conn(x-1,y+0,"CPE.RAM_O1", x,y,"RAM.DIA[0]") - self.create_conn(x-1,y+0,"CPE.RAM_O2", x,y,"RAM.DIA[1]") - self.create_conn(x-1,y+1,"CPE.RAM_O1", x,y,"RAM.DIA[2]") - self.create_conn(x-1,y+1,"CPE.RAM_O2", x,y,"RAM.DIA[3]") - self.create_conn(x-1,y+2,"CPE.RAM_O1", x,y,"RAM.DIA[4]") - self.create_conn(x-1,y+2,"CPE.RAM_O2", x,y,"RAM.DIA[5]") - self.create_conn(x-1,y+3,"CPE.RAM_O1", x,y,"RAM.DIA[6]") - self.create_conn(x-1,y+3,"CPE.RAM_O2", x,y,"RAM.DIA[7]") - self.create_conn(x-1,y+4,"CPE.RAM_O1", x,y,"RAM.DIA[8]") - self.create_conn(x-1,y+4,"CPE.RAM_O2", x,y,"RAM.DIA[9]") - self.create_conn(x-1,y+5,"CPE.RAM_O1", x,y,"RAM.DIA[10]") - self.create_conn(x-1,y+5,"CPE.RAM_O2", x,y,"RAM.DIA[11]") - self.create_conn(x-1,y+6,"CPE.RAM_O1", x,y,"RAM.DIA[12]") - self.create_conn(x-1,y+6,"CPE.RAM_O2", x,y,"RAM.DIA[13]") - self.create_conn(x-1,y+7,"CPE.RAM_O1", x,y,"RAM.DIA[14]") - self.create_conn(x-1,y+7,"CPE.RAM_O2", x,y,"RAM.DIA[15]") - self.create_conn(x-3,y+6,"CPE.RAM_O1", x,y,"RAM.DIA[16]") - self.create_conn(x-3,y+6,"CPE.RAM_O2", x,y,"RAM.DIA[17]") - self.create_conn(x-3,y+7,"CPE.RAM_O1", x,y,"RAM.DIA[18]") - self.create_conn(x-3,y+7,"CPE.RAM_O2", x,y,"RAM.DIA[19]") - self.create_conn(x-2,y+0,"CPE.RAM_O1", x,y,"RAM.WEA[0]") - self.create_conn(x-2,y+0,"CPE.RAM_O2", x,y,"RAM.WEA[1]") - self.create_conn(x-2,y+1,"CPE.RAM_O1", x,y,"RAM.WEA[2]") - self.create_conn(x-2,y+1,"CPE.RAM_O2", x,y,"RAM.WEA[3]") - self.create_conn(x-2,y+2,"CPE.RAM_O1", x,y,"RAM.WEA[4]") - self.create_conn(x-2,y+2,"CPE.RAM_O2", x,y,"RAM.WEA[5]") - self.create_conn(x-2,y+3,"CPE.RAM_O1", x,y,"RAM.WEA[6]") - self.create_conn(x-2,y+3,"CPE.RAM_O2", x,y,"RAM.WEA[7]") - self.create_conn(x-2,y+4,"CPE.RAM_O1", x,y,"RAM.WEA[8]") - self.create_conn(x-2,y+4,"CPE.RAM_O2", x,y,"RAM.WEA[9]") - self.create_conn(x-2,y+5,"CPE.RAM_O1", x,y,"RAM.WEA[10]") - self.create_conn(x-2,y+5,"CPE.RAM_O2", x,y,"RAM.WEA[11]") - self.create_conn(x-2,y+6,"CPE.RAM_O1", x,y,"RAM.WEA[12]") - self.create_conn(x-2,y+6,"CPE.RAM_O2", x,y,"RAM.WEA[13]") - self.create_conn(x-2,y+7,"CPE.RAM_O1", x,y,"RAM.WEA[14]") - self.create_conn(x-2,y+7,"CPE.RAM_O2", x,y,"RAM.WEA[15]") - self.create_conn(x-4,y+6,"CPE.RAM_O1", x,y,"RAM.WEA[16]") - self.create_conn(x-4,y+6,"CPE.RAM_O2", x,y,"RAM.WEA[17]") - self.create_conn(x-4,y+7,"CPE.RAM_O1", x,y,"RAM.WEA[18]") - self.create_conn(x-4,y+7,"CPE.RAM_O2", x,y,"RAM.WEA[19]") - self.create_conn(x-6,y+8,"CPE.RAM_O1", x,y,"RAM.CLKA[2]") - self.create_conn(x-3,y+8,"CPE.RAM_O1", x,y,"RAM.CLKA[3]") - self.create_conn(x-6,y+9,"CPE.RAM_O1", x,y,"RAM.ENA[2]") - self.create_conn(x-3,y+9,"CPE.RAM_O1", x,y,"RAM.ENA[3]") - self.create_conn(x-6,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEA[2]") - self.create_conn(x-3,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEA[3]") - self.create_conn(x-5,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1[0]") - self.create_conn(x-5,y+8,"CPE.RAM_O2", x,y,"RAM.ADDRA1[1]") - self.create_conn(x-5,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1[2]") - self.create_conn(x-5,y+9,"CPE.RAM_O2", x,y,"RAM.ADDRA1[3]") - self.create_conn(x-5,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1[4]") - self.create_conn(x-5,y+10,"CPE.RAM_O2", x,y,"RAM.ADDRA1[5]") - self.create_conn(x-5,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1[6]") - self.create_conn(x-5,y+11,"CPE.RAM_O2", x,y,"RAM.ADDRA1[7]") - self.create_conn(x-5,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1[8]") - self.create_conn(x-5,y+12,"CPE.RAM_O2", x,y,"RAM.ADDRA1[9]") - self.create_conn(x-5,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1[10]") - self.create_conn(x-5,y+13,"CPE.RAM_O2", x,y,"RAM.ADDRA1[11]") - self.create_conn(x-5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1[12]") - self.create_conn(x-5,y+14,"CPE.RAM_O2", x,y,"RAM.ADDRA1[13]") - self.create_conn(x-5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1[14]") - self.create_conn(x-5,y+15,"CPE.RAM_O2", x,y,"RAM.ADDRA1[15]") - self.create_conn(x-5,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[0]") - self.create_conn(x-4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[1]") - self.create_conn(x-5,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[2]") - self.create_conn(x-4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[3]") - self.create_conn(x-5,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[4]") - self.create_conn(x-4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[5]") - self.create_conn(x-5,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[6]") - self.create_conn(x-4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[7]") - self.create_conn(x-5,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[8]") - self.create_conn(x-4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[9]") - self.create_conn(x-5,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[10]") - self.create_conn(x-4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[11]") - self.create_conn(x-6,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[12]") - self.create_conn(x-5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[13]") - self.create_conn(x-6,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[14]") - self.create_conn(x-5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRA1X[15]") - self.create_conn(x-1,y+8,"CPE.RAM_O1", x,y,"RAM.DIA[20]") - self.create_conn(x-1,y+8,"CPE.RAM_O2", x,y,"RAM.DIA[21]") - self.create_conn(x-1,y+9,"CPE.RAM_O1", x,y,"RAM.DIA[22]") - self.create_conn(x-1,y+9,"CPE.RAM_O2", x,y,"RAM.DIA[23]") - self.create_conn(x-1,y+10,"CPE.RAM_O1", x,y,"RAM.DIA[24]") - self.create_conn(x-1,y+10,"CPE.RAM_O2", x,y,"RAM.DIA[25]") - self.create_conn(x-1,y+11,"CPE.RAM_O1", x,y,"RAM.DIA[26]") - self.create_conn(x-1,y+11,"CPE.RAM_O2", x,y,"RAM.DIA[27]") - self.create_conn(x-1,y+12,"CPE.RAM_O1", x,y,"RAM.DIA[28]") - self.create_conn(x-1,y+12,"CPE.RAM_O2", x,y,"RAM.DIA[29]") - self.create_conn(x-1,y+13,"CPE.RAM_O1", x,y,"RAM.DIA[30]") - self.create_conn(x-1,y+13,"CPE.RAM_O2", x,y,"RAM.DIA[31]") - self.create_conn(x-1,y+14,"CPE.RAM_O1", x,y,"RAM.DIA[32]") - self.create_conn(x-1,y+14,"CPE.RAM_O2", x,y,"RAM.DIA[33]") - self.create_conn(x-1,y+15,"CPE.RAM_O1", x,y,"RAM.DIA[34]") - self.create_conn(x-1,y+15,"CPE.RAM_O2", x,y,"RAM.DIA[35]") - self.create_conn(x-3,y+14,"CPE.RAM_O1", x,y,"RAM.DIA[36]") - self.create_conn(x-3,y+14,"CPE.RAM_O2", x,y,"RAM.DIA[37]") - self.create_conn(x-3,y+15,"CPE.RAM_O1", x,y,"RAM.DIA[38]") - self.create_conn(x-3,y+15,"CPE.RAM_O2", x,y,"RAM.DIA[39]") - self.create_conn(x-2,y+8,"CPE.RAM_O1", x,y,"RAM.WEA[20]") - self.create_conn(x-2,y+8,"CPE.RAM_O2", x,y,"RAM.WEA[21]") - self.create_conn(x-2,y+9,"CPE.RAM_O1", x,y,"RAM.WEA[22]") - self.create_conn(x-2,y+9,"CPE.RAM_O2", x,y,"RAM.WEA[23]") - self.create_conn(x-2,y+10,"CPE.RAM_O1", x,y,"RAM.WEA[24]") - self.create_conn(x-2,y+10,"CPE.RAM_O2", x,y,"RAM.WEA[25]") - self.create_conn(x-2,y+11,"CPE.RAM_O1", x,y,"RAM.WEA[26]") - self.create_conn(x-2,y+11,"CPE.RAM_O2", x,y,"RAM.WEA[27]") - self.create_conn(x-2,y+12,"CPE.RAM_O1", x,y,"RAM.WEA[28]") - self.create_conn(x-2,y+12,"CPE.RAM_O2", x,y,"RAM.WEA[29]") - self.create_conn(x-2,y+13,"CPE.RAM_O1", x,y,"RAM.WEA[30]") - self.create_conn(x-2,y+13,"CPE.RAM_O2", x,y,"RAM.WEA[31]") - self.create_conn(x-2,y+14,"CPE.RAM_O1", x,y,"RAM.WEA[32]") - self.create_conn(x-2,y+14,"CPE.RAM_O2", x,y,"RAM.WEA[33]") - self.create_conn(x-2,y+15,"CPE.RAM_O1", x,y,"RAM.WEA[34]") - self.create_conn(x-2,y+15,"CPE.RAM_O2", x,y,"RAM.WEA[35]") - self.create_conn(x-4,y+14,"CPE.RAM_O1", x,y,"RAM.WEA[36]") - self.create_conn(x-4,y+14,"CPE.RAM_O2", x,y,"RAM.WEA[37]") - self.create_conn(x-4,y+15,"CPE.RAM_O1", x,y,"RAM.WEA[38]") - self.create_conn(x-4,y+15,"CPE.RAM_O2", x,y,"RAM.WEA[39]") - self.create_conn(x+2,y+0,"CPE.RAM_O1", x,y,"RAM.CLKB[0]") - self.create_conn(x+5,y+0,"CPE.RAM_O1", x,y,"RAM.CLKB[1]") - self.create_conn(x+2,y+1,"CPE.RAM_O1", x,y,"RAM.ENB[0]") - self.create_conn(x+5,y+1,"CPE.RAM_O1", x,y,"RAM.ENB[1]") - self.create_conn(x+2,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEB[0]") - self.create_conn(x+5,y+0,"CPE.RAM_O2", x,y,"RAM.GLWEB[1]") - self.create_conn(x+4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0[0]") - self.create_conn(x+4,y+0,"CPE.RAM_O2", x,y,"RAM.ADDRB0[1]") - self.create_conn(x+4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0[2]") - self.create_conn(x+4,y+1,"CPE.RAM_O2", x,y,"RAM.ADDRB0[3]") - self.create_conn(x+4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0[4]") - self.create_conn(x+4,y+2,"CPE.RAM_O2", x,y,"RAM.ADDRB0[5]") - self.create_conn(x+4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0[6]") - self.create_conn(x+4,y+3,"CPE.RAM_O2", x,y,"RAM.ADDRB0[7]") - self.create_conn(x+4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0[8]") - self.create_conn(x+4,y+4,"CPE.RAM_O2", x,y,"RAM.ADDRB0[9]") - self.create_conn(x+4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0[10]") - self.create_conn(x+4,y+5,"CPE.RAM_O2", x,y,"RAM.ADDRB0[11]") - self.create_conn(x+4,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0[12]") - self.create_conn(x+4,y+6,"CPE.RAM_O2", x,y,"RAM.ADDRB0[13]") - self.create_conn(x+4,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0[14]") - self.create_conn(x+4,y+7,"CPE.RAM_O2", x,y,"RAM.ADDRB0[15]") - self.create_conn(x+3,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[0]") - self.create_conn(x+4,y+0,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[1]") - self.create_conn(x+3,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[2]") - self.create_conn(x+4,y+1,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[3]") - self.create_conn(x+3,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[4]") - self.create_conn(x+4,y+2,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[5]") - self.create_conn(x+3,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[6]") - self.create_conn(x+4,y+3,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[7]") - self.create_conn(x+3,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[8]") - self.create_conn(x+4,y+4,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[9]") - self.create_conn(x+3,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[10]") - self.create_conn(x+4,y+5,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[11]") - self.create_conn(x+4,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[12]") - self.create_conn(x+5,y+6,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[13]") - self.create_conn(x+4,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[14]") - self.create_conn(x+5,y+7,"CPE.RAM_O1", x,y,"RAM.ADDRB0X[15]") - self.create_conn(x+1,y+0,"CPE.RAM_O1", x,y,"RAM.DIB[0]") - self.create_conn(x+1,y+0,"CPE.RAM_O2", x,y,"RAM.DIB[1]") - self.create_conn(x+1,y+1,"CPE.RAM_O1", x,y,"RAM.DIB[2]") - self.create_conn(x+1,y+1,"CPE.RAM_O2", x,y,"RAM.DIB[3]") - self.create_conn(x+1,y+2,"CPE.RAM_O1", x,y,"RAM.DIB[4]") - self.create_conn(x+1,y+2,"CPE.RAM_O2", x,y,"RAM.DIB[5]") - self.create_conn(x+1,y+3,"CPE.RAM_O1", x,y,"RAM.DIB[6]") - self.create_conn(x+1,y+3,"CPE.RAM_O2", x,y,"RAM.DIB[7]") - self.create_conn(x+1,y+4,"CPE.RAM_O1", x,y,"RAM.DIB[8]") - self.create_conn(x+1,y+4,"CPE.RAM_O2", x,y,"RAM.DIB[9]") - self.create_conn(x+1,y+5,"CPE.RAM_O1", x,y,"RAM.DIB[10]") - self.create_conn(x+1,y+5,"CPE.RAM_O2", x,y,"RAM.DIB[11]") - self.create_conn(x+1,y+6,"CPE.RAM_O1", x,y,"RAM.DIB[12]") - self.create_conn(x+1,y+6,"CPE.RAM_O2", x,y,"RAM.DIB[13]") - self.create_conn(x+1,y+7,"CPE.RAM_O1", x,y,"RAM.DIB[14]") - self.create_conn(x+1,y+7,"CPE.RAM_O2", x,y,"RAM.DIB[15]") - self.create_conn(x+3,y+6,"CPE.RAM_O1", x,y,"RAM.DIB[16]") - self.create_conn(x+3,y+6,"CPE.RAM_O2", x,y,"RAM.DIB[17]") - self.create_conn(x+3,y+7,"CPE.RAM_O1", x,y,"RAM.DIB[18]") - self.create_conn(x+3,y+7,"CPE.RAM_O2", x,y,"RAM.DIB[19]") - self.create_conn(x+0,y+0,"CPE.RAM_O1", x,y,"RAM.WEB[0]") - self.create_conn(x+0,y+0,"CPE.RAM_O2", x,y,"RAM.WEB[1]") - self.create_conn(x+0,y+1,"CPE.RAM_O1", x,y,"RAM.WEB[2]") - self.create_conn(x+0,y+1,"CPE.RAM_O2", x,y,"RAM.WEB[3]") - self.create_conn(x+0,y+2,"CPE.RAM_O1", x,y,"RAM.WEB[4]") - self.create_conn(x+0,y+2,"CPE.RAM_O2", x,y,"RAM.WEB[5]") - self.create_conn(x+0,y+3,"CPE.RAM_O1", x,y,"RAM.WEB[6]") - self.create_conn(x+0,y+3,"CPE.RAM_O2", x,y,"RAM.WEB[7]") - self.create_conn(x+0,y+4,"CPE.RAM_O1", x,y,"RAM.WEB[8]") - self.create_conn(x+0,y+4,"CPE.RAM_O2", x,y,"RAM.WEB[9]") - self.create_conn(x+0,y+5,"CPE.RAM_O1", x,y,"RAM.WEB[10]") - self.create_conn(x+0,y+5,"CPE.RAM_O2", x,y,"RAM.WEB[11]") - self.create_conn(x+0,y+6,"CPE.RAM_O1", x,y,"RAM.WEB[12]") - self.create_conn(x+0,y+6,"CPE.RAM_O2", x,y,"RAM.WEB[13]") - self.create_conn(x+0,y+7,"CPE.RAM_O1", x,y,"RAM.WEB[14]") - self.create_conn(x+0,y+7,"CPE.RAM_O2", x,y,"RAM.WEB[15]") - self.create_conn(x+2,y+6,"CPE.RAM_O1", x,y,"RAM.WEB[16]") - self.create_conn(x+2,y+6,"CPE.RAM_O2", x,y,"RAM.WEB[17]") - self.create_conn(x+2,y+7,"CPE.RAM_O1", x,y,"RAM.WEB[18]") - self.create_conn(x+2,y+7,"CPE.RAM_O2", x,y,"RAM.WEB[19]") - self.create_conn(x+2,y+8,"CPE.RAM_O1", x,y,"RAM.CLKB[2]") - self.create_conn(x+5,y+8,"CPE.RAM_O1", x,y,"RAM.CLKB[3]") - self.create_conn(x+2,y+9,"CPE.RAM_O1", x,y,"RAM.ENB[2]") - self.create_conn(x+5,y+9,"CPE.RAM_O1", x,y,"RAM.ENB[3]") - self.create_conn(x+2,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEB[2]") - self.create_conn(x+5,y+8,"CPE.RAM_O2", x,y,"RAM.GLWEB[3]") - self.create_conn(x+4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1[0]") - self.create_conn(x+4,y+8,"CPE.RAM_O2", x,y,"RAM.ADDRB1[1]") - self.create_conn(x+4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1[2]") - self.create_conn(x+4,y+9,"CPE.RAM_O2", x,y,"RAM.ADDRB1[3]") - self.create_conn(x+4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1[4]") - self.create_conn(x+4,y+10,"CPE.RAM_O2", x,y,"RAM.ADDRB1[5]") - self.create_conn(x+4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1[6]") - self.create_conn(x+4,y+11,"CPE.RAM_O2", x,y,"RAM.ADDRB1[7]") - self.create_conn(x+4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1[8]") - self.create_conn(x+4,y+12,"CPE.RAM_O2", x,y,"RAM.ADDRB1[9]") - self.create_conn(x+4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1[10]") - self.create_conn(x+4,y+13,"CPE.RAM_O2", x,y,"RAM.ADDRB1[11]") - self.create_conn(x+4,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1[12]") - self.create_conn(x+4,y+14,"CPE.RAM_O2", x,y,"RAM.ADDRB1[13]") - self.create_conn(x+4,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1[14]") - self.create_conn(x+4,y+15,"CPE.RAM_O2", x,y,"RAM.ADDRB1[15]") - self.create_conn(x+3,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[0]") - self.create_conn(x+4,y+8,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[1]") - self.create_conn(x+3,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[2]") - self.create_conn(x+4,y+9,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[3]") - self.create_conn(x+3,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[4]") - self.create_conn(x+4,y+10,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[5]") - self.create_conn(x+3,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[6]") - self.create_conn(x+4,y+11,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[7]") - self.create_conn(x+3,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[8]") - self.create_conn(x+4,y+12,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[9]") - self.create_conn(x+3,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[10]") - self.create_conn(x+4,y+13,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[11]") - self.create_conn(x+4,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[12]") - self.create_conn(x+5,y+14,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[13]") - self.create_conn(x+4,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[14]") - self.create_conn(x+5,y+15,"CPE.RAM_O1", x,y,"RAM.ADDRB1X[15]") - self.create_conn(x+1,y+8,"CPE.RAM_O1", x,y,"RAM.DIB[20]") - self.create_conn(x+1,y+8,"CPE.RAM_O2", x,y,"RAM.DIB[21]") - self.create_conn(x+1,y+9,"CPE.RAM_O1", x,y,"RAM.DIB[22]") - self.create_conn(x+1,y+9,"CPE.RAM_O2", x,y,"RAM.DIB[23]") - self.create_conn(x+1,y+10,"CPE.RAM_O1", x,y,"RAM.DIB[24]") - self.create_conn(x+1,y+10,"CPE.RAM_O2", x,y,"RAM.DIB[25]") - self.create_conn(x+1,y+11,"CPE.RAM_O1", x,y,"RAM.DIB[26]") - self.create_conn(x+1,y+11,"CPE.RAM_O2", x,y,"RAM.DIB[27]") - self.create_conn(x+1,y+12,"CPE.RAM_O1", x,y,"RAM.DIB[28]") - self.create_conn(x+1,y+12,"CPE.RAM_O2", x,y,"RAM.DIB[29]") - self.create_conn(x+1,y+13,"CPE.RAM_O1", x,y,"RAM.DIB[30]") - self.create_conn(x+1,y+13,"CPE.RAM_O2", x,y,"RAM.DIB[31]") - self.create_conn(x+1,y+14,"CPE.RAM_O1", x,y,"RAM.DIB[32]") - self.create_conn(x+1,y+14,"CPE.RAM_O2", x,y,"RAM.DIB[33]") - self.create_conn(x+1,y+15,"CPE.RAM_O1", x,y,"RAM.DIB[34]") - self.create_conn(x+1,y+15,"CPE.RAM_O2", x,y,"RAM.DIB[35]") - self.create_conn(x+3,y+14,"CPE.RAM_O1", x,y,"RAM.DIB[36]") - self.create_conn(x+3,y+14,"CPE.RAM_O2", x,y,"RAM.DIB[37]") - self.create_conn(x+3,y+15,"CPE.RAM_O1", x,y,"RAM.DIB[38]") - self.create_conn(x+3,y+15,"CPE.RAM_O2", x,y,"RAM.DIB[39]") - self.create_conn(x+0,y+8,"CPE.RAM_O1", x,y,"RAM.WEB[20]") - self.create_conn(x+0,y+8,"CPE.RAM_O2", x,y,"RAM.WEB[21]") - self.create_conn(x+0,y+9,"CPE.RAM_O1", x,y,"RAM.WEB[22]") - self.create_conn(x+0,y+9,"CPE.RAM_O2", x,y,"RAM.WEB[23]") - self.create_conn(x+0,y+10,"CPE.RAM_O1", x,y,"RAM.WEB[24]") - self.create_conn(x+0,y+10,"CPE.RAM_O2", x,y,"RAM.WEB[25]") - self.create_conn(x+0,y+11,"CPE.RAM_O1", x,y,"RAM.WEB[26]") - self.create_conn(x+0,y+11,"CPE.RAM_O2", x,y,"RAM.WEB[27]") - self.create_conn(x+0,y+12,"CPE.RAM_O1", x,y,"RAM.WEB[28]") - self.create_conn(x+0,y+12,"CPE.RAM_O2", x,y,"RAM.WEB[29]") - self.create_conn(x+0,y+13,"CPE.RAM_O1", x,y,"RAM.WEB[30]") - self.create_conn(x+0,y+13,"CPE.RAM_O2", x,y,"RAM.WEB[31]") - self.create_conn(x+0,y+14,"CPE.RAM_O1", x,y,"RAM.WEB[32]") - self.create_conn(x+0,y+14,"CPE.RAM_O2", x,y,"RAM.WEB[33]") - self.create_conn(x+0,y+15,"CPE.RAM_O1", x,y,"RAM.WEB[34]") - self.create_conn(x+0,y+15,"CPE.RAM_O2", x,y,"RAM.WEB[35]") - self.create_conn(x+2,y+14,"CPE.RAM_O1", x,y,"RAM.WEB[36]") - self.create_conn(x+2,y+14,"CPE.RAM_O2", x,y,"RAM.WEB[37]") - self.create_conn(x+2,y+15,"CPE.RAM_O1", x,y,"RAM.WEB[38]") - self.create_conn(x+2,y+15,"CPE.RAM_O2", x,y,"RAM.WEB[39]") - self.create_conn(x-6,y+2,"CPE.RAM_O2", x,y,"RAM.F_RSTN") - self.create_conn(x,y,"RAM.DOA[0]", x-1,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[0]", x-2,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[1]", x-1,y+0,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[1]", x-1,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[2]", x-1,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[2]", x-2,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[3]", x-1,y+1,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[3]", x-1,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[4]", x-1,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[4]", x-2,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[5]", x-1,y+2,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[5]", x-1,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[6]", x-1,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[6]", x-2,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[7]", x-1,y+3,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[7]", x-1,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[8]", x-1,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[8]", x-2,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[9]", x-1,y+4,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[9]", x-1,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[10]", x-1,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[10]", x-2,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[11]", x-1,y+5,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[11]", x-1,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[12]", x-1,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[12]", x-2,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[13]", x-1,y+6,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[13]", x-1,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[14]", x-1,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[14]", x-2,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[15]", x-1,y+7,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[15]", x-1,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[16]", x-3,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[16]", x-4,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[17]", x-3,y+6,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[17]", x-3,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[18]", x-3,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[18]", x-4,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[19]", x-3,y+7,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[19]", x-3,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[20]", x-1,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[20]", x-2,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[21]", x-1,y+8,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[21]", x-1,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[22]", x-1,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[22]", x-2,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[23]", x-1,y+9,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[23]", x-1,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[24]", x-1,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[24]", x-2,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[25]", x-1,y+10,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[25]", x-1,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[26]", x-1,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[26]", x-2,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[27]", x-1,y+11,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[27]", x-1,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[28]", x-1,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[28]", x-2,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[29]", x-1,y+12,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[29]", x-1,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[30]", x-1,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[30]", x-2,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[31]", x-1,y+13,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[31]", x-1,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[32]", x-1,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[32]", x-2,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[33]", x-1,y+14,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[33]", x-1,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[34]", x-1,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[34]", x-2,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[35]", x-1,y+15,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[35]", x-1,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[36]", x-3,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[36]", x-4,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[37]", x-3,y+14,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[37]", x-3,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[38]", x-3,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOAX[38]", x-4,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOA[39]", x-3,y+15,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOAX[39]", x-3,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKA[1]", x-3,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.CLOCKA[2]", x-3,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.CLOCKA[3]", x-3,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.CLOCKA[4]", x-3,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOB[0]", x+1,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[0]", x+0,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[1]", x+1,y+0,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[1]", x+1,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[2]", x+1,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[2]", x+0,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[3]", x+1,y+1,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[3]", x+1,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[4]", x+1,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[4]", x+0,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[5]", x+1,y+2,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[5]", x+1,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[6]", x+1,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[6]", x+0,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[7]", x+1,y+3,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[7]", x+1,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[8]", x+1,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[8]", x+0,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[9]", x+1,y+4,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[9]", x+1,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[10]", x+1,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[10]", x+0,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[11]", x+1,y+5,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[11]", x+1,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[12]", x+1,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[12]", x+0,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[13]", x+1,y+6,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[13]", x+1,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[14]", x+1,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[14]", x+0,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[15]", x+1,y+7,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[15]", x+1,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[16]", x+3,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[16]", x+2,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[17]", x+3,y+6,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[17]", x+3,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[18]", x+3,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[18]", x+2,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[19]", x+3,y+7,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[19]", x+3,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[20]", x+1,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[20]", x+0,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[21]", x+1,y+8,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[21]", x+1,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[22]", x+1,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[22]", x+0,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[23]", x+1,y+9,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[23]", x+1,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[24]", x+1,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[24]", x+0,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[25]", x+1,y+10,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[25]", x+1,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[26]", x+1,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[26]", x+0,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[27]", x+1,y+11,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[27]", x+1,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[28]", x+1,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[28]", x+0,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[29]", x+1,y+12,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[29]", x+1,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[30]", x+1,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[30]", x+0,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[31]", x+1,y+13,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[31]", x+1,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[32]", x+1,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[32]", x+0,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[33]", x+1,y+14,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[33]", x+1,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[34]", x+1,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[34]", x+0,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[35]", x+1,y+15,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[35]", x+1,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[36]", x+3,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[36]", x+2,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[37]", x+3,y+14,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[37]", x+3,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[38]", x+3,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.DOBX[38]", x+2,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.DOB[39]", x+3,y+15,"CPE.RAM_I2") -# self.create_conn(x,y,"RAM.DOBX[39]", x+3,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKB[1]", x+2,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKB[2]", x+2,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKB[3]", x+2,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.CLOCKB[4]", x+2,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC1B_ERRA[0]", x-4,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRA[1]", x-4,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRA[2]", x+5,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRA[3]", x+5,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRB[0]", x-4,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRB[1]", x-4,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRB[2]", x+5,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC1B_ERRB[3]", x+5,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.ECC2B_ERRA[0]", x-4,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRA[1]", x-4,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRA[2]", x+5,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRA[3]", x+5,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRB[0]", x-4,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRB[1]", x-4,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRB[2]", x+5,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.ECC2B_ERRB[3]", x+5,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_FULL[0]", x-4,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_FULL[1]", x-4,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_EMPTY[0]", x-4,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.F_EMPTY[1]", x-4,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_AL_FULL[0]", x-4,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.F_AL_FULL[1]", x-4,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.F_AL_EMPTY[0]", x-4,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.F_AL_EMPTY[1]", x-4,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ERR[0]", x-4,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ERR[1]", x-4,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ERR[0]", x-4,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ERR[1]", x-4,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR[0]", x-6,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX[0]", x-5,y+8,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR[1]", x-6,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX[1]", x-5,y+8,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR[2]", x-6,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX[2]", x-5,y+9,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR[3]", x-6,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX[3]", x-5,y+9,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR[4]", x-6,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX[4]", x-5,y+10,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR[5]", x-6,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX[5]", x-5,y+10,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR[6]", x-6,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX[6]", x-5,y+11,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR[7]", x-6,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX[7]", x-5,y+11,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR[8]", x-6,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX[8]", x-5,y+12,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR[9]", x-6,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX[9]", x-5,y+12,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR[10]", x-6,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX[10]", x-5,y+13,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR[11]", x-6,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX[11]", x-5,y+13,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR[12]", x-6,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX[12]", x-5,y+14,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR[13]", x-6,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX[13]", x-5,y+14,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDR[14]", x-6,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDRX[14]", x-5,y+15,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FWR_ADDR[15]", x-6,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FWR_ADDRX[15]", x-5,y+15,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR[0]", x-6,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX[0]", x-5,y+0,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR[1]", x-6,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX[1]", x-5,y+0,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR[2]", x-6,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX[2]", x-5,y+1,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR[3]", x-6,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX[3]", x-5,y+1,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR[4]", x-6,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX[4]", x-5,y+2,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR[5]", x-6,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX[5]", x-5,y+2,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR[6]", x-6,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX[6]", x-5,y+3,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR[7]", x-6,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX[7]", x-5,y+3,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR[8]", x-6,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX[8]", x-5,y+4,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR[9]", x-6,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX[9]", x-5,y+4,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR[10]", x-6,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX[10]", x-5,y+5,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR[11]", x-6,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX[11]", x-5,y+5,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR[12]", x-6,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX[12]", x-5,y+6,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR[13]", x-6,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX[13]", x-5,y+6,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDR[14]", x-6,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDRX[14]", x-5,y+7,"CPE.RAM_I1") - self.create_conn(x,y,"RAM.FRD_ADDR[15]", x-6,y+7,"CPE.RAM_I2") - self.create_conn(x,y,"RAM.FRD_ADDRX[15]", x-5,y+7,"CPE.RAM_I2") + self.create_ram_io_conn("RAM", "RAM", x, y) if is_ram(x,y-16): self.create_conn(x,y,"RAM.FORW_CAS_WRAO", x,y-16,"RAM.FORW_CAS_WRAI") self.create_conn(x,y,"RAM.FORW_CAS_WRBO", x,y-16,"RAM.FORW_CAS_WRBI")