diff --git a/libgm/include/Die.hpp b/libgm/include/Die.hpp index c751638..5c0705b 100644 --- a/libgm/include/Die.hpp +++ b/libgm/include/Die.hpp @@ -38,7 +38,11 @@ class Die static constexpr int LATCH_BLOCK_SIZE = 112; static constexpr int RAM_BLOCK_SIZE = 27; static constexpr int MEMORY_SIZE = 5120; - static constexpr int PLL_CONFIG_SIZE = 12 * 8 + 4 + 8; + static constexpr int MAX_PLL = 4; + static constexpr int PLL_CFG_SIZE = 12; + static constexpr int CLKIN_CFG_SIZE = 4; + static constexpr int GLBOUT_CFG_SIZE = 8; + static constexpr int PLL_CONFIG_SIZE = PLL_CFG_SIZE * MAX_PLL * 2 + CLKIN_CFG_SIZE + GLBOUT_CFG_SIZE; public: explicit Die(); @@ -53,6 +57,8 @@ class Die bool is_ram_empty(int x, int y) const; bool is_ram_data_empty(int x, int y) const; bool is_pll_cfg_empty(int index) const; + bool is_clkin_cfg_empty() const; + bool is_glbout_cfg_empty() const; void write_latch(int x, int y, const std::vector &data); void write_ram(int x, int y, const std::vector &data); diff --git a/libgm/src/Bitstream.cpp b/libgm/src/Bitstream.cpp index 0fb660b..2007538 100644 --- a/libgm/src/Bitstream.cpp +++ b/libgm/src/Bitstream.cpp @@ -324,12 +324,13 @@ class BitstreamReadWriter write_nops(6); } - void write_cmd_pll(int index, std::vector data) + void write_cmd_pll(int index, std::vector data, int size) { - write_header(CMD_PLL, 24); - for (int i = 0; i < 12; i++) - write_byte(data[i + index * 12]); - for (int i = 12 * 8; i < 12 * 8 + 12; i++) + write_header(CMD_PLL, size); + for (int i = 0; i < Die::PLL_CFG_SIZE; i++) + write_byte(data[i + index * Die::PLL_CFG_SIZE]); + int pos = Die::PLL_CFG_SIZE * Die::MAX_PLL * 2; + for (int i = pos; i < pos + size - Die::PLL_CFG_SIZE; i++) write_byte(data[i]); insert_crc16(); write_nops(6); @@ -592,15 +593,20 @@ Bitstream Bitstream::serialise_chip(const Chip &chip) auto &die = chip.get_die(0); std::vector pll_data = die.get_pll_config(); bool pll_written = false; - for (int i = 0; i < 4; i++) { + for (int i = 0; i < Die::MAX_PLL; i++) { bool cfg_a = !die.is_pll_cfg_empty(i * 2 + 0); bool cfg_b = !die.is_pll_cfg_empty(i * 2 + 1); + int size = Die::PLL_CFG_SIZE; + if (!die.is_clkin_cfg_empty()) + size = Die::PLL_CFG_SIZE + Die::CLKIN_CFG_SIZE; + if (!die.is_glbout_cfg_empty()) + size = Die::PLL_CFG_SIZE + Die::CLKIN_CFG_SIZE + Die::GLBOUT_CFG_SIZE; if (cfg_a || cfg_b) { wr.write_cmd_spll(1 << i); - wr.write_cmd_pll(i * 2, pll_data); + wr.write_cmd_pll(i * 2, pll_data, size); if (cfg_b) { wr.write_cmd_spll(1 << i | 1 << (i + 4)); - wr.write_cmd_pll(i * 2, pll_data); + wr.write_cmd_pll(i * 2, pll_data, size); } pll_written = true; } diff --git a/libgm/src/Die.cpp b/libgm/src/Die.cpp index 2761072..390fff2 100644 --- a/libgm/src/Die.cpp +++ b/libgm/src/Die.cpp @@ -48,8 +48,26 @@ bool Die::is_ram_data_empty(int x, int y) const { return ram_data.at(std::make_p bool Die::is_pll_cfg_empty(int index) const { - int pos = index * 12; - for (int i = 0; i < 12; i++) + int pos = index * PLL_CFG_SIZE; + for (int i = 0; i < PLL_CFG_SIZE; i++) + if (pll_cfg[i + pos] != 0x00) + return false; + return true; +} + +bool Die::is_clkin_cfg_empty() const +{ + int pos = PLL_CFG_SIZE * MAX_PLL * 2; + for (int i = 0; i < CLKIN_CFG_SIZE; i++) + if (pll_cfg[i + pos] != 0x00) + return false; + return true; +} + +bool Die::is_glbout_cfg_empty() const +{ + int pos = PLL_CFG_SIZE * MAX_PLL * 2 + CLKIN_CFG_SIZE; + for (int i = 0; i < GLBOUT_CFG_SIZE; i++) if (pll_cfg[i + pos] != 0x00) return false; return true; @@ -84,18 +102,18 @@ void Die::write_ram_data(int x, int y, const std::vector &data, uint16_ void Die::write_pll_select(uint8_t select, const std::vector &data) { - for (int i = 0; i < 4; i++) { + for (int i = 0; i < MAX_PLL; i++) { if (select & (1 << i)) { - int pos = i * 2 * 12; + int pos = i * 2 * PLL_CFG_SIZE; if (select & (1 << (i + 4))) { - pos += 12; + pos += PLL_CFG_SIZE; } - for (size_t j = 0; j < 12; j++) + for (size_t j = 0; j < PLL_CFG_SIZE; j++) pll_cfg[pos++] = data[j]; } } - int pos = 8 * 12; // start after PLL data; - for (size_t j = 12; j < data.size(); j++) + int pos = PLL_CFG_SIZE * MAX_PLL * 2; // start after PLL data; + for (size_t j = PLL_CFG_SIZE; j < data.size(); j++) pll_cfg[pos++] = data[j]; }