diff --git a/doc/boards.yml b/doc/boards.yml
index 4ed2440..64513f4 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -202,6 +202,13 @@
   Memory: OK
   Flash: OK
 
+- ID: c5g
+  Description: Terasic C5G (Cyclone V GX Starter Kit)
+  URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=830
+  FPGA: Cyclone V GX 5CGXFC5C6F27C7N
+  Memory: OK
+  Flash: NT
+
 - ID: de0
   Description: Terasic DE0
   URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=364
diff --git a/src/board.hpp b/src/board.hpp
index ab278e1..a2ab6a2 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -119,6 +119,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("alinx_ax516",     "xc6slx16csg324", "",         0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("axu2cga",         "xczu2cg",        "",         0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("basys3",          "xc7a35tcpg236",  "digilent", 0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("c5g",             "", "usb-blaster",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("cmod_s7",         "xc7s25csga225",  "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("cmoda7_35t",      "xc7a35tcpg236",  "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("nexys_a7_50",     "xc7a50tcsg324",  "digilent", 0, 0, CABLE_DEFAULT),
diff --git a/src/part.hpp b/src/part.hpp
index 94032a2..06765f4 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -87,13 +87,20 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x020f30dd, {"altera", "cyclone 10 LP", "10CL025", 10}},
 	{0x020f50dd, {"altera", "cyclone 10 LP", "10CL055", 10}},
 
-	{0x02b140dd, {"altera", "cyclone V", "5CEBA9", 10}},
-	{0x02b150dd, {"altera", "cyclone V", "5CEA2", 10}},
-	{0x02b050dd, {"altera", "cyclone V", "5CEBA4", 10}},
-	{0x02b220dd, {"altera", "cyclone V", "5CEFA5", 10}},
-	{0x02d020dd, {"altera", "cyclone V Soc", "5CSEBA6", 10}},
-	{0x02d010dd, {"altera", "cyclone V Soc", "5CSEMA4", 10}},
-	{0x02d120dd, {"altera", "cyclone V Soc", "5CSEMA5", 10}},
+	{0x02b010dd, {"altera", "cyclone V", "5CGX*3", 10}},
+	{0x02b020dd, {"altera", "cyclone V", "5CGT*5/5CGX*5", 10}},
+	{0x02b030dd, {"altera", "cyclone V", "5CGT*7/5CGX*7", 10}},
+	{0x02b040dd, {"altera", "cyclone V", "5CGT*9/5CGX*9", 10}},
+	{0x02b050dd, {"altera", "cyclone V", "5CE*A4", 10}},
+	{0x02b120dd, {"altera", "cyclone V", "5CGX*4", 10}},
+	{0x02b130dd, {"altera", "cyclone V", "5CE*A7", 10}},
+	{0x02b140dd, {"altera", "cyclone V", "5CE*A9", 10}},
+	{0x02b150dd, {"altera", "cyclone V", "5CE*A2", 10}},
+	{0x02b220dd, {"altera", "cyclone V", "5CE*A5", 10}},
+	{0x02d010dd, {"altera", "cyclone V Soc", "5CSE*A4/5CSX*4", 10}},
+	{0x02d020dd, {"altera", "cyclone V Soc", "5CSE*A6/5CSX*6", 10}},
+	{0x02d110dd, {"altera", "cyclone V Soc", "5CSE*A2/5CSX*2", 10}},
+	{0x02d120dd, {"altera", "cyclone V Soc", "5CSE*A5/5CST*5/5CSX*5", 10}},
 
 	{0x031820dd, {"altera", "MAX 10",    "10M08SAU169C8G", 10}},
 	{0x031050dd, {"altera", "MAX 10",    "10M50DAF484", 10}},