From 951db00617b0b23b98b163fcf236dd51110eed25 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 22 May 2025 10:37:04 +0800 Subject: [PATCH 1/2] anlogicCable: Fix wrong ANLOGICCABLE_VIDv1 ANLOGICCABLE_VIDv1 should keep the old ANLOGICCABLE_VID to compatible with the original device. Fixes: 4b008a0 ("anlogicCable: refresh with new VID") Signed-off-by: Junhui Liu --- src/anlogicCable.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/anlogicCable.cpp b/src/anlogicCable.cpp index 3a84883..3107dfe 100644 --- a/src/anlogicCable.cpp +++ b/src/anlogicCable.cpp @@ -17,7 +17,7 @@ using namespace std; -#define ANLOGICCABLE_VIDv1 0x336C +#define ANLOGICCABLE_VIDv1 0x0547 #define ANLOGICCABLE_VIDv2 0x336C #define ANLOGICCABLE_PID 0x1002 From 5fefbb39afe2d6c2ba0ffda5f25096b33eb84c33 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 22 May 2025 11:01:44 +0800 Subject: [PATCH 2/2] Add support for MILIANKE-S200-EG4D20 and update document Add board definition and FPGA part ID for the MILIANKE S200 EG4D20 development board. Also update related documentation and outdated URL. Tested ok by loading bitstream to SRAM and FLASH. Signed-off-by: Junhui Liu --- doc/FPGAs.yml | 8 +++++--- doc/boards.yml | 7 +++++++ src/board.hpp | 1 + src/part.hpp | 1 + 4 files changed, 14 insertions(+), 3 deletions(-) diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml index b89391a..e05597e 100644 --- a/doc/FPGAs.yml +++ b/doc/FPGAs.yml @@ -1,14 +1,16 @@ Anlogic: - Description: EG4 - Model: S20 - URL: http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3 + Model: + - EG4D20 + - EG4S20 + URL: https://www.anlogic.com/en/product/fpga/saleagle/eg4 Memory: OK Flash: AS - Description: SALELF 2 Model: EF2M45 - URL: http://www.anlogic.com/prod_view.aspx?TypeId=12&Id=170&FId=t3:12:3 + URL: https://www.anlogic.com/en/product/fpga/salelf/salelf2 Memory: OK Flash: OK diff --git a/doc/boards.yml b/doc/boards.yml index c37bea7..9bdda30 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -552,6 +552,13 @@ Memory: OK Flash: OK +- ID: mlk-s200-eg4d20 + Description: MILIANKE S200 EG4D20 Development Board + URL: https://www.milianke.com/product-item-108.html + FPGA: eagle s20 EG4D20EG176 + Memory: OK + Flash: OK + - ID: mini_itx Description: Avnet Mini-ITX Base Kit URL: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/mini-itx/ diff --git a/src/board.hpp b/src/board.hpp index 72695f2..be05ea7 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -193,6 +193,7 @@ static std::map board_list = { JTAG_BOARD("machXO2EVN", "", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("machXO3SK", "", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("machXO3EVN", "", "ft2232", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("mlk-s200-eg4d20", "", "anlogicCable", 0, 0, CABLE_DEFAULT), JTAG_BOARD("mimas_a7", "xc7a50tfgg484", "numato", 0, 0, CABLE_MHZ(30)), JTAG_BOARD("neso_a7", "xc7a100tcsg324", "numato-neso", 0, 0, CABLE_MHZ(30)), JTAG_BOARD("minispartan6", "", "ft2232", 0, 0, CABLE_DEFAULT), diff --git a/src/part.hpp b/src/part.hpp index 2f7df5d..04852cb 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -24,6 +24,7 @@ static std::map fpga_list = { /**************************************************************************/ /* Anlogic Eagle */ + {0x04014c35, {"anlogic", "eagle d20", "EG4D20EG176", 8}}, {0x0a014c35, {"anlogic", "eagle s20", "EG4S20BG256", 8}}, /* Anlogic Elf2 */