diff --git a/doc/compatibility/fpga.rst b/doc/compatibility/fpga.rst
index 03725b1..d9c3a5c 100644
--- a/doc/compatibility/fpga.rst
+++ b/doc/compatibility/fpga.rst
@@ -30,6 +30,7 @@ Cologne Chip  `GateMate Series <https://colognechip.com/programmable-logic/gatem
       Xilinx  XC9500XL `xc9536xl, xc9572xl, xc95144xl, xc95188xl <https://www.xilinx.com/support/documentation/data_sheets/ds054.pdf>`__          NA     OK
       Xilinx  XC2C (coolrunner II) `xc2c32a <https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf>`__                               TBD    OK
       Xilinx  XCF `xcf01s, xcf02s, xcf04s <https://www.xilinx.com/products/silicon-devices/configuration-memory/platform-flash.html>`__           NA     OK
+      Xilinx  Zynq7000 `xc7z010, xc7z020<https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html>`__                                   OK     NA
 ============= =================================================================================================================================== ====== =====
 
 * IF: Internal Flash
diff --git a/src/part.hpp b/src/part.hpp
index 43b6af3..55dc6cd 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -50,6 +50,7 @@ static std::map <int, fpga_model> fpga_list = {
 	{0x05045093, {"xilinx", "xcf",      "xcf02s",    8}},
 	{0x05046093, {"xilinx", "xcf",      "xcf04s",    8}},
 
+	{0x03722093, {"xilinx", "zynq",     "xc7z010", 6}},
 	{0x03727093, {"xilinx", "zynq",     "xc7z020", 6}},
 
 	{0x020f20dd, {"altera", "cyclone III/IV", "EP3C16/EP4CE15", 10}},