From fbb8c58f46bd02127f63e51d11aa01fa1ce55ebb Mon Sep 17 00:00:00 2001 From: Francisco Ayala Le Brun Date: Fri, 16 Oct 2020 08:03:45 +0200 Subject: [PATCH 1/2] Add MachXO3D Development Board Support --- README.md | 2 ++ src/board.hpp | 1 + src/lattice.cpp | 2 ++ src/lattice.hpp | 5 +++-- src/part.hpp | 2 ++ 5 files changed, 10 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index e34b0ff..d667cb8 100644 --- a/README.md +++ b/README.md @@ -9,6 +9,7 @@ __Current support kits:__ * [Digilent Arty S7 xc7s50](https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start) (memory and spi flash) * [Lattice MachXO2 Breakout Board Evaluation Kit (LCMXO2-7000HE)](https://www.latticesemi.com/products/developmentboardsandkits/machxo2breakoutboard) (memory and flash) * Lattice MachXO3LF Starter Kit LCMX03LF-6900C (memory and flash) +* [Lattice MachXO3D Development Board (LCMXO3D-9400HC)](https://www.latticesemi.com/products/developmentboardsandkits/machxo3d_development_board) * [Lattice CrossLink-NX Evaluation Board (LIFCL-40-EVN)](https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/CrossLink-NXEvaluationBoard) (memory and spi flash) * [Lattice ECP5 5G Evaluation Board (LFE5UM5G-85F-EVN)](https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard) (memory and spi flash) * [Trenz Gowin LittleBee (TEC0117)](https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM) @@ -25,6 +26,7 @@ __Supported (tested) FPGA:__ * Gowin [GW1N (GW1N-1, GW1N-4, GW1NR-9)](https://www.gowinsemi.com/en/product/detail/2/) (SRAM and Flash) * Lattice [MachXO2](https://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO2) (SRAM and Flash) * Lattice [MachXO3LF](http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3.aspx) (SRAM and Flash) +* Lattice [MachXO3D](http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3D.aspx) (SRAM and Flash) * Lattice [ECP5 (25F, 5G 85F](http://www.latticesemi.com/Products/FPGAandCPLD/ECP5) (SRAM and Flash) * Lattice [ECP5 (25F, 5G 85F, CrossLink-NX (LIFCL-40)](https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX) (SRAM and Flash) * Xilinx Artix 7 [xc7a35ti, xc7a100t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory (all) and spi flash (xc7a35ti) diff --git a/src/board.hpp b/src/board.hpp index 5cb62ab..17dc47a 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -45,6 +45,7 @@ static std::map board_list = { {"ecp5_evn", {"ft2232", {}}}, {"machXO2EVN", {"ft2232", {}}}, {"machXO3SK", {"ft2232", {}}}, + {"machXO3EVN", {"ft2232", {}}}, {"licheeTang", {"anlogicCable", {}}}, {"littleBee", {"ft2232", {}}}, {"spartanEdgeAccelBoard", {"",{}}}, diff --git a/src/lattice.cpp b/src/lattice.cpp index b13f879..4612751 100644 --- a/src/lattice.cpp +++ b/src/lattice.cpp @@ -92,6 +92,8 @@ Lattice::Lattice(Jtag *jtag, const string filename, _fpga_family = MACHXO2_FAMILY; else if (family == "MachXO3LF") _fpga_family = MACHXO3_FAMILY; + else if (family == "MachXO3D") + _fpga_family = MACHXO3D_FAMILY; else if (family == "ECP5") _fpga_family = ECP5_FAMILY; else if (family == "CrosslinkNX") diff --git a/src/lattice.hpp b/src/lattice.hpp index 089351f..c277c2c 100644 --- a/src/lattice.hpp +++ b/src/lattice.hpp @@ -52,8 +52,9 @@ class Lattice: public Device, SPIInterface { enum lattice_family_t { MACHXO2_FAMILY = 0, MACHXO3_FAMILY = 1, - ECP5_FAMILY = 2, - NEXUS_FAMILY = 3, + MACHXO3D_FAMILY = 2, + ECP5_FAMILY = 3, + NEXUS_FAMILY = 4, UNKNOWN_FAMILY = 999 }; diff --git a/src/part.hpp b/src/part.hpp index 112cbe0..38ce0e3 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -43,6 +43,8 @@ static std::map fpga_list = { {0x612BE043, {"lattice", "MachXO3LF", "LCMX03LF-9400C"}}, {0x612B6043, {"lattice", "MachXO3LF", "LCMX03LF-9400E"}}, + {0x212e3043, {"lattice", "MachXO3D", "LCMX03D-9400H"}}, + {0x21111043, {"lattice", "ECP5", "LFE5U-12"}}, {0x41111043, {"lattice", "ECP5", "LFE5U-25"}}, {0x41112043, {"lattice", "ECP5", "LFE5U-45"}}, From a874a51be358302b46d14d3b0dc918acbe18d13f Mon Sep 17 00:00:00 2001 From: Francisco Ayala Le Brun Date: Fri, 16 Oct 2020 08:08:44 +0200 Subject: [PATCH 2/2] Fix part name typo --- src/part.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/part.hpp b/src/part.hpp index 38ce0e3..dda6e20 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -43,7 +43,7 @@ static std::map fpga_list = { {0x612BE043, {"lattice", "MachXO3LF", "LCMX03LF-9400C"}}, {0x612B6043, {"lattice", "MachXO3LF", "LCMX03LF-9400E"}}, - {0x212e3043, {"lattice", "MachXO3D", "LCMX03D-9400H"}}, + {0x212e3043, {"lattice", "MachXO3D", "LCMX03D-9400HC"}}, {0x21111043, {"lattice", "ECP5", "LFE5U-12"}}, {0x41111043, {"lattice", "ECP5", "LFE5U-25"}},