From e5481787d80b7a658acd38dd6f3ffb153dc71e90 Mon Sep 17 00:00:00 2001
From: Ricardo Barbedo <ricardo@barbedo.me>
Date: Sat, 21 Jan 2023 14:08:00 +0100
Subject: [PATCH] Fix VCU118 board part name and IR length

---
 doc/boards.yml | 2 +-
 src/board.hpp  | 2 +-
 src/part.hpp   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/doc/boards.yml b/doc/boards.yml
index 9338fa3..4ed2440 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -680,6 +680,6 @@
 - ID: vcu118
   Description: Xilinx VCU118
   URL: https://www.xilinx.com/products/boards-and-kits/vcu118.html
-  FPGA: Virtex UltraScale+ xcvu9pl2flga2104e
+  FPGA: Virtex UltraScale+ xcvu9p-flga2104
   Memory: OK
   Flash: NA
diff --git a/src/board.hpp b/src/board.hpp
index 0dac7e1..ab278e1 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -209,7 +209,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("papilio_one",     "xc3s500evq100", "papilio", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("usrpx300",        "xc7k325tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
 	JTAG_BOARD("usrpx310",        "xc7k410tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
-	JTAG_BOARD("vcu118",          "xcvu9pl2flga2104e", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT)
+	JTAG_BOARD("vcu118",          "xcvu9p-flga2104", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT)
 };
 
 #endif
diff --git a/src/part.hpp b/src/part.hpp
index 85b549d..94032a2 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -64,7 +64,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03727093, {"xilinx", "zynq",     "xc7z020", 6}},
 	{0x23731093, {"xilinx", "zynq",     "xc7z045", 6}},
 
-	{0x04b31093, {"xilinx", "virtexusp", "xcvu9p", 6}},
+	{0x04b31093, {"xilinx", "virtexusp", "xcvu9p", 18}},
 
 	/* When powering a zynq ultrascale+ MPSoC, PL Tap and ARM dap
 	 * are disabled and only PS tap with a specific IDCODE is seen.