diff --git a/doc/boards.yml b/doc/boards.yml
index 5801bc9..cde857d 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -94,6 +94,13 @@
   Memory: OK
   Flash: OK
 
+- ID: cmod_s7
+  Description: Digilent Cmod S7
+  URL: https://https://digilent.com/reference/programmable-logic/cmod-s7/start
+  FPGA: Spartan7 xc7s25csga225
+  Memory: NA
+  Flash: OK
+
 - ID: gatemate_evb_jtag
   Description: Cologne Chip GateMate FPGA Evaluation Board (JTAG mode)
   URL: https://colognechip.com/programmable-logic/gatemate-evaluation-board/
diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile
index 93cef95..d9ba999 100644
--- a/spiOverJtag/Makefile
+++ b/spiOverJtag/Makefile
@@ -4,7 +4,7 @@ XILINX_PARTS := xc3s500evq100 xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6sl
 	xc7a50tcpg236 xc7a75tfgg484 \
 	xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
 	xc7a200tsbg484 \
-	xc7s25csga324 xc7s50csga324 \
+	xc7s25csga225 xc7s25csga324 xc7s50csga324 \
 	xc7k160tffg676 \
 	xc7k325tffg676 xc7k325tffg900 \
 	xc7k420tffg901
diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py
index 90076eb..be0138e 100755
--- a/spiOverJtag/build.py
+++ b/spiOverJtag/build.py
@@ -81,6 +81,7 @@ if tool in ["ise", "vivado"]:
         "xc7k325tffg676"   : "xc7k_ffg676",
         "xc7k325tffg900"   : "xc7k_ffg900",
         "xc7k420tffg901"   : "xc7k_ffg901",
+        "xc7s25csga225"    : "xc7s_csga225",
         "xc7s25csga324"    : "xc7s_csga324",
         "xc7s50csga324"    : "xc7s_csga324"
         }[part]
diff --git a/spiOverJtag/constr_xc7s_csga225.xdc b/spiOverJtag/constr_xc7s_csga225.xdc
new file mode 100644
index 0000000..ae06441
--- /dev/null
+++ b/spiOverJtag/constr_xc7s_csga225.xdc
@@ -0,0 +1,10 @@
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS33} [get_ports {csn}];
+set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
+set_property -dict {PACKAGE_PIN J12 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
+set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
diff --git a/spiOverJtag/xilinx_spiOverJtag.tcl b/spiOverJtag/xilinx_spiOverJtag.tcl
index 0777075..ba50612 100644
--- a/spiOverJtag/xilinx_spiOverJtag.tcl
+++ b/spiOverJtag/xilinx_spiOverJtag.tcl
@@ -16,6 +16,7 @@ set grade [dict create \
 	xc7a200tsbg484 -1 \
 	xc7k325tffg676 -1 \
 	xc7k325tffg900 -2 \
+	xc7s25csga225  -1 \
 	xc7s50csga324  -1 \
 	]
 
@@ -30,6 +31,7 @@ set pkg_name [dict create \
 	xc7a200tfbg484 xc7a_fbg484 \
 	xc7k325tffg676 xc7k_ffg676 \
 	xc7k325tffg900 xc7k_ffg900 \
+	xc7s25csga225  xc7s_csga225 \
 	xc7s50csga324  xc7s_csga324 \
 	]
 
diff --git a/src/board.hpp b/src/board.hpp
index 1b72daa..6b1fd22 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -115,6 +115,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("arty_z7_20",      "xc7z020clg400",  "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("axu2cga",         "xczu2cg",        "",         0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("basys3",          "xc7a35tcpg236",  "digilent", 0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("cmod_s7",         "xc7s25csga225",  "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("cmoda7_35t",      "xc7a35tcpg236",  "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("nexysVideo",      "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("kc705",           "", "digilent", 0, 0, CABLE_DEFAULT),