From d188314ae329efe6dce186a0d14cbec57c6bd84d Mon Sep 17 00:00:00 2001
From: TG <tarik.graba@telecom-paris.fr>
Date: Wed, 9 Feb 2022 17:21:19 +0100
Subject: [PATCH] part: add altera 5CSEMA5 (cyclone V Soc)

---
 src/part.hpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/part.hpp b/src/part.hpp
index df8d8a6..422aee6 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -71,6 +71,7 @@ static std::map <int, fpga_model> fpga_list = {
 	{0x02b050dd, {"altera", "cyclone V", "5CEBA4", 10}},
 	{0x02d020dd, {"altera", "cyclone V Soc", "5CSEBA6", 10}},
 	{0x02d010dd, {"altera", "cyclone V Soc", "5CSEMA4", 10}},
+	{0x02d120dd, {"altera", "cyclone V Soc", "5CSEMA5", 10}},
 
 	{0x00000001, {"efinix", "Trion",    "T4/T8",            4}},
 	{0x00210a79, {"efinix", "Trion",    "T8QFP144/T13/T20", 4}},