diff --git a/CMakeLists.txt b/CMakeLists.txt index 0f8a6c1..2948dfa 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -159,5 +159,6 @@ install(TARGETS openFPGALoader DESTINATION bin) install(FILES test_sfl.svf spiOverJtag/spiOverJtag_xc7a35.bit + spiOverJtag/spiOverJtag_xc7s50.bit DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/openFPGALoader ) diff --git a/README.md b/README.md index 553349e..415a1d4 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,8 @@ __Current support kits:__ * Trenz cyc1000 Cyclone 10 LP 10CL025 (memory and spi flash) * [Colorlight 5A-75B (version 7)](https://fr.aliexpress.com/item/32281130824.html) (memory and spi flash) -* Digilent arty Artix xc7a35ti (memory and spi flash) +* [Digilent Arty A7 xc7a35ti](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) (memory and spi flash) +* [Digilent Arty S7 xc7s50](https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start) (memory and spi flash) * [Lattice MachXO2 Breakout Board Evaluation Kit (LCMXO2-7000HE)](https://www.latticesemi.com/products/developmentboardsandkits/machxo2breakoutboard) (memory and flash) * Lattice MachXO3LF Starter Kit LCMX03LF-6900C (memory and flash) * [Lattice ECP5 5G Evaluation Board (LFE5UM5G-85F-EVN)](https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard) (memory and spi flash) @@ -23,7 +24,7 @@ __Supported (tested) FPGA:__ * Lattice [ECP5 (25F, 5G 85F](http://www.latticesemi.com/Products/FPGAandCPLD/ECP5) (SRAM and Flash) * Xilinx Artix 7 [xc7a35ti, xc7a100t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory (all) and spi flash (xc7a35ti) * Xilinx Spartan 6 [xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory) -* Xilinx Spartan 7 [xc7s15](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) (memory) +* Xilinx Spartan 7 [xc7s15, xc7s50](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) (memory (all) and spi flash (xc7s50)) * Intel Cyclone 10 LP [10CL025](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html) __Supported cables:__ diff --git a/spiOverJtag/.gitignore b/spiOverJtag/.gitignore index a9a5aec..ab1a990 100644 --- a/spiOverJtag/.gitignore +++ b/spiOverJtag/.gitignore @@ -1 +1 @@ -tmp +tmp_* diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index 8be7aa5..834b4b1 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -1,14 +1,13 @@ VIVADO := vivado -nolog -nojournal -mode batch -source -MODEL = xc7a35 -PRJ = spiOverJtag_$(MODEL) +MODELS := xc7a35 xc7s50 +BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(MODELS))) -BIT_PATH = tmp/$(PRJ).runs/impl_1/ -BIT_TMP_FILE = $(BIT_PATH)/*.bit -BIT_FILE = $(PRJ).bit +all: $(BIT_FILES) + +$(BIT_FILES) : spiOverJtag_%.bit : tmp_%/spiOverJtag.runs/impl_1/xilinx_spiOverJtag.bit + cp $< $@ +tmp_%/spiOverJtag.runs/impl_1/xilinx_spiOverJtag.bit : xilinx_spiOverJtag.vhd constr_%.xdc + $(VIVADO) xilinx_spiOverJtag.tcl -tclargs $* -$(BIT_FILE) : $(BIT_TMP_FILE) - cp $(BIT_TMP_FILE) $(BIT_FILE) -$(BIT_TMP_FILE): xilinx_spiOverJtag.vhd constr.xdc - $(VIVADO) xilinx_spiOverJtag.tcl -tclargs $(MODEL) clean: - -rm -rf tmp *.jou *.log .Xil + -rm -rf tmp_* *.jou *.log .Xil diff --git a/spiOverJtag/constr.xdc b/spiOverJtag/constr_xc7a35.xdc similarity index 98% rename from spiOverJtag/constr.xdc rename to spiOverJtag/constr_xc7a35.xdc index 72cd66b..fd0df62 100644 --- a/spiOverJtag/constr.xdc +++ b/spiOverJtag/constr_xc7a35.xdc @@ -1,9 +1,9 @@ -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] - -set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports {csn}]; -set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; -set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; -set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] + +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports {csn}]; +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; diff --git a/spiOverJtag/constr_xc7s50.xdc b/spiOverJtag/constr_xc7s50.xdc new file mode 100644 index 0000000..28938dd --- /dev/null +++ b/spiOverJtag/constr_xc7s50.xdc @@ -0,0 +1,9 @@ +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] + +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {csn}]; +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; diff --git a/spiOverJtag/spiOverJtag_xc7s50.bit b/spiOverJtag/spiOverJtag_xc7s50.bit new file mode 100644 index 0000000..f3ea57e Binary files /dev/null and b/spiOverJtag/spiOverJtag_xc7s50.bit differ diff --git a/spiOverJtag/xilinx_spiOverJtag.tcl b/spiOverJtag/xilinx_spiOverJtag.tcl index e404bc4..4bfe615 100644 --- a/spiOverJtag/xilinx_spiOverJtag.tcl +++ b/spiOverJtag/xilinx_spiOverJtag.tcl @@ -1,15 +1,16 @@ set model [lindex $argv 0] -set project_name "spiOverJtag_${model}" +set project_name "spiOverJtag" -set build_path tmp +set build_path tmp_${model} file delete -force $build_path # Project creation -create_project $project_name $build_path -part xc7a35ticsg324-1L +set parts [dict create xc7a35 xc7a35ticsg324-1L xc7s50 xc7s50csga324-1] +create_project $project_name $build_path -part [dict get $parts $model] add_files -norecurse xilinx_spiOverJtag.vhd -add_files -norecurse -fileset constrs_1 constr.xdc +add_files -norecurse -fileset constrs_1 constr_${model}.xdc set_property VERILOG_DEFINE {TOOL_VIVADO} [current_fileset] diff --git a/src/part.hpp b/src/part.hpp index e81095a..08a004c 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -16,6 +16,7 @@ static std::map fpga_list = { {0x44008093, {"xilinx", "spartan6", "xc6slx45"}}, {0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1"}}, + {0x0362f093, {"xilinx", "spartan7", "xc7s50"}}, {0x020f30dd, {"altera", "cyclone 10 LP", "10CL025"}},