diff --git a/doc/boards.yml b/doc/boards.yml
index cde857d..665ed0e 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -19,7 +19,14 @@
   FPGA: Artix xc7a35tftg256
   Memory: OK
   Flash: OK
-
+  
+- ID: alchitry_au_plus
+  Description: Alchitry Au+ (Plus)
+  URL: https://www.sparkfun.com/products/17514
+  FPGA: Artix xc7a100tftg256
+  Memory: OK
+  Flash: OK
+  
 - ID: arty_a7_35t
   Description: Digilent Arty A7
   URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start
diff --git a/src/board.hpp b/src/board.hpp
index 6b1fd22..be39a72 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -105,6 +105,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("ac701",           "xc7a200t2fbg676c", "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("acornCle215",     "xc7a200tsbg484", "",         0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("alchitry_au",     "xc7a35tftg256",  "ft2232",   0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("alchitry_au_plus","xc7a100tftg256",  "ft2232",   0, 0, CABLE_DEFAULT),
 	/* left for backward compatibility, use right name instead */
 	JTAG_BOARD("arty",            "xc7a35tcsg324",  "digilent", 0, 0, CABLE_MHZ(10)),
 	JTAG_BOARD("arty_a7_35t",     "xc7a35tcsg324",  "digilent", 0, 0, CABLE_MHZ(10)),