From 905e96dfeceb00f19857096dd46bf163936163c7 Mon Sep 17 00:00:00 2001 From: Hansem Ro Date: Tue, 15 Feb 2022 17:16:52 -0800 Subject: [PATCH] Add digilent_zybo_z7 10/20 support --- doc/boards.yml | 14 ++++++++++++++ src/board.hpp | 2 ++ 2 files changed, 16 insertions(+) diff --git a/doc/boards.yml b/doc/boards.yml index 4fa129d..2913278 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -469,3 +469,17 @@ Memory: OK Flash: NA Constraints: ZedBoard + +- ID: zybo_z7_10 + Description: Digilent Zybo Z7-10 + URL: https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start + FPGA: zynq7000 xc7z010clg400 + Memory: OK + Flash: NA + +- ID: zybo_z7_20 + Description: Digilent Zybo Z7-20 + URL: https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start + FPGA: zynq7000 xc7z020clg400 + Memory: OK + Flash: NA diff --git a/src/board.hpp b/src/board.hpp index 61630ef..0217be5 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -118,6 +118,8 @@ static std::map board_list = { JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT), JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("zc702", "xc7z020clg484", "digilent", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("zybo_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("zybo_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("colorlight", "", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("colorlight-i5", "", "cmsisdap", 0, 0, CABLE_DEFAULT), JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),