From 88c4d86e635ebaf8959034f3e3b38de80a0da021 Mon Sep 17 00:00:00 2001
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 22 Mar 2023 17:52:41 +0100
Subject: [PATCH] Add xc7vx330t

---
 doc/FPGAs.yml | 17 +++++++++++++++++
 src/part.hpp  |  3 +++
 2 files changed, 20 insertions(+)

diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml
index 3a96de4..a423546 100644
--- a/doc/FPGAs.yml
+++ b/doc/FPGAs.yml
@@ -218,6 +218,23 @@ Xilinx:
     Memory: OK
     Flash: OK
 
+  - Description: Virtex 7
+    Model:
+      - xc7v585t
+      - xc7v2000t
+      - xc7vx330t
+      - xc7vx415t
+      - xc7vx485t
+      - xc7vx550t
+      - xc7vx690t
+      - xc7vx980t
+      - xc7vx1140t
+      - xc7vh580t
+      - xc7vh870t
+    URL: https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html#productTable
+    Memory: OK
+    Flash: OK
+
   - Description: Artix UltraScale+
     Model:
       - xcau25p
diff --git a/src/part.hpp b/src/part.hpp
index 188e88d..567d15d 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -82,6 +82,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03656093, {"xilinx", "kintex7", "xc7k410t", 6}},
 	{0x23752093, {"xilinx", "kintex7", "xc7k420t", 6}},
 
+	/* Xilinx XC7V */
+	{0x03667093, {"xilinx", "virtex7", "xc7vx330t",  6}},
+
 	/* Xilinx 7-Series / Zynq */
 	{0x03722093, {"xilinx", "zynq",     "xc7z010", 6}},
 	{0x03727093, {"xilinx", "zynq",     "xc7z020", 6}},