diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml index 3a96de4..a423546 100644 --- a/doc/FPGAs.yml +++ b/doc/FPGAs.yml @@ -218,6 +218,23 @@ Xilinx: Memory: OK Flash: OK + - Description: Virtex 7 + Model: + - xc7v585t + - xc7v2000t + - xc7vx330t + - xc7vx415t + - xc7vx485t + - xc7vx550t + - xc7vx690t + - xc7vx980t + - xc7vx1140t + - xc7vh580t + - xc7vh870t + URL: https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html#productTable + Memory: OK + Flash: OK + - Description: Artix UltraScale+ Model: - xcau25p diff --git a/doc/boards.yml b/doc/boards.yml index 8ff43af..06cc6c7 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -735,6 +735,12 @@ FPGA: Gowin Arora V GW5AST-138B (GW5AST-LV138FPG676A) Memory: OK Flash: TBD +- ID: te0712_8 + Description: Trenz Electronic TE0712 FPGA-Module mit AMD Artix™ 7(TE0712) + URL: https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM + FPGA: XC7A200TFBG484 + Memory: OK + Flash: OK - ID: tec0117 Description: Trenz Gowin LittleBee (TEC0117) @@ -750,6 +756,13 @@ Memory: OK Flash: NT +- ID: tec0330 + Description: PCIe FMC Carrier with Xilinx Virtex-7 FPGA (TEC0330) + URL: https://shop.trenz-electronic.de//TEC0330-05-PCIe-FMC-Carrier-with-Xilinx-Virtex-7-FPGA-8-Lane-PCIe-GEN2-SODIMM-SDRAM + FPGA: XC7VX330T-2FFG1157C + Memory: OK + Flash: OK + - ID: trion_t120_bga576 Description: Efinix Trion T120 BGA576 Dev Kit (SPI mode) URL: https://www.efinixinc.com/products-devkits-triont120bga576.html diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index 8990ae4..3d24a73 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -15,6 +15,7 @@ XILINX_PARTS := xc3s500evq100 \ xc7k325tffg676 xc7k325tffg900 \ xc7k420tffg901 \ xcku3p-ffva676 \ + xc7vx330tffg1157 \ xcku5p-ffvb676 \ xcvu9p-flga2104 xcvu37p-fsvh2892 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index d51c693..36b43fe 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -35,6 +35,9 @@ elif subpart[0:2] == '5c': elif subpart == "xc7a": family = "Artix" tool = "vivado" +elif subpart == "xc7v": + family = "Virtex 7" + tool = "vivado" elif subpart == "xc7k": device_size = int(part.split('k')[1].split('t')[0]) if device_size <= 160: @@ -100,6 +103,7 @@ if tool in ["ise", "vivado"]: "xc7k325tffg676" : "xc7k_ffg676", "xc7k325tffg900" : "xc7k_ffg900", "xc7k420tffg901" : "xc7k_ffg901", + "xc7vx330tffg1157" : "xc7v_ffg1157", "xc7s25csga225" : "xc7s_csga225", "xc7s25csga324" : "xc7s_csga324", "xc7s50csga324" : "xc7s_csga324", diff --git a/spiOverJtag/constr_xc7v_ffg1157.ucf b/spiOverJtag/constr_xc7v_ffg1157.ucf new file mode 100644 index 0000000..2901887 --- /dev/null +++ b/spiOverJtag/constr_xc7v_ffg1157.ucf @@ -0,0 +1,5 @@ +NET "csn" LOC = AL33 | IOSTANDARD = LVCMOS18; +NET "sdi_dq0" LOC = AN33 | IOSTANDARD = LVCMOS18; +NET "sdo_dq1" LOC = AN34 | IOSTANDARD = LVCMOS18; +NET "wpn_dq2" LOC = AK34 | IOSTANDARD = LVCMOS18; +NET "hldn_dq3" LOC = AL34 | IOSTANDARD = LVCMOS18; diff --git a/spiOverJtag/constr_xc7v_ffg1157.xdc b/spiOverJtag/constr_xc7v_ffg1157.xdc new file mode 100644 index 0000000..729913e --- /dev/null +++ b/spiOverJtag/constr_xc7v_ffg1157.xdc @@ -0,0 +1,11 @@ +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +# Table 1-2 from UG570 +set_property CFGBVS GND [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] + +set_property -dict {PACKAGE_PIN AL33 IOSTANDARD LVCMOS18} [get_ports {csn}] +set_property -dict {PACKAGE_PIN AN33 IOSTANDARD LVCMOS18} [get_ports {sdi_dq0}] +set_property -dict {PACKAGE_PIN AN34 IOSTANDARD LVCMOS18} [get_ports {sdo_dq1}] +set_property -dict {PACKAGE_PIN AK34 IOSTANDARD LVCMOS18} [get_ports {wpn_dq2}] +set_property -dict {PACKAGE_PIN AL34 IOSTANDARD LVCMOS18} [get_ports {hldn_dq3}] diff --git a/spiOverJtag/spiOverJtag_xc7vx330tffg1157.bit.gz b/spiOverJtag/spiOverJtag_xc7vx330tffg1157.bit.gz new file mode 100644 index 0000000..fc864b7 Binary files /dev/null and b/spiOverJtag/spiOverJtag_xc7vx330tffg1157.bit.gz differ diff --git a/src/board.hpp b/src/board.hpp index 7d1f84c..d845a06 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -210,7 +210,9 @@ static std::map board_list = { JTAG_BOARD("tangprimer20k", "", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("tangprimer25k", "", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("tangmega138k", "", "ft2232", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("te0712_8", "xc7a200tfbg484", "", 0, 0, CABLE_MHZ(15)), JTAG_BOARD("tec0117", "", "ft2232", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("tec0330", "xc7vx330tffg1157", "", 0, 0, CABLE_MHZ(15)), SPI_BOARD("titanium_ti60_f225","efinix", "efinix_spi_ft4232", DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT), JTAG_BOARD("titanium_ti60_f225_jtag", "ti60f225","efinix_jtag_ft4232", 0, 0, CABLE_DEFAULT), diff --git a/src/part.hpp b/src/part.hpp index 188e88d..567d15d 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -82,6 +82,9 @@ static std::map fpga_list = { {0x03656093, {"xilinx", "kintex7", "xc7k410t", 6}}, {0x23752093, {"xilinx", "kintex7", "xc7k420t", 6}}, + /* Xilinx XC7V */ + {0x03667093, {"xilinx", "virtex7", "xc7vx330t", 6}}, + /* Xilinx 7-Series / Zynq */ {0x03722093, {"xilinx", "zynq", "xc7z010", 6}}, {0x03727093, {"xilinx", "zynq", "xc7z020", 6}}, diff --git a/src/spiFlashdb.hpp b/src/spiFlashdb.hpp index cca1561..0918a6d 100644 --- a/src/spiFlashdb.hpp +++ b/src/spiFlashdb.hpp @@ -195,6 +195,19 @@ static std::map flash_list = { .bp_len = 4, .bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 6)}} }, + {0x0020bb19, { + .manufacturer = "micron", + .model = "N25Q256A", + .nr_sector = 512, + .sector_erase = true, + .subsector_erase = true, + .has_extended = true, + .tb_otp = false, + .tb_offset = (1 << 5), + .tb_register = STATR, + .bp_len = 4, + .bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 6)}} + }, {0x0020bb21, { .manufacturer = "micron", .model = "MT25QU01G",