From 7e4b42b7959022871e909fd99c69b2f362f091ce Mon Sep 17 00:00:00 2001 From: Julio Nunes Avelar Date: Fri, 12 Jul 2024 23:32:14 -0300 Subject: [PATCH] Adding support for AMD Virtex 7 FPGA VC709 Connectivity Kit Board --- doc/boards.yml | 7 +++++++ src/board.hpp | 1 + 2 files changed, 8 insertions(+) diff --git a/doc/boards.yml b/doc/boards.yml index 2989c0e..4573792 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -846,6 +846,13 @@ Memory: OK Flash: OK +- ID: vc709 + Description: AMD Virtex-7 FPGA VC709 Connectivity Kit + URL: https://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html + FPGA: Virtex7 xc7vx690tffg1761 + Memory: OK + Flash: NA + - ID: vcu118 Description: Xilinx VCU118 URL: https://www.xilinx.com/products/boards-and-kits/vcu118.html diff --git a/src/board.hpp b/src/board.hpp index 3425940..ae95cdc 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -233,6 +233,7 @@ static std::map board_list = { JTAG_BOARD("usrpx300", "xc7k325tffg900", "digilent", 0, 0, CABLE_MHZ(15)), JTAG_BOARD("usrpx310", "xc7k410tffg900", "digilent", 0, 0, CABLE_MHZ(15)), JTAG_BOARD("vec_v6", "xc6vlx130tff784", "ft2232", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("vc709", "xc7vx690tffg1761", "digilent", 0, 0, CABLE_MHZ(15)), JTAG_BOARD("vcu118", "xcvu9p-flga2104", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT), JTAG_BOARD("vcu128", "xcvu37p-fsvh2892", "ft4232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("vcu1525", "xcvu9p-fsgd2104", "ft4232", 0, 0, CABLE_MHZ(15)),