diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile
index f34c4bf..232fa2f 100644
--- a/spiOverJtag/Makefile
+++ b/spiOverJtag/Makefile
@@ -14,7 +14,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xcku040-ffva1156 xcku060-ffva1156 \
 	xcku5p-ffvb676 \
 	xcvu9p-flga2104 xcvu37p-fsvh2892 \
-	xcau10p-ffvb676 \
+	xcau7p-sbvc484 xcau10p-ffvb676 \
 	xcau15p-ffvb676
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
 
diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py
index 7a42fb8..299286b 100755
--- a/spiOverJtag/build.py
+++ b/spiOverJtag/build.py
@@ -151,6 +151,7 @@ if tool in ["ise", "vivado"]:
         "xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
         "xcku3p-ffva676"   : "xcku3p_ffva676",
         "xcku5p-ffvb676"   : "xcku5p_ffvb676",
+        "xcau7p-sbvc484"   : "xcau7p_sbvc484",
         "xcau10p-ffvb676"  : "xcau10p_ffvb676",
         "xcau15p-ffvb676"  : "xcau15p_ffvb676",
     }.get(part, pkg_name)
@@ -213,6 +214,8 @@ if tool in ["ise", "vivado"]:
                     'paramtype': 'vlogdefine',
                     'description': 'secondary flash',
                     'default': 1}
+            elif part == "xcau7p-sbvc484":
+                tool_options = {'part': part + '-1-e'}
             elif part == "xcau10p-ffvb676":
                 tool_options = {'part': part + '-1-e'}
             elif part == "xcau15p-ffvb676":
diff --git a/spiOverJtag/constr_xcau7p_sbvc484.xdc b/spiOverJtag/constr_xcau7p_sbvc484.xdc
new file mode 100644
index 0000000..bc4bb4a
--- /dev/null
+++ b/spiOverJtag/constr_xcau7p_sbvc484.xdc
@@ -0,0 +1,7 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+# Table 1-2 from UG570
+set_property CFGBVS GND [current_design]
+
+# Primary QSPI flash
+# Connection done through the STARTUPE3 block
diff --git a/spiOverJtag/xilinx_spiOverJtag.v b/spiOverJtag/xilinx_spiOverJtag.v
index 4406029..07316b1 100644
--- a/spiOverJtag/xilinx_spiOverJtag.v
+++ b/spiOverJtag/xilinx_spiOverJtag.v
@@ -74,7 +74,8 @@ module spiOverJtag
 	assign sck = drck;
 `else // !spartan6 && !spartan3e
 `ifdef xilinxultrascale
-	assign sck = drck;
+	wire csn;
+	wire sdi_dq0, sdo_dq1, wpn_dq2, hldn_dq3;
 	wire [3:0] di;
 	assign sdo_dq1 = di[1];
 	wire [3:0] do = {hldn_dq3, wpn_dq2, 1'b0, sdi_dq0};
diff --git a/src/part.hpp b/src/part.hpp
index 1fee941..86f36c5 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -131,6 +131,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x03842093, {"xilinx", "virtexus", "xcvu095", 6}},
 
 	/* Xilinx Ultrascale+ / Artix */
+	{0x04AF6093, {"xilinx", "artixusp",  "xcau7p-sbvc484",  6}},
 	{0x04AC4033, {"xilinx", "artixusp",  "xcau10p", 6}},
 	{0x04AC4093, {"xilinx", "artixusp",  "xcau10p", 6}},
 	{0x04AC2093, {"xilinx", "artixusp",  "xcau15p", 6}},