diff --git a/doc/boards.yml b/doc/boards.yml
index 674d41f..6e270c0 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -265,6 +265,13 @@
   Memory: OK
   Flash: OK
 
+- ID: cyc5000
+  Description: Trenz CYC5000
+  URL: https://shop.trenz-electronic.de/en/TEI0050-01-AAH13A-CYC5000-with-Cyclone-V-FPGA-25kLE-8-MByte-SDRAM
+  FPGA: Cyclone V 5CEBA2U15C8
+  Memory: OK
+  Flash: OK
+
 - ID: c10lp-refkit
   Description: Trenz c10lp-refkit
   URL: https://shop.trenz-electronic.de/en/TEI0009-02-055-8CA-Cyclone-10-LP-RefKit-10CL055-Development-Board-32-MByte-SDRAM-16-MByte-Flash
diff --git a/doc/vendors/intel.rst b/doc/vendors/intel.rst
index d87b997..9cce370 100644
--- a/doc/vendors/intel.rst
+++ b/doc/vendors/intel.rst
@@ -34,6 +34,14 @@ SVF and RBF files are supported.
   As mentioned in ``cyclone`` handbooks, real-time decompression is not supported by FPGA in JTAG mode.
   Keep in mind to disable this option.
 
+You can have Quartus automatically generate SVF and RBF files by adding these lines to the ``qsf`` file, or include them in a ``tcl`` file in FuseSoC
+
+.. code-block:: 
+
+    set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+    set_global_assignment -name GENERATE_RBF_FILE ON
+    set_global_assignment -name GENERATE_SVF_FILE ON
+
 file load:
 
 .. code-block:: bash
@@ -49,6 +57,12 @@ SPI flash
 
 RPD and RBF are supported.
 
+``pof`` to ``rpd``:
+
+.. code-block:: bash
+
+    quartus_cpf -c project_name.pof project_name.rpd
+
 ``sof`` to ``rpd``:
 
 .. code-block:: bash
diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile
index 8504ef7..52501cb 100644
--- a/spiOverJtag/Makefile
+++ b/spiOverJtag/Makefile
@@ -21,7 +21,7 @@ XILINX_PARTS := xc3s500evq100 \
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
 
 ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
-	ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce223 5ce423 5ce523 5ce927
+	ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927
 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
 
 EFINIX_PARTS := t8f81 t13f256
diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py
index 63da511..b135f76 100755
--- a/spiOverJtag/build.py
+++ b/spiOverJtag/build.py
@@ -189,6 +189,7 @@ else:
         "ep4ce1523"  : "EP4CE15F23C8",
         "ep4ce1017"  : "EP4CE10F17C8",
         "ep4ce622"   : "EP4CE6E22C8",
+        "5ce215"     : "5CEBA2U15C8",
         "5ce223"     : "5CEFA2F23I7",
         "5ce523"     : "5CEFA5F23I7",
         "5ce423"     : "5CEBA4F23C8",
diff --git a/spiOverJtag/spiOverJtag_5ce215.rbf.gz b/spiOverJtag/spiOverJtag_5ce215.rbf.gz
new file mode 100644
index 0000000..e32e7f5
Binary files /dev/null and b/spiOverJtag/spiOverJtag_5ce215.rbf.gz differ
diff --git a/src/board.hpp b/src/board.hpp
index 7a35a11..0e19d9f 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -137,6 +137,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("certuspronx_evn",       "", "ft2232", 0, 0, CABLE_MHZ(1)),
 	JTAG_BOARD("certuspronx_versa_evn", "", "ft2232", 0, 0, CABLE_MHZ(1)),
 	JTAG_BOARD("cyc1000",         "10cl025256", "ft2232",     0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("cyc5000",         "5ce215", "ft2232",     0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("c10lp-refkit",    "10cl055484", "ft2232",     0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de0",             "", "usb-blaster",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de0nano",         "ep4ce2217", "usb-blaster",0, 0, CABLE_DEFAULT),