From 6d787b4053df390552a67c55bdf568e22b6a7724 Mon Sep 17 00:00:00 2001 From: Dave Keeshan Date: Sat, 4 Jul 2026 00:17:21 +0100 Subject: [PATCH] boards: add ALINX AXKU095 (XCKU095-FFVA1156) Add board preset for the Alinx AXKU095 Kintex UltraScale dev board, using the Digilent HS2 cable (FT232H). Tested JTAG detect and SRAM programming with IDCODE 0x23844093. --- doc/boards.yml | 7 +++++++ src/board.hpp | 1 + 2 files changed, 8 insertions(+) diff --git a/doc/boards.yml b/doc/boards.yml index 2e04506..8892dc3 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -34,6 +34,13 @@ Memory: OK Flash: OK +- ID: alinx_axku095 + Description: ALINX AXKU095 Kintex UltraScale FPGA Dev Board + URL: https://www.en.alinx.com/Product/FPGA-Development-Boards/Kintex-UltraScale/AXKU095.html + FPGA: Kintex UltraScale xcku095-ffva1156 + Memory: OK + Flash: OK + - ID: atumA3Nano Description: Terasic Atum A3 Nano URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1373 diff --git a/src/board.hpp b/src/board.hpp index 7a570df..ed9cab0 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -124,6 +124,7 @@ static std::map board_list = { JTAG_BOARD("alinx_ax7102", "xc7a100tfgg484", "", SPI_FLASH, 0, 0, CABLE_DEFAULT), JTAG_BOARD("alinx_ax7201", "xc7a200tfbg484", "", SPI_FLASH, 0, 0, CABLE_DEFAULT), JTAG_BOARD("alinx_ax7203", "xc7a200tfbg484", "", SPI_FLASH, 0, 0, CABLE_DEFAULT), + JTAG_BOARD("alinx_axku095", "xcku095-ffva1156", "digilent_hs2", SPI_FLASH, 0, 0, CABLE_DEFAULT), JTAG_BOARD("antmicro_ddr4_tester", "xc7k160tffg676", "ft4232", SPI_FLASH, 0, 0, CABLE_DEFAULT), JTAG_BOARD("antmicro_ddr5_tester", "xc7k160tffg676", "ft4232", SPI_FLASH, 0, 0, CABLE_DEFAULT), JTAG_BOARD("antmicro_lpddr4_tester", "xc7k70tfbg484", "ft4232", SPI_FLASH, 0, 0, CABLE_DEFAULT),