diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index d599332..e9c94ee 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -3,13 +3,8 @@ XILINX_PARTS := xc3s500evq100 \ xc6slx16ftg256 xc6slx16csg324 xc6slx25csg324 xc6slx45csg324 xc6slx100fgg484 \ xc6slx25tcsg324 xc6slx45tfgg484 xc6slx150tfgg484 xc6slx150tcsg484 \ xc6vlx130tff784 \ - xc7a15tcpg236 xc7a15tfgg484 \ - xc7a25tcpg238 xc7a25tcsg325 \ - xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a35tfgg484 \ - xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a50tcsg325 xc7a75tfgg484 \ - xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\ - xc7a200tsbg484 xc7a200tfbg484 xc7a200tfbg676\ - xc7s6ftgb196 xc7s25csga225 xc7s25csga324 xc7s50csga324 \ + xc7a12t xc7a15t xc7a25t xc7a35t xc7a50t xc7a75t xc7a100t xc7a200t \ + xc7s6 xc7s15 xc7s25 xc7s50 xc7s75 xc7s100 \ xc7k70tfbg484 xc7k70tfbg676 \ xc7k160tffg676 \ xc7k325tffg676 xc7k325tffg900 \ @@ -19,7 +14,7 @@ XILINX_PARTS := xc3s500evq100 \ xcku040-ffva1156 xcku060-ffva1156 \ xcku5p-ffvb676 \ xcvu9p-flga2104 xcvu37p-fsvh2892 \ - xcau15p-ffvb676 + xcau15p-ffvb676 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \ @@ -39,7 +34,7 @@ tmp_efinix_%/efinix_spiOverJtag.bit : efinix_spiOverJtag.v ./efinix_build.py --device $* $(XILINX_BIT_FILES) : spiOverJtag_%.bit.gz : tmp_%/spiOverJtag.bit - gzip -9 -c $< > $@ + tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v spiOverJtag_core.v ./build.py $* diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index e5352fb..bcbaf41 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -1,7 +1,30 @@ #!/usr/bin/env python3 -from edalize.edatool import get_edatool + import os +from edalize.edatool import get_edatool + +packages = { + "Artix": { + "xc7a12t" : ["cpg238", "csg325"], + "xc7a15t" : ["cpg236", "csg324", "csg325", "ftg256", "fgg484"], + "xc7a25t" : ["cpg238", "csg325"], + "xc7a35t" : ["cpg236", "csg324", "csg325", "ftg256", "fgg484"], + "xc7a50t" : ["cpg236", "csg324", "csg325", "ftg256", "fgg484"], + "xc7a75t" : ["csg324", "ftg256", "fgg484", "fgg676"], + "xc7a100t" : ["csg324", "ftg256", "fgg484", "fgg676"], + "xc7a200t" : ["sbg484", "fbg484", "fbg676", "ffg1156"], + }, + "Spartan 7": { + "xc7s6" : ["ftgb196", "cpga196", "csga225"], + "xc7s15" : ["ftgb196", "cpga196", "csga225"], + "xc7s25" : ["ftgb196", "csga225", "csga324"], + "xc7s50" : ["ftgb196", "csga324", "fgga484"], + "xc7s75" : ["fgga484", "fgga676"], + "xc7s100" : ["fgga484", "fgga676"], + }, +} + if len(os.sys.argv) != 2: print("missing board param") os.sys.exit() @@ -16,9 +39,10 @@ if not os.path.isdir(build_dir): else: print ("Successfully created the directory %s " % build_dir) -currDir = os.path.abspath(os.path.curdir) + '/' -files = [] +currDir = os.path.abspath(os.path.curdir) + '/' +files = [] parameters = {} +pkg_name = None subpart = part[0:4].lower() if subpart == '10cl': @@ -39,7 +63,8 @@ elif subpart[0:2] == '5s': 'file_type': 'tclSource'}) elif subpart == "xc7a": family = "Artix" - tool = "vivado" + tool = "vivado" + model = subpart elif subpart == "xc7v": family = "Virtex 7" tool = "vivado" @@ -54,7 +79,8 @@ elif subpart == "xc7k": speed = -2 elif subpart == "xc7s": family = "Spartan 7" - tool = "vivado" + tool = "vivado" + model = subpart elif subpart == "xc6s": family = "Spartan6" tool = "ise" @@ -74,6 +100,10 @@ else: print("Error: unknown device") os.sys.exit() +if model in ["xc7a", "xc7s"]: + pkg = packages[family][part][0] + pkg_name = f"{model}_{pkg}" + if tool in ["ise", "vivado"]: pkg_name = { "xc3s500evq100" : "xc3s_vq100", @@ -89,25 +119,6 @@ if tool in ["ise", "vivado"]: "xc6slx150tcsg484" : "xc6s_csg484", "xc6slx150tfgg484" : "xc6s_t_fgg484", "xc6vlx130tff784" : "xc6v_ff784", - "xc7a15tcpg236" : "xc7a_cpg236", - "xc7a15tfgg484" : "xc7a_fgg484", - "xc7a25tcpg238" : "xc7a_cpg238", - "xc7a25tcsg325" : "xc7a_csg325", - "xc7a35tcpg236" : "xc7a_cpg236", - "xc7a35tcsg324" : "xc7a_csg324", - "xc7a35tftg256" : "xc7a_ftg256", - "xc7a35tfgg484" : "xc7a_fgg484", - "xc7a50tcpg236" : "xc7a_cpg236", - "xc7a50tcsg324" : "xc7a_csg324", - "xc7a50tfgg484" : "xc7a_fgg484", - "xc7a50tcsg325" : "xc7a_csg325", - "xc7a75tfgg484" : "xc7a_fgg484", - "xc7a100tcsg324" : "xc7a_csg324", - "xc7a100tfgg484" : "xc7a_fgg484", - "xc7a100tfgg676" : "xc7a_fgg676", - "xc7a200tsbg484" : "xc7a_sbg484", - "xc7a200tfbg484" : "xc7a_fbg484", - "xc7a200tfbg676" : "xc7a_fbg676", "xc7k70tfbg484" : "xc7k_fbg484", "xc7k70tfbg676" : "xc7k_fbg676", "xc7k160tffg676" : "xc7k_ffg676", @@ -115,11 +126,6 @@ if tool in ["ise", "vivado"]: "xc7k325tffg900" : "xc7k_ffg900", "xc7k420tffg901" : "xc7k_ffg901", "xc7vx330tffg1157" : "xc7v_ffg1157", - "xc7s6ftgb196" : "xc7s_ftgb196", - "xc7s25csga225" : "xc7s_csga225", - "xc7s25csga324" : "xc7s_csga324", - "xc7s50csga324" : "xc7s_csga324", - "xc7s75fgga676" : "xc7s_fgga676", "xcku040-ffva1156" : "xcku040_ffva1156", "xcku060-ffva1156" : "xcku060_ffva1156", "xcvu9p-flga2104" : "xcvu9p_flga2104", @@ -127,7 +133,7 @@ if tool in ["ise", "vivado"]: "xcku3p-ffva676" : "xcku3p_ffva676", "xcku5p-ffvb676" : "xcku5p_ffvb676", "xcau15p-ffvb676" : "xcau15p_ffvb676", - }[part] + }.get(part, pkg_name) if tool == "ise": cst_type = "UCF" tool_options = {'family': family, @@ -171,7 +177,10 @@ if tool in ["ise", "vivado"]: } else: cst_type = "xdc" - if family == "Xilinx UltraScale": + # Artix/Spartan 7 Specific use case: + if family in ["Artix", "Spartan 7"]: + tool_options = {'part': f"{part}{pkg}-1"} + elif family == "Xilinx UltraScale": if part in ["xcvu9p-flga2104", "xcku5p-ffvb676"]: tool_options = {'part': part + '-1-e'} parameters["secondaryflash"]= { @@ -194,6 +203,7 @@ if tool in ["ise", "vivado"]: tool_options = {'part': part + '-2-e'} else: tool_options = {'part': part + '-1'} + cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower() files.append({'name': currDir + 'xilinx_spiOverJtag.v', 'file_type': 'verilogSource'}) @@ -245,5 +255,18 @@ backend.build() if tool == "vivado": import shutil - shutil.copy("tmp_" + part + "/spiOverJtag.runs/impl_1/spiOverJtag.bit", - "tmp_" + part); + import subprocess + import gzip + + # Compress bitstream. + with open(f"tmp_{part}/spiOverJtag.bit", 'rb') as bit: + with gzip.open(f"spiOverJtag_{part}.bit.gz", 'wb', compresslevel=9) as bit_gz: + shutil.copyfileobj(bit, bit_gz) + + # Create Symbolic links for all supported packages. + if family in ["Artix", "Spartan 7"]: + in_file = f"spiOverJtag_{part}.bit.gz" + for pkg in packages[family][part]: + out_file = f"spiOverJtag_{part}{pkg}.bit.gz" + if not os.path.exists(out_file): + subprocess.run(["ln", "-s", in_file, out_file]) diff --git a/spiOverJtag/constr_xc7a_cpg236.xdc b/spiOverJtag/constr_xc7a_cpg236.xdc index 7b1edbf..2ae0665 100644 --- a/spiOverJtag/constr_xc7a_cpg236.xdc +++ b/spiOverJtag/constr_xc7a_cpg236.xdc @@ -2,9 +2,12 @@ set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS33} [get_ports {csn}]; set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}] +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}] diff --git a/spiOverJtag/constr_xc7a_cpg238.xdc b/spiOverJtag/constr_xc7a_cpg238.xdc index 9665243..0bd761e 100644 --- a/spiOverJtag/constr_xc7a_cpg238.xdc +++ b/spiOverJtag/constr_xc7a_cpg238.xdc @@ -9,3 +9,5 @@ set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}] +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}] diff --git a/spiOverJtag/constr_xc7a_csg324.xdc b/spiOverJtag/constr_xc7a_csg324.xdc index 955a208..d4a2e89 100644 --- a/spiOverJtag/constr_xc7a_csg324.xdc +++ b/spiOverJtag/constr_xc7a_csg324.xdc @@ -8,3 +8,6 @@ set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}] +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}] diff --git a/spiOverJtag/constr_xc7a_csg325.xdc b/spiOverJtag/constr_xc7a_csg325.xdc index 714880a..86ba53e 100644 --- a/spiOverJtag/constr_xc7a_csg325.xdc +++ b/spiOverJtag/constr_xc7a_csg325.xdc @@ -9,3 +9,5 @@ set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/constr_xc7a_csg325_1v35.xdc b/spiOverJtag/constr_xc7a_csg325_1v35.xdc index dcde0d4..4f6927c 100644 --- a/spiOverJtag/constr_xc7a_csg325_1v35.xdc +++ b/spiOverJtag/constr_xc7a_csg325_1v35.xdc @@ -1,23 +1,24 @@ -set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design] - -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property CFGBVS GND [current_design] - -set_property CONFIG_MODE SPIx4 [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] -set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] -set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] - -set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] -set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design] - -set_property -dict {PACKAGE_PIN L15 IOSTANDARD SSTL135_R} [get_ports csn] -set_property -dict {PACKAGE_PIN K16 IOSTANDARD SSTL135_R} [get_ports sdi_dq0] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD SSTL135_R} [get_ports sdo_dq1] -set_property -dict {PACKAGE_PIN J15 IOSTANDARD SSTL135_R} [get_ports wpn_dq2] -set_property -dict {PACKAGE_PIN J16 IOSTANDARD SSTL135_R} [get_ports hldn_dq3] - +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] +set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] +set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] + +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design] + +set_property -dict {PACKAGE_PIN L15 IOSTANDARD SSTL135_R} [get_ports csn] +set_property -dict {PACKAGE_PIN K16 IOSTANDARD SSTL135_R} [get_ports sdi_dq0] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD SSTL135_R} [get_ports sdo_dq1] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD SSTL135_R} [get_ports wpn_dq2] +set_property -dict {PACKAGE_PIN J16 IOSTANDARD SSTL135_R} [get_ports hldn_dq3] + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/constr_xc7a_fbg484.xdc b/spiOverJtag/constr_xc7a_fbg484.xdc index 96b9de8..cbeef1a 100644 --- a/spiOverJtag/constr_xc7a_fbg484.xdc +++ b/spiOverJtag/constr_xc7a_fbg484.xdc @@ -9,3 +9,5 @@ set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}] set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}] set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}] +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}] +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}] diff --git a/spiOverJtag/constr_xc7a_fbg676.xdc b/spiOverJtag/constr_xc7a_fbg676.xdc index fe12330..00375a5 100644 --- a/spiOverJtag/constr_xc7a_fbg676.xdc +++ b/spiOverJtag/constr_xc7a_fbg676.xdc @@ -8,3 +8,6 @@ set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {sdi_dq0}] set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVTTL} [get_ports {sdo_dq1}] set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {wpn_dq2}] set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVTTL} [get_ports {hldn_dq3}] + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}] +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}] diff --git a/spiOverJtag/constr_xc7a_fgg484.xdc b/spiOverJtag/constr_xc7a_fgg484.xdc index 5e2b0e6..cbeef1a 100644 --- a/spiOverJtag/constr_xc7a_fgg484.xdc +++ b/spiOverJtag/constr_xc7a_fgg484.xdc @@ -1,6 +1,7 @@ set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}] set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}] @@ -8,3 +9,5 @@ set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}] set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}] set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}] +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}] +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}] diff --git a/spiOverJtag/constr_xc7a_fgg676.xdc b/spiOverJtag/constr_xc7a_fgg676.xdc index aaf73d0..00375a5 100644 --- a/spiOverJtag/constr_xc7a_fgg676.xdc +++ b/spiOverJtag/constr_xc7a_fgg676.xdc @@ -3,9 +3,11 @@ set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {csn}] set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {sdi_dq0}] set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVTTL} [get_ports {sdo_dq1}] set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {wpn_dq2}] -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {hldn_dq3}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVTTL} [get_ports {hldn_dq3}] +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}] +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}] diff --git a/spiOverJtag/constr_xc7a_ftg256.xdc b/spiOverJtag/constr_xc7a_ftg256.xdc index a0dad16..32bec5a 100644 --- a/spiOverJtag/constr_xc7a_ftg256.xdc +++ b/spiOverJtag/constr_xc7a_ftg256.xdc @@ -8,3 +8,6 @@ set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK}] +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK}] diff --git a/spiOverJtag/constr_xc7a_sbg384.xdc b/spiOverJtag/constr_xc7a_sbg384.xdc index 61cb90c..6a0a825 100644 --- a/spiOverJtag/constr_xc7a_sbg384.xdc +++ b/spiOverJtag/constr_xc7a_sbg384.xdc @@ -6,4 +6,7 @@ set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {csn}] set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}] set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}] set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}] -set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}] \ No newline at end of file +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}] + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/constr_xc7a_sbg484.xdc b/spiOverJtag/constr_xc7a_sbg484.xdc new file mode 100644 index 0000000..e90d9bb --- /dev/null +++ b/spiOverJtag/constr_xc7a_sbg484.xdc @@ -0,0 +1,13 @@ +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVTTL} [get_ports {csn}] +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVTTL} [get_ports {sdi_dq0}] +set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVTTL} [get_ports {sdo_dq1}] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVTTL} [get_ports {wpn_dq2}] +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}] + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/constr_xc7s_cpga196.xdc b/spiOverJtag/constr_xc7s_cpga196.xdc new file mode 100644 index 0000000..12c103b --- /dev/null +++ b/spiOverJtag/constr_xc7s_cpga196.xdc @@ -0,0 +1,13 @@ +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + +set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS33} [get_ports {csn}]; +set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/constr_xc7s_csga225.xdc b/spiOverJtag/constr_xc7s_csga225.xdc index ae06441..1bc0b6c 100644 --- a/spiOverJtag/constr_xc7s_csga225.xdc +++ b/spiOverJtag/constr_xc7s_csga225.xdc @@ -8,3 +8,6 @@ set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; set_property -dict {PACKAGE_PIN J12 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/constr_xc7s_csga324.xdc b/spiOverJtag/constr_xc7s_csga324.xdc index 0861b63..e776557 100644 --- a/spiOverJtag/constr_xc7s_csga324.xdc +++ b/spiOverJtag/constr_xc7s_csga324.xdc @@ -8,3 +8,6 @@ set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/constr_xc7s_fgga484.xdc b/spiOverJtag/constr_xc7s_fgga484.xdc new file mode 100644 index 0000000..49b2853 --- /dev/null +++ b/spiOverJtag/constr_xc7s_fgga484.xdc @@ -0,0 +1,13 @@ +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {csn}]; +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; +set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/constr_xc7s_fgga676.xdc b/spiOverJtag/constr_xc7s_fgga676.xdc index 77a796c..993d716 100644 --- a/spiOverJtag/constr_xc7s_fgga676.xdc +++ b/spiOverJtag/constr_xc7s_fgga676.xdc @@ -8,3 +8,6 @@ set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/constr_xc7s_ftgb196.xdc b/spiOverJtag/constr_xc7s_ftgb196.xdc index 3eaa20a..a230f99 100644 --- a/spiOverJtag/constr_xc7s_ftgb196.xdc +++ b/spiOverJtag/constr_xc7s_ftgb196.xdc @@ -8,3 +8,6 @@ set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; + +create_clock -period 33.000 -name jtag_tck -waveform {0.000 16.500} [get_pins {bscane2_inst/DRCK]}} +create_clock -period 33.000 -name vers_tck -waveform {0.000 16.500} [get_pins {bscane2_version/DRCK]}} diff --git a/spiOverJtag/spiOverJtag_xc7a100t.bit.gz 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