diff --git a/README.md b/README.md
index 319ab5c..0585f6e 100644
--- a/README.md
+++ b/README.md
@@ -11,6 +11,8 @@ __Current supported kits:__
 * [Digilent Arty A7 xc7a35ti](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) (memory and spi flash)
 * [Digilent Arty S7 xc7s50](https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start) (memory and spi flash)
 * [Digilent Nexys Video xc7a200t](https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start) (memory and spi flash)
+* [Digilent Analog Discovery 2 xc6slx25](https://reference.digilentinc.com/test-and-measurement/analog-discovery-2/start) (memory)
+* [Digilent Digital Discovery xc6slx25](https://reference.digilentinc.com/test-and-measurement/digital-discovery/start) (memory)
 * [FairWaves XTRXPro](https://www.crowdsupply.com/fairwaves/xtrx) (memory and flash)
 * [Fireant Trion T8](https://www.crowdsupply.com/jungle-elec/fireant) (spi flash active mode)
 * [iCEBreaker](https://1bitsquared.com/collections/fpga/products/icebreaker)
@@ -50,7 +52,7 @@ __Supported (tested) FPGA:__
 * Lattice [ECP5 (25F, 5G 85F, CrossLink-NX (LIFCL-40)](https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX) (SRAM and Flash)
 * Xilinx Kintex 7 [xc7k325t](https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable) (SRAM)
 * Xilinx Artix 7 [xc7a35ti, xc7a50t, xc7a75t, xc7a100t, xc7a200t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory and spi flash)
-* Xilinx Spartan 6 [xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory)
+* Xilinx Spartan 6 [xc6slx25, xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory)
 * Xilinx Spartan 7 [xc7s15, xc7s25, xc7s50](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) (memory (all) and spi flash (xc7s50))
 * Intel Cyclone III [EP3C16](https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html) (memory)
 * Intel Cyclone IV CE [EP4CE22](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html) (memory. See note below)
diff --git a/src/cable.hpp b/src/cable.hpp
index 7e311b2..ff3aca4 100644
--- a/src/cable.hpp
+++ b/src/cable.hpp
@@ -32,6 +32,7 @@ static std::map <std::string, cable_t> cable_list = {
 	{"digilent_b",   {MODE_FTDI_SERIAL,  {0x0403, 0x6010, INTERFACE_B, 0xe8, 0xeb, 0x00, 0x60}}},
 	{"digilent_hs2", {MODE_FTDI_SERIAL,  {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}},
 	{"digilent_hs3", {MODE_FTDI_SERIAL,  {0x0403, 0x6014, INTERFACE_A, 0x88, 0x8B, 0x20, 0x30}}},
+	{"digilent_ad",  {MODE_FTDI_SERIAL,  {0x0403, 0x6014, INTERFACE_A, 0x08, 0x0B, 0x80, 0x80}}},
 	{"dirtyJtag",    {MODE_DIRTYJTAG,    {}}},
 	{"efinix_spi",   {MODE_FTDI_SERIAL,  {0x0403, 0x6011, INTERFACE_A, 0x08, 0x8B, 0x00, 0x00}}},
 	{"ft2232",       {MODE_FTDI_SERIAL,  {0x0403, 0x6010, INTERFACE_A, 0x08, 0x0B, 0x08, 0x0B}}},
diff --git a/src/ftdipp_mpsse.cpp b/src/ftdipp_mpsse.cpp
index 41a6db5..be95848 100644
--- a/src/ftdipp_mpsse.cpp
+++ b/src/ftdipp_mpsse.cpp
@@ -186,7 +186,7 @@ int FTDIpp_MPSSE::init(unsigned char latency, unsigned char bitmask_mode,
 		buf_cmd[1] = _cable.bit_low_val;  // 0xe8;
 		buf_cmd[2] = _cable.bit_low_dir;  // 0xeb;
 
-		if (_ftdi->type != TYPE_4232H && _ftdi->type != TYPE_232H) {
+		if (_ftdi->type != TYPE_4232H) {
 			buf_cmd[4] = _cable.bit_high_val;  // 0x00;
 			buf_cmd[5] = _cable.bit_high_dir;  // 0x60;
 			to_wr = 6;
diff --git a/src/part.hpp b/src/part.hpp
index 4721388..829c4ee 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -22,6 +22,7 @@ static std::map <int, fpga_model> fpga_list = {
 
 	{0x43651093, {"xilinx", "kintex7", "xc7k325t", 6}},
 
+	{0x24004093, {"xilinx", "spartan6", "xc6slx25", 6}},
 	{0x44008093, {"xilinx", "spartan6", "xc6slx45", 6}},
 	{0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}},
 	{0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}},