From 6aa3906e01815a4764265fc9ca1ce3a583ce145e Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 1 Feb 2020 18:12:09 +0100 Subject: [PATCH] README: add SeeedStudio Spartan Edge Accelerator Board --- README.md | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index c497404..aa73cd3 100644 --- a/README.md +++ b/README.md @@ -8,6 +8,7 @@ __Current support kits:__ * Lattice MachXO3LF Starter Kit LCMX03LF-6900C (memory and flash) * [Lattice ECP5 5G Evaluation Board (LFE5UM5G-85F-EVN)](https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard) * [Trenz Gowin LittleBee (TEC0117)](https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM) +* [SeeedStudio Spartan Edge Accelerator Board](http://wiki.seeedstudio.com/Spartan-Edge-Accelerator-Board) (memory) * [Sipeed Tang Nano](https://tangnano.sipeed.com/en/) (memory) __Supported (tested) FPGA:__ @@ -148,11 +149,14 @@ configured in SPI mode and sfl primitive used to access EPCQ SPI flash.** This interface is used for SPI communication only when the dedicated svf is loaded in RAM, rest of the time, user is free to use for what he want.** -### ARTY +### ARTY and Spartan Edge Accelerator Board To simplify further explanations, we consider the project is generated in the current directory. +**Note: Spartan Edge Accelerator Board has only pinheader, so the cable must be +provided** + #### loading in memory: *.bit* file is the default format generated by *vivado*, so nothing special @@ -162,8 +166,12 @@ __file load:__ ```bash openFPGALoader -b arty *.runs/impl_1/*.bit ``` +or +```bash +openFPGALoader -b spartanEdgeAccelBoard -c digilent_hs2 *.runs/impl_1/*.bit +``` -#### SPI flash: +#### SPI flash (only for ARTY): .mcs must be generates through vivado with a tcl script like ```tcl set project [lindex $argv 0]