diff --git a/99-openfpgaloader.rules b/99-openfpgaloader.rules
index eb918f5..be2fcbb 100644
--- a/99-openfpgaloader.rules
+++ b/99-openfpgaloader.rules
@@ -27,6 +27,8 @@ ATTRS{idVendor}=="0547", ATTRS{idProduct}=="1002", MODE="664", GROUP="plugdev",
 
 # altera usb-blaster
 ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6002", MODE="664", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6003", MODE="664", GROUP="plugdev", TAG+="uaccess"
 
 # altera usb-blasterII - uninitialized
 ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6810", MODE="664", GROUP="plugdev", TAG+="uaccess"
diff --git a/doc/boards.yml b/doc/boards.yml
index 895c066..9338fa3 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -222,6 +222,12 @@
   FPGA: Cyclone V SoC 5CSEMA4U23C6
   Memory: OK
 
+- ID: de10lite
+  Description: Terasic de10lite
+  URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1021&PartNo=1
+  FPGA: MAX 10 10M50DAF484C7G
+  Memory: OK
+
 - ID: de10nano
   Description: Terasic de10Nano
   URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=1046
diff --git a/src/board.hpp b/src/board.hpp
index 1f8c984..0dac7e1 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -137,6 +137,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("de0",             "", "usb-blaster",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de0nano",         "ep4ce2217", "usb-blaster",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de0nanoSoc",      "", "usb-blasterII",0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("de10lite",        "", "usb-blaster",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de10nano",        "", "usb-blasterII",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de1Soc",          "5CSEMA5", "usb-blasterII",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("deca",            "10M50DA", "usb-blasterII",0, 0, CABLE_DEFAULT),
diff --git a/src/part.hpp b/src/part.hpp
index a218a57..85b549d 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -96,7 +96,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x02d120dd, {"altera", "cyclone V Soc", "5CSEMA5", 10}},
 
 	{0x031820dd, {"altera", "MAX 10",    "10M08SAU169C8G", 10}},
-	{0x031050dd, {"altera", "MAX 10",    "10M50DAF484C6GES", 10}},
+	{0x031050dd, {"altera", "MAX 10",    "10M50DAF484", 10}},
 
 	{0x00000001, {"efinix", "Trion",    "T4/T8",            4}},
 	{0x00210a79, {"efinix", "Trion",    "T8QFP144/T13/T20", 4}},