From 61e9ddecbfb3c5a74ee98c69e7892061fc6174cb Mon Sep 17 00:00:00 2001
From: trabucayre <trabucayre@users.noreply.github.com>
Date: Wed, 13 May 2026 08:58:04 +0000
Subject: [PATCH] deploy: 22e782ac957934cdb492be65666669ba88ea7220

---
 .doctrees/compatibility/board.doctree | Bin 200327 -> 201497 bytes
 .doctrees/environment.pickle          | Bin 2587557 -> 2587557 bytes
 .doctrees/vendors/gowin.doctree       | Bin 13418 -> 14197 bytes
 _sources/vendors/gowin.rst.txt        |   5 +-
 compatibility/board.html              |  71 ++++++++++++++------------
 searchindex.js                        |   2 +-
 vendors/gowin.html                    |   5 +-
 7 files changed, 48 insertions(+), 35 deletions(-)

diff --git a/.doctrees/compatibility/board.doctree b/.doctrees/compatibility/board.doctree
index c993f83431b118da7775f0df88372700dbc785fc..24af398ac419ec8a6bbc36a7e5c9df0047effcb1 100644
GIT binary patch
delta 3849
zcmb7Hc~n*97U%n2Kn0u<U&ySaOfeP_)YAZg(i9YM%3cf+mn#Bt;eiSXsEEl+=z?1u
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zoM?0ku2FsxM$s5G=F&^=B8wKM!jg8q3s3q!72af(j5Io+!7OS?#tTx~3=9xdI91qC
zWg3HB)o>A~srEhi(UqBagN~?im_AKsj>=TLMy=`00S)%i>I~-an}Js-EED;<OcxtE
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C(u+I*

delta 3406
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diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle
index f7b67b346d923c7fead27178aaaab37bc917e0f6..6fec2b3f22893b4b40ee41a5c95421392aa58ce9 100644
GIT binary patch
delta 2758
zcmY+FdrZ_<7RR~6zz=!K@KUU;IJR1ORjVjurJxjXM_cWJ0YzXOe!`5y{Mebn=jw<L
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LaV}n+eI)%?kC*r<

delta 2839
zcmY+Ge^6A{700>D%0obu<%fcaKe8%T5UPnpoQ9w>id~Hwe+&o_p34IkmVIP*5h2wT
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diff --git a/.doctrees/vendors/gowin.doctree b/.doctrees/vendors/gowin.doctree
index d4fed7e57fadaecb4cab06c6d9925c943f22745e..36b57c09cf48a0919f4810b1903a593982b03575 100644
GIT binary patch
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diff --git a/_sources/vendors/gowin.rst.txt b/_sources/vendors/gowin.rst.txt
index 103c3e3..4258156 100644
--- a/_sources/vendors/gowin.rst.txt
+++ b/_sources/vendors/gowin.rst.txt
@@ -13,6 +13,7 @@ GOWIN GW1N
   * Sipeed Tang Nano 4K
   * Honeycomb
   * RUNBER
+  * BrisbaneSilicon BRS-100-GW1NR9
 
 ``.fs`` file is the default format generated by *Gowin IDE*, so nothing special must be done to generates this file.
 
@@ -37,12 +38,13 @@ where ``BOARD_NAME`` is:
 * ``tangnano20k``
 * ``tangprimer20k``
 * ``runber``
+* ``brs-100-gw1nr9``
 
 Flash
 -----
 
 .. ATTENTION::
-  Only with Trenz TEC0117 and runber.
+  Only with Trenz TEC0117, runber and brs-100-gw1nr9.
 
 with ``-f``, file load:
 
@@ -54,6 +56,7 @@ where ``BOARD_NAME`` is:
 
 * ``tec0117``
 * ``runber``
+* ``brs-100-gw1nr9``
 
 It's possible to flash external SPI Flash (connected to MSPI) in bscan mode by using ``--external-flash`` instead of
 ``-f``.
diff --git a/compatibility/board.html b/compatibility/board.html
index 98d52e7..f44aa2f 100644
--- a/compatibility/board.html
+++ b/compatibility/board.html
@@ -894,224 +894,231 @@ openFPGALoader<span class="w"> </span>-b<span class="w"> </span>arty<span class=
 <td><p>IF</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>trion_t20_bga256_jtag</p></td>
+<tr class="row-even"><td><p>brs-100-gw1nr9</p></td>
+<td><p><a class="reference external" href="https://brisbanesilicon.com.au/brs-100-gw1nr9/">BrisbaneSilicon BRS-100-GW1NR9</a></p></td>
+<td><p>littleBee GW1NR-9C</p></td>
+<td><p>OK</p></td>
+<td><p>IF/EF</p></td>
+<td></td>
+</tr>
+<tr class="row-odd"><td><p>trion_t20_bga256_jtag</p></td>
 <td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-triont20.html">Efinix Trion T20 BGA256 Dev Kit</a></p></td>
 <td><p>Trion T20BGA256</p></td>
 <td><p>OK</p></td>
 <td><p>NT</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>tec0330</p></td>
+<tr class="row-even"><td><p>tec0330</p></td>
 <td><p><a class="reference external" href="https://shop.trenz-electronic.de//TEC0330-05-PCIe-FMC-Carrier-with-Xilinx-Virtex-7-FPGA-8-Lane-PCIe-GEN2-SODIMM-SDRAM">PCIe FMC Carrier with Xilinx Virtex-7 FPGA (TEC0330)</a></p></td>
 <td><p>XC7VX330T-2FFG1157C</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>trion_t120_bga576</p></td>
+<tr class="row-odd"><td><p>trion_t120_bga576</p></td>
 <td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-triont120bga576.html">Efinix Trion T120 BGA576 Dev Kit (SPI mode)</a></p></td>
 <td><p>Trion T120BGA576</p></td>
 <td><p>NA</p></td>
 <td><p>AS</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>trion_t120_bga576_jtag</p></td>
+<tr class="row-even"><td><p>trion_t120_bga576_jtag</p></td>
 <td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-triont120bga576.html">Efinix Trion T120 BGA576 Dev Kit (JTAG mode)</a></p></td>
 <td><p>Trion T120BGA576</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>trion_ti60_f225</p></td>
+<tr class="row-odd"><td><p>trion_ti60_f225</p></td>
 <td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-titaniumti60f225.html">Efinix Titanium F225 Dev Kit (SPI mode)</a></p></td>
 <td><p>Titanium Ti60F225</p></td>
 <td><p>NA</p></td>
 <td><p>AS</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>trion_ti60_f225_jtag</p></td>
+<tr class="row-even"><td><p>trion_ti60_f225_jtag</p></td>
 <td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-titaniumti60f225.html">Efinix Titanium F225 Dev Kit (JTAG mode)</a></p></td>
 <td><p>Titanium Ti60F225</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>ulx3s</p></td>
+<tr class="row-odd"><td><p>ulx3s</p></td>
 <td><p><a class="reference external" href="https://radiona.org/ulx3s/">Radiona ULX3S</a></p></td>
 <td><p>ECP5 LFE5U</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td><p><a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-ulx3s-12f" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ULX3S-12F ➚</span></a> <a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-ulx3s-25f" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ULX3S-25F ➚</span></a> <a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-ulx3s-45f" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ULX3S-45F ➚</span></a> <a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-ulx3s-85f" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ULX3S-85F ➚</span></a></p></td>
 </tr>
-<tr class="row-odd"><td><p>ulx3s_dfu</p></td>
+<tr class="row-even"><td><p>ulx3s_dfu</p></td>
 <td><p><a class="reference external" href="https://github.com/emard/had2019-playground">Radiona ULX3S DFU mode</a></p></td>
 <td><p>ECP5 LFE5U</p></td>
 <td><p>NA</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>ulx4m_dfu</p></td>
+<tr class="row-odd"><td><p>ulx4m_dfu</p></td>
 <td><p><a class="reference external" href="https://github.com/intergalaktik/ulx4m-ls">Radiona ULX4M LD/LS DFU mode</a></p></td>
 <td><p>ECP5 LFE5U</p></td>
 <td><p>NA</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>vec_v6</p></td>
+<tr class="row-even"><td><p>vec_v6</p></td>
 <td><p><a class="reference external" href="https://vmm-srs.docs.cern.ch/">Xilinx VCU118</a></p></td>
 <td><p>xc6vlx130tff784</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>vc709</p></td>
+<tr class="row-odd"><td><p>vc709</p></td>
 <td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html">AMD Virtex-7 FPGA VC709 Connectivity Kit</a></p></td>
 <td><p>Virtex7 xc7vx690tffg1761</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>vcu108</p></td>
+<tr class="row-even"><td><p>vcu108</p></td>
 <td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/vcu108.html">Xilinx VCU108</a></p></td>
 <td><p>Virtex UltraScale xcvu095-ffva2104</p></td>
 <td><p>OK</p></td>
 <td><p>TBD</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>vcu118</p></td>
+<tr class="row-odd"><td><p>vcu118</p></td>
 <td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/vcu118.html">Xilinx VCU118</a></p></td>
 <td><p>Virtex UltraScale+ xcvu9p-flga2104</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>vcu128</p></td>
+<tr class="row-even"><td><p>vcu128</p></td>
 <td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/vcu128.html">Xilinx VCU128</a></p></td>
 <td><p>Virtex UltraScale+ xcvu37p-fsvh2892</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>vcu1525</p></td>
+<tr class="row-odd"><td><p>vcu1525</p></td>
 <td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/vcu1525-a.html">AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit</a></p></td>
 <td><p>Virtex UltraScale+ xcvu9p-fsgd2104</p></td>
 <td><p>OK</p></td>
 <td><p>NT</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>xtrx</p></td>
+<tr class="row-even"><td><p>xtrx</p></td>
 <td><p><a class="reference external" href="https://www.crowdsupply.com/fairwaves/xtrx">FairWaves XTRXPro</a></p></td>
 <td><p>Artix xc7a50tcpg236</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>xyloni_spi</p></td>
+<tr class="row-odd"><td><p>xyloni_spi</p></td>
 <td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-xyloni.html">Efinix Xyloni</a></p></td>
 <td><p>Trion T8F81</p></td>
 <td><p>NA</p></td>
 <td><p>AS</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>usrpx300</p></td>
+<tr class="row-even"><td><p>usrpx300</p></td>
 <td><p><a class="reference external" href="https://www.ettus.com/all-products/x300-kit/">Ettus Research USRP X300</a></p></td>
 <td><p>Kintex xc7k325tffg900</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>usrpx310</p></td>
+<tr class="row-odd"><td><p>usrpx310</p></td>
 <td><p><a class="reference external" href="https://www.ettus.com/all-products/x310-kit/">Ettus Research USRP X300</a></p></td>
 <td><p>Kintex xc7k410tffg900</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>xmf3</p></td>
+<tr class="row-even"><td><p>xmf3</p></td>
 <td><p><a class="reference external" href="https://pldkit.com/xilinx/xmf3">PLDkit XMF3</a></p></td>
 <td><p>Xilinx xc3s200ft256, xcf01s</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>ypcb003381p1</p></td>
+<tr class="row-odd"><td><p>ypcb003381p1</p></td>
 <td><p><a class="reference external" href="https://www.tiferking.cn/index.php/2024/12/19/650/">YPCB-00338-1P1 Kintex-7 Accelerator Card</a></p></td>
 <td><p>Kintex7 xc7k480tffg1156</p></td>
 <td><p>OK</p></td>
 <td><p>OK. BPI parallel NOR flash (MT28GU512AAA1EGC)</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>zc702</p></td>
+<tr class="row-even"><td><p>zc702</p></td>
 <td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html">Xilinx ZC702</a></p></td>
 <td><p>zynq7000 xc7z020clg484</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>zc706</p></td>
+<tr class="row-odd"><td><p>zc706</p></td>
 <td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html">Xilinx ZC706</a></p></td>
 <td><p>zynq7000 xc7z045ffg900</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td><p><a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-zc706" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ZC706 ➚</span></a></p></td>
 </tr>
-<tr class="row-odd"><td><p>zcu102</p></td>
+<tr class="row-even"><td><p>zcu102</p></td>
 <td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html">Xilinx ZCU102</a></p></td>
 <td><p>zynqMPSoC XCZU9EG</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>zcu106</p></td>
+<tr class="row-odd"><td><p>zcu106</p></td>
 <td><p><a class="reference external" href="https://www.xilinx.com/products/boards-and-kits/zcu106.html">Xilinx ZCU106</a></p></td>
 <td><p>zynqMPSoC XCZU7EV</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>zedboard</p></td>
+<tr class="row-even"><td><p>zedboard</p></td>
 <td><p><a class="reference external" href="https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/">Avnet ZedBoard</a></p></td>
 <td><p>zynq7000 xc7z020clg484</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td><p><a class="reference external" href="https://hdl.github.io/constraints/Data/Boards/index.html#boards-zedboard" title="(in FPGA Board Constraints latest)"><span class="xref std std-ref">ZedBoard ➚</span></a></p></td>
 </tr>
-<tr class="row-even"><td><p>zybo_z7_10</p></td>
+<tr class="row-odd"><td><p>zybo_z7_10</p></td>
 <td><p><a class="reference external" href="https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start">Digilent Zybo Z7-10</a></p></td>
 <td><p>zynq7000 xc7z010clg400</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>zybo_z7_20</p></td>
+<tr class="row-even"><td><p>zybo_z7_20</p></td>
 <td><p><a class="reference external" href="https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start">Digilent Zybo Z7-20</a></p></td>
 <td><p>zynq7000 xc7z020clg400</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>VMM3</p></td>
+<tr class="row-odd"><td><p>VMM3</p></td>
 <td><p><a class="reference external" href="https://vmm-srs.docs.cern.ch/">CERN board with VMM3</a></p></td>
 <td><p>xc7s50csga324?</p></td>
 <td><p>OK</p></td>
 <td><p>OK</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>efinix_jtag_ft2232</p></td>
+<tr class="row-even"><td><p>efinix_jtag_ft2232</p></td>
 <td><p><a class="reference external" href="https://www.efinixinc.com/products-devkits-titaniumti180j484.html">Efinix FT2232 development boards with JTAG on port 2 (Ti180J484 EVK, etc)</a></p></td>
 <td><p>Titanium Ti180J484 (and others)</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-even"><td><p>step-max10_v1</p></td>
+<tr class="row-odd"><td><p>step-max10_v1</p></td>
 <td><p><a class="reference external" href="https://wiki.stepfpga.com/step-max10">STEP MAX10 V1</a></p></td>
 <td><p>Altera 10M02SCM153C8G</p></td>
 <td><p>OK</p></td>
 <td><p>NA</p></td>
 <td></td>
 </tr>
-<tr class="row-odd"><td><p>step-mxo2_v2</p></td>
+<tr class="row-even"><td><p>step-mxo2_v2</p></td>
 <td><p><a class="reference external" href="https://wiki.stepfpga.com/xo2-4000hc">STEP MXO2 V2</a></p></td>
 <td><p>Lattice LCMXO2-4000HC-4MG132CC</p></td>
 <td><p>OK</p></td>
diff --git a/searchindex.js b/searchindex.js
index 9f63f81..a34e8d3 100644
--- a/searchindex.js
+++ b/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
diff --git a/vendors/gowin.html b/vendors/gowin.html
index 3b776ed..26c2273 100644
--- a/vendors/gowin.html
+++ b/vendors/gowin.html
@@ -45,6 +45,7 @@
 <li><p>Sipeed Tang Nano 4K</p></li>
 <li><p>Honeycomb</p></li>
 <li><p>RUNBER</p></li>
+<li><p>BrisbaneSilicon BRS-100-GW1NR9</p></li>
 </ul>
 </div>
 <p><code class="docutils literal notranslate"><span class="pre">.fs</span></code> file is the default format generated by <em>Gowin IDE</em>, so nothing special must be done to generates this file.</p>
@@ -65,13 +66,14 @@
 <li><p><code class="docutils literal notranslate"><span class="pre">tangnano20k</span></code></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">tangprimer20k</span></code></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">runber</span></code></p></li>
+<li><p><code class="docutils literal notranslate"><span class="pre">brs-100-gw1nr9</span></code></p></li>
 </ul>
 </section>
 <section id="flash">
 <h3>Flash<a class="headerlink" href="#flash" title="Link to this heading">¶</a></h3>
 <div class="admonition attention">
 <p class="admonition-title">Attention</p>
-<p>Only with Trenz TEC0117 and runber.</p>
+<p>Only with Trenz TEC0117, runber and brs-100-gw1nr9.</p>
 </div>
 <p>with <code class="docutils literal notranslate"><span class="pre">-f</span></code>, file load:</p>
 <div class="highlight-bash notranslate"><div class="highlight"><pre><span></span>openFPGALoader<span class="w"> </span>-f<span class="w"> </span>-b<span class="w"> </span>BOARD_NAME<span class="w"> </span>impl/pnr/*.fs
@@ -81,6 +83,7 @@
 <ul class="simple">
 <li><p><code class="docutils literal notranslate"><span class="pre">tec0117</span></code></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">runber</span></code></p></li>
+<li><p><code class="docutils literal notranslate"><span class="pre">brs-100-gw1nr9</span></code></p></li>
 </ul>
 <p>It’s possible to flash external SPI Flash (connected to MSPI) in bscan mode by using <code class="docutils literal notranslate"><span class="pre">--external-flash</span></code> instead of
 <code class="docutils literal notranslate"><span class="pre">-f</span></code>.</p>