From 5847ec2666b2e581bbab6104d4e79e1a8b2de625 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 15 Jan 2025 06:57:42 +0100 Subject: [PATCH] doc/boards.yml,src/board.hpp: fixed ac701 device code --- doc/boards.yml | 2 +- src/board.hpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/boards.yml b/doc/boards.yml index ab818df..e0bfc4a 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -1,7 +1,7 @@ - ID: ac701 Description: Xilinx Artix-7 FPGA AC701 Evaluation Kit URL: https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html - FPGA: Artix xc7a200t2fbg676c + FPGA: Artix xc7a200tfbg676 Memory: OK Flash: NT Constraints: AC701 diff --git a/src/board.hpp b/src/board.hpp index 6c5ba9e..3e2a65e 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -102,7 +102,7 @@ typedef struct { {_name, {"", _cable, _fpga_part, 0, 0, 0, COMM_DFU, {}, {}, 0, _vid, _pid, _alt}} static std::map board_list = { - JTAG_BOARD("ac701", "xc7a200t2fbg676c", "digilent", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("ac701", "xc7a200tfbg676", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("analogMax", "", "ft2232", 0, 0, CABLE_DEFAULT), JTAG_BOARD("litex-acorn-baseboard-mini", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT),