From 57e9860b43a640c769b7ea4cc7c563d377193029 Mon Sep 17 00:00:00 2001
From: umarcor <unai.martinezcorral@ehu.eus>
Date: Wed, 12 Jan 2022 01:52:55 +0100
Subject: [PATCH] doc: move 'board.inc' generation 'boards.py'

---
 doc/boards.py | 39 +++++++++++++++++++++++++++++++++++++++
 doc/conf.py   | 31 +++++++------------------------
 2 files changed, 46 insertions(+), 24 deletions(-)
 create mode 100644 doc/boards.py

diff --git a/doc/boards.py b/doc/boards.py
new file mode 100644
index 0000000..229bade
--- /dev/null
+++ b/doc/boards.py
@@ -0,0 +1,39 @@
+from pathlib import Path
+from dataclasses import dataclass
+from yaml import load as yaml_load, Loader as yaml_loader, dump as yaml_dump
+from tabulate import tabulate
+
+
+ROOT = Path(__file__).resolve().parent
+
+
+@dataclass
+class Board:
+    ID: str
+    Description: str = None
+    URL: str = None
+    FPGA: str = None
+    Memory: str = None
+    Flash: str = None
+
+
+def ReadDataFromYAML():
+    with (ROOT / 'boards.yml').open('r', encoding='utf-8') as fptr:
+        data = [Board(**item) for item in yaml_load(fptr, yaml_loader)]
+    return data
+
+
+def DataToTable(data, tablefmt: str = "rst"):
+    return tabulate(
+        [
+            [
+                item.ID,
+                f"`{item.Description} <{item.URL}>`__",
+                item.FPGA,
+                item.Memory,
+                item.Flash
+            ] for item in data
+        ],
+        headers=["Board name", "Description", "FPGA", "Memory", "Flash"],
+        tablefmt=tablefmt
+    )
diff --git a/doc/conf.py b/doc/conf.py
index ddb9cd8..a7612bd 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -5,10 +5,15 @@ from os.path import abspath
 from pathlib import Path
 from json import loads
 
+
 ROOT = Path(__file__).resolve().parent
 
 sys_path.insert(0, abspath("."))
 
+
+from boards import ReadDataFromYAML, DataToTable
+
+
 # -- General configuration ------------------------------------------------
 
 extensions = [
@@ -102,29 +107,7 @@ extlinks = {
     "ghsrc": ("https://github.com/trabucayre/openFPGALoader/blob/master/%s", None),
 }
 
-# -- Read board data from boards.yml
-
-from dataclasses import dataclass
-from yaml import load as yaml_load, Loader as yaml_loader, dump as yaml_dump
-from tabulate import tabulate
-
-@dataclass
-class Board:
-    ID: str
-    Description: str = None
-    URL: str = None
-    FPGA: str = None
-    Memory: str = None
-    Flash: str = None
-
-with (ROOT / 'boards.yml').open('r', encoding='utf-8') as fptr:
-    data = [Board(**item) for item in yaml_load(fptr, yaml_loader)]
-
-table = tabulate(
-    [[item.ID, f"`{item.Description} <{item.URL}>`__", item.FPGA, item.Memory, item.Flash] for item in data],
-    headers=["Board name", "Description", "FPGA", "Memory", "Flash"],
-    tablefmt="rst"
-)
+# -- Generate partial board compatibility page (`board.inc`) with data from `boards.yml`
 
 with (ROOT / "compatibility/boards.inc").open("w", encoding="utf-8") as wptr:
-    wptr.write(table)
+    wptr.write(DataToTable(ReadDataFromYAML()))