From 4c2a091ab1611d5a9a92cd1373162dd797b7094c Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 6 Oct 2021 08:46:00 +0200 Subject: [PATCH] xilinx: introduce coolrunner-II support --- CMakeLists.txt | 3 + INSTALL.md | 11 ++ doc/fpga-compatibility-list.md | 3 +- src/part.hpp | 1 + src/xilinx.cpp | 306 +++++++++++++++++++++++++++++++-- src/xilinx.hpp | 36 +++- 6 files changed, 347 insertions(+), 13 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index a1ee634..9f1f7ce 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -14,6 +14,7 @@ endif() option(ENABLE_CMSISDAP "enable cmsis DAP interface (requires hidapi)" ON) option(USE_PKGCONFIG "Use pkgconfig to find libraries" ON) option(LINK_CMAKE_THREADS "Use CMake find_package to link the threading library" OFF) +set(ISE_PATH "/opt/Xilinx/14.7" CACHE STRING "ise root directory (default: /opt/Xilinx/14.7)") ## specify the C++ standard set(CMAKE_CXX_STANDARD 11) @@ -29,6 +30,8 @@ include(GNUInstallDirs) # By default: DATA_DIR="/usr/local/share" add_definitions(-DDATA_DIR=\"${CMAKE_INSTALL_FULL_DATAROOTDIR}\") +add_definitions(-DISE_DIR=\"${ISE_PATH}\") + if(USE_PKGCONFIG) find_package(PkgConfig REQUIRED) pkg_check_modules(LIBFTDI REQUIRED libftdi1) diff --git a/INSTALL.md b/INSTALL.md index d0ac772..bd3fb00 100644 --- a/INSTALL.md +++ b/INSTALL.md @@ -95,3 +95,14 @@ brew install openfpgaloader ``` ## Windows + +## Common + +Bitstreams for **XC2C (coolrunner-II)** needs to be remapped using `.map` shipped with +**ISE**. **ISE** path is set at configure time using + +``` +-DISE_PATH=/somewhere/Xilinx/ISE_VERS/ +``` + +default: `/opt/Xilinx/14.7` diff --git a/doc/fpga-compatibility-list.md b/doc/fpga-compatibility-list.md index e7b0c81..aad5904 100644 --- a/doc/fpga-compatibility-list.md +++ b/doc/fpga-compatibility-list.md @@ -4,7 +4,7 @@ |--------:|:---------------------------------------------------------------------------------------------------------------------------------|:-------|:------| | Anlogic | [EG4S20](http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3) | OK | AS | | Efinix | [Trion T8](https://www.efinixinc.com/products-trion.html) | NA | OK | -| Gowin | [GW1N (GW1N-1, GW1N-4, GW1NR-9, GW1NS-2C, GW1NSR-4C)](https://www.gowinsemi.com/en/product/detail/2/) | OK | IF | +| Gowin | [GW1N (GW1N-1, GW1N-4, GW1NR-9, GW1NS-2C, GW1NSR-4C)](https://www.gowinsemi.com/en/product/detail/2/) | OK | IF | | Intel | Cyclone III [EP3C16](https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html) | OK | OK | | | Cyclone IV CE [EP4CE22](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html) | OK | OK | | | Cyclone V E [5CEA2, 5CEBA4](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html) | OK | OK | @@ -21,6 +21,7 @@ | | Spartan 6 [xc6slx9, xc6slx16, xc6slx25, xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) | OK | OK | | | Spartan 7 [xc7s15, xc7s25, xc7s50](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) | OK | OK | | | XC9500XL [xc9536xl, xc9572xl, xc95144xl, xc95188xl](https://www.xilinx.com/support/documentation/data_sheets/ds054.pdf) | NA | OK | +| | XC2C (coolrunner II) [xc2c32a](https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf) | TBD | OK | | | XCF [xcf01s, xcf02s, xcf04s](https://www.xilinx.com/products/silicon-devices/configuration-memory/platform-flash.html) | NA | OK | - *IF* Internal Flash diff --git a/src/part.hpp b/src/part.hpp index b318eb1..1769421 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -39,6 +39,7 @@ static std::map fpga_list = { {0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}}, {0x0362f093, {"xilinx", "spartan7", "xc7s50", 6}}, + {0x06e1c093, {"xilinx", "xc2c", "xc2c32a", 8}}, {0x09602093, {"xilinx", "xc9500xl", "xc9536xl", 8}}, {0x09604093, {"xilinx", "xc9500xl", "xc9572xl", 8}}, {0x09608093, {"xilinx", "xc9500xl", "xc95144xl", 8}}, diff --git a/src/xilinx.cpp b/src/xilinx.cpp index 1f9ebf3..f1832d6 100644 --- a/src/xilinx.cpp +++ b/src/xilinx.cpp @@ -9,6 +9,7 @@ #include #include #include +#include #include "jtag.hpp" #include "bitparser.hpp" @@ -20,6 +21,7 @@ #include "display.hpp" #include "xilinx.hpp" +#include "xilinxMapParser.hpp" #include "part.hpp" #include "progressBar.hpp" @@ -69,6 +71,8 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename, } } else if (family == "spartan6") { _fpga_family = SPARTAN6_FAMILY; + } else if (family == "xc2c") { + xc2c_init(idcode); } else if (family == "xc9500xl") { _fpga_family = XC95_FAMILY; switch (idcode) { @@ -166,7 +170,22 @@ void Xilinx::program(unsigned int offset) return; if (_mode == Device::FLASH_MODE && _file_extension == "jed") { - flow_program(); + JedParser *jed; + printInfo("Open file ", false); + + jed = new JedParser(_filename, _verbose); + if (jed->parse() == EXIT_FAILURE) { + printError("FAIL"); + return; + } + printSuccess("DONE"); + + if (_fpga_family == XC95_FAMILY) + flow_program(jed); + else if (_fpga_family == XC2C_FAMILY) + xc2c_flow_program(jed); + else + throw std::runtime_error("Error: jed only supported for xc95 and xc2c"); return; } @@ -486,19 +505,10 @@ bool Xilinx::flow_erase() return true; } -bool Xilinx::flow_program() +bool Xilinx::flow_program(JedParser *jed) { uint8_t wr_buf[16+2]; // largest section length uint8_t rd_buf[16+3]; - JedParser *jed; - printInfo("Open file ", false); - - jed = new JedParser(_filename, _verbose); - if (jed->parse() == EXIT_FAILURE) { - printError("FAIL"); - return false; - } - printSuccess("DONE"); /* enable ISC */ flow_enable(); @@ -858,6 +868,280 @@ std::string Xilinx::xcf_read() return buffer; } +/*--------------------------------------------------------*/ +/* xc2c */ +/*--------------------------------------------------------*/ +#define XC2C_IDCODE 0x01 +#define XC2C_ISC_DISABLE 0xc0 +#define XC2C_VERIFY 0xd1 +#define XC2C_ISC_ENABLE_OTF 0xe4 +#define XC2C_ISC_WRITE 0xe6 +#define XC2C_ISC_SRAM_READ 0xe7 +#define XC2C_ISC_ENABLE 0xe8 +#define XC2C_ISC_PROGRAM 0xea +#define XC2C_ISC_ERASE 0xed +#define XC2C_ISC_READ 0xee +#define XC2C_ISC_INIT 0xf0 +#define XC2C_USERCODE 0xfd + +/* xilinx programmer qualification specification 6.2 + * directly reversed + */ +static constexpr uint8_t _gray_code[256] = { + 0x00, 0x80, 0xc0, 0x40, 0x60, 0xe0, 0xa0, 0x20, + 0x30, 0xb0, 0xf0, 0x70, 0x50, 0xd0, 0x90, 0x10, + 0x18, 0x98, 0xd8, 0x58, 0x78, 0xf8, 0xb8, 0x38, + 0x28, 0xa8, 0xe8, 0x68, 0x48, 0xc8, 0x88, 0x08, + 0x0c, 0x8c, 0xcc, 0x4c, 0x6c, 0xec, 0xac, 0x2c, + 0x3c, 0xbc, 0xfc, 0x7c, 0x5c, 0xdc, 0x9c, 0x1c, + 0x14, 0x94, 0xd4, 0x54, 0x74, 0xf4, 0xb4, 0x34, + 0x24, 0xa4, 0xe4, 0x64, 0x44, 0xc4, 0x84, 0x04, + 0x06, 0x86, 0xc6, 0x46, 0x66, 0xe6, 0xa6, 0x26, + 0x36, 0xb6, 0xf6, 0x76, 0x56, 0xd6, 0x96, 0x16, + 0x1e, 0x9e, 0xde, 0x5e, 0x7e, 0xfe, 0xbe, 0x3e, + 0x2e, 0xae, 0xee, 0x6e, 0x4e, 0xce, 0x8e, 0x0e, + 0x0a, 0x8a, 0xca, 0x4a, 0x6a, 0xea, 0xaa, 0x2a, + 0x3a, 0xba, 0xfa, 0x7a, 0x5a, 0xda, 0x9a, 0x1a, + 0x12, 0x92, 0xd2, 0x52, 0x72, 0xf2, 0xb2, 0x32, + 0x22, 0xa2, 0xe2, 0x62, 0x42, 0xc2, 0x82, 0x02, + 0x03, 0x83, 0xc3, 0x43, 0x63, 0xe3, 0xa3, 0x23, + 0x33, 0xb3, 0xf3, 0x73, 0x53, 0xd3, 0x93, 0x13, + 0x1b, 0x9b, 0xdb, 0x5b, 0x7b, 0xfb, 0xbb, 0x3b, + 0x2b, 0xab, 0xeb, 0x6b, 0x4b, 0xcb, 0x8b, 0x0b, + 0x0f, 0x8f, 0xcf, 0x4f, 0x6f, 0xef, 0xaf, 0x2f, + 0x3f, 0xbf, 0xff, 0x7f, 0x5f, 0xdf, 0x9f, 0x1f, + 0x17, 0x97, 0xd7, 0x57, 0x77, 0xf7, 0xb7, 0x37, + 0x27, 0xa7, 0xe7, 0x67, 0x47, 0xc7, 0x87, 0x07, + 0x05, 0x85, 0xc5, 0x45, 0x65, 0xe5, 0xa5, 0x25, + 0x35, 0xb5, 0xf5, 0x75, 0x55, 0xd5, 0x95, 0x15, + 0x1d, 0x9d, 0xdd, 0x5d, 0x7d, 0xfd, 0xbd, 0x3d, + 0x2d, 0xad, 0xed, 0x6d, 0x4d, 0xcd, 0x8d, 0x0d, + 0x09, 0x89, 0xc9, 0x49, 0x69, 0xe9, 0xa9, 0x29, + 0x39, 0xb9, 0xf9, 0x79, 0x59, 0xd9, 0x99, 0x19, + 0x11, 0x91, 0xd1, 0x51, 0x71, 0xf1, 0xb1, 0x31, + 0x21, 0xa1, 0xe1, 0x61, 0x41, 0xc1, 0x81, 0x01, +}; + +void Xilinx::xc2c_init(uint32_t idcode) +{ + _fpga_family = XC2C_FAMILY; + std::string model = fpga_list[idcode].model; + int underscore_pos = model.find_first_of('_', 0); + snprintf(_cpld_base_name, underscore_pos, + "%s", model.substr(0, underscore_pos).c_str()); + switch ((idcode >> 16) & 0x3f) { + case 0x01: /* xc2c32 */ + case 0x11: /* xc2c32a PC44 */ + case 0x21: /* xc2c32a */ + _cpld_nb_col = 260; + _cpld_nb_row = 48; + _cpld_addr_size = 6; + break; + case 0x05: /* xc2c64 */ + case 0x25: /* xc2c64a */ + _cpld_nb_col = 274; + _cpld_nb_row = 96; + _cpld_addr_size = 7; + break; + case 0x18: /* xc2c128 */ + _cpld_nb_col = 752; + _cpld_nb_row = 80; + _cpld_addr_size = 7; + break; + case 0x14: /* xc2c256 */ + _cpld_nb_col = 1364; + _cpld_nb_row = 96; + _cpld_addr_size = 7; + break; + case 0x15: /* xc2c384 */ + _cpld_nb_col = 1868; + _cpld_nb_row = 120; + _cpld_addr_size = 7; + break; + case 0x17: /* xc2c512 */ + _cpld_nb_col = 1980; + _cpld_nb_row = 160; + _cpld_addr_size = 8; + break; + default: + throw std::runtime_error("Error: unknown XC2C version"); + } + _cpld_nb_row += 2; // 2 more row: done + sec and usercode + // datasheet table 2 p.15 +} + +/* reinit device + * datasheet table 47-48 p.61-62 + */ +void Xilinx::xc2c_flow_reinit() +{ + uint8_t c = 0; + _jtag->shiftIR(XC2C_ISC_ENABLE_OTF, 8); + _jtag->shiftIR(XC2C_ISC_INIT, 8); + _jtag->toggleClk((_jtag->getClkFreq() * 20) / 1000); + _jtag->shiftIR(XC2C_ISC_INIT, 8); + _jtag->shiftDR(&c, NULL, 8); + _jtag->toggleClk((_jtag->getClkFreq() * 800) / 1000); + _jtag->shiftIR(XC2C_ISC_DISABLE, 8); + _jtag->shiftIR(BYPASS, 8); +} + +/* full flash erase (with optional blank check) + * datasheet 12.1 (table41) p.56 + */ +bool Xilinx::xc2c_flow_erase() +{ + _jtag->shiftIR(XC2C_ISC_ENABLE_OTF, 8, Jtag::UPDATE_IR); + _jtag->shiftIR(XC2C_ISC_ERASE, 8); + _jtag->toggleClk((_jtag->getClkFreq() * 100) / 1000); + _jtag->shiftIR(XC2C_ISC_DISABLE, 8); + + if (_verify) { + std::string rx_buf = xc2c_flow_read(); + for (auto &val : rx_buf) { + if ((uint8_t)val != 0xff) { + printError("Erase: fails to verify blank check"); + return false; + } + } + } + + return true; +} + +/* read flash full content + * return it has string buffer + * table 45 - 46 p. 59-60 + */ +std::string Xilinx::xc2c_flow_read() +{ + uint8_t rx_buf[249]; + uint32_t delay_loop = (_jtag->getClkFreq() * 20) / 1000000; + uint16_t pos = 0; + uint8_t addr_shift = 8 - _cpld_addr_size; + + std::string buffer; + buffer.resize(((_cpld_nb_col * _cpld_nb_row) + 7) / 8); + + ProgressBar progress("Read Flash", _cpld_nb_row + 1, 50, _quiet); + + _jtag->shiftIR(BYPASS, 8); + _jtag->shiftIR(XC2C_ISC_ENABLE_OTF, 8); + _jtag->shiftIR(XC2C_ISC_READ, 8); + + /* send address + * send addr 0 before loop because each row content + * is followed by next addr (or dummy for the last row + */ + /* send address */ + uint8_t addr = _gray_code[0] >> addr_shift; + _jtag->shiftDR(&addr, NULL, _cpld_addr_size); + /* wait 20us */ + _jtag->toggleClk(delay_loop); + + for (size_t row = 1; row <= _cpld_nb_row; row++) { + /* read nb_col bits, stay in shift_dr to send next addr */ + _jtag->shiftDR(NULL, rx_buf, _cpld_nb_col, Jtag::SHIFT_DR); + /* send address */ + addr = _gray_code[row] >> addr_shift; + _jtag->shiftDR(&addr, NULL, _cpld_addr_size); + /* wait 20us */ + _jtag->toggleClk(delay_loop); + + for (int i = 0; i < _cpld_nb_col; i++, pos++) + if (rx_buf[i >> 3] & (1 << (i & 0x07))) + buffer[pos >> 3] |= (1 << (pos & 0x07)); + else + buffer[pos >> 3] &= ~(1 << (pos & 0x07)); + + progress.display(row); + } + progress.done(); + + _jtag->shiftIR(XC2C_ISC_DISABLE, Jtag::TEST_LOGIC_RESET); + + return buffer; +} + +bool Xilinx::xc2c_flow_program(JedParser *jed) +{ + uint8_t wr_buf[249]; // largest section length + uint32_t delay_loop = (_jtag->getClkFreq() * 20) / 1000; + uint8_t shift_addr = 8 - _cpld_addr_size; + + /* map jed fuse using device map */ + printInfo("Map jed fuses: ", false); + XilinxMapParser *map_parser; + try { + std::string mapname = ISE_DIR "/ISE_DS/ISE/xbr/data/" + + std::string(_cpld_base_name) + ".map"; + map_parser = new XilinxMapParser(mapname, _cpld_nb_row, _cpld_nb_col, + jed, 0xffffffff, _verbose); + map_parser->parse(); + } catch(std::exception &e) { + printError("FAIL"); + throw std::runtime_error(e.what()); + } + printSuccess("DONE"); + + std::vector listfuse = map_parser->cfg_data(); + + /* erase internal flash */ + printInfo("Erase Flash: ", false); + if (!xc2c_flow_erase()) { + printError("FAIL"); + throw std::runtime_error("Fail to erase interface flash"); + } else { + printSuccess("DONE"); + } + + ProgressBar progress("Write Flash", _cpld_nb_row, 50, _quiet); + + _jtag->shiftIR(XC2C_ISC_ENABLE_OTF, 8); + _jtag->shiftIR(XC2C_ISC_PROGRAM, 8); + + uint16_t iter = 0; + for (auto row : listfuse) { + uint16_t pos = 0; + uint8_t addr = _gray_code[iter] >> shift_addr; + for (auto col : row) { + if (col) + wr_buf[pos >> 3] |= (1 << (pos & 0x07)); + else + wr_buf[pos >> 3] &= ~(1 << (pos & 0x07)); + pos++; + } + _jtag->shiftDR(wr_buf, NULL, _cpld_nb_col, Jtag::SHIFT_DR); + _jtag->shiftDR(&addr, NULL, _cpld_addr_size); + _jtag->toggleClk(delay_loop); + + iter++; + } + + /* done bit and usercode are shipped into listfuse + * so only needs to send isc disable + */ + _jtag->shiftIR(XC2C_ISC_DISABLE, 8); + + if (_verify) { + std::string rx_buffer = xc2c_flow_read(); + iter = 0; + for (auto row : listfuse) { + for (auto col : row) { + if ((rx_buffer[iter >> 3] >> (iter & 0x07)) != col) { + throw std::runtime_error("Program: verify failed"); + } + iter++; + } + } + } + + /* reload */ + xc2c_flow_reinit(); + + return true; +} + /* */ /* SPI interface */ /* */ diff --git a/src/xilinx.hpp b/src/xilinx.hpp index 7a894a2..282319a 100644 --- a/src/xilinx.hpp +++ b/src/xilinx.hpp @@ -52,7 +52,7 @@ class Xilinx: public Device, SPIInterface { * program and disable ISC * \return false if something wrong */ - bool flow_program(); + bool flow_program(JedParser *jed); /*! * \brief fill a buffer with internal flash content @@ -69,6 +69,35 @@ class Xilinx: public Device, SPIInterface { bool xcf_program(ConfigBitstreamParser *bitfile); std::string xcf_read(); + /* -------------------- */ + /* XC2C (CoolRunner II) */ + /* -------------------- */ + /*! + * \brief configure instance using model name and idcode + * \param[in] idcode: targeted device idcode + */ + void xc2c_init(uint32_t idcode); + /*! + * \brief reset device, force read configuration + */ + void xc2c_flow_reinit(); + /*! + * \brief erase full internal flash (optionnally verify) + * \return false if erase fails, true otherwise + */ + bool xc2c_flow_erase(); + /*! + * \brief read full internal flash + * \return flash configuration data + */ + std::string xc2c_flow_read(); + /*! + * \brief write program to the flash (erase before, optional read after) + * \param[in] jed: bitstream instance + * \return false when erase or verify fails + */ + bool xc2c_flow_program(JedParser *jed); + /* spi interface */ int spi_put(uint8_t cmd, uint8_t *tx, uint8_t *rx, uint32_t len) override; @@ -80,6 +109,7 @@ class Xilinx: public Device, SPIInterface { /* list of xilinx family devices */ enum xilinx_family_t { XC95_FAMILY = 0, + XC2C_FAMILY, SPARTAN3_FAMILY, SPARTAN6_FAMILY, SPARTAN7_FAMILY, @@ -100,6 +130,10 @@ class Xilinx: public Device, SPIInterface { bool load_bridge(); std::string _device_package; int _xc95_line_len; /**< xc95 only: number of col by flash line */ + uint16_t _cpld_nb_row; /**< number of flash rows */ + uint16_t _cpld_nb_col; /**< number of cols in a row */ + uint16_t _cpld_addr_size; /**< number of addr bits */ + char _cpld_base_name[7]; /**< cpld name (without package size) */ }; #endif