diff --git a/doc/boards.yml b/doc/boards.yml index 054467a..8b6fbe3 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -710,4 +710,4 @@ URL: https://www.xilinx.com/products/boards-and-kits/vcu128.html FPGA: Virtex UltraScale+ xcvu37p-fsvh2892 Memory: OK - Flash: NA + Flash: OK diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index 04dc9b0..8f72773 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -8,7 +8,7 @@ XILINX_PARTS := xc3s500evq100 xc6slx9tqg144 xc6slx16ftg256 xc6slx16csg324 xc6slx xc7k160tffg676 \ xc7k325tffg676 xc7k325tffg900 \ xc7k420tffg901 \ - xcvu9p-flga2104 + xcvu9p-flga2104 xcvu37p-fsvh2892 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) ALTERA_PARTS := 10cl025256 10cl055484 ep4ce2217 ep4ce1523 ep4ce11523 5ce223 5ce423 5ce523 5ce927 diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index bfa49a6..f112e0e 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -91,6 +91,7 @@ if tool in ["ise", "vivado"]: "xc7s25csga324" : "xc7s_csga324", "xc7s50csga324" : "xc7s_csga324", "xcvu9p-flga2104" : "xcvu9p_flga2104", + "xcvu37p-fsvh2892" : "xcvu37p_fsvh2892", }[part] if tool == "ise": cst_type = "UCF" @@ -127,6 +128,14 @@ if tool in ["ise", "vivado"]: cst_type = "xdc" if family == "Virtex UltraScale": tool_options = {'part': part + '-1-e'} + if part == "xcvu9p-flga2104": + parameters["secondaryflash"]= { + 'datatype': 'int', + 'paramtype': 'vlogdefine', + 'description': 'secondary flash', + 'default': 1} + elif part == "xcvu37p-fsvh2892": + tool_options = {'part': part + '-2L-e'} else: tool_options = {'part': part + '-1'} cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower() diff --git a/spiOverJtag/constr_xcvu37p_fsvh2892.xdc b/spiOverJtag/constr_xcvu37p_fsvh2892.xdc new file mode 100644 index 0000000..90a0e84 --- /dev/null +++ b/spiOverJtag/constr_xcvu37p_fsvh2892.xdc @@ -0,0 +1,13 @@ +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +# Table 3-5 from UG1302 +set_property CFGBVS GND [current_design] + +# Primary QSPI flash +# Connection done through the STARTUPE3 block +# sdi_dq0 - PACKAGE_PIN AW15 - QSPI0_DQ0 Bank 0 - D00_MOSI_0 +# sdo_dq1 - PACKAGE_PIN AY15 - QSPI0_DQ1 Bank 0 - D01_DIN_0 +# wpn_dq2 - PACKAGE_PIN AY14 - QSPI0_DQ2 Bank 0 - D02_0 +# hldn_dq3 - PACKAGE_PIN AY13 - QSPI0_DQ3 Bank 0 - D03_0 +# csn - PACKAGE_PIN BC15 - QSPI0_CS_B Bank 0 - RDWR_FCS_B_0 +# sck - PACKAGE_PIN BD14 - QSPI_CCLK Bank 0 - CCLK_0 \ No newline at end of file diff --git a/spiOverJtag/spiOverJtag_xcvu37p-fsvh2892.bit.gz b/spiOverJtag/spiOverJtag_xcvu37p-fsvh2892.bit.gz new file mode 100644 index 0000000..b0a8560 Binary files /dev/null and b/spiOverJtag/spiOverJtag_xcvu37p-fsvh2892.bit.gz differ diff --git a/spiOverJtag/xilinx_spiOverJtag.v b/spiOverJtag/xilinx_spiOverJtag.v index fdf6552..b94ceea 100644 --- a/spiOverJtag/xilinx_spiOverJtag.v +++ b/spiOverJtag/xilinx_spiOverJtag.v @@ -13,13 +13,15 @@ module spiOverJtag input sdo_dq1, output wpn_dq2, output hldn_dq3 -`else // virtexultrascale +`endif // virtexultrascale + +`ifdef secondaryflash output sdi_sec_dq0, input sdo_sec_dq1, output wpn_sec_dq2, output hldn_sec_dq3, output csn_sec -`endif // virtexultrascale +`endif // secondaryflash ); wire capture, drck, sel, update; @@ -51,42 +53,20 @@ module spiOverJtag end end -`ifndef virtexultrascale `ifdef spartan6 assign sck = drck; -`else +`else // !spartan6 `ifdef spartan3e assign sck = drck; assign runtest = tmp_up_s; -`else - STARTUPE2 #( - .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams. - .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation. - ) startupe2_inst ( - .CFGCLK (), // 1-bit output: Configuration main clock output - .CFGMCLK (), // 1-bit output: Configuration internal oscillator clock output - .EOS (), // 1-bit output: Active high output signal indicating the End Of Startup. - .PREQ (), // 1-bit output: PROGRAM request to fabric output - .CLK (1'b0), // 1-bit input: User start-up clock input - .GSR (1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) - .GTS (1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name) - .KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) - .PACK (1'b1), // 1-bit input: PROGRAM acknowledge input - .USRCCLKO (drck), // 1-bit input: User CCLK input - .USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input - .USRDONEO (1'b1), // 1-bit input: User DONE pin output control - .USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output - ); -`endif -`endif -`else // virtexultrascale +`else // !spartan6 && !spartan3e +`ifdef virtexultrascale wire [3:0] di; assign sdo_dq1 = di[1]; wire [3:0] do = {hldn_dq3, wpn_dq2, 1'b0, sdi_dq0}; wire [3:0] dts = 4'b0010; // secondary BSCANE3 signals - wire drck_sec, tdo_sec; - reg fsm_csn_sec; + wire sel_sec, drck_sec; wire sck = (sel_sec) ? drck_sec : drck; @@ -112,6 +92,27 @@ module spiOverJtag .USRDONEO (1'b1), // 1-bit input: User DONE pin output control. .USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output. ); +`else // !spartan6 && !spartan3e && !virtexultrascale + STARTUPE2 #( + .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams. + .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation. + ) startupe2_inst ( + .CFGCLK (), // 1-bit output: Configuration main clock output + .CFGMCLK (), // 1-bit output: Configuration internal oscillator clock output + .EOS (), // 1-bit output: Active high output signal indicating the End Of Startup. + .PREQ (), // 1-bit output: PROGRAM request to fabric output + .CLK (1'b0), // 1-bit input: User start-up clock input + .GSR (1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) + .GTS (1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name) + .KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) + .PACK (1'b1), // 1-bit input: PROGRAM acknowledge input + .USRCCLKO (drck), // 1-bit input: User CCLK input + .USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input + .USRDONEO (1'b1), // 1-bit input: User DONE pin output control + .USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output + ); +`endif +`endif `endif `ifdef spartan3e @@ -161,7 +162,10 @@ module spiOverJtag ); `endif -`ifdef virtexultrascale +`ifdef secondaryflash + reg fsm_csn_sec; + wire tdo_sec; + assign wpn_sec_dq2 = 1'b1; assign hldn_sec_dq3 = 1'b1; assign sdi_sec_dq0 = tdi; @@ -207,6 +211,9 @@ module spiOverJtag .TDO (tdo_sec) // 1-bit input: Test Data Output (TDO) input // for USER function. ); -`endif +`else // secondaryflash + assign sel_sec = 1'b0; + assign drck_sec = 1'b0; +`endif // secondaryflash endmodule diff --git a/src/spiFlashdb.hpp b/src/spiFlashdb.hpp index 24e6746..48eb38c 100644 --- a/src/spiFlashdb.hpp +++ b/src/spiFlashdb.hpp @@ -153,7 +153,7 @@ static std::map flash_list = { }, {0x0020bb21, { .manufacturer = "micron", - .model = "MT25QU01", + .model = "MT25QU01G", .nr_sector = 2048, .sector_erase = true, .subsector_erase = true, @@ -164,6 +164,19 @@ static std::map flash_list = { .bp_len = 4, .bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 6)}} }, + {0x0020bb22, { + .manufacturer = "micron", + .model = "MT25QU02G", + .nr_sector = 4096, + .sector_erase = true, + .subsector_erase = true, + .has_extended = true, + .tb_otp = false, + .tb_offset = (1 << 5), + .tb_register = STATR, + .bp_len = 4, + .bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 6)}} + }, {0xbf258d, { .manufacturer = "microchip", .model = "SST25VF040B", diff --git a/src/xilinx.cpp b/src/xilinx.cpp index d7bab96..eaa6091 100644 --- a/src/xilinx.cpp +++ b/src/xilinx.cpp @@ -167,6 +167,9 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename, _secondary_file_extension = secondary_filename.substr( secondary_filename.find_last_of(".") + 1); _mode = Device::SPI_MODE; + if (_device_package != "xcvu9p-flga2104") { + throw std::runtime_error("Error: secondary flash unavailable"); + } } uint32_t idcode = _jtag->get_target_device_id();