diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml
index 3cf4671..0f97f9e 100644
--- a/doc/FPGAs.yml
+++ b/doc/FPGAs.yml
@@ -182,6 +182,7 @@ Xilinx:
 
   - Description: Artix 7
     Model:
+      - xc7a25t
       - xc7a35ti
       - xc7a50t
       - xc7a75t
diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile
index 050faaf..7093016 100644
--- a/spiOverJtag/Makefile
+++ b/spiOverJtag/Makefile
@@ -1,5 +1,6 @@
 XILINX_PARTS := xc3s500evq100 xc6slx9tqg144 xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
 	xc6slx150tfgg484 xc6slx150tcsg484 \
+	xc7a25tcpg238 xc7a25tcsg325 \
 	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
 	xc7a50tcsg324 xc7a50tcpg236 xc7a75tfgg484 \
 	xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\
diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py
index 214ac36..5c22cac 100755
--- a/spiOverJtag/build.py
+++ b/spiOverJtag/build.py
@@ -72,6 +72,8 @@ if tool in ["ise", "vivado"]:
         "xc6slx100fgg484"  : "xc6s_fgg484",
         "xc6slx150tcsg484" : "xc6s_csg484",
         "xc6slx150tfgg484" : "xc6s_fgg484",
+        "xc7a25tcpg238"    : "xc7a_cpg238",
+        "xc7a25tcsg325"    : "xc7a_csg325",
         "xc7a35tcpg236"    : "xc7a_cpg236",
         "xc7a35tcsg324"    : "xc7a_csg324",
         "xc7a35tftg256"    : "xc7a_ftg256",
diff --git a/spiOverJtag/constr_xc7a_cpg238.xdc b/spiOverJtag/constr_xc7a_cpg238.xdc
new file mode 100644
index 0000000..9665243
--- /dev/null
+++ b/spiOverJtag/constr_xc7a_cpg238.xdc
@@ -0,0 +1,11 @@
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports {csn}];
+set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
+set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
+set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
+set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
+
diff --git a/spiOverJtag/constr_xc7a_csg325.xdc b/spiOverJtag/constr_xc7a_csg325.xdc
new file mode 100644
index 0000000..714880a
--- /dev/null
+++ b/spiOverJtag/constr_xc7a_csg325.xdc
@@ -0,0 +1,11 @@
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {csn}];
+set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}];
+set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}];
+set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}];
+set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}];
+
diff --git a/spiOverJtag/spiOverJtag_xc7a25tcpg238.bit.gz b/spiOverJtag/spiOverJtag_xc7a25tcpg238.bit.gz
new file mode 100644
index 0000000..a77fb2a
Binary files /dev/null and b/spiOverJtag/spiOverJtag_xc7a25tcpg238.bit.gz differ
diff --git a/spiOverJtag/spiOverJtag_xc7a25tcsg325.bit.gz b/spiOverJtag/spiOverJtag_xc7a25tcsg325.bit.gz
new file mode 100644
index 0000000..47cd909
Binary files /dev/null and b/spiOverJtag/spiOverJtag_xc7a25tcsg325.bit.gz differ
diff --git a/spiOverJtag/xilinx_spiOverJtag.tcl b/spiOverJtag/xilinx_spiOverJtag.tcl
index ba50612..b30f614 100644
--- a/spiOverJtag/xilinx_spiOverJtag.tcl
+++ b/spiOverJtag/xilinx_spiOverJtag.tcl
@@ -7,6 +7,8 @@ file delete -force $build_path
 
 # Project creation
 set grade [dict create \
+	xc7a25tcpg238  -1 \
+	xc7a25tcsg325  -1 \
 	xc7a35tcpg236  -1 \
 	xc7a35tcsg324  -1 \
 	xc7a35tftg256  -1 \
@@ -21,6 +23,8 @@ set grade [dict create \
 	]
 
 set pkg_name [dict create \
+	xc7a25tcpg238  xc7a_cpg238 \
+	xc7a25tcsg325  xc7a_csg325 \
 	xc7a35tcpg236  xc7a_cpg236 \
 	xc7a35tcsg324  xc7a_csg324 \
 	xc7a35tftg256  xc7a_ftg256 \
diff --git a/src/part.hpp b/src/part.hpp
index 1c770b9..548e176 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -22,6 +22,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x0a014c35, {"anlogic", "eagle s20", "EG4S20BG256", 8}},
 	{0x00004c37, {"anlogic", "elf2", "EF2M45", 8}},
 
+	{0x037c2093, {"xilinx", "artix a7 25t", "xc7a25", 6}},
 	{0x0362D093, {"xilinx", "artix a7 35t", "xc7a35", 6}},
 	{0x0362c093, {"xilinx", "artix a7 50t",  "xc7a50t", 6}},
 	{0x03632093, {"xilinx", "artix a7 75t",  "xc7a75t", 6}},