From 354d3f86ab23a0a168864f0ccdfba4776025ab28 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 27 Feb 2024 15:44:14 +0100 Subject: [PATCH] Virtex6: Add spiOverJtag for Virtex6, detect xc6vlx130 and provide bitfile for xc6vlx130tff784 --- doc/FPGAs.yml | 7 ++++ spiOverJtag/Makefile | 1 + spiOverJtag/build.py | 7 ++++ spiOverJtag/constr_xc6v_ff784.ucf | 2 ++ .../spiOverJtag_xc6vlx130tff784.bit.gz | Bin 0 -> 9040 bytes spiOverJtag/xilinx_spiOverJtag.v | 32 +++++++++++++++++- src/part.hpp | 3 ++ 7 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 spiOverJtag/constr_xc6v_ff784.ucf create mode 100644 spiOverJtag/spiOverJtag_xc6vlx130tff784.bit.gz diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml index 30508aa..3a96de4 100644 --- a/doc/FPGAs.yml +++ b/doc/FPGAs.yml @@ -235,6 +235,13 @@ Xilinx: Memory: OK Flash: NA + - Description: Virtex 6 + Model: + - xc6vlx130t + URL: https://www.xilinx.com/products/silicon-devices/fpga/virtex-6.html + Memory: OK + Flash: OK + - Description: Virtex UltraScale+ Model: - xcvu9p diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index 1036668..8990ae4 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -2,6 +2,7 @@ XILINX_PARTS := xc3s500evq100 \ xc6slx9tqg144 xc6slx9csg324 \ xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \ xc6slx150tfgg484 xc6slx150tcsg484 \ + xc6vlx130tff784 \ xc7a15tcpg236 \ xc7a25tcpg238 xc7a25tcsg325 \ xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a35tfgg484 \ diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index 52810d6..0cfcadc 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -55,6 +55,10 @@ elif subpart == "xc3s": family = "Spartan3E" tool = "ise" speed = -4 +elif subpart == "xc6v": + family = "Virtex6" + tool = "ise" + speed = -1 elif subpart in ["xcvu", "xcku"]: family = "Xilinx UltraScale" tool = "vivado" @@ -73,6 +77,7 @@ if tool in ["ise", "vivado"]: "xc6slx100fgg484" : "xc6s_fgg484", "xc6slx150tcsg484" : "xc6s_csg484", "xc6slx150tfgg484" : "xc6s_fgg484", + "xc6vlx130tff784" : "xc6v_ff784", "xc7a15tcpg236" : "xc7a_cpg236", "xc7a25tcpg238" : "xc7a_cpg238", "xc7a25tcsg325" : "xc7a_csg325", @@ -116,6 +121,7 @@ if tool in ["ise", "vivado"]: "xc6slx100fgg484": "xc6slx100", "xc6slx150tcsg484": "xc6slx150t", "xc6slx150tfgg484": "xc6slx150t", + "xc6vlx130tff784": "xc6vlx130t", "xc7k325tffg676": "xc7k325t", "xc7k325tffg900": "xc7k325t", "xc7k420tffg901": "xc7k420t", @@ -130,6 +136,7 @@ if tool in ["ise", "vivado"]: "xc6slx100fgg484": "fgg484", "xc6slx150tcsg484": "csg484", "xc6slx150tfgg484": "fgg484", + "xc6vlx130tff784": "ff784", "xc7k325tffg676": "ffg676", "xc7k325tffg900": "ffg900", "xc7k420tffg901": "ffg901", diff --git a/spiOverJtag/constr_xc6v_ff784.ucf b/spiOverJtag/constr_xc6v_ff784.ucf new file mode 100644 index 0000000..872a41a --- /dev/null +++ b/spiOverJtag/constr_xc6v_ff784.ucf @@ -0,0 +1,2 @@ +NET "sdi_dq0" LOC = AF24 | IOSTANDARD = LVCMOS25; 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+`ifdef virtex6 + wire di; + wire tdo = (sel) ? di : tdi; +`else wire tdo = (sel) ? sdo_dq1 : tdi; +`endif assign csn = fsm_csn; wire tmp_cap_s = capture && sel; @@ -98,6 +106,26 @@ module spiOverJtag assign runtest = tmp_up_s; `elsif spartan6 assign sck = drck; +`elsif virtex6 + STARTUP_VIRTEX6 #( + .PROG_USR("FALSE") + ) startup_virtex6_inst ( + .CFGCLK(), // unused + .CFGMCLK(), // unused + .CLK(1'b0), // unused + .DINSPI(di), // data from SPI flash + .EOS(), + .GSR(1'b0), // unused + .GTS(1'b0), // unused + .KEYCLEARB(1'b0), // not used + .PACK(1'b1), // tied low for 'safe' operations + .PREQ(), // unused + .TCKSPI(), // echo of CCLK from TCK pin + .USRCCLKO (drck), // user FPGA -> CCLK pin + .USRCCLKTS(1'b0), // drive CCLK not in high-Z + .USRDONEO (1'b1), // why both USRDONE are high? + .USRDONETS(1'b1) // ?? + ); `else STARTUPE2 #( .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams. @@ -138,7 +166,9 @@ module spiOverJtag .TDO2 () // 1-bit input: USER2 function ); `else -`ifdef spartan6 +`ifdef virtex6 + BSCAN_VIRTEX6 #( +`elsif spartan6 BSCAN_SPARTAN6 #( `else BSCANE2 #( diff --git a/src/part.hpp b/src/part.hpp index cd4f2ab..188e88d 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -64,6 +64,9 @@ static std::map fpga_list = { {0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}}, {0x0362f093, {"xilinx", "spartan7", "xc7s50", 6}}, + /* Xilinx Virtex6 */ + {0x8424a093, {"xilinx", "virtex6", "xc6vlx130t", 10}}, + /* Xilinx 7-Series / Artix7 */ {0x037c2093, {"xilinx", "artix a7 25t", "xc7a25", 6}}, {0x0362D093, {"xilinx", "artix a7 35t", "xc7a35", 6}},