diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index a4f3a42..1014fdf 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -7,7 +7,8 @@ XILINX_PARTS := xc3s500evq100 xc6slx9tqg144 xc6slx16ftg256 xc6slx16csg324 xc6slx xc7s25csga225 xc7s25csga324 xc7s50csga324 \ xc7k160tffg676 \ xc7k325tffg676 xc7k325tffg900 \ - xc7k420tffg901 + xc7k420tffg901 \ + xcvu9p-flga2104 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) ALTERA_PARTS := 10cl025256 10cl055484 ep4ce2217 ep4ce1523 ep4ce11523 5ce223 5ce423 5ce523 5ce927 diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index 43a2e5b..dc13f32 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -55,6 +55,9 @@ elif subpart == "xc3s": family = "Spartan3E" tool = "ise" speed = -4 +elif subpart == "xcvu": + family = "Virtex UltraScale" + tool = "vivado" else: print("Error: unknown device") os.sys.exit() @@ -85,7 +88,8 @@ if tool in ["ise", "vivado"]: "xc7k420tffg901" : "xc7k_ffg901", "xc7s25csga225" : "xc7s_csga225", "xc7s25csga324" : "xc7s_csga324", - "xc7s50csga324" : "xc7s_csga324" + "xc7s50csga324" : "xc7s_csga324", + "xcvu9p-flga2104" : "xcvu9p_flga2104", }[part] if tool == "ise": cst_type = "UCF" @@ -118,7 +122,10 @@ if tool in ["ise", "vivado"]: } else: cst_type = "xdc" - tool_options = {'part': part+ '-1'} + if family == "Virtex UltraScale": + tool_options = {'part': part + '-1-e'} + else: + tool_options = {'part': part + '-1'} cst_file = currDir + "constr_" + pkg_name + "." + cst_type.lower() files.append({'name': currDir + 'xilinx_spiOverJtag.v', 'file_type': 'verilogSource'}) diff --git a/spiOverJtag/constr_xcvu9p_flga2104.xdc b/spiOverJtag/constr_xcvu9p_flga2104.xdc new file mode 100644 index 0000000..3a42a3e --- /dev/null +++ b/spiOverJtag/constr_xcvu9p_flga2104.xdc @@ -0,0 +1,25 @@ +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +# Table 1-2 from UG570 +set_property CFGBVS GND [current_design] + +# Primary QSPI flash +# Connection done through the STARTUPE3 block +# sdi_dq0 - PACKAGE_PIN AP11 - QSPI0_DQ0 Bank 0 - D00_MOSI_0 +# sdo_dq1 - PACKAGE_PIN AN11 - QSPI0_DQ1 Bank 0 - D01_DIN_0 +# wpn_dq2 - PACKAGE_PIN AM11 - QSPI0_DQ2 Bank 0 - D02_0 +# hldn_dq3 - PACKAGE_PIN AL11 - QSPI0_DQ3 Bank 0 - D03_0 +# csn - PACKAGE_PIN AJ11 - QSPI0_CS_B Bank 0 - RDWR_FCS_B_0 +# sck - PACKAGE_PIN AF13 - QSPI_CCLK Bank 0 - CCLK_0 + +# Secondary QSPI flash +set_property PACKAGE_PIN AM19 [get_ports "sdi_sec_dq0"]; +set_property IOSTANDARD LVCMOS18 [get_ports "sdi_sec_dq0"]; +set_property PACKAGE_PIN AM18 [get_ports "sdo_sec_dq1"]; +set_property IOSTANDARD LVCMOS18 [get_ports "sdo_sec_dq1"]; +set_property PACKAGE_PIN AN20 [get_ports "wpn_sec_dq2"]; +set_property IOSTANDARD LVCMOS18 [get_ports "wpn_sec_dq2"]; +set_property PACKAGE_PIN AP20 [get_ports "hldn_sec_dq3"]; +set_property IOSTANDARD LVCMOS18 [get_ports "hldn_sec_dq3"]; +set_property PACKAGE_PIN BF16 [get_ports "csn_sec"]; +set_property IOSTANDARD LVCMOS18 [get_ports "csn_sec"]; diff --git a/spiOverJtag/spiOverJtag_xcvu9p-flga2104.bit.gz b/spiOverJtag/spiOverJtag_xcvu9p-flga2104.bit.gz new file mode 100644 index 0000000..5fdec20 Binary files /dev/null and b/spiOverJtag/spiOverJtag_xcvu9p-flga2104.bit.gz differ diff --git a/spiOverJtag/xilinx_spiOverJtag.v b/spiOverJtag/xilinx_spiOverJtag.v index e982489..fdf6552 100644 --- a/spiOverJtag/xilinx_spiOverJtag.v +++ b/spiOverJtag/xilinx_spiOverJtag.v @@ -1,5 +1,6 @@ module spiOverJtag ( +`ifndef virtexultrascale output csn, `ifdef spartan6 @@ -12,6 +13,13 @@ module spiOverJtag input sdo_dq1, output wpn_dq2, output hldn_dq3 +`else // virtexultrascale + output sdi_sec_dq0, + input sdo_sec_dq1, + output wpn_sec_dq2, + output hldn_sec_dq3, + output csn_sec +`endif // virtexultrascale ); wire capture, drck, sel, update; @@ -43,6 +51,7 @@ module spiOverJtag end end +`ifndef virtexultrascale `ifdef spartan6 assign sck = drck; `else @@ -70,6 +79,40 @@ module spiOverJtag ); `endif `endif +`else // virtexultrascale + wire [3:0] di; + assign sdo_dq1 = di[1]; + wire [3:0] do = {hldn_dq3, wpn_dq2, 1'b0, sdi_dq0}; + wire [3:0] dts = 4'b0010; + // secondary BSCANE3 signals + wire drck_sec, tdo_sec; + reg fsm_csn_sec; + + wire sck = (sel_sec) ? drck_sec : drck; + + STARTUPE3 #( + .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams. + .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency (ns) for simulation. + ) startupe3_inst ( + .CFGCLK (), // 1-bit output: Configuration main clock output. + .CFGMCLK (), // 1-bit output: Configuration internal oscillator clock output. + .DI (di), // 4-bit output: Allow receiving on the D input pin. + .EOS (), // 1-bit output: Active-High output signal indicating the End Of Startup. + .PREQ (), // 1-bit output: PROGRAM request to fabric output. + .DO (do), // 4-bit input: Allows control of the D pin output. + .DTS (dts), // 4-bit input: Allows tristate of the D pin. + .FCSBO (csn), // 1-bit input: Controls the FCS_B pin for flash access. + .FCSBTS (1'b0), // 1-bit input: Tristate the FCS_B pin. + .GSR (1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port). + .GTS (1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name). + .KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM). + .PACK (1'b0), // 1-bit input: PROGRAM acknowledge input. + .USRCCLKO (sck), // 1-bit input: User CCLK input. + .USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input. + .USRDONEO (1'b1), // 1-bit input: User DONE pin output control. + .USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output. + ); +`endif `ifdef spartan3e BSCAN_SPARTAN3 bscane2_inst ( @@ -118,4 +161,52 @@ module spiOverJtag ); `endif +`ifdef virtexultrascale + assign wpn_sec_dq2 = 1'b1; + assign hldn_sec_dq3 = 1'b1; + assign sdi_sec_dq0 = tdi; + assign tdo_sec = (sel_sec) ? sdo_sec_dq1 : tdi; + assign csn_sec = fsm_csn_sec; + + wire tmp_cap_sec_s = capture && sel_sec; + wire tmp_up_sec_s = update && sel_sec; + + always @(posedge drck_sec, posedge runtest) begin + if (runtest) begin + fsm_csn_sec <= 1'b1; + end else begin + if (tmp_cap_sec_s) begin + fsm_csn_sec <= 1'b0; + end else if (tmp_up_sec_s) begin + fsm_csn_sec <= 1'b1; + end else begin + fsm_csn_sec <= fsm_csn_sec; + end + end + end + + BSCANE2 #( + .JTAG_CHAIN(2) // Value for USER command. + ) bscane2_sec_inst ( + .CAPTURE(), // 1-bit output: CAPTURE output from TAP controller. + .DRCK (drck_sec), // 1-bit output: Gated TCK output. When SEL + // is asserted, DRCK toggles when + // CAPTURE or SHIFT are asserted. + .RESET (), // 1-bit output: Reset output for TAP controller. + .RUNTEST(), // 1-bit output: Output asserted when TAP + // controller is in Run Test/Idle state. + .SEL (sel_sec), // 1-bit output: USER instruction active output. + .SHIFT (), // 1-bit output: SHIFT output from TAP controller. + .TCK (), // 1-bit output: Test Clock output. + // Fabric connection to TAP Clock pin. + .TDI (), // 1-bit output: Test Data Input (TDI) output + // from TAP controller. + .TMS (), // 1-bit output: Test Mode Select output. + // Fabric connection to TAP. + .UPDATE (), // 1-bit output: UPDATE output from TAP controller + .TDO (tdo_sec) // 1-bit input: Test Data Output (TDO) input + // for USER function. + ); +`endif + endmodule