From 3abc591bd58037f17f94d4109acf8294b3a78a87 Mon Sep 17 00:00:00 2001 From: GEORGIOS KARNAS Date: Sat, 5 Jun 2021 23:24:47 -0700 Subject: [PATCH 1/5] Add LCMXO2-1200HC --- src/part.hpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/part.hpp b/src/part.hpp index 5b0316e..4721388 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -43,6 +43,7 @@ static std::map fpga_list = { {0x310F1043, {"lattice", "CertusNX", "LFD2NX-40", 8}}, {0x012b9043, {"lattice", "MachXO2", "LCMXO2-640HC", 8}}, + {0x012ba043, {"lattice", "MachXO2", "LCMXO2-1200HC", 8}}, {0x012bd043, {"lattice", "MachXO2", "LCMXO2-7000HC", 8}}, {0x012b5043, {"lattice", "MachXO2", "LCMXO2-7000HE", 8}}, From 291f1b6d6feeea667b771123bb21c2532bebe77f Mon Sep 17 00:00:00 2001 From: ultraembedded Date: Thu, 10 Jun 2021 22:38:17 +0100 Subject: [PATCH 2/5] Add support for Digilent Digital Discovery and Analog Discovery 2 (openFPGALoader -c digilent_ad) --- README.md | 3 +++ src/cable.hpp | 1 + src/ftdipp_mpsse.cpp | 2 +- src/ftdipp_mpsse.hpp | 1 + src/part.hpp | 1 + 5 files changed, 7 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 319ab5c..5c3a429 100644 --- a/README.md +++ b/README.md @@ -11,6 +11,8 @@ __Current supported kits:__ * [Digilent Arty A7 xc7a35ti](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) (memory and spi flash) * [Digilent Arty S7 xc7s50](https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start) (memory and spi flash) * [Digilent Nexys Video xc7a200t](https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start) (memory and spi flash) +* [Digilent Analog Discovery 2 xc6slx25](https://reference.digilentinc.com/test-and-measurement/analog-discovery-2/start) (memory) +* [Digilent Digital Discovery xc6slx25](https://reference.digilentinc.com/test-and-measurement/digital-discovery/start) (memory) * [FairWaves XTRXPro](https://www.crowdsupply.com/fairwaves/xtrx) (memory and flash) * [Fireant Trion T8](https://www.crowdsupply.com/jungle-elec/fireant) (spi flash active mode) * [iCEBreaker](https://1bitsquared.com/collections/fpga/products/icebreaker) @@ -50,6 +52,7 @@ __Supported (tested) FPGA:__ * Lattice [ECP5 (25F, 5G 85F, CrossLink-NX (LIFCL-40)](https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX) (SRAM and Flash) * Xilinx Kintex 7 [xc7k325t](https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable) (SRAM) * Xilinx Artix 7 [xc7a35ti, xc7a50t, xc7a75t, xc7a100t, xc7a200t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory and spi flash) +* Xilinx Spartan 6 [xc6slx25](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory) * Xilinx Spartan 6 [xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory) * Xilinx Spartan 7 [xc7s15, xc7s25, xc7s50](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) (memory (all) and spi flash (xc7s50)) * Intel Cyclone III [EP3C16](https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html) (memory) diff --git a/src/cable.hpp b/src/cable.hpp index 7e311b2..09b5540 100644 --- a/src/cable.hpp +++ b/src/cable.hpp @@ -32,6 +32,7 @@ static std::map cable_list = { {"digilent_b", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0xe8, 0xeb, 0x00, 0x60}}}, {"digilent_hs2", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}}, {"digilent_hs3", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x88, 0x8B, 0x20, 0x30}}}, + {"digilent_ad", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x08, 0x0B, 0x80, 0x80, true}}}, {"dirtyJtag", {MODE_DIRTYJTAG, {}}}, {"efinix_spi", {MODE_FTDI_SERIAL, {0x0403, 0x6011, INTERFACE_A, 0x08, 0x8B, 0x00, 0x00}}}, {"ft2232", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0x08, 0x0B, 0x08, 0x0B}}}, diff --git a/src/ftdipp_mpsse.cpp b/src/ftdipp_mpsse.cpp index 41a6db5..c5bdb54 100644 --- a/src/ftdipp_mpsse.cpp +++ b/src/ftdipp_mpsse.cpp @@ -186,7 +186,7 @@ int FTDIpp_MPSSE::init(unsigned char latency, unsigned char bitmask_mode, buf_cmd[1] = _cable.bit_low_val; // 0xe8; buf_cmd[2] = _cable.bit_low_dir; // 0xeb; - if (_ftdi->type != TYPE_4232H && _ftdi->type != TYPE_232H) { + if (_cable.force_high_bits || (_ftdi->type != TYPE_4232H && _ftdi->type != TYPE_232H)) { buf_cmd[4] = _cable.bit_high_val; // 0x00; buf_cmd[5] = _cable.bit_high_dir; // 0x60; to_wr = 6; diff --git a/src/ftdipp_mpsse.hpp b/src/ftdipp_mpsse.hpp index 532dce4..e26bbd7 100644 --- a/src/ftdipp_mpsse.hpp +++ b/src/ftdipp_mpsse.hpp @@ -13,6 +13,7 @@ class FTDIpp_MPSSE { int bit_low_dir; int bit_high_val; int bit_high_dir; + int force_high_bits; } mpsse_bit_config; FTDIpp_MPSSE(const mpsse_bit_config &cable, const std::string &dev, diff --git a/src/part.hpp b/src/part.hpp index 4721388..829c4ee 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -22,6 +22,7 @@ static std::map fpga_list = { {0x43651093, {"xilinx", "kintex7", "xc7k325t", 6}}, + {0x24004093, {"xilinx", "spartan6", "xc6slx25", 6}}, {0x44008093, {"xilinx", "spartan6", "xc6slx45", 6}}, {0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}}, {0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}}, From dc003f6212ef7f6ffc1bf7af686f9a7d30cf96e1 Mon Sep 17 00:00:00 2001 From: ultraembedded Date: Fri, 11 Jun 2021 11:24:57 +0100 Subject: [PATCH 3/5] As per feedback, allow 232H devices to have upper bank pins configured on init. --- src/cable.hpp | 2 +- src/ftdipp_mpsse.cpp | 2 +- src/ftdipp_mpsse.hpp | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/cable.hpp b/src/cable.hpp index 09b5540..ff3aca4 100644 --- a/src/cable.hpp +++ b/src/cable.hpp @@ -32,7 +32,7 @@ static std::map cable_list = { {"digilent_b", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0xe8, 0xeb, 0x00, 0x60}}}, {"digilent_hs2", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}}, {"digilent_hs3", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x88, 0x8B, 0x20, 0x30}}}, - {"digilent_ad", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x08, 0x0B, 0x80, 0x80, true}}}, + {"digilent_ad", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x08, 0x0B, 0x80, 0x80}}}, {"dirtyJtag", {MODE_DIRTYJTAG, {}}}, {"efinix_spi", {MODE_FTDI_SERIAL, {0x0403, 0x6011, INTERFACE_A, 0x08, 0x8B, 0x00, 0x00}}}, {"ft2232", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0x08, 0x0B, 0x08, 0x0B}}}, diff --git a/src/ftdipp_mpsse.cpp b/src/ftdipp_mpsse.cpp index c5bdb54..be95848 100644 --- a/src/ftdipp_mpsse.cpp +++ b/src/ftdipp_mpsse.cpp @@ -186,7 +186,7 @@ int FTDIpp_MPSSE::init(unsigned char latency, unsigned char bitmask_mode, buf_cmd[1] = _cable.bit_low_val; // 0xe8; buf_cmd[2] = _cable.bit_low_dir; // 0xeb; - if (_cable.force_high_bits || (_ftdi->type != TYPE_4232H && _ftdi->type != TYPE_232H)) { + if (_ftdi->type != TYPE_4232H) { buf_cmd[4] = _cable.bit_high_val; // 0x00; buf_cmd[5] = _cable.bit_high_dir; // 0x60; to_wr = 6; diff --git a/src/ftdipp_mpsse.hpp b/src/ftdipp_mpsse.hpp index e26bbd7..532dce4 100644 --- a/src/ftdipp_mpsse.hpp +++ b/src/ftdipp_mpsse.hpp @@ -13,7 +13,6 @@ class FTDIpp_MPSSE { int bit_low_dir; int bit_high_val; int bit_high_dir; - int force_high_bits; } mpsse_bit_config; FTDIpp_MPSSE(const mpsse_bit_config &cable, const std::string &dev, From 0dd7355b36e3cb607f00d895aeb07fc3c7555ed1 Mon Sep 17 00:00:00 2001 From: ultraembedded Date: Fri, 11 Jun 2021 11:52:08 +0100 Subject: [PATCH 4/5] Recombine Spartan 6 supported parts list --- README.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/README.md b/README.md index 5c3a429..0585f6e 100644 --- a/README.md +++ b/README.md @@ -52,8 +52,7 @@ __Supported (tested) FPGA:__ * Lattice [ECP5 (25F, 5G 85F, CrossLink-NX (LIFCL-40)](https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX) (SRAM and Flash) * Xilinx Kintex 7 [xc7k325t](https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable) (SRAM) * Xilinx Artix 7 [xc7a35ti, xc7a50t, xc7a75t, xc7a100t, xc7a200t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory and spi flash) -* Xilinx Spartan 6 [xc6slx25](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory) -* Xilinx Spartan 6 [xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory) +* Xilinx Spartan 6 [xc6slx25, xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory) * Xilinx Spartan 7 [xc7s15, xc7s25, xc7s50](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) (memory (all) and spi flash (xc7s50)) * Intel Cyclone III [EP3C16](https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html) (memory) * Intel Cyclone IV CE [EP4CE22](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html) (memory. See note below) From b5f2506fd101532703ee8532658334c36a55c07d Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 12 Jun 2021 08:40:40 +0200 Subject: [PATCH 5/5] clkHZ: be more generic --- src/anlogicCable.cpp | 2 ++ src/ftdiJtagBitbang.cpp | 2 +- src/ftdiJtagMPSSE.hpp | 2 ++ src/ftdipp_mpsse.cpp | 2 ++ src/ftdipp_mpsse.hpp | 1 + src/jtagInterface.hpp | 4 +++- 6 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/anlogicCable.cpp b/src/anlogicCable.cpp index 032e603..e9843f3 100644 --- a/src/anlogicCable.cpp +++ b/src/anlogicCable.cpp @@ -145,6 +145,8 @@ int AnlogicCable::setClkFreq(uint32_t clkHZ) printWarn("Jtag frequency : requested " + std::to_string(req_freq) + "Hz -> real " + std::to_string(clkHZ) + "Hz"); + _clkHZ = clkHZ; + return clkHZ; } diff --git a/src/ftdiJtagBitbang.cpp b/src/ftdiJtagBitbang.cpp index fd937d6..e15cdb2 100644 --- a/src/ftdiJtagBitbang.cpp +++ b/src/ftdiJtagBitbang.cpp @@ -76,7 +76,7 @@ FtdiJtagBitBang::FtdiJtagBitBang(const FTDIpp_MPSSE::mpsse_bit_config &cable, throw std::runtime_error("_buffer realloc failed\n"); _buffer = ptr; - setClkFreq(_clkHZ); + setClkFreq(clkHZ); init(1, _tck_pin | _tms_pin | _tdi_pin, BITMODE_BITBANG); setBitmode(BITMODE_BITBANG); diff --git a/src/ftdiJtagMPSSE.hpp b/src/ftdiJtagMPSSE.hpp index 5b3282d..1e25599 100644 --- a/src/ftdiJtagMPSSE.hpp +++ b/src/ftdiJtagMPSSE.hpp @@ -42,6 +42,8 @@ class FtdiJtagMPSSE : public JtagInterface, private FTDIpp_MPSSE { return FTDIpp_MPSSE::setClkFreq(clkHZ); } + uint32_t getClkFreq() override {return FTDIpp_MPSSE::getClkFreq();} + /* TMS */ int writeTMS(uint8_t *tms, int len, bool flush_buffer) override; /* clock */ diff --git a/src/ftdipp_mpsse.cpp b/src/ftdipp_mpsse.cpp index be95848..847b60e 100644 --- a/src/ftdipp_mpsse.cpp +++ b/src/ftdipp_mpsse.cpp @@ -294,6 +294,8 @@ int FTDIpp_MPSSE::setClkFreq(uint32_t clkHZ) ftdi_tcioflush(_ftdi); #endif + _clkHZ = real_freq; + return real_freq; } diff --git a/src/ftdipp_mpsse.hpp b/src/ftdipp_mpsse.hpp index 532dce4..f8aabce 100644 --- a/src/ftdipp_mpsse.hpp +++ b/src/ftdipp_mpsse.hpp @@ -22,6 +22,7 @@ class FTDIpp_MPSSE { int init(unsigned char latency, unsigned char bitmask_mode, unsigned char mode); int setClkFreq(uint32_t clkHZ); + uint32_t getClkFreq() { return _clkHZ;} int vid() {return _vid;} int pid() {return _pid;} diff --git a/src/jtagInterface.hpp b/src/jtagInterface.hpp index 4278daa..1006250 100644 --- a/src/jtagInterface.hpp +++ b/src/jtagInterface.hpp @@ -33,7 +33,7 @@ class JtagInterface { virtual ~JtagInterface() {} virtual int setClkFreq(uint32_t clkHZ) = 0; - virtual uint32_t getClkFreq() { return 0;} + virtual uint32_t getClkFreq() {return _clkHZ;} /*! * \brief flush TMS internal buffer (ie. transmit to converter) @@ -80,5 +80,7 @@ class JtagInterface { * \return 1 if success, 0 if nothing to write, -1 is something wrong */ virtual int flush() = 0; + protected: + uint32_t _clkHZ; /*!< current clk frequency */ }; #endif // _JTAGINTERFACE_H_