From ed390f468ade8954999bc9a78c5c31d2cd57b908 Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Wed, 26 Jan 2022 16:14:00 +0100 Subject: [PATCH 1/6] Adding dev kit Xilinx Zynq-7000 SoC ZC702 Evaluation Kit --- doc/boards.yml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/doc/boards.yml b/doc/boards.yml index 66575c5..5ba7067 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -268,6 +268,13 @@ Flash: NT Constraints: KC705 +- ID: zc702 + Description: Xilinx ZC702 + URL: https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html + FPGA: zynq7000 xc7z020clg484 + Memory: OK + Flash: NA + - ID: licheeTang Description: Sipeed Lichee Tang URL: https://tang.sipeed.com/en/hardware-overview/lichee-tang/ From 0d1905425c8f842b4d3812b8810e516b80301385 Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Wed, 26 Jan 2022 16:21:52 +0100 Subject: [PATCH 2/6] add board zc702 in board.hpp --- src/board.hpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/board.hpp b/src/board.hpp index 967e876..3a32d2d 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -116,6 +116,7 @@ static std::map board_list = { JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT), JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("zc702", "xc7z020-clg484", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("colorlight", "", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("colorlight-i5", "", "cmsisdap", 0, 0, CABLE_DEFAULT), JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT), From 99df2829057f139c8357a707a59ddadea5b7b6db Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Wed, 26 Jan 2022 16:27:16 +0100 Subject: [PATCH 3/6] alphabetical order --- doc/boards.yml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/doc/boards.yml b/doc/boards.yml index 5ba7067..35c939b 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -268,13 +268,6 @@ Flash: NT Constraints: KC705 -- ID: zc702 - Description: Xilinx ZC702 - URL: https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html - FPGA: zynq7000 xc7z020clg484 - Memory: OK - Flash: NA - - ID: licheeTang Description: Sipeed Lichee Tang URL: https://tang.sipeed.com/en/hardware-overview/lichee-tang/ @@ -441,6 +434,13 @@ Memory: OK Flash: OK +- ID: zc702 + Description: Xilinx ZC702 + URL: https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html + FPGA: zynq7000 xc7z020clg484 + Memory: OK + Flash: NA + - ID: zedboard Description: Avnet ZedBoard URL: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/ From f30cca46d84c772e11a60a3c3bcad386cfc1b783 Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Wed, 26 Jan 2022 16:29:35 +0100 Subject: [PATCH 4/6] no dash for zedboard fpga name --- src/board.hpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/board.hpp b/src/board.hpp index 3a32d2d..350cd42 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -116,7 +116,7 @@ static std::map board_list = { JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT), JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT), - JTAG_BOARD("zc702", "xc7z020-clg484", "digilent", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("zc702", "xc7z020clg484", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("colorlight", "", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("colorlight-i5", "", "cmsisdap", 0, 0, CABLE_DEFAULT), JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT), @@ -177,7 +177,7 @@ static std::map board_list = { SPI_BOARD("titanium_ti60_f225","efinix", "efinix_spi_ft4232", DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT), JTAG_BOARD("titanium_ti60_f225_jtag", "","efinix_jtag_ft4232", 0, 0, CABLE_DEFAULT), - JTAG_BOARD("zedboard", "xc7z020-clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("zedboard", "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT), }; #endif From db407a426364a0dcad71ba2f867ea48e4d85c50e Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Wed, 26 Jan 2022 16:42:03 +0100 Subject: [PATCH 5/6] adding xilinx AC701 development kit --- doc/boards.yml | 7 +++++++ src/board.hpp | 1 + 2 files changed, 8 insertions(+) diff --git a/doc/boards.yml b/doc/boards.yml index 35c939b..ecf3116 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -1,3 +1,10 @@ +- ID: ac701 + Description: Xilinx Artix-7 FPGA AC701 Evaluation Kit + URL: https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html + FPGA: Artix xc7a200t2fbg676c + Memory: OK + Flash: NT + - ID: acornCle215 Description: Acorn CLE 215+ URL: http://squirrelsresearch.com/acorn-cle-215 diff --git a/src/board.hpp b/src/board.hpp index 350cd42..3fd8bff 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -102,6 +102,7 @@ typedef struct { {_name, {"", _cable, _fpga_part, 0, 0, 0, COMM_DFU, {}, {}, 0, _vid, _pid, _alt}} static std::map board_list = { + JTAG_BOARD("ac701", "xc7a200t2fbg676c", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT), JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT), /* left for backward compatibility, use right name instead */ From dc5eedfdde28f29d8564184f5889fa8d1108542e Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Thu, 27 Jan 2022 09:32:59 +0100 Subject: [PATCH 6/6] adding constraints AC701 --- doc/boards.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/boards.yml b/doc/boards.yml index ecf3116..43c70c6 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -4,6 +4,7 @@ FPGA: Artix xc7a200t2fbg676c Memory: OK Flash: NT + Constraints: AC701 - ID: acornCle215 Description: Acorn CLE 215+