diff --git a/doc/boards.yml b/doc/boards.yml
index 522b608..9ed4fc6 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -234,6 +234,12 @@
   FPGA: Cyclone V SoC 5CSEMA5F31C6
   Memory: OK
 
+- ID: deca
+  Description: Arrow/Terasic DECA
+  URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=&No=944&PartNo=1
+  FPGA: MAX 10 10M50DAF484C6GES
+  Memory: OK
+
 - ID: ecp5_evn
   Description: Lattice ECP5 5G Evaluation Board
   URL: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard
diff --git a/src/board.hpp b/src/board.hpp
index 52a178b..f892808 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -139,6 +139,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("de0nanoSoc",      "", "usb-blasterII",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de10nano",        "", "usb-blasterII",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de1Soc",          "5CSEMA5", "usb-blasterII",0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("deca",            "10M50DA", "usb-blasterII",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("ecp5_evn",        "", "ft2232",     0, 0, CABLE_DEFAULT),
 	SPI_BOARD("fireant",              "efinix", "ft232",
 			DBUS4, DBUS5, 0, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
diff --git a/src/part.hpp b/src/part.hpp
index a4131b6..a218a57 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -96,6 +96,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x02d120dd, {"altera", "cyclone V Soc", "5CSEMA5", 10}},
 
 	{0x031820dd, {"altera", "MAX 10",    "10M08SAU169C8G", 10}},
+	{0x031050dd, {"altera", "MAX 10",    "10M50DAF484C6GES", 10}},
 
 	{0x00000001, {"efinix", "Trion",    "T4/T8",            4}},
 	{0x00210a79, {"efinix", "Trion",    "T8QFP144/T13/T20", 4}},