diff --git a/README.md b/README.md index d667cb8..a1c6f66 100644 --- a/README.md +++ b/README.md @@ -7,6 +7,7 @@ __Current support kits:__ * [Colorlight 5A-75B (version 7)](https://fr.aliexpress.com/item/32281130824.html) (memory and spi flash) * [Digilent Arty A7 xc7a35ti](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) (memory and spi flash) * [Digilent Arty S7 xc7s50](https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start) (memory and spi flash) +* [Digilent Nexys Video xc7a200t](https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start) (memory and spi flash) * [Lattice MachXO2 Breakout Board Evaluation Kit (LCMXO2-7000HE)](https://www.latticesemi.com/products/developmentboardsandkits/machxo2breakoutboard) (memory and flash) * Lattice MachXO3LF Starter Kit LCMX03LF-6900C (memory and flash) * [Lattice MachXO3D Development Board (LCMXO3D-9400HC)](https://www.latticesemi.com/products/developmentboardsandkits/machxo3d_development_board) @@ -29,7 +30,7 @@ __Supported (tested) FPGA:__ * Lattice [MachXO3D](http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3D.aspx) (SRAM and Flash) * Lattice [ECP5 (25F, 5G 85F](http://www.latticesemi.com/Products/FPGAandCPLD/ECP5) (SRAM and Flash) * Lattice [ECP5 (25F, 5G 85F, CrossLink-NX (LIFCL-40)](https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX) (SRAM and Flash) -* Xilinx Artix 7 [xc7a35ti, xc7a100t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory (all) and spi flash (xc7a35ti) +* Xilinx Artix 7 [xc7a35ti, xc7a100t, xc7a200t](https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) (memory and spi flash) * Xilinx Spartan 6 [xc6slx45](https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html) (memory) * Xilinx Spartan 7 [xc7s15, xc7s50](https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html) (memory (all) and spi flash (xc7s50)) * Intel Cyclone IV CE [EP4CE22](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html) (memory. See note below) diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index 9c02cad..d874a86 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -1,5 +1,5 @@ VIVADO := vivado -nolog -nojournal -mode batch -source -MODELS := xc7a35 xc7a100 xc7s50 +MODELS := xc7a35 xc7a100 xc7s50 xc7a200 BIT_FILES := $(addsuffix .bit,$(addprefix spiOverJtag_, $(MODELS))) all: $(BIT_FILES) diff --git a/spiOverJtag/constr_xc7a200.xdc b/spiOverJtag/constr_xc7a200.xdc new file mode 100644 index 0000000..61cb90c --- /dev/null +++ b/spiOverJtag/constr_xc7a200.xdc @@ -0,0 +1,9 @@ +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] + +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports {csn}] +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}] +set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}] +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}] \ No newline at end of file diff --git a/spiOverJtag/spiOverJtag_xc7a200.bit b/spiOverJtag/spiOverJtag_xc7a200.bit new file mode 100644 index 0000000..015f5d8 Binary files /dev/null and b/spiOverJtag/spiOverJtag_xc7a200.bit differ diff --git a/spiOverJtag/xilinx_spiOverJtag.tcl b/spiOverJtag/xilinx_spiOverJtag.tcl index 33a9bf9..dd41230 100644 --- a/spiOverJtag/xilinx_spiOverJtag.tcl +++ b/spiOverJtag/xilinx_spiOverJtag.tcl @@ -6,7 +6,12 @@ set build_path tmp_${model} file delete -force $build_path # Project creation -set parts [dict create xc7a35 xc7a35ticsg324-1L xc7a100 xc7a100tfgg484-2 xc7s50 xc7s50csga324-1] +set parts [dict create \ + xc7a35 xc7a35ticsg324-1L \ + xc7s50 xc7s50csga324-1 \ + xc7a100 xc7a100tfgg484-2 \ + xc7a200 xc7a200tsbg484-1 \ + ] create_project $project_name $build_path -part [dict get $parts $model] add_files -norecurse xilinx_spiOverJtag.vhd diff --git a/src/board.hpp b/src/board.hpp index 17dc47a..e576d02 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -38,6 +38,7 @@ typedef struct { static std::map board_list = { {"arty", {"digilent", {}}}, + {"nexysVideo", {"digilent_b", {}}}, {"colorlight", {"", {}}}, {"crosslinknx_evn", {"ft2232", {}}}, {"cyc1000", {"ft2232", {}}}, diff --git a/src/cable.hpp b/src/cable.hpp index 0d9d1d9..709076b 100644 --- a/src/cable.hpp +++ b/src/cable.hpp @@ -29,6 +29,7 @@ static std::map cable_list = { {"bus_blaster", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0x08, 0x1B, 0x08, 0x0B}}}, {"bus_blaster_b",{MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0x08, 0x0B, 0x08, 0x0B}}}, {"digilent", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}}, + {"digilent_b", {MODE_FTDI_SERIAL, {0x0403, 0x6010, INTERFACE_B, 0xe8, 0xeb, 0x00, 0x60}}}, {"digilent_hs2", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0xe8, 0xeb, 0x00, 0x60}}}, {"digilent_hs3", {MODE_FTDI_SERIAL, {0x0403, 0x6014, INTERFACE_A, 0x88, 0x8B, 0x20, 0x30}}}, {"dirtyJtag", {MODE_DIRTYJTAG, {}}}, diff --git a/src/part.hpp b/src/part.hpp index dda6e20..e86bd5b 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -15,6 +15,7 @@ static std::map fpga_list = { {0x0362D093, {"xilinx", "artix a7 35t", "xc7a35"}}, {0x13631093, {"xilinx", "artix a7 100t", "xc7a100"}}, + {0x13636093, {"xilinx", "artix a7 200t", "xc7a200"}}, {0x44008093, {"xilinx", "spartan6", "xc6slx45"}}, {0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1"}},